The LLVM Target-Independent Code Generator¶
Warning
This is a work in progress.
Introduction¶
The LLVM target-independent code generator is a framework that provides a suite of reusable components for translating the LLVM internal representation to the machine code for a specified target—either in assembly form (suitable for a static compiler) or in binary machine code format (usable for a JIT compiler). The LLVM target-independent code generator consists of six main components:
Abstract target description interfaces which capture important properties about various aspects of the machine, independently of how they will be used. These interfaces are defined in
include/llvm/Target/.Classes used to represent the code being generated for a target. These classes are intended to be abstract enough to represent the machine code for any target machine. These classes are defined in
include/llvm/CodeGen/. At this level, concepts like “constant pool entries” and “jump tables” are explicitly exposed.Classes and algorithms used to represent code at the object file level, the MC Layer. These classes represent assembly level constructs like labels, sections, and instructions. At this level, concepts like “constant pool entries” and “jump tables” don’t exist.
Target-independent algorithms used to implement various phases of native code generation (register allocation, scheduling, stack frame representation, etc). This code lives in
lib/CodeGen/.Implementations of the abstract target description interfaces for particular targets. These machine descriptions make use of the components provided by LLVM, and can optionally provide custom target-specific passes, to build complete code generators for a specific target. Target descriptions live in
lib/Target/.The target-independent JIT components. The LLVM JIT is completely target independent (it uses the
TargetJITInfostructure to interface for target-specific issues. The code for the target-independent JIT lives inlib/ExecutionEngine/JIT.
Depending on which part of the code generator you are interested in working on, different pieces of this will be useful to you. In any case, you should be familiar with the target description and machine code representation classes. If you want to add a backend for a new target, you will need to implement the target description classes for your new target and understand the LLVM code representation. If you are interested in implementing a new code generation algorithm, it should only depend on the target-description and machine code representation classes, ensuring that it is portable.
Required components in the code generator¶
The two pieces of the LLVM code generator are the high-level interface to the code generator and the set of reusable components that can be used to build target-specific backends. The two most important interfaces ( TargetMachine and DataLayout ) are the only ones that are required to be defined for a backend to fit into the LLVM system, but the others must be defined if the reusable code generator components are going to be used.
This design has two important implications. The first is that LLVM can support completely non-traditional code generation targets. For example, the C backend does not require register allocation, instruction selection, or any of the other standard components provided by the system. As such, it only implements these two interfaces, and does its own thing. Note that C backend was removed from the trunk since LLVM 3.1 release. Another example of a code generator like this is a (purely hypothetical) backend that converts LLVM to the GCC RTL form and uses GCC to emit machine code for a target.
This design also implies that it is possible to design and implement radically different code generators in the LLVM system that do not make use of any of the built-in components. Doing so is not recommended at all, but could be required for radically different targets that do not fit into the LLVM machine description model: FPGAs for example.
The high-level design of the code generator¶
The LLVM target-independent code generator is designed to support efficient and quality code generation for standard register-based microprocessors. Code generation in this model is divided into the following stages:
Instruction Selection — This phase determines an efficient way to express the input LLVM code in the target instruction set. This stage produces the initial code for the program in the target instruction set, then makes use of virtual registers in SSA form and physical registers that represent any required register assignments due to target constraints or calling conventions. This step turns the LLVM code into a DAG of target instructions.
Scheduling and Formation — This phase takes the DAG of target instructions produced by the instruction selection phase, determines an ordering of the instructions, then emits the instructions as MachineInstrs with that ordering. Note that we describe this in the instruction selection section because it operates on a SelectionDAG.
SSA-based Machine Code Optimizations — This optional stage consists of a series of machine-code optimizations that operate on the SSA-form produced by the instruction selector. Optimizations like modulo-scheduling or peephole optimization work here.
Register Allocation — The target code is transformed from an infinite virtual register file in SSA form to the concrete register file used by the target. This phase introduces spill code and eliminates all virtual register references from the program.
Prolog/Epilog Code Insertion — Once the machine code has been generated for the function and the amount of stack space required is known (used for LLVM alloca’s and spill slots), the prolog and epilog code for the function can be inserted and “abstract stack location references” can be eliminated. This stage is responsible for implementing optimizations like frame-pointer elimination and stack packing.
Late Machine Code Optimizations — Optimizations that operate on “final” machine code can go here, such as spill code scheduling and peephole optimizations.
Code Emission — The final stage actually puts out the code for the current function, either in the target assembler format or in machine code.
The code generator is based on the assumption that the instruction selector will use an optimal pattern matching selector to create high-quality sequences of native instructions. Alternative code generator designs based on pattern expansion and aggressive iterative peephole optimization are much slower. This design permits efficient compilation (important for JIT environments) and aggressive optimization (used when generating code offline) by allowing components of varying levels of sophistication to be used for any step of compilation.
In addition to these stages, target implementations can insert arbitrary target-specific passes into the flow. For example, the X86 target uses a special pass to handle the 80x87 floating point stack architecture. Other targets with unusual requirements can be supported with custom passes as needed.
Using TableGen for target description¶
The target description classes require a detailed description of the target
architecture. These target descriptions often have a large amount of common
information (e.g., an add instruction is almost identical to a sub
instruction). In order to allow the maximum amount of commonality to be
factored out, the LLVM code generator uses the
TableGen Overview tool to describe big chunks of the
target machine, which allows the use of domain-specific and target-specific
abstractions to reduce the amount of repetition.
As LLVM continues to be developed and refined, we plan to move more and more of
the target description to the .td form. Doing so gives us a number of
advantages. The most important is that it makes it easier to port LLVM because
it reduces the amount of C++ code that has to be written, and the surface area
of the code generator that needs to be understood before someone can get
something working. Second, it makes it easier to change things. In particular,
if tables and other things are all emitted by tblgen, we only need a change
in one place (tblgen) to update all of the targets to a new interface.
Target description classes¶
The LLVM target description classes (located in the include/llvm/Target
directory) provide an abstract description of the target machine independent of
any particular client. These classes are designed to capture the abstract
properties of the target (such as the instructions and registers it has), and do
not incorporate any particular pieces of code generation algorithms.
All of the target description classes (except the DataLayout class) are designed to be subclassed by the concrete target implementation, and have virtual methods implemented. To get to these implementations, the TargetMachine class provides accessors that should be implemented by the target.
The TargetMachine class¶
The TargetMachine class provides virtual methods that are used to access the
target-specific implementations of the various target description classes via
the get*Info methods (getInstrInfo, getRegisterInfo,
getFrameInfo, etc.). This class is designed to be specialized by a concrete
target implementation (e.g., X86TargetMachine) which implements the various
virtual methods. The only required target description class is the
DataLayout class, but if the code
generator components are to be used, the other interfaces should be implemented
as well.
The DataLayout class¶
The DataLayout class is the only required target description class, and it
is the only class that is not extensible (you cannot derive a new class from
it). DataLayout specifies information about how the target lays out memory
for structures, the alignment requirements for various data types, the size of
pointers in the target, and whether the target is little-endian or
big-endian.
The TargetLowering class¶
The TargetLowering class is used by SelectionDAG based instruction selectors
primarily to describe how LLVM code should be lowered to SelectionDAG
operations. Among other things, this class indicates:
an initial register class to use for various
ValueTypes,which operations are natively supported by the target machine,
the return type of
setccoperations,the type to use for shift amounts, and
various high-level characteristics, like whether it is profitable to turn division by a constant into a multiplication sequence.
The TargetRegisterInfo class¶
The TargetRegisterInfo class is used to describe the register file of the
target and any interactions between the registers.
Registers are represented in the code generator by unsigned integers. Physical
registers (those that actually exist in the target description) are unique
small numbers, and virtual registers are generally large. Note that
register #0 is reserved as a flag value.
Each register in the processor description has an associated
TargetRegisterDesc entry, which provides a textual name for the register
(used for assembly output and debugging dumps) and a set of aliases (used to
indicate whether one register overlaps with another).
In addition to the per-register description, the TargetRegisterInfo class
exposes a set of processor specific register classes (instances of the
TargetRegisterClass class). Each register class contains sets of registers
that have the same properties (for example, they are all 32-bit integer
registers). Each SSA virtual register created by the instruction selector has
an associated register class. When the register allocator runs, it replaces
virtual registers with a physical register in the set.
The target-specific implementations of these classes is auto-generated from a TableGen Overview description of the register file.
The TargetInstrInfo class¶
The TargetInstrInfo class is used to describe the machine instructions
supported by the target. Descriptions define things like the mnemonic for
the opcode, the number of operands, the list of implicit register uses and defs,
whether the instruction has certain target-independent properties (accesses
memory, is commutable, etc), and holds any target-specific flags.
The TargetFrameLowering class¶
The TargetFrameLowering class is used to provide information about the stack
frame layout of the target. It holds the direction of stack growth, the known
stack alignment on entry to each function, and the offset to the local area.
The offset to the local area is the offset from the stack pointer on function
entry to the first location where function data (local variables, spill
locations) can be stored.
The TargetSubtarget class¶
The TargetSubtarget class is used to provide information about the specific
chip set being targeted. A sub-target informs code generation of which
instructions are supported, instruction latencies and instruction execution
itinerary; i.e., which processing units are used, in what order, and for how
long.
The TargetJITInfo class¶
The TargetJITInfo class exposes an abstract interface used by the
Just-In-Time code generator to perform target-specific activities, such as
emitting stubs. If a TargetMachine supports JIT code generation, it should
provide one of these objects through the getJITInfo method.
Machine code description classes¶
At the high-level, LLVM code is translated to a machine specific representation
formed out of MachineFunction ,
MachineBasicBlock , and
MachineInstr instances (defined in
include/llvm/CodeGen). This representation is completely target agnostic,
representing instructions in their most abstract form: an opcode and a series of
operands. This representation is designed to support both an SSA representation
for machine code, as well as a register allocated, non-SSA form.
The MachineInstr class¶
Target machine instructions are represented as instances of the MachineInstr
class. This class is an extremely abstract way of representing machine
instructions. In particular, it only keeps track of an opcode number and a set
of operands.
The opcode number is a simple unsigned integer that only has meaning to a
specific backend. All of the instructions for a target should be defined in the
*InstrInfo.td file for the target. The opcode enum values are auto-generated
from this description. The MachineInstr class does not have any information
about how to interpret the instruction (i.e., what the semantics of the
instruction are); for that you must refer to the
TargetInstrInfo class.
The operands of a machine instruction can be of several different types: a register reference, a constant integer, a basic block reference, etc. In addition, a machine operand should be marked as a def or a use of the value (though only registers are allowed to be defs).
By convention, the LLVM code generator orders instruction operands so that all
register definitions come before the register uses, even on architectures that
are normally printed in other orders. For example, the SPARC add instruction:
“add %i1, %i2, %i3” adds the “%i1”, and “%i2” registers and stores the
result into the “%i3” register. In the LLVM code generator, the operands should
be stored as “%i3, %i1, %i2”: with the destination first.
Keeping destination (definition) operands at the beginning of the operand list has several advantages. In particular, the debugging printer will print the instruction like this:
%r3 = add %i1, %i2
Also if the first operand is a def, it is easier to create instructions whose only def is the first operand.
Using the MachineInstrBuilder.h functions¶
Machine instructions are created by using the BuildMI functions, located in
the include/llvm/CodeGen/MachineInstrBuilder.h file. The BuildMI
functions make it easy to build arbitrary machine instructions. Usage of the
BuildMI functions look like this:
// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
// instruction and insert it at the end of the given MachineBasicBlock.
const TargetInstrInfo &TII = ...
MachineBasicBlock &MBB = ...
DebugLoc DL;
MachineInstr *MI = BuildMI(MBB, DL, TII.get(X86::MOV32ri), DestReg).addImm(42);
// Create the same instr, but insert it before a specified iterator point.
MachineBasicBlock::iterator MBBI = ...
BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), DestReg).addImm(42);
// Create a 'cmp Reg, 0' instruction, no destination reg.
MI = BuildMI(MBB, DL, TII.get(X86::CMP32ri8)).addReg(Reg).addImm(42);
// Create an 'sahf' instruction which takes no operands and stores nothing.
MI = BuildMI(MBB, DL, TII.get(X86::SAHF));
// Create a self looping branch instruction.
BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(&MBB);
If you need to add a definition operand (other than the optional destination register), you must explicitly mark it as such:
MI.addReg(Reg, RegState::Define);
Fixed (preassigned) registers¶
One important issue that the code generator needs to be aware of is the presence
of fixed registers. In particular, there are often places in the instruction
stream where the register allocator must arrange for a particular value to be
in a particular register. This can occur due to limitations of the instruction
set (e.g., the X86 can only do a 32-bit divide with the EAX/EDX
registers), or external factors like calling conventions. In any case, the
instruction selector should emit code that copies a virtual register into or out
of a physical register when needed.
For example, consider this simple LLVM example:
define i32 @test(i32 %X, i32 %Y) {
%Z = sdiv i32 %X, %Y
ret i32 %Z
}
The X86 instruction selector might produce this machine code for the div and
ret:
;; Start of div
%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
%reg1027 = sar %reg1024, 31
%EDX = mov %reg1027 ;; Sign extend X into EDX
idiv %reg1025 ;; Divide by Y (in reg1025)
%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
;; Start of ret
%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
ret
By the end of code generation, the register allocator would coalesce the registers and delete the resultant identity moves producing the following code:
;; X is in EAX, Y is in ECX
mov %EAX, %EDX
sar %EDX, 31
idiv %ECX
ret
This approach is extremely general (if it can handle the X86 architecture, it can handle anything!) and allows all of the target specific knowledge about the instruction stream to be isolated in the instruction selector. Note that physical registers should have a short lifetime for good code generation, and all physical registers are assumed dead on entry to and exit from basic blocks (before register allocation). Thus, if you need a value to be live across basic block boundaries, it must live in a virtual register.
Call-clobbered registers¶
Some machine instructions, like calls, clobber a large number of physical
registers. Rather than adding <def,dead> operands for all of them, it is
possible to use an MO_RegisterMask operand instead. The register mask
operand holds a bit mask of preserved registers, and everything else is
considered to be clobbered by the instruction.
Machine code in SSA form¶
MachineInstr’s are initially selected in SSA-form, and are maintained in
SSA-form until register allocation happens. For the most part, this is
trivially simple since LLVM is already in SSA form; LLVM PHI nodes become
machine code PHI nodes, and virtual registers are only allowed to have a single
definition.
After register allocation, machine code is no longer in SSA-form because there are no virtual registers left in the code.
The MachineBasicBlock class¶
The MachineBasicBlock class contains a list of machine instructions
( MachineInstr instances). It roughly
corresponds to the LLVM code input to the instruction selector, but there can be
a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
basic blocks). The MachineBasicBlock class has a “getBasicBlock” method,
which returns the LLVM basic block that it comes from.
The MachineFunction class¶
The MachineFunction class contains a list of machine basic blocks
( MachineBasicBlock instances). It
corresponds one-to-one with the LLVM function input to the instruction selector.
In addition to a list of basic blocks, the MachineFunction contains a
MachineConstantPool, a MachineFrameInfo, a MachineFunctionInfo, and
a MachineRegisterInfo. See include/llvm/CodeGen/MachineFunction.h for
more information.