All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size
ROM
size
EEPROM
size
Common
SFRs
  APFCON 0x11D "top: 32px">Mirrored
0x5F0 - 0x5FF
16 bytes
Unimplemented
0x68C - 0x690
5 bytes
Unimplemented
0x696 - 0x6EF
90 bytes
Mirrored
0x6F0 - 0x6FF
16 bytes
-mcus.html">12 bits14 bits16 bitsRAM
size
ROM
size
EEPROM  ( Last address of ROM/FLASH
 
 
 
 
 
 
 
 
 
 
 
 
ANSELA 0x18C
ANSELB
ANSELE 0x190
PMADRPMADRL 0x191
PMADRH 0x192
PMDATPMDATL 0x193
Unimplemented
0x70C - 0x76F
100 bytes
Mirrored
0x770 - 0x77F
16 bytes
Unimplemented
0x78C - 0x7EF
100 bytes
Unimplemented
0xD8C - 0xDEF
100 bytes
Mirrored
0xDF0 - 0xDFF
16 bytes
Unimplemented
0xE0C - 0xE6F
100 bytes
Mirrored
0xE70 - 0xE7F
16 bytes
class="sfrName">CLC4GLS2 0xF2E
Unimplemented
0xE8C - 0xEEF
100 bytessfrSep"> 
 
 
 
 
 
 
 
 
 
 
 
ICDIO 0xF8C
ICDSTAT 0xF91
 
 
 
DEVSEL 0xF95
ICDINSTL 0xF96
ICDINSTH 0xF97
 
0x07FF
Size of ROM 2048 words
Address space of User ID 0x2000 - 0x2003  (4 bytes)
Address of Device ID 0x2006  (1 byte)
Address of Configuration Word 0x2007  (1 word)
Number of RAM Banks GPR
0 bytes
Common
0 bytes
Mirrored
16 bytes
Unimplemented
89 bytes
Unimplemented
0x30C - 0x31F
20 bytes
WRT = OFF
0x3FFF Write protection off.
 General-purpose RAM.

 Common RAM.

 Mirrored RAM.

 In this place no RAM.

This page generated automatically by the device-help.pl program (2022-01-30 15:56:09 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.

./usr/share/doc/gputils/html/PIC16LF1517-sfr.html0000644000000000000000000006726514737157030020053 0ustar rootroot PIC16LF1517
Low-voltage programming enabled.

This page generated automatically by the device-help.pl program (2022-01-30 15:56:09 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.

tr> /td> ( Last address of ROM/FLASH
INDF0 0x000
ICDINSTH 0xF97
 
0x07FF
Size of ROM 2048 words
Address space of User ID 0x2000 - 0x2003  (4 bytes)
Address of Device ID 0x2006  (1 byte)
Address of Configuration Word 0x2007  (1 word)
Number of RAM Banks GPR
0 bytes
Common
0 bytes
Mirrored
16 bytes
Unimplemented
89 bytes
Unimplemented
0x30C - 0x31F
20 bytes
WRT = OFF
0x3FFF Write protection off.
 General-purpose RAM.

 Common RAM.

 Mirrored RAM.

 In this place no RAM.

This page generated automatically by the device-help.pl program (2022-01-30 15:56:09 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn

./usr/share/doc/gputils/html/PIC16LF1517-sfr.html000064400000000000000000000672Name">PWRTE = ON
0x3FEF PWRT enabled.
PWRTE = OFF 0x3FFF
T2CON 0x01C
1l">CLKOUT function is enabled on the CLKOUT pin.sk:0x0400)0xF1D256 bytes0xF1D256 bytes0xF1D 0 class="confSwExpl">Brown-out Reset Voltage (Vb6212 high trip point
 
 
 
 
 
 
CLKOUTEN = OFF 0x3FFF CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
IESO -- Internal/External Switchover Mode (bitmask CP = OFF 0x3FFF Internal/External Switchover Mode is disabled.
IESO = ON 0x3FFF Internal/External Switchover Mode is enabled.
FCMEN -- Fail-Safe Clock Monitor Enable (bitmask:0x2000)
FCMEN = OFF 0x1FFF Fail-Safe Clock Monitor is disabled.
FCMEN = ON 0x3FFF Fail-Safe Clock Monitor is enabled.
CONFIG2 (address:0x8008, mask:0x3E03, default:0x3E03)
WRT -- Flash Memory Self-Write Protection (bitmask:0x0003)
WRT = ALL 0x3FFC 000h to 1FFFh write protected, no addresses may be modified by EECON control.
WRT = HALF 0x3FFD 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
WRT = BOOT 0x3FFE 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
WRT = OFF 0x3FFF Write protection off.
STVREN -- Stack Overflow/Underflow Reset Enable (bitmask:0x0200)
STVREN = OFF 0x3DFF Stack Overflow or Underflow will not cause a Reset.
STVREN = ON CONFIG2 (address:0x8008, mask:0x3E03, default:0x3E03)
WRT -- Flash Memory Self-Write Protection (bitmask:0x0003)
BORV = HI 0x3BFF Brown-out Reset Voltage (Vbor), high trip point selected.
BORV = LO 0x3FFF Brown-out Reset Voltage (Vbor), low trip point selected.
LPBOR -- Low-Power Brown Out Reset (bitmask:0x0800)
LPBOR = ON 0x37FF Low-Power BOR is enabled.
LPBOR = OFF 0x3FFF Low-Power BOR is disabled.
DEBUG -- Debugger enable bit (bitmask:0x1000)
DEBUG = ON 0x2FFF Background debugger enabled.
DEBUG = OFF 0x3FFF Background debugger disabled.
LVP -- Low-Voltage Programming Enable (bitmask:0x2000)
Unimplemented
0x020
GPR
0x021 - 0x06F
79 bytes
Common
0x070 - 0x07F
16 bytes
Unimplemented
0x088 - 0x089
2 bytes
Unimplemented
0x091
SFR
12 bytes
GPR
0 bytes
Common
0 bytes
Mirrored
16 bytes
Unimplemented
100 bytes
SFR
12 bytes
GPR
0 bytes
Common
0 bytes
Mirrored
16 bytes
Unimplemented
100 bytes
SFR
12 bytes
GPR
0 bytes
Common
0 bytes
Mirrored
16 bytes
Unimplemented
100 bytes
SFR
12 bytes
GPR
0 bytes
Common
0 bytes
Mirrored
16 bytes
Unimplemented
100 bytes
SFR
12 bytes
GPR
0 bytes
Common
0 bytes
Mirrored
16 bytes
Unimplemented<
4096 words
Address space of User ID 0x8000 - 0x8003  (4 bytes)
Address of Device ID 0x8006  (1 byte)
Address space of Configuration Words 0x8007 - 0x8008  (2 words)
Number of RAM Banks 32  (128 bytes/banks)
Number of SFRs 165
Size of shared GPRs 16 bytes
Size of all GPRs 256 bytes
Joint size of SFRs + GPRs 421 bytes
Start address of Linear RAM Mirrored
16 bytes
Unimplemented
100 bytes
 
 
 
 
 
 
 
 
 
 
 
 
CLCDATA 0xF0F
CLC1CON 0xF10
CLC1POL 0x2  (128 bytes/banks)
Number of SFRs 165
Size of shared GPRs 16 bytes
Size of all GPRs 256 bytes
Joint size of SFRs + GPRs 421 bytes
Start address of Linear RAM Mirrored
16 bytes
Unimplemented
100 bytes
 
 
 
 
 
 
 
 
 
 
 
 
CLCDATA 0xF0F
CLC2GLS2 0xF1E
CLC2GLS3 0xF1F
CLC3CON 0xF20
CLC3POL 0xF21
Joint size of SFRs + GPRs 421 bytes
Start address of Linear RAM Mirrored
16 bytes
Unimplemented
100 bytes
 
 
 
 
 
 
 
 
 
 
 
 
CLCDATA 0xF0F
CLC2GLS2 0xF1E
CLC2GLS3 0xF1F
CLC3CON 0xF20
CLC3POL 0xF21
Joint size of SFRs + GPRs 421 bytes
Start address of Linear RAM Mirrored
16 bytes
Unimplemented
100 bytes
 
 
 
 
 
 
 
 
 
 
 
 
CLCDATA 0xF0F
CLC2GLS2 0xF1E
Unimplemented
0xB8C - 0xBEF
100 bytes
Mirrored
0xBF0 - 0xBFF
16 bytes
Unimplemented
0xC0C - 0xC6F
100 bytes
Mirrored
0xC70 - 0xC7F
16 bytes
Unimplemented
0xC8C - 0xCEF
100 bytes
Mirrored
0xCF0 - 0xCFF
16 bytes
Unimplemented
0xD0C - 0xD6F
100 bytes
Mirrored
0xD70 - 0xD7F
16 bytes
Unversioned directory). The mpasmx is included in the MPLAB X.

./usr/share/doc/gputils/html/PIC16LF1526-feat.html0000644000000000000000000001073514737157030020166 0ustar rootroot SFR
0xE80 - 0xE8B
12 bytes
Unimplemented
0xE8C - 0xEEF
100 bytes
Mirrored
0xEF0 - 0xEFF
16 bytes
Unimplemented
0xF0C - 0xF0E
3 bytes
Unimplemented
0xF30 - 0xF6F
64 bytes
Coff ID of device 0xA526
Number of ROM/FLASH pages 4  (2048 words/pages)
Last address of ROM/FLASH 0x1FFF
Size of ROM 8192 words
Address space of User ID 0x8000 - 0x8003  (4 bytes)
Address of
ADCON0 0x01F
alue">752 bytes
 <
Number of RAM Banks 32  (128 bytes/banks)
Number of SFRs 172
Size of shared GPRs 16 bytes
Size of all GPRs 768 bytes
Joint size of SFRs + GPRs 940 bytes
Start address of Linear RAM 0x2000
Size of Linear RAM
Number of Linear RAM sections 10
Standard header p16lf1526.inc
Standard linker script 16lf1526_g.lkr

This page generated automatically by the device-help.pl program (2022-01-30 15:56:09 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.

.ck Overflow or Underflow will not cause a Reset. STVREN = ON CONFIG2 (address:0x8008, mask:0x3E03,
GPR
0x120 - 0x16F
80 bytes
Mirrored
0x170 - 0x17F
16 bytes
Unimplemented
0x181
Unimplemented
0x185 - 0x189
5 bytes
DEBUG -- Debugg