<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
 <component
   name="$${FILENAME}"
   displayName="$${FILENAME}"
   version="1.0"
   description=""
   tags=""
   categories="System" />
 <parameter name="bonusData"><![CDATA[bonusData 
{
   element ad9361_clk_bridge
   {
      datum _sortIndex
      {
         value = "4";
         type = "int";
      }
   }
   element adc_pack
   {
      datum _sortIndex
      {
         value = "6";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element arradio_bd
   {
      datum _originalDeviceFamily
      {
         value = "Cyclone V";
         type = "String";
      }
   }
   element arradio_bd
   {
      datum _originalDeviceFamily
      {
         value = "Cyclone V";
         type = "String";
      }
   }
   element arradio_bd
   {
      datum _originalDeviceFamily
      {
         value = "Cyclone V";
         type = "String";
      }
   }
   element arradio_bd
   {
      datum _originalDeviceFamily
      {
         value = "Cyclone V";
         type = "String";
      }
   }
   element arradio_bd
   {
      datum _originalDeviceFamily
      {
         value = "Cyclone V";
         type = "String";
      }
   }
   element arradio_bd
   {
      datum _originalDeviceFamily
      {
         value = "Cyclone V";
         type = "String";
      }
   }
   element arradio_bd
   {
      datum _originalDeviceFamily
      {
         value = "Cyclone V";
         type = "String";
      }
   }
   element arradio_bd
   {
      datum _originalDeviceFamily
      {
         value = "Cyclone V";
         type = "String";
      }
   }
   element axi_ad9361
   {
      datum _sortIndex
      {
         value = "5";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element axi_ad9361.s_axi
   {
      datum baseAddress
      {
         value = "131072";
         type = "String";
      }
   }
   element axi_dmac_adc
   {
      datum _sortIndex
      {
         value = "7";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element axi_dmac_adc.s_axi
   {
      datum baseAddress
      {
         value = "0";
         type = "String";
      }
   }
   element axi_dmac_dac
   {
      datum _sortIndex
      {
         value = "9";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element axi_dmac_dac.s_axi
   {
      datum baseAddress
      {
         value = "16384";
         type = "String";
      }
   }
   element dac_upack
   {
      datum _sortIndex
      {
         value = "8";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element gpio
   {
      datum _sortIndex
      {
         value = "11";
         type = "int";
      }
   }
   element mem_clk
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
   }
   element mem_rst
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
   }
   element spi_ad9361
   {
      datum _sortIndex
      {
         value = "10";
         type = "int";
      }
      datum sopceditor_expanded
      {
         value = "1";
         type = "boolean";
      }
   }
   element spi_ad9361.spi_control_port
   {
      datum baseAddress
      {
         value = "32768";
         type = "String";
      }
   }
   element sys_clk
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
   element sys_rst
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
   }
}
]]></parameter>
 <parameter name="clockCrossingAdapter" value="FIFO" />
 <parameter name="device" value="5CSXFC6D6F31C8ES" />
 <parameter name="deviceFamily" value="Cyclone V" />
 <parameter name="deviceSpeedGrade" value="8_H6" />
 <parameter name="fabricMode" value="QSYS" />
 <parameter name="generateLegacySim" value="false" />
 <parameter name="generationId" value="0" />
 <parameter name="globalResetBus" value="false" />
 <parameter name="hdlLanguage" value="VERILOG" />
 <parameter name="hideFromIPCatalog" value="false" />
 <parameter name="lockedInterfaceDefinition" value="" />
 <parameter name="maxAdditionalLatency" value="2" />
 <parameter name="projectName" value="" />
 <parameter name="sopcBorderPoints" value="false" />
 <parameter name="systemHash" value="0" />
 <parameter name="testBenchDutName" value="" />
 <parameter name="timeStamp" value="0" />
 <parameter name="useTestBenchNamingPattern" value="false" />
 <instanceScript></instanceScript>
 <interface
   name="axi_ad9361_device_clock"
   internal="axi_ad9361.device_clock"
   type="clock"
   dir="end" />
 <interface
   name="axi_ad9361_device_if"
   internal="axi_ad9361.device_if"
   type="conduit"
   dir="end" />
 <interface
   name="axi_ad9361_l_clk"
   internal="ad9361_clk_bridge.out_clk"
   type="clock"
   dir="start" />
 <interface
   name="axi_ad9361_s_axi"
   internal="axi_ad9361.s_axi"
   type="axi4lite"
   dir="end" />
 <interface
   name="axi_dmac_adc_fifo_wr_clock"
   internal="axi_dmac_adc.fifo_wr_clock" />
 <interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
 <interface
   name="axi_dmac_adc_intr"
   internal="axi_dmac_adc.interrupt_sender"
   type="interrupt"
   dir="end" />
 <interface
   name="axi_dmac_adc_m_dest_axi"
   internal="axi_dmac_adc.m_dest_axi"
   type="axi4"
   dir="start" />
 <interface
   name="axi_dmac_adc_s_axi"
   internal="axi_dmac_adc.s_axi"
   type="axi4lite"
   dir="end" />
 <interface
   name="axi_dmac_dac_fifo_rd_clock"
   internal="axi_dmac_dac.fifo_rd_clock" />
 <interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
 <interface
   name="axi_dmac_dac_intr"
   internal="axi_dmac_dac.interrupt_sender"
   type="interrupt"
   dir="end" />
 <interface
   name="axi_dmac_dac_m_src_axi"
   internal="axi_dmac_dac.m_src_axi"
   type="axi4"
   dir="start" />
 <interface
   name="axi_dmac_dac_s_axi"
   internal="axi_dmac_dac.s_axi"
   type="axi4lite"
   dir="end" />
 <interface
   name="gpio_external_connection"
   internal="gpio.external_connection"
   type="conduit"
   dir="end" />
 <interface name="gpio_s1" internal="gpio.s1" type="avalon" dir="end" />
 <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
 <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
 <interface
   name="spi_ad9361_external"
   internal="spi_ad9361.external"
   type="conduit"
   dir="end" />
 <interface
   name="spi_ad9361_irq"
   internal="spi_ad9361.irq"
   type="interrupt"
   dir="end" />
 <interface
   name="spi_ad9361_spi_control_port"
   internal="spi_ad9361.spi_control_port"
   type="avalon"
   dir="end" />
 <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
 <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
 <module
   name="ad9361_clk_bridge"
   kind="altera_clock_bridge"
   version="15.1"
   enabled="1">
  <parameter name="DERIVED_CLOCK_RATE" value="0" />
  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
 </module>
 <module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
  <parameter name="NUM_OF_CHANNELS" value="4" />
 </module>
 <module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
  <parameter name="DEVICE_TYPE" value="0" />
  <parameter name="ID" value="0" />
 </module>
 <module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
  <parameter name="AXI_SLICE_DEST" value="0" />
  <parameter name="AXI_SLICE_SRC" value="0" />
  <parameter name="CYCLIC" value="0" />
  <parameter name="DMA_2D_TRANSFER" value="0" />
  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
  <parameter name="DMA_LENGTH_WIDTH" value="24" />
  <parameter name="DMA_TYPE_DEST" value="0" />
  <parameter name="DMA_TYPE_SRC" value="2" />
  <parameter name="FIFO_SIZE" value="4" />
  <parameter name="ID" value="0" />
  <parameter name="SYNC_TRANSFER_START" value="1" />
 </module>
 <module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
  <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
  <parameter name="ASYNC_CLK_REQ_SRC" value="1" />
  <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
  <parameter name="AXI_SLICE_DEST" value="0" />
  <parameter name="AXI_SLICE_SRC" value="0" />
  <parameter name="CYCLIC" value="1" />
  <parameter name="DMA_2D_TRANSFER" value="0" />
  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
  <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
  <parameter name="DMA_LENGTH_WIDTH" value="24" />
  <parameter name="DMA_TYPE_DEST" value="2" />
  <parameter name="DMA_TYPE_SRC" value="0" />
  <parameter name="FIFO_SIZE" value="4" />
  <parameter name="ID" value="0" />
  <parameter name="SYNC_TRANSFER_START" value="0" />
 </module>
 <module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
  <parameter name="CHANNEL_DATA_WIDTH" value="16" />
  <parameter name="NUM_OF_CHANNELS" value="4" />
 </module>
 <module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="direction" value="Output" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="5" />
 </module>
 <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
  <parameter name="DERIVED_CLOCK_RATE" value="0" />
  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
 </module>
 <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
  <parameter name="ACTIVE_LOW_RESET" value="0" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
  <parameter name="NUM_RESET_OUTPUTS" value="1" />
  <parameter name="SYNCHRONOUS_EDGES" value="none" />
  <parameter name="USE_RESET_REQUEST" value="0" />
 </module>
 <module name="spi_ad9361" kind="altera_avalon_spi" version="15.1" enabled="1">
  <parameter name="avalonSpec" value="2.0" />
  <parameter name="clockPhase" value="0" />
  <parameter name="clockPolarity" value="1" />
  <parameter name="dataWidth" value="8" />
  <parameter name="disableAvalonFlowControl" value="false" />
  <parameter name="inputClockRate" value="50000000" />
  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
  <parameter name="insertSync" value="false" />
  <parameter name="lsbOrderedFirst" value="false" />
  <parameter name="masterSPI" value="true" />
  <parameter name="numberOfSlaves" value="1" />
  <parameter name="syncRegDepth" value="2" />
  <parameter name="targetClockRate" value="50000000" />
  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
 </module>
 <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
  <parameter name="DERIVED_CLOCK_RATE" value="0" />
  <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
 </module>
 <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
  <parameter name="ACTIVE_LOW_RESET" value="0" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
  <parameter name="NUM_RESET_OUTPUTS" value="1" />
  <parameter name="SYNCHRONOUS_EDGES" value="none" />
  <parameter name="USE_RESET_REQUEST" value="0" />
 </module>
 <connection
   kind="clock"
   version="15.1"
   start="axi_ad9361.if_l_clk"
   end="adc_pack.if_adc_clk" />
 <connection
   kind="clock"
   version="15.1"
   start="axi_ad9361.if_l_clk"
   end="dac_upack.if_dac_clk" />
 <connection
   kind="clock"
   version="15.1"
   start="axi_ad9361.if_l_clk"
   end="axi_dmac_dac.if_fifo_rd_clk" />
 <connection
   kind="clock"
   version="15.1"
   start="axi_ad9361.if_l_clk"
   end="axi_dmac_adc.if_fifo_wr_clk" />
 <connection
   kind="clock"
   version="15.1"
   start="axi_ad9361.if_l_clk"
   end="ad9361_clk_bridge.in_clk" />
 <connection
   kind="clock"
   version="15.1"
   start="sys_clk.out_clk"
   end="spi_ad9361.clk" />
 <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
 <connection
   kind="clock"
   version="15.1"
   start="sys_clk.out_clk"
   end="axi_ad9361.delay_clock" />
 <connection
   kind="clock"
   version="15.1"
   start="mem_clk.out_clk"
   end="axi_dmac_adc.m_dest_axi_clock" />
 <connection
   kind="clock"
   version="15.1"
   start="mem_clk.out_clk"
   end="axi_dmac_dac.m_src_axi_clock" />
 <connection
   kind="clock"
   version="15.1"
   start="sys_clk.out_clk"
   end="axi_ad9361.s_axi_clock" />
 <connection
   kind="clock"
   version="15.1"
   start="sys_clk.out_clk"
   end="axi_dmac_adc.s_axi_clock" />
 <connection
   kind="clock"
   version="15.1"
   start="sys_clk.out_clk"
   end="axi_dmac_dac.s_axi_clock" />
 <connection
   kind="conduit"
   version="15.1"
   start="dac_upack.fifo_ch_0"
   end="axi_ad9361.fifo_ch_0_out">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="axi_ad9361.fifo_ch_0_in"
   end="adc_pack.fifo_ch_0">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="axi_ad9361.fifo_ch_1_in"
   end="adc_pack.fifo_ch_1">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="axi_ad9361.fifo_ch_1_out"
   end="dac_upack.fifo_ch_1">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="axi_ad9361.fifo_ch_2_in"
   end="adc_pack.fifo_ch_2">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="axi_ad9361.fifo_ch_2_out"
   end="dac_upack.fifo_ch_2">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="axi_ad9361.fifo_ch_3_in"
   end="adc_pack.fifo_ch_3">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="axi_ad9361.fifo_ch_3_out"
   end="dac_upack.fifo_ch_3">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="adc_pack.if_adc_data"
   end="axi_dmac_adc.if_fifo_wr_din">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="adc_pack.if_adc_sync"
   end="axi_dmac_adc.if_fifo_wr_sync">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="adc_pack.if_adc_valid"
   end="axi_dmac_adc.if_fifo_wr_en">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="dac_upack.if_dac_data"
   end="axi_dmac_dac.if_fifo_rd_dout">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="dac_upack.if_dma_xfer_in"
   end="axi_dmac_dac.if_fifo_rd_xfer_req">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="axi_dmac_dac.if_fifo_rd_en"
   end="dac_upack.if_dac_valid">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="axi_dmac_dac.if_fifo_rd_underflow"
   end="axi_ad9361.if_dac_dunf">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="conduit"
   version="15.1"
   start="axi_dmac_adc.if_fifo_wr_overflow"
   end="axi_ad9361.if_adc_dovf">
  <parameter name="endPort" value="" />
  <parameter name="endPortLSB" value="0" />
  <parameter name="startPort" value="" />
  <parameter name="startPortLSB" value="0" />
  <parameter name="width" value="0" />
 </connection>
 <connection
   kind="reset"
   version="15.1"
   start="axi_ad9361.if_rst"
   end="adc_pack.if_adc_rst" />
 <connection
   kind="reset"
   version="15.1"
   start="sys_rst.out_reset"
   end="adc_pack.if_adc_rst" />
 <connection
   kind="reset"
   version="15.1"
   start="mem_rst.out_reset"
   end="adc_pack.if_adc_rst" />
 <connection
   kind="reset"
   version="15.1"
   start="mem_rst.out_reset"
   end="axi_dmac_adc.m_dest_axi_reset" />
 <connection
   kind="reset"
   version="15.1"
   start="mem_rst.out_reset"
   end="axi_dmac_dac.m_src_axi_reset" />
 <connection
   kind="reset"
   version="15.1"
   start="sys_rst.out_reset"
   end="spi_ad9361.reset" />
 <connection
   kind="reset"
   version="15.1"
   start="sys_rst.out_reset"
   end="gpio.reset" />
 <connection
   kind="reset"
   version="15.1"
   start="sys_rst.out_reset"
   end="axi_ad9361.s_axi_reset" />
 <connection
   kind="reset"
   version="15.1"
   start="sys_rst.out_reset"
   end="axi_dmac_adc.s_axi_reset" />
 <connection
   kind="reset"
   version="15.1"
   start="sys_rst.out_reset"
   end="axi_dmac_dac.s_axi_reset" />
 <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
 <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
 <interconnectRequirement
   for="mm_interconnect_0|cmd_mux"
   name="qsys_mm.postTransform.pipelineCount"
   value="0" />
 <interconnectRequirement
   for="mm_interconnect_2|cmd_mux"
   name="qsys_mm.postTransform.pipelineCount"
   value="0" />
 <interconnectRequirement
   for="mm_interconnect_3|cmd_mux"
   name="qsys_mm.postTransform.pipelineCount"
   value="0" />
 <interconnectRequirement
   for="mm_interconnect_3|cmd_mux_001"
   name="qsys_mm.postTransform.pipelineCount"
   value="0" />
 <interconnectRequirement
   for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
   name="qsys_mm.postTransform.pipelineCount"
   value="0" />
 <interconnectRequirement
   for="mm_interconnect_4|cmd_mux"
   name="qsys_mm.postTransform.pipelineCount"
   value="0" />
 <interconnectRequirement
   for="mm_interconnect_4|cmd_mux_001"
   name="qsys_mm.postTransform.pipelineCount"
   value="0" />
</system>
