# This file gets copied by Qsys into the work directory.
# Need to use paths relative to that.
set adi_ip_dir   [file join $::quartus(qip_path) ../../../../../../fpga/ip/analogdevicesinc/hdl/]
set nuand_ip_dir [file join $::quartus(qip_path) ../../../../../../fpga/ip/nuand/]

set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_rst.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/altera/ad_lvds_clk.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/altera/ad_lvds_in.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/altera/ad_lvds_out.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/altera/MULT_MACRO.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/altera/DSP48E1.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_mul.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_pnmon.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_dds_sine.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_dds_1.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_dds.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_datafmt.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_dcfilter.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_iqcor.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/up_axi.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/up_xfer_cntrl.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/up_xfer_status.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/up_clock_mon.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/up_delay_cntrl.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/up_adc_common.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/up_adc_channel.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/up_dac_common.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/up_dac_channel.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/up_tdd_cntrl.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_tdd_control.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/common/ad_addsub.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361_alt_lvds_tx.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361_alt_lvds_rx.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361_dev_if_alt.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361_rx_pnmon.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361_rx_channel.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361_rx.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361_tx_channel.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361_tx.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361_tdd.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361_tdd_if.v]]
set_global_assignment -name VERILOG_FILE [file normalize [file join $adi_ip_dir/library/axi_ad9361/axi_ad9361.v]]

set_global_assignment -name VHDL_FILE [file normalize [file join $nuand_ip_dir/pll_reset/vhdl/pll_reset.vhd]]
