--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/avr-man
+++ avr-libc-2.0.0+Atmel3.6.2/debian/avr-man
@@ -0,0 +1,2 @@
+#! /bin/sh
+exec man -s 3avr "$@"
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/avr-man.1
+++ avr-libc-2.0.0+Atmel3.6.2/debian/avr-man.1
@@ -0,0 +1,17 @@
+.TH "AVR_MAN" 1 "2014-01-02"
+.SH NAME
+avr-man - a man(1) replacement to access the avr-libc manual pages
+.SH SYNOPSIS
+\fB avr-man \fR [ \fIOPTION\fR ] \fIpage\fR
+.SH DESCRIPTION
+.B avr-man
+is a wrapper script for \fBman\fR(1), displaying results for the specified \fIpage\fR from the manual pages shipped with the
+.IR avr-libc
+package.
+.PP
+\fIOPTION\fR parameters are passed to man. It is included for backwards compatibility. The recommended way to access these pages is now:
+
+    man 3avr page
+
+.SH "SEE ALSO"
+\fBman\fR(1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/bug_675759.patch
+++ avr-libc-2.0.0+Atmel3.6.2/debian/bug_675759.patch
@@ -0,0 +1,15 @@
+Index: include/avr/pgmspace.h
+===================================================================
+--- include/avr/pgmspace.h	(revision 2293)
++++ include/avr/pgmspace.h	(revision 2294)
+@@ -1081,8 +1081,8 @@
+ extern int memcmp_PF(const void *, uint_farptr_t, size_t) __ATTR_PURE__;
+ 
+ 
+-__attribute__((__always_inline__)) static inline size_t strlen_P(const char * s);
+-static inline size_t strlen_P(const char *s) {
++__attribute__((__always_inline__)) static __inline__ size_t strlen_P(const char * s);
++static __inline__ size_t strlen_P(const char *s) {
+   return __builtin_constant_p(__builtin_strlen(s))
+      ? __builtin_strlen(s) : __strlen_P(s);
+ } 
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/changelog
+++ avr-libc-2.0.0+Atmel3.6.2/debian/changelog
@@ -0,0 +1,379 @@
+avr-libc (1:2.0.0+Atmel3.6.2-3) unstable; urgency=medium
+
+  * Bump debhelper compat to 7 (closes: #965428)
+
+ -- Hakan Ardo <hakan@debian.org>  Fri, 07 Jan 2022 13:18:49 +0100
+
+avr-libc (1:2.0.0+Atmel3.6.2-2) unstable; urgency=medium
+
+  * Source only upload for migration to testing
+
+ -- Hakan Ardo <hakan@debian.org>  Fri, 11 Dec 2020 15:00:22 +0100
+
+avr-libc (1:2.0.0+Atmel3.6.2-1) unstable; urgency=medium
+
+  * New upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Wed, 11 Nov 2020 08:22:47 +0100
+
+avr-libc (1:2.0.0+Atmel3.6.1-2) unstable; urgency=medium
+
+  [ Hakan Ardo ]
+  * Fix latex errors (closes: #921775)
+
+  [ Ondřej Nový ]
+  * d/control: Deprecating priority extra as per policy 4.0.1
+  * d/changelog: Remove trailing whitespaces
+  * d/control: Remove trailing whitespaces
+  * d/rules: Remove trailing whitespaces
+  * d/control: Add Vcs-* field
+
+ -- Hakan Ardo <hakan@debian.org>  Sat, 16 Feb 2019 16:54:38 +0100
+
+avr-libc (1:2.0.0+Atmel3.6.1-1) unstable; urgency=medium
+
+  * New upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Thu, 28 Jun 2018 12:03:45 +0200
+
+avr-libc (1:2.0.0+Atmel3.6.0-1) unstable; urgency=medium
+
+  * New upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Fri, 04 Aug 2017 19:22:45 +0200
+
+avr-libc (1:2.0.0+Atmel3.5.4-1.1) unstable; urgency=medium
+
+  * Non-maintainer upload.
+  * Replaced the versioned build-dependency on autoconf2.59 by a
+    dependency on autoconf, which closes: #859535
+
+ -- Georges Khaznadar <georgesk@debian.org>  Wed, 12 Jul 2017 10:03:02 +0200
+
+avr-libc (1:2.0.0+Atmel3.5.4-1) unstable; urgency=medium
+
+  * New upstream release (closes: #779495, #787715, #762303, #785797)
+
+ -- Hakan Ardo <hakan@debian.org>  Wed, 05 Apr 2017 19:32:00 +0200
+
+avr-libc (1:1.8.0+Atmel3.5.0-1) unstable; urgency=medium
+
+  * New upstream release
+  * Add configure option --enable-device-lib
+
+ -- Hakan Ardo <hakan@debian.org>  Fri, 11 Dec 2015 16:58:02 +0100
+
+avr-libc (1:1.8.0+Atmel3.4.5-1) unstable; urgency=medium
+
+  * Added watch file
+  * New upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Wed, 01 Apr 2015 20:17:29 +0200
+
+avr-libc (1:1.8.0+Atmel3.4.4-1) unstable; urgency=medium
+
+  * New upstream release from Atmel-AVR-GNU-Toolchain v3.4.4
+    (http://distribute.atmel.no/tools/opensource/Atmel-AVR-GNU-
+    Toolchain/3.4.4/) (closes: #740391, #739953, #695514, #719635)
+  * Moved manpages to the 3avr section of /usr/share/man
+  * Added avr-man manpage (closes: #733939)
+  * Added build-arch and build-indep targets
+  * Moved build to binary-indep target
+  * Increased standards version to 3.9.5
+  * Added ${misc:Depends} dependency
+  * Applied upstream fix to make pgmspace.h ansi compatible (closes:
+    #675759)
+
+ -- Hakan Ardo <hakan@debian.org>  Tue, 03 Jun 2014 14:25:22 +0200
+
+avr-libc (1:1.8.0-4.1) unstable; urgency=medium
+
+  * Non-maintainer upload.
+  * debian/control: Switch to automake1.11. (Closes: #724351)
+
+ -- Eric Dorland <eric@debian.org>  Sun, 02 Mar 2014 18:14:01 -0500
+
+avr-libc (1:1.8.0-4) unstable; urgency=low
+
+  * Recompiled with gcc 4.8
+
+ -- Hakan Ardo <hakan@debian.org>  Sat, 05 Oct 2013 15:54:43 +0200
+
+avr-libc (1:1.8.0-3) unstable; urgency=low
+
+  * Move man pages to /usr/share/doc/avr-libc/man (closes: #678584,
+    #677059)
+
+ -- Hakan Ardo <hakan@debian.org>  Thu, 26 Jul 2012 07:31:00 +0200
+
+avr-libc (1:1.8.0-2) unstable; urgency=low
+
+  * New upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Wed, 23 May 2012 10:30:07 +0200
+
+avr-libc (1:1.8.0-1) experimental; urgency=low
+
+  * new upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Thu, 22 Mar 2012 21:01:33 +0100
+
+avr-libc (1:1.7.1-3) experimental; urgency=low
+
+  * recompiled with gcc 4.7
+
+ -- Hakan Ardo <hakan@debian.org>  Thu, 22 Mar 2012 20:43:05 +0100
+
+avr-libc (1:1.7.1-2) unstable; urgency=low
+
+  * include/util/delay.h.in: Add math.h to list of includes (closes:
+    #633822)
+
+ -- Hakan Ardo <hakan@debian.org>  Thu, 14 Jul 2011 11:15:32 +0200
+
+avr-libc (1:1.7.1-1) unstable; urgency=low
+
+  * New upstream release (closes: #626119)
+  * Now build-depends on doxygen-latex (closes: #616199)
+
+ -- Hakan Ardo <hakan@debian.org>  Sun, 10 Jul 2011 16:46:05 +0200
+
+avr-libc (1:1.6.8-2) unstable; urgency=low
+
+  * Recompiled with new toolchain
+  * Added ATmega325P to wdt.h (closes: #587574)
+
+ -- Hakan Ardo <hakan@debian.org>  Fri, 30 Jul 2010 10:55:29 +0200
+
+avr-libc (1:1.6.8-1) unstable; urgency=low
+
+  * New upstream release
+  * Replaced builddep on gs-gpl with ghostscript
+  * Autotools executed during build.
+  * Now build-depends on doxygen >= 1.6.2
+  * Errors in first two latex passes ignored (closes: #562312)
+
+ -- Hakan Ardo <hakan@debian.org>  Sun, 21 Feb 2010 11:54:12 +0100
+
+avr-libc (1:1.6.7-1) unstable; urgency=low
+
+  * New upstream relese (closes: #544030)
+  * Added lintian overrides (closes: #553265)
+
+ -- Hakan Ardo <hakan@debian.org>  Sat, 31 Oct 2009 11:52:10 +0100
+
+avr-libc (1:1.6.2.cvs20080610-2) unstable; urgency=low
+
+  * Added build-depends on texlive-extra-utils (closes: #493454)
+
+ -- Hakan Ardo <hakan@debian.org>  Sun, 10 Aug 2008 09:59:16 +0200
+
+avr-libc (1:1.6.2.cvs20080610-1) unstable; urgency=low
+
+  * New upstream release: WinAVR-20080610
+
+ -- Hakan Ardo <hakan@debian.org>  Sat, 19 Jul 2008 11:18:39 +0200
+
+avr-libc (1:1.6.2-2) unstable; urgency=low
+
+  * Recompiled with new gcc to add support for avr6
+  * Moved /usr/avr to /usr/lib/avr (closes: #486844)
+  * pdf manual index now has pagenumbers (closes: #486219)
+
+ -- Hakan Ardo <hakan@debian.org>  Wed, 02 Jul 2008 13:53:45 +0200
+
+avr-libc (1:1.6.2-1) unstable; urgency=low
+
+  * New upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Fri, 04 Apr 2008 17:05:32 +0200
+
+avr-libc (1:1.6.1-1) unstable; urgency=low
+
+  * New upstream release (closes: #464622)
+
+ -- Hakan Ardo <hakan@debian.org>  Fri, 08 Feb 2008 14:58:42 +0100
+
+avr-libc (1:1.4.7-1) unstable; urgency=low
+
+  * New upstream release (closes: #410831, #420163, #421088, #452199, #394231)
+  * Replaced tetex packages with texlive in Build-Depends (closes:
+    #427266)
+  * Now ignores returnstatus of pdflatex when generating docs to prevent
+    the build processing from halting on latex warnings (closes:
+    #427266)
+
+ -- Hakan Ardo <hakan@debian.org>  Sat, 29 Dec 2007 16:20:03 +0100
+
+avr-libc (1:1.4.6-1) unstable; urgency=low
+
+  * New upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Thu,  9 Aug 2007 11:28:01 +0200
+
+avr-libc (1:1.4.5-3) unstable; urgency=low
+
+  * Recompiled with new gcc/binutils
+  * Fixed build-depends (closes: #420060)
+
+ -- Hakan Ardo <hakan@debian.org>  Sun, 22 Apr 2007 17:52:23 +0200
+
+avr-libc (1:1.4.5-2) unstable; urgency=low
+
+  * Convertion to debheler fixed (closes: #398220)
+  * Reference to /usr/share/common-licenses in copyright file
+
+ -- Hakan Ardo <hakan@debian.org>  Wed, 15 Nov 2006 21:12:47 +0100
+
+avr-libc (1:1.4.5-1) unstable; urgency=low
+
+  * New upstream release
+  * Converted from debmake to debhelper (closes: #373000)
+
+ -- Hakan Ardo <hakan@debian.org>  Wed,  1 Nov 2006 07:32:23 +0100
+
+avr-libc (1:1.4.4-2) unstable; urgency=low
+
+  * Recompiled with gcc-4.1
+
+ -- Hakan Ardo <hakan@debian.org>  Mon,  1 May 2006 12:03:39 +0200
+
+avr-libc (1:1.4.4-1) unstable; urgency=low
+
+  * New upstream release (closes: #355631, #360685)
+
+ -- Hakan Ardo <hakan@debian.org>  Mon, 24 Apr 2006 20:43:52 +0200
+
+avr-libc (1:1.4.3-1) unstable; urgency=low
+
+  * New upstream release (closes: #350536,#299881). Older versions of avr-libc
+    are avalible as avr-libc-1.2 and avr-libc-1.0.
+
+ -- Hakan Ardo <hakan@debian.org>  Sun,  5 Feb 2006 11:29:51 +0100
+
+avr-libc (1:1.2.3-3) unstable; urgency=low
+
+  * Added build depends on netpbm
+  * Added build depends on tetex-extra
+
+ -- Hakan Ardo <hakan@debian.org>  Sat, 19 Mar 2005 11:16:14 +0100
+
+avr-libc (1:1.2.3-2) unstable; urgency=low
+
+  * Added gs to Build-Depends
+
+ -- Hakan Ardo <hakan@debian.org>  Wed,  2 Mar 2005 07:05:20 +0100
+
+avr-libc (1:1.2.3-1) unstable; urgency=low
+
+  * Upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Sun, 27 Feb 2005 10:19:36 +0100
+
+avr-libc (1:1.2.0-1) unstable; urgency=low
+
+  * Upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Sun,  2 Jan 2005 15:31:06 +0100
+
+avr-libc (1:1.0.5-1) unstable; urgency=low
+
+  * New upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Sun, 26 Dec 2004 12:58:53 +0100
+
+avr-libc (1:1.0.4-1) unstable; urgency=low
+
+  * Upstream update
+
+ -- Hakan Ardo <hakan@debian.org>  Wed, 11 Aug 2004 17:48:58 +0200
+
+avr-libc (1:1.0.3-1) unstable; urgency=low
+
+  * Upstream update
+
+ -- Hakan Ardo <hakan@debian.org>  Mon, 29 Mar 2004 15:08:19 +0200
+
+avr-libc (20030512cvs-1) unstable; urgency=low
+
+  * Updated to 20030512
+
+ -- Hakan Ardo <hakan@debian.org>  Sat, 24 May 2003 13:39:43 +0200
+
+avr-libc (20020203-4) unstable; urgency=low
+
+  * Enabled crtm8.o and crtm128.o (closes: #160290)
+  * Secured __port_cbi_sbi_ok macro with parens (closes: #182898)
+  * LICENSE file now included (closes: #182899)
+
+ -- Hakan Ardo <hakan@debian.org>  Sat, 15 Mar 2003 10:09:49 +0100
+
+avr-libc (20020203-3) unstable; urgency=low
+
+  * Added avr link in include dir (closes: #173755)
+  * Documents and examples now included (closes: #160298)
+  * Moved around )s in iomacros.h (closes: #162030, #174505)
+
+ -- Hakan Ardo <hakan@debian.org>  Wed, 26 Feb 2003 18:31:28 +0100
+
+avr-libc (20020203-2) unstable; urgency=low
+
+  * Support for the mega AVRs now restored (avr3,avr4 and avr5)
+
+ -- Hakan Ardo <hakan@debian.org>  Mon, 15 Apr 2002 14:53:38 +0200
+
+avr-libc (20020203-1) unstable; urgency=low
+
+  * New upstream release (closes: #139033)
+
+ -- Hakan Ardo <hakan@debian.org>  Sat, 30 Mar 2002 10:23:12 +0100
+
+avr-libc (20010708-4) unstable; urgency=low
+
+  * Updated Build-Depend on gcc to reflect version dependency
+    (close: #133366).
+  * Changed arch to all (closes: #134443)
+
+ -- Hakan Ardo <hakan@debian.org>  Mon, 11 Mar 2002 15:56:30 +0100
+
+avr-libc (20010708-3) unstable; urgency=low
+
+  * Recompiled with new avr-gcc instead oc avr-linux-gcc
+
+ -- Hakan Ardo <hakan@debian.org>  Sat,  9 Feb 2002 16:10:00 +0100
+
+avr-libc (20010708-2) unstable; urgency=low
+
+  * Fixed some spell errors (Bug  #100109)
+  * Fixed clean target not to craete dirs (Bug #107089)
+
+ -- Hakan Ardo <hakan@debian.org>  Sat,  9 Feb 2002 16:09:35 +0100
+
+avr-libc (20010708-1) unstable; urgency=low
+
+  * New upstream release
+
+ -- Hakan Ardo <hakan@debian.org>  Sat, 14 Jul 2001 12:46:11 +0200
+
+avr-libc (20010331-1) unstable; urgency=low
+
+  * New upstream release.
+  * Added Build-Depends
+
+ -- Hakan Ardo <hakan@debian.org>  Sat,  7 Apr 2001 19:15:22 +0200
+
+avr-libc (20000514-2) unstable; urgency=low
+
+  * Moved to main
+
+ -- Hakan Ardo <hakan@debian.org>  Sun, 29 Oct 2000 13:11:28 +0100
+
+avr-libc (20000514-1) unstable; urgency=low
+
+  * Initial Release.
+
+ -- Hakan Ardo <hakan@debian.org>  Wed, 20 Sep 2000 22:08:40 +0200
+
+Local variables:
+mode: debian-changelog
+End:
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/compat
+++ avr-libc-2.0.0+Atmel3.6.2/debian/compat
@@ -0,0 +1 @@
+7
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/control
+++ avr-libc-2.0.0+Atmel3.6.2/debian/control
@@ -0,0 +1,16 @@
+Source: avr-libc
+Section: otherosfs
+Priority: optional
+Maintainer: Hakan Ardo <hakan@debian.org>
+Standards-Version: 3.9.5
+Build-Depends: gcc-avr (>=5.4.0+Atmel3.6.2-1), binutils-avr (>=2.26.20160125+Atmel3.6.2-1), debhelper (>=7), doxygen-latex (>=1.8.7), doxygen (>=1.8.7), transfig, ghostscript, netpbm, x11-common, autotools-dev, autoconf, automake1.11, unzip
+Vcs-Browser: https://salsa.debian.org/debian/avr-libc
+Vcs-Git: https://salsa.debian.org/debian/avr-libc.git
+
+Package: avr-libc
+Architecture: all
+Depends: ${shlibs:Depends}, ${misc:Depends},  gcc-avr (>=5.4.0+Atmel3.6.2-1), binutils-avr (>=2.26.20160125+Atmel3.6.2-1)
+Description: Standard C library for Atmel AVR development
+ Standard library used to the development of C programs for the
+ Atmel AVR micro controllers. This package contains static
+ libraries as well as the header files needed.
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/copyright
+++ avr-libc-2.0.0+Atmel3.6.2/debian/copyright
@@ -0,0 +1,78 @@
+This package was debianized by Hakan Ardo hakan@debian.org on
+Wed, 20 Sep 2000 22:08:40 +0200.
+
+It was downloaded from:
+
+  https://www.microchip.com/mplab/avr-support/avr-and-sam-downloads-archive
+  https://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en611560
+
+Copyright:
+
+The contents of avr-libc are licensed with a Modified BSD License.
+
+All of this is supposed to be Free Software, Open Source, DFSG-free,
+GPL-compatible, and OK to use in both free and proprietary applications.
+
+See the license information in the individual source files for details.
+
+Additions and corrections to this file are welcome.
+
+Both the BSD and GPL licens is available in /usr/share/common-licenses.
+
+*******************************************************************************
+Portions of avr-libc are Copyright (c) 1999-2004
+Keith Gudger,
+Steinar Haugen,
+Peter Jansen,
+Reinhard Jessich,
+Magnus Johansson,
+Artur Lipowski,
+Marek Michalkiewicz,
+Colin O'Flynn,
+Bob Paddock,
+Reiner Patommel,
+Michael Rickman,
+Theodore A. Roth,
+Juergen Schilling,
+Philip Soeberg,
+Nils Kristian Strom,
+Michael Stumpf,
+Stefan Swanepoel,
+Eric B. Weddington,
+Joerg Wunsch,
+The Regents of the University of California. 
+All rights reserved.
+
+Portions of avr-libc documentation Copyright (c) 1990, 1991, 1993, 1994
+The Regents of the University of California.
+All rights reserved.
+
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. 
+
+*******************************************************************************
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/docs
+++ avr-libc-2.0.0+Atmel3.6.2/debian/docs
@@ -0,0 +1 @@
+libc/avr-libc/README 
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/ignore_latext_exit_code.patch
+++ avr-libc-2.0.0+Atmel3.6.2/debian/ignore_latext_exit_code.patch
@@ -0,0 +1,19 @@
+*** avr-libc/doc/api/Makefile.am.org	2014-06-04 12:52:19.029957750 +0200
+--- avr-libc/doc/api/Makefile.am	2014-06-04 12:52:32.273985630 +0200
+***************
+*** 227,233 ****
+  dox-pdf: $(USER_MANUAL).pdf
+  
+  $(USER_MANUAL).pdf: latex_src/refman.tex
+! 	cd latex_src && ${MAKE} refman.pdf
+  	cp latex_src/refman.pdf $(USER_MANUAL).pdf
+  
+  # Install rules for the various documentation parts.  The actual
+--- 227,233 ----
+  dox-pdf: $(USER_MANUAL).pdf
+  
+  $(USER_MANUAL).pdf: latex_src/refman.tex
+! 	-cd latex_src && ${MAKE} refman.pdf
+  	cp latex_src/refman.pdf $(USER_MANUAL).pdf
+  
+  # Install rules for the various documentation parts.  The actual
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/lintian_overrides
+++ avr-libc-2.0.0+Atmel3.6.2/debian/lintian_overrides
@@ -0,0 +1,2 @@
+avr-libc: arch-independent-package-contains-binary-or-object
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/rules
+++ avr-libc-2.0.0+Atmel3.6.2/debian/rules
@@ -0,0 +1,67 @@
+#!/usr/bin/make -f
+# Made with the aid of debmake, by Christoph Lameter,
+# based on the sample debian/rules file for GNU hello by Ian Jackson.
+
+package=avr-libc
+
+SRC=libc/avr-libc
+
+build: build-stamp
+build-stamp:
+	$(checkdir)
+	cd $(SRC) && ./bootstrap
+	cd $(SRC) && ./configure --build=`./config.guess` --host=avr \
+	    --prefix=/usr/lib --enable-device-lib \
+	    --disable-versioned-doc --enable-doc \
+	    --disable-ps-doc --datadir=/usr/share --bindir=/usr/bin \
+	    --mandir=/usr/share/man
+
+	cd $(SRC) && make
+	touch build-stamp
+
+build-arch: build
+build-indep: build
+
+clean:
+	$(checkdir)
+	-make -C $(SRC) distclean
+	-rm -rf debian/tmp debian/files* core debian/substvars
+	-rm build-stamp
+	-rm -r libc/avr-libc/avr
+	-dh_clean
+
+binary-indep: checkroot build
+	$(checkdir)
+	RGBDEF=/etc/X11/rgb.txt make -C $(SRC) install DESTDIR=`pwd`/debian/$(package)
+	cp $(SRC)/NEWS debian/$(package)/usr/share/doc/$(package)/changelog
+	install -d debian/$(package)/usr/share/lintian/overrides
+	cp debian/lintian_overrides debian/$(package)/usr/share/lintian/overrides/$(package)
+	mv debian/avr-libc/usr/lib/bin debian/avr-libc/usr/
+	install -d debian/avr-libc/usr/share/man/man1
+	cp debian/avr-man.1 debian/avr-libc/usr/share/man/man1
+	cp debian/avr-man debian/avr-libc/usr/bin/
+
+	dh_installchangelogs
+	dh_installdocs
+	dh_installman
+	dh_compress
+	dh_fixperms
+	dh_installdeb
+
+	dh_md5sums
+	dh_gencontrol
+	dh_builddeb
+
+binary-arch: checkroot build
+
+define checkdir
+	test -f debian/rules
+endef
+
+binary: binary-indep binary-arch
+
+checkroot:
+	$(checkdir)
+	test root = "`whoami`"
+
+.PHONY: binary binary-arch binary-indep clean checkroot
--- avr-libc-2.0.0+Atmel3.6.2.orig/debian/watch
+++ avr-libc-2.0.0+Atmel3.6.2/debian/watch
@@ -0,0 +1,3 @@
+version=3
+opts=dversionmangle=s/^.*\+Atmel// \
+  http://distribute.atmel.no/tools/opensource/Atmel-AVR-GNU-Toolchain/ (\d+\.\d+\.\d+)/
--- avr-libc-2.0.0+Atmel3.6.2.orig/import_upstream.sh
+++ avr-libc-2.0.0+Atmel3.6.2/import_upstream.sh
@@ -0,0 +1,47 @@
+#!/bin/bash
+
+if [ $# -ne 3 ]; then 
+    echo Usage: $0 '<tar archive>' '<zip archive>' '<version>'
+    echo Exmpl: $0 avr-libc.tar.bz2 avr8-headers.zip 2.0.0+Atmel3.6.0
+    exit -1
+fi
+
+VER=$3
+
+set -x
+set -e
+
+git checkout upstream
+rm -Rf libc avr
+tar xf $1
+unzip $2
+git add libc avr
+git commit -m "Import upstream version $VER"
+git tag upstream/$VER
+git push
+git push --tags
+
+git checkout master
+git merge --no-commit upstream || true
+#sed -i -s 's/^MAN_EXTENSION.*/MAN_EXTENSION = .3avr/' libc/avr-libc/doc/api/doxygen.config.in
+#echo 'MAN_SUBDIR = man3' >> libc/avr-libc/doc/api/doxygen.config.in
+#sed -i -s 's/man\/man3\/\*.3/man\/man3\/\*.3avr/' libc/avr-libc/doc/api/Makefile.am
+mv avr/*.h libc/avr-libc/include/avr/
+git add libc
+git rm -r avr
+git commit -m "Merge patched upstream version $VER"
+
+dch -v 1:$VER-1 New upstream release
+dch -r ok
+git add debian/changelog
+
+vim debian/control
+git add debian/control
+
+git commit -m 'Release message in changelog and new versioned deps'
+
+git tag "debian/$VER-1"
+git push
+git push --tags
+
+gbp buildpackage --git-pbuilder --git-upstream-tree=branch --git-upstream-branch=upstream
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/Makefile.in
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/Makefile.in
@@ -0,0 +1,854 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# Copyright (c) 2004,2005  Theodore A. Roth
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in
+#   the documentation and/or other materials provided with the
+#   distribution.
+# * Neither the name of the copyright holders nor the names of
+#   contributors may be used to endorse or promote products derived
+#   from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+# $Id$
+#
+VPATH = @srcdir@
+am__is_gnu_make = { \
+  if test -z '$(MAKELEVEL)'; then \
+    false; \
+  elif test -n '$(MAKE_HOST)'; then \
+    true; \
+  elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+    true; \
+  else \
+    false; \
+  fi; \
+}
+am__make_running_with_option = \
+  case $${target_option-} in \
+      ?) ;; \
+      *) echo "am__make_running_with_option: internal error: invalid" \
+              "target option '$${target_option-}' specified" >&2; \
+         exit 1;; \
+  esac; \
+  has_opt=no; \
+  sane_makeflags=$$MAKEFLAGS; \
+  if $(am__is_gnu_make); then \
+    sane_makeflags=$$MFLAGS; \
+  else \
+    case $$MAKEFLAGS in \
+      *\\[\ \	]*) \
+        bs=\\; \
+        sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+          | sed "s/$$bs$$bs[$$bs $$bs	]*//g"`;; \
+    esac; \
+  fi; \
+  skip_next=no; \
+  strip_trailopt () \
+  { \
+    flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+  }; \
+  for flg in $$sane_makeflags; do \
+    test $$skip_next = yes && { skip_next=no; continue; }; \
+    case $$flg in \
+      *=*|--*) continue;; \
+        -*I) strip_trailopt 'I'; skip_next=yes;; \
+      -*I?*) strip_trailopt 'I';; \
+        -*O) strip_trailopt 'O'; skip_next=yes;; \
+      -*O?*) strip_trailopt 'O';; \
+        -*l) strip_trailopt 'l'; skip_next=yes;; \
+      -*l?*) strip_trailopt 'l';; \
+      -[dEDm]) skip_next=yes;; \
+      -[JT]) skip_next=yes;; \
+    esac; \
+    case $$flg in \
+      *$$target_option*) has_opt=yes; break;; \
+    esac; \
+  done; \
+  test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+subdir = .
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+	$(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(top_srcdir)/configure \
+	$(am__configure_deps) $(am__DIST_COMMON)
+am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
+ configure.lineno config.status.lineno
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = config.h
+CONFIG_CLEAN_FILES = avr-libc.spec
+CONFIG_CLEAN_VPATH_FILES =
+AM_V_P = $(am__v_P_@AM_V@)
+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+am__v_P_0 = false
+am__v_P_1 = :
+AM_V_GEN = $(am__v_GEN_@AM_V@)
+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
+am__v_GEN_0 = @echo "  GEN     " $@;
+am__v_GEN_1 = 
+AM_V_at = $(am__v_at_@AM_V@)
+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
+am__v_at_0 = @
+am__v_at_1 = 
+SOURCES =
+DIST_SOURCES =
+RECURSIVE_TARGETS = all-recursive check-recursive cscopelist-recursive \
+	ctags-recursive dvi-recursive html-recursive info-recursive \
+	install-data-recursive install-dvi-recursive \
+	install-exec-recursive install-html-recursive \
+	install-info-recursive install-pdf-recursive \
+	install-ps-recursive install-recursive installcheck-recursive \
+	installdirs-recursive pdf-recursive ps-recursive \
+	tags-recursive uninstall-recursive
+am__can_run_installinfo = \
+  case $$AM_UPDATE_INFO_DIR in \
+    n|no|NO) false;; \
+    *) (install-info --version) >/dev/null 2>&1;; \
+  esac
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive	\
+  distclean-recursive maintainer-clean-recursive
+am__recursive_targets = \
+  $(RECURSIVE_TARGETS) \
+  $(RECURSIVE_CLEAN_TARGETS) \
+  $(am__extra_recursive_targets)
+AM_RECURSIVE_TARGETS = $(am__recursive_targets:-recursive=) TAGS CTAGS \
+	cscope distdir dist dist-all distcheck
+am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) \
+	$(LISP)config.h.in
+# Read a list of newline-separated strings from the standard input,
+# and print each of them once, without duplicates.  Input order is
+# *not* preserved.
+am__uniquify_input = $(AWK) '\
+  BEGIN { nonempty = 0; } \
+  { items[$$0] = 1; nonempty = 1; } \
+  END { if (nonempty) { for (i in items) print i; }; } \
+'
+# Make sure the list of sources is unique.  This is necessary because,
+# e.g., the same source file might be shared among _SOURCES variables
+# for different programs/libraries.
+am__define_uniq_tagged_files = \
+  list='$(am__tagged_files)'; \
+  unique=`for i in $$list; do \
+    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+  done | $(am__uniquify_input)`
+ETAGS = etags
+CTAGS = ctags
+CSCOPE = cscope
+am__DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/avr-libc.spec.in \
+	$(srcdir)/config.h.in AUTHORS ChangeLog INSTALL NEWS README \
+	compile config.guess config.sub depcomp install-sh missing
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+distdir = $(PACKAGE)-$(VERSION)
+top_distdir = $(distdir)
+am__remove_distdir = \
+  if test -d "$(distdir)"; then \
+    find "$(distdir)" -type d ! -perm -200 -exec chmod u+w {} ';' \
+      && rm -rf "$(distdir)" \
+      || { sleep 5 && rm -rf "$(distdir)"; }; \
+  else :; fi
+am__post_remove_distdir = $(am__remove_distdir)
+am__relativize = \
+  dir0=`pwd`; \
+  sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+  sed_rest='s,^[^/]*/*,,'; \
+  sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+  sed_butlast='s,/*[^/]*$$,,'; \
+  while test -n "$$dir1"; do \
+    first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+    if test "$$first" != "."; then \
+      if test "$$first" = ".."; then \
+        dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+        dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+      else \
+        first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+        if test "$$first2" = "$$first"; then \
+          dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+        else \
+          dir2="../$$dir2"; \
+        fi; \
+        dir0="$$dir0"/"$$first"; \
+      fi; \
+    fi; \
+    dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+  done; \
+  reldir="$$dir2"
+GZIP_ENV = --best
+DIST_ARCHIVES = $(distdir).tar.bz2
+DIST_TARGETS = dist-bzip2
+distuninstallcheck_listfiles = find . -type f -print
+am__distuninstallcheck_listfiles = $(distuninstallcheck_listfiles) \
+  | sed 's|^\./|$(prefix)/|' | grep -v '$(infodir)/dir$$'
+distcleancheck_listfiles = find . -type f -print
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@
+AR = @AR@
+AS = @AS@
+ASDEBUG = @ASDEBUG@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AVR_LIBC_MAJOR = @AVR_LIBC_MAJOR@
+AVR_LIBC_MINOR = @AVR_LIBC_MINOR@
+AVR_LIBC_RELDATE = @AVR_LIBC_RELDATE@
+AVR_LIBC_REVISION = @AVR_LIBC_REVISION@
+AVR_LIBC_USER_MANUAL = @AVR_LIBC_USER_MANUAL@
+AVR_LIBC_VERSION = @AVR_LIBC_VERSION@
+AVR_LIBC_VERSION_NUMERIC = @AVR_LIBC_VERSION_NUMERIC@
+AWK = @AWK@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CDEBUG = @CDEBUG@
+CFLAGS = @CFLAGS@
+CPPFLAGS = @CPPFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DOCSDIR = @DOCSDIR@
+DOC_INST_DIR = @DOC_INST_DIR@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EXEEXT = @EXEEXT@
+FNO_JUMP_TABLES = @FNO_JUMP_TABLES@
+HAS_DELAY_CYCLES = @HAS_DELAY_CYCLES@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_DOX_HTML = @INSTALL_DOX_HTML@
+INSTALL_DOX_MAN = @INSTALL_DOX_MAN@
+INSTALL_DOX_PDF = @INSTALL_DOX_PDF@
+INSTALL_DOX_XML = @INSTALL_DOX_XML@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PNGTOPNM = @PNGTOPNM@
+PNMTOPNG = @PNMTOPNG@
+RANLIB = @RANLIB@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+TARGET_DOX_HTML = @TARGET_DOX_HTML@
+TARGET_DOX_PDF = @TARGET_DOX_PDF@
+TARGET_DOX_XML = @TARGET_DOX_XML@
+VERSION = @VERSION@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+runstatedir = @runstatedir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+EXTRA_DIST = \
+	LICENSE \
+	bootstrap \
+	ChangeLog \
+	ChangeLog-2009 \
+	ChangeLog-2008 \
+	ChangeLog-2007 \
+	ChangeLog-2006 \
+	ChangeLog-2005 \
+	ChangeLog-2004 \
+	ChangeLog-2003 \
+	ChangeLog-2002
+
+DISTCHECK_CONFIGURE_FLAGS = --host=avr
+SUBDIRS = common include crt1 libc libm avr doc scripts
+DIST_SUBDIRS = common include crt1 libc libm avr doc scripts devtools
+all: config.h
+	$(MAKE) $(AM_MAKEFLAGS) all-recursive
+
+.SUFFIXES:
+am--refresh: Makefile
+	@:
+$(srcdir)/Makefile.in:  $(srcdir)/Makefile.am  $(am__configure_deps)
+	@for dep in $?; do \
+	  case '$(am__configure_deps)' in \
+	    *$$dep*) \
+	      echo ' cd $(srcdir) && $(AUTOMAKE) --foreign'; \
+	      $(am__cd) $(srcdir) && $(AUTOMAKE) --foreign \
+		&& exit 0; \
+	      exit 1;; \
+	  esac; \
+	done; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign Makefile'; \
+	$(am__cd) $(top_srcdir) && \
+	  $(AUTOMAKE) --foreign Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+	@case '$?' in \
+	  *config.status*) \
+	    echo ' $(SHELL) ./config.status'; \
+	    $(SHELL) ./config.status;; \
+	  *) \
+	    echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \
+	    cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \
+	esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+	$(SHELL) ./config.status --recheck
+
+$(top_srcdir)/configure:  $(am__configure_deps)
+	$(am__cd) $(srcdir) && $(AUTOCONF)
+$(ACLOCAL_M4):  $(am__aclocal_m4_deps)
+	$(am__cd) $(srcdir) && $(ACLOCAL) $(ACLOCAL_AMFLAGS)
+$(am__aclocal_m4_deps):
+
+config.h: stamp-h1
+	@test -f $@ || rm -f stamp-h1
+	@test -f $@ || $(MAKE) $(AM_MAKEFLAGS) stamp-h1
+
+stamp-h1: $(srcdir)/config.h.in $(top_builddir)/config.status
+	@rm -f stamp-h1
+	cd $(top_builddir) && $(SHELL) ./config.status config.h
+$(srcdir)/config.h.in:  $(am__configure_deps) 
+	($(am__cd) $(top_srcdir) && $(AUTOHEADER))
+	rm -f stamp-h1
+	touch $@
+
+distclean-hdr:
+	-rm -f config.h stamp-h1
+avr-libc.spec: $(top_builddir)/config.status $(srcdir)/avr-libc.spec.in
+	cd $(top_builddir) && $(SHELL) ./config.status $@
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run 'make' without going through this Makefile.
+# To change the values of 'make' variables: instead of editing Makefiles,
+# (1) if the variable is set in 'config.status', edit 'config.status'
+#     (which will cause the Makefiles to be regenerated when you run 'make');
+# (2) otherwise, pass the desired values on the 'make' command line.
+$(am__recursive_targets):
+	@fail=; \
+	if $(am__make_keepgoing); then \
+	  failcom='fail=yes'; \
+	else \
+	  failcom='exit 1'; \
+	fi; \
+	dot_seen=no; \
+	target=`echo $@ | sed s/-recursive//`; \
+	case "$@" in \
+	  distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+	  *) list='$(SUBDIRS)' ;; \
+	esac; \
+	for subdir in $$list; do \
+	  echo "Making $$target in $$subdir"; \
+	  if test "$$subdir" = "."; then \
+	    dot_seen=yes; \
+	    local_target="$$target-am"; \
+	  else \
+	    local_target="$$target"; \
+	  fi; \
+	  ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+	  || eval $$failcom; \
+	done; \
+	if test "$$dot_seen" = "no"; then \
+	  $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+	fi; test -z "$$fail"
+
+ID: $(am__tagged_files)
+	$(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-recursive
+TAGS: tags
+
+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+	set x; \
+	here=`pwd`; \
+	if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+	  include_option=--etags-include; \
+	  empty_fix=.; \
+	else \
+	  include_option=--include; \
+	  empty_fix=; \
+	fi; \
+	list='$(SUBDIRS)'; for subdir in $$list; do \
+	  if test "$$subdir" = .; then :; else \
+	    test ! -f $$subdir/TAGS || \
+	      set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+	  fi; \
+	done; \
+	$(am__define_uniq_tagged_files); \
+	shift; \
+	if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+	  test -n "$$unique" || unique=$$empty_fix; \
+	  if test $$# -gt 0; then \
+	    $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+	      "$$@" $$unique; \
+	  else \
+	    $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+	      $$unique; \
+	  fi; \
+	fi
+ctags: ctags-recursive
+
+CTAGS: ctags
+ctags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+	$(am__define_uniq_tagged_files); \
+	test -z "$(CTAGS_ARGS)$$unique" \
+	  || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+	     $$unique
+
+GTAGS:
+	here=`$(am__cd) $(top_builddir) && pwd` \
+	  && $(am__cd) $(top_srcdir) \
+	  && gtags -i $(GTAGS_ARGS) "$$here"
+cscope: cscope.files
+	test ! -s cscope.files \
+	  || $(CSCOPE) -b -q $(AM_CSCOPEFLAGS) $(CSCOPEFLAGS) -i cscope.files $(CSCOPE_ARGS)
+clean-cscope:
+	-rm -f cscope.files
+cscope.files: clean-cscope cscopelist
+cscopelist: cscopelist-recursive
+
+cscopelist-am: $(am__tagged_files)
+	list='$(am__tagged_files)'; \
+	case "$(srcdir)" in \
+	  [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \
+	  *) sdir=$(subdir)/$(srcdir) ;; \
+	esac; \
+	for i in $$list; do \
+	  if test -f "$$i"; then \
+	    echo "$(subdir)/$$i"; \
+	  else \
+	    echo "$$sdir/$$i"; \
+	  fi; \
+	done >> $(top_builddir)/cscope.files
+
+distclean-tags:
+	-rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+	-rm -f cscope.out cscope.in.out cscope.po.out cscope.files
+
+distdir: $(DISTFILES)
+	$(am__remove_distdir)
+	test -d "$(distdir)" || mkdir "$(distdir)"
+	@srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+	topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+	list='$(DISTFILES)'; \
+	  dist_files=`for file in $$list; do echo $$file; done | \
+	  sed -e "s|^$$srcdirstrip/||;t" \
+	      -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+	case $$dist_files in \
+	  */*) $(MKDIR_P) `echo "$$dist_files" | \
+			   sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+			   sort -u` ;; \
+	esac; \
+	for file in $$dist_files; do \
+	  if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+	  if test -d $$d/$$file; then \
+	    dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+	    if test -d "$(distdir)/$$file"; then \
+	      find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+	    fi; \
+	    if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+	      cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+	      find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+	    fi; \
+	    cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+	  else \
+	    test -f "$(distdir)/$$file" \
+	    || cp -p $$d/$$file "$(distdir)/$$file" \
+	    || exit 1; \
+	  fi; \
+	done
+	@list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+	  if test "$$subdir" = .; then :; else \
+	    $(am__make_dryrun) \
+	      || test -d "$(distdir)/$$subdir" \
+	      || $(MKDIR_P) "$(distdir)/$$subdir" \
+	      || exit 1; \
+	    dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+	    $(am__relativize); \
+	    new_distdir=$$reldir; \
+	    dir1=$$subdir; dir2="$(top_distdir)"; \
+	    $(am__relativize); \
+	    new_top_distdir=$$reldir; \
+	    echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+	    echo "     am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+	    ($(am__cd) $$subdir && \
+	      $(MAKE) $(AM_MAKEFLAGS) \
+	        top_distdir="$$new_top_distdir" \
+	        distdir="$$new_distdir" \
+		am__remove_distdir=: \
+		am__skip_length_check=: \
+		am__skip_mode_fix=: \
+	        distdir) \
+	      || exit 1; \
+	  fi; \
+	done
+	$(MAKE) $(AM_MAKEFLAGS) \
+	  top_distdir="$(top_distdir)" distdir="$(distdir)" \
+	  dist-hook
+	-test -n "$(am__skip_mode_fix)" \
+	|| find "$(distdir)" -type d ! -perm -755 \
+		-exec chmod u+rwx,go+rx {} \; -o \
+	  ! -type d ! -perm -444 -links 1 -exec chmod a+r {} \; -o \
+	  ! -type d ! -perm -400 -exec chmod a+r {} \; -o \
+	  ! -type d ! -perm -444 -exec $(install_sh) -c -m a+r {} {} \; \
+	|| chmod -R a+r "$(distdir)"
+dist-gzip: distdir
+	tardir=$(distdir) && $(am__tar) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).tar.gz
+	$(am__post_remove_distdir)
+dist-bzip2: distdir
+	tardir=$(distdir) && $(am__tar) | BZIP2=$${BZIP2--9} bzip2 -c >$(distdir).tar.bz2
+	$(am__post_remove_distdir)
+
+dist-lzip: distdir
+	tardir=$(distdir) && $(am__tar) | lzip -c $${LZIP_OPT--9} >$(distdir).tar.lz
+	$(am__post_remove_distdir)
+
+dist-xz: distdir
+	tardir=$(distdir) && $(am__tar) | XZ_OPT=$${XZ_OPT--e} xz -c >$(distdir).tar.xz
+	$(am__post_remove_distdir)
+
+dist-tarZ: distdir
+	@echo WARNING: "Support for distribution archives compressed with" \
+		       "legacy program 'compress' is deprecated." >&2
+	@echo WARNING: "It will be removed altogether in Automake 2.0" >&2
+	tardir=$(distdir) && $(am__tar) | compress -c >$(distdir).tar.Z
+	$(am__post_remove_distdir)
+
+dist-shar: distdir
+	@echo WARNING: "Support for shar distribution archives is" \
+	               "deprecated." >&2
+	@echo WARNING: "It will be removed altogether in Automake 2.0" >&2
+	shar $(distdir) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).shar.gz
+	$(am__post_remove_distdir)
+
+dist-zip: distdir
+	-rm -f $(distdir).zip
+	zip -rq $(distdir).zip $(distdir)
+	$(am__post_remove_distdir)
+
+dist dist-all:
+	$(MAKE) $(AM_MAKEFLAGS) $(DIST_TARGETS) am__post_remove_distdir='@:'
+	$(am__post_remove_distdir)
+
+# This target untars the dist file and tries a VPATH configuration.  Then
+# it guarantees that the distribution is self-contained by making another
+# tarfile.
+distcheck: dist
+	case '$(DIST_ARCHIVES)' in \
+	*.tar.gz*) \
+	  GZIP=$(GZIP_ENV) gzip -dc $(distdir).tar.gz | $(am__untar) ;;\
+	*.tar.bz2*) \
+	  bzip2 -dc $(distdir).tar.bz2 | $(am__untar) ;;\
+	*.tar.lz*) \
+	  lzip -dc $(distdir).tar.lz | $(am__untar) ;;\
+	*.tar.xz*) \
+	  xz -dc $(distdir).tar.xz | $(am__untar) ;;\
+	*.tar.Z*) \
+	  uncompress -c $(distdir).tar.Z | $(am__untar) ;;\
+	*.shar.gz*) \
+	  GZIP=$(GZIP_ENV) gzip -dc $(distdir).shar.gz | unshar ;;\
+	*.zip*) \
+	  unzip $(distdir).zip ;;\
+	esac
+	chmod -R a-w $(distdir)
+	chmod u+w $(distdir)
+	mkdir $(distdir)/_build $(distdir)/_build/sub $(distdir)/_inst
+	chmod a-w $(distdir)
+	test -d $(distdir)/_build || exit 0; \
+	dc_install_base=`$(am__cd) $(distdir)/_inst && pwd | sed -e 's,^[^:\\/]:[\\/],/,'` \
+	  && dc_destdir="$${TMPDIR-/tmp}/am-dc-$$$$/" \
+	  && am__cwd=`pwd` \
+	  && $(am__cd) $(distdir)/_build/sub \
+	  && ../../configure \
+	    $(AM_DISTCHECK_CONFIGURE_FLAGS) \
+	    $(DISTCHECK_CONFIGURE_FLAGS) \
+	    --srcdir=../.. --prefix="$$dc_install_base" \
+	  && $(MAKE) $(AM_MAKEFLAGS) \
+	  && $(MAKE) $(AM_MAKEFLAGS) dvi \
+	  && $(MAKE) $(AM_MAKEFLAGS) check \
+	  && $(MAKE) $(AM_MAKEFLAGS) install \
+	  && $(MAKE) $(AM_MAKEFLAGS) installcheck \
+	  && $(MAKE) $(AM_MAKEFLAGS) uninstall \
+	  && $(MAKE) $(AM_MAKEFLAGS) distuninstallcheck_dir="$$dc_install_base" \
+	        distuninstallcheck \
+	  && chmod -R a-w "$$dc_install_base" \
+	  && ({ \
+	       (cd ../.. && umask 077 && mkdir "$$dc_destdir") \
+	       && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" install \
+	       && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" uninstall \
+	       && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" \
+	            distuninstallcheck_dir="$$dc_destdir" distuninstallcheck; \
+	      } || { rm -rf "$$dc_destdir"; exit 1; }) \
+	  && rm -rf "$$dc_destdir" \
+	  && $(MAKE) $(AM_MAKEFLAGS) dist \
+	  && rm -rf $(DIST_ARCHIVES) \
+	  && $(MAKE) $(AM_MAKEFLAGS) distcleancheck \
+	  && cd "$$am__cwd" \
+	  || exit 1
+	$(am__post_remove_distdir)
+	@(echo "$(distdir) archives ready for distribution: "; \
+	  list='$(DIST_ARCHIVES)'; for i in $$list; do echo $$i; done) | \
+	  sed -e 1h -e 1s/./=/g -e 1p -e 1x -e '$$p' -e '$$x'
+distuninstallcheck:
+	@test -n '$(distuninstallcheck_dir)' || { \
+	  echo 'ERROR: trying to run $@ with an empty' \
+	       '$$(distuninstallcheck_dir)' >&2; \
+	  exit 1; \
+	}; \
+	$(am__cd) '$(distuninstallcheck_dir)' || { \
+	  echo 'ERROR: cannot chdir into $(distuninstallcheck_dir)' >&2; \
+	  exit 1; \
+	}; \
+	test `$(am__distuninstallcheck_listfiles) | wc -l` -eq 0 \
+	   || { echo "ERROR: files left after uninstall:" ; \
+	        if test -n "$(DESTDIR)"; then \
+	          echo "  (check DESTDIR support)"; \
+	        fi ; \
+	        $(distuninstallcheck_listfiles) ; \
+	        exit 1; } >&2
+distcleancheck: distclean
+	@if test '$(srcdir)' = . ; then \
+	  echo "ERROR: distcleancheck can only run from a VPATH build" ; \
+	  exit 1 ; \
+	fi
+	@test `$(distcleancheck_listfiles) | wc -l` -eq 0 \
+	  || { echo "ERROR: files left in build directory after distclean:" ; \
+	       $(distcleancheck_listfiles) ; \
+	       exit 1; } >&2
+check-am: all-am
+check: check-recursive
+all-am: Makefile config.h
+installdirs: installdirs-recursive
+installdirs-am:
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+	@$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+	if test -z '$(STRIP)'; then \
+	  $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+	    install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+	      install; \
+	else \
+	  $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+	    install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+	    "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+	fi
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+	-test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+	-test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+	@echo "This command is intended for maintainers to use"
+	@echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-generic mostlyclean-am
+
+distclean: distclean-recursive
+	-rm -f $(am__CONFIG_DISTCLEAN_FILES)
+	-rm -f Makefile
+distclean-am: clean-am distclean-generic distclean-hdr distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+	-rm -f $(am__CONFIG_DISTCLEAN_FILES)
+	-rm -rf $(top_srcdir)/autom4te.cache
+	-rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: $(am__recursive_targets) all install-am install-strip
+
+.PHONY: $(am__recursive_targets) CTAGS GTAGS TAGS all all-am \
+	am--refresh check check-am clean clean-cscope clean-generic \
+	cscope cscopelist-am ctags ctags-am dist dist-all dist-bzip2 \
+	dist-gzip dist-hook dist-lzip dist-shar dist-tarZ dist-xz \
+	dist-zip distcheck distclean distclean-generic distclean-hdr \
+	distclean-tags distcleancheck distdir distuninstallcheck dvi \
+	dvi-am html html-am info info-am install install-am \
+	install-data install-data-am install-dvi install-dvi-am \
+	install-exec install-exec-am install-html install-html-am \
+	install-info install-info-am install-man install-pdf \
+	install-pdf-am install-ps install-ps-am install-strip \
+	installcheck installcheck-am installdirs installdirs-am \
+	maintainer-clean maintainer-clean-generic mostlyclean \
+	mostlyclean-generic pdf pdf-am ps ps-am tags tags-am uninstall \
+	uninstall-am
+
+.PRECIOUS: Makefile
+
+
+dist-hook:
+	cp avr-libc.spec $(distdir)/avr-libc.spec
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/aclocal.m4
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/aclocal.m4
@@ -0,0 +1,1172 @@
+# generated automatically by aclocal 1.15 -*- Autoconf -*-
+
+# Copyright (C) 1996-2014 Free Software Foundation, Inc.
+
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+m4_ifndef([AC_CONFIG_MACRO_DIRS], [m4_defun([_AM_CONFIG_MACRO_DIRS], [])m4_defun([AC_CONFIG_MACRO_DIRS], [_AM_CONFIG_MACRO_DIRS($@)])])
+m4_ifndef([AC_AUTOCONF_VERSION],
+  [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl
+m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.69],,
+[m4_warning([this file was generated for autoconf 2.69.
+You have another version of autoconf.  It may work, but is not guaranteed to.
+If you have problems, you may need to regenerate the build system entirely.
+To do so, use the procedure documented by the package, typically 'autoreconf'.])])
+
+# Copyright (C) 2002-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_AUTOMAKE_VERSION(VERSION)
+# ----------------------------
+# Automake X.Y traces this macro to ensure aclocal.m4 has been
+# generated from the m4 files accompanying Automake X.Y.
+# (This private macro should not be called outside this file.)
+AC_DEFUN([AM_AUTOMAKE_VERSION],
+[am__api_version='1.15'
+dnl Some users find AM_AUTOMAKE_VERSION and mistake it for a way to
+dnl require some minimum version.  Point them to the right macro.
+m4_if([$1], [1.15], [],
+      [AC_FATAL([Do not call $0, use AM_INIT_AUTOMAKE([$1]).])])dnl
+])
+
+# _AM_AUTOCONF_VERSION(VERSION)
+# -----------------------------
+# aclocal traces this macro to find the Autoconf version.
+# This is a private macro too.  Using m4_define simplifies
+# the logic in aclocal, which can simply ignore this definition.
+m4_define([_AM_AUTOCONF_VERSION], [])
+
+# AM_SET_CURRENT_AUTOMAKE_VERSION
+# -------------------------------
+# Call AM_AUTOMAKE_VERSION and AM_AUTOMAKE_VERSION so they can be traced.
+# This function is AC_REQUIREd by AM_INIT_AUTOMAKE.
+AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION],
+[AM_AUTOMAKE_VERSION([1.15])dnl
+m4_ifndef([AC_AUTOCONF_VERSION],
+  [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl
+_AM_AUTOCONF_VERSION(m4_defn([AC_AUTOCONF_VERSION]))])
+
+# Figure out how to run the assembler.                      -*- Autoconf -*-
+
+# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_PROG_AS
+# ----------
+AC_DEFUN([AM_PROG_AS],
+[# By default we simply use the C compiler to build assembly code.
+AC_REQUIRE([AC_PROG_CC])
+test "${CCAS+set}" = set || CCAS=$CC
+test "${CCASFLAGS+set}" = set || CCASFLAGS=$CFLAGS
+AC_ARG_VAR([CCAS],      [assembler compiler command (defaults to CC)])
+AC_ARG_VAR([CCASFLAGS], [assembler compiler flags (defaults to CFLAGS)])
+_AM_IF_OPTION([no-dependencies],, [_AM_DEPENDENCIES([CCAS])])dnl
+])
+
+# AM_AUX_DIR_EXPAND                                         -*- Autoconf -*-
+
+# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# For projects using AC_CONFIG_AUX_DIR([foo]), Autoconf sets
+# $ac_aux_dir to '$srcdir/foo'.  In other projects, it is set to
+# '$srcdir', '$srcdir/..', or '$srcdir/../..'.
+#
+# Of course, Automake must honor this variable whenever it calls a
+# tool from the auxiliary directory.  The problem is that $srcdir (and
+# therefore $ac_aux_dir as well) can be either absolute or relative,
+# depending on how configure is run.  This is pretty annoying, since
+# it makes $ac_aux_dir quite unusable in subdirectories: in the top
+# source directory, any form will work fine, but in subdirectories a
+# relative path needs to be adjusted first.
+#
+# $ac_aux_dir/missing
+#    fails when called from a subdirectory if $ac_aux_dir is relative
+# $top_srcdir/$ac_aux_dir/missing
+#    fails if $ac_aux_dir is absolute,
+#    fails when called from a subdirectory in a VPATH build with
+#          a relative $ac_aux_dir
+#
+# The reason of the latter failure is that $top_srcdir and $ac_aux_dir
+# are both prefixed by $srcdir.  In an in-source build this is usually
+# harmless because $srcdir is '.', but things will broke when you
+# start a VPATH build or use an absolute $srcdir.
+#
+# So we could use something similar to $top_srcdir/$ac_aux_dir/missing,
+# iff we strip the leading $srcdir from $ac_aux_dir.  That would be:
+#   am_aux_dir='\$(top_srcdir)/'`expr "$ac_aux_dir" : "$srcdir//*\(.*\)"`
+# and then we would define $MISSING as
+#   MISSING="\${SHELL} $am_aux_dir/missing"
+# This will work as long as MISSING is not called from configure, because
+# unfortunately $(top_srcdir) has no meaning in configure.
+# However there are other variables, like CC, which are often used in
+# configure, and could therefore not use this "fixed" $ac_aux_dir.
+#
+# Another solution, used here, is to always expand $ac_aux_dir to an
+# absolute PATH.  The drawback is that using absolute paths prevent a
+# configured tree to be moved without reconfiguration.
+
+AC_DEFUN([AM_AUX_DIR_EXPAND],
+[AC_REQUIRE([AC_CONFIG_AUX_DIR_DEFAULT])dnl
+# Expand $ac_aux_dir to an absolute path.
+am_aux_dir=`cd "$ac_aux_dir" && pwd`
+])
+
+# AM_CONDITIONAL                                            -*- Autoconf -*-
+
+# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_CONDITIONAL(NAME, SHELL-CONDITION)
+# -------------------------------------
+# Define a conditional.
+AC_DEFUN([AM_CONDITIONAL],
+[AC_PREREQ([2.52])dnl
+ m4_if([$1], [TRUE],  [AC_FATAL([$0: invalid condition: $1])],
+       [$1], [FALSE], [AC_FATAL([$0: invalid condition: $1])])dnl
+AC_SUBST([$1_TRUE])dnl
+AC_SUBST([$1_FALSE])dnl
+_AM_SUBST_NOTMAKE([$1_TRUE])dnl
+_AM_SUBST_NOTMAKE([$1_FALSE])dnl
+m4_define([_AM_COND_VALUE_$1], [$2])dnl
+if $2; then
+  $1_TRUE=
+  $1_FALSE='#'
+else
+  $1_TRUE='#'
+  $1_FALSE=
+fi
+AC_CONFIG_COMMANDS_PRE(
+[if test -z "${$1_TRUE}" && test -z "${$1_FALSE}"; then
+  AC_MSG_ERROR([[conditional "$1" was never defined.
+Usually this means the macro was only invoked conditionally.]])
+fi])])
+
+# Copyright (C) 1999-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+
+# There are a few dirty hacks below to avoid letting 'AC_PROG_CC' be
+# written in clear, in which case automake, when reading aclocal.m4,
+# will think it sees a *use*, and therefore will trigger all it's
+# C support machinery.  Also note that it means that autoscan, seeing
+# CC etc. in the Makefile, will ask for an AC_PROG_CC use...
+
+
+# _AM_DEPENDENCIES(NAME)
+# ----------------------
+# See how the compiler implements dependency checking.
+# NAME is "CC", "CXX", "OBJC", "OBJCXX", "UPC", or "GJC".
+# We try a few techniques and use that to set a single cache variable.
+#
+# We don't AC_REQUIRE the corresponding AC_PROG_CC since the latter was
+# modified to invoke _AM_DEPENDENCIES(CC); we would have a circular
+# dependency, and given that the user is not expected to run this macro,
+# just rely on AC_PROG_CC.
+AC_DEFUN([_AM_DEPENDENCIES],
+[AC_REQUIRE([AM_SET_DEPDIR])dnl
+AC_REQUIRE([AM_OUTPUT_DEPENDENCY_COMMANDS])dnl
+AC_REQUIRE([AM_MAKE_INCLUDE])dnl
+AC_REQUIRE([AM_DEP_TRACK])dnl
+
+m4_if([$1], [CC],   [depcc="$CC"   am_compiler_list=],
+      [$1], [CXX],  [depcc="$CXX"  am_compiler_list=],
+      [$1], [OBJC], [depcc="$OBJC" am_compiler_list='gcc3 gcc'],
+      [$1], [OBJCXX], [depcc="$OBJCXX" am_compiler_list='gcc3 gcc'],
+      [$1], [UPC],  [depcc="$UPC"  am_compiler_list=],
+      [$1], [GCJ],  [depcc="$GCJ"  am_compiler_list='gcc3 gcc'],
+                    [depcc="$$1"   am_compiler_list=])
+
+AC_CACHE_CHECK([dependency style of $depcc],
+               [am_cv_$1_dependencies_compiler_type],
+[if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then
+  # We make a subdir and do the tests there.  Otherwise we can end up
+  # making bogus files that we don't know about and never remove.  For
+  # instance it was reported that on HP-UX the gcc test will end up
+  # making a dummy file named 'D' -- because '-MD' means "put the output
+  # in D".
+  rm -rf conftest.dir
+  mkdir conftest.dir
+  # Copy depcomp to subdir because otherwise we won't find it if we're
+  # using a relative directory.
+  cp "$am_depcomp" conftest.dir
+  cd conftest.dir
+  # We will build objects and dependencies in a subdirectory because
+  # it helps to detect inapplicable dependency modes.  For instance
+  # both Tru64's cc and ICC support -MD to output dependencies as a
+  # side effect of compilation, but ICC will put the dependencies in
+  # the current directory while Tru64 will put them in the object
+  # directory.
+  mkdir sub
+
+  am_cv_$1_dependencies_compiler_type=none
+  if test "$am_compiler_list" = ""; then
+     am_compiler_list=`sed -n ['s/^#*\([a-zA-Z0-9]*\))$/\1/p'] < ./depcomp`
+  fi
+  am__universal=false
+  m4_case([$1], [CC],
+    [case " $depcc " in #(
+     *\ -arch\ *\ -arch\ *) am__universal=true ;;
+     esac],
+    [CXX],
+    [case " $depcc " in #(
+     *\ -arch\ *\ -arch\ *) am__universal=true ;;
+     esac])
+
+  for depmode in $am_compiler_list; do
+    # Setup a source with many dependencies, because some compilers
+    # like to wrap large dependency lists on column 80 (with \), and
+    # we should not choose a depcomp mode which is confused by this.
+    #
+    # We need to recreate these files for each test, as the compiler may
+    # overwrite some of them when testing with obscure command lines.
+    # This happens at least with the AIX C compiler.
+    : > sub/conftest.c
+    for i in 1 2 3 4 5 6; do
+      echo '#include "conftst'$i'.h"' >> sub/conftest.c
+      # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with
+      # Solaris 10 /bin/sh.
+      echo '/* dummy */' > sub/conftst$i.h
+    done
+    echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf
+
+    # We check with '-c' and '-o' for the sake of the "dashmstdout"
+    # mode.  It turns out that the SunPro C++ compiler does not properly
+    # handle '-M -o', and we need to detect this.  Also, some Intel
+    # versions had trouble with output in subdirs.
+    am__obj=sub/conftest.${OBJEXT-o}
+    am__minus_obj="-o $am__obj"
+    case $depmode in
+    gcc)
+      # This depmode causes a compiler race in universal mode.
+      test "$am__universal" = false || continue
+      ;;
+    nosideeffect)
+      # After this tag, mechanisms are not by side-effect, so they'll
+      # only be used when explicitly requested.
+      if test "x$enable_dependency_tracking" = xyes; then
+	continue
+      else
+	break
+      fi
+      ;;
+    msvc7 | msvc7msys | msvisualcpp | msvcmsys)
+      # This compiler won't grok '-c -o', but also, the minuso test has
+      # not run yet.  These depmodes are late enough in the game, and
+      # so weak that their functioning should not be impacted.
+      am__obj=conftest.${OBJEXT-o}
+      am__minus_obj=
+      ;;
+    none) break ;;
+    esac
+    if depmode=$depmode \
+       source=sub/conftest.c object=$am__obj \
+       depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \
+       $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \
+         >/dev/null 2>conftest.err &&
+       grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 &&
+       grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 &&
+       grep $am__obj sub/conftest.Po > /dev/null 2>&1 &&
+       ${MAKE-make} -s -f confmf > /dev/null 2>&1; then
+      # icc doesn't choke on unknown options, it will just issue warnings
+      # or remarks (even with -Werror).  So we grep stderr for any message
+      # that says an option was ignored or not supported.
+      # When given -MP, icc 7.0 and 7.1 complain thusly:
+      #   icc: Command line warning: ignoring option '-M'; no argument required
+      # The diagnosis changed in icc 8.0:
+      #   icc: Command line remark: option '-MP' not supported
+      if (grep 'ignoring option' conftest.err ||
+          grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else
+        am_cv_$1_dependencies_compiler_type=$depmode
+        break
+      fi
+    fi
+  done
+
+  cd ..
+  rm -rf conftest.dir
+else
+  am_cv_$1_dependencies_compiler_type=none
+fi
+])
+AC_SUBST([$1DEPMODE], [depmode=$am_cv_$1_dependencies_compiler_type])
+AM_CONDITIONAL([am__fastdep$1], [
+  test "x$enable_dependency_tracking" != xno \
+  && test "$am_cv_$1_dependencies_compiler_type" = gcc3])
+])
+
+
+# AM_SET_DEPDIR
+# -------------
+# Choose a directory name for dependency files.
+# This macro is AC_REQUIREd in _AM_DEPENDENCIES.
+AC_DEFUN([AM_SET_DEPDIR],
+[AC_REQUIRE([AM_SET_LEADING_DOT])dnl
+AC_SUBST([DEPDIR], ["${am__leading_dot}deps"])dnl
+])
+
+
+# AM_DEP_TRACK
+# ------------
+AC_DEFUN([AM_DEP_TRACK],
+[AC_ARG_ENABLE([dependency-tracking], [dnl
+AS_HELP_STRING(
+  [--enable-dependency-tracking],
+  [do not reject slow dependency extractors])
+AS_HELP_STRING(
+  [--disable-dependency-tracking],
+  [speeds up one-time build])])
+if test "x$enable_dependency_tracking" != xno; then
+  am_depcomp="$ac_aux_dir/depcomp"
+  AMDEPBACKSLASH='\'
+  am__nodep='_no'
+fi
+AM_CONDITIONAL([AMDEP], [test "x$enable_dependency_tracking" != xno])
+AC_SUBST([AMDEPBACKSLASH])dnl
+_AM_SUBST_NOTMAKE([AMDEPBACKSLASH])dnl
+AC_SUBST([am__nodep])dnl
+_AM_SUBST_NOTMAKE([am__nodep])dnl
+])
+
+# Generate code to set up dependency tracking.              -*- Autoconf -*-
+
+# Copyright (C) 1999-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+
+# _AM_OUTPUT_DEPENDENCY_COMMANDS
+# ------------------------------
+AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS],
+[{
+  # Older Autoconf quotes --file arguments for eval, but not when files
+  # are listed without --file.  Let's play safe and only enable the eval
+  # if we detect the quoting.
+  case $CONFIG_FILES in
+  *\'*) eval set x "$CONFIG_FILES" ;;
+  *)   set x $CONFIG_FILES ;;
+  esac
+  shift
+  for mf
+  do
+    # Strip MF so we end up with the name of the file.
+    mf=`echo "$mf" | sed -e 's/:.*$//'`
+    # Check whether this is an Automake generated Makefile or not.
+    # We used to match only the files named 'Makefile.in', but
+    # some people rename them; so instead we look at the file content.
+    # Grep'ing the first line is not enough: some people post-process
+    # each Makefile.in and add a new line on top of each file to say so.
+    # Grep'ing the whole file is not good either: AIX grep has a line
+    # limit of 2048, but all sed's we know have understand at least 4000.
+    if sed -n 's,^#.*generated by automake.*,X,p' "$mf" | grep X >/dev/null 2>&1; then
+      dirpart=`AS_DIRNAME("$mf")`
+    else
+      continue
+    fi
+    # Extract the definition of DEPDIR, am__include, and am__quote
+    # from the Makefile without running 'make'.
+    DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"`
+    test -z "$DEPDIR" && continue
+    am__include=`sed -n 's/^am__include = //p' < "$mf"`
+    test -z "$am__include" && continue
+    am__quote=`sed -n 's/^am__quote = //p' < "$mf"`
+    # Find all dependency output files, they are included files with
+    # $(DEPDIR) in their names.  We invoke sed twice because it is the
+    # simplest approach to changing $(DEPDIR) to its actual value in the
+    # expansion.
+    for file in `sed -n "
+      s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \
+	 sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g'`; do
+      # Make sure the directory exists.
+      test -f "$dirpart/$file" && continue
+      fdir=`AS_DIRNAME(["$file"])`
+      AS_MKDIR_P([$dirpart/$fdir])
+      # echo "creating $dirpart/$file"
+      echo '# dummy' > "$dirpart/$file"
+    done
+  done
+}
+])# _AM_OUTPUT_DEPENDENCY_COMMANDS
+
+
+# AM_OUTPUT_DEPENDENCY_COMMANDS
+# -----------------------------
+# This macro should only be invoked once -- use via AC_REQUIRE.
+#
+# This code is only required when automatic dependency tracking
+# is enabled.  FIXME.  This creates each '.P' file that we will
+# need in order to bootstrap the dependency handling code.
+AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS],
+[AC_CONFIG_COMMANDS([depfiles],
+     [test x"$AMDEP_TRUE" != x"" || _AM_OUTPUT_DEPENDENCY_COMMANDS],
+     [AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"])
+])
+
+# Do all the work for Automake.                             -*- Autoconf -*-
+
+# Copyright (C) 1996-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This macro actually does too much.  Some checks are only needed if
+# your package does certain things.  But this isn't really a big deal.
+
+dnl Redefine AC_PROG_CC to automatically invoke _AM_PROG_CC_C_O.
+m4_define([AC_PROG_CC],
+m4_defn([AC_PROG_CC])
+[_AM_PROG_CC_C_O
+])
+
+# AM_INIT_AUTOMAKE(PACKAGE, VERSION, [NO-DEFINE])
+# AM_INIT_AUTOMAKE([OPTIONS])
+# -----------------------------------------------
+# The call with PACKAGE and VERSION arguments is the old style
+# call (pre autoconf-2.50), which is being phased out.  PACKAGE
+# and VERSION should now be passed to AC_INIT and removed from
+# the call to AM_INIT_AUTOMAKE.
+# We support both call styles for the transition.  After
+# the next Automake release, Autoconf can make the AC_INIT
+# arguments mandatory, and then we can depend on a new Autoconf
+# release and drop the old call support.
+AC_DEFUN([AM_INIT_AUTOMAKE],
+[AC_PREREQ([2.65])dnl
+dnl Autoconf wants to disallow AM_ names.  We explicitly allow
+dnl the ones we care about.
+m4_pattern_allow([^AM_[A-Z]+FLAGS$])dnl
+AC_REQUIRE([AM_SET_CURRENT_AUTOMAKE_VERSION])dnl
+AC_REQUIRE([AC_PROG_INSTALL])dnl
+if test "`cd $srcdir && pwd`" != "`pwd`"; then
+  # Use -I$(srcdir) only when $(srcdir) != ., so that make's output
+  # is not polluted with repeated "-I."
+  AC_SUBST([am__isrc], [' -I$(srcdir)'])_AM_SUBST_NOTMAKE([am__isrc])dnl
+  # test to see if srcdir already configured
+  if test -f $srcdir/config.status; then
+    AC_MSG_ERROR([source directory already configured; run "make distclean" there first])
+  fi
+fi
+
+# test whether we have cygpath
+if test -z "$CYGPATH_W"; then
+  if (cygpath --version) >/dev/null 2>/dev/null; then
+    CYGPATH_W='cygpath -w'
+  else
+    CYGPATH_W=echo
+  fi
+fi
+AC_SUBST([CYGPATH_W])
+
+# Define the identity of the package.
+dnl Distinguish between old-style and new-style calls.
+m4_ifval([$2],
+[AC_DIAGNOSE([obsolete],
+             [$0: two- and three-arguments forms are deprecated.])
+m4_ifval([$3], [_AM_SET_OPTION([no-define])])dnl
+ AC_SUBST([PACKAGE], [$1])dnl
+ AC_SUBST([VERSION], [$2])],
+[_AM_SET_OPTIONS([$1])dnl
+dnl Diagnose old-style AC_INIT with new-style AM_AUTOMAKE_INIT.
+m4_if(
+  m4_ifdef([AC_PACKAGE_NAME], [ok]):m4_ifdef([AC_PACKAGE_VERSION], [ok]),
+  [ok:ok],,
+  [m4_fatal([AC_INIT should be called with package and version arguments])])dnl
+ AC_SUBST([PACKAGE], ['AC_PACKAGE_TARNAME'])dnl
+ AC_SUBST([VERSION], ['AC_PACKAGE_VERSION'])])dnl
+
+_AM_IF_OPTION([no-define],,
+[AC_DEFINE_UNQUOTED([PACKAGE], ["$PACKAGE"], [Name of package])
+ AC_DEFINE_UNQUOTED([VERSION], ["$VERSION"], [Version number of package])])dnl
+
+# Some tools Automake needs.
+AC_REQUIRE([AM_SANITY_CHECK])dnl
+AC_REQUIRE([AC_ARG_PROGRAM])dnl
+AM_MISSING_PROG([ACLOCAL], [aclocal-${am__api_version}])
+AM_MISSING_PROG([AUTOCONF], [autoconf])
+AM_MISSING_PROG([AUTOMAKE], [automake-${am__api_version}])
+AM_MISSING_PROG([AUTOHEADER], [autoheader])
+AM_MISSING_PROG([MAKEINFO], [makeinfo])
+AC_REQUIRE([AM_PROG_INSTALL_SH])dnl
+AC_REQUIRE([AM_PROG_INSTALL_STRIP])dnl
+AC_REQUIRE([AC_PROG_MKDIR_P])dnl
+# For better backward compatibility.  To be removed once Automake 1.9.x
+# dies out for good.  For more background, see:
+# <http://lists.gnu.org/archive/html/automake/2012-07/msg00001.html>
+# <http://lists.gnu.org/archive/html/automake/2012-07/msg00014.html>
+AC_SUBST([mkdir_p], ['$(MKDIR_P)'])
+# We need awk for the "check" target (and possibly the TAP driver).  The
+# system "awk" is bad on some platforms.
+AC_REQUIRE([AC_PROG_AWK])dnl
+AC_REQUIRE([AC_PROG_MAKE_SET])dnl
+AC_REQUIRE([AM_SET_LEADING_DOT])dnl
+_AM_IF_OPTION([tar-ustar], [_AM_PROG_TAR([ustar])],
+	      [_AM_IF_OPTION([tar-pax], [_AM_PROG_TAR([pax])],
+			     [_AM_PROG_TAR([v7])])])
+_AM_IF_OPTION([no-dependencies],,
+[AC_PROVIDE_IFELSE([AC_PROG_CC],
+		  [_AM_DEPENDENCIES([CC])],
+		  [m4_define([AC_PROG_CC],
+			     m4_defn([AC_PROG_CC])[_AM_DEPENDENCIES([CC])])])dnl
+AC_PROVIDE_IFELSE([AC_PROG_CXX],
+		  [_AM_DEPENDENCIES([CXX])],
+		  [m4_define([AC_PROG_CXX],
+			     m4_defn([AC_PROG_CXX])[_AM_DEPENDENCIES([CXX])])])dnl
+AC_PROVIDE_IFELSE([AC_PROG_OBJC],
+		  [_AM_DEPENDENCIES([OBJC])],
+		  [m4_define([AC_PROG_OBJC],
+			     m4_defn([AC_PROG_OBJC])[_AM_DEPENDENCIES([OBJC])])])dnl
+AC_PROVIDE_IFELSE([AC_PROG_OBJCXX],
+		  [_AM_DEPENDENCIES([OBJCXX])],
+		  [m4_define([AC_PROG_OBJCXX],
+			     m4_defn([AC_PROG_OBJCXX])[_AM_DEPENDENCIES([OBJCXX])])])dnl
+])
+AC_REQUIRE([AM_SILENT_RULES])dnl
+dnl The testsuite driver may need to know about EXEEXT, so add the
+dnl 'am__EXEEXT' conditional if _AM_COMPILER_EXEEXT was seen.  This
+dnl macro is hooked onto _AC_COMPILER_EXEEXT early, see below.
+AC_CONFIG_COMMANDS_PRE(dnl
+[m4_provide_if([_AM_COMPILER_EXEEXT],
+  [AM_CONDITIONAL([am__EXEEXT], [test -n "$EXEEXT"])])])dnl
+
+# POSIX will say in a future version that running "rm -f" with no argument
+# is OK; and we want to be able to make that assumption in our Makefile
+# recipes.  So use an aggressive probe to check that the usage we want is
+# actually supported "in the wild" to an acceptable degree.
+# See automake bug#10828.
+# To make any issue more visible, cause the running configure to be aborted
+# by default if the 'rm' program in use doesn't match our expectations; the
+# user can still override this though.
+if rm -f && rm -fr && rm -rf; then : OK; else
+  cat >&2 <<'END'
+Oops!
+
+Your 'rm' program seems unable to run without file operands specified
+on the command line, even when the '-f' option is present.  This is contrary
+to the behaviour of most rm programs out there, and not conforming with
+the upcoming POSIX standard: <http://austingroupbugs.net/view.php?id=542>
+
+Please tell bug-automake@gnu.org about your system, including the value
+of your $PATH and any error possibly output before this message.  This
+can help us improve future automake versions.
+
+END
+  if test x"$ACCEPT_INFERIOR_RM_PROGRAM" = x"yes"; then
+    echo 'Configuration will proceed anyway, since you have set the' >&2
+    echo 'ACCEPT_INFERIOR_RM_PROGRAM variable to "yes"' >&2
+    echo >&2
+  else
+    cat >&2 <<'END'
+Aborting the configuration process, to ensure you take notice of the issue.
+
+You can download and install GNU coreutils to get an 'rm' implementation
+that behaves properly: <http://www.gnu.org/software/coreutils/>.
+
+If you want to complete the configuration process using your problematic
+'rm' anyway, export the environment variable ACCEPT_INFERIOR_RM_PROGRAM
+to "yes", and re-run configure.
+
+END
+    AC_MSG_ERROR([Your 'rm' program is bad, sorry.])
+  fi
+fi
+dnl The trailing newline in this macro's definition is deliberate, for
+dnl backward compatibility and to allow trailing 'dnl'-style comments
+dnl after the AM_INIT_AUTOMAKE invocation. See automake bug#16841.
+])
+
+dnl Hook into '_AC_COMPILER_EXEEXT' early to learn its expansion.  Do not
+dnl add the conditional right here, as _AC_COMPILER_EXEEXT may be further
+dnl mangled by Autoconf and run in a shell conditional statement.
+m4_define([_AC_COMPILER_EXEEXT],
+m4_defn([_AC_COMPILER_EXEEXT])[m4_provide([_AM_COMPILER_EXEEXT])])
+
+# When config.status generates a header, we must update the stamp-h file.
+# This file resides in the same directory as the config header
+# that is generated.  The stamp files are numbered to have different names.
+
+# Autoconf calls _AC_AM_CONFIG_HEADER_HOOK (when defined) in the
+# loop where config.status creates the headers, so we can generate
+# our stamp files there.
+AC_DEFUN([_AC_AM_CONFIG_HEADER_HOOK],
+[# Compute $1's index in $config_headers.
+_am_arg=$1
+_am_stamp_count=1
+for _am_header in $config_headers :; do
+  case $_am_header in
+    $_am_arg | $_am_arg:* )
+      break ;;
+    * )
+      _am_stamp_count=`expr $_am_stamp_count + 1` ;;
+  esac
+done
+echo "timestamp for $_am_arg" >`AS_DIRNAME(["$_am_arg"])`/stamp-h[]$_am_stamp_count])
+
+# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_PROG_INSTALL_SH
+# ------------------
+# Define $install_sh.
+AC_DEFUN([AM_PROG_INSTALL_SH],
+[AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl
+if test x"${install_sh+set}" != xset; then
+  case $am_aux_dir in
+  *\ * | *\	*)
+    install_sh="\${SHELL} '$am_aux_dir/install-sh'" ;;
+  *)
+    install_sh="\${SHELL} $am_aux_dir/install-sh"
+  esac
+fi
+AC_SUBST([install_sh])])
+
+# Copyright (C) 2003-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# Check whether the underlying file-system supports filenames
+# with a leading dot.  For instance MS-DOS doesn't.
+AC_DEFUN([AM_SET_LEADING_DOT],
+[rm -rf .tst 2>/dev/null
+mkdir .tst 2>/dev/null
+if test -d .tst; then
+  am__leading_dot=.
+else
+  am__leading_dot=_
+fi
+rmdir .tst 2>/dev/null
+AC_SUBST([am__leading_dot])])
+
+# Check to see how 'make' treats includes.	            -*- Autoconf -*-
+
+# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_MAKE_INCLUDE()
+# -----------------
+# Check to see how make treats includes.
+AC_DEFUN([AM_MAKE_INCLUDE],
+[am_make=${MAKE-make}
+cat > confinc << 'END'
+am__doit:
+	@echo this is the am__doit target
+.PHONY: am__doit
+END
+# If we don't find an include directive, just comment out the code.
+AC_MSG_CHECKING([for style of include used by $am_make])
+am__include="#"
+am__quote=
+_am_result=none
+# First try GNU make style include.
+echo "include confinc" > confmf
+# Ignore all kinds of additional output from 'make'.
+case `$am_make -s -f confmf 2> /dev/null` in #(
+*the\ am__doit\ target*)
+  am__include=include
+  am__quote=
+  _am_result=GNU
+  ;;
+esac
+# Now try BSD make style include.
+if test "$am__include" = "#"; then
+   echo '.include "confinc"' > confmf
+   case `$am_make -s -f confmf 2> /dev/null` in #(
+   *the\ am__doit\ target*)
+     am__include=.include
+     am__quote="\""
+     _am_result=BSD
+     ;;
+   esac
+fi
+AC_SUBST([am__include])
+AC_SUBST([am__quote])
+AC_MSG_RESULT([$_am_result])
+rm -f confinc confmf
+])
+
+# Fake the existence of programs that GNU maintainers use.  -*- Autoconf -*-
+
+# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_MISSING_PROG(NAME, PROGRAM)
+# ------------------------------
+AC_DEFUN([AM_MISSING_PROG],
+[AC_REQUIRE([AM_MISSING_HAS_RUN])
+$1=${$1-"${am_missing_run}$2"}
+AC_SUBST($1)])
+
+# AM_MISSING_HAS_RUN
+# ------------------
+# Define MISSING if not defined so far and test if it is modern enough.
+# If it is, set am_missing_run to use it, otherwise, to nothing.
+AC_DEFUN([AM_MISSING_HAS_RUN],
+[AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl
+AC_REQUIRE_AUX_FILE([missing])dnl
+if test x"${MISSING+set}" != xset; then
+  case $am_aux_dir in
+  *\ * | *\	*)
+    MISSING="\${SHELL} \"$am_aux_dir/missing\"" ;;
+  *)
+    MISSING="\${SHELL} $am_aux_dir/missing" ;;
+  esac
+fi
+# Use eval to expand $SHELL
+if eval "$MISSING --is-lightweight"; then
+  am_missing_run="$MISSING "
+else
+  am_missing_run=
+  AC_MSG_WARN(['missing' script is too old or missing])
+fi
+])
+
+# Helper functions for option handling.                     -*- Autoconf -*-
+
+# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# _AM_MANGLE_OPTION(NAME)
+# -----------------------
+AC_DEFUN([_AM_MANGLE_OPTION],
+[[_AM_OPTION_]m4_bpatsubst($1, [[^a-zA-Z0-9_]], [_])])
+
+# _AM_SET_OPTION(NAME)
+# --------------------
+# Set option NAME.  Presently that only means defining a flag for this option.
+AC_DEFUN([_AM_SET_OPTION],
+[m4_define(_AM_MANGLE_OPTION([$1]), [1])])
+
+# _AM_SET_OPTIONS(OPTIONS)
+# ------------------------
+# OPTIONS is a space-separated list of Automake options.
+AC_DEFUN([_AM_SET_OPTIONS],
+[m4_foreach_w([_AM_Option], [$1], [_AM_SET_OPTION(_AM_Option)])])
+
+# _AM_IF_OPTION(OPTION, IF-SET, [IF-NOT-SET])
+# -------------------------------------------
+# Execute IF-SET if OPTION is set, IF-NOT-SET otherwise.
+AC_DEFUN([_AM_IF_OPTION],
+[m4_ifset(_AM_MANGLE_OPTION([$1]), [$2], [$3])])
+
+# Copyright (C) 1999-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# _AM_PROG_CC_C_O
+# ---------------
+# Like AC_PROG_CC_C_O, but changed for automake.  We rewrite AC_PROG_CC
+# to automatically call this.
+AC_DEFUN([_AM_PROG_CC_C_O],
+[AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl
+AC_REQUIRE_AUX_FILE([compile])dnl
+AC_LANG_PUSH([C])dnl
+AC_CACHE_CHECK(
+  [whether $CC understands -c and -o together],
+  [am_cv_prog_cc_c_o],
+  [AC_LANG_CONFTEST([AC_LANG_PROGRAM([])])
+  # Make sure it works both with $CC and with simple cc.
+  # Following AC_PROG_CC_C_O, we do the test twice because some
+  # compilers refuse to overwrite an existing .o file with -o,
+  # though they will create one.
+  am_cv_prog_cc_c_o=yes
+  for am_i in 1 2; do
+    if AM_RUN_LOG([$CC -c conftest.$ac_ext -o conftest2.$ac_objext]) \
+         && test -f conftest2.$ac_objext; then
+      : OK
+    else
+      am_cv_prog_cc_c_o=no
+      break
+    fi
+  done
+  rm -f core conftest*
+  unset am_i])
+if test "$am_cv_prog_cc_c_o" != yes; then
+   # Losing compiler, so override with the script.
+   # FIXME: It is wrong to rewrite CC.
+   # But if we don't then we get into trouble of one sort or another.
+   # A longer-term fix would be to have automake use am__CC in this case,
+   # and then we could set am__CC="\$(top_srcdir)/compile \$(CC)"
+   CC="$am_aux_dir/compile $CC"
+fi
+AC_LANG_POP([C])])
+
+# For backward compatibility.
+AC_DEFUN_ONCE([AM_PROG_CC_C_O], [AC_REQUIRE([AC_PROG_CC])])
+
+# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_RUN_LOG(COMMAND)
+# -------------------
+# Run COMMAND, save the exit status in ac_status, and log it.
+# (This has been adapted from Autoconf's _AC_RUN_LOG macro.)
+AC_DEFUN([AM_RUN_LOG],
+[{ echo "$as_me:$LINENO: $1" >&AS_MESSAGE_LOG_FD
+   ($1) >&AS_MESSAGE_LOG_FD 2>&AS_MESSAGE_LOG_FD
+   ac_status=$?
+   echo "$as_me:$LINENO: \$? = $ac_status" >&AS_MESSAGE_LOG_FD
+   (exit $ac_status); }])
+
+# Check to make sure that the build environment is sane.    -*- Autoconf -*-
+
+# Copyright (C) 1996-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_SANITY_CHECK
+# ---------------
+AC_DEFUN([AM_SANITY_CHECK],
+[AC_MSG_CHECKING([whether build environment is sane])
+# Reject unsafe characters in $srcdir or the absolute working directory
+# name.  Accept space and tab only in the latter.
+am_lf='
+'
+case `pwd` in
+  *[[\\\"\#\$\&\'\`$am_lf]]*)
+    AC_MSG_ERROR([unsafe absolute working directory name]);;
+esac
+case $srcdir in
+  *[[\\\"\#\$\&\'\`$am_lf\ \	]]*)
+    AC_MSG_ERROR([unsafe srcdir value: '$srcdir']);;
+esac
+
+# Do 'set' in a subshell so we don't clobber the current shell's
+# arguments.  Must try -L first in case configure is actually a
+# symlink; some systems play weird games with the mod time of symlinks
+# (eg FreeBSD returns the mod time of the symlink's containing
+# directory).
+if (
+   am_has_slept=no
+   for am_try in 1 2; do
+     echo "timestamp, slept: $am_has_slept" > conftest.file
+     set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null`
+     if test "$[*]" = "X"; then
+	# -L didn't work.
+	set X `ls -t "$srcdir/configure" conftest.file`
+     fi
+     if test "$[*]" != "X $srcdir/configure conftest.file" \
+	&& test "$[*]" != "X conftest.file $srcdir/configure"; then
+
+	# If neither matched, then we have a broken ls.  This can happen
+	# if, for instance, CONFIG_SHELL is bash and it inherits a
+	# broken ls alias from the environment.  This has actually
+	# happened.  Such a system could not be considered "sane".
+	AC_MSG_ERROR([ls -t appears to fail.  Make sure there is not a broken
+  alias in your environment])
+     fi
+     if test "$[2]" = conftest.file || test $am_try -eq 2; then
+       break
+     fi
+     # Just in case.
+     sleep 1
+     am_has_slept=yes
+   done
+   test "$[2]" = conftest.file
+   )
+then
+   # Ok.
+   :
+else
+   AC_MSG_ERROR([newly created file is older than distributed files!
+Check your system clock])
+fi
+AC_MSG_RESULT([yes])
+# If we didn't sleep, we still need to ensure time stamps of config.status and
+# generated files are strictly newer.
+am_sleep_pid=
+if grep 'slept: no' conftest.file >/dev/null 2>&1; then
+  ( sleep 1 ) &
+  am_sleep_pid=$!
+fi
+AC_CONFIG_COMMANDS_PRE(
+  [AC_MSG_CHECKING([that generated files are newer than configure])
+   if test -n "$am_sleep_pid"; then
+     # Hide warnings about reused PIDs.
+     wait $am_sleep_pid 2>/dev/null
+   fi
+   AC_MSG_RESULT([done])])
+rm -f conftest.file
+])
+
+# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_SILENT_RULES([DEFAULT])
+# --------------------------
+# Enable less verbose build rules; with the default set to DEFAULT
+# ("yes" being less verbose, "no" or empty being verbose).
+AC_DEFUN([AM_SILENT_RULES],
+[AC_ARG_ENABLE([silent-rules], [dnl
+AS_HELP_STRING(
+  [--enable-silent-rules],
+  [less verbose build output (undo: "make V=1")])
+AS_HELP_STRING(
+  [--disable-silent-rules],
+  [verbose build output (undo: "make V=0")])dnl
+])
+case $enable_silent_rules in @%:@ (((
+  yes) AM_DEFAULT_VERBOSITY=0;;
+   no) AM_DEFAULT_VERBOSITY=1;;
+    *) AM_DEFAULT_VERBOSITY=m4_if([$1], [yes], [0], [1]);;
+esac
+dnl
+dnl A few 'make' implementations (e.g., NonStop OS and NextStep)
+dnl do not support nested variable expansions.
+dnl See automake bug#9928 and bug#10237.
+am_make=${MAKE-make}
+AC_CACHE_CHECK([whether $am_make supports nested variables],
+   [am_cv_make_support_nested_variables],
+   [if AS_ECHO([['TRUE=$(BAR$(V))
+BAR0=false
+BAR1=true
+V=1
+am__doit:
+	@$(TRUE)
+.PHONY: am__doit']]) | $am_make -f - >/dev/null 2>&1; then
+  am_cv_make_support_nested_variables=yes
+else
+  am_cv_make_support_nested_variables=no
+fi])
+if test $am_cv_make_support_nested_variables = yes; then
+  dnl Using '$V' instead of '$(V)' breaks IRIX make.
+  AM_V='$(V)'
+  AM_DEFAULT_V='$(AM_DEFAULT_VERBOSITY)'
+else
+  AM_V=$AM_DEFAULT_VERBOSITY
+  AM_DEFAULT_V=$AM_DEFAULT_VERBOSITY
+fi
+AC_SUBST([AM_V])dnl
+AM_SUBST_NOTMAKE([AM_V])dnl
+AC_SUBST([AM_DEFAULT_V])dnl
+AM_SUBST_NOTMAKE([AM_DEFAULT_V])dnl
+AC_SUBST([AM_DEFAULT_VERBOSITY])dnl
+AM_BACKSLASH='\'
+AC_SUBST([AM_BACKSLASH])dnl
+_AM_SUBST_NOTMAKE([AM_BACKSLASH])dnl
+])
+
+# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_PROG_INSTALL_STRIP
+# ---------------------
+# One issue with vendor 'install' (even GNU) is that you can't
+# specify the program used to strip binaries.  This is especially
+# annoying in cross-compiling environments, where the build's strip
+# is unlikely to handle the host's binaries.
+# Fortunately install-sh will honor a STRIPPROG variable, so we
+# always use install-sh in "make install-strip", and initialize
+# STRIPPROG with the value of the STRIP variable (set by the user).
+AC_DEFUN([AM_PROG_INSTALL_STRIP],
+[AC_REQUIRE([AM_PROG_INSTALL_SH])dnl
+# Installed binaries are usually stripped using 'strip' when the user
+# run "make install-strip".  However 'strip' might not be the right
+# tool to use in cross-compilation environments, therefore Automake
+# will honor the 'STRIP' environment variable to overrule this program.
+dnl Don't test for $cross_compiling = yes, because it might be 'maybe'.
+if test "$cross_compiling" != no; then
+  AC_CHECK_TOOL([STRIP], [strip], :)
+fi
+INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s"
+AC_SUBST([INSTALL_STRIP_PROGRAM])])
+
+# Copyright (C) 2006-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# _AM_SUBST_NOTMAKE(VARIABLE)
+# ---------------------------
+# Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in.
+# This macro is traced by Automake.
+AC_DEFUN([_AM_SUBST_NOTMAKE])
+
+# AM_SUBST_NOTMAKE(VARIABLE)
+# --------------------------
+# Public sister of _AM_SUBST_NOTMAKE.
+AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)])
+
+# Check how to create a tarball.                            -*- Autoconf -*-
+
+# Copyright (C) 2004-2014 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# _AM_PROG_TAR(FORMAT)
+# --------------------
+# Check how to create a tarball in format FORMAT.
+# FORMAT should be one of 'v7', 'ustar', or 'pax'.
+#
+# Substitute a variable $(am__tar) that is a command
+# writing to stdout a FORMAT-tarball containing the directory
+# $tardir.
+#     tardir=directory && $(am__tar) > result.tar
+#
+# Substitute a variable $(am__untar) that extract such
+# a tarball read from stdin.
+#     $(am__untar) < result.tar
+#
+AC_DEFUN([_AM_PROG_TAR],
+[# Always define AMTAR for backward compatibility.  Yes, it's still used
+# in the wild :-(  We should find a proper way to deprecate it ...
+AC_SUBST([AMTAR], ['$${TAR-tar}'])
+
+# We'll loop over all known methods to create a tar archive until one works.
+_am_tools='gnutar m4_if([$1], [ustar], [plaintar]) pax cpio none'
+
+m4_if([$1], [v7],
+  [am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -'],
+
+  [m4_case([$1],
+    [ustar],
+     [# The POSIX 1988 'ustar' format is defined with fixed-size fields.
+      # There is notably a 21 bits limit for the UID and the GID.  In fact,
+      # the 'pax' utility can hang on bigger UID/GID (see automake bug#8343
+      # and bug#13588).
+      am_max_uid=2097151 # 2^21 - 1
+      am_max_gid=$am_max_uid
+      # The $UID and $GID variables are not portable, so we need to resort
+      # to the POSIX-mandated id(1) utility.  Errors in the 'id' calls
+      # below are definitely unexpected, so allow the users to see them
+      # (that is, avoid stderr redirection).
+      am_uid=`id -u || echo unknown`
+      am_gid=`id -g || echo unknown`
+      AC_MSG_CHECKING([whether UID '$am_uid' is supported by ustar format])
+      if test $am_uid -le $am_max_uid; then
+         AC_MSG_RESULT([yes])
+      else
+         AC_MSG_RESULT([no])
+         _am_tools=none
+      fi
+      AC_MSG_CHECKING([whether GID '$am_gid' is supported by ustar format])
+      if test $am_gid -le $am_max_gid; then
+         AC_MSG_RESULT([yes])
+      else
+        AC_MSG_RESULT([no])
+        _am_tools=none
+      fi],
+
+  [pax],
+    [],
+
+  [m4_fatal([Unknown tar format])])
+
+  AC_MSG_CHECKING([how to create a $1 tar archive])
+
+  # Go ahead even if we have the value already cached.  We do so because we
+  # need to set the values for the 'am__tar' and 'am__untar' variables.
+  _am_tools=${am_cv_prog_tar_$1-$_am_tools}
+
+  for _am_tool in $_am_tools; do
+    case $_am_tool in
+    gnutar)
+      for _am_tar in tar gnutar gtar; do
+        AM_RUN_LOG([$_am_tar --version]) && break
+      done
+      am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"'
+      am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"'
+      am__untar="$_am_tar -xf -"
+      ;;
+    plaintar)
+      # Must skip GNU tar: if it does not support --format= it doesn't create
+      # ustar tarball either.
+      (tar --version) >/dev/null 2>&1 && continue
+      am__tar='tar chf - "$$tardir"'
+      am__tar_='tar chf - "$tardir"'
+      am__untar='tar xf -'
+      ;;
+    pax)
+      am__tar='pax -L -x $1 -w "$$tardir"'
+      am__tar_='pax -L -x $1 -w "$tardir"'
+      am__untar='pax -r'
+      ;;
+    cpio)
+      am__tar='find "$$tardir" -print | cpio -o -H $1 -L'
+      am__tar_='find "$tardir" -print | cpio -o -H $1 -L'
+      am__untar='cpio -i -H $1 -d'
+      ;;
+    none)
+      am__tar=false
+      am__tar_=false
+      am__untar=false
+      ;;
+    esac
+
+    # If the value was cached, stop now.  We just wanted to have am__tar
+    # and am__untar set.
+    test -n "${am_cv_prog_tar_$1}" && break
+
+    # tar/untar a dummy directory, and stop if the command works.
+    rm -rf conftest.dir
+    mkdir conftest.dir
+    echo GrepMe > conftest.dir/file
+    AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar])
+    rm -rf conftest.dir
+    if test -s conftest.tar; then
+      AM_RUN_LOG([$am__untar <conftest.tar])
+      AM_RUN_LOG([cat conftest.dir/file])
+      grep GrepMe conftest.dir/file >/dev/null 2>&1 && break
+    fi
+  done
+  rm -rf conftest.dir
+
+  AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool])
+  AC_MSG_RESULT([$am_cv_prog_tar_$1])])
+
+AC_SUBST([am__tar])
+AC_SUBST([am__untar])
+]) # _AM_PROG_TAR
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/compile
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/compile
@@ -0,0 +1,347 @@
+#! /bin/sh
+# Wrapper for compilers which do not understand '-c -o'.
+
+scriptversion=2012-10-14.11; # UTC
+
+# Copyright (C) 1999-2014 Free Software Foundation, Inc.
+# Written by Tom Tromey <tromey@cygnus.com>.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# As a special exception to the GNU General Public License, if you
+# distribute this file as part of a program that contains a
+# configuration script generated by Autoconf, you may include it under
+# the same distribution terms that you use for the rest of that program.
+
+# This file is maintained in Automake, please report
+# bugs to <bug-automake@gnu.org> or send patches to
+# <automake-patches@gnu.org>.
+
+nl='
+'
+
+# We need space, tab and new line, in precisely that order.  Quoting is
+# there to prevent tools from complaining about whitespace usage.
+IFS=" ""	$nl"
+
+file_conv=
+
+# func_file_conv build_file lazy
+# Convert a $build file to $host form and store it in $file
+# Currently only supports Windows hosts. If the determined conversion
+# type is listed in (the comma separated) LAZY, no conversion will
+# take place.
+func_file_conv ()
+{
+  file=$1
+  case $file in
+    / | /[!/]*) # absolute file, and not a UNC file
+      if test -z "$file_conv"; then
+	# lazily determine how to convert abs files
+	case `uname -s` in
+	  MINGW*)
+	    file_conv=mingw
+	    ;;
+	  CYGWIN*)
+	    file_conv=cygwin
+	    ;;
+	  *)
+	    file_conv=wine
+	    ;;
+	esac
+      fi
+      case $file_conv/,$2, in
+	*,$file_conv,*)
+	  ;;
+	mingw/*)
+	  file=`cmd //C echo "$file " | sed -e 's/"\(.*\) " *$/\1/'`
+	  ;;
+	cygwin/*)
+	  file=`cygpath -m "$file" || echo "$file"`
+	  ;;
+	wine/*)
+	  file=`winepath -w "$file" || echo "$file"`
+	  ;;
+      esac
+      ;;
+  esac
+}
+
+# func_cl_dashL linkdir
+# Make cl look for libraries in LINKDIR
+func_cl_dashL ()
+{
+  func_file_conv "$1"
+  if test -z "$lib_path"; then
+    lib_path=$file
+  else
+    lib_path="$lib_path;$file"
+  fi
+  linker_opts="$linker_opts -LIBPATH:$file"
+}
+
+# func_cl_dashl library
+# Do a library search-path lookup for cl
+func_cl_dashl ()
+{
+  lib=$1
+  found=no
+  save_IFS=$IFS
+  IFS=';'
+  for dir in $lib_path $LIB
+  do
+    IFS=$save_IFS
+    if $shared && test -f "$dir/$lib.dll.lib"; then
+      found=yes
+      lib=$dir/$lib.dll.lib
+      break
+    fi
+    if test -f "$dir/$lib.lib"; then
+      found=yes
+      lib=$dir/$lib.lib
+      break
+    fi
+    if test -f "$dir/lib$lib.a"; then
+      found=yes
+      lib=$dir/lib$lib.a
+      break
+    fi
+  done
+  IFS=$save_IFS
+
+  if test "$found" != yes; then
+    lib=$lib.lib
+  fi
+}
+
+# func_cl_wrapper cl arg...
+# Adjust compile command to suit cl
+func_cl_wrapper ()
+{
+  # Assume a capable shell
+  lib_path=
+  shared=:
+  linker_opts=
+  for arg
+  do
+    if test -n "$eat"; then
+      eat=
+    else
+      case $1 in
+	-o)
+	  # configure might choose to run compile as 'compile cc -o foo foo.c'.
+	  eat=1
+	  case $2 in
+	    *.o | *.[oO][bB][jJ])
+	      func_file_conv "$2"
+	      set x "$@" -Fo"$file"
+	      shift
+	      ;;
+	    *)
+	      func_file_conv "$2"
+	      set x "$@" -Fe"$file"
+	      shift
+	      ;;
+	  esac
+	  ;;
+	-I)
+	  eat=1
+	  func_file_conv "$2" mingw
+	  set x "$@" -I"$file"
+	  shift
+	  ;;
+	-I*)
+	  func_file_conv "${1#-I}" mingw
+	  set x "$@" -I"$file"
+	  shift
+	  ;;
+	-l)
+	  eat=1
+	  func_cl_dashl "$2"
+	  set x "$@" "$lib"
+	  shift
+	  ;;
+	-l*)
+	  func_cl_dashl "${1#-l}"
+	  set x "$@" "$lib"
+	  shift
+	  ;;
+	-L)
+	  eat=1
+	  func_cl_dashL "$2"
+	  ;;
+	-L*)
+	  func_cl_dashL "${1#-L}"
+	  ;;
+	-static)
+	  shared=false
+	  ;;
+	-Wl,*)
+	  arg=${1#-Wl,}
+	  save_ifs="$IFS"; IFS=','
+	  for flag in $arg; do
+	    IFS="$save_ifs"
+	    linker_opts="$linker_opts $flag"
+	  done
+	  IFS="$save_ifs"
+	  ;;
+	-Xlinker)
+	  eat=1
+	  linker_opts="$linker_opts $2"
+	  ;;
+	-*)
+	  set x "$@" "$1"
+	  shift
+	  ;;
+	*.cc | *.CC | *.cxx | *.CXX | *.[cC]++)
+	  func_file_conv "$1"
+	  set x "$@" -Tp"$file"
+	  shift
+	  ;;
+	*.c | *.cpp | *.CPP | *.lib | *.LIB | *.Lib | *.OBJ | *.obj | *.[oO])
+	  func_file_conv "$1" mingw
+	  set x "$@" "$file"
+	  shift
+	  ;;
+	*)
+	  set x "$@" "$1"
+	  shift
+	  ;;
+      esac
+    fi
+    shift
+  done
+  if test -n "$linker_opts"; then
+    linker_opts="-link$linker_opts"
+  fi
+  exec "$@" $linker_opts
+  exit 1
+}
+
+eat=
+
+case $1 in
+  '')
+     echo "$0: No command.  Try '$0 --help' for more information." 1>&2
+     exit 1;
+     ;;
+  -h | --h*)
+    cat <<\EOF
+Usage: compile [--help] [--version] PROGRAM [ARGS]
+
+Wrapper for compilers which do not understand '-c -o'.
+Remove '-o dest.o' from ARGS, run PROGRAM with the remaining
+arguments, and rename the output as expected.
+
+If you are trying to build a whole package this is not the
+right script to run: please start by reading the file 'INSTALL'.
+
+Report bugs to <bug-automake@gnu.org>.
+EOF
+    exit $?
+    ;;
+  -v | --v*)
+    echo "compile $scriptversion"
+    exit $?
+    ;;
+  cl | *[/\\]cl | cl.exe | *[/\\]cl.exe )
+    func_cl_wrapper "$@"      # Doesn't return...
+    ;;
+esac
+
+ofile=
+cfile=
+
+for arg
+do
+  if test -n "$eat"; then
+    eat=
+  else
+    case $1 in
+      -o)
+	# configure might choose to run compile as 'compile cc -o foo foo.c'.
+	# So we strip '-o arg' only if arg is an object.
+	eat=1
+	case $2 in
+	  *.o | *.obj)
+	    ofile=$2
+	    ;;
+	  *)
+	    set x "$@" -o "$2"
+	    shift
+	    ;;
+	esac
+	;;
+      *.c)
+	cfile=$1
+	set x "$@" "$1"
+	shift
+	;;
+      *)
+	set x "$@" "$1"
+	shift
+	;;
+    esac
+  fi
+  shift
+done
+
+if test -z "$ofile" || test -z "$cfile"; then
+  # If no '-o' option was seen then we might have been invoked from a
+  # pattern rule where we don't need one.  That is ok -- this is a
+  # normal compilation that the losing compiler can handle.  If no
+  # '.c' file was seen then we are probably linking.  That is also
+  # ok.
+  exec "$@"
+fi
+
+# Name of file we expect compiler to create.
+cofile=`echo "$cfile" | sed 's|^.*[\\/]||; s|^[a-zA-Z]:||; s/\.c$/.o/'`
+
+# Create the lock directory.
+# Note: use '[/\\:.-]' here to ensure that we don't use the same name
+# that we are using for the .o file.  Also, base the name on the expected
+# object file name, since that is what matters with a parallel build.
+lockdir=`echo "$cofile" | sed -e 's|[/\\:.-]|_|g'`.d
+while true; do
+  if mkdir "$lockdir" >/dev/null 2>&1; then
+    break
+  fi
+  sleep 1
+done
+# FIXME: race condition here if user kills between mkdir and trap.
+trap "rmdir '$lockdir'; exit 1" 1 2 15
+
+# Run the compile.
+"$@"
+ret=$?
+
+if test -f "$cofile"; then
+  test "$cofile" = "$ofile" || mv "$cofile" "$ofile"
+elif test -f "${cofile}bj"; then
+  test "${cofile}bj" = "$ofile" || mv "${cofile}bj" "$ofile"
+fi
+
+rmdir "$lockdir"
+exit $ret
+
+# Local Variables:
+# mode: shell-script
+# sh-indentation: 2
+# eval: (add-hook 'write-file-hooks 'time-stamp)
+# time-stamp-start: "scriptversion="
+# time-stamp-format: "%:y-%02m-%02d.%02H"
+# time-stamp-time-zone: "UTC"
+# time-stamp-end: "; # UTC"
+# End:
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/config.guess
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/config.guess
@@ -0,0 +1,1462 @@
+#! /bin/sh
+# Attempt to guess a canonical system name.
+#   Copyright 1992-2016 Free Software Foundation, Inc.
+
+timestamp='2016-10-02'
+
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, see <http://www.gnu.org/licenses/>.
+#
+# As a special exception to the GNU General Public License, if you
+# distribute this file as part of a program that contains a
+# configuration script generated by Autoconf, you may include it under
+# the same distribution terms that you use for the rest of that
+# program.  This Exception is an additional permission under section 7
+# of the GNU General Public License, version 3 ("GPLv3").
+#
+# Originally written by Per Bothner; maintained since 2000 by Ben Elliston.
+#
+# You can get the latest version of this script from:
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess
+#
+# Please send patches to <config-patches@gnu.org>.
+
+
+me=`echo "$0" | sed -e 's,.*/,,'`
+
+usage="\
+Usage: $0 [OPTION]
+
+Output the configuration name of the system \`$me' is run on.
+
+Operation modes:
+  -h, --help         print this help, then exit
+  -t, --time-stamp   print date of last modification, then exit
+  -v, --version      print version number, then exit
+
+Report bugs and patches to <config-patches@gnu.org>."
+
+version="\
+GNU config.guess ($timestamp)
+
+Originally written by Per Bothner.
+Copyright 1992-2016 Free Software Foundation, Inc.
+
+This is free software; see the source for copying conditions.  There is NO
+warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
+
+help="
+Try \`$me --help' for more information."
+
+# Parse command line
+while test $# -gt 0 ; do
+  case $1 in
+    --time-stamp | --time* | -t )
+       echo "$timestamp" ; exit ;;
+    --version | -v )
+       echo "$version" ; exit ;;
+    --help | --h* | -h )
+       echo "$usage"; exit ;;
+    -- )     # Stop option processing
+       shift; break ;;
+    - )	# Use stdin as input.
+       break ;;
+    -* )
+       echo "$me: invalid option $1$help" >&2
+       exit 1 ;;
+    * )
+       break ;;
+  esac
+done
+
+if test $# != 0; then
+  echo "$me: too many arguments$help" >&2
+  exit 1
+fi
+
+trap 'exit 1' 1 2 15
+
+# CC_FOR_BUILD -- compiler used by this script. Note that the use of a
+# compiler to aid in system detection is discouraged as it requires
+# temporary files to be created and, as you can see below, it is a
+# headache to deal with in a portable fashion.
+
+# Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still
+# use `HOST_CC' if defined, but it is deprecated.
+
+# Portable tmp directory creation inspired by the Autoconf team.
+
+set_cc_for_build='
+trap "exitcode=\$?; (rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null) && exit \$exitcode" 0 ;
+trap "rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null; exit 1" 1 2 13 15 ;
+: ${TMPDIR=/tmp} ;
+ { tmp=`(umask 077 && mktemp -d "$TMPDIR/cgXXXXXX") 2>/dev/null` && test -n "$tmp" && test -d "$tmp" ; } ||
+ { test -n "$RANDOM" && tmp=$TMPDIR/cg$$-$RANDOM && (umask 077 && mkdir $tmp) ; } ||
+ { tmp=$TMPDIR/cg-$$ && (umask 077 && mkdir $tmp) && echo "Warning: creating insecure temp directory" >&2 ; } ||
+ { echo "$me: cannot create a temporary directory in $TMPDIR" >&2 ; exit 1 ; } ;
+dummy=$tmp/dummy ;
+tmpfiles="$dummy.c $dummy.o $dummy.rel $dummy" ;
+case $CC_FOR_BUILD,$HOST_CC,$CC in
+ ,,)    echo "int x;" > $dummy.c ;
+	for c in cc gcc c89 c99 ; do
+	  if ($c -c -o $dummy.o $dummy.c) >/dev/null 2>&1 ; then
+	     CC_FOR_BUILD="$c"; break ;
+	  fi ;
+	done ;
+	if test x"$CC_FOR_BUILD" = x ; then
+	  CC_FOR_BUILD=no_compiler_found ;
+	fi
+	;;
+ ,,*)   CC_FOR_BUILD=$CC ;;
+ ,*,*)  CC_FOR_BUILD=$HOST_CC ;;
+esac ; set_cc_for_build= ;'
+
+# This is needed to find uname on a Pyramid OSx when run in the BSD universe.
+# (ghazi@noc.rutgers.edu 1994-08-24)
+if (test -f /.attbin/uname) >/dev/null 2>&1 ; then
+	PATH=$PATH:/.attbin ; export PATH
+fi
+
+UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown
+UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown
+UNAME_SYSTEM=`(uname -s) 2>/dev/null`  || UNAME_SYSTEM=unknown
+UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown
+
+case "${UNAME_SYSTEM}" in
+Linux|GNU|GNU/*)
+	# If the system lacks a compiler, then just pick glibc.
+	# We could probably try harder.
+	LIBC=gnu
+
+	eval $set_cc_for_build
+	cat <<-EOF > $dummy.c
+	#include <features.h>
+	#if defined(__UCLIBC__)
+	LIBC=uclibc
+	#elif defined(__dietlibc__)
+	LIBC=dietlibc
+	#else
+	LIBC=gnu
+	#endif
+	EOF
+	eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC' | sed 's, ,,g'`
+	;;
+esac
+
+# Note: order is significant - the case branches are not exclusive.
+
+case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
+    *:NetBSD:*:*)
+	# NetBSD (nbsd) targets should (where applicable) match one or
+	# more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*,
+	# *-*-netbsdecoff* and *-*-netbsd*.  For targets that recently
+	# switched to ELF, *-*-netbsd* would select the old
+	# object file format.  This provides both forward
+	# compatibility and a consistent mechanism for selecting the
+	# object file format.
+	#
+	# Note: NetBSD doesn't particularly care about the vendor
+	# portion of the name.  We always set it to "unknown".
+	sysctl="sysctl -n hw.machine_arch"
+	UNAME_MACHINE_ARCH=`(uname -p 2>/dev/null || \
+	    /sbin/$sysctl 2>/dev/null || \
+	    /usr/sbin/$sysctl 2>/dev/null || \
+	    echo unknown)`
+	case "${UNAME_MACHINE_ARCH}" in
+	    armeb) machine=armeb-unknown ;;
+	    arm*) machine=arm-unknown ;;
+	    sh3el) machine=shl-unknown ;;
+	    sh3eb) machine=sh-unknown ;;
+	    sh5el) machine=sh5le-unknown ;;
+	    earmv*)
+		arch=`echo ${UNAME_MACHINE_ARCH} | sed -e 's,^e\(armv[0-9]\).*$,\1,'`
+		endian=`echo ${UNAME_MACHINE_ARCH} | sed -ne 's,^.*\(eb\)$,\1,p'`
+		machine=${arch}${endian}-unknown
+		;;
+	    *) machine=${UNAME_MACHINE_ARCH}-unknown ;;
+	esac
+	# The Operating System including object format, if it has switched
+	# to ELF recently (or will in the future) and ABI.
+	case "${UNAME_MACHINE_ARCH}" in
+	    earm*)
+		os=netbsdelf
+		;;
+	    arm*|i386|m68k|ns32k|sh3*|sparc|vax)
+		eval $set_cc_for_build
+		if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \
+			| grep -q __ELF__
+		then
+		    # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout).
+		    # Return netbsd for either.  FIX?
+		    os=netbsd
+		else
+		    os=netbsdelf
+		fi
+		;;
+	    *)
+		os=netbsd
+		;;
+	esac
+	# Determine ABI tags.
+	case "${UNAME_MACHINE_ARCH}" in
+	    earm*)
+		expr='s/^earmv[0-9]/-eabi/;s/eb$//'
+		abi=`echo ${UNAME_MACHINE_ARCH} | sed -e "$expr"`
+		;;
+	esac
+	# The OS release
+	# Debian GNU/NetBSD machines have a different userland, and
+	# thus, need a distinct triplet. However, they do not need
+	# kernel version information, so it can be replaced with a
+	# suitable tag, in the style of linux-gnu.
+	case "${UNAME_VERSION}" in
+	    Debian*)
+		release='-gnu'
+		;;
+	    *)
+		release=`echo ${UNAME_RELEASE} | sed -e 's/[-_].*//' | cut -d. -f1,2`
+		;;
+	esac
+	# Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM:
+	# contains redundant information, the shorter form:
+	# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used.
+	echo "${machine}-${os}${release}${abi}"
+	exit ;;
+    *:Bitrig:*:*)
+	UNAME_MACHINE_ARCH=`arch | sed 's/Bitrig.//'`
+	echo ${UNAME_MACHINE_ARCH}-unknown-bitrig${UNAME_RELEASE}
+	exit ;;
+    *:OpenBSD:*:*)
+	UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'`
+	echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE}
+	exit ;;
+    *:LibertyBSD:*:*)
+	UNAME_MACHINE_ARCH=`arch | sed 's/^.*BSD\.//'`
+	echo ${UNAME_MACHINE_ARCH}-unknown-libertybsd${UNAME_RELEASE}
+	exit ;;
+    *:ekkoBSD:*:*)
+	echo ${UNAME_MACHINE}-unknown-ekkobsd${UNAME_RELEASE}
+	exit ;;
+    *:SolidBSD:*:*)
+	echo ${UNAME_MACHINE}-unknown-solidbsd${UNAME_RELEASE}
+	exit ;;
+    macppc:MirBSD:*:*)
+	echo powerpc-unknown-mirbsd${UNAME_RELEASE}
+	exit ;;
+    *:MirBSD:*:*)
+	echo ${UNAME_MACHINE}-unknown-mirbsd${UNAME_RELEASE}
+	exit ;;
+    *:Sortix:*:*)
+	echo ${UNAME_MACHINE}-unknown-sortix
+	exit ;;
+    alpha:OSF1:*:*)
+	case $UNAME_RELEASE in
+	*4.0)
+		UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'`
+		;;
+	*5.*)
+		UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'`
+		;;
+	esac
+	# According to Compaq, /usr/sbin/psrinfo has been available on
+	# OSF/1 and Tru64 systems produced since 1995.  I hope that
+	# covers most systems running today.  This code pipes the CPU
+	# types through head -n 1, so we only detect the type of CPU 0.
+	ALPHA_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^  The alpha \(.*\) processor.*$/\1/p' | head -n 1`
+	case "$ALPHA_CPU_TYPE" in
+	    "EV4 (21064)")
+		UNAME_MACHINE=alpha ;;
+	    "EV4.5 (21064)")
+		UNAME_MACHINE=alpha ;;
+	    "LCA4 (21066/21068)")
+		UNAME_MACHINE=alpha ;;
+	    "EV5 (21164)")
+		UNAME_MACHINE=alphaev5 ;;
+	    "EV5.6 (21164A)")
+		UNAME_MACHINE=alphaev56 ;;
+	    "EV5.6 (21164PC)")
+		UNAME_MACHINE=alphapca56 ;;
+	    "EV5.7 (21164PC)")
+		UNAME_MACHINE=alphapca57 ;;
+	    "EV6 (21264)")
+		UNAME_MACHINE=alphaev6 ;;
+	    "EV6.7 (21264A)")
+		UNAME_MACHINE=alphaev67 ;;
+	    "EV6.8CB (21264C)")
+		UNAME_MACHINE=alphaev68 ;;
+	    "EV6.8AL (21264B)")
+		UNAME_MACHINE=alphaev68 ;;
+	    "EV6.8CX (21264D)")
+		UNAME_MACHINE=alphaev68 ;;
+	    "EV6.9A (21264/EV69A)")
+		UNAME_MACHINE=alphaev69 ;;
+	    "EV7 (21364)")
+		UNAME_MACHINE=alphaev7 ;;
+	    "EV7.9 (21364A)")
+		UNAME_MACHINE=alphaev79 ;;
+	esac
+	# A Pn.n version is a patched version.
+	# A Vn.n version is a released version.
+	# A Tn.n version is a released field test version.
+	# A Xn.n version is an unreleased experimental baselevel.
+	# 1.2 uses "1.2" for uname -r.
+	echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz`
+	# Reset EXIT trap before exiting to avoid spurious non-zero exit code.
+	exitcode=$?
+	trap '' 0
+	exit $exitcode ;;
+    Alpha\ *:Windows_NT*:*)
+	# How do we know it's Interix rather than the generic POSIX subsystem?
+	# Should we change UNAME_MACHINE based on the output of uname instead
+	# of the specific Alpha model?
+	echo alpha-pc-interix
+	exit ;;
+    21064:Windows_NT:50:3)
+	echo alpha-dec-winnt3.5
+	exit ;;
+    Amiga*:UNIX_System_V:4.0:*)
+	echo m68k-unknown-sysv4
+	exit ;;
+    *:[Aa]miga[Oo][Ss]:*:*)
+	echo ${UNAME_MACHINE}-unknown-amigaos
+	exit ;;
+    *:[Mm]orph[Oo][Ss]:*:*)
+	echo ${UNAME_MACHINE}-unknown-morphos
+	exit ;;
+    *:OS/390:*:*)
+	echo i370-ibm-openedition
+	exit ;;
+    *:z/VM:*:*)
+	echo s390-ibm-zvmoe
+	exit ;;
+    *:OS400:*:*)
+	echo powerpc-ibm-os400
+	exit ;;
+    arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*)
+	echo arm-acorn-riscix${UNAME_RELEASE}
+	exit ;;
+    arm*:riscos:*:*|arm*:RISCOS:*:*)
+	echo arm-unknown-riscos
+	exit ;;
+    SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*)
+	echo hppa1.1-hitachi-hiuxmpp
+	exit ;;
+    Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*)
+	# akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE.
+	if test "`(/bin/universe) 2>/dev/null`" = att ; then
+		echo pyramid-pyramid-sysv3
+	else
+		echo pyramid-pyramid-bsd
+	fi
+	exit ;;
+    NILE*:*:*:dcosx)
+	echo pyramid-pyramid-svr4
+	exit ;;
+    DRS?6000:unix:4.0:6*)
+	echo sparc-icl-nx6
+	exit ;;
+    DRS?6000:UNIX_SV:4.2*:7* | DRS?6000:isis:4.2*:7*)
+	case `/usr/bin/uname -p` in
+	    sparc) echo sparc-icl-nx7; exit ;;
+	esac ;;
+    s390x:SunOS:*:*)
+	echo ${UNAME_MACHINE}-ibm-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+	exit ;;
+    sun4H:SunOS:5.*:*)
+	echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+	exit ;;
+    sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*)
+	echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+	exit ;;
+    i86pc:AuroraUX:5.*:* | i86xen:AuroraUX:5.*:*)
+	echo i386-pc-auroraux${UNAME_RELEASE}
+	exit ;;
+    i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*)
+	eval $set_cc_for_build
+	SUN_ARCH=i386
+	# If there is a compiler, see if it is configured for 64-bit objects.
+	# Note that the Sun cc does not turn __LP64__ into 1 like gcc does.
+	# This test works for both compilers.
+	if [ "$CC_FOR_BUILD" != no_compiler_found ]; then
+	    if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \
+		(CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \
+		grep IS_64BIT_ARCH >/dev/null
+	    then
+		SUN_ARCH=x86_64
+	    fi
+	fi
+	echo ${SUN_ARCH}-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+	exit ;;
+    sun4*:SunOS:6*:*)
+	# According to config.sub, this is the proper way to canonicalize
+	# SunOS6.  Hard to guess exactly what SunOS6 will be like, but
+	# it's likely to be more like Solaris than SunOS4.
+	echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+	exit ;;
+    sun4*:SunOS:*:*)
+	case "`/usr/bin/arch -k`" in
+	    Series*|S4*)
+		UNAME_RELEASE=`uname -v`
+		;;
+	esac
+	# Japanese Language versions have a version number like `4.1.3-JL'.
+	echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'`
+	exit ;;
+    sun3*:SunOS:*:*)
+	echo m68k-sun-sunos${UNAME_RELEASE}
+	exit ;;
+    sun*:*:4.2BSD:*)
+	UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null`
+	test "x${UNAME_RELEASE}" = x && UNAME_RELEASE=3
+	case "`/bin/arch`" in
+	    sun3)
+		echo m68k-sun-sunos${UNAME_RELEASE}
+		;;
+	    sun4)
+		echo sparc-sun-sunos${UNAME_RELEASE}
+		;;
+	esac
+	exit ;;
+    aushp:SunOS:*:*)
+	echo sparc-auspex-sunos${UNAME_RELEASE}
+	exit ;;
+    # The situation for MiNT is a little confusing.  The machine name
+    # can be virtually everything (everything which is not
+    # "atarist" or "atariste" at least should have a processor
+    # > m68000).  The system name ranges from "MiNT" over "FreeMiNT"
+    # to the lowercase version "mint" (or "freemint").  Finally
+    # the system name "TOS" denotes a system which is actually not
+    # MiNT.  But MiNT is downward compatible to TOS, so this should
+    # be no problem.
+    atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*)
+	echo m68k-atari-mint${UNAME_RELEASE}
+	exit ;;
+    atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*)
+	echo m68k-atari-mint${UNAME_RELEASE}
+	exit ;;
+    *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*)
+	echo m68k-atari-mint${UNAME_RELEASE}
+	exit ;;
+    milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*)
+	echo m68k-milan-mint${UNAME_RELEASE}
+	exit ;;
+    hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*)
+	echo m68k-hades-mint${UNAME_RELEASE}
+	exit ;;
+    *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*)
+	echo m68k-unknown-mint${UNAME_RELEASE}
+	exit ;;
+    m68k:machten:*:*)
+	echo m68k-apple-machten${UNAME_RELEASE}
+	exit ;;
+    powerpc:machten:*:*)
+	echo powerpc-apple-machten${UNAME_RELEASE}
+	exit ;;
+    RISC*:Mach:*:*)
+	echo mips-dec-mach_bsd4.3
+	exit ;;
+    RISC*:ULTRIX:*:*)
+	echo mips-dec-ultrix${UNAME_RELEASE}
+	exit ;;
+    VAX*:ULTRIX*:*:*)
+	echo vax-dec-ultrix${UNAME_RELEASE}
+	exit ;;
+    2020:CLIX:*:* | 2430:CLIX:*:*)
+	echo clipper-intergraph-clix${UNAME_RELEASE}
+	exit ;;
+    mips:*:*:UMIPS | mips:*:*:RISCos)
+	eval $set_cc_for_build
+	sed 's/^	//' << EOF >$dummy.c
+#ifdef __cplusplus
+#include <stdio.h>  /* for printf() prototype */
+	int main (int argc, char *argv[]) {
+#else
+	int main (argc, argv) int argc; char *argv[]; {
+#endif
+	#if defined (host_mips) && defined (MIPSEB)
+	#if defined (SYSTYPE_SYSV)
+	  printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0);
+	#endif
+	#if defined (SYSTYPE_SVR4)
+	  printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0);
+	#endif
+	#if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD)
+	  printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0);
+	#endif
+	#endif
+	  exit (-1);
+	}
+EOF
+	$CC_FOR_BUILD -o $dummy $dummy.c &&
+	  dummyarg=`echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` &&
+	  SYSTEM_NAME=`$dummy $dummyarg` &&
+	    { echo "$SYSTEM_NAME"; exit; }
+	echo mips-mips-riscos${UNAME_RELEASE}
+	exit ;;
+    Motorola:PowerMAX_OS:*:*)
+	echo powerpc-motorola-powermax
+	exit ;;
+    Motorola:*:4.3:PL8-*)
+	echo powerpc-harris-powermax
+	exit ;;
+    Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*)
+	echo powerpc-harris-powermax
+	exit ;;
+    Night_Hawk:Power_UNIX:*:*)
+	echo powerpc-harris-powerunix
+	exit ;;
+    m88k:CX/UX:7*:*)
+	echo m88k-harris-cxux7
+	exit ;;
+    m88k:*:4*:R4*)
+	echo m88k-motorola-sysv4
+	exit ;;
+    m88k:*:3*:R3*)
+	echo m88k-motorola-sysv3
+	exit ;;
+    AViiON:dgux:*:*)
+	# DG/UX returns AViiON for all architectures
+	UNAME_PROCESSOR=`/usr/bin/uname -p`
+	if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ]
+	then
+	    if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \
+	       [ ${TARGET_BINARY_INTERFACE}x = x ]
+	    then
+		echo m88k-dg-dgux${UNAME_RELEASE}
+	    else
+		echo m88k-dg-dguxbcs${UNAME_RELEASE}
+	    fi
+	else
+	    echo i586-dg-dgux${UNAME_RELEASE}
+	fi
+	exit ;;
+    M88*:DolphinOS:*:*)	# DolphinOS (SVR3)
+	echo m88k-dolphin-sysv3
+	exit ;;
+    M88*:*:R3*:*)
+	# Delta 88k system running SVR3
+	echo m88k-motorola-sysv3
+	exit ;;
+    XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3)
+	echo m88k-tektronix-sysv3
+	exit ;;
+    Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD)
+	echo m68k-tektronix-bsd
+	exit ;;
+    *:IRIX*:*:*)
+	echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'`
+	exit ;;
+    ????????:AIX?:[12].1:2)   # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX.
+	echo romp-ibm-aix     # uname -m gives an 8 hex-code CPU id
+	exit ;;               # Note that: echo "'`uname -s`'" gives 'AIX '
+    i*86:AIX:*:*)
+	echo i386-ibm-aix
+	exit ;;
+    ia64:AIX:*:*)
+	if [ -x /usr/bin/oslevel ] ; then
+		IBM_REV=`/usr/bin/oslevel`
+	else
+		IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE}
+	fi
+	echo ${UNAME_MACHINE}-ibm-aix${IBM_REV}
+	exit ;;
+    *:AIX:2:3)
+	if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then
+		eval $set_cc_for_build
+		sed 's/^		//' << EOF >$dummy.c
+		#include <sys/systemcfg.h>
+
+		main()
+			{
+			if (!__power_pc())
+				exit(1);
+			puts("powerpc-ibm-aix3.2.5");
+			exit(0);
+			}
+EOF
+		if $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy`
+		then
+			echo "$SYSTEM_NAME"
+		else
+			echo rs6000-ibm-aix3.2.5
+		fi
+	elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then
+		echo rs6000-ibm-aix3.2.4
+	else
+		echo rs6000-ibm-aix3.2
+	fi
+	exit ;;
+    *:AIX:*:[4567])
+	IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'`
+	if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then
+		IBM_ARCH=rs6000
+	else
+		IBM_ARCH=powerpc
+	fi
+	if [ -x /usr/bin/lslpp ] ; then
+		IBM_REV=`/usr/bin/lslpp -Lqc bos.rte.libc |
+			   awk -F: '{ print $3 }' | sed s/[0-9]*$/0/`
+	else
+		IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE}
+	fi
+	echo ${IBM_ARCH}-ibm-aix${IBM_REV}
+	exit ;;
+    *:AIX:*:*)
+	echo rs6000-ibm-aix
+	exit ;;
+    ibmrt:4.4BSD:*|romp-ibm:BSD:*)
+	echo romp-ibm-bsd4.4
+	exit ;;
+    ibmrt:*BSD:*|romp-ibm:BSD:*)            # covers RT/PC BSD and
+	echo romp-ibm-bsd${UNAME_RELEASE}   # 4.3 with uname added to
+	exit ;;                             # report: romp-ibm BSD 4.3
+    *:BOSX:*:*)
+	echo rs6000-bull-bosx
+	exit ;;
+    DPX/2?00:B.O.S.:*:*)
+	echo m68k-bull-sysv3
+	exit ;;
+    9000/[34]??:4.3bsd:1.*:*)
+	echo m68k-hp-bsd
+	exit ;;
+    hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*)
+	echo m68k-hp-bsd4.4
+	exit ;;
+    9000/[34678]??:HP-UX:*:*)
+	HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'`
+	case "${UNAME_MACHINE}" in
+	    9000/31? )            HP_ARCH=m68000 ;;
+	    9000/[34]?? )         HP_ARCH=m68k ;;
+	    9000/[678][0-9][0-9])
+		if [ -x /usr/bin/getconf ]; then
+		    sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null`
+		    sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null`
+		    case "${sc_cpu_version}" in
+		      523) HP_ARCH=hppa1.0 ;; # CPU_PA_RISC1_0
+		      528) HP_ARCH=hppa1.1 ;; # CPU_PA_RISC1_1
+		      532)                      # CPU_PA_RISC2_0
+			case "${sc_kernel_bits}" in
+			  32) HP_ARCH=hppa2.0n ;;
+			  64) HP_ARCH=hppa2.0w ;;
+			  '') HP_ARCH=hppa2.0 ;;   # HP-UX 10.20
+			esac ;;
+		    esac
+		fi
+		if [ "${HP_ARCH}" = "" ]; then
+		    eval $set_cc_for_build
+		    sed 's/^		//' << EOF >$dummy.c
+
+		#define _HPUX_SOURCE
+		#include <stdlib.h>
+		#include <unistd.h>
+
+		int main ()
+		{
+		#if defined(_SC_KERNEL_BITS)
+		    long bits = sysconf(_SC_KERNEL_BITS);
+		#endif
+		    long cpu  = sysconf (_SC_CPU_VERSION);
+
+		    switch (cpu)
+			{
+			case CPU_PA_RISC1_0: puts ("hppa1.0"); break;
+			case CPU_PA_RISC1_1: puts ("hppa1.1"); break;
+			case CPU_PA_RISC2_0:
+		#if defined(_SC_KERNEL_BITS)
+			    switch (bits)
+				{
+				case 64: puts ("hppa2.0w"); break;
+				case 32: puts ("hppa2.0n"); break;
+				default: puts ("hppa2.0"); break;
+				} break;
+		#else  /* !defined(_SC_KERNEL_BITS) */
+			    puts ("hppa2.0"); break;
+		#endif
+			default: puts ("hppa1.0"); break;
+			}
+		    exit (0);
+		}
+EOF
+		    (CCOPTS="" $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy`
+		    test -z "$HP_ARCH" && HP_ARCH=hppa
+		fi ;;
+	esac
+	if [ ${HP_ARCH} = hppa2.0w ]
+	then
+	    eval $set_cc_for_build
+
+	    # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating
+	    # 32-bit code.  hppa64-hp-hpux* has the same kernel and a compiler
+	    # generating 64-bit code.  GNU and HP use different nomenclature:
+	    #
+	    # $ CC_FOR_BUILD=cc ./config.guess
+	    # => hppa2.0w-hp-hpux11.23
+	    # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess
+	    # => hppa64-hp-hpux11.23
+
+	    if echo __LP64__ | (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) |
+		grep -q __LP64__
+	    then
+		HP_ARCH=hppa2.0w
+	    else
+		HP_ARCH=hppa64
+	    fi
+	fi
+	echo ${HP_ARCH}-hp-hpux${HPUX_REV}
+	exit ;;
+    ia64:HP-UX:*:*)
+	HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'`
+	echo ia64-hp-hpux${HPUX_REV}
+	exit ;;
+    3050*:HI-UX:*:*)
+	eval $set_cc_for_build
+	sed 's/^	//' << EOF >$dummy.c
+	#include <unistd.h>
+	int
+	main ()
+	{
+	  long cpu = sysconf (_SC_CPU_VERSION);
+	  /* The order matters, because CPU_IS_HP_MC68K erroneously returns
+	     true for CPU_PA_RISC1_0.  CPU_IS_PA_RISC returns correct
+	     results, however.  */
+	  if (CPU_IS_PA_RISC (cpu))
+	    {
+	      switch (cpu)
+		{
+		  case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break;
+		  case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break;
+		  case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break;
+		  default: puts ("hppa-hitachi-hiuxwe2"); break;
+		}
+	    }
+	  else if (CPU_IS_HP_MC68K (cpu))
+	    puts ("m68k-hitachi-hiuxwe2");
+	  else puts ("unknown-hitachi-hiuxwe2");
+	  exit (0);
+	}
+EOF
+	$CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` &&
+		{ echo "$SYSTEM_NAME"; exit; }
+	echo unknown-hitachi-hiuxwe2
+	exit ;;
+    9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* )
+	echo hppa1.1-hp-bsd
+	exit ;;
+    9000/8??:4.3bsd:*:*)
+	echo hppa1.0-hp-bsd
+	exit ;;
+    *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*)
+	echo hppa1.0-hp-mpeix
+	exit ;;
+    hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* )
+	echo hppa1.1-hp-osf
+	exit ;;
+    hp8??:OSF1:*:*)
+	echo hppa1.0-hp-osf
+	exit ;;
+    i*86:OSF1:*:*)
+	if [ -x /usr/sbin/sysversion ] ; then
+	    echo ${UNAME_MACHINE}-unknown-osf1mk
+	else
+	    echo ${UNAME_MACHINE}-unknown-osf1
+	fi
+	exit ;;
+    parisc*:Lites*:*:*)
+	echo hppa1.1-hp-lites
+	exit ;;
+    C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*)
+	echo c1-convex-bsd
+	exit ;;
+    C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*)
+	if getsysinfo -f scalar_acc
+	then echo c32-convex-bsd
+	else echo c2-convex-bsd
+	fi
+	exit ;;
+    C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*)
+	echo c34-convex-bsd
+	exit ;;
+    C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*)
+	echo c38-convex-bsd
+	exit ;;
+    C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*)
+	echo c4-convex-bsd
+	exit ;;
+    CRAY*Y-MP:*:*:*)
+	echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
+	exit ;;
+    CRAY*[A-Z]90:*:*:*)
+	echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \
+	| sed -e 's/CRAY.*\([A-Z]90\)/\1/' \
+	      -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \
+	      -e 's/\.[^.]*$/.X/'
+	exit ;;
+    CRAY*TS:*:*:*)
+	echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
+	exit ;;
+    CRAY*T3E:*:*:*)
+	echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
+	exit ;;
+    CRAY*SV1:*:*:*)
+	echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
+	exit ;;
+    *:UNICOS/mp:*:*)
+	echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
+	exit ;;
+    F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*)
+	FUJITSU_PROC=`uname -m | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz`
+	FUJITSU_SYS=`uname -p | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/\///'`
+	FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'`
+	echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
+	exit ;;
+    5000:UNIX_System_V:4.*:*)
+	FUJITSU_SYS=`uname -p | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/\///'`
+	FUJITSU_REL=`echo ${UNAME_RELEASE} | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/ /_/'`
+	echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
+	exit ;;
+    i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*)
+	echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE}
+	exit ;;
+    sparc*:BSD/OS:*:*)
+	echo sparc-unknown-bsdi${UNAME_RELEASE}
+	exit ;;
+    *:BSD/OS:*:*)
+	echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE}
+	exit ;;
+    *:FreeBSD:*:*)
+	UNAME_PROCESSOR=`/usr/bin/uname -p`
+	case ${UNAME_PROCESSOR} in
+	    amd64)
+		echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
+	    *)
+		echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
+	esac
+	exit ;;
+    i*:CYGWIN*:*)
+	echo ${UNAME_MACHINE}-pc-cygwin
+	exit ;;
+    *:MINGW64*:*)
+	echo ${UNAME_MACHINE}-pc-mingw64
+	exit ;;
+    *:MINGW*:*)
+	echo ${UNAME_MACHINE}-pc-mingw32
+	exit ;;
+    *:MSYS*:*)
+	echo ${UNAME_MACHINE}-pc-msys
+	exit ;;
+    i*:windows32*:*)
+	# uname -m includes "-pc" on this system.
+	echo ${UNAME_MACHINE}-mingw32
+	exit ;;
+    i*:PW*:*)
+	echo ${UNAME_MACHINE}-pc-pw32
+	exit ;;
+    *:Interix*:*)
+	case ${UNAME_MACHINE} in
+	    x86)
+		echo i586-pc-interix${UNAME_RELEASE}
+		exit ;;
+	    authenticamd | genuineintel | EM64T)
+		echo x86_64-unknown-interix${UNAME_RELEASE}
+		exit ;;
+	    IA64)
+		echo ia64-unknown-interix${UNAME_RELEASE}
+		exit ;;
+	esac ;;
+    [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*)
+	echo i${UNAME_MACHINE}-pc-mks
+	exit ;;
+    8664:Windows_NT:*)
+	echo x86_64-pc-mks
+	exit ;;
+    i*:Windows_NT*:* | Pentium*:Windows_NT*:*)
+	# How do we know it's Interix rather than the generic POSIX subsystem?
+	# It also conflicts with pre-2.0 versions of AT&T UWIN. Should we
+	# UNAME_MACHINE based on the output of uname instead of i386?
+	echo i586-pc-interix
+	exit ;;
+    i*:UWIN*:*)
+	echo ${UNAME_MACHINE}-pc-uwin
+	exit ;;
+    amd64:CYGWIN*:*:* | x86_64:CYGWIN*:*:*)
+	echo x86_64-unknown-cygwin
+	exit ;;
+    p*:CYGWIN*:*)
+	echo powerpcle-unknown-cygwin
+	exit ;;
+    prep*:SunOS:5.*:*)
+	echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+	exit ;;
+    *:GNU:*:*)
+	# the GNU system
+	echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`
+	exit ;;
+    *:GNU/*:*:*)
+	# other systems with GNU libc and userland
+	echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr "[:upper:]" "[:lower:]"``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC}
+	exit ;;
+    i*86:Minix:*:*)
+	echo ${UNAME_MACHINE}-pc-minix
+	exit ;;
+    aarch64:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    aarch64_be:Linux:*:*)
+	UNAME_MACHINE=aarch64_be
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    alpha:Linux:*:*)
+	case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
+	  EV5)   UNAME_MACHINE=alphaev5 ;;
+	  EV56)  UNAME_MACHINE=alphaev56 ;;
+	  PCA56) UNAME_MACHINE=alphapca56 ;;
+	  PCA57) UNAME_MACHINE=alphapca56 ;;
+	  EV6)   UNAME_MACHINE=alphaev6 ;;
+	  EV67)  UNAME_MACHINE=alphaev67 ;;
+	  EV68*) UNAME_MACHINE=alphaev68 ;;
+	esac
+	objdump --private-headers /bin/sh | grep -q ld.so.1
+	if test "$?" = 0 ; then LIBC=gnulibc1 ; fi
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    arc:Linux:*:* | arceb:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    arm*:Linux:*:*)
+	eval $set_cc_for_build
+	if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \
+	    | grep -q __ARM_EABI__
+	then
+	    echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	else
+	    if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \
+		| grep -q __ARM_PCS_VFP
+	    then
+		echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi
+	    else
+		echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf
+	    fi
+	fi
+	exit ;;
+    avr32*:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    cris:Linux:*:*)
+	echo ${UNAME_MACHINE}-axis-linux-${LIBC}
+	exit ;;
+    crisv32:Linux:*:*)
+	echo ${UNAME_MACHINE}-axis-linux-${LIBC}
+	exit ;;
+    e2k:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    frv:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    hexagon:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    i*86:Linux:*:*)
+	echo ${UNAME_MACHINE}-pc-linux-${LIBC}
+	exit ;;
+    ia64:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    k1om:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    m32r*:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    m68*:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    mips:Linux:*:* | mips64:Linux:*:*)
+	eval $set_cc_for_build
+	sed 's/^	//' << EOF >$dummy.c
+	#undef CPU
+	#undef ${UNAME_MACHINE}
+	#undef ${UNAME_MACHINE}el
+	#if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL)
+	CPU=${UNAME_MACHINE}el
+	#else
+	#if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB)
+	CPU=${UNAME_MACHINE}
+	#else
+	CPU=
+	#endif
+	#endif
+EOF
+	eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'`
+	test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; }
+	;;
+    mips64el:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    openrisc*:Linux:*:*)
+	echo or1k-unknown-linux-${LIBC}
+	exit ;;
+    or32:Linux:*:* | or1k*:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    padre:Linux:*:*)
+	echo sparc-unknown-linux-${LIBC}
+	exit ;;
+    parisc64:Linux:*:* | hppa64:Linux:*:*)
+	echo hppa64-unknown-linux-${LIBC}
+	exit ;;
+    parisc:Linux:*:* | hppa:Linux:*:*)
+	# Look for CPU level
+	case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in
+	  PA7*) echo hppa1.1-unknown-linux-${LIBC} ;;
+	  PA8*) echo hppa2.0-unknown-linux-${LIBC} ;;
+	  *)    echo hppa-unknown-linux-${LIBC} ;;
+	esac
+	exit ;;
+    ppc64:Linux:*:*)
+	echo powerpc64-unknown-linux-${LIBC}
+	exit ;;
+    ppc:Linux:*:*)
+	echo powerpc-unknown-linux-${LIBC}
+	exit ;;
+    ppc64le:Linux:*:*)
+	echo powerpc64le-unknown-linux-${LIBC}
+	exit ;;
+    ppcle:Linux:*:*)
+	echo powerpcle-unknown-linux-${LIBC}
+	exit ;;
+    riscv32:Linux:*:* | riscv64:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    s390:Linux:*:* | s390x:Linux:*:*)
+	echo ${UNAME_MACHINE}-ibm-linux-${LIBC}
+	exit ;;
+    sh64*:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    sh*:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    sparc:Linux:*:* | sparc64:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    tile*:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    vax:Linux:*:*)
+	echo ${UNAME_MACHINE}-dec-linux-${LIBC}
+	exit ;;
+    x86_64:Linux:*:*)
+	echo ${UNAME_MACHINE}-pc-linux-${LIBC}
+	exit ;;
+    xtensa*:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+	exit ;;
+    i*86:DYNIX/ptx:4*:*)
+	# ptx 4.0 does uname -s correctly, with DYNIX/ptx in there.
+	# earlier versions are messed up and put the nodename in both
+	# sysname and nodename.
+	echo i386-sequent-sysv4
+	exit ;;
+    i*86:UNIX_SV:4.2MP:2.*)
+	# Unixware is an offshoot of SVR4, but it has its own version
+	# number series starting with 2...
+	# I am not positive that other SVR4 systems won't match this,
+	# I just have to hope.  -- rms.
+	# Use sysv4.2uw... so that sysv4* matches it.
+	echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION}
+	exit ;;
+    i*86:OS/2:*:*)
+	# If we were able to find `uname', then EMX Unix compatibility
+	# is probably installed.
+	echo ${UNAME_MACHINE}-pc-os2-emx
+	exit ;;
+    i*86:XTS-300:*:STOP)
+	echo ${UNAME_MACHINE}-unknown-stop
+	exit ;;
+    i*86:atheos:*:*)
+	echo ${UNAME_MACHINE}-unknown-atheos
+	exit ;;
+    i*86:syllable:*:*)
+	echo ${UNAME_MACHINE}-pc-syllable
+	exit ;;
+    i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.[02]*:*)
+	echo i386-unknown-lynxos${UNAME_RELEASE}
+	exit ;;
+    i*86:*DOS:*:*)
+	echo ${UNAME_MACHINE}-pc-msdosdjgpp
+	exit ;;
+    i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*)
+	UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'`
+	if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then
+		echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL}
+	else
+		echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL}
+	fi
+	exit ;;
+    i*86:*:5:[678]*)
+	# UnixWare 7.x, OpenUNIX and OpenServer 6.
+	case `/bin/uname -X | grep "^Machine"` in
+	    *486*)	     UNAME_MACHINE=i486 ;;
+	    *Pentium)	     UNAME_MACHINE=i586 ;;
+	    *Pent*|*Celeron) UNAME_MACHINE=i686 ;;
+	esac
+	echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION}
+	exit ;;
+    i*86:*:3.2:*)
+	if test -f /usr/options/cb.name; then
+		UNAME_REL=`sed -n 's/.*Version //p' </usr/options/cb.name`
+		echo ${UNAME_MACHINE}-pc-isc$UNAME_REL
+	elif /bin/uname -X 2>/dev/null >/dev/null ; then
+		UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')`
+		(/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486
+		(/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \
+			&& UNAME_MACHINE=i586
+		(/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \
+			&& UNAME_MACHINE=i686
+		(/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \
+			&& UNAME_MACHINE=i686
+		echo ${UNAME_MACHINE}-pc-sco$UNAME_REL
+	else
+		echo ${UNAME_MACHINE}-pc-sysv32
+	fi
+	exit ;;
+    pc:*:*:*)
+	# Left here for compatibility:
+	# uname -m prints for DJGPP always 'pc', but it prints nothing about
+	# the processor, so we play safe by assuming i586.
+	# Note: whatever this is, it MUST be the same as what config.sub
+	# prints for the "djgpp" host, or else GDB configure will decide that
+	# this is a cross-build.
+	echo i586-pc-msdosdjgpp
+	exit ;;
+    Intel:Mach:3*:*)
+	echo i386-pc-mach3
+	exit ;;
+    paragon:*:*:*)
+	echo i860-intel-osf1
+	exit ;;
+    i860:*:4.*:*) # i860-SVR4
+	if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then
+	  echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4
+	else # Add other i860-SVR4 vendors below as they are discovered.
+	  echo i860-unknown-sysv${UNAME_RELEASE}  # Unknown i860-SVR4
+	fi
+	exit ;;
+    mini*:CTIX:SYS*5:*)
+	# "miniframe"
+	echo m68010-convergent-sysv
+	exit ;;
+    mc68k:UNIX:SYSTEM5:3.51m)
+	echo m68k-convergent-sysv
+	exit ;;
+    M680?0:D-NIX:5.3:*)
+	echo m68k-diab-dnix
+	exit ;;
+    M68*:*:R3V[5678]*:*)
+	test -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;;
+    3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0)
+	OS_REL=''
+	test -r /etc/.relid \
+	&& OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid`
+	/bin/uname -p 2>/dev/null | grep 86 >/dev/null \
+	  && { echo i486-ncr-sysv4.3${OS_REL}; exit; }
+	/bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \
+	  && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;;
+    3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*)
+	/bin/uname -p 2>/dev/null | grep 86 >/dev/null \
+	  && { echo i486-ncr-sysv4; exit; } ;;
+    NCR*:*:4.2:* | MPRAS*:*:4.2:*)
+	OS_REL='.3'
+	test -r /etc/.relid \
+	    && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid`
+	/bin/uname -p 2>/dev/null | grep 86 >/dev/null \
+	    && { echo i486-ncr-sysv4.3${OS_REL}; exit; }
+	/bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \
+	    && { echo i586-ncr-sysv4.3${OS_REL}; exit; }
+	/bin/uname -p 2>/dev/null | /bin/grep pteron >/dev/null \
+	    && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;;
+    m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*)
+	echo m68k-unknown-lynxos${UNAME_RELEASE}
+	exit ;;
+    mc68030:UNIX_System_V:4.*:*)
+	echo m68k-atari-sysv4
+	exit ;;
+    TSUNAMI:LynxOS:2.*:*)
+	echo sparc-unknown-lynxos${UNAME_RELEASE}
+	exit ;;
+    rs6000:LynxOS:2.*:*)
+	echo rs6000-unknown-lynxos${UNAME_RELEASE}
+	exit ;;
+    PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.[02]*:*)
+	echo powerpc-unknown-lynxos${UNAME_RELEASE}
+	exit ;;
+    SM[BE]S:UNIX_SV:*:*)
+	echo mips-dde-sysv${UNAME_RELEASE}
+	exit ;;
+    RM*:ReliantUNIX-*:*:*)
+	echo mips-sni-sysv4
+	exit ;;
+    RM*:SINIX-*:*:*)
+	echo mips-sni-sysv4
+	exit ;;
+    *:SINIX-*:*:*)
+	if uname -p 2>/dev/null >/dev/null ; then
+		UNAME_MACHINE=`(uname -p) 2>/dev/null`
+		echo ${UNAME_MACHINE}-sni-sysv4
+	else
+		echo ns32k-sni-sysv
+	fi
+	exit ;;
+    PENTIUM:*:4.0*:*)	# Unisys `ClearPath HMP IX 4000' SVR4/MP effort
+			# says <Richard.M.Bartel@ccMail.Census.GOV>
+	echo i586-unisys-sysv4
+	exit ;;
+    *:UNIX_System_V:4*:FTX*)
+	# From Gerald Hewes <hewes@openmarket.com>.
+	# How about differentiating between stratus architectures? -djm
+	echo hppa1.1-stratus-sysv4
+	exit ;;
+    *:*:*:FTX*)
+	# From seanf@swdc.stratus.com.
+	echo i860-stratus-sysv4
+	exit ;;
+    i*86:VOS:*:*)
+	# From Paul.Green@stratus.com.
+	echo ${UNAME_MACHINE}-stratus-vos
+	exit ;;
+    *:VOS:*:*)
+	# From Paul.Green@stratus.com.
+	echo hppa1.1-stratus-vos
+	exit ;;
+    mc68*:A/UX:*:*)
+	echo m68k-apple-aux${UNAME_RELEASE}
+	exit ;;
+    news*:NEWS-OS:6*:*)
+	echo mips-sony-newsos6
+	exit ;;
+    R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*)
+	if [ -d /usr/nec ]; then
+		echo mips-nec-sysv${UNAME_RELEASE}
+	else
+		echo mips-unknown-sysv${UNAME_RELEASE}
+	fi
+	exit ;;
+    BeBox:BeOS:*:*)	# BeOS running on hardware made by Be, PPC only.
+	echo powerpc-be-beos
+	exit ;;
+    BeMac:BeOS:*:*)	# BeOS running on Mac or Mac clone, PPC only.
+	echo powerpc-apple-beos
+	exit ;;
+    BePC:BeOS:*:*)	# BeOS running on Intel PC compatible.
+	echo i586-pc-beos
+	exit ;;
+    BePC:Haiku:*:*)	# Haiku running on Intel PC compatible.
+	echo i586-pc-haiku
+	exit ;;
+    x86_64:Haiku:*:*)
+	echo x86_64-unknown-haiku
+	exit ;;
+    SX-4:SUPER-UX:*:*)
+	echo sx4-nec-superux${UNAME_RELEASE}
+	exit ;;
+    SX-5:SUPER-UX:*:*)
+	echo sx5-nec-superux${UNAME_RELEASE}
+	exit ;;
+    SX-6:SUPER-UX:*:*)
+	echo sx6-nec-superux${UNAME_RELEASE}
+	exit ;;
+    SX-7:SUPER-UX:*:*)
+	echo sx7-nec-superux${UNAME_RELEASE}
+	exit ;;
+    SX-8:SUPER-UX:*:*)
+	echo sx8-nec-superux${UNAME_RELEASE}
+	exit ;;
+    SX-8R:SUPER-UX:*:*)
+	echo sx8r-nec-superux${UNAME_RELEASE}
+	exit ;;
+    SX-ACE:SUPER-UX:*:*)
+	echo sxace-nec-superux${UNAME_RELEASE}
+	exit ;;
+    Power*:Rhapsody:*:*)
+	echo powerpc-apple-rhapsody${UNAME_RELEASE}
+	exit ;;
+    *:Rhapsody:*:*)
+	echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE}
+	exit ;;
+    *:Darwin:*:*)
+	UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown
+	eval $set_cc_for_build
+	if test "$UNAME_PROCESSOR" = unknown ; then
+	    UNAME_PROCESSOR=powerpc
+	fi
+	if test `echo "$UNAME_RELEASE" | sed -e 's/\..*//'` -le 10 ; then
+	    if [ "$CC_FOR_BUILD" != no_compiler_found ]; then
+		if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \
+		    (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \
+		    grep IS_64BIT_ARCH >/dev/null
+		then
+		    case $UNAME_PROCESSOR in
+			i386) UNAME_PROCESSOR=x86_64 ;;
+			powerpc) UNAME_PROCESSOR=powerpc64 ;;
+		    esac
+		fi
+	    fi
+	elif test "$UNAME_PROCESSOR" = i386 ; then
+	    # Avoid executing cc on OS X 10.9, as it ships with a stub
+	    # that puts up a graphical alert prompting to install
+	    # developer tools.  Any system running Mac OS X 10.7 or
+	    # later (Darwin 11 and later) is required to have a 64-bit
+	    # processor. This is not true of the ARM version of Darwin
+	    # that Apple uses in portable devices.
+	    UNAME_PROCESSOR=x86_64
+	fi
+	echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE}
+	exit ;;
+    *:procnto*:*:* | *:QNX:[0123456789]*:*)
+	UNAME_PROCESSOR=`uname -p`
+	if test "$UNAME_PROCESSOR" = x86; then
+		UNAME_PROCESSOR=i386
+		UNAME_MACHINE=pc
+	fi
+	echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE}
+	exit ;;
+    *:QNX:*:4*)
+	echo i386-pc-qnx
+	exit ;;
+    NEO-?:NONSTOP_KERNEL:*:*)
+	echo neo-tandem-nsk${UNAME_RELEASE}
+	exit ;;
+    NSE-*:NONSTOP_KERNEL:*:*)
+	echo nse-tandem-nsk${UNAME_RELEASE}
+	exit ;;
+    NSR-?:NONSTOP_KERNEL:*:*)
+	echo nsr-tandem-nsk${UNAME_RELEASE}
+	exit ;;
+    *:NonStop-UX:*:*)
+	echo mips-compaq-nonstopux
+	exit ;;
+    BS2000:POSIX*:*:*)
+	echo bs2000-siemens-sysv
+	exit ;;
+    DS/*:UNIX_System_V:*:*)
+	echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE}
+	exit ;;
+    *:Plan9:*:*)
+	# "uname -m" is not consistent, so use $cputype instead. 386
+	# is converted to i386 for consistency with other x86
+	# operating systems.
+	if test "$cputype" = 386; then
+	    UNAME_MACHINE=i386
+	else
+	    UNAME_MACHINE="$cputype"
+	fi
+	echo ${UNAME_MACHINE}-unknown-plan9
+	exit ;;
+    *:TOPS-10:*:*)
+	echo pdp10-unknown-tops10
+	exit ;;
+    *:TENEX:*:*)
+	echo pdp10-unknown-tenex
+	exit ;;
+    KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*)
+	echo pdp10-dec-tops20
+	exit ;;
+    XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*)
+	echo pdp10-xkl-tops20
+	exit ;;
+    *:TOPS-20:*:*)
+	echo pdp10-unknown-tops20
+	exit ;;
+    *:ITS:*:*)
+	echo pdp10-unknown-its
+	exit ;;
+    SEI:*:*:SEIUX)
+	echo mips-sei-seiux${UNAME_RELEASE}
+	exit ;;
+    *:DragonFly:*:*)
+	echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`
+	exit ;;
+    *:*VMS:*:*)
+	UNAME_MACHINE=`(uname -p) 2>/dev/null`
+	case "${UNAME_MACHINE}" in
+	    A*) echo alpha-dec-vms ; exit ;;
+	    I*) echo ia64-dec-vms ; exit ;;
+	    V*) echo vax-dec-vms ; exit ;;
+	esac ;;
+    *:XENIX:*:SysV)
+	echo i386-pc-xenix
+	exit ;;
+    i*86:skyos:*:*)
+	echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE} | sed -e 's/ .*$//'`
+	exit ;;
+    i*86:rdos:*:*)
+	echo ${UNAME_MACHINE}-pc-rdos
+	exit ;;
+    i*86:AROS:*:*)
+	echo ${UNAME_MACHINE}-pc-aros
+	exit ;;
+    x86_64:VMkernel:*:*)
+	echo ${UNAME_MACHINE}-unknown-esx
+	exit ;;
+    amd64:Isilon\ OneFS:*:*)
+	echo x86_64-unknown-onefs
+	exit ;;
+esac
+
+cat >&2 <<EOF
+$0: unable to guess system type
+
+This script (version $timestamp), has failed to recognize the
+operating system you are using. If your script is old, overwrite
+config.guess and config.sub with the latest versions from:
+
+  http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess
+and
+  http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub
+
+If $0 has already been updated, send the following data and any
+information you think might be pertinent to config-patches@gnu.org to
+provide the necessary information to handle your system.
+
+config.guess timestamp = $timestamp
+
+uname -m = `(uname -m) 2>/dev/null || echo unknown`
+uname -r = `(uname -r) 2>/dev/null || echo unknown`
+uname -s = `(uname -s) 2>/dev/null || echo unknown`
+uname -v = `(uname -v) 2>/dev/null || echo unknown`
+
+/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null`
+/bin/uname -X     = `(/bin/uname -X) 2>/dev/null`
+
+hostinfo               = `(hostinfo) 2>/dev/null`
+/bin/universe          = `(/bin/universe) 2>/dev/null`
+/usr/bin/arch -k       = `(/usr/bin/arch -k) 2>/dev/null`
+/bin/arch              = `(/bin/arch) 2>/dev/null`
+/usr/bin/oslevel       = `(/usr/bin/oslevel) 2>/dev/null`
+/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null`
+
+UNAME_MACHINE = ${UNAME_MACHINE}
+UNAME_RELEASE = ${UNAME_RELEASE}
+UNAME_SYSTEM  = ${UNAME_SYSTEM}
+UNAME_VERSION = ${UNAME_VERSION}
+EOF
+
+exit 1
+
+# Local variables:
+# eval: (add-hook 'write-file-hooks 'time-stamp)
+# time-stamp-start: "timestamp='"
+# time-stamp-format: "%:y-%02m-%02d"
+# time-stamp-end: "'"
+# End:
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/config.h.in
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/config.h.in
@@ -0,0 +1,25 @@
+/* config.h.in.  Generated from configure.ac by autoheader.  */
+
+/* Name of package */
+#undef PACKAGE
+
+/* Define to the address where bug reports for this package should be sent. */
+#undef PACKAGE_BUGREPORT
+
+/* Define to the full name of this package. */
+#undef PACKAGE_NAME
+
+/* Define to the full name and version of this package. */
+#undef PACKAGE_STRING
+
+/* Define to the one symbol short name of this package. */
+#undef PACKAGE_TARNAME
+
+/* Define to the home page for this package. */
+#undef PACKAGE_URL
+
+/* Define to the version of this package. */
+#undef PACKAGE_VERSION
+
+/* Version number of package */
+#undef VERSION
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/config.sub
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/config.sub
@@ -0,0 +1,1825 @@
+#! /bin/sh
+# Configuration validation subroutine script.
+#   Copyright 1992-2016 Free Software Foundation, Inc.
+
+timestamp='2016-11-04'
+
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, see <http://www.gnu.org/licenses/>.
+#
+# As a special exception to the GNU General Public License, if you
+# distribute this file as part of a program that contains a
+# configuration script generated by Autoconf, you may include it under
+# the same distribution terms that you use for the rest of that
+# program.  This Exception is an additional permission under section 7
+# of the GNU General Public License, version 3 ("GPLv3").
+
+
+# Please send patches to <config-patches@gnu.org>.
+#
+# Configuration subroutine to validate and canonicalize a configuration type.
+# Supply the specified configuration type as an argument.
+# If it is invalid, we print an error message on stderr and exit with code 1.
+# Otherwise, we print the canonical config type on stdout and succeed.
+
+# You can get the latest version of this script from:
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub
+
+# This file is supposed to be the same for all GNU packages
+# and recognize all the CPU types, system types and aliases
+# that are meaningful with *any* GNU software.
+# Each package is responsible for reporting which valid configurations
+# it does not support.  The user should be able to distinguish
+# a failure to support a valid configuration from a meaningless
+# configuration.
+
+# The goal of this file is to map all the various variations of a given
+# machine specification into a single specification in the form:
+#	CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM
+# or in some cases, the newer four-part form:
+#	CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM
+# It is wrong to echo any other type of specification.
+
+me=`echo "$0" | sed -e 's,.*/,,'`
+
+usage="\
+Usage: $0 [OPTION] CPU-MFR-OPSYS or ALIAS
+
+Canonicalize a configuration name.
+
+Operation modes:
+  -h, --help         print this help, then exit
+  -t, --time-stamp   print date of last modification, then exit
+  -v, --version      print version number, then exit
+
+Report bugs and patches to <config-patches@gnu.org>."
+
+version="\
+GNU config.sub ($timestamp)
+
+Copyright 1992-2016 Free Software Foundation, Inc.
+
+This is free software; see the source for copying conditions.  There is NO
+warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
+
+help="
+Try \`$me --help' for more information."
+
+# Parse command line
+while test $# -gt 0 ; do
+  case $1 in
+    --time-stamp | --time* | -t )
+       echo "$timestamp" ; exit ;;
+    --version | -v )
+       echo "$version" ; exit ;;
+    --help | --h* | -h )
+       echo "$usage"; exit ;;
+    -- )     # Stop option processing
+       shift; break ;;
+    - )	# Use stdin as input.
+       break ;;
+    -* )
+       echo "$me: invalid option $1$help"
+       exit 1 ;;
+
+    *local*)
+       # First pass through any local machine types.
+       echo $1
+       exit ;;
+
+    * )
+       break ;;
+  esac
+done
+
+case $# in
+ 0) echo "$me: missing argument$help" >&2
+    exit 1;;
+ 1) ;;
+ *) echo "$me: too many arguments$help" >&2
+    exit 1;;
+esac
+
+# Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any).
+# Here we must recognize all the valid KERNEL-OS combinations.
+maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
+case $maybe_os in
+  nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \
+  linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \
+  knetbsd*-gnu* | netbsd*-gnu* | netbsd*-eabi* | \
+  kopensolaris*-gnu* | cloudabi*-eabi* | \
+  storm-chaos* | os2-emx* | rtmk-nova*)
+    os=-$maybe_os
+    basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`
+    ;;
+  android-linux)
+    os=-linux-android
+    basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`-unknown
+    ;;
+  *)
+    basic_machine=`echo $1 | sed 's/-[^-]*$//'`
+    if [ $basic_machine != $1 ]
+    then os=`echo $1 | sed 's/.*-/-/'`
+    else os=; fi
+    ;;
+esac
+
+### Let's recognize common machines as not being operating systems so
+### that things like config.sub decstation-3100 work.  We also
+### recognize some manufacturers as not being operating systems, so we
+### can provide default operating systems below.
+case $os in
+	-sun*os*)
+		# Prevent following clause from handling this invalid input.
+		;;
+	-dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \
+	-att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \
+	-unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \
+	-convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\
+	-c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \
+	-harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \
+	-apple | -axis | -knuth | -cray | -microblaze*)
+		os=
+		basic_machine=$1
+		;;
+	-bluegene*)
+		os=-cnk
+		;;
+	-sim | -cisco | -oki | -wec | -winbond)
+		os=
+		basic_machine=$1
+		;;
+	-scout)
+		;;
+	-wrs)
+		os=-vxworks
+		basic_machine=$1
+		;;
+	-chorusos*)
+		os=-chorusos
+		basic_machine=$1
+		;;
+	-chorusrdb)
+		os=-chorusrdb
+		basic_machine=$1
+		;;
+	-hiux*)
+		os=-hiuxwe2
+		;;
+	-sco6)
+		os=-sco5v6
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
+	-sco5)
+		os=-sco3.2v5
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
+	-sco4)
+		os=-sco3.2v4
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
+	-sco3.2.[4-9]*)
+		os=`echo $os | sed -e 's/sco3.2./sco3.2v/'`
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
+	-sco3.2v[4-9]*)
+		# Don't forget version if it is 3.2v4 or newer.
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
+	-sco5v6*)
+		# Don't forget version if it is 3.2v4 or newer.
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
+	-sco*)
+		os=-sco3.2v2
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
+	-udk*)
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
+	-isc)
+		os=-isc2.2
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
+	-clix*)
+		basic_machine=clipper-intergraph
+		;;
+	-isc*)
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
+	-lynx*178)
+		os=-lynxos178
+		;;
+	-lynx*5)
+		os=-lynxos5
+		;;
+	-lynx*)
+		os=-lynxos
+		;;
+	-ptx*)
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'`
+		;;
+	-windowsnt*)
+		os=`echo $os | sed -e 's/windowsnt/winnt/'`
+		;;
+	-psos*)
+		os=-psos
+		;;
+	-mint | -mint[0-9]*)
+		basic_machine=m68k-atari
+		os=-mint
+		;;
+esac
+
+# Decode aliases for certain CPU-COMPANY combinations.
+case $basic_machine in
+	# Recognize the basic CPU types without company name.
+	# Some are omitted here because they have special meanings below.
+	1750a | 580 \
+	| a29k \
+	| aarch64 | aarch64_be \
+	| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
+	| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
+	| am33_2.0 \
+	| arc | arceb \
+	| arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \
+	| avr | avr32 \
+	| ba \
+	| be32 | be64 \
+	| bfin \
+	| c4x | c8051 | clipper \
+	| d10v | d30v | dlx | dsp16xx \
+	| e2k | epiphany \
+	| fido | fr30 | frv | ft32 \
+	| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
+	| hexagon \
+	| i370 | i860 | i960 | ia64 \
+	| ip2k | iq2000 \
+	| k1om \
+	| le32 | le64 \
+	| lm32 \
+	| m32c | m32r | m32rle | m68000 | m68k | m88k \
+	| maxq | mb | microblaze | microblazeel | mcore | mep | metag \
+	| mips | mipsbe | mipseb | mipsel | mipsle \
+	| mips16 \
+	| mips64 | mips64el \
+	| mips64octeon | mips64octeonel \
+	| mips64orion | mips64orionel \
+	| mips64r5900 | mips64r5900el \
+	| mips64vr | mips64vrel \
+	| mips64vr4100 | mips64vr4100el \
+	| mips64vr4300 | mips64vr4300el \
+	| mips64vr5000 | mips64vr5000el \
+	| mips64vr5900 | mips64vr5900el \
+	| mipsisa32 | mipsisa32el \
+	| mipsisa32r2 | mipsisa32r2el \
+	| mipsisa32r6 | mipsisa32r6el \
+	| mipsisa64 | mipsisa64el \
+	| mipsisa64r2 | mipsisa64r2el \
+	| mipsisa64r6 | mipsisa64r6el \
+	| mipsisa64sb1 | mipsisa64sb1el \
+	| mipsisa64sr71k | mipsisa64sr71kel \
+	| mipsr5900 | mipsr5900el \
+	| mipstx39 | mipstx39el \
+	| mn10200 | mn10300 \
+	| moxie \
+	| mt \
+	| msp430 \
+	| nds32 | nds32le | nds32be \
+	| nios | nios2 | nios2eb | nios2el \
+	| ns16k | ns32k \
+	| open8 | or1k | or1knd | or32 \
+	| pdp10 | pdp11 | pj | pjl \
+	| powerpc | powerpc64 | powerpc64le | powerpcle \
+	| pru \
+	| pyramid \
+	| riscv32 | riscv64 \
+	| rl78 | rx \
+	| score \
+	| sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[234]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
+	| sh64 | sh64le \
+	| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
+	| sparcv8 | sparcv9 | sparcv9b | sparcv9v \
+	| spu \
+	| tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \
+	| ubicom32 \
+	| v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \
+	| visium \
+	| we32k \
+	| x86 | xc16x | xstormy16 | xtensa \
+	| z8k | z80)
+		basic_machine=$basic_machine-unknown
+		;;
+	c54x)
+		basic_machine=tic54x-unknown
+		;;
+	c55x)
+		basic_machine=tic55x-unknown
+		;;
+	c6x)
+		basic_machine=tic6x-unknown
+		;;
+	leon|leon[3-9])
+		basic_machine=sparc-$basic_machine
+		;;
+	m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip)
+		basic_machine=$basic_machine-unknown
+		os=-none
+		;;
+	m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k)
+		;;
+	ms1)
+		basic_machine=mt-unknown
+		;;
+
+	strongarm | thumb | xscale)
+		basic_machine=arm-unknown
+		;;
+	xgate)
+		basic_machine=$basic_machine-unknown
+		os=-none
+		;;
+	xscaleeb)
+		basic_machine=armeb-unknown
+		;;
+
+	xscaleel)
+		basic_machine=armel-unknown
+		;;
+
+	# We use `pc' rather than `unknown'
+	# because (1) that's what they normally are, and
+	# (2) the word "unknown" tends to confuse beginning users.
+	i*86 | x86_64)
+	  basic_machine=$basic_machine-pc
+	  ;;
+	# Object if more than one company name word.
+	*-*-*)
+		echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2
+		exit 1
+		;;
+	# Recognize the basic CPU types with company name.
+	580-* \
+	| a29k-* \
+	| aarch64-* | aarch64_be-* \
+	| alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \
+	| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
+	| alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \
+	| arm-*  | armbe-* | armle-* | armeb-* | armv*-* \
+	| avr-* | avr32-* \
+	| ba-* \
+	| be32-* | be64-* \
+	| bfin-* | bs2000-* \
+	| c[123]* | c30-* | [cjt]90-* | c4x-* \
+	| c8051-* | clipper-* | craynv-* | cydra-* \
+	| d10v-* | d30v-* | dlx-* \
+	| e2k-* | elxsi-* \
+	| f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
+	| h8300-* | h8500-* \
+	| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
+	| hexagon-* \
+	| i*86-* | i860-* | i960-* | ia64-* \
+	| ip2k-* | iq2000-* \
+	| k1om-* \
+	| le32-* | le64-* \
+	| lm32-* \
+	| m32c-* | m32r-* | m32rle-* \
+	| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
+	| m88110-* | m88k-* | maxq-* | mcore-* | metag-* \
+	| microblaze-* | microblazeel-* \
+	| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
+	| mips16-* \
+	| mips64-* | mips64el-* \
+	| mips64octeon-* | mips64octeonel-* \
+	| mips64orion-* | mips64orionel-* \
+	| mips64r5900-* | mips64r5900el-* \
+	| mips64vr-* | mips64vrel-* \
+	| mips64vr4100-* | mips64vr4100el-* \
+	| mips64vr4300-* | mips64vr4300el-* \
+	| mips64vr5000-* | mips64vr5000el-* \
+	| mips64vr5900-* | mips64vr5900el-* \
+	| mipsisa32-* | mipsisa32el-* \
+	| mipsisa32r2-* | mipsisa32r2el-* \
+	| mipsisa32r6-* | mipsisa32r6el-* \
+	| mipsisa64-* | mipsisa64el-* \
+	| mipsisa64r2-* | mipsisa64r2el-* \
+	| mipsisa64r6-* | mipsisa64r6el-* \
+	| mipsisa64sb1-* | mipsisa64sb1el-* \
+	| mipsisa64sr71k-* | mipsisa64sr71kel-* \
+	| mipsr5900-* | mipsr5900el-* \
+	| mipstx39-* | mipstx39el-* \
+	| mmix-* \
+	| mt-* \
+	| msp430-* \
+	| nds32-* | nds32le-* | nds32be-* \
+	| nios-* | nios2-* | nios2eb-* | nios2el-* \
+	| none-* | np1-* | ns16k-* | ns32k-* \
+	| open8-* \
+	| or1k*-* \
+	| orion-* \
+	| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
+	| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \
+	| pru-* \
+	| pyramid-* \
+	| riscv32-* | riscv64-* \
+	| rl78-* | romp-* | rs6000-* | rx-* \
+	| sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
+	| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
+	| sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
+	| sparclite-* \
+	| sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx*-* \
+	| tahoe-* \
+	| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \
+	| tile*-* \
+	| tron-* \
+	| ubicom32-* \
+	| v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \
+	| vax-* \
+	| visium-* \
+	| we32k-* \
+	| x86-* | x86_64-* | xc16x-* | xps100-* \
+	| xstormy16-* | xtensa*-* \
+	| ymp-* \
+	| z8k-* | z80-*)
+		;;
+	# Recognize the basic CPU types without company name, with glob match.
+	xtensa*)
+		basic_machine=$basic_machine-unknown
+		;;
+	# Recognize the various machine names and aliases which stand
+	# for a CPU type and a company and sometimes even an OS.
+	386bsd)
+		basic_machine=i386-unknown
+		os=-bsd
+		;;
+	3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc)
+		basic_machine=m68000-att
+		;;
+	3b*)
+		basic_machine=we32k-att
+		;;
+	a29khif)
+		basic_machine=a29k-amd
+		os=-udi
+		;;
+	abacus)
+		basic_machine=abacus-unknown
+		;;
+	adobe68k)
+		basic_machine=m68010-adobe
+		os=-scout
+		;;
+	alliant | fx80)
+		basic_machine=fx80-alliant
+		;;
+	altos | altos3068)
+		basic_machine=m68k-altos
+		;;
+	am29k)
+		basic_machine=a29k-none
+		os=-bsd
+		;;
+	amd64)
+		basic_machine=x86_64-pc
+		;;
+	amd64-*)
+		basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	amdahl)
+		basic_machine=580-amdahl
+		os=-sysv
+		;;
+	amiga | amiga-*)
+		basic_machine=m68k-unknown
+		;;
+	amigaos | amigados)
+		basic_machine=m68k-unknown
+		os=-amigaos
+		;;
+	amigaunix | amix)
+		basic_machine=m68k-unknown
+		os=-sysv4
+		;;
+	apollo68)
+		basic_machine=m68k-apollo
+		os=-sysv
+		;;
+	apollo68bsd)
+		basic_machine=m68k-apollo
+		os=-bsd
+		;;
+	aros)
+		basic_machine=i386-pc
+		os=-aros
+		;;
+	asmjs)
+		basic_machine=asmjs-unknown
+		;;
+	aux)
+		basic_machine=m68k-apple
+		os=-aux
+		;;
+	balance)
+		basic_machine=ns32k-sequent
+		os=-dynix
+		;;
+	blackfin)
+		basic_machine=bfin-unknown
+		os=-linux
+		;;
+	blackfin-*)
+		basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'`
+		os=-linux
+		;;
+	bluegene*)
+		basic_machine=powerpc-ibm
+		os=-cnk
+		;;
+	c54x-*)
+		basic_machine=tic54x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	c55x-*)
+		basic_machine=tic55x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	c6x-*)
+		basic_machine=tic6x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	c90)
+		basic_machine=c90-cray
+		os=-unicos
+		;;
+	cegcc)
+		basic_machine=arm-unknown
+		os=-cegcc
+		;;
+	convex-c1)
+		basic_machine=c1-convex
+		os=-bsd
+		;;
+	convex-c2)
+		basic_machine=c2-convex
+		os=-bsd
+		;;
+	convex-c32)
+		basic_machine=c32-convex
+		os=-bsd
+		;;
+	convex-c34)
+		basic_machine=c34-convex
+		os=-bsd
+		;;
+	convex-c38)
+		basic_machine=c38-convex
+		os=-bsd
+		;;
+	cray | j90)
+		basic_machine=j90-cray
+		os=-unicos
+		;;
+	craynv)
+		basic_machine=craynv-cray
+		os=-unicosmp
+		;;
+	cr16 | cr16-*)
+		basic_machine=cr16-unknown
+		os=-elf
+		;;
+	crds | unos)
+		basic_machine=m68k-crds
+		;;
+	crisv32 | crisv32-* | etraxfs*)
+		basic_machine=crisv32-axis
+		;;
+	cris | cris-* | etrax*)
+		basic_machine=cris-axis
+		;;
+	crx)
+		basic_machine=crx-unknown
+		os=-elf
+		;;
+	da30 | da30-*)
+		basic_machine=m68k-da30
+		;;
+	decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn)
+		basic_machine=mips-dec
+		;;
+	decsystem10* | dec10*)
+		basic_machine=pdp10-dec
+		os=-tops10
+		;;
+	decsystem20* | dec20*)
+		basic_machine=pdp10-dec
+		os=-tops20
+		;;
+	delta | 3300 | motorola-3300 | motorola-delta \
+	      | 3300-motorola | delta-motorola)
+		basic_machine=m68k-motorola
+		;;
+	delta88)
+		basic_machine=m88k-motorola
+		os=-sysv3
+		;;
+	dicos)
+		basic_machine=i686-pc
+		os=-dicos
+		;;
+	djgpp)
+		basic_machine=i586-pc
+		os=-msdosdjgpp
+		;;
+	dpx20 | dpx20-*)
+		basic_machine=rs6000-bull
+		os=-bosx
+		;;
+	dpx2* | dpx2*-bull)
+		basic_machine=m68k-bull
+		os=-sysv3
+		;;
+	e500v[12])
+		basic_machine=powerpc-unknown
+		os=$os"spe"
+		;;
+	e500v[12]-*)
+		basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
+		os=$os"spe"
+		;;
+	ebmon29k)
+		basic_machine=a29k-amd
+		os=-ebmon
+		;;
+	elxsi)
+		basic_machine=elxsi-elxsi
+		os=-bsd
+		;;
+	encore | umax | mmax)
+		basic_machine=ns32k-encore
+		;;
+	es1800 | OSE68k | ose68k | ose | OSE)
+		basic_machine=m68k-ericsson
+		os=-ose
+		;;
+	fx2800)
+		basic_machine=i860-alliant
+		;;
+	genix)
+		basic_machine=ns32k-ns
+		;;
+	gmicro)
+		basic_machine=tron-gmicro
+		os=-sysv
+		;;
+	go32)
+		basic_machine=i386-pc
+		os=-go32
+		;;
+	h3050r* | hiux*)
+		basic_machine=hppa1.1-hitachi
+		os=-hiuxwe2
+		;;
+	h8300hms)
+		basic_machine=h8300-hitachi
+		os=-hms
+		;;
+	h8300xray)
+		basic_machine=h8300-hitachi
+		os=-xray
+		;;
+	h8500hms)
+		basic_machine=h8500-hitachi
+		os=-hms
+		;;
+	harris)
+		basic_machine=m88k-harris
+		os=-sysv3
+		;;
+	hp300-*)
+		basic_machine=m68k-hp
+		;;
+	hp300bsd)
+		basic_machine=m68k-hp
+		os=-bsd
+		;;
+	hp300hpux)
+		basic_machine=m68k-hp
+		os=-hpux
+		;;
+	hp3k9[0-9][0-9] | hp9[0-9][0-9])
+		basic_machine=hppa1.0-hp
+		;;
+	hp9k2[0-9][0-9] | hp9k31[0-9])
+		basic_machine=m68000-hp
+		;;
+	hp9k3[2-9][0-9])
+		basic_machine=m68k-hp
+		;;
+	hp9k6[0-9][0-9] | hp6[0-9][0-9])
+		basic_machine=hppa1.0-hp
+		;;
+	hp9k7[0-79][0-9] | hp7[0-79][0-9])
+		basic_machine=hppa1.1-hp
+		;;
+	hp9k78[0-9] | hp78[0-9])
+		# FIXME: really hppa2.0-hp
+		basic_machine=hppa1.1-hp
+		;;
+	hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893)
+		# FIXME: really hppa2.0-hp
+		basic_machine=hppa1.1-hp
+		;;
+	hp9k8[0-9][13679] | hp8[0-9][13679])
+		basic_machine=hppa1.1-hp
+		;;
+	hp9k8[0-9][0-9] | hp8[0-9][0-9])
+		basic_machine=hppa1.0-hp
+		;;
+	hppa-next)
+		os=-nextstep3
+		;;
+	hppaosf)
+		basic_machine=hppa1.1-hp
+		os=-osf
+		;;
+	hppro)
+		basic_machine=hppa1.1-hp
+		os=-proelf
+		;;
+	i370-ibm* | ibm*)
+		basic_machine=i370-ibm
+		;;
+	i*86v32)
+		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
+		os=-sysv32
+		;;
+	i*86v4*)
+		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
+		os=-sysv4
+		;;
+	i*86v)
+		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
+		os=-sysv
+		;;
+	i*86sol2)
+		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
+		os=-solaris2
+		;;
+	i386mach)
+		basic_machine=i386-mach
+		os=-mach
+		;;
+	i386-vsta | vsta)
+		basic_machine=i386-unknown
+		os=-vsta
+		;;
+	iris | iris4d)
+		basic_machine=mips-sgi
+		case $os in
+		    -irix*)
+			;;
+		    *)
+			os=-irix4
+			;;
+		esac
+		;;
+	isi68 | isi)
+		basic_machine=m68k-isi
+		os=-sysv
+		;;
+	leon-*|leon[3-9]-*)
+		basic_machine=sparc-`echo $basic_machine | sed 's/-.*//'`
+		;;
+	m68knommu)
+		basic_machine=m68k-unknown
+		os=-linux
+		;;
+	m68knommu-*)
+		basic_machine=m68k-`echo $basic_machine | sed 's/^[^-]*-//'`
+		os=-linux
+		;;
+	m88k-omron*)
+		basic_machine=m88k-omron
+		;;
+	magnum | m3230)
+		basic_machine=mips-mips
+		os=-sysv
+		;;
+	merlin)
+		basic_machine=ns32k-utek
+		os=-sysv
+		;;
+	microblaze*)
+		basic_machine=microblaze-xilinx
+		;;
+	mingw64)
+		basic_machine=x86_64-pc
+		os=-mingw64
+		;;
+	mingw32)
+		basic_machine=i686-pc
+		os=-mingw32
+		;;
+	mingw32ce)
+		basic_machine=arm-unknown
+		os=-mingw32ce
+		;;
+	miniframe)
+		basic_machine=m68000-convergent
+		;;
+	*mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*)
+		basic_machine=m68k-atari
+		os=-mint
+		;;
+	mips3*-*)
+		basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
+		;;
+	mips3*)
+		basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown
+		;;
+	monitor)
+		basic_machine=m68k-rom68k
+		os=-coff
+		;;
+	morphos)
+		basic_machine=powerpc-unknown
+		os=-morphos
+		;;
+	moxiebox)
+		basic_machine=moxie-unknown
+		os=-moxiebox
+		;;
+	msdos)
+		basic_machine=i386-pc
+		os=-msdos
+		;;
+	ms1-*)
+		basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'`
+		;;
+	msys)
+		basic_machine=i686-pc
+		os=-msys
+		;;
+	mvs)
+		basic_machine=i370-ibm
+		os=-mvs
+		;;
+	nacl)
+		basic_machine=le32-unknown
+		os=-nacl
+		;;
+	ncr3000)
+		basic_machine=i486-ncr
+		os=-sysv4
+		;;
+	netbsd386)
+		basic_machine=i386-unknown
+		os=-netbsd
+		;;
+	netwinder)
+		basic_machine=armv4l-rebel
+		os=-linux
+		;;
+	news | news700 | news800 | news900)
+		basic_machine=m68k-sony
+		os=-newsos
+		;;
+	news1000)
+		basic_machine=m68030-sony
+		os=-newsos
+		;;
+	news-3600 | risc-news)
+		basic_machine=mips-sony
+		os=-newsos
+		;;
+	necv70)
+		basic_machine=v70-nec
+		os=-sysv
+		;;
+	next | m*-next )
+		basic_machine=m68k-next
+		case $os in
+		    -nextstep* )
+			;;
+		    -ns2*)
+		      os=-nextstep2
+			;;
+		    *)
+		      os=-nextstep3
+			;;
+		esac
+		;;
+	nh3000)
+		basic_machine=m68k-harris
+		os=-cxux
+		;;
+	nh[45]000)
+		basic_machine=m88k-harris
+		os=-cxux
+		;;
+	nindy960)
+		basic_machine=i960-intel
+		os=-nindy
+		;;
+	mon960)
+		basic_machine=i960-intel
+		os=-mon960
+		;;
+	nonstopux)
+		basic_machine=mips-compaq
+		os=-nonstopux
+		;;
+	np1)
+		basic_machine=np1-gould
+		;;
+	neo-tandem)
+		basic_machine=neo-tandem
+		;;
+	nse-tandem)
+		basic_machine=nse-tandem
+		;;
+	nsr-tandem)
+		basic_machine=nsr-tandem
+		;;
+	op50n-* | op60c-*)
+		basic_machine=hppa1.1-oki
+		os=-proelf
+		;;
+	openrisc | openrisc-*)
+		basic_machine=or32-unknown
+		;;
+	os400)
+		basic_machine=powerpc-ibm
+		os=-os400
+		;;
+	OSE68000 | ose68000)
+		basic_machine=m68000-ericsson
+		os=-ose
+		;;
+	os68k)
+		basic_machine=m68k-none
+		os=-os68k
+		;;
+	pa-hitachi)
+		basic_machine=hppa1.1-hitachi
+		os=-hiuxwe2
+		;;
+	paragon)
+		basic_machine=i860-intel
+		os=-osf
+		;;
+	parisc)
+		basic_machine=hppa-unknown
+		os=-linux
+		;;
+	parisc-*)
+		basic_machine=hppa-`echo $basic_machine | sed 's/^[^-]*-//'`
+		os=-linux
+		;;
+	pbd)
+		basic_machine=sparc-tti
+		;;
+	pbb)
+		basic_machine=m68k-tti
+		;;
+	pc532 | pc532-*)
+		basic_machine=ns32k-pc532
+		;;
+	pc98)
+		basic_machine=i386-pc
+		;;
+	pc98-*)
+		basic_machine=i386-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	pentium | p5 | k5 | k6 | nexgen | viac3)
+		basic_machine=i586-pc
+		;;
+	pentiumpro | p6 | 6x86 | athlon | athlon_*)
+		basic_machine=i686-pc
+		;;
+	pentiumii | pentium2 | pentiumiii | pentium3)
+		basic_machine=i686-pc
+		;;
+	pentium4)
+		basic_machine=i786-pc
+		;;
+	pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*)
+		basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	pentiumpro-* | p6-* | 6x86-* | athlon-*)
+		basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*)
+		basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	pentium4-*)
+		basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	pn)
+		basic_machine=pn-gould
+		;;
+	power)	basic_machine=power-ibm
+		;;
+	ppc | ppcbe)	basic_machine=powerpc-unknown
+		;;
+	ppc-* | ppcbe-*)
+		basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	ppcle | powerpclittle)
+		basic_machine=powerpcle-unknown
+		;;
+	ppcle-* | powerpclittle-*)
+		basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	ppc64)	basic_machine=powerpc64-unknown
+		;;
+	ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	ppc64le | powerpc64little)
+		basic_machine=powerpc64le-unknown
+		;;
+	ppc64le-* | powerpc64little-*)
+		basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	ps2)
+		basic_machine=i386-ibm
+		;;
+	pw32)
+		basic_machine=i586-unknown
+		os=-pw32
+		;;
+	rdos | rdos64)
+		basic_machine=x86_64-pc
+		os=-rdos
+		;;
+	rdos32)
+		basic_machine=i386-pc
+		os=-rdos
+		;;
+	rom68k)
+		basic_machine=m68k-rom68k
+		os=-coff
+		;;
+	rm[46]00)
+		basic_machine=mips-siemens
+		;;
+	rtpc | rtpc-*)
+		basic_machine=romp-ibm
+		;;
+	s390 | s390-*)
+		basic_machine=s390-ibm
+		;;
+	s390x | s390x-*)
+		basic_machine=s390x-ibm
+		;;
+	sa29200)
+		basic_machine=a29k-amd
+		os=-udi
+		;;
+	sb1)
+		basic_machine=mipsisa64sb1-unknown
+		;;
+	sb1el)
+		basic_machine=mipsisa64sb1el-unknown
+		;;
+	sde)
+		basic_machine=mipsisa32-sde
+		os=-elf
+		;;
+	sei)
+		basic_machine=mips-sei
+		os=-seiux
+		;;
+	sequent)
+		basic_machine=i386-sequent
+		;;
+	sh)
+		basic_machine=sh-hitachi
+		os=-hms
+		;;
+	sh5el)
+		basic_machine=sh5le-unknown
+		;;
+	sh64)
+		basic_machine=sh64-unknown
+		;;
+	sparclite-wrs | simso-wrs)
+		basic_machine=sparclite-wrs
+		os=-vxworks
+		;;
+	sps7)
+		basic_machine=m68k-bull
+		os=-sysv2
+		;;
+	spur)
+		basic_machine=spur-unknown
+		;;
+	st2000)
+		basic_machine=m68k-tandem
+		;;
+	stratus)
+		basic_machine=i860-stratus
+		os=-sysv4
+		;;
+	strongarm-* | thumb-*)
+		basic_machine=arm-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	sun2)
+		basic_machine=m68000-sun
+		;;
+	sun2os3)
+		basic_machine=m68000-sun
+		os=-sunos3
+		;;
+	sun2os4)
+		basic_machine=m68000-sun
+		os=-sunos4
+		;;
+	sun3os3)
+		basic_machine=m68k-sun
+		os=-sunos3
+		;;
+	sun3os4)
+		basic_machine=m68k-sun
+		os=-sunos4
+		;;
+	sun4os3)
+		basic_machine=sparc-sun
+		os=-sunos3
+		;;
+	sun4os4)
+		basic_machine=sparc-sun
+		os=-sunos4
+		;;
+	sun4sol2)
+		basic_machine=sparc-sun
+		os=-solaris2
+		;;
+	sun3 | sun3-*)
+		basic_machine=m68k-sun
+		;;
+	sun4)
+		basic_machine=sparc-sun
+		;;
+	sun386 | sun386i | roadrunner)
+		basic_machine=i386-sun
+		;;
+	sv1)
+		basic_machine=sv1-cray
+		os=-unicos
+		;;
+	symmetry)
+		basic_machine=i386-sequent
+		os=-dynix
+		;;
+	t3e)
+		basic_machine=alphaev5-cray
+		os=-unicos
+		;;
+	t90)
+		basic_machine=t90-cray
+		os=-unicos
+		;;
+	tile*)
+		basic_machine=$basic_machine-unknown
+		os=-linux-gnu
+		;;
+	tx39)
+		basic_machine=mipstx39-unknown
+		;;
+	tx39el)
+		basic_machine=mipstx39el-unknown
+		;;
+	toad1)
+		basic_machine=pdp10-xkl
+		os=-tops20
+		;;
+	tower | tower-32)
+		basic_machine=m68k-ncr
+		;;
+	tpf)
+		basic_machine=s390x-ibm
+		os=-tpf
+		;;
+	udi29k)
+		basic_machine=a29k-amd
+		os=-udi
+		;;
+	ultra3)
+		basic_machine=a29k-nyu
+		os=-sym1
+		;;
+	v810 | necv810)
+		basic_machine=v810-nec
+		os=-none
+		;;
+	vaxv)
+		basic_machine=vax-dec
+		os=-sysv
+		;;
+	vms)
+		basic_machine=vax-dec
+		os=-vms
+		;;
+	vpp*|vx|vx-*)
+		basic_machine=f301-fujitsu
+		;;
+	vxworks960)
+		basic_machine=i960-wrs
+		os=-vxworks
+		;;
+	vxworks68)
+		basic_machine=m68k-wrs
+		os=-vxworks
+		;;
+	vxworks29k)
+		basic_machine=a29k-wrs
+		os=-vxworks
+		;;
+	w65*)
+		basic_machine=w65-wdc
+		os=-none
+		;;
+	w89k-*)
+		basic_machine=hppa1.1-winbond
+		os=-proelf
+		;;
+	xbox)
+		basic_machine=i686-pc
+		os=-mingw32
+		;;
+	xps | xps100)
+		basic_machine=xps100-honeywell
+		;;
+	xscale-* | xscalee[bl]-*)
+		basic_machine=`echo $basic_machine | sed 's/^xscale/arm/'`
+		;;
+	ymp)
+		basic_machine=ymp-cray
+		os=-unicos
+		;;
+	z8k-*-coff)
+		basic_machine=z8k-unknown
+		os=-sim
+		;;
+	z80-*-coff)
+		basic_machine=z80-unknown
+		os=-sim
+		;;
+	none)
+		basic_machine=none-none
+		os=-none
+		;;
+
+# Here we handle the default manufacturer of certain CPU types.  It is in
+# some cases the only manufacturer, in others, it is the most popular.
+	w89k)
+		basic_machine=hppa1.1-winbond
+		;;
+	op50n)
+		basic_machine=hppa1.1-oki
+		;;
+	op60c)
+		basic_machine=hppa1.1-oki
+		;;
+	romp)
+		basic_machine=romp-ibm
+		;;
+	mmix)
+		basic_machine=mmix-knuth
+		;;
+	rs6000)
+		basic_machine=rs6000-ibm
+		;;
+	vax)
+		basic_machine=vax-dec
+		;;
+	pdp10)
+		# there are many clones, so DEC is not a safe bet
+		basic_machine=pdp10-unknown
+		;;
+	pdp11)
+		basic_machine=pdp11-dec
+		;;
+	we32k)
+		basic_machine=we32k-att
+		;;
+	sh[1234] | sh[24]a | sh[24]aeb | sh[34]eb | sh[1234]le | sh[23]ele)
+		basic_machine=sh-unknown
+		;;
+	sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v)
+		basic_machine=sparc-sun
+		;;
+	cydra)
+		basic_machine=cydra-cydrome
+		;;
+	orion)
+		basic_machine=orion-highlevel
+		;;
+	orion105)
+		basic_machine=clipper-highlevel
+		;;
+	mac | mpw | mac-mpw)
+		basic_machine=m68k-apple
+		;;
+	pmac | pmac-mpw)
+		basic_machine=powerpc-apple
+		;;
+	*-unknown)
+		# Make sure to match an already-canonicalized machine name.
+		;;
+	*)
+		echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2
+		exit 1
+		;;
+esac
+
+# Here we canonicalize certain aliases for manufacturers.
+case $basic_machine in
+	*-digital*)
+		basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'`
+		;;
+	*-commodore*)
+		basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'`
+		;;
+	*)
+		;;
+esac
+
+# Decode manufacturer-specific aliases for certain operating systems.
+
+if [ x"$os" != x"" ]
+then
+case $os in
+	# First match some system type aliases
+	# that might get confused with valid system types.
+	# -solaris* is a basic system type, with this one exception.
+	-auroraux)
+		os=-auroraux
+		;;
+	-solaris1 | -solaris1.*)
+		os=`echo $os | sed -e 's|solaris1|sunos4|'`
+		;;
+	-solaris)
+		os=-solaris2
+		;;
+	-svr4*)
+		os=-sysv4
+		;;
+	-unixware*)
+		os=-sysv4.2uw
+		;;
+	-gnu/linux*)
+		os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'`
+		;;
+	# First accept the basic system types.
+	# The portable systems comes first.
+	# Each alternative MUST END IN A *, to match a version number.
+	# -sysv* is not here because it comes later, after sysvr4.
+	-gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \
+	      | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\
+	      | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \
+	      | -sym* | -kopensolaris* | -plan9* \
+	      | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \
+	      | -aos* | -aros* | -cloudabi* | -sortix* \
+	      | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
+	      | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \
+	      | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \
+	      | -bitrig* | -openbsd* | -solidbsd* | -libertybsd* \
+	      | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \
+	      | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
+	      | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
+	      | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
+	      | -chorusos* | -chorusrdb* | -cegcc* \
+	      | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
+	      | -midipix* | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \
+	      | -linux-newlib* | -linux-musl* | -linux-uclibc* \
+	      | -uxpv* | -beos* | -mpeix* | -udk* | -moxiebox* \
+	      | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
+	      | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
+	      | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \
+	      | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
+	      | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \
+	      | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \
+	      | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* \
+	      | -onefs* | -tirtos* | -phoenix* | -fuchsia*)
+	# Remember, each alternative MUST END IN *, to match a version number.
+		;;
+	-qnx*)
+		case $basic_machine in
+		    x86-* | i*86-*)
+			;;
+		    *)
+			os=-nto$os
+			;;
+		esac
+		;;
+	-nto-qnx*)
+		;;
+	-nto*)
+		os=`echo $os | sed -e 's|nto|nto-qnx|'`
+		;;
+	-sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \
+	      | -windows* | -osx | -abug | -netware* | -os9* | -beos* | -haiku* \
+	      | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*)
+		;;
+	-mac*)
+		os=`echo $os | sed -e 's|mac|macos|'`
+		;;
+	-linux-dietlibc)
+		os=-linux-dietlibc
+		;;
+	-linux*)
+		os=`echo $os | sed -e 's|linux|linux-gnu|'`
+		;;
+	-sunos5*)
+		os=`echo $os | sed -e 's|sunos5|solaris2|'`
+		;;
+	-sunos6*)
+		os=`echo $os | sed -e 's|sunos6|solaris3|'`
+		;;
+	-opened*)
+		os=-openedition
+		;;
+	-os400*)
+		os=-os400
+		;;
+	-wince*)
+		os=-wince
+		;;
+	-osfrose*)
+		os=-osfrose
+		;;
+	-osf*)
+		os=-osf
+		;;
+	-utek*)
+		os=-bsd
+		;;
+	-dynix*)
+		os=-bsd
+		;;
+	-acis*)
+		os=-aos
+		;;
+	-atheos*)
+		os=-atheos
+		;;
+	-syllable*)
+		os=-syllable
+		;;
+	-386bsd)
+		os=-bsd
+		;;
+	-ctix* | -uts*)
+		os=-sysv
+		;;
+	-nova*)
+		os=-rtmk-nova
+		;;
+	-ns2 )
+		os=-nextstep2
+		;;
+	-nsk*)
+		os=-nsk
+		;;
+	# Preserve the version number of sinix5.
+	-sinix5.*)
+		os=`echo $os | sed -e 's|sinix|sysv|'`
+		;;
+	-sinix*)
+		os=-sysv4
+		;;
+	-tpf*)
+		os=-tpf
+		;;
+	-triton*)
+		os=-sysv3
+		;;
+	-oss*)
+		os=-sysv3
+		;;
+	-svr4)
+		os=-sysv4
+		;;
+	-svr3)
+		os=-sysv3
+		;;
+	-sysvr4)
+		os=-sysv4
+		;;
+	# This must come after -sysvr4.
+	-sysv*)
+		;;
+	-ose*)
+		os=-ose
+		;;
+	-es1800*)
+		os=-ose
+		;;
+	-xenix)
+		os=-xenix
+		;;
+	-*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*)
+		os=-mint
+		;;
+	-aros*)
+		os=-aros
+		;;
+	-zvmoe)
+		os=-zvmoe
+		;;
+	-dicos*)
+		os=-dicos
+		;;
+	-nacl*)
+		;;
+	-ios)
+		;;
+	-none)
+		;;
+	*)
+		# Get rid of the `-' at the beginning of $os.
+		os=`echo $os | sed 's/[^-]*-//'`
+		echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2
+		exit 1
+		;;
+esac
+else
+
+# Here we handle the default operating systems that come with various machines.
+# The value should be what the vendor currently ships out the door with their
+# machine or put another way, the most popular os provided with the machine.
+
+# Note that if you're going to try to match "-MANUFACTURER" here (say,
+# "-sun"), then you have to tell the case statement up towards the top
+# that MANUFACTURER isn't an operating system.  Otherwise, code above
+# will signal an error saying that MANUFACTURER isn't an operating
+# system, and we'll never get to this point.
+
+case $basic_machine in
+	score-*)
+		os=-elf
+		;;
+	spu-*)
+		os=-elf
+		;;
+	*-acorn)
+		os=-riscix1.2
+		;;
+	arm*-rebel)
+		os=-linux
+		;;
+	arm*-semi)
+		os=-aout
+		;;
+	c4x-* | tic4x-*)
+		os=-coff
+		;;
+	c8051-*)
+		os=-elf
+		;;
+	hexagon-*)
+		os=-elf
+		;;
+	tic54x-*)
+		os=-coff
+		;;
+	tic55x-*)
+		os=-coff
+		;;
+	tic6x-*)
+		os=-coff
+		;;
+	# This must come before the *-dec entry.
+	pdp10-*)
+		os=-tops20
+		;;
+	pdp11-*)
+		os=-none
+		;;
+	*-dec | vax-*)
+		os=-ultrix4.2
+		;;
+	m68*-apollo)
+		os=-domain
+		;;
+	i386-sun)
+		os=-sunos4.0.2
+		;;
+	m68000-sun)
+		os=-sunos3
+		;;
+	m68*-cisco)
+		os=-aout
+		;;
+	mep-*)
+		os=-elf
+		;;
+	mips*-cisco)
+		os=-elf
+		;;
+	mips*-*)
+		os=-elf
+		;;
+	or32-*)
+		os=-coff
+		;;
+	*-tti)	# must be before sparc entry or we get the wrong os.
+		os=-sysv3
+		;;
+	sparc-* | *-sun)
+		os=-sunos4.1.1
+		;;
+	*-be)
+		os=-beos
+		;;
+	*-haiku)
+		os=-haiku
+		;;
+	*-ibm)
+		os=-aix
+		;;
+	*-knuth)
+		os=-mmixware
+		;;
+	*-wec)
+		os=-proelf
+		;;
+	*-winbond)
+		os=-proelf
+		;;
+	*-oki)
+		os=-proelf
+		;;
+	*-hp)
+		os=-hpux
+		;;
+	*-hitachi)
+		os=-hiux
+		;;
+	i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent)
+		os=-sysv
+		;;
+	*-cbm)
+		os=-amigaos
+		;;
+	*-dg)
+		os=-dgux
+		;;
+	*-dolphin)
+		os=-sysv3
+		;;
+	m68k-ccur)
+		os=-rtu
+		;;
+	m88k-omron*)
+		os=-luna
+		;;
+	*-next )
+		os=-nextstep
+		;;
+	*-sequent)
+		os=-ptx
+		;;
+	*-crds)
+		os=-unos
+		;;
+	*-ns)
+		os=-genix
+		;;
+	i370-*)
+		os=-mvs
+		;;
+	*-next)
+		os=-nextstep3
+		;;
+	*-gould)
+		os=-sysv
+		;;
+	*-highlevel)
+		os=-bsd
+		;;
+	*-encore)
+		os=-bsd
+		;;
+	*-sgi)
+		os=-irix
+		;;
+	*-siemens)
+		os=-sysv4
+		;;
+	*-masscomp)
+		os=-rtu
+		;;
+	f30[01]-fujitsu | f700-fujitsu)
+		os=-uxpv
+		;;
+	*-rom68k)
+		os=-coff
+		;;
+	*-*bug)
+		os=-coff
+		;;
+	*-apple)
+		os=-macos
+		;;
+	*-atari*)
+		os=-mint
+		;;
+	*)
+		os=-none
+		;;
+esac
+fi
+
+# Here we handle the case where we know the os, and the CPU type, but not the
+# manufacturer.  We pick the logical manufacturer.
+vendor=unknown
+case $basic_machine in
+	*-unknown)
+		case $os in
+			-riscix*)
+				vendor=acorn
+				;;
+			-sunos*)
+				vendor=sun
+				;;
+			-cnk*|-aix*)
+				vendor=ibm
+				;;
+			-beos*)
+				vendor=be
+				;;
+			-hpux*)
+				vendor=hp
+				;;
+			-mpeix*)
+				vendor=hp
+				;;
+			-hiux*)
+				vendor=hitachi
+				;;
+			-unos*)
+				vendor=crds
+				;;
+			-dgux*)
+				vendor=dg
+				;;
+			-luna*)
+				vendor=omron
+				;;
+			-genix*)
+				vendor=ns
+				;;
+			-mvs* | -opened*)
+				vendor=ibm
+				;;
+			-os400*)
+				vendor=ibm
+				;;
+			-ptx*)
+				vendor=sequent
+				;;
+			-tpf*)
+				vendor=ibm
+				;;
+			-vxsim* | -vxworks* | -windiss*)
+				vendor=wrs
+				;;
+			-aux*)
+				vendor=apple
+				;;
+			-hms*)
+				vendor=hitachi
+				;;
+			-mpw* | -macos*)
+				vendor=apple
+				;;
+			-*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*)
+				vendor=atari
+				;;
+			-vos*)
+				vendor=stratus
+				;;
+		esac
+		basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"`
+		;;
+esac
+
+echo $basic_machine$os
+exit
+
+# Local variables:
+# eval: (add-hook 'write-file-hooks 'time-stamp)
+# time-stamp-start: "timestamp='"
+# time-stamp-format: "%:y-%02m-%02d"
+# time-stamp-end: "'"
+# End:
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/configure
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/configure
@@ -0,0 +1,17418 @@
+#! /bin/sh
+# From configure.ac Revision.
+# Guess values for system-dependent variables and create Makefiles.
+# Generated by GNU Autoconf 2.69 for avr-libc 2.0.0.
+#
+# Report bugs to <avr-libc-dev@nongnu.org>.
+#
+#
+# Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+#
+#
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+## -------------------- ##
+## M4sh Initialization. ##
+## -------------------- ##
+
+# Be more Bourne compatible
+DUALCASE=1; export DUALCASE # for MKS sh
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
+  emulate sh
+  NULLCMD=:
+  # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '${1+"$@"}'='"$@"'
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in #(
+  *posix*) :
+    set -o posix ;; #(
+  *) :
+     ;;
+esac
+fi
+
+
+as_nl='
+'
+export as_nl
+# Printing a long string crashes Solaris 7 /usr/bin/printf.
+as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
+# Prefer a ksh shell builtin over an external printf program on Solaris,
+# but without wasting forks for bash or zsh.
+if test -z "$BASH_VERSION$ZSH_VERSION" \
+    && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
+  as_echo='print -r --'
+  as_echo_n='print -rn --'
+elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
+  as_echo='printf %s\n'
+  as_echo_n='printf %s'
+else
+  if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
+    as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
+    as_echo_n='/usr/ucb/echo -n'
+  else
+    as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
+    as_echo_n_body='eval
+      arg=$1;
+      case $arg in #(
+      *"$as_nl"*)
+	expr "X$arg" : "X\\(.*\\)$as_nl";
+	arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
+      esac;
+      expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
+    '
+    export as_echo_n_body
+    as_echo_n='sh -c $as_echo_n_body as_echo'
+  fi
+  export as_echo_body
+  as_echo='sh -c $as_echo_body as_echo'
+fi
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  PATH_SEPARATOR=:
+  (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
+    (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
+      PATH_SEPARATOR=';'
+  }
+fi
+
+
+# IFS
+# We need space, tab and new line, in precisely that order.  Quoting is
+# there to prevent editors from complaining about space-tab.
+# (If _AS_PATH_WALK were called with IFS unset, it would disable word
+# splitting by setting IFS to empty value.)
+IFS=" ""	$as_nl"
+
+# Find who we are.  Look in the path if we contain no directory separator.
+as_myself=
+case $0 in #((
+  *[\\/]* ) as_myself=$0 ;;
+  *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+  done
+IFS=$as_save_IFS
+
+     ;;
+esac
+# We did not find ourselves, most probably we were run as `sh COMMAND'
+# in which case we are not to be found in the path.
+if test "x$as_myself" = x; then
+  as_myself=$0
+fi
+if test ! -f "$as_myself"; then
+  $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
+  exit 1
+fi
+
+# Unset variables that we do not need and which cause bugs (e.g. in
+# pre-3.0 UWIN ksh).  But do not cause bugs in bash 2.01; the "|| exit 1"
+# suppresses any "Segmentation fault" message there.  '((' could
+# trigger a bug in pdksh 5.2.14.
+for as_var in BASH_ENV ENV MAIL MAILPATH
+do eval test x\${$as_var+set} = xset \
+  && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
+done
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+LC_ALL=C
+export LC_ALL
+LANGUAGE=C
+export LANGUAGE
+
+# CDPATH.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+# Use a proper internal environment variable to ensure we don't fall
+  # into an infinite loop, continuously re-executing ourselves.
+  if test x"${_as_can_reexec}" != xno && test "x$CONFIG_SHELL" != x; then
+    _as_can_reexec=no; export _as_can_reexec;
+    # We cannot yet assume a decent shell, so we have to provide a
+# neutralization value for shells without unset; and this also
+# works around shells that cannot unset nonexistent variables.
+# Preserve -v and -x to the replacement shell.
+BASH_ENV=/dev/null
+ENV=/dev/null
+(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV
+case $- in # ((((
+  *v*x* | *x*v* ) as_opts=-vx ;;
+  *v* ) as_opts=-v ;;
+  *x* ) as_opts=-x ;;
+  * ) as_opts= ;;
+esac
+exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"}
+# Admittedly, this is quite paranoid, since all the known shells bail
+# out after a failed `exec'.
+$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2
+as_fn_exit 255
+  fi
+  # We don't want this to propagate to other subprocesses.
+          { _as_can_reexec=; unset _as_can_reexec;}
+if test "x$CONFIG_SHELL" = x; then
+  as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then :
+  emulate sh
+  NULLCMD=:
+  # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '\${1+\"\$@\"}'='\"\$@\"'
+  setopt NO_GLOB_SUBST
+else
+  case \`(set -o) 2>/dev/null\` in #(
+  *posix*) :
+    set -o posix ;; #(
+  *) :
+     ;;
+esac
+fi
+"
+  as_required="as_fn_return () { (exit \$1); }
+as_fn_success () { as_fn_return 0; }
+as_fn_failure () { as_fn_return 1; }
+as_fn_ret_success () { return 0; }
+as_fn_ret_failure () { return 1; }
+
+exitcode=0
+as_fn_success || { exitcode=1; echo as_fn_success failed.; }
+as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; }
+as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; }
+as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; }
+if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then :
+
+else
+  exitcode=1; echo positional parameters were not saved.
+fi
+test x\$exitcode = x0 || exit 1
+test -x / || exit 1"
+  as_suggested="  as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO
+  as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO
+  eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" &&
+  test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1"
+  if (eval "$as_required") 2>/dev/null; then :
+  as_have_required=yes
+else
+  as_have_required=no
+fi
+  if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then :
+
+else
+  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+as_found=false
+for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  as_found=:
+  case $as_dir in #(
+	 /*)
+	   for as_base in sh bash ksh sh5; do
+	     # Try only shells that exist, to save several forks.
+	     as_shell=$as_dir/$as_base
+	     if { test -f "$as_shell" || test -f "$as_shell.exe"; } &&
+		    { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then :
+  CONFIG_SHELL=$as_shell as_have_required=yes
+		   if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then :
+  break 2
+fi
+fi
+	   done;;
+       esac
+  as_found=false
+done
+$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } &&
+	      { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then :
+  CONFIG_SHELL=$SHELL as_have_required=yes
+fi; }
+IFS=$as_save_IFS
+
+
+      if test "x$CONFIG_SHELL" != x; then :
+  export CONFIG_SHELL
+             # We cannot yet assume a decent shell, so we have to provide a
+# neutralization value for shells without unset; and this also
+# works around shells that cannot unset nonexistent variables.
+# Preserve -v and -x to the replacement shell.
+BASH_ENV=/dev/null
+ENV=/dev/null
+(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV
+case $- in # ((((
+  *v*x* | *x*v* ) as_opts=-vx ;;
+  *v* ) as_opts=-v ;;
+  *x* ) as_opts=-x ;;
+  * ) as_opts= ;;
+esac
+exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"}
+# Admittedly, this is quite paranoid, since all the known shells bail
+# out after a failed `exec'.
+$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2
+exit 255
+fi
+
+    if test x$as_have_required = xno; then :
+  $as_echo "$0: This script requires a shell more modern than all"
+  $as_echo "$0: the shells that I found on your system."
+  if test x${ZSH_VERSION+set} = xset ; then
+    $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should"
+    $as_echo "$0: be upgraded to zsh 4.3.4 or later."
+  else
+    $as_echo "$0: Please tell bug-autoconf@gnu.org and
+$0: avr-libc-dev@nongnu.org about your system, including
+$0: any error possibly output before this message. Then
+$0: install a modern shell, or manually run the script
+$0: under such a shell if you do have one."
+  fi
+  exit 1
+fi
+fi
+fi
+SHELL=${CONFIG_SHELL-/bin/sh}
+export SHELL
+# Unset more variables known to interfere with behavior of common tools.
+CLICOLOR_FORCE= GREP_OPTIONS=
+unset CLICOLOR_FORCE GREP_OPTIONS
+
+## --------------------- ##
+## M4sh Shell Functions. ##
+## --------------------- ##
+# as_fn_unset VAR
+# ---------------
+# Portably unset VAR.
+as_fn_unset ()
+{
+  { eval $1=; unset $1;}
+}
+as_unset=as_fn_unset
+
+# as_fn_set_status STATUS
+# -----------------------
+# Set $? to STATUS, without forking.
+as_fn_set_status ()
+{
+  return $1
+} # as_fn_set_status
+
+# as_fn_exit STATUS
+# -----------------
+# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
+as_fn_exit ()
+{
+  set +e
+  as_fn_set_status $1
+  exit $1
+} # as_fn_exit
+
+# as_fn_mkdir_p
+# -------------
+# Create "$as_dir" as a directory, including parents if necessary.
+as_fn_mkdir_p ()
+{
+
+  case $as_dir in #(
+  -*) as_dir=./$as_dir;;
+  esac
+  test -d "$as_dir" || eval $as_mkdir_p || {
+    as_dirs=
+    while :; do
+      case $as_dir in #(
+      *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
+      *) as_qdir=$as_dir;;
+      esac
+      as_dirs="'$as_qdir' $as_dirs"
+      as_dir=`$as_dirname -- "$as_dir" ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$as_dir" : 'X\(//\)[^/]' \| \
+	 X"$as_dir" : 'X\(//\)$' \| \
+	 X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$as_dir" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+      test -d "$as_dir" && break
+    done
+    test -z "$as_dirs" || eval "mkdir $as_dirs"
+  } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir"
+
+
+} # as_fn_mkdir_p
+
+# as_fn_executable_p FILE
+# -----------------------
+# Test if FILE is an executable regular file.
+as_fn_executable_p ()
+{
+  test -f "$1" && test -x "$1"
+} # as_fn_executable_p
+# as_fn_append VAR VALUE
+# ----------------------
+# Append the text in VALUE to the end of the definition contained in VAR. Take
+# advantage of any shell optimizations that allow amortized linear growth over
+# repeated appends, instead of the typical quadratic growth present in naive
+# implementations.
+if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
+  eval 'as_fn_append ()
+  {
+    eval $1+=\$2
+  }'
+else
+  as_fn_append ()
+  {
+    eval $1=\$$1\$2
+  }
+fi # as_fn_append
+
+# as_fn_arith ARG...
+# ------------------
+# Perform arithmetic evaluation on the ARGs, and store the result in the
+# global $as_val. Take advantage of shells that can avoid forks. The arguments
+# must be portable across $(()) and expr.
+if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
+  eval 'as_fn_arith ()
+  {
+    as_val=$(( $* ))
+  }'
+else
+  as_fn_arith ()
+  {
+    as_val=`expr "$@" || test $? -eq 1`
+  }
+fi # as_fn_arith
+
+
+# as_fn_error STATUS ERROR [LINENO LOG_FD]
+# ----------------------------------------
+# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
+# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
+# script with STATUS, using 1 if that was 0.
+as_fn_error ()
+{
+  as_status=$1; test $as_status -eq 0 && as_status=1
+  if test "$4"; then
+    as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+    $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4
+  fi
+  $as_echo "$as_me: error: $2" >&2
+  as_fn_exit $as_status
+} # as_fn_error
+
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+   test "X`expr 00001 : '.*\(...\)'`" = X001; then
+  as_expr=expr
+else
+  as_expr=false
+fi
+
+if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
+  as_basename=basename
+else
+  as_basename=false
+fi
+
+if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
+  as_dirname=dirname
+else
+  as_dirname=false
+fi
+
+as_me=`$as_basename -- "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+	 X"$0" : 'X\(//\)$' \| \
+	 X"$0" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X/"$0" |
+    sed '/^.*\/\([^/][^/]*\)\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\/\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\/\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+
+  as_lineno_1=$LINENO as_lineno_1a=$LINENO
+  as_lineno_2=$LINENO as_lineno_2a=$LINENO
+  eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" &&
+  test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || {
+  # Blame Lee E. McMahon (1931-1989) for sed's syntax.  :-)
+  sed -n '
+    p
+    /[$]LINENO/=
+  ' <$as_myself |
+    sed '
+      s/[$]LINENO.*/&-/
+      t lineno
+      b
+      :lineno
+      N
+      :loop
+      s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/
+      t loop
+      s/-\n.*//
+    ' >$as_me.lineno &&
+  chmod +x "$as_me.lineno" ||
+    { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; }
+
+  # If we had to re-execute with $CONFIG_SHELL, we're ensured to have
+  # already done that, so ensure we don't try to do so again and fall
+  # in an infinite loop.  This has already happened in practice.
+  _as_can_reexec=no; export _as_can_reexec
+  # Don't try to exec as it changes $[0], causing all sort of problems
+  # (the dirname of $[0] is not the place where we might find the
+  # original and so on.  Autoconf is especially sensitive to this).
+  . "./$as_me.lineno"
+  # Exit status is that of the last command.
+  exit
+}
+
+ECHO_C= ECHO_N= ECHO_T=
+case `echo -n x` in #(((((
+-n*)
+  case `echo 'xy\c'` in
+  *c*) ECHO_T='	';;	# ECHO_T is single tab character.
+  xy)  ECHO_C='\c';;
+  *)   echo `echo ksh88 bug on AIX 6.1` > /dev/null
+       ECHO_T='	';;
+  esac;;
+*)
+  ECHO_N='-n';;
+esac
+
+rm -f conf$$ conf$$.exe conf$$.file
+if test -d conf$$.dir; then
+  rm -f conf$$.dir/conf$$.file
+else
+  rm -f conf$$.dir
+  mkdir conf$$.dir 2>/dev/null
+fi
+if (echo >conf$$.file) 2>/dev/null; then
+  if ln -s conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s='ln -s'
+    # ... but there are two gotchas:
+    # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
+    # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
+    # In both cases, we have to default to `cp -pR'.
+    ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
+      as_ln_s='cp -pR'
+  elif ln conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s=ln
+  else
+    as_ln_s='cp -pR'
+  fi
+else
+  as_ln_s='cp -pR'
+fi
+rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
+rmdir conf$$.dir 2>/dev/null
+
+if mkdir -p . 2>/dev/null; then
+  as_mkdir_p='mkdir -p "$as_dir"'
+else
+  test -d ./-p && rmdir ./-p
+  as_mkdir_p=false
+fi
+
+as_test_x='test -x'
+as_executable_p=as_fn_executable_p
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+as_awk_strverscmp='
+  # Use only awk features that work with 7th edition Unix awk (1978).
+  # My, what an old awk you have, Mr. Solaris!
+  END {
+    while (length(v1) && length(v2)) {
+      # Set d1 to be the next thing to compare from v1, and likewise for d2.
+      # Normally this is a single character, but if v1 and v2 contain digits,
+      # compare them as integers and fractions as strverscmp does.
+      if (v1 ~ /^[0-9]/ && v2 ~ /^[0-9]/) {
+	# Split v1 and v2 into their leading digit string components d1 and d2,
+	# and advance v1 and v2 past the leading digit strings.
+	for (len1 = 1; substr(v1, len1 + 1) ~ /^[0-9]/; len1++) continue
+	for (len2 = 1; substr(v2, len2 + 1) ~ /^[0-9]/; len2++) continue
+	d1 = substr(v1, 1, len1); v1 = substr(v1, len1 + 1)
+	d2 = substr(v2, 1, len2); v2 = substr(v2, len2 + 1)
+	if (d1 ~ /^0/) {
+	  if (d2 ~ /^0/) {
+	    # Compare two fractions.
+	    while (d1 ~ /^0/ && d2 ~ /^0/) {
+	      d1 = substr(d1, 2); len1--
+	      d2 = substr(d2, 2); len2--
+	    }
+	    if (len1 != len2 && ! (len1 && len2 && substr(d1, 1, 1) == substr(d2, 1, 1))) {
+	      # The two components differ in length, and the common prefix
+	      # contains only leading zeros.  Consider the longer to be less.
+	      d1 = -len1
+	      d2 = -len2
+	    } else {
+	      # Otherwise, compare as strings.
+	      d1 = "x" d1
+	      d2 = "x" d2
+	    }
+	  } else {
+	    # A fraction is less than an integer.
+	    exit 1
+	  }
+	} else {
+	  if (d2 ~ /^0/) {
+	    # An integer is greater than a fraction.
+	    exit 2
+	  } else {
+	    # Compare two integers.
+	    d1 += 0
+	    d2 += 0
+	  }
+	}
+      } else {
+	# The normal case, without worrying about digits.
+	d1 = substr(v1, 1, 1); v1 = substr(v1, 2)
+	d2 = substr(v2, 1, 1); v2 = substr(v2, 2)
+      }
+      if (d1 < d2) exit 1
+      if (d1 > d2) exit 2
+    }
+    # Beware Solaris /usr/xgp4/bin/awk (at least through Solaris 10),
+    # which mishandles some comparisons of empty strings to integers.
+    if (length(v2)) exit 1
+    if (length(v1)) exit 2
+  }
+'
+
+test -n "$DJDIR" || exec 7<&0 </dev/null
+exec 6>&1
+
+# Name of the host.
+# hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status,
+# so uname gets run too.
+ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
+
+#
+# Initializations.
+#
+ac_default_prefix=/usr/local
+ac_clean_files=
+ac_config_libobj_dir=.
+LIBOBJS=
+cross_compiling=no
+subdirs=
+MFLAGS=
+MAKEFLAGS=
+
+# Identity of this package.
+PACKAGE_NAME='avr-libc'
+PACKAGE_TARNAME='avr-libc'
+PACKAGE_VERSION='2.0.0'
+PACKAGE_STRING='avr-libc 2.0.0'
+PACKAGE_BUGREPORT='avr-libc-dev@nongnu.org'
+PACKAGE_URL=''
+
+ac_unique_file="doc/examples/demo/demo.c"
+ac_no_link=no
+ac_subst_vars='am__EXEEXT_FALSE
+am__EXEEXT_TRUE
+LTLIBOBJS
+LIBOBJS
+HAS_attiny40_FALSE
+HAS_attiny40_TRUE
+HAS_attiny20_FALSE
+HAS_attiny20_TRUE
+HAS_attiny10_FALSE
+HAS_attiny10_TRUE
+HAS_attiny9_FALSE
+HAS_attiny9_TRUE
+HAS_attiny5_FALSE
+HAS_attiny5_TRUE
+HAS_attiny4_FALSE
+HAS_attiny4_TRUE
+HAS_avrtiny_FALSE
+HAS_avrtiny_TRUE
+HAS_atxmega128a4u_FALSE
+HAS_atxmega128a4u_TRUE
+HAS_atxmega128a1u_FALSE
+HAS_atxmega128a1u_TRUE
+HAS_atxmega128a1_FALSE
+HAS_atxmega128a1_TRUE
+HAS_avrxmega7_FALSE
+HAS_avrxmega7_TRUE
+HAS_atxmega384d3_FALSE
+HAS_atxmega384d3_TRUE
+HAS_atxmega384c3_FALSE
+HAS_atxmega384c3_TRUE
+HAS_atxmega256d3_FALSE
+HAS_atxmega256d3_TRUE
+HAS_atxmega256c3_FALSE
+HAS_atxmega256c3_TRUE
+HAS_atxmega256a3bu_FALSE
+HAS_atxmega256a3bu_TRUE
+HAS_atxmega256a3b_FALSE
+HAS_atxmega256a3b_TRUE
+HAS_atxmega256a3u_FALSE
+HAS_atxmega256a3u_TRUE
+HAS_atxmega256a3_FALSE
+HAS_atxmega256a3_TRUE
+HAS_atxmega192d3_FALSE
+HAS_atxmega192d3_TRUE
+HAS_atxmega192c3_FALSE
+HAS_atxmega192c3_TRUE
+HAS_atxmega192a3u_FALSE
+HAS_atxmega192a3u_TRUE
+HAS_atxmega192a3_FALSE
+HAS_atxmega192a3_TRUE
+HAS_atxmega128d4_FALSE
+HAS_atxmega128d4_TRUE
+HAS_atxmega128d3_FALSE
+HAS_atxmega128d3_TRUE
+HAS_atxmega128c3_FALSE
+HAS_atxmega128c3_TRUE
+HAS_atxmega128b3_FALSE
+HAS_atxmega128b3_TRUE
+HAS_atxmega128b1_FALSE
+HAS_atxmega128b1_TRUE
+HAS_atxmega128a3u_FALSE
+HAS_atxmega128a3u_TRUE
+HAS_atxmega128a3_FALSE
+HAS_atxmega128a3_TRUE
+HAS_avrxmega6_FALSE
+HAS_avrxmega6_TRUE
+HAS_atxmega64a1u_FALSE
+HAS_atxmega64a1u_TRUE
+HAS_atxmega64a1_FALSE
+HAS_atxmega64a1_TRUE
+HAS_avrxmega5_FALSE
+HAS_avrxmega5_TRUE
+HAS_atxmega64d4_FALSE
+HAS_atxmega64d4_TRUE
+HAS_atxmega64d3_FALSE
+HAS_atxmega64d3_TRUE
+HAS_atxmega64c3_FALSE
+HAS_atxmega64c3_TRUE
+HAS_atxmega64b3_FALSE
+HAS_atxmega64b3_TRUE
+HAS_atxmega64b1_FALSE
+HAS_atxmega64b1_TRUE
+HAS_atxmega64a4u_FALSE
+HAS_atxmega64a4u_TRUE
+HAS_atxmega64a3u_FALSE
+HAS_atxmega64a3u_TRUE
+HAS_atxmega64a3_FALSE
+HAS_atxmega64a3_TRUE
+HAS_avrxmega4_FALSE
+HAS_avrxmega4_TRUE
+HAS_avrxmega3_FALSE
+HAS_avrxmega3_TRUE
+HAS_atxmega32e5_FALSE
+HAS_atxmega32e5_TRUE
+HAS_atxmega16e5_FALSE
+HAS_atxmega16e5_TRUE
+HAS_atxmega32d4_FALSE
+HAS_atxmega32d4_TRUE
+HAS_atxmega32d3_FALSE
+HAS_atxmega32d3_TRUE
+HAS_atxmega32c4_FALSE
+HAS_atxmega32c4_TRUE
+HAS_atxmega32c3_FALSE
+HAS_atxmega32c3_TRUE
+HAS_atxmega32a4u_FALSE
+HAS_atxmega32a4u_TRUE
+HAS_atxmega32a4_FALSE
+HAS_atxmega32a4_TRUE
+HAS_atxmega16d4_FALSE
+HAS_atxmega16d4_TRUE
+HAS_atxmega16c4_FALSE
+HAS_atxmega16c4_TRUE
+HAS_atxmega16a4u_FALSE
+HAS_atxmega16a4u_TRUE
+HAS_atxmega16a4_FALSE
+HAS_atxmega16a4_TRUE
+HAS_atxmega8e5_FALSE
+HAS_atxmega8e5_TRUE
+HAS_avrxmega2_FALSE
+HAS_avrxmega2_TRUE
+HAS_atmega256rfr2_FALSE
+HAS_atmega256rfr2_TRUE
+HAS_atmega2564rfr2_FALSE
+HAS_atmega2564rfr2_TRUE
+HAS_atmega2561_FALSE
+HAS_atmega2561_TRUE
+HAS_atmega2560_FALSE
+HAS_atmega2560_TRUE
+HAS_avr6_FALSE
+HAS_avr6_TRUE
+HAS_atmega128rfr2_FALSE
+HAS_atmega128rfr2_TRUE
+HAS_atmega1284rfr2_FALSE
+HAS_atmega1284rfr2_TRUE
+HAS_at90usb1287_FALSE
+HAS_at90usb1287_TRUE
+HAS_at90usb1286_FALSE
+HAS_at90usb1286_TRUE
+HAS_at90can128_FALSE
+HAS_at90can128_TRUE
+HAS_atmega1284p_FALSE
+HAS_atmega1284p_TRUE
+HAS_atmega1284_FALSE
+HAS_atmega1284_TRUE
+HAS_atmega1281_FALSE
+HAS_atmega1281_TRUE
+HAS_atmega1280_FALSE
+HAS_atmega1280_TRUE
+HAS_atmega128a_FALSE
+HAS_atmega128a_TRUE
+HAS_atmega128_FALSE
+HAS_atmega128_TRUE
+HAS_avr51_FALSE
+HAS_avr51_TRUE
+HAS_m3000_FALSE
+HAS_m3000_TRUE
+HAS_atmega128rfa1_FALSE
+HAS_atmega128rfa1_TRUE
+HAS_atmega64m1_FALSE
+HAS_atmega64m1_TRUE
+HAS_atmega64hve2_FALSE
+HAS_atmega64hve2_TRUE
+HAS_atmega64hve_FALSE
+HAS_atmega64hve_TRUE
+HAS_atmega64c1_FALSE
+HAS_atmega64c1_TRUE
+HAS_atmega6490p_FALSE
+HAS_atmega6490p_TRUE
+HAS_atmega6490a_FALSE
+HAS_atmega6490a_TRUE
+HAS_atmega6490_FALSE
+HAS_atmega6490_TRUE
+HAS_atmega649p_FALSE
+HAS_atmega649p_TRUE
+HAS_atmega649a_FALSE
+HAS_atmega649a_TRUE
+HAS_atmega649_FALSE
+HAS_atmega649_TRUE
+HAS_atmega6450p_FALSE
+HAS_atmega6450p_TRUE
+HAS_atmega6450a_FALSE
+HAS_atmega6450a_TRUE
+HAS_atmega6450_FALSE
+HAS_atmega6450_TRUE
+HAS_atmega645p_FALSE
+HAS_atmega645p_TRUE
+HAS_atmega645a_FALSE
+HAS_atmega645a_TRUE
+HAS_atmega645_FALSE
+HAS_atmega645_TRUE
+HAS_atmega644pa_FALSE
+HAS_atmega644pa_TRUE
+HAS_atmega644p_FALSE
+HAS_atmega644p_TRUE
+HAS_atmega644a_FALSE
+HAS_atmega644a_TRUE
+HAS_atmega644_FALSE
+HAS_atmega644_TRUE
+HAS_atmega640_FALSE
+HAS_atmega640_TRUE
+HAS_atmega64a_FALSE
+HAS_atmega64a_TRUE
+HAS_atmega64_FALSE
+HAS_atmega64_TRUE
+HAS_atmega64rfr2_FALSE
+HAS_atmega64rfr2_TRUE
+HAS_atmega644rfr2_FALSE
+HAS_atmega644rfr2_TRUE
+HAS_atmega406_FALSE
+HAS_atmega406_TRUE
+HAS_atmega32u6_FALSE
+HAS_atmega32u6_TRUE
+HAS_atmega32u4_FALSE
+HAS_atmega32u4_TRUE
+HAS_atmega32m1_FALSE
+HAS_atmega32m1_TRUE
+HAS_atmega32hvbrevb_FALSE
+HAS_atmega32hvbrevb_TRUE
+HAS_atmega32hvb_FALSE
+HAS_atmega32hvb_TRUE
+HAS_atmega32c1_FALSE
+HAS_atmega32c1_TRUE
+HAS_atmega3290pa_FALSE
+HAS_atmega3290pa_TRUE
+HAS_atmega3290p_FALSE
+HAS_atmega3290p_TRUE
+HAS_atmega3290a_FALSE
+HAS_atmega3290a_TRUE
+HAS_atmega3290_FALSE
+HAS_atmega3290_TRUE
+HAS_atmega329pa_FALSE
+HAS_atmega329pa_TRUE
+HAS_atmega329p_FALSE
+HAS_atmega329p_TRUE
+HAS_atmega329a_FALSE
+HAS_atmega329a_TRUE
+HAS_atmega329_FALSE
+HAS_atmega329_TRUE
+HAS_atmega328p_FALSE
+HAS_atmega328p_TRUE
+HAS_atmega328_FALSE
+HAS_atmega328_TRUE
+HAS_atmega3250pa_FALSE
+HAS_atmega3250pa_TRUE
+HAS_atmega3250p_FALSE
+HAS_atmega3250p_TRUE
+HAS_atmega3250a_FALSE
+HAS_atmega3250a_TRUE
+HAS_atmega3250_FALSE
+HAS_atmega3250_TRUE
+HAS_atmega325pa_FALSE
+HAS_atmega325pa_TRUE
+HAS_atmega325p_FALSE
+HAS_atmega325p_TRUE
+HAS_atmega325a_FALSE
+HAS_atmega325a_TRUE
+HAS_atmega325_FALSE
+HAS_atmega325_TRUE
+HAS_atmega324pa_FALSE
+HAS_atmega324pa_TRUE
+HAS_atmega324p_FALSE
+HAS_atmega324p_TRUE
+HAS_atmega324a_FALSE
+HAS_atmega324a_TRUE
+HAS_atmega323_FALSE
+HAS_atmega323_TRUE
+HAS_atmega32a_FALSE
+HAS_atmega32a_TRUE
+HAS_atmega32_FALSE
+HAS_atmega32_TRUE
+HAS_atmega16u4_FALSE
+HAS_atmega16u4_TRUE
+HAS_atmega16m1_FALSE
+HAS_atmega16m1_TRUE
+HAS_atmega16hvbrevb_FALSE
+HAS_atmega16hvbrevb_TRUE
+HAS_atmega16hvb_FALSE
+HAS_atmega16hvb_TRUE
+HAS_atmega16hva2_FALSE
+HAS_atmega16hva2_TRUE
+HAS_atmega16hva_FALSE
+HAS_atmega16hva_TRUE
+HAS_atmega169pa_FALSE
+HAS_atmega169pa_TRUE
+HAS_atmega169p_FALSE
+HAS_atmega169p_TRUE
+HAS_atmega169a_FALSE
+HAS_atmega169a_TRUE
+HAS_atmega169_FALSE
+HAS_atmega169_TRUE
+HAS_atmega168pb_FALSE
+HAS_atmega168pb_TRUE
+HAS_atmega168pa_FALSE
+HAS_atmega168pa_TRUE
+HAS_atmega168p_FALSE
+HAS_atmega168p_TRUE
+HAS_atmega168a_FALSE
+HAS_atmega168a_TRUE
+HAS_atmega168_FALSE
+HAS_atmega168_TRUE
+HAS_atmega165pa_FALSE
+HAS_atmega165pa_TRUE
+HAS_atmega165p_FALSE
+HAS_atmega165p_TRUE
+HAS_atmega165a_FALSE
+HAS_atmega165a_TRUE
+HAS_atmega165_FALSE
+HAS_atmega165_TRUE
+HAS_atmega164pa_FALSE
+HAS_atmega164pa_TRUE
+HAS_atmega164p_FALSE
+HAS_atmega164p_TRUE
+HAS_atmega164a_FALSE
+HAS_atmega164a_TRUE
+HAS_atmega163_FALSE
+HAS_atmega163_TRUE
+HAS_atmega162_FALSE
+HAS_atmega162_TRUE
+HAS_atmega161_FALSE
+HAS_atmega161_TRUE
+HAS_atmega16a_FALSE
+HAS_atmega16a_TRUE
+HAS_atmega16_FALSE
+HAS_atmega16_TRUE
+HAS_ata8510_FALSE
+HAS_ata8510_TRUE
+HAS_ata8210_FALSE
+HAS_ata8210_TRUE
+HAS_ata6614q_FALSE
+HAS_ata6614q_TRUE
+HAS_ata6613c_FALSE
+HAS_ata6613c_TRUE
+HAS_ata5831_FALSE
+HAS_ata5831_TRUE
+HAS_ata5795_FALSE
+HAS_ata5795_TRUE
+HAS_ata5791_FALSE
+HAS_ata5791_TRUE
+HAS_ata5790n_FALSE
+HAS_ata5790n_TRUE
+HAS_ata5790_FALSE
+HAS_ata5790_TRUE
+HAS_ata5782_FALSE
+HAS_ata5782_TRUE
+HAS_ata5702m322_FALSE
+HAS_ata5702m322_TRUE
+HAS_at94k_FALSE
+HAS_at94k_TRUE
+HAS_at90pwm161_FALSE
+HAS_at90pwm161_TRUE
+HAS_at90pwm216_FALSE
+HAS_at90pwm216_TRUE
+HAS_at90pwm316_FALSE
+HAS_at90pwm316_TRUE
+HAS_at90usb647_FALSE
+HAS_at90usb647_TRUE
+HAS_at90usb646_FALSE
+HAS_at90usb646_TRUE
+HAS_at90scr100_FALSE
+HAS_at90scr100_TRUE
+HAS_at90can64_FALSE
+HAS_at90can64_TRUE
+HAS_at90can32_FALSE
+HAS_at90can32_TRUE
+HAS_avr5_FALSE
+HAS_avr5_TRUE
+HAS_at90pwm81_FALSE
+HAS_at90pwm81_TRUE
+HAS_at90pwm3b_FALSE
+HAS_at90pwm3b_TRUE
+HAS_at90pwm3_FALSE
+HAS_at90pwm3_TRUE
+HAS_at90pwm2b_FALSE
+HAS_at90pwm2b_TRUE
+HAS_at90pwm2_FALSE
+HAS_at90pwm2_TRUE
+HAS_at90pwm1_FALSE
+HAS_at90pwm1_TRUE
+HAS_atmega8hva_FALSE
+HAS_atmega8hva_TRUE
+HAS_atmega88pb_FALSE
+HAS_atmega88pb_TRUE
+HAS_atmega88pa_FALSE
+HAS_atmega88pa_TRUE
+HAS_atmega88p_FALSE
+HAS_atmega88p_TRUE
+HAS_atmega88a_FALSE
+HAS_atmega88a_TRUE
+HAS_atmega88_FALSE
+HAS_atmega88_TRUE
+HAS_atmega48p_FALSE
+HAS_atmega48p_TRUE
+HAS_atmega48pb_FALSE
+HAS_atmega48pb_TRUE
+HAS_atmega48pa_FALSE
+HAS_atmega48pa_TRUE
+HAS_atmega48a_FALSE
+HAS_atmega48a_TRUE
+HAS_atmega48_FALSE
+HAS_atmega48_TRUE
+HAS_atmega8a_FALSE
+HAS_atmega8a_TRUE
+HAS_ata6612c_FALSE
+HAS_ata6612c_TRUE
+HAS_ata6289_FALSE
+HAS_ata6289_TRUE
+HAS_ata6286_FALSE
+HAS_ata6286_TRUE
+HAS_ata6285_FALSE
+HAS_ata6285_TRUE
+HAS_atmega8535_FALSE
+HAS_atmega8535_TRUE
+HAS_atmega8515_FALSE
+HAS_atmega8515_TRUE
+HAS_atmega8_FALSE
+HAS_atmega8_TRUE
+HAS_avr4_FALSE
+HAS_avr4_TRUE
+HAS_attiny1634_FALSE
+HAS_attiny1634_TRUE
+HAS_attiny167_FALSE
+HAS_attiny167_TRUE
+HAS_atmega32u2_FALSE
+HAS_atmega32u2_TRUE
+HAS_atmega16u2_FALSE
+HAS_atmega16u2_TRUE
+HAS_atmega8u2_FALSE
+HAS_atmega8u2_TRUE
+HAS_ata664251_FALSE
+HAS_ata664251_TRUE
+HAS_ata6617c_FALSE
+HAS_ata6617c_TRUE
+HAS_ata5505_FALSE
+HAS_ata5505_TRUE
+HAS_at90usb162_FALSE
+HAS_at90usb162_TRUE
+HAS_at90usb82_FALSE
+HAS_at90usb82_TRUE
+HAS_avr35_FALSE
+HAS_avr35_TRUE
+HAS_atmega103_FALSE
+HAS_atmega103_TRUE
+HAS_avr31_FALSE
+HAS_avr31_TRUE
+HAS_at76c711_FALSE
+HAS_at76c711_TRUE
+HAS_at43usb355_FALSE
+HAS_at43usb355_TRUE
+HAS_at43usb320_FALSE
+HAS_at43usb320_TRUE
+HAS_avr3_FALSE
+HAS_avr3_TRUE
+HAS_at86rf401_FALSE
+HAS_at86rf401_TRUE
+HAS_attiny88_FALSE
+HAS_attiny88_TRUE
+HAS_attiny87_FALSE
+HAS_attiny87_TRUE
+HAS_attiny861a_FALSE
+HAS_attiny861a_TRUE
+HAS_attiny861_FALSE
+HAS_attiny861_TRUE
+HAS_attiny85_FALSE
+HAS_attiny85_TRUE
+HAS_attiny84a_FALSE
+HAS_attiny84a_TRUE
+HAS_attiny841_FALSE
+HAS_attiny841_TRUE
+HAS_attiny84_FALSE
+HAS_attiny84_TRUE
+HAS_attiny828_FALSE
+HAS_attiny828_TRUE
+HAS_attiny48_FALSE
+HAS_attiny48_TRUE
+HAS_attiny461a_FALSE
+HAS_attiny461a_TRUE
+HAS_attiny461_FALSE
+HAS_attiny461_TRUE
+HAS_attiny45_FALSE
+HAS_attiny45_TRUE
+HAS_attiny44a_FALSE
+HAS_attiny44a_TRUE
+HAS_attiny441_FALSE
+HAS_attiny441_TRUE
+HAS_attiny44_FALSE
+HAS_attiny44_TRUE
+HAS_attiny4313_FALSE
+HAS_attiny4313_TRUE
+HAS_attiny43u_FALSE
+HAS_attiny43u_TRUE
+HAS_attiny261a_FALSE
+HAS_attiny261a_TRUE
+HAS_attiny261_FALSE
+HAS_attiny261_TRUE
+HAS_attiny25_FALSE
+HAS_attiny25_TRUE
+HAS_attiny24a_FALSE
+HAS_attiny24a_TRUE
+HAS_attiny24_FALSE
+HAS_attiny24_TRUE
+HAS_attiny2313a_FALSE
+HAS_attiny2313a_TRUE
+HAS_attiny2313_FALSE
+HAS_attiny2313_TRUE
+HAS_attiny13a_FALSE
+HAS_attiny13a_TRUE
+HAS_attiny13_FALSE
+HAS_attiny13_TRUE
+HAS_ata6616c_FALSE
+HAS_ata6616c_TRUE
+HAS_ata5272_FALSE
+HAS_ata5272_TRUE
+HAS_avr25_FALSE
+HAS_avr25_TRUE
+HAS_attiny26_FALSE
+HAS_attiny26_TRUE
+HAS_attiny22_FALSE
+HAS_attiny22_TRUE
+HAS_at90s8535_FALSE
+HAS_at90s8535_TRUE
+HAS_at90c8534_FALSE
+HAS_at90c8534_TRUE
+HAS_at90s8515_FALSE
+HAS_at90s8515_TRUE
+HAS_at90s4434_FALSE
+HAS_at90s4434_TRUE
+HAS_at90s4433_FALSE
+HAS_at90s4433_TRUE
+HAS_at90s4414_FALSE
+HAS_at90s4414_TRUE
+HAS_at90s2343_FALSE
+HAS_at90s2343_TRUE
+HAS_at90s2333_FALSE
+HAS_at90s2333_TRUE
+HAS_at90s2323_FALSE
+HAS_at90s2323_TRUE
+HAS_at90s2313_FALSE
+HAS_at90s2313_TRUE
+HAS_avr2_FALSE
+HAS_avr2_TRUE
+HAS_attiny28_FALSE
+HAS_attiny28_TRUE
+HAS_attiny15_FALSE
+HAS_attiny15_TRUE
+HAS_attiny12_FALSE
+HAS_attiny12_TRUE
+HAS_attiny11_FALSE
+HAS_attiny11_TRUE
+HAS_at90s1200_FALSE
+HAS_at90s1200_TRUE
+HAS_avr1_FALSE
+HAS_avr1_TRUE
+HAS_DELAY_CYCLES
+FNO_JUMP_TABLES
+ASDEBUG
+CDEBUG
+DOC_INST_DIR
+AVR_LIBC_USER_MANUAL
+DOCSDIR
+PNMTOPNG
+PNGTOPNM
+INSTALL_DOX_MAN
+INSTALL_DOX_XML
+INSTALL_DOX_HTML
+INSTALL_DOX_PDF
+TARGET_DOX_XML
+TARGET_DOX_HTML
+TARGET_DOX_PDF
+HAS_DEV_LIB_FALSE
+HAS_DEV_LIB_TRUE
+HAS_GCC_5_1_FALSE
+HAS_GCC_5_1_TRUE
+LN_S
+AR
+RANLIB
+am__fastdepCCAS_FALSE
+am__fastdepCCAS_TRUE
+CCASDEPMODE
+CCASFLAGS
+CCAS
+AS
+am__fastdepCC_FALSE
+am__fastdepCC_TRUE
+CCDEPMODE
+am__nodep
+AMDEPBACKSLASH
+AMDEP_FALSE
+AMDEP_TRUE
+am__quote
+am__include
+DEPDIR
+OBJEXT
+EXEEXT
+ac_ct_CC
+CPPFLAGS
+LDFLAGS
+CFLAGS
+CC
+AM_BACKSLASH
+AM_DEFAULT_VERBOSITY
+AM_DEFAULT_V
+AM_V
+am__untar
+am__tar
+AMTAR
+am__leading_dot
+SET_MAKE
+AWK
+mkdir_p
+MKDIR_P
+INSTALL_STRIP_PROGRAM
+STRIP
+install_sh
+MAKEINFO
+AUTOHEADER
+AUTOMAKE
+AUTOCONF
+ACLOCAL
+VERSION
+PACKAGE
+CYGPATH_W
+am__isrc
+INSTALL_DATA
+INSTALL_SCRIPT
+INSTALL_PROGRAM
+host_os
+host_vendor
+host_cpu
+host
+build_os
+build_vendor
+build_cpu
+build
+AVR_LIBC_VERSION_NUMERIC
+AVR_LIBC_VERSION
+AVR_LIBC_RELDATE
+AVR_LIBC_REVISION
+AVR_LIBC_MINOR
+AVR_LIBC_MAJOR
+target_alias
+host_alias
+build_alias
+LIBS
+ECHO_T
+ECHO_N
+ECHO_C
+DEFS
+mandir
+localedir
+libdir
+psdir
+pdfdir
+dvidir
+htmldir
+infodir
+docdir
+oldincludedir
+includedir
+runstatedir
+localstatedir
+sharedstatedir
+sysconfdir
+datadir
+datarootdir
+libexecdir
+sbindir
+bindir
+program_transform_name
+prefix
+exec_prefix
+PACKAGE_URL
+PACKAGE_BUGREPORT
+PACKAGE_STRING
+PACKAGE_VERSION
+PACKAGE_TARNAME
+PACKAGE_NAME
+PATH_SEPARATOR
+SHELL'
+ac_subst_files=''
+ac_user_opts='
+enable_option_checking
+enable_silent_rules
+enable_dependency_tracking
+enable_device_lib
+enable_doc
+enable_html_doc
+enable_xml_doc
+enable_pdf_doc
+enable_man_doc
+enable_versioned_doc
+enable_debug_info
+'
+      ac_precious_vars='build_alias
+host_alias
+target_alias
+CC
+CFLAGS
+LDFLAGS
+LIBS
+CPPFLAGS
+CCAS
+CCASFLAGS'
+
+
+# Initialize some variables set by options.
+ac_init_help=
+ac_init_version=false
+ac_unrecognized_opts=
+ac_unrecognized_sep=
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+cache_file=/dev/null
+exec_prefix=NONE
+no_create=
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+srcdir=
+verbose=
+x_includes=NONE
+x_libraries=NONE
+
+# Installation directory options.
+# These are left unexpanded so users can "make install exec_prefix=/foo"
+# and all the variables that are supposed to be based on exec_prefix
+# by default will actually change.
+# Use braces instead of parens because sh, perl, etc. also accept them.
+# (The list follows the same order as the GNU Coding Standards.)
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datarootdir='${prefix}/share'
+datadir='${datarootdir}'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+runstatedir='${localstatedir}/run'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
+infodir='${datarootdir}/info'
+htmldir='${docdir}'
+dvidir='${docdir}'
+pdfdir='${docdir}'
+psdir='${docdir}'
+libdir='${exec_prefix}/lib'
+localedir='${datarootdir}/locale'
+mandir='${datarootdir}/man'
+
+ac_prev=
+ac_dashdash=
+for ac_option
+do
+  # If the previous option needs an argument, assign it.
+  if test -n "$ac_prev"; then
+    eval $ac_prev=\$ac_option
+    ac_prev=
+    continue
+  fi
+
+  case $ac_option in
+  *=?*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;;
+  *=)   ac_optarg= ;;
+  *)    ac_optarg=yes ;;
+  esac
+
+  # Accept the important Cygnus configure options, so we can diagnose typos.
+
+  case $ac_dashdash$ac_option in
+  --)
+    ac_dashdash=yes ;;
+
+  -bindir | --bindir | --bindi | --bind | --bin | --bi)
+    ac_prev=bindir ;;
+  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+    bindir=$ac_optarg ;;
+
+  -build | --build | --buil | --bui | --bu)
+    ac_prev=build_alias ;;
+  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+    build_alias=$ac_optarg ;;
+
+  -cache-file | --cache-file | --cache-fil | --cache-fi \
+  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+    ac_prev=cache_file ;;
+  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+    cache_file=$ac_optarg ;;
+
+  --config-cache | -C)
+    cache_file=config.cache ;;
+
+  -datadir | --datadir | --datadi | --datad)
+    ac_prev=datadir ;;
+  -datadir=* | --datadir=* | --datadi=* | --datad=*)
+    datadir=$ac_optarg ;;
+
+  -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \
+  | --dataroo | --dataro | --datar)
+    ac_prev=datarootdir ;;
+  -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \
+  | --dataroot=* | --dataroo=* | --dataro=* | --datar=*)
+    datarootdir=$ac_optarg ;;
+
+  -disable-* | --disable-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      as_fn_error $? "invalid feature name: $ac_useropt"
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"enable_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--disable-$ac_useropt_orig"
+	 ac_unrecognized_sep=', ';;
+    esac
+    eval enable_$ac_useropt=no ;;
+
+  -docdir | --docdir | --docdi | --doc | --do)
+    ac_prev=docdir ;;
+  -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*)
+    docdir=$ac_optarg ;;
+
+  -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv)
+    ac_prev=dvidir ;;
+  -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*)
+    dvidir=$ac_optarg ;;
+
+  -enable-* | --enable-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      as_fn_error $? "invalid feature name: $ac_useropt"
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"enable_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--enable-$ac_useropt_orig"
+	 ac_unrecognized_sep=', ';;
+    esac
+    eval enable_$ac_useropt=\$ac_optarg ;;
+
+  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+  | --exec | --exe | --ex)
+    ac_prev=exec_prefix ;;
+  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+  | --exec=* | --exe=* | --ex=*)
+    exec_prefix=$ac_optarg ;;
+
+  -gas | --gas | --ga | --g)
+    # Obsolete; use --with-gas.
+    with_gas=yes ;;
+
+  -help | --help | --hel | --he | -h)
+    ac_init_help=long ;;
+  -help=r* | --help=r* | --hel=r* | --he=r* | -hr*)
+    ac_init_help=recursive ;;
+  -help=s* | --help=s* | --hel=s* | --he=s* | -hs*)
+    ac_init_help=short ;;
+
+  -host | --host | --hos | --ho)
+    ac_prev=host_alias ;;
+  -host=* | --host=* | --hos=* | --ho=*)
+    host_alias=$ac_optarg ;;
+
+  -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht)
+    ac_prev=htmldir ;;
+  -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \
+  | --ht=*)
+    htmldir=$ac_optarg ;;
+
+  -includedir | --includedir | --includedi | --included | --include \
+  | --includ | --inclu | --incl | --inc)
+    ac_prev=includedir ;;
+  -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+  | --includ=* | --inclu=* | --incl=* | --inc=*)
+    includedir=$ac_optarg ;;
+
+  -infodir | --infodir | --infodi | --infod | --info | --inf)
+    ac_prev=infodir ;;
+  -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+    infodir=$ac_optarg ;;
+
+  -libdir | --libdir | --libdi | --libd)
+    ac_prev=libdir ;;
+  -libdir=* | --libdir=* | --libdi=* | --libd=*)
+    libdir=$ac_optarg ;;
+
+  -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+  | --libexe | --libex | --libe)
+    ac_prev=libexecdir ;;
+  -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+  | --libexe=* | --libex=* | --libe=*)
+    libexecdir=$ac_optarg ;;
+
+  -localedir | --localedir | --localedi | --localed | --locale)
+    ac_prev=localedir ;;
+  -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*)
+    localedir=$ac_optarg ;;
+
+  -localstatedir | --localstatedir | --localstatedi | --localstated \
+  | --localstate | --localstat | --localsta | --localst | --locals)
+    ac_prev=localstatedir ;;
+  -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+  | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*)
+    localstatedir=$ac_optarg ;;
+
+  -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+    ac_prev=mandir ;;
+  -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+    mandir=$ac_optarg ;;
+
+  -nfp | --nfp | --nf)
+    # Obsolete; use --without-fp.
+    with_fp=no ;;
+
+  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+  | --no-cr | --no-c | -n)
+    no_create=yes ;;
+
+  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+    no_recursion=yes ;;
+
+  -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+  | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+  | --oldin | --oldi | --old | --ol | --o)
+    ac_prev=oldincludedir ;;
+  -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+  | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+  | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+    oldincludedir=$ac_optarg ;;
+
+  -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+    ac_prev=prefix ;;
+  -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+    prefix=$ac_optarg ;;
+
+  -program-prefix | --program-prefix | --program-prefi | --program-pref \
+  | --program-pre | --program-pr | --program-p)
+    ac_prev=program_prefix ;;
+  -program-prefix=* | --program-prefix=* | --program-prefi=* \
+  | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+    program_prefix=$ac_optarg ;;
+
+  -program-suffix | --program-suffix | --program-suffi | --program-suff \
+  | --program-suf | --program-su | --program-s)
+    ac_prev=program_suffix ;;
+  -program-suffix=* | --program-suffix=* | --program-suffi=* \
+  | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+    program_suffix=$ac_optarg ;;
+
+  -program-transform-name | --program-transform-name \
+  | --program-transform-nam | --program-transform-na \
+  | --program-transform-n | --program-transform- \
+  | --program-transform | --program-transfor \
+  | --program-transfo | --program-transf \
+  | --program-trans | --program-tran \
+  | --progr-tra | --program-tr | --program-t)
+    ac_prev=program_transform_name ;;
+  -program-transform-name=* | --program-transform-name=* \
+  | --program-transform-nam=* | --program-transform-na=* \
+  | --program-transform-n=* | --program-transform-=* \
+  | --program-transform=* | --program-transfor=* \
+  | --program-transfo=* | --program-transf=* \
+  | --program-trans=* | --program-tran=* \
+  | --progr-tra=* | --program-tr=* | --program-t=*)
+    program_transform_name=$ac_optarg ;;
+
+  -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd)
+    ac_prev=pdfdir ;;
+  -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*)
+    pdfdir=$ac_optarg ;;
+
+  -psdir | --psdir | --psdi | --psd | --ps)
+    ac_prev=psdir ;;
+  -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*)
+    psdir=$ac_optarg ;;
+
+  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+  | -silent | --silent | --silen | --sile | --sil)
+    silent=yes ;;
+
+  -runstatedir | --runstatedir | --runstatedi | --runstated \
+  | --runstate | --runstat | --runsta | --runst | --runs \
+  | --run | --ru | --r)
+    ac_prev=runstatedir ;;
+  -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
+  | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
+  | --run=* | --ru=* | --r=*)
+    runstatedir=$ac_optarg ;;
+
+  -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+    ac_prev=sbindir ;;
+  -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+  | --sbi=* | --sb=*)
+    sbindir=$ac_optarg ;;
+
+  -sharedstatedir | --sharedstatedir | --sharedstatedi \
+  | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+  | --sharedst | --shareds | --shared | --share | --shar \
+  | --sha | --sh)
+    ac_prev=sharedstatedir ;;
+  -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
+  | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
+  | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
+  | --sha=* | --sh=*)
+    sharedstatedir=$ac_optarg ;;
+
+  -site | --site | --sit)
+    ac_prev=site ;;
+  -site=* | --site=* | --sit=*)
+    site=$ac_optarg ;;
+
+  -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
+    ac_prev=srcdir ;;
+  -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
+    srcdir=$ac_optarg ;;
+
+  -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
+  | --syscon | --sysco | --sysc | --sys | --sy)
+    ac_prev=sysconfdir ;;
+  -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
+  | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
+    sysconfdir=$ac_optarg ;;
+
+  -target | --target | --targe | --targ | --tar | --ta | --t)
+    ac_prev=target_alias ;;
+  -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
+    target_alias=$ac_optarg ;;
+
+  -v | -verbose | --verbose | --verbos | --verbo | --verb)
+    verbose=yes ;;
+
+  -version | --version | --versio | --versi | --vers | -V)
+    ac_init_version=: ;;
+
+  -with-* | --with-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      as_fn_error $? "invalid package name: $ac_useropt"
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"with_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--with-$ac_useropt_orig"
+	 ac_unrecognized_sep=', ';;
+    esac
+    eval with_$ac_useropt=\$ac_optarg ;;
+
+  -without-* | --without-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*without-\(.*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      as_fn_error $? "invalid package name: $ac_useropt"
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"with_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--without-$ac_useropt_orig"
+	 ac_unrecognized_sep=', ';;
+    esac
+    eval with_$ac_useropt=no ;;
+
+  --x)
+    # Obsolete; use --with-x.
+    with_x=yes ;;
+
+  -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
+  | --x-incl | --x-inc | --x-in | --x-i)
+    ac_prev=x_includes ;;
+  -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
+  | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
+    x_includes=$ac_optarg ;;
+
+  -x-libraries | --x-libraries | --x-librarie | --x-librari \
+  | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
+    ac_prev=x_libraries ;;
+  -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
+  | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
+    x_libraries=$ac_optarg ;;
+
+  -*) as_fn_error $? "unrecognized option: \`$ac_option'
+Try \`$0 --help' for more information"
+    ;;
+
+  *=*)
+    ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='`
+    # Reject names that are not valid shell variable names.
+    case $ac_envvar in #(
+      '' | [0-9]* | *[!_$as_cr_alnum]* )
+      as_fn_error $? "invalid variable name: \`$ac_envvar'" ;;
+    esac
+    eval $ac_envvar=\$ac_optarg
+    export $ac_envvar ;;
+
+  *)
+    # FIXME: should be removed in autoconf 3.0.
+    $as_echo "$as_me: WARNING: you should use --build, --host, --target" >&2
+    expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null &&
+      $as_echo "$as_me: WARNING: invalid host type: $ac_option" >&2
+    : "${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}"
+    ;;
+
+  esac
+done
+
+if test -n "$ac_prev"; then
+  ac_option=--`echo $ac_prev | sed 's/_/-/g'`
+  as_fn_error $? "missing argument to $ac_option"
+fi
+
+if test -n "$ac_unrecognized_opts"; then
+  case $enable_option_checking in
+    no) ;;
+    fatal) as_fn_error $? "unrecognized options: $ac_unrecognized_opts" ;;
+    *)     $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;;
+  esac
+fi
+
+# Check all directory arguments for consistency.
+for ac_var in	exec_prefix prefix bindir sbindir libexecdir datarootdir \
+		datadir sysconfdir sharedstatedir localstatedir includedir \
+		oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
+		libdir localedir mandir runstatedir
+do
+  eval ac_val=\$$ac_var
+  # Remove trailing slashes.
+  case $ac_val in
+    */ )
+      ac_val=`expr "X$ac_val" : 'X\(.*[^/]\)' \| "X$ac_val" : 'X\(.*\)'`
+      eval $ac_var=\$ac_val;;
+  esac
+  # Be sure to have absolute directory names.
+  case $ac_val in
+    [\\/$]* | ?:[\\/]* )  continue;;
+    NONE | '' ) case $ac_var in *prefix ) continue;; esac;;
+  esac
+  as_fn_error $? "expected an absolute directory name for --$ac_var: $ac_val"
+done
+
+# There might be people who depend on the old broken behavior: `$host'
+# used to hold the argument of --host etc.
+# FIXME: To remove some day.
+build=$build_alias
+host=$host_alias
+target=$target_alias
+
+# FIXME: To remove some day.
+if test "x$host_alias" != x; then
+  if test "x$build_alias" = x; then
+    cross_compiling=maybe
+  elif test "x$build_alias" != "x$host_alias"; then
+    cross_compiling=yes
+  fi
+fi
+
+ac_tool_prefix=
+test -n "$host_alias" && ac_tool_prefix=$host_alias-
+
+test "$silent" = yes && exec 6>/dev/null
+
+
+ac_pwd=`pwd` && test -n "$ac_pwd" &&
+ac_ls_di=`ls -di .` &&
+ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` ||
+  as_fn_error $? "working directory cannot be determined"
+test "X$ac_ls_di" = "X$ac_pwd_ls_di" ||
+  as_fn_error $? "pwd does not report name of working directory"
+
+
+# Find the source files, if location was not specified.
+if test -z "$srcdir"; then
+  ac_srcdir_defaulted=yes
+  # Try the directory containing this script, then the parent directory.
+  ac_confdir=`$as_dirname -- "$as_myself" ||
+$as_expr X"$as_myself" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$as_myself" : 'X\(//\)[^/]' \| \
+	 X"$as_myself" : 'X\(//\)$' \| \
+	 X"$as_myself" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$as_myself" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+  srcdir=$ac_confdir
+  if test ! -r "$srcdir/$ac_unique_file"; then
+    srcdir=..
+  fi
+else
+  ac_srcdir_defaulted=no
+fi
+if test ! -r "$srcdir/$ac_unique_file"; then
+  test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .."
+  as_fn_error $? "cannot find sources ($ac_unique_file) in $srcdir"
+fi
+ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work"
+ac_abs_confdir=`(
+	cd "$srcdir" && test -r "./$ac_unique_file" || as_fn_error $? "$ac_msg"
+	pwd)`
+# When building in place, set srcdir=.
+if test "$ac_abs_confdir" = "$ac_pwd"; then
+  srcdir=.
+fi
+# Remove unnecessary trailing slashes from srcdir.
+# Double slashes in file names in object file debugging info
+# mess up M-x gdb in Emacs.
+case $srcdir in
+*/) srcdir=`expr "X$srcdir" : 'X\(.*[^/]\)' \| "X$srcdir" : 'X\(.*\)'`;;
+esac
+for ac_var in $ac_precious_vars; do
+  eval ac_env_${ac_var}_set=\${${ac_var}+set}
+  eval ac_env_${ac_var}_value=\$${ac_var}
+  eval ac_cv_env_${ac_var}_set=\${${ac_var}+set}
+  eval ac_cv_env_${ac_var}_value=\$${ac_var}
+done
+
+#
+# Report the --help message.
+#
+if test "$ac_init_help" = "long"; then
+  # Omit some internal or obsolete options to make the list less imposing.
+  # This message is too long to be a string in the A/UX 3.1 sh.
+  cat <<_ACEOF
+\`configure' configures avr-libc 2.0.0 to adapt to many kinds of systems.
+
+Usage: $0 [OPTION]... [VAR=VALUE]...
+
+To assign environment variables (e.g., CC, CFLAGS...), specify them as
+VAR=VALUE.  See below for descriptions of some of the useful variables.
+
+Defaults for the options are specified in brackets.
+
+Configuration:
+  -h, --help              display this help and exit
+      --help=short        display options specific to this package
+      --help=recursive    display the short help of all the included packages
+  -V, --version           display version information and exit
+  -q, --quiet, --silent   do not print \`checking ...' messages
+      --cache-file=FILE   cache test results in FILE [disabled]
+  -C, --config-cache      alias for \`--cache-file=config.cache'
+  -n, --no-create         do not create output files
+      --srcdir=DIR        find the sources in DIR [configure dir or \`..']
+
+Installation directories:
+  --prefix=PREFIX         install architecture-independent files in PREFIX
+                          [$ac_default_prefix]
+  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
+                          [PREFIX]
+
+By default, \`make install' will install all the files in
+\`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc.  You can specify
+an installation prefix other than \`$ac_default_prefix' using \`--prefix',
+for instance \`--prefix=\$HOME'.
+
+For better control, use the options below.
+
+Fine tuning of the installation directories:
+  --bindir=DIR            user executables [EPREFIX/bin]
+  --sbindir=DIR           system admin executables [EPREFIX/sbin]
+  --libexecdir=DIR        program executables [EPREFIX/libexec]
+  --sysconfdir=DIR        read-only single-machine data [PREFIX/etc]
+  --sharedstatedir=DIR    modifiable architecture-independent data [PREFIX/com]
+  --localstatedir=DIR     modifiable single-machine data [PREFIX/var]
+  --runstatedir=DIR       modifiable per-process data [LOCALSTATEDIR/run]
+  --libdir=DIR            object code libraries [EPREFIX/lib]
+  --includedir=DIR        C header files [PREFIX/include]
+  --oldincludedir=DIR     C header files for non-gcc [/usr/include]
+  --datarootdir=DIR       read-only arch.-independent data root [PREFIX/share]
+  --datadir=DIR           read-only architecture-independent data [DATAROOTDIR]
+  --infodir=DIR           info documentation [DATAROOTDIR/info]
+  --localedir=DIR         locale-dependent data [DATAROOTDIR/locale]
+  --mandir=DIR            man documentation [DATAROOTDIR/man]
+  --docdir=DIR            documentation root [DATAROOTDIR/doc/avr-libc]
+  --htmldir=DIR           html documentation [DOCDIR]
+  --dvidir=DIR            dvi documentation [DOCDIR]
+  --pdfdir=DIR            pdf documentation [DOCDIR]
+  --psdir=DIR             ps documentation [DOCDIR]
+_ACEOF
+
+  cat <<\_ACEOF
+
+Program names:
+  --program-prefix=PREFIX            prepend PREFIX to installed program names
+  --program-suffix=SUFFIX            append SUFFIX to installed program names
+  --program-transform-name=PROGRAM   run sed PROGRAM on installed program names
+
+System types:
+  --build=BUILD     configure for building on BUILD [guessed]
+  --host=HOST       cross-compile to build programs to run on HOST [BUILD]
+_ACEOF
+fi
+
+if test -n "$ac_init_help"; then
+  case $ac_init_help in
+     short | recursive ) echo "Configuration of avr-libc 2.0.0:";;
+   esac
+  cat <<\_ACEOF
+
+Optional Features:
+  --disable-option-checking  ignore unrecognized --enable/--with options
+  --disable-FEATURE       do not include FEATURE (same as --enable-FEATURE=no)
+  --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
+  --enable-silent-rules   less verbose build output (undo: "make V=1")
+  --disable-silent-rules  verbose build output (undo: "make V=0")
+  --enable-dependency-tracking
+                          do not reject slow dependency extractors
+  --disable-dependency-tracking
+                          speeds up one-time build
+  --enable-device-lib     build separate device library
+  --enable-doc            build all doc formats (disabled is default)
+  --enable-html-doc       build HTML documentation (default)
+  --enable-xml-doc        build XML documentation (default)
+  --enable-pdf-doc        build PDF documentation (default)
+  --enable-man-doc        build Unix-style manual pages (default)
+  --enable-versioned-doc  install docs in directory with version name (default)
+  --enable-debug-info=stabs|dwarf-2|dwarf-4  Enable generation of debugging information
+
+Some influential environment variables:
+  CC          C compiler command
+  CFLAGS      C compiler flags
+  LDFLAGS     linker flags, e.g. -L<lib dir> if you have libraries in a
+              nonstandard directory <lib dir>
+  LIBS        libraries to pass to the linker, e.g. -l<library>
+  CPPFLAGS    (Objective) C/C++ preprocessor flags, e.g. -I<include dir> if
+              you have headers in a nonstandard directory <include dir>
+  CCAS        assembler compiler command (defaults to CC)
+  CCASFLAGS   assembler compiler flags (defaults to CFLAGS)
+
+Use these variables to override the choices made by `configure' or to help
+it to find libraries and programs with nonstandard names/locations.
+
+Report bugs to <avr-libc-dev@nongnu.org>.
+_ACEOF
+ac_status=$?
+fi
+
+if test "$ac_init_help" = "recursive"; then
+  # If there are subdirs, report their specific --help.
+  for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue
+    test -d "$ac_dir" ||
+      { cd "$srcdir" && ac_pwd=`pwd` && srcdir=. && test -d "$ac_dir"; } ||
+      continue
+    ac_builddir=.
+
+case "$ac_dir" in
+.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
+*)
+  ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
+  # A ".." for each directory in $ac_dir_suffix.
+  ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
+  case $ac_top_builddir_sub in
+  "") ac_top_builddir_sub=. ac_top_build_prefix= ;;
+  *)  ac_top_build_prefix=$ac_top_builddir_sub/ ;;
+  esac ;;
+esac
+ac_abs_top_builddir=$ac_pwd
+ac_abs_builddir=$ac_pwd$ac_dir_suffix
+# for backward compatibility:
+ac_top_builddir=$ac_top_build_prefix
+
+case $srcdir in
+  .)  # We are building in place.
+    ac_srcdir=.
+    ac_top_srcdir=$ac_top_builddir_sub
+    ac_abs_top_srcdir=$ac_pwd ;;
+  [\\/]* | ?:[\\/]* )  # Absolute name.
+    ac_srcdir=$srcdir$ac_dir_suffix;
+    ac_top_srcdir=$srcdir
+    ac_abs_top_srcdir=$srcdir ;;
+  *) # Relative name.
+    ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
+    ac_top_srcdir=$ac_top_build_prefix$srcdir
+    ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
+esac
+ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
+
+    cd "$ac_dir" || { ac_status=$?; continue; }
+    # Check for guested configure.
+    if test -f "$ac_srcdir/configure.gnu"; then
+      echo &&
+      $SHELL "$ac_srcdir/configure.gnu" --help=recursive
+    elif test -f "$ac_srcdir/configure"; then
+      echo &&
+      $SHELL "$ac_srcdir/configure" --help=recursive
+    else
+      $as_echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
+    fi || ac_status=$?
+    cd "$ac_pwd" || { ac_status=$?; break; }
+  done
+fi
+
+test -n "$ac_init_help" && exit $ac_status
+if $ac_init_version; then
+  cat <<\_ACEOF
+avr-libc configure 2.0.0
+generated by GNU Autoconf 2.69
+
+Copyright (C) 2012 Free Software Foundation, Inc.
+This configure script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it.
+_ACEOF
+  exit
+fi
+
+## ------------------------ ##
+## Autoconf initialization. ##
+## ------------------------ ##
+
+# ac_fn_c_try_compile LINENO
+# --------------------------
+# Try to compile conftest.$ac_ext, and return whether this succeeded.
+ac_fn_c_try_compile ()
+{
+  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+  rm -f conftest.$ac_objext
+  if { { ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_compile") 2>conftest.err
+  ac_status=$?
+  if test -s conftest.err; then
+    grep -v '^ *+' conftest.err >conftest.er1
+    cat conftest.er1 >&5
+    mv -f conftest.er1 conftest.err
+  fi
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; } && {
+	 test -z "$ac_c_werror_flag" ||
+	 test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then :
+  ac_retval=0
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+	ac_retval=1
+fi
+  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
+  as_fn_set_status $ac_retval
+
+} # ac_fn_c_try_compile
+cat >config.log <<_ACEOF
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+
+It was created by avr-libc $as_me 2.0.0, which was
+generated by GNU Autoconf 2.69.  Invocation command line was
+
+  $ $0 $@
+
+_ACEOF
+exec 5>>config.log
+{
+cat <<_ASUNAME
+## --------- ##
+## Platform. ##
+## --------- ##
+
+hostname = `(hostname || uname -n) 2>/dev/null | sed 1q`
+uname -m = `(uname -m) 2>/dev/null || echo unknown`
+uname -r = `(uname -r) 2>/dev/null || echo unknown`
+uname -s = `(uname -s) 2>/dev/null || echo unknown`
+uname -v = `(uname -v) 2>/dev/null || echo unknown`
+
+/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
+/bin/uname -X     = `(/bin/uname -X) 2>/dev/null     || echo unknown`
+
+/bin/arch              = `(/bin/arch) 2>/dev/null              || echo unknown`
+/usr/bin/arch -k       = `(/usr/bin/arch -k) 2>/dev/null       || echo unknown`
+/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
+/usr/bin/hostinfo      = `(/usr/bin/hostinfo) 2>/dev/null      || echo unknown`
+/bin/machine           = `(/bin/machine) 2>/dev/null           || echo unknown`
+/usr/bin/oslevel       = `(/usr/bin/oslevel) 2>/dev/null       || echo unknown`
+/bin/universe          = `(/bin/universe) 2>/dev/null          || echo unknown`
+
+_ASUNAME
+
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    $as_echo "PATH: $as_dir"
+  done
+IFS=$as_save_IFS
+
+} >&5
+
+cat >&5 <<_ACEOF
+
+
+## ----------- ##
+## Core tests. ##
+## ----------- ##
+
+_ACEOF
+
+
+# Keep a trace of the command line.
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Strip out --silent because we don't want to record it for future runs.
+# Also quote any args containing shell meta-characters.
+# Make two passes to allow for proper duplicate-argument suppression.
+ac_configure_args=
+ac_configure_args0=
+ac_configure_args1=
+ac_must_keep_next=false
+for ac_pass in 1 2
+do
+  for ac_arg
+  do
+    case $ac_arg in
+    -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;;
+    -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+    | -silent | --silent | --silen | --sile | --sil)
+      continue ;;
+    *\'*)
+      ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;;
+    esac
+    case $ac_pass in
+    1) as_fn_append ac_configure_args0 " '$ac_arg'" ;;
+    2)
+      as_fn_append ac_configure_args1 " '$ac_arg'"
+      if test $ac_must_keep_next = true; then
+	ac_must_keep_next=false # Got value, back to normal.
+      else
+	case $ac_arg in
+	  *=* | --config-cache | -C | -disable-* | --disable-* \
+	  | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \
+	  | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \
+	  | -with-* | --with-* | -without-* | --without-* | --x)
+	    case "$ac_configure_args0 " in
+	      "$ac_configure_args1"*" '$ac_arg' "* ) continue ;;
+	    esac
+	    ;;
+	  -* ) ac_must_keep_next=true ;;
+	esac
+      fi
+      as_fn_append ac_configure_args " '$ac_arg'"
+      ;;
+    esac
+  done
+done
+{ ac_configure_args0=; unset ac_configure_args0;}
+{ ac_configure_args1=; unset ac_configure_args1;}
+
+# When interrupted or exit'd, cleanup temporary files, and complete
+# config.log.  We remove comments because anyway the quotes in there
+# would cause problems or look ugly.
+# WARNING: Use '\'' to represent an apostrophe within the trap.
+# WARNING: Do not start the trap code with a newline, due to a FreeBSD 4.0 bug.
+trap 'exit_status=$?
+  # Save into config.log some information that might help in debugging.
+  {
+    echo
+
+    $as_echo "## ---------------- ##
+## Cache variables. ##
+## ---------------- ##"
+    echo
+    # The following way of writing the cache mishandles newlines in values,
+(
+  for ac_var in `(set) 2>&1 | sed -n '\''s/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'\''`; do
+    eval ac_val=\$$ac_var
+    case $ac_val in #(
+    *${as_nl}*)
+      case $ac_var in #(
+      *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5
+$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
+      esac
+      case $ac_var in #(
+      _ | IFS | as_nl) ;; #(
+      BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
+      *) { eval $ac_var=; unset $ac_var;} ;;
+      esac ;;
+    esac
+  done
+  (set) 2>&1 |
+    case $as_nl`(ac_space='\'' '\''; set) 2>&1` in #(
+    *${as_nl}ac_space=\ *)
+      sed -n \
+	"s/'\''/'\''\\\\'\'''\''/g;
+	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\''\\2'\''/p"
+      ;; #(
+    *)
+      sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
+      ;;
+    esac |
+    sort
+)
+    echo
+
+    $as_echo "## ----------------- ##
+## Output variables. ##
+## ----------------- ##"
+    echo
+    for ac_var in $ac_subst_vars
+    do
+      eval ac_val=\$$ac_var
+      case $ac_val in
+      *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;;
+      esac
+      $as_echo "$ac_var='\''$ac_val'\''"
+    done | sort
+    echo
+
+    if test -n "$ac_subst_files"; then
+      $as_echo "## ------------------- ##
+## File substitutions. ##
+## ------------------- ##"
+      echo
+      for ac_var in $ac_subst_files
+      do
+	eval ac_val=\$$ac_var
+	case $ac_val in
+	*\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;;
+	esac
+	$as_echo "$ac_var='\''$ac_val'\''"
+      done | sort
+      echo
+    fi
+
+    if test -s confdefs.h; then
+      $as_echo "## ----------- ##
+## confdefs.h. ##
+## ----------- ##"
+      echo
+      cat confdefs.h
+      echo
+    fi
+    test "$ac_signal" != 0 &&
+      $as_echo "$as_me: caught signal $ac_signal"
+    $as_echo "$as_me: exit $exit_status"
+  } >&5
+  rm -f core *.core core.conftest.* &&
+    rm -f -r conftest* confdefs* conf$$* $ac_clean_files &&
+    exit $exit_status
+' 0
+for ac_signal in 1 2 13 15; do
+  trap 'ac_signal='$ac_signal'; as_fn_exit 1' $ac_signal
+done
+ac_signal=0
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -f -r conftest* confdefs.h
+
+$as_echo "/* confdefs.h */" > confdefs.h
+
+# Predefined preprocessor variables.
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_NAME "$PACKAGE_NAME"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_VERSION "$PACKAGE_VERSION"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_STRING "$PACKAGE_STRING"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_URL "$PACKAGE_URL"
+_ACEOF
+
+
+# Let the site file select an alternate cache file if it wants to.
+# Prefer an explicitly selected file to automatically selected ones.
+ac_site_file1=NONE
+ac_site_file2=NONE
+if test -n "$CONFIG_SITE"; then
+  # We do not want a PATH search for config.site.
+  case $CONFIG_SITE in #((
+    -*)  ac_site_file1=./$CONFIG_SITE;;
+    */*) ac_site_file1=$CONFIG_SITE;;
+    *)   ac_site_file1=./$CONFIG_SITE;;
+  esac
+elif test "x$prefix" != xNONE; then
+  ac_site_file1=$prefix/share/config.site
+  ac_site_file2=$prefix/etc/config.site
+else
+  ac_site_file1=$ac_default_prefix/share/config.site
+  ac_site_file2=$ac_default_prefix/etc/config.site
+fi
+for ac_site_file in "$ac_site_file1" "$ac_site_file2"
+do
+  test "x$ac_site_file" = xNONE && continue
+  if test /dev/null != "$ac_site_file" && test -r "$ac_site_file"; then
+    { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5
+$as_echo "$as_me: loading site script $ac_site_file" >&6;}
+    sed 's/^/| /' "$ac_site_file" >&5
+    . "$ac_site_file" \
+      || { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "failed to load site script $ac_site_file
+See \`config.log' for more details" "$LINENO" 5; }
+  fi
+done
+
+if test -r "$cache_file"; then
+  # Some versions of bash will fail to source /dev/null (special files
+  # actually), so we avoid doing that.  DJGPP emulates it as a regular file.
+  if test /dev/null != "$cache_file" && test -f "$cache_file"; then
+    { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5
+$as_echo "$as_me: loading cache $cache_file" >&6;}
+    case $cache_file in
+      [\\/]* | ?:[\\/]* ) . "$cache_file";;
+      *)                      . "./$cache_file";;
+    esac
+  fi
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5
+$as_echo "$as_me: creating cache $cache_file" >&6;}
+  >$cache_file
+fi
+
+# Check that the precious variables saved in the cache have kept the same
+# value.
+ac_cache_corrupted=false
+for ac_var in $ac_precious_vars; do
+  eval ac_old_set=\$ac_cv_env_${ac_var}_set
+  eval ac_new_set=\$ac_env_${ac_var}_set
+  eval ac_old_val=\$ac_cv_env_${ac_var}_value
+  eval ac_new_val=\$ac_env_${ac_var}_value
+  case $ac_old_set,$ac_new_set in
+    set,)
+      { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5
+$as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;}
+      ac_cache_corrupted=: ;;
+    ,set)
+      { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was not set in the previous run" >&5
+$as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;}
+      ac_cache_corrupted=: ;;
+    ,);;
+    *)
+      if test "x$ac_old_val" != "x$ac_new_val"; then
+	# differences in whitespace do not lead to failure.
+	ac_old_val_w=`echo x $ac_old_val`
+	ac_new_val_w=`echo x $ac_new_val`
+	if test "$ac_old_val_w" != "$ac_new_val_w"; then
+	  { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' has changed since the previous run:" >&5
+$as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
+	  ac_cache_corrupted=:
+	else
+	  { $as_echo "$as_me:${as_lineno-$LINENO}: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5
+$as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;}
+	  eval $ac_var=\$ac_old_val
+	fi
+	{ $as_echo "$as_me:${as_lineno-$LINENO}:   former value:  \`$ac_old_val'" >&5
+$as_echo "$as_me:   former value:  \`$ac_old_val'" >&2;}
+	{ $as_echo "$as_me:${as_lineno-$LINENO}:   current value: \`$ac_new_val'" >&5
+$as_echo "$as_me:   current value: \`$ac_new_val'" >&2;}
+      fi;;
+  esac
+  # Pass precious variables to config.status.
+  if test "$ac_new_set" = set; then
+    case $ac_new_val in
+    *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
+    *) ac_arg=$ac_var=$ac_new_val ;;
+    esac
+    case " $ac_configure_args " in
+      *" '$ac_arg' "*) ;; # Avoid dups.  Use of quotes ensures accuracy.
+      *) as_fn_append ac_configure_args " '$ac_arg'" ;;
+    esac
+  fi
+done
+if $ac_cache_corrupted; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+  { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5
+$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;}
+  as_fn_error $? "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5
+fi
+## -------------------- ##
+## Main body of script. ##
+## -------------------- ##
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+
+
+
+
+
+ac_config_headers="$ac_config_headers config.h"
+
+
+AVR_LIBC_MAJOR=2
+AVR_LIBC_MINOR=0
+AVR_LIBC_REVISION=0
+AVR_LIBC_RELDATE=20150208
+AVR_LIBC_VERSION=2.0.0
+AVR_LIBC_VERSION_NUMERIC=20000
+
+
+
+
+
+
+
+ac_aux_dir=
+for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do
+  if test -f "$ac_dir/install-sh"; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install-sh -c"
+    break
+  elif test -f "$ac_dir/install.sh"; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install.sh -c"
+    break
+  elif test -f "$ac_dir/shtool"; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/shtool install -c"
+    break
+  fi
+done
+if test -z "$ac_aux_dir"; then
+  as_fn_error $? "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5
+fi
+
+# These three variables are undocumented and unsupported,
+# and are intended to be withdrawn in a future Autoconf release.
+# They can cause serious problems if a builder's source tree is in a directory
+# whose full name contains unusual characters.
+ac_config_guess="$SHELL $ac_aux_dir/config.guess"  # Please don't use this var.
+ac_config_sub="$SHELL $ac_aux_dir/config.sub"  # Please don't use this var.
+ac_configure="$SHELL $ac_aux_dir/configure"  # Please don't use this var.
+
+
+# Make sure we can run config.sub.
+$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 ||
+  as_fn_error $? "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5
+$as_echo_n "checking build system type... " >&6; }
+if ${ac_cv_build+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  ac_build_alias=$build_alias
+test "x$ac_build_alias" = x &&
+  ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"`
+test "x$ac_build_alias" = x &&
+  as_fn_error $? "cannot guess build type; you must specify one" "$LINENO" 5
+ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` ||
+  as_fn_error $? "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5
+$as_echo "$ac_cv_build" >&6; }
+case $ac_cv_build in
+*-*-*) ;;
+*) as_fn_error $? "invalid value of canonical build" "$LINENO" 5;;
+esac
+build=$ac_cv_build
+ac_save_IFS=$IFS; IFS='-'
+set x $ac_cv_build
+shift
+build_cpu=$1
+build_vendor=$2
+shift; shift
+# Remember, the first character of IFS is used to create $*,
+# except with old shells:
+build_os=$*
+IFS=$ac_save_IFS
+case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5
+$as_echo_n "checking host system type... " >&6; }
+if ${ac_cv_host+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test "x$host_alias" = x; then
+  ac_cv_host=$ac_cv_build
+else
+  ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` ||
+    as_fn_error $? "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5
+fi
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5
+$as_echo "$ac_cv_host" >&6; }
+case $ac_cv_host in
+*-*-*) ;;
+*) as_fn_error $? "invalid value of canonical host" "$LINENO" 5;;
+esac
+host=$ac_cv_host
+ac_save_IFS=$IFS; IFS='-'
+set x $ac_cv_host
+shift
+host_cpu=$1
+host_vendor=$2
+shift; shift
+# Remember, the first character of IFS is used to create $*,
+# except with old shells:
+host_os=$*
+IFS=$ac_save_IFS
+case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac
+
+
+
+# See if the user specified '--build=`../config.guess` --host=avr' when
+# running ../configure.
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if configuring for cross compile" >&5
+$as_echo_n "checking if configuring for cross compile... " >&6; }
+if test "x${build_alias}" = "x${host_alias}"; then
+	if test "x${build_alias}" = "x" ; then
+		build_alias='`./config.guess`'
+	fi
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: " >&5
+$as_echo "$as_me: WARNING: " >&2;}
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: AVR-LIBC must be built using an avr cross-compiler." >&5
+$as_echo "$as_me: WARNING: AVR-LIBC must be built using an avr cross-compiler." >&2;}
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Try configuring with:" >&5
+$as_echo "$as_me: WARNING: Try configuring with:" >&2;}
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: \"$0 --build=$build_alias --host=avr\"" >&5
+$as_echo "$as_me: WARNING: \"$0 --build=$build_alias --host=avr\"" >&2;}
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: " >&5
+$as_echo "$as_me: WARNING: " >&2;}
+	as_fn_error $? "aborting configure" "$LINENO" 5
+else
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+fi
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if target host is avr" >&5
+$as_echo_n "checking if target host is avr... " >&6; }
+case "$host" in
+	avr* )
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+		;;
+	* )
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: " >&5
+$as_echo "$as_me: WARNING: " >&2;}
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Avr-libc must be built using an avr cross-compiler." >&5
+$as_echo "$as_me: WARNING: Avr-libc must be built using an avr cross-compiler." >&2;}
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Try configuring with:" >&5
+$as_echo "$as_me: WARNING: Try configuring with:" >&2;}
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: \"$0 --build=$build --host=avr\"" >&5
+$as_echo "$as_me: WARNING: \"$0 --build=$build --host=avr\"" >&2;}
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: " >&5
+$as_echo "$as_me: WARNING: " >&2;}
+		as_fn_error $? "aborting configure" "$LINENO" 5
+		;;
+esac
+
+## TODO: Write a check for GNU Make
+
+
+
+am__api_version='1.15'
+
+# Find a good install program.  We prefer a C program (faster),
+# so one script is as good as another.  But avoid the broken or
+# incompatible versions:
+# SysV /etc/install, /usr/sbin/install
+# SunOS /usr/etc/install
+# IRIX /sbin/install
+# AIX /bin/install
+# AmigaOS /C/install, which installs bootblocks on floppy discs
+# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
+# AFS /usr/afsws/bin/install, which mishandles nonexistent args
+# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
+# OS/2's system install, which has a completely different semantic
+# ./install, which can be erroneously created by make from ./install.sh.
+# Reject install programs that cannot install multiple files.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5
+$as_echo_n "checking for a BSD-compatible install... " >&6; }
+if test -z "$INSTALL"; then
+if ${ac_cv_path_install+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    # Account for people who put trailing slashes in PATH elements.
+case $as_dir/ in #((
+  ./ | .// | /[cC]/* | \
+  /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \
+  ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \
+  /usr/ucb/* ) ;;
+  *)
+    # OSF1 and SCO ODT 3.0 have their own names for install.
+    # Don't use installbsd from OSF since it installs stuff as root
+    # by default.
+    for ac_prog in ginstall scoinst install; do
+      for ac_exec_ext in '' $ac_executable_extensions; do
+	if as_fn_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then
+	  if test $ac_prog = install &&
+	    grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
+	    # AIX install.  It has an incompatible calling convention.
+	    :
+	  elif test $ac_prog = install &&
+	    grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
+	    # program-specific install script used by HP pwplus--don't use.
+	    :
+	  else
+	    rm -rf conftest.one conftest.two conftest.dir
+	    echo one > conftest.one
+	    echo two > conftest.two
+	    mkdir conftest.dir
+	    if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" &&
+	      test -s conftest.one && test -s conftest.two &&
+	      test -s conftest.dir/conftest.one &&
+	      test -s conftest.dir/conftest.two
+	    then
+	      ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c"
+	      break 3
+	    fi
+	  fi
+	fi
+      done
+    done
+    ;;
+esac
+
+  done
+IFS=$as_save_IFS
+
+rm -rf conftest.one conftest.two conftest.dir
+
+fi
+  if test "${ac_cv_path_install+set}" = set; then
+    INSTALL=$ac_cv_path_install
+  else
+    # As a last resort, use the slow shell script.  Don't cache a
+    # value for INSTALL within a source directory, because that will
+    # break other packages using the cache if that directory is
+    # removed, or if the value is a relative name.
+    INSTALL=$ac_install_sh
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5
+$as_echo "$INSTALL" >&6; }
+
+# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
+# It thinks the first close brace ends the variable substitution.
+test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
+
+test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}'
+
+test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether build environment is sane" >&5
+$as_echo_n "checking whether build environment is sane... " >&6; }
+# Reject unsafe characters in $srcdir or the absolute working directory
+# name.  Accept space and tab only in the latter.
+am_lf='
+'
+case `pwd` in
+  *[\\\"\#\$\&\'\`$am_lf]*)
+    as_fn_error $? "unsafe absolute working directory name" "$LINENO" 5;;
+esac
+case $srcdir in
+  *[\\\"\#\$\&\'\`$am_lf\ \	]*)
+    as_fn_error $? "unsafe srcdir value: '$srcdir'" "$LINENO" 5;;
+esac
+
+# Do 'set' in a subshell so we don't clobber the current shell's
+# arguments.  Must try -L first in case configure is actually a
+# symlink; some systems play weird games with the mod time of symlinks
+# (eg FreeBSD returns the mod time of the symlink's containing
+# directory).
+if (
+   am_has_slept=no
+   for am_try in 1 2; do
+     echo "timestamp, slept: $am_has_slept" > conftest.file
+     set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null`
+     if test "$*" = "X"; then
+	# -L didn't work.
+	set X `ls -t "$srcdir/configure" conftest.file`
+     fi
+     if test "$*" != "X $srcdir/configure conftest.file" \
+	&& test "$*" != "X conftest.file $srcdir/configure"; then
+
+	# If neither matched, then we have a broken ls.  This can happen
+	# if, for instance, CONFIG_SHELL is bash and it inherits a
+	# broken ls alias from the environment.  This has actually
+	# happened.  Such a system could not be considered "sane".
+	as_fn_error $? "ls -t appears to fail.  Make sure there is not a broken
+  alias in your environment" "$LINENO" 5
+     fi
+     if test "$2" = conftest.file || test $am_try -eq 2; then
+       break
+     fi
+     # Just in case.
+     sleep 1
+     am_has_slept=yes
+   done
+   test "$2" = conftest.file
+   )
+then
+   # Ok.
+   :
+else
+   as_fn_error $? "newly created file is older than distributed files!
+Check your system clock" "$LINENO" 5
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+# If we didn't sleep, we still need to ensure time stamps of config.status and
+# generated files are strictly newer.
+am_sleep_pid=
+if grep 'slept: no' conftest.file >/dev/null 2>&1; then
+  ( sleep 1 ) &
+  am_sleep_pid=$!
+fi
+
+rm -f conftest.file
+
+test "$program_prefix" != NONE &&
+  program_transform_name="s&^&$program_prefix&;$program_transform_name"
+# Use a double $ so make ignores it.
+test "$program_suffix" != NONE &&
+  program_transform_name="s&\$&$program_suffix&;$program_transform_name"
+# Double any \ or $.
+# By default was `s,x,x', remove it if useless.
+ac_script='s/[\\$]/&&/g;s/;s,x,x,$//'
+program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"`
+
+# Expand $ac_aux_dir to an absolute path.
+am_aux_dir=`cd "$ac_aux_dir" && pwd`
+
+if test x"${MISSING+set}" != xset; then
+  case $am_aux_dir in
+  *\ * | *\	*)
+    MISSING="\${SHELL} \"$am_aux_dir/missing\"" ;;
+  *)
+    MISSING="\${SHELL} $am_aux_dir/missing" ;;
+  esac
+fi
+# Use eval to expand $SHELL
+if eval "$MISSING --is-lightweight"; then
+  am_missing_run="$MISSING "
+else
+  am_missing_run=
+  { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: 'missing' script is too old or missing" >&5
+$as_echo "$as_me: WARNING: 'missing' script is too old or missing" >&2;}
+fi
+
+if test x"${install_sh+set}" != xset; then
+  case $am_aux_dir in
+  *\ * | *\	*)
+    install_sh="\${SHELL} '$am_aux_dir/install-sh'" ;;
+  *)
+    install_sh="\${SHELL} $am_aux_dir/install-sh"
+  esac
+fi
+
+# Installed binaries are usually stripped using 'strip' when the user
+# run "make install-strip".  However 'strip' might not be the right
+# tool to use in cross-compilation environments, therefore Automake
+# will honor the 'STRIP' environment variable to overrule this program.
+if test "$cross_compiling" != no; then
+  if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args.
+set dummy ${ac_tool_prefix}strip; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_STRIP+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$STRIP"; then
+  ac_cv_prog_STRIP="$STRIP" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_STRIP="${ac_tool_prefix}strip"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+STRIP=$ac_cv_prog_STRIP
+if test -n "$STRIP"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5
+$as_echo "$STRIP" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_STRIP"; then
+  ac_ct_STRIP=$STRIP
+  # Extract the first word of "strip", so it can be a program name with args.
+set dummy strip; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_ac_ct_STRIP+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_STRIP"; then
+  ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_STRIP="strip"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP
+if test -n "$ac_ct_STRIP"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5
+$as_echo "$ac_ct_STRIP" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+  if test "x$ac_ct_STRIP" = x; then
+    STRIP=":"
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    STRIP=$ac_ct_STRIP
+  fi
+else
+  STRIP="$ac_cv_prog_STRIP"
+fi
+
+fi
+INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s"
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a thread-safe mkdir -p" >&5
+$as_echo_n "checking for a thread-safe mkdir -p... " >&6; }
+if test -z "$MKDIR_P"; then
+  if ${ac_cv_path_mkdir+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH$PATH_SEPARATOR/opt/sfw/bin
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_prog in mkdir gmkdir; do
+	 for ac_exec_ext in '' $ac_executable_extensions; do
+	   as_fn_executable_p "$as_dir/$ac_prog$ac_exec_ext" || continue
+	   case `"$as_dir/$ac_prog$ac_exec_ext" --version 2>&1` in #(
+	     'mkdir (GNU coreutils) '* | \
+	     'mkdir (coreutils) '* | \
+	     'mkdir (fileutils) '4.1*)
+	       ac_cv_path_mkdir=$as_dir/$ac_prog$ac_exec_ext
+	       break 3;;
+	   esac
+	 done
+       done
+  done
+IFS=$as_save_IFS
+
+fi
+
+  test -d ./--version && rmdir ./--version
+  if test "${ac_cv_path_mkdir+set}" = set; then
+    MKDIR_P="$ac_cv_path_mkdir -p"
+  else
+    # As a last resort, use the slow shell script.  Don't cache a
+    # value for MKDIR_P within a source directory, because that will
+    # break other packages using the cache if that directory is
+    # removed, or if the value is a relative name.
+    MKDIR_P="$ac_install_sh -d"
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $MKDIR_P" >&5
+$as_echo "$MKDIR_P" >&6; }
+
+for ac_prog in gawk mawk nawk awk
+do
+  # Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_AWK+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$AWK"; then
+  ac_cv_prog_AWK="$AWK" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_AWK="$ac_prog"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+AWK=$ac_cv_prog_AWK
+if test -n "$AWK"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AWK" >&5
+$as_echo "$AWK" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+  test -n "$AWK" && break
+done
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${MAKE-make} sets \$(MAKE)" >&5
+$as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... " >&6; }
+set x ${MAKE-make}
+ac_make=`$as_echo "$2" | sed 's/+/p/g; s/[^a-zA-Z0-9_]/_/g'`
+if eval \${ac_cv_prog_make_${ac_make}_set+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat >conftest.make <<\_ACEOF
+SHELL = /bin/sh
+all:
+	@echo '@@@%%%=$(MAKE)=@@@%%%'
+_ACEOF
+# GNU make sometimes prints "make[1]: Entering ...", which would confuse us.
+case `${MAKE-make} -f conftest.make 2>/dev/null` in
+  *@@@%%%=?*=@@@%%%*)
+    eval ac_cv_prog_make_${ac_make}_set=yes;;
+  *)
+    eval ac_cv_prog_make_${ac_make}_set=no;;
+esac
+rm -f conftest.make
+fi
+if eval test \$ac_cv_prog_make_${ac_make}_set = yes; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+  SET_MAKE=
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+  SET_MAKE="MAKE=${MAKE-make}"
+fi
+
+rm -rf .tst 2>/dev/null
+mkdir .tst 2>/dev/null
+if test -d .tst; then
+  am__leading_dot=.
+else
+  am__leading_dot=_
+fi
+rmdir .tst 2>/dev/null
+
+# Check whether --enable-silent-rules was given.
+if test "${enable_silent_rules+set}" = set; then :
+  enableval=$enable_silent_rules;
+fi
+
+case $enable_silent_rules in # (((
+  yes) AM_DEFAULT_VERBOSITY=0;;
+   no) AM_DEFAULT_VERBOSITY=1;;
+    *) AM_DEFAULT_VERBOSITY=1;;
+esac
+am_make=${MAKE-make}
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $am_make supports nested variables" >&5
+$as_echo_n "checking whether $am_make supports nested variables... " >&6; }
+if ${am_cv_make_support_nested_variables+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if $as_echo 'TRUE=$(BAR$(V))
+BAR0=false
+BAR1=true
+V=1
+am__doit:
+	@$(TRUE)
+.PHONY: am__doit' | $am_make -f - >/dev/null 2>&1; then
+  am_cv_make_support_nested_variables=yes
+else
+  am_cv_make_support_nested_variables=no
+fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_make_support_nested_variables" >&5
+$as_echo "$am_cv_make_support_nested_variables" >&6; }
+if test $am_cv_make_support_nested_variables = yes; then
+    AM_V='$(V)'
+  AM_DEFAULT_V='$(AM_DEFAULT_VERBOSITY)'
+else
+  AM_V=$AM_DEFAULT_VERBOSITY
+  AM_DEFAULT_V=$AM_DEFAULT_VERBOSITY
+fi
+AM_BACKSLASH='\'
+
+if test "`cd $srcdir && pwd`" != "`pwd`"; then
+  # Use -I$(srcdir) only when $(srcdir) != ., so that make's output
+  # is not polluted with repeated "-I."
+  am__isrc=' -I$(srcdir)'
+  # test to see if srcdir already configured
+  if test -f $srcdir/config.status; then
+    as_fn_error $? "source directory already configured; run \"make distclean\" there first" "$LINENO" 5
+  fi
+fi
+
+# test whether we have cygpath
+if test -z "$CYGPATH_W"; then
+  if (cygpath --version) >/dev/null 2>/dev/null; then
+    CYGPATH_W='cygpath -w'
+  else
+    CYGPATH_W=echo
+  fi
+fi
+
+
+# Define the identity of the package.
+ PACKAGE='avr-libc'
+ VERSION='2.0.0'
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE "$PACKAGE"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define VERSION "$VERSION"
+_ACEOF
+
+# Some tools Automake needs.
+
+ACLOCAL=${ACLOCAL-"${am_missing_run}aclocal-${am__api_version}"}
+
+
+AUTOCONF=${AUTOCONF-"${am_missing_run}autoconf"}
+
+
+AUTOMAKE=${AUTOMAKE-"${am_missing_run}automake-${am__api_version}"}
+
+
+AUTOHEADER=${AUTOHEADER-"${am_missing_run}autoheader"}
+
+
+MAKEINFO=${MAKEINFO-"${am_missing_run}makeinfo"}
+
+# For better backward compatibility.  To be removed once Automake 1.9.x
+# dies out for good.  For more background, see:
+# <http://lists.gnu.org/archive/html/automake/2012-07/msg00001.html>
+# <http://lists.gnu.org/archive/html/automake/2012-07/msg00014.html>
+mkdir_p='$(MKDIR_P)'
+
+# We need awk for the "check" target (and possibly the TAP driver).  The
+# system "awk" is bad on some platforms.
+# Always define AMTAR for backward compatibility.  Yes, it's still used
+# in the wild :-(  We should find a proper way to deprecate it ...
+AMTAR='$${TAR-tar}'
+
+
+# We'll loop over all known methods to create a tar archive until one works.
+_am_tools='gnutar  pax cpio none'
+
+am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -'
+
+
+
+
+
+
+# POSIX will say in a future version that running "rm -f" with no argument
+# is OK; and we want to be able to make that assumption in our Makefile
+# recipes.  So use an aggressive probe to check that the usage we want is
+# actually supported "in the wild" to an acceptable degree.
+# See automake bug#10828.
+# To make any issue more visible, cause the running configure to be aborted
+# by default if the 'rm' program in use doesn't match our expectations; the
+# user can still override this though.
+if rm -f && rm -fr && rm -rf; then : OK; else
+  cat >&2 <<'END'
+Oops!
+
+Your 'rm' program seems unable to run without file operands specified
+on the command line, even when the '-f' option is present.  This is contrary
+to the behaviour of most rm programs out there, and not conforming with
+the upcoming POSIX standard: <http://austingroupbugs.net/view.php?id=542>
+
+Please tell bug-automake@gnu.org about your system, including the value
+of your $PATH and any error possibly output before this message.  This
+can help us improve future automake versions.
+
+END
+  if test x"$ACCEPT_INFERIOR_RM_PROGRAM" = x"yes"; then
+    echo 'Configuration will proceed anyway, since you have set the' >&2
+    echo 'ACCEPT_INFERIOR_RM_PROGRAM variable to "yes"' >&2
+    echo >&2
+  else
+    cat >&2 <<'END'
+Aborting the configuration process, to ensure you take notice of the issue.
+
+You can download and install GNU coreutils to get an 'rm' implementation
+that behaves properly: <http://www.gnu.org/software/coreutils/>.
+
+If you want to complete the configuration process using your problematic
+'rm' anyway, export the environment variable ACCEPT_INFERIOR_RM_PROGRAM
+to "yes", and re-run configure.
+
+END
+    as_fn_error $? "Your 'rm' program is bad, sorry." "$LINENO" 5
+  fi
+fi
+
+
+# We don't want touse the cflags from the environment since we need control
+# of this when we're building the libs.
+CFLAGS=""
+
+
+
+
+
+# Checks for programs.
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}gcc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_CC="${ac_tool_prefix}gcc"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_CC"; then
+  ac_ct_CC=$CC
+  # Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_ac_ct_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_CC"; then
+  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_CC="gcc"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5
+$as_echo "$ac_ct_CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+  if test "x$ac_ct_CC" = x; then
+    CC=""
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    CC=$ac_ct_CC
+  fi
+else
+  CC="$ac_cv_prog_CC"
+fi
+
+if test -z "$CC"; then
+          if test -n "$ac_tool_prefix"; then
+    # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}cc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_CC="${ac_tool_prefix}cc"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+  fi
+fi
+if test -z "$CC"; then
+  # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  ac_prog_rejected=no
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then
+       ac_prog_rejected=yes
+       continue
+     fi
+    ac_cv_prog_CC="cc"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+if test $ac_prog_rejected = yes; then
+  # We found a bogon in the path, so make sure we never use it.
+  set dummy $ac_cv_prog_CC
+  shift
+  if test $# != 0; then
+    # We chose a different compiler from the bogus one.
+    # However, it has the same basename, so the bogon will be chosen
+    # first if we set CC to just the basename; use the full file name.
+    shift
+    ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@"
+  fi
+fi
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$CC"; then
+  if test -n "$ac_tool_prefix"; then
+  for ac_prog in cl.exe
+  do
+    # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
+set dummy $ac_tool_prefix$ac_prog; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_CC="$ac_tool_prefix$ac_prog"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+    test -n "$CC" && break
+  done
+fi
+if test -z "$CC"; then
+  ac_ct_CC=$CC
+  for ac_prog in cl.exe
+do
+  # Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_ac_ct_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_CC"; then
+  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_CC="$ac_prog"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5
+$as_echo "$ac_ct_CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+  test -n "$ac_ct_CC" && break
+done
+
+  if test "x$ac_ct_CC" = x; then
+    CC=""
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    CC=$ac_ct_CC
+  fi
+fi
+
+fi
+
+
+test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "no acceptable C compiler found in \$PATH
+See \`config.log' for more details" "$LINENO" 5; }
+
+# Provide some information about the compiler.
+$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5
+set X $ac_compile
+ac_compiler=$2
+for ac_option in --version -v -V -qversion; do
+  { { ac_try="$ac_compiler $ac_option >&5"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_compiler $ac_option >&5") 2>conftest.err
+  ac_status=$?
+  if test -s conftest.err; then
+    sed '10a\
+... rest of stderr output deleted ...
+         10q' conftest.err >conftest.er1
+    cat conftest.er1 >&5
+  fi
+  rm -f conftest.er1 conftest.err
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }
+done
+
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+if { { ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_link") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; then
+  ac_no_link=no
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out"
+# Try to create an executable without -o first, disregard a.out.
+# It will help us diagnose broken compilers, and finding out an intuition
+# of exeext.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5
+$as_echo_n "checking whether the C compiler works... " >&6; }
+ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'`
+
+# The possible output files:
+ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*"
+
+ac_rmfiles=
+for ac_file in $ac_files
+do
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;;
+    * ) ac_rmfiles="$ac_rmfiles $ac_file";;
+  esac
+done
+rm -f $ac_rmfiles
+
+if { { ac_try="$ac_link_default"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_link_default") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; then :
+  # Autoconf-2.13 could set the ac_cv_exeext variable to `no'.
+# So ignore a value of `no', otherwise this would lead to `EXEEXT = no'
+# in a Makefile.  We should not override ac_cv_exeext if it was cached,
+# so that the user can short-circuit this test for compilers unknown to
+# Autoconf.
+for ac_file in $ac_files ''
+do
+  test -f "$ac_file" || continue
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj )
+	;;
+    [ab].out )
+	# We found the default executable, but exeext='' is most
+	# certainly right.
+	break;;
+    *.* )
+	if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no;
+	then :; else
+	   ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+	fi
+	# We set ac_cv_exeext here because the later test for it is not
+	# safe: cross compilers may not add the suffix if given an `-o'
+	# argument, so we may need to know it at that point already.
+	# Even if this section looks crufty: it has the advantage of
+	# actually working.
+	break;;
+    * )
+	break;;
+  esac
+done
+test "$ac_cv_exeext" = no && ac_cv_exeext=
+
+else
+  ac_file=''
+fi
+if test -z "$ac_file"; then :
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+$as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error 77 "C compiler cannot create executables
+See \`config.log' for more details" "$LINENO" 5; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5
+$as_echo_n "checking for C compiler default output file name... " >&6; }
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5
+$as_echo "$ac_file" >&6; }
+ac_exeext=$ac_cv_exeext
+
+rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out
+ac_clean_files=$ac_clean_files_save
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5
+$as_echo_n "checking for suffix of executables... " >&6; }
+if { { ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_link") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; then :
+  # If both `conftest.exe' and `conftest' are `present' (well, observable)
+# catch `conftest.exe'.  For instance with Cygwin, `ls conftest' will
+# work properly (i.e., refer to `conftest.exe'), while it won't with
+# `rm'.
+for ac_file in conftest.exe conftest conftest.*; do
+  test -f "$ac_file" || continue
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;;
+    *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+	  break;;
+    * ) break;;
+  esac
+done
+else
+  { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "cannot compute suffix of executables: cannot compile and link
+See \`config.log' for more details" "$LINENO" 5; }
+fi
+rm -f conftest conftest$ac_cv_exeext
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5
+$as_echo "$ac_cv_exeext" >&6; }
+
+rm -f conftest.$ac_ext
+EXEEXT=$ac_cv_exeext
+ac_exeext=$EXEEXT
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+#include <stdio.h>
+int
+main ()
+{
+FILE *f = fopen ("conftest.out", "w");
+ return ferror (f) || fclose (f) != 0;
+
+  ;
+  return 0;
+}
+_ACEOF
+ac_clean_files="$ac_clean_files conftest.out"
+# Check that the compiler produces executables we can run.  If not, either
+# the compiler is broken, or we cross compile.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5
+$as_echo_n "checking whether we are cross compiling... " >&6; }
+if test "$cross_compiling" != yes; then
+  { { ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_link") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }
+  if { ac_try='./conftest$ac_cv_exeext'
+  { { case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_try") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; }; then
+    cross_compiling=no
+  else
+    if test "$cross_compiling" = maybe; then
+	cross_compiling=yes
+    else
+	{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "cannot run C compiled programs.
+If you meant to cross compile, use \`--host'.
+See \`config.log' for more details" "$LINENO" 5; }
+    fi
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5
+$as_echo "$cross_compiling" >&6; }
+
+rm -f conftest.$ac_ext conftest$ac_cv_exeext conftest.out
+ac_clean_files=$ac_clean_files_save
+
+else
+  rm -f -r a.out a.exe b.out conftest.$ac_ext conftest.o conftest.obj conftest.dSYM
+  ac_no_link=yes
+  # Setting cross_compile will disable run tests; it will
+  # also disable AC_CHECK_FILE but that's generally
+  # correct if we can't link.
+  cross_compiling=yes
+  EXEEXT=
+  # Check that the compiler produces executables we can run.  If not, either
+# the compiler is broken, or we cross compile.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5
+$as_echo_n "checking whether we are cross compiling... " >&6; }
+if test "$cross_compiling" != yes; then
+  { { ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_link") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }
+  if { ac_try='./conftest$ac_cv_exeext'
+  { { case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_try") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; }; then
+    cross_compiling=no
+  else
+    if test "$cross_compiling" = maybe; then
+	cross_compiling=yes
+    else
+	{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "cannot run C compiled programs.
+If you meant to cross compile, use \`--host'.
+See \`config.log' for more details" "$LINENO" 5; }
+    fi
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5
+$as_echo "$cross_compiling" >&6; }
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5
+$as_echo_n "checking for suffix of object files... " >&6; }
+if ${ac_cv_objext+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.o conftest.obj
+if { { ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_compile") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; then :
+  for ac_file in conftest.o conftest.obj conftest.*; do
+  test -f "$ac_file" || continue;
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;;
+    *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'`
+       break;;
+  esac
+done
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "cannot compute suffix of object files: cannot compile
+See \`config.log' for more details" "$LINENO" 5; }
+fi
+rm -f conftest.$ac_cv_objext conftest.$ac_ext
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5
+$as_echo "$ac_cv_objext" >&6; }
+OBJEXT=$ac_cv_objext
+ac_objext=$OBJEXT
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5
+$as_echo_n "checking whether we are using the GNU C compiler... " >&6; }
+if ${ac_cv_c_compiler_gnu+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+#ifndef __GNUC__
+       choke me
+#endif
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  ac_compiler_gnu=yes
+else
+  ac_compiler_gnu=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+ac_cv_c_compiler_gnu=$ac_compiler_gnu
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5
+$as_echo "$ac_cv_c_compiler_gnu" >&6; }
+if test $ac_compiler_gnu = yes; then
+  GCC=yes
+else
+  GCC=
+fi
+ac_test_CFLAGS=${CFLAGS+set}
+ac_save_CFLAGS=$CFLAGS
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5
+$as_echo_n "checking whether $CC accepts -g... " >&6; }
+if ${ac_cv_prog_cc_g+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  ac_save_c_werror_flag=$ac_c_werror_flag
+   ac_c_werror_flag=yes
+   ac_cv_prog_cc_g=no
+   CFLAGS="-g"
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  ac_cv_prog_cc_g=yes
+else
+  CFLAGS=""
+      cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+
+else
+  ac_c_werror_flag=$ac_save_c_werror_flag
+	 CFLAGS="-g"
+	 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  ac_cv_prog_cc_g=yes
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+   ac_c_werror_flag=$ac_save_c_werror_flag
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5
+$as_echo "$ac_cv_prog_cc_g" >&6; }
+if test "$ac_test_CFLAGS" = set; then
+  CFLAGS=$ac_save_CFLAGS
+elif test $ac_cv_prog_cc_g = yes; then
+  if test "$GCC" = yes; then
+    CFLAGS="-g -O2"
+  else
+    CFLAGS="-g"
+  fi
+else
+  if test "$GCC" = yes; then
+    CFLAGS="-O2"
+  else
+    CFLAGS=
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5
+$as_echo_n "checking for $CC option to accept ISO C89... " >&6; }
+if ${ac_cv_prog_cc_c89+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  ac_cv_prog_cc_c89=no
+ac_save_CC=$CC
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+#include <stdarg.h>
+#include <stdio.h>
+struct stat;
+/* Most of the following tests are stolen from RCS 5.7's src/conf.sh.  */
+struct buf { int x; };
+FILE * (*rcsopen) (struct buf *, struct stat *, int);
+static char *e (p, i)
+     char **p;
+     int i;
+{
+  return p[i];
+}
+static char *f (char * (*g) (char **, int), char **p, ...)
+{
+  char *s;
+  va_list v;
+  va_start (v,p);
+  s = g (p, va_arg (v,int));
+  va_end (v);
+  return s;
+}
+
+/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default.  It has
+   function prototypes and stuff, but not '\xHH' hex character constants.
+   These don't provoke an error unfortunately, instead are silently treated
+   as 'x'.  The following induces an error, until -std is added to get
+   proper ANSI mode.  Curiously '\x00'!='x' always comes out true, for an
+   array size at least.  It's necessary to write '\x00'==0 to get something
+   that's true only with -std.  */
+int osf4_cc_array ['\x00' == 0 ? 1 : -1];
+
+/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters
+   inside strings and character constants.  */
+#define FOO(x) 'x'
+int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1];
+
+int test (int i, double x);
+struct s1 {int (*f) (int a);};
+struct s2 {int (*f) (double a);};
+int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int);
+int argc;
+char **argv;
+int
+main ()
+{
+return f (e, argv, 0) != argv[0]  ||  f (e, argv, 1) != argv[1];
+  ;
+  return 0;
+}
+_ACEOF
+for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \
+	-Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__"
+do
+  CC="$ac_save_CC $ac_arg"
+  if ac_fn_c_try_compile "$LINENO"; then :
+  ac_cv_prog_cc_c89=$ac_arg
+fi
+rm -f core conftest.err conftest.$ac_objext
+  test "x$ac_cv_prog_cc_c89" != "xno" && break
+done
+rm -f conftest.$ac_ext
+CC=$ac_save_CC
+
+fi
+# AC_CACHE_VAL
+case "x$ac_cv_prog_cc_c89" in
+  x)
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5
+$as_echo "none needed" >&6; } ;;
+  xno)
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5
+$as_echo "unsupported" >&6; } ;;
+  *)
+    CC="$CC $ac_cv_prog_cc_c89"
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5
+$as_echo "$ac_cv_prog_cc_c89" >&6; } ;;
+esac
+if test "x$ac_cv_prog_cc_c89" != xno; then :
+
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC understands -c and -o together" >&5
+$as_echo_n "checking whether $CC understands -c and -o together... " >&6; }
+if ${am_cv_prog_cc_c_o+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+  # Make sure it works both with $CC and with simple cc.
+  # Following AC_PROG_CC_C_O, we do the test twice because some
+  # compilers refuse to overwrite an existing .o file with -o,
+  # though they will create one.
+  am_cv_prog_cc_c_o=yes
+  for am_i in 1 2; do
+    if { echo "$as_me:$LINENO: $CC -c conftest.$ac_ext -o conftest2.$ac_objext" >&5
+   ($CC -c conftest.$ac_ext -o conftest2.$ac_objext) >&5 2>&5
+   ac_status=$?
+   echo "$as_me:$LINENO: \$? = $ac_status" >&5
+   (exit $ac_status); } \
+         && test -f conftest2.$ac_objext; then
+      : OK
+    else
+      am_cv_prog_cc_c_o=no
+      break
+    fi
+  done
+  rm -f core conftest*
+  unset am_i
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_prog_cc_c_o" >&5
+$as_echo "$am_cv_prog_cc_c_o" >&6; }
+if test "$am_cv_prog_cc_c_o" != yes; then
+   # Losing compiler, so override with the script.
+   # FIXME: It is wrong to rewrite CC.
+   # But if we don't then we get into trouble of one sort or another.
+   # A longer-term fix would be to have automake use am__CC in this case,
+   # and then we could set am__CC="\$(top_srcdir)/compile \$(CC)"
+   CC="$am_aux_dir/compile $CC"
+fi
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+DEPDIR="${am__leading_dot}deps"
+
+ac_config_commands="$ac_config_commands depfiles"
+
+
+am_make=${MAKE-make}
+cat > confinc << 'END'
+am__doit:
+	@echo this is the am__doit target
+.PHONY: am__doit
+END
+# If we don't find an include directive, just comment out the code.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for style of include used by $am_make" >&5
+$as_echo_n "checking for style of include used by $am_make... " >&6; }
+am__include="#"
+am__quote=
+_am_result=none
+# First try GNU make style include.
+echo "include confinc" > confmf
+# Ignore all kinds of additional output from 'make'.
+case `$am_make -s -f confmf 2> /dev/null` in #(
+*the\ am__doit\ target*)
+  am__include=include
+  am__quote=
+  _am_result=GNU
+  ;;
+esac
+# Now try BSD make style include.
+if test "$am__include" = "#"; then
+   echo '.include "confinc"' > confmf
+   case `$am_make -s -f confmf 2> /dev/null` in #(
+   *the\ am__doit\ target*)
+     am__include=.include
+     am__quote="\""
+     _am_result=BSD
+     ;;
+   esac
+fi
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $_am_result" >&5
+$as_echo "$_am_result" >&6; }
+rm -f confinc confmf
+
+# Check whether --enable-dependency-tracking was given.
+if test "${enable_dependency_tracking+set}" = set; then :
+  enableval=$enable_dependency_tracking;
+fi
+
+if test "x$enable_dependency_tracking" != xno; then
+  am_depcomp="$ac_aux_dir/depcomp"
+  AMDEPBACKSLASH='\'
+  am__nodep='_no'
+fi
+ if test "x$enable_dependency_tracking" != xno; then
+  AMDEP_TRUE=
+  AMDEP_FALSE='#'
+else
+  AMDEP_TRUE='#'
+  AMDEP_FALSE=
+fi
+
+
+
+depcc="$CC"   am_compiler_list=
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5
+$as_echo_n "checking dependency style of $depcc... " >&6; }
+if ${am_cv_CC_dependencies_compiler_type+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then
+  # We make a subdir and do the tests there.  Otherwise we can end up
+  # making bogus files that we don't know about and never remove.  For
+  # instance it was reported that on HP-UX the gcc test will end up
+  # making a dummy file named 'D' -- because '-MD' means "put the output
+  # in D".
+  rm -rf conftest.dir
+  mkdir conftest.dir
+  # Copy depcomp to subdir because otherwise we won't find it if we're
+  # using a relative directory.
+  cp "$am_depcomp" conftest.dir
+  cd conftest.dir
+  # We will build objects and dependencies in a subdirectory because
+  # it helps to detect inapplicable dependency modes.  For instance
+  # both Tru64's cc and ICC support -MD to output dependencies as a
+  # side effect of compilation, but ICC will put the dependencies in
+  # the current directory while Tru64 will put them in the object
+  # directory.
+  mkdir sub
+
+  am_cv_CC_dependencies_compiler_type=none
+  if test "$am_compiler_list" = ""; then
+     am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp`
+  fi
+  am__universal=false
+  case " $depcc " in #(
+     *\ -arch\ *\ -arch\ *) am__universal=true ;;
+     esac
+
+  for depmode in $am_compiler_list; do
+    # Setup a source with many dependencies, because some compilers
+    # like to wrap large dependency lists on column 80 (with \), and
+    # we should not choose a depcomp mode which is confused by this.
+    #
+    # We need to recreate these files for each test, as the compiler may
+    # overwrite some of them when testing with obscure command lines.
+    # This happens at least with the AIX C compiler.
+    : > sub/conftest.c
+    for i in 1 2 3 4 5 6; do
+      echo '#include "conftst'$i'.h"' >> sub/conftest.c
+      # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with
+      # Solaris 10 /bin/sh.
+      echo '/* dummy */' > sub/conftst$i.h
+    done
+    echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf
+
+    # We check with '-c' and '-o' for the sake of the "dashmstdout"
+    # mode.  It turns out that the SunPro C++ compiler does not properly
+    # handle '-M -o', and we need to detect this.  Also, some Intel
+    # versions had trouble with output in subdirs.
+    am__obj=sub/conftest.${OBJEXT-o}
+    am__minus_obj="-o $am__obj"
+    case $depmode in
+    gcc)
+      # This depmode causes a compiler race in universal mode.
+      test "$am__universal" = false || continue
+      ;;
+    nosideeffect)
+      # After this tag, mechanisms are not by side-effect, so they'll
+      # only be used when explicitly requested.
+      if test "x$enable_dependency_tracking" = xyes; then
+	continue
+      else
+	break
+      fi
+      ;;
+    msvc7 | msvc7msys | msvisualcpp | msvcmsys)
+      # This compiler won't grok '-c -o', but also, the minuso test has
+      # not run yet.  These depmodes are late enough in the game, and
+      # so weak that their functioning should not be impacted.
+      am__obj=conftest.${OBJEXT-o}
+      am__minus_obj=
+      ;;
+    none) break ;;
+    esac
+    if depmode=$depmode \
+       source=sub/conftest.c object=$am__obj \
+       depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \
+       $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \
+         >/dev/null 2>conftest.err &&
+       grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 &&
+       grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 &&
+       grep $am__obj sub/conftest.Po > /dev/null 2>&1 &&
+       ${MAKE-make} -s -f confmf > /dev/null 2>&1; then
+      # icc doesn't choke on unknown options, it will just issue warnings
+      # or remarks (even with -Werror).  So we grep stderr for any message
+      # that says an option was ignored or not supported.
+      # When given -MP, icc 7.0 and 7.1 complain thusly:
+      #   icc: Command line warning: ignoring option '-M'; no argument required
+      # The diagnosis changed in icc 8.0:
+      #   icc: Command line remark: option '-MP' not supported
+      if (grep 'ignoring option' conftest.err ||
+          grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else
+        am_cv_CC_dependencies_compiler_type=$depmode
+        break
+      fi
+    fi
+  done
+
+  cd ..
+  rm -rf conftest.dir
+else
+  am_cv_CC_dependencies_compiler_type=none
+fi
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CC_dependencies_compiler_type" >&5
+$as_echo "$am_cv_CC_dependencies_compiler_type" >&6; }
+CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type
+
+ if
+  test "x$enable_dependency_tracking" != xno \
+  && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then
+  am__fastdepCC_TRUE=
+  am__fastdepCC_FALSE='#'
+else
+  am__fastdepCC_TRUE='#'
+  am__fastdepCC_FALSE=
+fi
+
+
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}as", so it can be a program name with args.
+set dummy ${ac_tool_prefix}as; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_AS+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$AS"; then
+  ac_cv_prog_AS="$AS" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_AS="${ac_tool_prefix}as"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+AS=$ac_cv_prog_AS
+if test -n "$AS"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AS" >&5
+$as_echo "$AS" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_AS"; then
+  ac_ct_AS=$AS
+  # Extract the first word of "as", so it can be a program name with args.
+set dummy as; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_ac_ct_AS+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_AS"; then
+  ac_cv_prog_ac_ct_AS="$ac_ct_AS" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_AS="as"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_AS=$ac_cv_prog_ac_ct_AS
+if test -n "$ac_ct_AS"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AS" >&5
+$as_echo "$ac_ct_AS" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+  if test "x$ac_ct_AS" = x; then
+    AS="as"
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    AS=$ac_ct_AS
+  fi
+else
+  AS="$ac_cv_prog_AS"
+fi
+
+# By default we simply use the C compiler to build assembly code.
+
+test "${CCAS+set}" = set || CCAS=$CC
+test "${CCASFLAGS+set}" = set || CCASFLAGS=$CFLAGS
+
+
+
+depcc="$CCAS"   am_compiler_list=
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5
+$as_echo_n "checking dependency style of $depcc... " >&6; }
+if ${am_cv_CCAS_dependencies_compiler_type+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then
+  # We make a subdir and do the tests there.  Otherwise we can end up
+  # making bogus files that we don't know about and never remove.  For
+  # instance it was reported that on HP-UX the gcc test will end up
+  # making a dummy file named 'D' -- because '-MD' means "put the output
+  # in D".
+  rm -rf conftest.dir
+  mkdir conftest.dir
+  # Copy depcomp to subdir because otherwise we won't find it if we're
+  # using a relative directory.
+  cp "$am_depcomp" conftest.dir
+  cd conftest.dir
+  # We will build objects and dependencies in a subdirectory because
+  # it helps to detect inapplicable dependency modes.  For instance
+  # both Tru64's cc and ICC support -MD to output dependencies as a
+  # side effect of compilation, but ICC will put the dependencies in
+  # the current directory while Tru64 will put them in the object
+  # directory.
+  mkdir sub
+
+  am_cv_CCAS_dependencies_compiler_type=none
+  if test "$am_compiler_list" = ""; then
+     am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp`
+  fi
+  am__universal=false
+
+
+  for depmode in $am_compiler_list; do
+    # Setup a source with many dependencies, because some compilers
+    # like to wrap large dependency lists on column 80 (with \), and
+    # we should not choose a depcomp mode which is confused by this.
+    #
+    # We need to recreate these files for each test, as the compiler may
+    # overwrite some of them when testing with obscure command lines.
+    # This happens at least with the AIX C compiler.
+    : > sub/conftest.c
+    for i in 1 2 3 4 5 6; do
+      echo '#include "conftst'$i'.h"' >> sub/conftest.c
+      # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with
+      # Solaris 10 /bin/sh.
+      echo '/* dummy */' > sub/conftst$i.h
+    done
+    echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf
+
+    # We check with '-c' and '-o' for the sake of the "dashmstdout"
+    # mode.  It turns out that the SunPro C++ compiler does not properly
+    # handle '-M -o', and we need to detect this.  Also, some Intel
+    # versions had trouble with output in subdirs.
+    am__obj=sub/conftest.${OBJEXT-o}
+    am__minus_obj="-o $am__obj"
+    case $depmode in
+    gcc)
+      # This depmode causes a compiler race in universal mode.
+      test "$am__universal" = false || continue
+      ;;
+    nosideeffect)
+      # After this tag, mechanisms are not by side-effect, so they'll
+      # only be used when explicitly requested.
+      if test "x$enable_dependency_tracking" = xyes; then
+	continue
+      else
+	break
+      fi
+      ;;
+    msvc7 | msvc7msys | msvisualcpp | msvcmsys)
+      # This compiler won't grok '-c -o', but also, the minuso test has
+      # not run yet.  These depmodes are late enough in the game, and
+      # so weak that their functioning should not be impacted.
+      am__obj=conftest.${OBJEXT-o}
+      am__minus_obj=
+      ;;
+    none) break ;;
+    esac
+    if depmode=$depmode \
+       source=sub/conftest.c object=$am__obj \
+       depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \
+       $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \
+         >/dev/null 2>conftest.err &&
+       grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 &&
+       grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 &&
+       grep $am__obj sub/conftest.Po > /dev/null 2>&1 &&
+       ${MAKE-make} -s -f confmf > /dev/null 2>&1; then
+      # icc doesn't choke on unknown options, it will just issue warnings
+      # or remarks (even with -Werror).  So we grep stderr for any message
+      # that says an option was ignored or not supported.
+      # When given -MP, icc 7.0 and 7.1 complain thusly:
+      #   icc: Command line warning: ignoring option '-M'; no argument required
+      # The diagnosis changed in icc 8.0:
+      #   icc: Command line remark: option '-MP' not supported
+      if (grep 'ignoring option' conftest.err ||
+          grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else
+        am_cv_CCAS_dependencies_compiler_type=$depmode
+        break
+      fi
+    fi
+  done
+
+  cd ..
+  rm -rf conftest.dir
+else
+  am_cv_CCAS_dependencies_compiler_type=none
+fi
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CCAS_dependencies_compiler_type" >&5
+$as_echo "$am_cv_CCAS_dependencies_compiler_type" >&6; }
+CCASDEPMODE=depmode=$am_cv_CCAS_dependencies_compiler_type
+
+ if
+  test "x$enable_dependency_tracking" != xno \
+  && test "$am_cv_CCAS_dependencies_compiler_type" = gcc3; then
+  am__fastdepCCAS_TRUE=
+  am__fastdepCCAS_FALSE='#'
+else
+  am__fastdepCCAS_TRUE='#'
+  am__fastdepCCAS_FALSE=
+fi
+
+
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ranlib; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_RANLIB+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$RANLIB"; then
+  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+RANLIB=$ac_cv_prog_RANLIB
+if test -n "$RANLIB"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5
+$as_echo "$RANLIB" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_RANLIB"; then
+  ac_ct_RANLIB=$RANLIB
+  # Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_ac_ct_RANLIB+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_RANLIB"; then
+  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_RANLIB="ranlib"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
+if test -n "$ac_ct_RANLIB"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5
+$as_echo "$ac_ct_RANLIB" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+  if test "x$ac_ct_RANLIB" = x; then
+    RANLIB=":"
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    RANLIB=$ac_ct_RANLIB
+  fi
+else
+  RANLIB="$ac_cv_prog_RANLIB"
+fi
+
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ar; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_AR+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$AR"; then
+  ac_cv_prog_AR="$AR" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_AR="${ac_tool_prefix}ar"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+AR=$ac_cv_prog_AR
+if test -n "$AR"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5
+$as_echo "$AR" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_AR"; then
+  ac_ct_AR=$AR
+  # Extract the first word of "ar", so it can be a program name with args.
+set dummy ar; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_ac_ct_AR+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_AR"; then
+  ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_AR="ar"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_AR=$ac_cv_prog_ac_ct_AR
+if test -n "$ac_ct_AR"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5
+$as_echo "$ac_ct_AR" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+  if test "x$ac_ct_AR" = x; then
+    AR="ar"
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    AR=$ac_ct_AR
+  fi
+else
+  AR="$ac_cv_prog_AR"
+fi
+
+
+# Make sure that we found the right avr cross-compiler.
+
+case "${CC}" in
+   *gcc*)
+       case "X`${CC} -dumpmachine`X" in
+           XavrX) ;;
+           *) as_fn_error $? "Wrong C compiler found; check the PATH!" "$LINENO" 5 ;;
+       esac
+       ;;
+   *) as_fn_error $? "Wrong C compiler found; check the PATH!" "$LINENO" 5 ;;
+esac
+case "${AS}" in
+   *avr*as*) ;;
+   *) as_fn_error $? "Wrong assembler found; check the PATH!" "$LINENO" 5 ;;
+esac
+case "${AR}" in
+   *avr*ar*) ;;
+   *) as_fn_error $? "Wrong archiver found; check the PATH!" "$LINENO" 5 ;;
+esac
+case "${RANLIB}" in
+   *avr*ranlib*) ;;
+   *) as_fn_error $? "Wrong ranlib found; check the PATH!" "$LINENO" 5 ;;
+esac
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ln -s works" >&5
+$as_echo_n "checking whether ln -s works... " >&6; }
+LN_S=$as_ln_s
+if test "$LN_S" = "ln -s"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no, using $LN_S" >&5
+$as_echo "no, using $LN_S" >&6; }
+fi
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${MAKE-make} sets \$(MAKE)" >&5
+$as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... " >&6; }
+set x ${MAKE-make}
+ac_make=`$as_echo "$2" | sed 's/+/p/g; s/[^a-zA-Z0-9_]/_/g'`
+if eval \${ac_cv_prog_make_${ac_make}_set+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat >conftest.make <<\_ACEOF
+SHELL = /bin/sh
+all:
+	@echo '@@@%%%=$(MAKE)=@@@%%%'
+_ACEOF
+# GNU make sometimes prints "make[1]: Entering ...", which would confuse us.
+case `${MAKE-make} -f conftest.make 2>/dev/null` in
+  *@@@%%%=?*=@@@%%%*)
+    eval ac_cv_prog_make_${ac_make}_set=yes;;
+  *)
+    eval ac_cv_prog_make_${ac_make}_set=no;;
+esac
+rm -f conftest.make
+fi
+if eval test \$ac_cv_prog_make_${ac_make}_set = yes; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+  SET_MAKE=
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+  SET_MAKE="MAKE=${MAKE-make}"
+fi
+
+
+GCC_VER=`${CC} -dumpversion`
+as_arg_v1=${GCC_VER}
+as_arg_v2="5.1.0"
+awk "$as_awk_strverscmp" v1="$as_arg_v1" v2="$as_arg_v2" /dev/null
+case $? in #(
+  1) :
+    DEV_LIB="no" ;; #(
+  0) :
+    DEV_LIB="yes" ;; #(
+  2) :
+    DEV_LIB="yes" ;; #(
+  *) :
+     ;;
+esac
+ if test "x${GCC_VER}" = "x5.1.0"; then
+  HAS_GCC_5_1_TRUE=
+  HAS_GCC_5_1_FALSE='#'
+else
+  HAS_GCC_5_1_TRUE='#'
+  HAS_GCC_5_1_FALSE=
+fi
+
+
+# Check whether --enable-device-lib was given.
+if test "${enable_device_lib+set}" = set; then :
+  enableval=$enable_device_lib; enable_device_lib=true
+else
+  case "${DEV_LIB}" in
+  yes) enable_device_lib=true
+       { $as_echo "$as_me:${as_lineno-$LINENO}: Enabled device library" >&5
+$as_echo "$as_me: Enabled device library" >&6;} ;;
+  *) ;;
+ esac
+fi
+
+
+ if test x$enable_device_lib = xtrue; then
+  HAS_DEV_LIB_TRUE=
+  HAS_DEV_LIB_FALSE='#'
+else
+  HAS_DEV_LIB_TRUE='#'
+  HAS_DEV_LIB_FALSE=
+fi
+
+
+
+
+# Check whether --enable-doc was given.
+if test "${enable_doc+set}" = set; then :
+  enableval=$enable_doc; case "${enableval}" in
+  yes) enable_doc=yes ;;
+  no)  enable_doc=no ;;
+  *)   as_fn_error $? "bad value ${enableval} for global doc option" "$LINENO" 5 ;;
+ esac
+else
+  enable_doc=no
+fi
+# Check whether --enable-html-doc was given.
+if test "${enable_html_doc+set}" = set; then :
+  enableval=$enable_html_doc; case "${enableval}" in
+  yes) html_doc=yes ;;
+  no)  html_doc=no ;;
+  *)   as_fn_error $? "bad value ${enableval} for html-doc option" "$LINENO" 5 ;;
+ esac
+else
+  html_doc=yes
+fi
+
+# Check whether --enable-xml-doc was given.
+if test "${enable_xml_doc+set}" = set; then :
+  enableval=$enable_xml_doc; case "${enableval}" in
+  yes) xml_doc=yes ;;
+  no)  xml_doc=no ;;
+  *)   as_fn_error $? "bad value ${enableval} for xml-doc option" "$LINENO" 5 ;;
+ esac
+else
+  xml_doc=yes
+fi
+
+# Check whether --enable-pdf-doc was given.
+if test "${enable_pdf_doc+set}" = set; then :
+  enableval=$enable_pdf_doc; case "${enableval}" in
+  yes) pdf_doc=yes ;;
+  no)  pdf_doc=no ;;
+  *)   as_fn_error $? "bad value ${enableval} for pdf-doc option" "$LINENO" 5 ;;
+ esac
+else
+  pdf_doc=yes
+fi
+
+# Check whether --enable-man-doc was given.
+if test "${enable_man_doc+set}" = set; then :
+  enableval=$enable_man_doc; case "${enableval}" in
+  yes) man_doc=yes ;;
+  no)  man_doc=no ;;
+  *)   as_fn_error $? "bad value ${enableval} for man-doc option" "$LINENO" 5 ;;
+ esac
+else
+  man_doc=yes
+fi
+
+# Check whether --enable-versioned-doc was given.
+if test "${enable_versioned_doc+set}" = set; then :
+  enableval=$enable_versioned_doc; case "${enableval}" in
+  yes) versioned_doc=yes ;;
+  no)  versioned_doc=no ;;
+  *)   as_fn_error $? "bad value ${enableval} for versioned-doc option" "$LINENO" 5 ;;
+ esac
+else
+  versioned_doc=yes
+fi
+
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for doxygen" >&5
+$as_echo_n "checking for doxygen... " >&6; }
+dox_ver=`doxygen --version 2>/dev/null`
+if test "x$dox_ver" = "x"; then
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+else
+	# FIXME: should also check for dox_ver >= 1.4.1
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+	if test "$pdf_doc" = "yes"; then
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: Enabling PDF docs" >&5
+$as_echo "$as_me: Enabling PDF docs" >&6;}
+		TARGET_DOX_PDF=dox-pdf
+		INSTALL_DOX_PDF=install-dox-pdf
+	fi
+	if test "$html_doc" = "yes"; then
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: Enabling HTML docs" >&5
+$as_echo "$as_me: Enabling HTML docs" >&6;}
+		TARGET_DOX_HTML=dox-html
+		INSTALL_DOX_HTML=install-dox-html
+	fi
+	if test "$xml_doc" = "yes"; then
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: Enabling XML docs" >&5
+$as_echo "$as_me: Enabling XML docs" >&6;}
+		TARGET_DOX_XML=dox-xml
+		INSTALL_DOX_XML=install-dox-xml
+	fi
+	if test "$man_doc" = "yes"; then
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: Enabling man pages" >&5
+$as_echo "$as_me: Enabling man pages" >&6;}
+		TARGET_DOX_HTML=dox-html
+		INSTALL_DOX_MAN=install-dox-man
+	fi
+fi
+
+
+
+
+
+
+
+
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for pngtopnm" >&5
+$as_echo_n "checking for pngtopnm... " >&6; }
+has_pngtopnm=`pngtopnm --version 2>&1 | grep -c -i Version`
+if test "$has_pngtopnm" = "1"; then
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+	PNGTOPNM="pngtopnm"
+else
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+	PNGTOPNM="cat"
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for pnmtopng" >&5
+$as_echo_n "checking for pnmtopng... " >&6; }
+has_pnmtopng=`pnmtopng --version 2>&1 | grep -c -i Version`
+if test "$has_pnmtopng" = "1"; then
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+	PNMTOPNG="pnmtopng"
+else
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+	PNMTOPNG="cat"
+    PNGTOPNM="cat"
+fi
+
+
+
+
+if test "$versioned_doc" = "yes"; then
+	DOC_INST_DIR='${DESTDIR}${datadir}/doc/avr-libc-$(VERSION)'
+	AVR_LIBC_USER_MANUAL="avr-libc-user-manual-${VERSION}"
+else
+	DOC_INST_DIR='${DESTDIR}${datadir}/doc/avr-libc'
+	AVR_LIBC_USER_MANUAL="avr-libc-user-manual"
+fi
+
+if test "$enable_doc" = "yes"; then
+	DOCSDIR='api'
+else
+	DOCSDIR=''
+fi
+
+
+
+
+
+# Check whether --enable-debug-info was given.
+if test "${enable_debug_info+set}" = set; then :
+  enableval=$enable_debug_info; case "${enableval}" in
+  yes|dwarf2|dwarf-2) debuginfo=dwarf2 ;;
+  no)                 debuginfo="" ;;
+  stabs)              debuginfo=stabs ;;
+  dwarf4|dwarf-4)     debuginfo=dwarf4 ;;
+  dwarf)              debuginfo=dwarf ;;
+  *)                  as_fn_error $? "bad value ${enableval} for --enable-debug-info option; should be either stabs, dwarf-2, or dwarf-4" "$LINENO" 5 ;;
+ esac
+else
+  debuginfo=""
+fi
+
+
+case "$debuginfo" in
+"")      CDEBUG=""; ASDEBUG="" ;;
+stabs)   CDEBUG="-gstabs"; ASDEBUG="-Wa,-gstabs" ;;
+dwarf2)  CDEBUG="-gdwarf-2"; ASDEBUG="-Wa,-gdwarf-2" ;;
+dwarf4)  CDEBUG="-gdwarf-4"; ASDEBUG="-Wa,-gdwarf-2" ;;
+dwarf)   CDEBUG="-gdwarf"; ASDEBUG="-Wa,-gdwarf-2" ;;
+esac
+
+
+
+
+FNO_JUMP_TABLES=""
+
+
+HAS_DELAY_CYCLES=0
+
+
+
+
+
+
+
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mno-tablejump"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${CC} supports -mno-tablejump" >&5
+$as_echo_n "checking whether ${CC} supports -mno-tablejump... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_mno_tablejump=yes
+else
+  has_mno_tablejump=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_mno_tablejump" = "xyes"
+    then
+      FNO_JUMP_TABLES="-mno-tablejump"
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_mno_tablejump" >&5
+$as_echo "$has_mno_tablejump" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-fno-jump-tables"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${CC} supports -fno-jump-tables" >&5
+$as_echo_n "checking whether ${CC} supports -fno-jump-tables... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_fno_jump_tables=yes
+else
+  has_fno_jump_tables=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_fno_jump_tables" = "xyes"
+    then
+      FNO_JUMP_TABLES="-fno-jump-tables"
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_fno_jump_tables" >&5
+$as_echo "$has_fno_jump_tables" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${CC} supports __builtin_avr_delay_cycles" >&5
+$as_echo_n "checking whether ${CC} supports __builtin_avr_delay_cycles... " >&6; }
+    echo "extern void __builtin_avr_delay_cycles(unsigned long);\
+    int main(void) { __builtin_avr_delay_cycles(42); return 0; }" |\
+    ${CC} -S -xc -o - - |\
+    grep __builtin_avr_delay_cycles >/dev/null
+    if test "$?" != "0"
+    then
+      HAS_DELAY_CYCLES=1
+      has_delay_cycles="yes"
+    else
+      has_delay_cycles="no"
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_delay_cycles" >&5
+$as_echo "$has_delay_cycles" >&6; }
+    CC=${old_CC}
+
+
+
+
+
+
+# avr1
+ if true; then
+  HAS_avr1_TRUE=
+  HAS_avr1_FALSE='#'
+else
+  HAS_avr1_TRUE='#'
+  HAS_avr1_FALSE=
+fi
+
+ if true; then
+  HAS_at90s1200_TRUE=
+  HAS_at90s1200_FALSE='#'
+else
+  HAS_at90s1200_TRUE='#'
+  HAS_at90s1200_FALSE=
+fi
+
+ if true; then
+  HAS_attiny11_TRUE=
+  HAS_attiny11_FALSE='#'
+else
+  HAS_attiny11_TRUE='#'
+  HAS_attiny11_FALSE=
+fi
+
+ if true; then
+  HAS_attiny12_TRUE=
+  HAS_attiny12_FALSE='#'
+else
+  HAS_attiny12_TRUE='#'
+  HAS_attiny12_FALSE=
+fi
+
+ if true; then
+  HAS_attiny15_TRUE=
+  HAS_attiny15_FALSE='#'
+else
+  HAS_attiny15_TRUE='#'
+  HAS_attiny15_FALSE=
+fi
+
+ if true; then
+  HAS_attiny28_TRUE=
+  HAS_attiny28_FALSE='#'
+else
+  HAS_attiny28_TRUE='#'
+  HAS_attiny28_FALSE=
+fi
+
+
+
+# avr2
+ if true; then
+  HAS_avr2_TRUE=
+  HAS_avr2_FALSE='#'
+else
+  HAS_avr2_TRUE='#'
+  HAS_avr2_FALSE=
+fi
+
+ if true; then
+  HAS_at90s2313_TRUE=
+  HAS_at90s2313_FALSE='#'
+else
+  HAS_at90s2313_TRUE='#'
+  HAS_at90s2313_FALSE=
+fi
+
+ if true; then
+  HAS_at90s2323_TRUE=
+  HAS_at90s2323_FALSE='#'
+else
+  HAS_at90s2323_TRUE='#'
+  HAS_at90s2323_FALSE=
+fi
+
+ if true; then
+  HAS_at90s2333_TRUE=
+  HAS_at90s2333_FALSE='#'
+else
+  HAS_at90s2333_TRUE='#'
+  HAS_at90s2333_FALSE=
+fi
+
+ if true; then
+  HAS_at90s2343_TRUE=
+  HAS_at90s2343_FALSE='#'
+else
+  HAS_at90s2343_TRUE='#'
+  HAS_at90s2343_FALSE=
+fi
+
+ if true; then
+  HAS_at90s4414_TRUE=
+  HAS_at90s4414_FALSE='#'
+else
+  HAS_at90s4414_TRUE='#'
+  HAS_at90s4414_FALSE=
+fi
+
+ if true; then
+  HAS_at90s4433_TRUE=
+  HAS_at90s4433_FALSE='#'
+else
+  HAS_at90s4433_TRUE='#'
+  HAS_at90s4433_FALSE=
+fi
+
+ if true; then
+  HAS_at90s4434_TRUE=
+  HAS_at90s4434_FALSE='#'
+else
+  HAS_at90s4434_TRUE='#'
+  HAS_at90s4434_FALSE=
+fi
+
+ if true; then
+  HAS_at90s8515_TRUE=
+  HAS_at90s8515_FALSE='#'
+else
+  HAS_at90s8515_TRUE='#'
+  HAS_at90s8515_FALSE=
+fi
+
+ if true; then
+  HAS_at90c8534_TRUE=
+  HAS_at90c8534_FALSE='#'
+else
+  HAS_at90c8534_TRUE='#'
+  HAS_at90c8534_FALSE=
+fi
+
+ if true; then
+  HAS_at90s8535_TRUE=
+  HAS_at90s8535_FALSE='#'
+else
+  HAS_at90s8535_TRUE='#'
+  HAS_at90s8535_FALSE=
+fi
+
+ if true; then
+  HAS_attiny22_TRUE=
+  HAS_attiny22_FALSE='#'
+else
+  HAS_attiny22_TRUE='#'
+  HAS_attiny22_FALSE=
+fi
+
+ if true; then
+  HAS_attiny26_TRUE=
+  HAS_attiny26_FALSE='#'
+else
+  HAS_attiny26_TRUE='#'
+  HAS_attiny26_FALSE=
+fi
+
+
+
+#avr25
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avr25"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr25" >&5
+$as_echo_n "checking if ${CC} has support for avr25... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avr25=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avr25" = "xyes"; then
+  HAS_avr25_TRUE=
+  HAS_avr25_FALSE='#'
+else
+  HAS_avr25_TRUE='#'
+  HAS_avr25_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata5272"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5272" >&5
+$as_echo_n "checking if ${CC} has support for ata5272... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata5272=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata5272" = "xyes"; then
+  HAS_ata5272_TRUE=
+  HAS_ata5272_FALSE='#'
+else
+  HAS_ata5272_TRUE='#'
+  HAS_ata5272_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata6616c"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6616c" >&5
+$as_echo_n "checking if ${CC} has support for ata6616c... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata6616c=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata6616c" = "xyes"; then
+  HAS_ata6616c_TRUE=
+  HAS_ata6616c_FALSE='#'
+else
+  HAS_ata6616c_TRUE='#'
+  HAS_ata6616c_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny13"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny13" >&5
+$as_echo_n "checking if ${CC} has support for attiny13... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny13=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny13" = "xyes"; then
+  HAS_attiny13_TRUE=
+  HAS_attiny13_FALSE='#'
+else
+  HAS_attiny13_TRUE='#'
+  HAS_attiny13_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny13a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny13a" >&5
+$as_echo_n "checking if ${CC} has support for attiny13a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny13a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny13a" = "xyes"; then
+  HAS_attiny13a_TRUE=
+  HAS_attiny13a_FALSE='#'
+else
+  HAS_attiny13a_TRUE='#'
+  HAS_attiny13a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny2313"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny2313" >&5
+$as_echo_n "checking if ${CC} has support for attiny2313... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny2313=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny2313" = "xyes"; then
+  HAS_attiny2313_TRUE=
+  HAS_attiny2313_FALSE='#'
+else
+  HAS_attiny2313_TRUE='#'
+  HAS_attiny2313_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny2313a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny2313a" >&5
+$as_echo_n "checking if ${CC} has support for attiny2313a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny2313a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny2313a" = "xyes"; then
+  HAS_attiny2313a_TRUE=
+  HAS_attiny2313a_FALSE='#'
+else
+  HAS_attiny2313a_TRUE='#'
+  HAS_attiny2313a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny24"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny24" >&5
+$as_echo_n "checking if ${CC} has support for attiny24... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny24=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny24" = "xyes"; then
+  HAS_attiny24_TRUE=
+  HAS_attiny24_FALSE='#'
+else
+  HAS_attiny24_TRUE='#'
+  HAS_attiny24_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny24a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny24a" >&5
+$as_echo_n "checking if ${CC} has support for attiny24a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny24a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny24a" = "xyes"; then
+  HAS_attiny24a_TRUE=
+  HAS_attiny24a_FALSE='#'
+else
+  HAS_attiny24a_TRUE='#'
+  HAS_attiny24a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny25"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny25" >&5
+$as_echo_n "checking if ${CC} has support for attiny25... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny25=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny25" = "xyes"; then
+  HAS_attiny25_TRUE=
+  HAS_attiny25_FALSE='#'
+else
+  HAS_attiny25_TRUE='#'
+  HAS_attiny25_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny261"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny261" >&5
+$as_echo_n "checking if ${CC} has support for attiny261... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny261=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny261" = "xyes"; then
+  HAS_attiny261_TRUE=
+  HAS_attiny261_FALSE='#'
+else
+  HAS_attiny261_TRUE='#'
+  HAS_attiny261_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny261a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny261a" >&5
+$as_echo_n "checking if ${CC} has support for attiny261a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny261a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny261a" = "xyes"; then
+  HAS_attiny261a_TRUE=
+  HAS_attiny261a_FALSE='#'
+else
+  HAS_attiny261a_TRUE='#'
+  HAS_attiny261a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny43u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny43u" >&5
+$as_echo_n "checking if ${CC} has support for attiny43u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny43u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny43u" = "xyes"; then
+  HAS_attiny43u_TRUE=
+  HAS_attiny43u_FALSE='#'
+else
+  HAS_attiny43u_TRUE='#'
+  HAS_attiny43u_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny4313"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny4313" >&5
+$as_echo_n "checking if ${CC} has support for attiny4313... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny4313=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny4313" = "xyes"; then
+  HAS_attiny4313_TRUE=
+  HAS_attiny4313_FALSE='#'
+else
+  HAS_attiny4313_TRUE='#'
+  HAS_attiny4313_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny44"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny44" >&5
+$as_echo_n "checking if ${CC} has support for attiny44... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny44=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny44" = "xyes"; then
+  HAS_attiny44_TRUE=
+  HAS_attiny44_FALSE='#'
+else
+  HAS_attiny44_TRUE='#'
+  HAS_attiny44_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny441"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny441" >&5
+$as_echo_n "checking if ${CC} has support for attiny441... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny441=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny441" = "xyes"; then
+  HAS_attiny441_TRUE=
+  HAS_attiny441_FALSE='#'
+else
+  HAS_attiny441_TRUE='#'
+  HAS_attiny441_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny44a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny44a" >&5
+$as_echo_n "checking if ${CC} has support for attiny44a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny44a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny44a" = "xyes"; then
+  HAS_attiny44a_TRUE=
+  HAS_attiny44a_FALSE='#'
+else
+  HAS_attiny44a_TRUE='#'
+  HAS_attiny44a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny45"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny45" >&5
+$as_echo_n "checking if ${CC} has support for attiny45... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny45=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny45" = "xyes"; then
+  HAS_attiny45_TRUE=
+  HAS_attiny45_FALSE='#'
+else
+  HAS_attiny45_TRUE='#'
+  HAS_attiny45_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny461"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny461" >&5
+$as_echo_n "checking if ${CC} has support for attiny461... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny461=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny461" = "xyes"; then
+  HAS_attiny461_TRUE=
+  HAS_attiny461_FALSE='#'
+else
+  HAS_attiny461_TRUE='#'
+  HAS_attiny461_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny461a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny461a" >&5
+$as_echo_n "checking if ${CC} has support for attiny461a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny461a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny461a" = "xyes"; then
+  HAS_attiny461a_TRUE=
+  HAS_attiny461a_FALSE='#'
+else
+  HAS_attiny461a_TRUE='#'
+  HAS_attiny461a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny48"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny48" >&5
+$as_echo_n "checking if ${CC} has support for attiny48... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny48=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny48" = "xyes"; then
+  HAS_attiny48_TRUE=
+  HAS_attiny48_FALSE='#'
+else
+  HAS_attiny48_TRUE='#'
+  HAS_attiny48_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny828"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny828" >&5
+$as_echo_n "checking if ${CC} has support for attiny828... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny828=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny828" = "xyes"; then
+  HAS_attiny828_TRUE=
+  HAS_attiny828_FALSE='#'
+else
+  HAS_attiny828_TRUE='#'
+  HAS_attiny828_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny84"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny84" >&5
+$as_echo_n "checking if ${CC} has support for attiny84... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny84=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny84" = "xyes"; then
+  HAS_attiny84_TRUE=
+  HAS_attiny84_FALSE='#'
+else
+  HAS_attiny84_TRUE='#'
+  HAS_attiny84_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny841"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny841" >&5
+$as_echo_n "checking if ${CC} has support for attiny841... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny841=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny841" = "xyes"; then
+  HAS_attiny841_TRUE=
+  HAS_attiny841_FALSE='#'
+else
+  HAS_attiny841_TRUE='#'
+  HAS_attiny841_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny84a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny84a" >&5
+$as_echo_n "checking if ${CC} has support for attiny84a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny84a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny84a" = "xyes"; then
+  HAS_attiny84a_TRUE=
+  HAS_attiny84a_FALSE='#'
+else
+  HAS_attiny84a_TRUE='#'
+  HAS_attiny84a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny85"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny85" >&5
+$as_echo_n "checking if ${CC} has support for attiny85... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny85=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny85" = "xyes"; then
+  HAS_attiny85_TRUE=
+  HAS_attiny85_FALSE='#'
+else
+  HAS_attiny85_TRUE='#'
+  HAS_attiny85_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny861"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny861" >&5
+$as_echo_n "checking if ${CC} has support for attiny861... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny861=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny861" = "xyes"; then
+  HAS_attiny861_TRUE=
+  HAS_attiny861_FALSE='#'
+else
+  HAS_attiny861_TRUE='#'
+  HAS_attiny861_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny861a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny861a" >&5
+$as_echo_n "checking if ${CC} has support for attiny861a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny861a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny861a" = "xyes"; then
+  HAS_attiny861a_TRUE=
+  HAS_attiny861a_FALSE='#'
+else
+  HAS_attiny861a_TRUE='#'
+  HAS_attiny861a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny87"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny87" >&5
+$as_echo_n "checking if ${CC} has support for attiny87... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny87=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny87" = "xyes"; then
+  HAS_attiny87_TRUE=
+  HAS_attiny87_FALSE='#'
+else
+  HAS_attiny87_TRUE='#'
+  HAS_attiny87_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny88"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny88" >&5
+$as_echo_n "checking if ${CC} has support for attiny88... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny88=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny88" = "xyes"; then
+  HAS_attiny88_TRUE=
+  HAS_attiny88_FALSE='#'
+else
+  HAS_attiny88_TRUE='#'
+  HAS_attiny88_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at86rf401"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at86rf401" >&5
+$as_echo_n "checking if ${CC} has support for at86rf401... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at86rf401=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at86rf401" = "xyes"; then
+  HAS_at86rf401_TRUE=
+  HAS_at86rf401_FALSE='#'
+else
+  HAS_at86rf401_TRUE='#'
+  HAS_at86rf401_FALSE=
+fi
+
+
+
+# avr3
+ if true; then
+  HAS_avr3_TRUE=
+  HAS_avr3_FALSE='#'
+else
+  HAS_avr3_TRUE='#'
+  HAS_avr3_FALSE=
+fi
+
+ if true; then
+  HAS_at43usb320_TRUE=
+  HAS_at43usb320_FALSE='#'
+else
+  HAS_at43usb320_TRUE='#'
+  HAS_at43usb320_FALSE=
+fi
+
+ if true; then
+  HAS_at43usb355_TRUE=
+  HAS_at43usb355_FALSE='#'
+else
+  HAS_at43usb355_TRUE='#'
+  HAS_at43usb355_FALSE=
+fi
+
+ if true; then
+  HAS_at76c711_TRUE=
+  HAS_at76c711_FALSE='#'
+else
+  HAS_at76c711_TRUE='#'
+  HAS_at76c711_FALSE=
+fi
+
+
+#avr31
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avr31"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr31" >&5
+$as_echo_n "checking if ${CC} has support for avr31... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avr31=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avr31" = "xyes"; then
+  HAS_avr31_TRUE=
+  HAS_avr31_FALSE='#'
+else
+  HAS_avr31_TRUE='#'
+  HAS_avr31_FALSE=
+fi
+
+
+ if true; then
+  HAS_atmega103_TRUE=
+  HAS_atmega103_FALSE='#'
+else
+  HAS_atmega103_TRUE='#'
+  HAS_atmega103_FALSE=
+fi
+
+
+
+#avr35
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avr35"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr35" >&5
+$as_echo_n "checking if ${CC} has support for avr35... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avr35=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avr35" = "xyes"; then
+  HAS_avr35_TRUE=
+  HAS_avr35_FALSE='#'
+else
+  HAS_avr35_TRUE='#'
+  HAS_avr35_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90usb82"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb82" >&5
+$as_echo_n "checking if ${CC} has support for at90usb82... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90usb82=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90usb82" = "xyes"; then
+  HAS_at90usb82_TRUE=
+  HAS_at90usb82_FALSE='#'
+else
+  HAS_at90usb82_TRUE='#'
+  HAS_at90usb82_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90usb162"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb162" >&5
+$as_echo_n "checking if ${CC} has support for at90usb162... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90usb162=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90usb162" = "xyes"; then
+  HAS_at90usb162_TRUE=
+  HAS_at90usb162_FALSE='#'
+else
+  HAS_at90usb162_TRUE='#'
+  HAS_at90usb162_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata5505"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5505" >&5
+$as_echo_n "checking if ${CC} has support for ata5505... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata5505=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata5505" = "xyes"; then
+  HAS_ata5505_TRUE=
+  HAS_ata5505_FALSE='#'
+else
+  HAS_ata5505_TRUE='#'
+  HAS_ata5505_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata6617c"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6617c" >&5
+$as_echo_n "checking if ${CC} has support for ata6617c... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata6617c=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata6617c" = "xyes"; then
+  HAS_ata6617c_TRUE=
+  HAS_ata6617c_FALSE='#'
+else
+  HAS_ata6617c_TRUE='#'
+  HAS_ata6617c_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata664251"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata664251" >&5
+$as_echo_n "checking if ${CC} has support for ata664251... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata664251=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata664251" = "xyes"; then
+  HAS_ata664251_TRUE=
+  HAS_ata664251_FALSE='#'
+else
+  HAS_ata664251_TRUE='#'
+  HAS_ata664251_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega8u2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega8u2" >&5
+$as_echo_n "checking if ${CC} has support for atmega8u2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega8u2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega8u2" = "xyes"; then
+  HAS_atmega8u2_TRUE=
+  HAS_atmega8u2_FALSE='#'
+else
+  HAS_atmega8u2_TRUE='#'
+  HAS_atmega8u2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega16u2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16u2" >&5
+$as_echo_n "checking if ${CC} has support for atmega16u2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega16u2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega16u2" = "xyes"; then
+  HAS_atmega16u2_TRUE=
+  HAS_atmega16u2_FALSE='#'
+else
+  HAS_atmega16u2_TRUE='#'
+  HAS_atmega16u2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega32u2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32u2" >&5
+$as_echo_n "checking if ${CC} has support for atmega32u2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega32u2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega32u2" = "xyes"; then
+  HAS_atmega32u2_TRUE=
+  HAS_atmega32u2_FALSE='#'
+else
+  HAS_atmega32u2_TRUE='#'
+  HAS_atmega32u2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny167"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny167" >&5
+$as_echo_n "checking if ${CC} has support for attiny167... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny167=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny167" = "xyes"; then
+  HAS_attiny167_TRUE=
+  HAS_attiny167_FALSE='#'
+else
+  HAS_attiny167_TRUE='#'
+  HAS_attiny167_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny1634"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny1634" >&5
+$as_echo_n "checking if ${CC} has support for attiny1634... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny1634=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny1634" = "xyes"; then
+  HAS_attiny1634_TRUE=
+  HAS_attiny1634_FALSE='#'
+else
+  HAS_attiny1634_TRUE='#'
+  HAS_attiny1634_FALSE=
+fi
+
+
+
+# avr4
+ if true; then
+  HAS_avr4_TRUE=
+  HAS_avr4_FALSE='#'
+else
+  HAS_avr4_TRUE='#'
+  HAS_avr4_FALSE=
+fi
+
+ if true; then
+  HAS_atmega8_TRUE=
+  HAS_atmega8_FALSE='#'
+else
+  HAS_atmega8_TRUE='#'
+  HAS_atmega8_FALSE=
+fi
+
+ if true; then
+  HAS_atmega8515_TRUE=
+  HAS_atmega8515_FALSE='#'
+else
+  HAS_atmega8515_TRUE='#'
+  HAS_atmega8515_FALSE=
+fi
+
+ if true; then
+  HAS_atmega8535_TRUE=
+  HAS_atmega8535_FALSE='#'
+else
+  HAS_atmega8535_TRUE='#'
+  HAS_atmega8535_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata6285"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6285" >&5
+$as_echo_n "checking if ${CC} has support for ata6285... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata6285=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata6285" = "xyes"; then
+  HAS_ata6285_TRUE=
+  HAS_ata6285_FALSE='#'
+else
+  HAS_ata6285_TRUE='#'
+  HAS_ata6285_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata6286"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6286" >&5
+$as_echo_n "checking if ${CC} has support for ata6286... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata6286=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata6286" = "xyes"; then
+  HAS_ata6286_TRUE=
+  HAS_ata6286_FALSE='#'
+else
+  HAS_ata6286_TRUE='#'
+  HAS_ata6286_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata6289"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6289" >&5
+$as_echo_n "checking if ${CC} has support for ata6289... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata6289=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata6289" = "xyes"; then
+  HAS_ata6289_TRUE=
+  HAS_ata6289_FALSE='#'
+else
+  HAS_ata6289_TRUE='#'
+  HAS_ata6289_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata6612c"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6612c" >&5
+$as_echo_n "checking if ${CC} has support for ata6612c... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata6612c=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata6612c" = "xyes"; then
+  HAS_ata6612c_TRUE=
+  HAS_ata6612c_FALSE='#'
+else
+  HAS_ata6612c_TRUE='#'
+  HAS_ata6612c_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega8a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega8a" >&5
+$as_echo_n "checking if ${CC} has support for atmega8a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega8a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega8a" = "xyes"; then
+  HAS_atmega8a_TRUE=
+  HAS_atmega8a_FALSE='#'
+else
+  HAS_atmega8a_TRUE='#'
+  HAS_atmega8a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega48"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48" >&5
+$as_echo_n "checking if ${CC} has support for atmega48... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega48=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega48" = "xyes"; then
+  HAS_atmega48_TRUE=
+  HAS_atmega48_FALSE='#'
+else
+  HAS_atmega48_TRUE='#'
+  HAS_atmega48_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega48a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48a" >&5
+$as_echo_n "checking if ${CC} has support for atmega48a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega48a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega48a" = "xyes"; then
+  HAS_atmega48a_TRUE=
+  HAS_atmega48a_FALSE='#'
+else
+  HAS_atmega48a_TRUE='#'
+  HAS_atmega48a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega48pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega48pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega48pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega48pa" = "xyes"; then
+  HAS_atmega48pa_TRUE=
+  HAS_atmega48pa_FALSE='#'
+else
+  HAS_atmega48pa_TRUE='#'
+  HAS_atmega48pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega48pb"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48pb" >&5
+$as_echo_n "checking if ${CC} has support for atmega48pb... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega48pb=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega48pb" = "xyes"; then
+  HAS_atmega48pb_TRUE=
+  HAS_atmega48pb_FALSE='#'
+else
+  HAS_atmega48pb_TRUE='#'
+  HAS_atmega48pb_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega48p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48p" >&5
+$as_echo_n "checking if ${CC} has support for atmega48p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega48p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega48p" = "xyes"; then
+  HAS_atmega48p_TRUE=
+  HAS_atmega48p_FALSE='#'
+else
+  HAS_atmega48p_TRUE='#'
+  HAS_atmega48p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega88"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88" >&5
+$as_echo_n "checking if ${CC} has support for atmega88... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega88=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega88" = "xyes"; then
+  HAS_atmega88_TRUE=
+  HAS_atmega88_FALSE='#'
+else
+  HAS_atmega88_TRUE='#'
+  HAS_atmega88_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega88a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88a" >&5
+$as_echo_n "checking if ${CC} has support for atmega88a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega88a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega88a" = "xyes"; then
+  HAS_atmega88a_TRUE=
+  HAS_atmega88a_FALSE='#'
+else
+  HAS_atmega88a_TRUE='#'
+  HAS_atmega88a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega88p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88p" >&5
+$as_echo_n "checking if ${CC} has support for atmega88p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega88p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega88p" = "xyes"; then
+  HAS_atmega88p_TRUE=
+  HAS_atmega88p_FALSE='#'
+else
+  HAS_atmega88p_TRUE='#'
+  HAS_atmega88p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega88pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega88pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega88pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega88pa" = "xyes"; then
+  HAS_atmega88pa_TRUE=
+  HAS_atmega88pa_FALSE='#'
+else
+  HAS_atmega88pa_TRUE='#'
+  HAS_atmega88pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega88pb"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88pb" >&5
+$as_echo_n "checking if ${CC} has support for atmega88pb... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega88pb=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega88pb" = "xyes"; then
+  HAS_atmega88pb_TRUE=
+  HAS_atmega88pb_FALSE='#'
+else
+  HAS_atmega88pb_TRUE='#'
+  HAS_atmega88pb_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega8hva"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega8hva" >&5
+$as_echo_n "checking if ${CC} has support for atmega8hva... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega8hva=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega8hva" = "xyes"; then
+  HAS_atmega8hva_TRUE=
+  HAS_atmega8hva_FALSE='#'
+else
+  HAS_atmega8hva_TRUE='#'
+  HAS_atmega8hva_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90pwm1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm1" >&5
+$as_echo_n "checking if ${CC} has support for at90pwm1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90pwm1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90pwm1" = "xyes"; then
+  HAS_at90pwm1_TRUE=
+  HAS_at90pwm1_FALSE='#'
+else
+  HAS_at90pwm1_TRUE='#'
+  HAS_at90pwm1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90pwm2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm2" >&5
+$as_echo_n "checking if ${CC} has support for at90pwm2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90pwm2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90pwm2" = "xyes"; then
+  HAS_at90pwm2_TRUE=
+  HAS_at90pwm2_FALSE='#'
+else
+  HAS_at90pwm2_TRUE='#'
+  HAS_at90pwm2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90pwm2b"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm2b" >&5
+$as_echo_n "checking if ${CC} has support for at90pwm2b... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90pwm2b=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90pwm2b" = "xyes"; then
+  HAS_at90pwm2b_TRUE=
+  HAS_at90pwm2b_FALSE='#'
+else
+  HAS_at90pwm2b_TRUE='#'
+  HAS_at90pwm2b_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90pwm3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm3" >&5
+$as_echo_n "checking if ${CC} has support for at90pwm3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90pwm3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90pwm3" = "xyes"; then
+  HAS_at90pwm3_TRUE=
+  HAS_at90pwm3_FALSE='#'
+else
+  HAS_at90pwm3_TRUE='#'
+  HAS_at90pwm3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90pwm3b"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm3b" >&5
+$as_echo_n "checking if ${CC} has support for at90pwm3b... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90pwm3b=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90pwm3b" = "xyes"; then
+  HAS_at90pwm3b_TRUE=
+  HAS_at90pwm3b_FALSE='#'
+else
+  HAS_at90pwm3b_TRUE='#'
+  HAS_at90pwm3b_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90pwm81"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm81" >&5
+$as_echo_n "checking if ${CC} has support for at90pwm81... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90pwm81=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90pwm81" = "xyes"; then
+  HAS_at90pwm81_TRUE=
+  HAS_at90pwm81_FALSE='#'
+else
+  HAS_at90pwm81_TRUE='#'
+  HAS_at90pwm81_FALSE=
+fi
+
+
+
+# avr5
+ if true; then
+  HAS_avr5_TRUE=
+  HAS_avr5_FALSE='#'
+else
+  HAS_avr5_TRUE='#'
+  HAS_avr5_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90can32"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90can32" >&5
+$as_echo_n "checking if ${CC} has support for at90can32... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90can32=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90can32" = "xyes"; then
+  HAS_at90can32_TRUE=
+  HAS_at90can32_FALSE='#'
+else
+  HAS_at90can32_TRUE='#'
+  HAS_at90can32_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90can64"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90can64" >&5
+$as_echo_n "checking if ${CC} has support for at90can64... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90can64=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90can64" = "xyes"; then
+  HAS_at90can64_TRUE=
+  HAS_at90can64_FALSE='#'
+else
+  HAS_at90can64_TRUE='#'
+  HAS_at90can64_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90scr100"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90scr100" >&5
+$as_echo_n "checking if ${CC} has support for at90scr100... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90scr100=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90scr100" = "xyes"; then
+  HAS_at90scr100_TRUE=
+  HAS_at90scr100_FALSE='#'
+else
+  HAS_at90scr100_TRUE='#'
+  HAS_at90scr100_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90usb646"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb646" >&5
+$as_echo_n "checking if ${CC} has support for at90usb646... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90usb646=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90usb646" = "xyes"; then
+  HAS_at90usb646_TRUE=
+  HAS_at90usb646_FALSE='#'
+else
+  HAS_at90usb646_TRUE='#'
+  HAS_at90usb646_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90usb647"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb647" >&5
+$as_echo_n "checking if ${CC} has support for at90usb647... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90usb647=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90usb647" = "xyes"; then
+  HAS_at90usb647_TRUE=
+  HAS_at90usb647_FALSE='#'
+else
+  HAS_at90usb647_TRUE='#'
+  HAS_at90usb647_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90pwm316"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm316" >&5
+$as_echo_n "checking if ${CC} has support for at90pwm316... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90pwm316=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90pwm316" = "xyes"; then
+  HAS_at90pwm316_TRUE=
+  HAS_at90pwm316_FALSE='#'
+else
+  HAS_at90pwm316_TRUE='#'
+  HAS_at90pwm316_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90pwm216"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm216" >&5
+$as_echo_n "checking if ${CC} has support for at90pwm216... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90pwm216=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90pwm216" = "xyes"; then
+  HAS_at90pwm216_TRUE=
+  HAS_at90pwm216_FALSE='#'
+else
+  HAS_at90pwm216_TRUE='#'
+  HAS_at90pwm216_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90pwm161"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm161" >&5
+$as_echo_n "checking if ${CC} has support for at90pwm161... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90pwm161=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90pwm161" = "xyes"; then
+  HAS_at90pwm161_TRUE=
+  HAS_at90pwm161_FALSE='#'
+else
+  HAS_at90pwm161_TRUE='#'
+  HAS_at90pwm161_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at94k"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at94k" >&5
+$as_echo_n "checking if ${CC} has support for at94k... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at94k=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at94k" = "xyes"; then
+  HAS_at94k_TRUE=
+  HAS_at94k_FALSE='#'
+else
+  HAS_at94k_TRUE='#'
+  HAS_at94k_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata5702m322"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5702m322" >&5
+$as_echo_n "checking if ${CC} has support for ata5702m322... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata5702m322=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata5702m322" = "xyes"; then
+  HAS_ata5702m322_TRUE=
+  HAS_ata5702m322_FALSE='#'
+else
+  HAS_ata5702m322_TRUE='#'
+  HAS_ata5702m322_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata5782"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5782" >&5
+$as_echo_n "checking if ${CC} has support for ata5782... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata5782=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata5782" = "xyes"; then
+  HAS_ata5782_TRUE=
+  HAS_ata5782_FALSE='#'
+else
+  HAS_ata5782_TRUE='#'
+  HAS_ata5782_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata5790"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5790" >&5
+$as_echo_n "checking if ${CC} has support for ata5790... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata5790=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata5790" = "xyes"; then
+  HAS_ata5790_TRUE=
+  HAS_ata5790_FALSE='#'
+else
+  HAS_ata5790_TRUE='#'
+  HAS_ata5790_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata5790n"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5790n" >&5
+$as_echo_n "checking if ${CC} has support for ata5790n... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata5790n=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata5790n" = "xyes"; then
+  HAS_ata5790n_TRUE=
+  HAS_ata5790n_FALSE='#'
+else
+  HAS_ata5790n_TRUE='#'
+  HAS_ata5790n_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata5791"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5791" >&5
+$as_echo_n "checking if ${CC} has support for ata5791... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata5791=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata5791" = "xyes"; then
+  HAS_ata5791_TRUE=
+  HAS_ata5791_FALSE='#'
+else
+  HAS_ata5791_TRUE='#'
+  HAS_ata5791_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata5795"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5795" >&5
+$as_echo_n "checking if ${CC} has support for ata5795... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata5795=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata5795" = "xyes"; then
+  HAS_ata5795_TRUE=
+  HAS_ata5795_FALSE='#'
+else
+  HAS_ata5795_TRUE='#'
+  HAS_ata5795_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata5831"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5831" >&5
+$as_echo_n "checking if ${CC} has support for ata5831... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata5831=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata5831" = "xyes"; then
+  HAS_ata5831_TRUE=
+  HAS_ata5831_FALSE='#'
+else
+  HAS_ata5831_TRUE='#'
+  HAS_ata5831_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata6613c"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6613c" >&5
+$as_echo_n "checking if ${CC} has support for ata6613c... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata6613c=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata6613c" = "xyes"; then
+  HAS_ata6613c_TRUE=
+  HAS_ata6613c_FALSE='#'
+else
+  HAS_ata6613c_TRUE='#'
+  HAS_ata6613c_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata6614q"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6614q" >&5
+$as_echo_n "checking if ${CC} has support for ata6614q... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata6614q=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata6614q" = "xyes"; then
+  HAS_ata6614q_TRUE=
+  HAS_ata6614q_FALSE='#'
+else
+  HAS_ata6614q_TRUE='#'
+  HAS_ata6614q_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata8210"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata8210" >&5
+$as_echo_n "checking if ${CC} has support for ata8210... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata8210=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata8210" = "xyes"; then
+  HAS_ata8210_TRUE=
+  HAS_ata8210_FALSE='#'
+else
+  HAS_ata8210_TRUE='#'
+  HAS_ata8210_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=ata8510"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata8510" >&5
+$as_echo_n "checking if ${CC} has support for ata8510... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_ata8510=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_ata8510" = "xyes"; then
+  HAS_ata8510_TRUE=
+  HAS_ata8510_FALSE='#'
+else
+  HAS_ata8510_TRUE='#'
+  HAS_ata8510_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega16"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16" >&5
+$as_echo_n "checking if ${CC} has support for atmega16... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega16=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega16" = "xyes"; then
+  HAS_atmega16_TRUE=
+  HAS_atmega16_FALSE='#'
+else
+  HAS_atmega16_TRUE='#'
+  HAS_atmega16_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega16a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16a" >&5
+$as_echo_n "checking if ${CC} has support for atmega16a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega16a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega16a" = "xyes"; then
+  HAS_atmega16a_TRUE=
+  HAS_atmega16a_FALSE='#'
+else
+  HAS_atmega16a_TRUE='#'
+  HAS_atmega16a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega161"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega161" >&5
+$as_echo_n "checking if ${CC} has support for atmega161... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega161=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega161" = "xyes"; then
+  HAS_atmega161_TRUE=
+  HAS_atmega161_FALSE='#'
+else
+  HAS_atmega161_TRUE='#'
+  HAS_atmega161_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega162"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega162" >&5
+$as_echo_n "checking if ${CC} has support for atmega162... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega162=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega162" = "xyes"; then
+  HAS_atmega162_TRUE=
+  HAS_atmega162_FALSE='#'
+else
+  HAS_atmega162_TRUE='#'
+  HAS_atmega162_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega163"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega163" >&5
+$as_echo_n "checking if ${CC} has support for atmega163... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega163=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega163" = "xyes"; then
+  HAS_atmega163_TRUE=
+  HAS_atmega163_FALSE='#'
+else
+  HAS_atmega163_TRUE='#'
+  HAS_atmega163_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega164a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega164a" >&5
+$as_echo_n "checking if ${CC} has support for atmega164a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega164a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega164a" = "xyes"; then
+  HAS_atmega164a_TRUE=
+  HAS_atmega164a_FALSE='#'
+else
+  HAS_atmega164a_TRUE='#'
+  HAS_atmega164a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega164p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega164p" >&5
+$as_echo_n "checking if ${CC} has support for atmega164p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega164p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega164p" = "xyes"; then
+  HAS_atmega164p_TRUE=
+  HAS_atmega164p_FALSE='#'
+else
+  HAS_atmega164p_TRUE='#'
+  HAS_atmega164p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega164pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega164pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega164pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega164pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega164pa" = "xyes"; then
+  HAS_atmega164pa_TRUE=
+  HAS_atmega164pa_FALSE='#'
+else
+  HAS_atmega164pa_TRUE='#'
+  HAS_atmega164pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega165"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165" >&5
+$as_echo_n "checking if ${CC} has support for atmega165... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega165=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega165" = "xyes"; then
+  HAS_atmega165_TRUE=
+  HAS_atmega165_FALSE='#'
+else
+  HAS_atmega165_TRUE='#'
+  HAS_atmega165_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega165a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165a" >&5
+$as_echo_n "checking if ${CC} has support for atmega165a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega165a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega165a" = "xyes"; then
+  HAS_atmega165a_TRUE=
+  HAS_atmega165a_FALSE='#'
+else
+  HAS_atmega165a_TRUE='#'
+  HAS_atmega165a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega165p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165p" >&5
+$as_echo_n "checking if ${CC} has support for atmega165p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega165p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega165p" = "xyes"; then
+  HAS_atmega165p_TRUE=
+  HAS_atmega165p_FALSE='#'
+else
+  HAS_atmega165p_TRUE='#'
+  HAS_atmega165p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega165pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega165pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega165pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega165pa" = "xyes"; then
+  HAS_atmega165pa_TRUE=
+  HAS_atmega165pa_FALSE='#'
+else
+  HAS_atmega165pa_TRUE='#'
+  HAS_atmega165pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega168"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168" >&5
+$as_echo_n "checking if ${CC} has support for atmega168... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega168=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega168" = "xyes"; then
+  HAS_atmega168_TRUE=
+  HAS_atmega168_FALSE='#'
+else
+  HAS_atmega168_TRUE='#'
+  HAS_atmega168_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega168a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168a" >&5
+$as_echo_n "checking if ${CC} has support for atmega168a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega168a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega168a" = "xyes"; then
+  HAS_atmega168a_TRUE=
+  HAS_atmega168a_FALSE='#'
+else
+  HAS_atmega168a_TRUE='#'
+  HAS_atmega168a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega168p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168p" >&5
+$as_echo_n "checking if ${CC} has support for atmega168p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega168p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega168p" = "xyes"; then
+  HAS_atmega168p_TRUE=
+  HAS_atmega168p_FALSE='#'
+else
+  HAS_atmega168p_TRUE='#'
+  HAS_atmega168p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega168pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega168pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega168pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega168pa" = "xyes"; then
+  HAS_atmega168pa_TRUE=
+  HAS_atmega168pa_FALSE='#'
+else
+  HAS_atmega168pa_TRUE='#'
+  HAS_atmega168pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega168pb"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168pb" >&5
+$as_echo_n "checking if ${CC} has support for atmega168pb... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega168pb=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega168pb" = "xyes"; then
+  HAS_atmega168pb_TRUE=
+  HAS_atmega168pb_FALSE='#'
+else
+  HAS_atmega168pb_TRUE='#'
+  HAS_atmega168pb_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega169"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169" >&5
+$as_echo_n "checking if ${CC} has support for atmega169... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega169=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega169" = "xyes"; then
+  HAS_atmega169_TRUE=
+  HAS_atmega169_FALSE='#'
+else
+  HAS_atmega169_TRUE='#'
+  HAS_atmega169_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega169a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169a" >&5
+$as_echo_n "checking if ${CC} has support for atmega169a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega169a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega169a" = "xyes"; then
+  HAS_atmega169a_TRUE=
+  HAS_atmega169a_FALSE='#'
+else
+  HAS_atmega169a_TRUE='#'
+  HAS_atmega169a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega169p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169p" >&5
+$as_echo_n "checking if ${CC} has support for atmega169p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega169p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega169p" = "xyes"; then
+  HAS_atmega169p_TRUE=
+  HAS_atmega169p_FALSE='#'
+else
+  HAS_atmega169p_TRUE='#'
+  HAS_atmega169p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega169pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega169pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega169pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega169pa" = "xyes"; then
+  HAS_atmega169pa_TRUE=
+  HAS_atmega169pa_FALSE='#'
+else
+  HAS_atmega169pa_TRUE='#'
+  HAS_atmega169pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega16hva"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hva" >&5
+$as_echo_n "checking if ${CC} has support for atmega16hva... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega16hva=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega16hva" = "xyes"; then
+  HAS_atmega16hva_TRUE=
+  HAS_atmega16hva_FALSE='#'
+else
+  HAS_atmega16hva_TRUE='#'
+  HAS_atmega16hva_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega16hva2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hva2" >&5
+$as_echo_n "checking if ${CC} has support for atmega16hva2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega16hva2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega16hva2" = "xyes"; then
+  HAS_atmega16hva2_TRUE=
+  HAS_atmega16hva2_FALSE='#'
+else
+  HAS_atmega16hva2_TRUE='#'
+  HAS_atmega16hva2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega16hvb"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hvb" >&5
+$as_echo_n "checking if ${CC} has support for atmega16hvb... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega16hvb=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega16hvb" = "xyes"; then
+  HAS_atmega16hvb_TRUE=
+  HAS_atmega16hvb_FALSE='#'
+else
+  HAS_atmega16hvb_TRUE='#'
+  HAS_atmega16hvb_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega16hvbrevb"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hvbrevb" >&5
+$as_echo_n "checking if ${CC} has support for atmega16hvbrevb... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega16hvbrevb=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega16hvbrevb" = "xyes"; then
+  HAS_atmega16hvbrevb_TRUE=
+  HAS_atmega16hvbrevb_FALSE='#'
+else
+  HAS_atmega16hvbrevb_TRUE='#'
+  HAS_atmega16hvbrevb_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega16m1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16m1" >&5
+$as_echo_n "checking if ${CC} has support for atmega16m1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega16m1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega16m1" = "xyes"; then
+  HAS_atmega16m1_TRUE=
+  HAS_atmega16m1_FALSE='#'
+else
+  HAS_atmega16m1_TRUE='#'
+  HAS_atmega16m1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega16u4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16u4" >&5
+$as_echo_n "checking if ${CC} has support for atmega16u4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega16u4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega16u4" = "xyes"; then
+  HAS_atmega16u4_TRUE=
+  HAS_atmega16u4_FALSE='#'
+else
+  HAS_atmega16u4_TRUE='#'
+  HAS_atmega16u4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega32"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32" >&5
+$as_echo_n "checking if ${CC} has support for atmega32... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega32=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega32" = "xyes"; then
+  HAS_atmega32_TRUE=
+  HAS_atmega32_FALSE='#'
+else
+  HAS_atmega32_TRUE='#'
+  HAS_atmega32_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega32a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32a" >&5
+$as_echo_n "checking if ${CC} has support for atmega32a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega32a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega32a" = "xyes"; then
+  HAS_atmega32a_TRUE=
+  HAS_atmega32a_FALSE='#'
+else
+  HAS_atmega32a_TRUE='#'
+  HAS_atmega32a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega323"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega323" >&5
+$as_echo_n "checking if ${CC} has support for atmega323... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega323=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega323" = "xyes"; then
+  HAS_atmega323_TRUE=
+  HAS_atmega323_FALSE='#'
+else
+  HAS_atmega323_TRUE='#'
+  HAS_atmega323_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega324a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega324a" >&5
+$as_echo_n "checking if ${CC} has support for atmega324a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega324a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega324a" = "xyes"; then
+  HAS_atmega324a_TRUE=
+  HAS_atmega324a_FALSE='#'
+else
+  HAS_atmega324a_TRUE='#'
+  HAS_atmega324a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega324p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega324p" >&5
+$as_echo_n "checking if ${CC} has support for atmega324p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega324p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega324p" = "xyes"; then
+  HAS_atmega324p_TRUE=
+  HAS_atmega324p_FALSE='#'
+else
+  HAS_atmega324p_TRUE='#'
+  HAS_atmega324p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega324pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega324pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega324pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega324pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega324pa" = "xyes"; then
+  HAS_atmega324pa_TRUE=
+  HAS_atmega324pa_FALSE='#'
+else
+  HAS_atmega324pa_TRUE='#'
+  HAS_atmega324pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega325"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325" >&5
+$as_echo_n "checking if ${CC} has support for atmega325... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega325=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega325" = "xyes"; then
+  HAS_atmega325_TRUE=
+  HAS_atmega325_FALSE='#'
+else
+  HAS_atmega325_TRUE='#'
+  HAS_atmega325_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega325a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325a" >&5
+$as_echo_n "checking if ${CC} has support for atmega325a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega325a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega325a" = "xyes"; then
+  HAS_atmega325a_TRUE=
+  HAS_atmega325a_FALSE='#'
+else
+  HAS_atmega325a_TRUE='#'
+  HAS_atmega325a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega325p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325p" >&5
+$as_echo_n "checking if ${CC} has support for atmega325p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega325p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega325p" = "xyes"; then
+  HAS_atmega325p_TRUE=
+  HAS_atmega325p_FALSE='#'
+else
+  HAS_atmega325p_TRUE='#'
+  HAS_atmega325p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega325pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega325pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega325pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega325pa" = "xyes"; then
+  HAS_atmega325pa_TRUE=
+  HAS_atmega325pa_FALSE='#'
+else
+  HAS_atmega325pa_TRUE='#'
+  HAS_atmega325pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega3250"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250" >&5
+$as_echo_n "checking if ${CC} has support for atmega3250... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega3250=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega3250" = "xyes"; then
+  HAS_atmega3250_TRUE=
+  HAS_atmega3250_FALSE='#'
+else
+  HAS_atmega3250_TRUE='#'
+  HAS_atmega3250_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega3250a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250a" >&5
+$as_echo_n "checking if ${CC} has support for atmega3250a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega3250a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega3250a" = "xyes"; then
+  HAS_atmega3250a_TRUE=
+  HAS_atmega3250a_FALSE='#'
+else
+  HAS_atmega3250a_TRUE='#'
+  HAS_atmega3250a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega3250p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250p" >&5
+$as_echo_n "checking if ${CC} has support for atmega3250p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega3250p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega3250p" = "xyes"; then
+  HAS_atmega3250p_TRUE=
+  HAS_atmega3250p_FALSE='#'
+else
+  HAS_atmega3250p_TRUE='#'
+  HAS_atmega3250p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega3250pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega3250pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega3250pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega3250pa" = "xyes"; then
+  HAS_atmega3250pa_TRUE=
+  HAS_atmega3250pa_FALSE='#'
+else
+  HAS_atmega3250pa_TRUE='#'
+  HAS_atmega3250pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega328"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega328" >&5
+$as_echo_n "checking if ${CC} has support for atmega328... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega328=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega328" = "xyes"; then
+  HAS_atmega328_TRUE=
+  HAS_atmega328_FALSE='#'
+else
+  HAS_atmega328_TRUE='#'
+  HAS_atmega328_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega328p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega328p" >&5
+$as_echo_n "checking if ${CC} has support for atmega328p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega328p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega328p" = "xyes"; then
+  HAS_atmega328p_TRUE=
+  HAS_atmega328p_FALSE='#'
+else
+  HAS_atmega328p_TRUE='#'
+  HAS_atmega328p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega329"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329" >&5
+$as_echo_n "checking if ${CC} has support for atmega329... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega329=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega329" = "xyes"; then
+  HAS_atmega329_TRUE=
+  HAS_atmega329_FALSE='#'
+else
+  HAS_atmega329_TRUE='#'
+  HAS_atmega329_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega329a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329a" >&5
+$as_echo_n "checking if ${CC} has support for atmega329a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega329a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega329a" = "xyes"; then
+  HAS_atmega329a_TRUE=
+  HAS_atmega329a_FALSE='#'
+else
+  HAS_atmega329a_TRUE='#'
+  HAS_atmega329a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega329p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329p" >&5
+$as_echo_n "checking if ${CC} has support for atmega329p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega329p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega329p" = "xyes"; then
+  HAS_atmega329p_TRUE=
+  HAS_atmega329p_FALSE='#'
+else
+  HAS_atmega329p_TRUE='#'
+  HAS_atmega329p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega329pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega329pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega329pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega329pa" = "xyes"; then
+  HAS_atmega329pa_TRUE=
+  HAS_atmega329pa_FALSE='#'
+else
+  HAS_atmega329pa_TRUE='#'
+  HAS_atmega329pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega3290"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290" >&5
+$as_echo_n "checking if ${CC} has support for atmega3290... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega3290=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega3290" = "xyes"; then
+  HAS_atmega3290_TRUE=
+  HAS_atmega3290_FALSE='#'
+else
+  HAS_atmega3290_TRUE='#'
+  HAS_atmega3290_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega3290a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290a" >&5
+$as_echo_n "checking if ${CC} has support for atmega3290a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega3290a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega3290a" = "xyes"; then
+  HAS_atmega3290a_TRUE=
+  HAS_atmega3290a_FALSE='#'
+else
+  HAS_atmega3290a_TRUE='#'
+  HAS_atmega3290a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega3290p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290p" >&5
+$as_echo_n "checking if ${CC} has support for atmega3290p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega3290p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega3290p" = "xyes"; then
+  HAS_atmega3290p_TRUE=
+  HAS_atmega3290p_FALSE='#'
+else
+  HAS_atmega3290p_TRUE='#'
+  HAS_atmega3290p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega3290pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega3290pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega3290pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega3290pa" = "xyes"; then
+  HAS_atmega3290pa_TRUE=
+  HAS_atmega3290pa_FALSE='#'
+else
+  HAS_atmega3290pa_TRUE='#'
+  HAS_atmega3290pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega32c1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32c1" >&5
+$as_echo_n "checking if ${CC} has support for atmega32c1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega32c1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega32c1" = "xyes"; then
+  HAS_atmega32c1_TRUE=
+  HAS_atmega32c1_FALSE='#'
+else
+  HAS_atmega32c1_TRUE='#'
+  HAS_atmega32c1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega32hvb"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32hvb" >&5
+$as_echo_n "checking if ${CC} has support for atmega32hvb... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega32hvb=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega32hvb" = "xyes"; then
+  HAS_atmega32hvb_TRUE=
+  HAS_atmega32hvb_FALSE='#'
+else
+  HAS_atmega32hvb_TRUE='#'
+  HAS_atmega32hvb_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega32hvbrevb"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32hvbrevb" >&5
+$as_echo_n "checking if ${CC} has support for atmega32hvbrevb... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega32hvbrevb=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega32hvbrevb" = "xyes"; then
+  HAS_atmega32hvbrevb_TRUE=
+  HAS_atmega32hvbrevb_FALSE='#'
+else
+  HAS_atmega32hvbrevb_TRUE='#'
+  HAS_atmega32hvbrevb_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega32m1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32m1" >&5
+$as_echo_n "checking if ${CC} has support for atmega32m1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega32m1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega32m1" = "xyes"; then
+  HAS_atmega32m1_TRUE=
+  HAS_atmega32m1_FALSE='#'
+else
+  HAS_atmega32m1_TRUE='#'
+  HAS_atmega32m1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega32u4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32u4" >&5
+$as_echo_n "checking if ${CC} has support for atmega32u4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega32u4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega32u4" = "xyes"; then
+  HAS_atmega32u4_TRUE=
+  HAS_atmega32u4_FALSE='#'
+else
+  HAS_atmega32u4_TRUE='#'
+  HAS_atmega32u4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega32u6"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32u6" >&5
+$as_echo_n "checking if ${CC} has support for atmega32u6... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega32u6=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega32u6" = "xyes"; then
+  HAS_atmega32u6_TRUE=
+  HAS_atmega32u6_FALSE='#'
+else
+  HAS_atmega32u6_TRUE='#'
+  HAS_atmega32u6_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega406"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega406" >&5
+$as_echo_n "checking if ${CC} has support for atmega406... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega406=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega406" = "xyes"; then
+  HAS_atmega406_TRUE=
+  HAS_atmega406_FALSE='#'
+else
+  HAS_atmega406_TRUE='#'
+  HAS_atmega406_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega644rfr2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644rfr2" >&5
+$as_echo_n "checking if ${CC} has support for atmega644rfr2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega644rfr2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega644rfr2" = "xyes"; then
+  HAS_atmega644rfr2_TRUE=
+  HAS_atmega644rfr2_FALSE='#'
+else
+  HAS_atmega644rfr2_TRUE='#'
+  HAS_atmega644rfr2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega64rfr2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64rfr2" >&5
+$as_echo_n "checking if ${CC} has support for atmega64rfr2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega64rfr2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega64rfr2" = "xyes"; then
+  HAS_atmega64rfr2_TRUE=
+  HAS_atmega64rfr2_FALSE='#'
+else
+  HAS_atmega64rfr2_TRUE='#'
+  HAS_atmega64rfr2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega64"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64" >&5
+$as_echo_n "checking if ${CC} has support for atmega64... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega64=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega64" = "xyes"; then
+  HAS_atmega64_TRUE=
+  HAS_atmega64_FALSE='#'
+else
+  HAS_atmega64_TRUE='#'
+  HAS_atmega64_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega64a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64a" >&5
+$as_echo_n "checking if ${CC} has support for atmega64a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega64a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega64a" = "xyes"; then
+  HAS_atmega64a_TRUE=
+  HAS_atmega64a_FALSE='#'
+else
+  HAS_atmega64a_TRUE='#'
+  HAS_atmega64a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega640"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega640" >&5
+$as_echo_n "checking if ${CC} has support for atmega640... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega640=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega640" = "xyes"; then
+  HAS_atmega640_TRUE=
+  HAS_atmega640_FALSE='#'
+else
+  HAS_atmega640_TRUE='#'
+  HAS_atmega640_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega644"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644" >&5
+$as_echo_n "checking if ${CC} has support for atmega644... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega644=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega644" = "xyes"; then
+  HAS_atmega644_TRUE=
+  HAS_atmega644_FALSE='#'
+else
+  HAS_atmega644_TRUE='#'
+  HAS_atmega644_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega644a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644a" >&5
+$as_echo_n "checking if ${CC} has support for atmega644a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega644a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega644a" = "xyes"; then
+  HAS_atmega644a_TRUE=
+  HAS_atmega644a_FALSE='#'
+else
+  HAS_atmega644a_TRUE='#'
+  HAS_atmega644a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega644p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644p" >&5
+$as_echo_n "checking if ${CC} has support for atmega644p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega644p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega644p" = "xyes"; then
+  HAS_atmega644p_TRUE=
+  HAS_atmega644p_FALSE='#'
+else
+  HAS_atmega644p_TRUE='#'
+  HAS_atmega644p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega644pa"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644pa" >&5
+$as_echo_n "checking if ${CC} has support for atmega644pa... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega644pa=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega644pa" = "xyes"; then
+  HAS_atmega644pa_TRUE=
+  HAS_atmega644pa_FALSE='#'
+else
+  HAS_atmega644pa_TRUE='#'
+  HAS_atmega644pa_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega645"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega645" >&5
+$as_echo_n "checking if ${CC} has support for atmega645... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega645=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega645" = "xyes"; then
+  HAS_atmega645_TRUE=
+  HAS_atmega645_FALSE='#'
+else
+  HAS_atmega645_TRUE='#'
+  HAS_atmega645_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega645a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega645a" >&5
+$as_echo_n "checking if ${CC} has support for atmega645a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega645a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega645a" = "xyes"; then
+  HAS_atmega645a_TRUE=
+  HAS_atmega645a_FALSE='#'
+else
+  HAS_atmega645a_TRUE='#'
+  HAS_atmega645a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega645p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega645p" >&5
+$as_echo_n "checking if ${CC} has support for atmega645p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega645p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega645p" = "xyes"; then
+  HAS_atmega645p_TRUE=
+  HAS_atmega645p_FALSE='#'
+else
+  HAS_atmega645p_TRUE='#'
+  HAS_atmega645p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega6450"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6450" >&5
+$as_echo_n "checking if ${CC} has support for atmega6450... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega6450=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega6450" = "xyes"; then
+  HAS_atmega6450_TRUE=
+  HAS_atmega6450_FALSE='#'
+else
+  HAS_atmega6450_TRUE='#'
+  HAS_atmega6450_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega6450a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6450a" >&5
+$as_echo_n "checking if ${CC} has support for atmega6450a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega6450a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega6450a" = "xyes"; then
+  HAS_atmega6450a_TRUE=
+  HAS_atmega6450a_FALSE='#'
+else
+  HAS_atmega6450a_TRUE='#'
+  HAS_atmega6450a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega6450p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6450p" >&5
+$as_echo_n "checking if ${CC} has support for atmega6450p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega6450p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega6450p" = "xyes"; then
+  HAS_atmega6450p_TRUE=
+  HAS_atmega6450p_FALSE='#'
+else
+  HAS_atmega6450p_TRUE='#'
+  HAS_atmega6450p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega649"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega649" >&5
+$as_echo_n "checking if ${CC} has support for atmega649... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega649=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega649" = "xyes"; then
+  HAS_atmega649_TRUE=
+  HAS_atmega649_FALSE='#'
+else
+  HAS_atmega649_TRUE='#'
+  HAS_atmega649_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega649a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega649a" >&5
+$as_echo_n "checking if ${CC} has support for atmega649a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega649a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega649a" = "xyes"; then
+  HAS_atmega649a_TRUE=
+  HAS_atmega649a_FALSE='#'
+else
+  HAS_atmega649a_TRUE='#'
+  HAS_atmega649a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega649p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega649p" >&5
+$as_echo_n "checking if ${CC} has support for atmega649p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega649p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega649p" = "xyes"; then
+  HAS_atmega649p_TRUE=
+  HAS_atmega649p_FALSE='#'
+else
+  HAS_atmega649p_TRUE='#'
+  HAS_atmega649p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega6490"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6490" >&5
+$as_echo_n "checking if ${CC} has support for atmega6490... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega6490=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega6490" = "xyes"; then
+  HAS_atmega6490_TRUE=
+  HAS_atmega6490_FALSE='#'
+else
+  HAS_atmega6490_TRUE='#'
+  HAS_atmega6490_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega6490a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6490a" >&5
+$as_echo_n "checking if ${CC} has support for atmega6490a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega6490a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega6490a" = "xyes"; then
+  HAS_atmega6490a_TRUE=
+  HAS_atmega6490a_FALSE='#'
+else
+  HAS_atmega6490a_TRUE='#'
+  HAS_atmega6490a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega6490p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6490p" >&5
+$as_echo_n "checking if ${CC} has support for atmega6490p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega6490p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega6490p" = "xyes"; then
+  HAS_atmega6490p_TRUE=
+  HAS_atmega6490p_FALSE='#'
+else
+  HAS_atmega6490p_TRUE='#'
+  HAS_atmega6490p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega64c1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64c1" >&5
+$as_echo_n "checking if ${CC} has support for atmega64c1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega64c1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega64c1" = "xyes"; then
+  HAS_atmega64c1_TRUE=
+  HAS_atmega64c1_FALSE='#'
+else
+  HAS_atmega64c1_TRUE='#'
+  HAS_atmega64c1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega64hve"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64hve" >&5
+$as_echo_n "checking if ${CC} has support for atmega64hve... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega64hve=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega64hve" = "xyes"; then
+  HAS_atmega64hve_TRUE=
+  HAS_atmega64hve_FALSE='#'
+else
+  HAS_atmega64hve_TRUE='#'
+  HAS_atmega64hve_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega64hve2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64hve2" >&5
+$as_echo_n "checking if ${CC} has support for atmega64hve2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega64hve2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega64hve2" = "xyes"; then
+  HAS_atmega64hve2_TRUE=
+  HAS_atmega64hve2_FALSE='#'
+else
+  HAS_atmega64hve2_TRUE='#'
+  HAS_atmega64hve2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega64m1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64m1" >&5
+$as_echo_n "checking if ${CC} has support for atmega64m1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega64m1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega64m1" = "xyes"; then
+  HAS_atmega64m1_TRUE=
+  HAS_atmega64m1_FALSE='#'
+else
+  HAS_atmega64m1_TRUE='#'
+  HAS_atmega64m1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega128rfa1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega128rfa1" >&5
+$as_echo_n "checking if ${CC} has support for atmega128rfa1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega128rfa1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega128rfa1" = "xyes"; then
+  HAS_atmega128rfa1_TRUE=
+  HAS_atmega128rfa1_FALSE='#'
+else
+  HAS_atmega128rfa1_TRUE='#'
+  HAS_atmega128rfa1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=m3000"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for m3000" >&5
+$as_echo_n "checking if ${CC} has support for m3000... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_m3000=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_m3000" = "xyes"; then
+  HAS_m3000_TRUE=
+  HAS_m3000_FALSE='#'
+else
+  HAS_m3000_TRUE='#'
+  HAS_m3000_FALSE=
+fi
+
+
+
+
+#avr51
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avr51"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr51" >&5
+$as_echo_n "checking if ${CC} has support for avr51... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avr51=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avr51" = "xyes"; then
+  HAS_avr51_TRUE=
+  HAS_avr51_FALSE='#'
+else
+  HAS_avr51_TRUE='#'
+  HAS_avr51_FALSE=
+fi
+
+
+ if true; then
+  HAS_atmega128_TRUE=
+  HAS_atmega128_FALSE='#'
+else
+  HAS_atmega128_TRUE='#'
+  HAS_atmega128_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega128a"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega128a" >&5
+$as_echo_n "checking if ${CC} has support for atmega128a... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega128a=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega128a" = "xyes"; then
+  HAS_atmega128a_TRUE=
+  HAS_atmega128a_FALSE='#'
+else
+  HAS_atmega128a_TRUE='#'
+  HAS_atmega128a_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega1280"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1280" >&5
+$as_echo_n "checking if ${CC} has support for atmega1280... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega1280=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega1280" = "xyes"; then
+  HAS_atmega1280_TRUE=
+  HAS_atmega1280_FALSE='#'
+else
+  HAS_atmega1280_TRUE='#'
+  HAS_atmega1280_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega1281"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1281" >&5
+$as_echo_n "checking if ${CC} has support for atmega1281... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega1281=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega1281" = "xyes"; then
+  HAS_atmega1281_TRUE=
+  HAS_atmega1281_FALSE='#'
+else
+  HAS_atmega1281_TRUE='#'
+  HAS_atmega1281_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega1284"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1284" >&5
+$as_echo_n "checking if ${CC} has support for atmega1284... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega1284=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega1284" = "xyes"; then
+  HAS_atmega1284_TRUE=
+  HAS_atmega1284_FALSE='#'
+else
+  HAS_atmega1284_TRUE='#'
+  HAS_atmega1284_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega1284p"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1284p" >&5
+$as_echo_n "checking if ${CC} has support for atmega1284p... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega1284p=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega1284p" = "xyes"; then
+  HAS_atmega1284p_TRUE=
+  HAS_atmega1284p_FALSE='#'
+else
+  HAS_atmega1284p_TRUE='#'
+  HAS_atmega1284p_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90can128"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90can128" >&5
+$as_echo_n "checking if ${CC} has support for at90can128... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90can128=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90can128" = "xyes"; then
+  HAS_at90can128_TRUE=
+  HAS_at90can128_FALSE='#'
+else
+  HAS_at90can128_TRUE='#'
+  HAS_at90can128_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90usb1286"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb1286" >&5
+$as_echo_n "checking if ${CC} has support for at90usb1286... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90usb1286=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90usb1286" = "xyes"; then
+  HAS_at90usb1286_TRUE=
+  HAS_at90usb1286_FALSE='#'
+else
+  HAS_at90usb1286_TRUE='#'
+  HAS_at90usb1286_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=at90usb1287"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb1287" >&5
+$as_echo_n "checking if ${CC} has support for at90usb1287... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_at90usb1287=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_at90usb1287" = "xyes"; then
+  HAS_at90usb1287_TRUE=
+  HAS_at90usb1287_FALSE='#'
+else
+  HAS_at90usb1287_TRUE='#'
+  HAS_at90usb1287_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega1284rfr2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1284rfr2" >&5
+$as_echo_n "checking if ${CC} has support for atmega1284rfr2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega1284rfr2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega1284rfr2" = "xyes"; then
+  HAS_atmega1284rfr2_TRUE=
+  HAS_atmega1284rfr2_FALSE='#'
+else
+  HAS_atmega1284rfr2_TRUE='#'
+  HAS_atmega1284rfr2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega128rfr2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega128rfr2" >&5
+$as_echo_n "checking if ${CC} has support for atmega128rfr2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega128rfr2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega128rfr2" = "xyes"; then
+  HAS_atmega128rfr2_TRUE=
+  HAS_atmega128rfr2_FALSE='#'
+else
+  HAS_atmega128rfr2_TRUE='#'
+  HAS_atmega128rfr2_FALSE=
+fi
+
+
+
+# avr6
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avr6"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr6" >&5
+$as_echo_n "checking if ${CC} has support for avr6... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avr6=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avr6" = "xyes"; then
+  HAS_avr6_TRUE=
+  HAS_avr6_FALSE='#'
+else
+  HAS_avr6_TRUE='#'
+  HAS_avr6_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega2560"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega2560" >&5
+$as_echo_n "checking if ${CC} has support for atmega2560... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega2560=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega2560" = "xyes"; then
+  HAS_atmega2560_TRUE=
+  HAS_atmega2560_FALSE='#'
+else
+  HAS_atmega2560_TRUE='#'
+  HAS_atmega2560_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega2561"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega2561" >&5
+$as_echo_n "checking if ${CC} has support for atmega2561... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega2561=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega2561" = "xyes"; then
+  HAS_atmega2561_TRUE=
+  HAS_atmega2561_FALSE='#'
+else
+  HAS_atmega2561_TRUE='#'
+  HAS_atmega2561_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega2564rfr2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega2564rfr2" >&5
+$as_echo_n "checking if ${CC} has support for atmega2564rfr2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega2564rfr2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega2564rfr2" = "xyes"; then
+  HAS_atmega2564rfr2_TRUE=
+  HAS_atmega2564rfr2_FALSE='#'
+else
+  HAS_atmega2564rfr2_TRUE='#'
+  HAS_atmega2564rfr2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atmega256rfr2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega256rfr2" >&5
+$as_echo_n "checking if ${CC} has support for atmega256rfr2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atmega256rfr2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atmega256rfr2" = "xyes"; then
+  HAS_atmega256rfr2_TRUE=
+  HAS_atmega256rfr2_FALSE='#'
+else
+  HAS_atmega256rfr2_TRUE='#'
+  HAS_atmega256rfr2_FALSE=
+fi
+
+
+
+# avrxmega2
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avrxmega2"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega2" >&5
+$as_echo_n "checking if ${CC} has support for avrxmega2... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avrxmega2=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avrxmega2" = "xyes"; then
+  HAS_avrxmega2_TRUE=
+  HAS_avrxmega2_FALSE='#'
+else
+  HAS_avrxmega2_TRUE='#'
+  HAS_avrxmega2_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega8e5"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega8e5" >&5
+$as_echo_n "checking if ${CC} has support for atxmega8e5... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega8e5=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega8e5" = "xyes"; then
+  HAS_atxmega8e5_TRUE=
+  HAS_atxmega8e5_FALSE='#'
+else
+  HAS_atxmega8e5_TRUE='#'
+  HAS_atxmega8e5_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega16a4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16a4" >&5
+$as_echo_n "checking if ${CC} has support for atxmega16a4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega16a4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega16a4" = "xyes"; then
+  HAS_atxmega16a4_TRUE=
+  HAS_atxmega16a4_FALSE='#'
+else
+  HAS_atxmega16a4_TRUE='#'
+  HAS_atxmega16a4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega16a4u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16a4u" >&5
+$as_echo_n "checking if ${CC} has support for atxmega16a4u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega16a4u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega16a4u" = "xyes"; then
+  HAS_atxmega16a4u_TRUE=
+  HAS_atxmega16a4u_FALSE='#'
+else
+  HAS_atxmega16a4u_TRUE='#'
+  HAS_atxmega16a4u_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega16c4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16c4" >&5
+$as_echo_n "checking if ${CC} has support for atxmega16c4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega16c4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega16c4" = "xyes"; then
+  HAS_atxmega16c4_TRUE=
+  HAS_atxmega16c4_FALSE='#'
+else
+  HAS_atxmega16c4_TRUE='#'
+  HAS_atxmega16c4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega16d4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16d4" >&5
+$as_echo_n "checking if ${CC} has support for atxmega16d4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega16d4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega16d4" = "xyes"; then
+  HAS_atxmega16d4_TRUE=
+  HAS_atxmega16d4_FALSE='#'
+else
+  HAS_atxmega16d4_TRUE='#'
+  HAS_atxmega16d4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega32a4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32a4" >&5
+$as_echo_n "checking if ${CC} has support for atxmega32a4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega32a4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega32a4" = "xyes"; then
+  HAS_atxmega32a4_TRUE=
+  HAS_atxmega32a4_FALSE='#'
+else
+  HAS_atxmega32a4_TRUE='#'
+  HAS_atxmega32a4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega32a4u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32a4u" >&5
+$as_echo_n "checking if ${CC} has support for atxmega32a4u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega32a4u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega32a4u" = "xyes"; then
+  HAS_atxmega32a4u_TRUE=
+  HAS_atxmega32a4u_FALSE='#'
+else
+  HAS_atxmega32a4u_TRUE='#'
+  HAS_atxmega32a4u_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega32c3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32c3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega32c3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega32c3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega32c3" = "xyes"; then
+  HAS_atxmega32c3_TRUE=
+  HAS_atxmega32c3_FALSE='#'
+else
+  HAS_atxmega32c3_TRUE='#'
+  HAS_atxmega32c3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega32c4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32c4" >&5
+$as_echo_n "checking if ${CC} has support for atxmega32c4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega32c4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega32c4" = "xyes"; then
+  HAS_atxmega32c4_TRUE=
+  HAS_atxmega32c4_FALSE='#'
+else
+  HAS_atxmega32c4_TRUE='#'
+  HAS_atxmega32c4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega32d3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32d3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega32d3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega32d3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega32d3" = "xyes"; then
+  HAS_atxmega32d3_TRUE=
+  HAS_atxmega32d3_FALSE='#'
+else
+  HAS_atxmega32d3_TRUE='#'
+  HAS_atxmega32d3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega32d4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32d4" >&5
+$as_echo_n "checking if ${CC} has support for atxmega32d4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega32d4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega32d4" = "xyes"; then
+  HAS_atxmega32d4_TRUE=
+  HAS_atxmega32d4_FALSE='#'
+else
+  HAS_atxmega32d4_TRUE='#'
+  HAS_atxmega32d4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega16e5"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16e5" >&5
+$as_echo_n "checking if ${CC} has support for atxmega16e5... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega16e5=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega16e5" = "xyes"; then
+  HAS_atxmega16e5_TRUE=
+  HAS_atxmega16e5_FALSE='#'
+else
+  HAS_atxmega16e5_TRUE='#'
+  HAS_atxmega16e5_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega32e5"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32e5" >&5
+$as_echo_n "checking if ${CC} has support for atxmega32e5... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega32e5=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega32e5" = "xyes"; then
+  HAS_atxmega32e5_TRUE=
+  HAS_atxmega32e5_FALSE='#'
+else
+  HAS_atxmega32e5_TRUE='#'
+  HAS_atxmega32e5_FALSE=
+fi
+
+
+
+# avrxmega3
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avrxmega3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega3" >&5
+$as_echo_n "checking if ${CC} has support for avrxmega3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avrxmega3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avrxmega3" = "xyes"; then
+  HAS_avrxmega3_TRUE=
+  HAS_avrxmega3_FALSE='#'
+else
+  HAS_avrxmega3_TRUE='#'
+  HAS_avrxmega3_FALSE=
+fi
+
+
+
+# avrxmega4
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avrxmega4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega4" >&5
+$as_echo_n "checking if ${CC} has support for avrxmega4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avrxmega4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avrxmega4" = "xyes"; then
+  HAS_avrxmega4_TRUE=
+  HAS_avrxmega4_FALSE='#'
+else
+  HAS_avrxmega4_TRUE='#'
+  HAS_avrxmega4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega64a3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega64a3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega64a3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega64a3" = "xyes"; then
+  HAS_atxmega64a3_TRUE=
+  HAS_atxmega64a3_FALSE='#'
+else
+  HAS_atxmega64a3_TRUE='#'
+  HAS_atxmega64a3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega64a3u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a3u" >&5
+$as_echo_n "checking if ${CC} has support for atxmega64a3u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega64a3u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega64a3u" = "xyes"; then
+  HAS_atxmega64a3u_TRUE=
+  HAS_atxmega64a3u_FALSE='#'
+else
+  HAS_atxmega64a3u_TRUE='#'
+  HAS_atxmega64a3u_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega64a4u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a4u" >&5
+$as_echo_n "checking if ${CC} has support for atxmega64a4u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega64a4u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega64a4u" = "xyes"; then
+  HAS_atxmega64a4u_TRUE=
+  HAS_atxmega64a4u_FALSE='#'
+else
+  HAS_atxmega64a4u_TRUE='#'
+  HAS_atxmega64a4u_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega64b1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64b1" >&5
+$as_echo_n "checking if ${CC} has support for atxmega64b1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega64b1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega64b1" = "xyes"; then
+  HAS_atxmega64b1_TRUE=
+  HAS_atxmega64b1_FALSE='#'
+else
+  HAS_atxmega64b1_TRUE='#'
+  HAS_atxmega64b1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega64b3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64b3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega64b3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega64b3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega64b3" = "xyes"; then
+  HAS_atxmega64b3_TRUE=
+  HAS_atxmega64b3_FALSE='#'
+else
+  HAS_atxmega64b3_TRUE='#'
+  HAS_atxmega64b3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega64c3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64c3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega64c3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega64c3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega64c3" = "xyes"; then
+  HAS_atxmega64c3_TRUE=
+  HAS_atxmega64c3_FALSE='#'
+else
+  HAS_atxmega64c3_TRUE='#'
+  HAS_atxmega64c3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega64d3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64d3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega64d3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega64d3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega64d3" = "xyes"; then
+  HAS_atxmega64d3_TRUE=
+  HAS_atxmega64d3_FALSE='#'
+else
+  HAS_atxmega64d3_TRUE='#'
+  HAS_atxmega64d3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega64d4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64d4" >&5
+$as_echo_n "checking if ${CC} has support for atxmega64d4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega64d4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega64d4" = "xyes"; then
+  HAS_atxmega64d4_TRUE=
+  HAS_atxmega64d4_FALSE='#'
+else
+  HAS_atxmega64d4_TRUE='#'
+  HAS_atxmega64d4_FALSE=
+fi
+
+
+
+# avrxmega5
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avrxmega5"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega5" >&5
+$as_echo_n "checking if ${CC} has support for avrxmega5... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avrxmega5=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avrxmega5" = "xyes"; then
+  HAS_avrxmega5_TRUE=
+  HAS_avrxmega5_FALSE='#'
+else
+  HAS_avrxmega5_TRUE='#'
+  HAS_avrxmega5_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega64a1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a1" >&5
+$as_echo_n "checking if ${CC} has support for atxmega64a1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega64a1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega64a1" = "xyes"; then
+  HAS_atxmega64a1_TRUE=
+  HAS_atxmega64a1_FALSE='#'
+else
+  HAS_atxmega64a1_TRUE='#'
+  HAS_atxmega64a1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega64a1u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a1u" >&5
+$as_echo_n "checking if ${CC} has support for atxmega64a1u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega64a1u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega64a1u" = "xyes"; then
+  HAS_atxmega64a1u_TRUE=
+  HAS_atxmega64a1u_FALSE='#'
+else
+  HAS_atxmega64a1u_TRUE='#'
+  HAS_atxmega64a1u_FALSE=
+fi
+
+
+
+# avrxmega6
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avrxmega6"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega6" >&5
+$as_echo_n "checking if ${CC} has support for avrxmega6... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avrxmega6=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avrxmega6" = "xyes"; then
+  HAS_avrxmega6_TRUE=
+  HAS_avrxmega6_FALSE='#'
+else
+  HAS_avrxmega6_TRUE='#'
+  HAS_avrxmega6_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega128a3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega128a3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega128a3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega128a3" = "xyes"; then
+  HAS_atxmega128a3_TRUE=
+  HAS_atxmega128a3_FALSE='#'
+else
+  HAS_atxmega128a3_TRUE='#'
+  HAS_atxmega128a3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega128a3u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a3u" >&5
+$as_echo_n "checking if ${CC} has support for atxmega128a3u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega128a3u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega128a3u" = "xyes"; then
+  HAS_atxmega128a3u_TRUE=
+  HAS_atxmega128a3u_FALSE='#'
+else
+  HAS_atxmega128a3u_TRUE='#'
+  HAS_atxmega128a3u_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega128b1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128b1" >&5
+$as_echo_n "checking if ${CC} has support for atxmega128b1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega128b1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega128b1" = "xyes"; then
+  HAS_atxmega128b1_TRUE=
+  HAS_atxmega128b1_FALSE='#'
+else
+  HAS_atxmega128b1_TRUE='#'
+  HAS_atxmega128b1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega128b3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128b3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega128b3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega128b3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega128b3" = "xyes"; then
+  HAS_atxmega128b3_TRUE=
+  HAS_atxmega128b3_FALSE='#'
+else
+  HAS_atxmega128b3_TRUE='#'
+  HAS_atxmega128b3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega128c3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128c3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega128c3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega128c3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega128c3" = "xyes"; then
+  HAS_atxmega128c3_TRUE=
+  HAS_atxmega128c3_FALSE='#'
+else
+  HAS_atxmega128c3_TRUE='#'
+  HAS_atxmega128c3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega128d3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128d3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega128d3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega128d3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega128d3" = "xyes"; then
+  HAS_atxmega128d3_TRUE=
+  HAS_atxmega128d3_FALSE='#'
+else
+  HAS_atxmega128d3_TRUE='#'
+  HAS_atxmega128d3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega128d4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128d4" >&5
+$as_echo_n "checking if ${CC} has support for atxmega128d4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega128d4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega128d4" = "xyes"; then
+  HAS_atxmega128d4_TRUE=
+  HAS_atxmega128d4_FALSE='#'
+else
+  HAS_atxmega128d4_TRUE='#'
+  HAS_atxmega128d4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega192a3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega192a3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega192a3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega192a3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega192a3" = "xyes"; then
+  HAS_atxmega192a3_TRUE=
+  HAS_atxmega192a3_FALSE='#'
+else
+  HAS_atxmega192a3_TRUE='#'
+  HAS_atxmega192a3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega192a3u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega192a3u" >&5
+$as_echo_n "checking if ${CC} has support for atxmega192a3u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega192a3u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega192a3u" = "xyes"; then
+  HAS_atxmega192a3u_TRUE=
+  HAS_atxmega192a3u_FALSE='#'
+else
+  HAS_atxmega192a3u_TRUE='#'
+  HAS_atxmega192a3u_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega192c3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega192c3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega192c3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega192c3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega192c3" = "xyes"; then
+  HAS_atxmega192c3_TRUE=
+  HAS_atxmega192c3_FALSE='#'
+else
+  HAS_atxmega192c3_TRUE='#'
+  HAS_atxmega192c3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega192d3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega192d3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega192d3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega192d3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega192d3" = "xyes"; then
+  HAS_atxmega192d3_TRUE=
+  HAS_atxmega192d3_FALSE='#'
+else
+  HAS_atxmega192d3_TRUE='#'
+  HAS_atxmega192d3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega256a3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256a3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega256a3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega256a3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega256a3" = "xyes"; then
+  HAS_atxmega256a3_TRUE=
+  HAS_atxmega256a3_FALSE='#'
+else
+  HAS_atxmega256a3_TRUE='#'
+  HAS_atxmega256a3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega256a3u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256a3u" >&5
+$as_echo_n "checking if ${CC} has support for atxmega256a3u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega256a3u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega256a3u" = "xyes"; then
+  HAS_atxmega256a3u_TRUE=
+  HAS_atxmega256a3u_FALSE='#'
+else
+  HAS_atxmega256a3u_TRUE='#'
+  HAS_atxmega256a3u_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega256a3b"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256a3b" >&5
+$as_echo_n "checking if ${CC} has support for atxmega256a3b... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega256a3b=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega256a3b" = "xyes"; then
+  HAS_atxmega256a3b_TRUE=
+  HAS_atxmega256a3b_FALSE='#'
+else
+  HAS_atxmega256a3b_TRUE='#'
+  HAS_atxmega256a3b_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega256a3bu"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256a3bu" >&5
+$as_echo_n "checking if ${CC} has support for atxmega256a3bu... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega256a3bu=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega256a3bu" = "xyes"; then
+  HAS_atxmega256a3bu_TRUE=
+  HAS_atxmega256a3bu_FALSE='#'
+else
+  HAS_atxmega256a3bu_TRUE='#'
+  HAS_atxmega256a3bu_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega256c3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256c3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega256c3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega256c3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega256c3" = "xyes"; then
+  HAS_atxmega256c3_TRUE=
+  HAS_atxmega256c3_FALSE='#'
+else
+  HAS_atxmega256c3_TRUE='#'
+  HAS_atxmega256c3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega256d3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256d3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega256d3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega256d3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega256d3" = "xyes"; then
+  HAS_atxmega256d3_TRUE=
+  HAS_atxmega256d3_FALSE='#'
+else
+  HAS_atxmega256d3_TRUE='#'
+  HAS_atxmega256d3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega384c3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega384c3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega384c3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega384c3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega384c3" = "xyes"; then
+  HAS_atxmega384c3_TRUE=
+  HAS_atxmega384c3_FALSE='#'
+else
+  HAS_atxmega384c3_TRUE='#'
+  HAS_atxmega384c3_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega384d3"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega384d3" >&5
+$as_echo_n "checking if ${CC} has support for atxmega384d3... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega384d3=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega384d3" = "xyes"; then
+  HAS_atxmega384d3_TRUE=
+  HAS_atxmega384d3_FALSE='#'
+else
+  HAS_atxmega384d3_TRUE='#'
+  HAS_atxmega384d3_FALSE=
+fi
+
+
+# avrxmega7
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avrxmega7"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega7" >&5
+$as_echo_n "checking if ${CC} has support for avrxmega7... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avrxmega7=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avrxmega7" = "xyes"; then
+  HAS_avrxmega7_TRUE=
+  HAS_avrxmega7_FALSE='#'
+else
+  HAS_avrxmega7_TRUE='#'
+  HAS_avrxmega7_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega128a1"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a1" >&5
+$as_echo_n "checking if ${CC} has support for atxmega128a1... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega128a1=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega128a1" = "xyes"; then
+  HAS_atxmega128a1_TRUE=
+  HAS_atxmega128a1_FALSE='#'
+else
+  HAS_atxmega128a1_TRUE='#'
+  HAS_atxmega128a1_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega128a1u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a1u" >&5
+$as_echo_n "checking if ${CC} has support for atxmega128a1u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega128a1u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega128a1u" = "xyes"; then
+  HAS_atxmega128a1u_TRUE=
+  HAS_atxmega128a1u_FALSE='#'
+else
+  HAS_atxmega128a1u_TRUE='#'
+  HAS_atxmega128a1u_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=atxmega128a4u"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a4u" >&5
+$as_echo_n "checking if ${CC} has support for atxmega128a4u... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_atxmega128a4u=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_atxmega128a4u" = "xyes"; then
+  HAS_atxmega128a4u_TRUE=
+  HAS_atxmega128a4u_FALSE='#'
+else
+  HAS_atxmega128a4u_TRUE='#'
+  HAS_atxmega128a4u_FALSE=
+fi
+
+
+
+# avrtiny
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=avrtiny"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrtiny" >&5
+$as_echo_n "checking if ${CC} has support for avrtiny... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_avrtiny=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_avrtiny" = "xyes"; then
+  HAS_avrtiny_TRUE=
+  HAS_avrtiny_FALSE='#'
+else
+  HAS_avrtiny_TRUE='#'
+  HAS_avrtiny_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny4"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny4" >&5
+$as_echo_n "checking if ${CC} has support for attiny4... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny4=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny4" = "xyes"; then
+  HAS_attiny4_TRUE=
+  HAS_attiny4_FALSE='#'
+else
+  HAS_attiny4_TRUE='#'
+  HAS_attiny4_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny5"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny5" >&5
+$as_echo_n "checking if ${CC} has support for attiny5... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny5=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny5" = "xyes"; then
+  HAS_attiny5_TRUE=
+  HAS_attiny5_FALSE='#'
+else
+  HAS_attiny5_TRUE='#'
+  HAS_attiny5_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny9"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny9" >&5
+$as_echo_n "checking if ${CC} has support for attiny9... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny9=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny9" = "xyes"; then
+  HAS_attiny9_TRUE=
+  HAS_attiny9_FALSE='#'
+else
+  HAS_attiny9_TRUE='#'
+  HAS_attiny9_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny10"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny10" >&5
+$as_echo_n "checking if ${CC} has support for attiny10... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny10=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny10" = "xyes"; then
+  HAS_attiny10_TRUE=
+  HAS_attiny10_FALSE='#'
+else
+  HAS_attiny10_TRUE='#'
+  HAS_attiny10_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny20"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny20" >&5
+$as_echo_n "checking if ${CC} has support for attiny20... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny20=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny20" = "xyes"; then
+  HAS_attiny20_TRUE=
+  HAS_attiny20_FALSE='#'
+else
+  HAS_attiny20_TRUE='#'
+  HAS_attiny20_FALSE=
+fi
+
+
+
+    old_CC=${CC}
+    old_CFLAGS=${CFLAGS}
+    CFLAGS="-mmcu=attiny40"
+    CC=`echo "${CC}" | sed 's/-mmcu=avr.//'`
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny40" >&5
+$as_echo_n "checking if ${CC} has support for attiny40... " >&6; }
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  has_dev_support=yes
+else
+  has_dev_support=no
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+    if test "x$has_dev_support" = "xyes"
+    then
+      HAS_attiny40=yes
+    fi
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5
+$as_echo "$has_dev_support" >&6; }
+    CC=${old_CC}
+    CFLAGS=${old_CFLAGS}
+
+
+ if test "x$HAS_attiny40" = "xyes"; then
+  HAS_attiny40_TRUE=
+  HAS_attiny40_FALSE='#'
+else
+  HAS_attiny40_TRUE='#'
+  HAS_attiny40_FALSE=
+fi
+
+
+
+
+
+# Generate all files from *.in sources.
+
+ac_config_files="$ac_config_files Makefile avr-libc.spec avr/Makefile avr/lib/Makefile common/Makefile crt1/Makefile crt1/iosym/Makefile doc/Makefile doc/api/Makefile doc/examples/Makefile include/Makefile include/avr/Makefile include/avr/builtins.h include/compat/Makefile include/util/Makefile include/util/delay.h include/sys/Makefile libc/Makefile libc/misc/Makefile libc/pmstring/Makefile libc/stdio/Makefile libc/stdlib/Makefile libc/string/Makefile libc/time/Makefile libm/Makefile libm/fplib/Makefile scripts/Makefile devtools/Makefile"
+
+
+#avr1 and avr2
+ac_config_files="$ac_config_files avr/lib/avr2/Makefile avr/lib/avr2/at90s1200/Makefile avr/lib/avr2/at90s4414/Makefile avr/lib/avr2/at90s4434/Makefile avr/lib/avr2/at90s8515/Makefile avr/lib/avr2/at90c8534/Makefile avr/lib/avr2/at90s8535/Makefile avr/lib/avr2/attiny11/Makefile avr/lib/avr2/attiny12/Makefile avr/lib/avr2/attiny15/Makefile avr/lib/avr2/attiny28/Makefile"
+
+
+#avr2/tiny-stack
+ac_config_files="$ac_config_files avr/lib/avr2/tiny-stack/Makefile avr/lib/avr2/tiny-stack/at90s2313/Makefile avr/lib/avr2/tiny-stack/at90s2323/Makefile avr/lib/avr2/tiny-stack/at90s2333/Makefile avr/lib/avr2/tiny-stack/at90s2343/Makefile avr/lib/avr2/tiny-stack/attiny22/Makefile avr/lib/avr2/tiny-stack/attiny26/Makefile avr/lib/avr2/tiny-stack/at90s4433/Makefile"
+
+
+#avr25
+ac_config_files="$ac_config_files avr/lib/avr25/Makefile avr/lib/avr25/at86rf401/Makefile avr/lib/avr25/ata5272/Makefile avr/lib/avr25/ata6616c/Makefile avr/lib/avr25/attiny4313/Makefile avr/lib/avr25/attiny43u/Makefile avr/lib/avr25/attiny44/Makefile avr/lib/avr25/attiny44a/Makefile avr/lib/avr25/attiny441/Makefile avr/lib/avr25/attiny45/Makefile avr/lib/avr25/attiny461/Makefile avr/lib/avr25/attiny461a/Makefile avr/lib/avr25/attiny48/Makefile avr/lib/avr25/attiny828/Makefile avr/lib/avr25/attiny84/Makefile avr/lib/avr25/attiny84a/Makefile avr/lib/avr25/attiny841/Makefile avr/lib/avr25/attiny85/Makefile avr/lib/avr25/attiny861/Makefile avr/lib/avr25/attiny861a/Makefile avr/lib/avr25/attiny87/Makefile avr/lib/avr25/attiny88/Makefile"
+
+
+#avr25/tiny-stack
+ac_config_files="$ac_config_files avr/lib/avr25/tiny-stack/Makefile avr/lib/avr25/tiny-stack/attiny13/Makefile avr/lib/avr25/tiny-stack/attiny13a/Makefile avr/lib/avr25/tiny-stack/attiny2313/Makefile avr/lib/avr25/tiny-stack/attiny2313a/Makefile avr/lib/avr25/tiny-stack/attiny24/Makefile avr/lib/avr25/tiny-stack/attiny24a/Makefile avr/lib/avr25/tiny-stack/attiny25/Makefile avr/lib/avr25/tiny-stack/attiny261/Makefile avr/lib/avr25/tiny-stack/attiny261a/Makefile"
+
+
+#avr3
+ac_config_files="$ac_config_files avr/lib/avr3/Makefile avr/lib/avr3/at43usb355/Makefile avr/lib/avr3/at76c711/Makefile"
+
+
+#avr31
+ac_config_files="$ac_config_files avr/lib/avr31/Makefile avr/lib/avr31/atmega103/Makefile avr/lib/avr31/at43usb320/Makefile"
+
+
+#avr35
+ac_config_files="$ac_config_files avr/lib/avr35/Makefile avr/lib/avr35/at90usb82/Makefile avr/lib/avr35/at90usb162/Makefile avr/lib/avr35/ata5505/Makefile avr/lib/avr35/ata6617c/Makefile avr/lib/avr35/ata664251/Makefile avr/lib/avr35/atmega8u2/Makefile avr/lib/avr35/atmega16u2/Makefile avr/lib/avr35/atmega32u2/Makefile avr/lib/avr35/attiny167/Makefile avr/lib/avr35/attiny1634/Makefile"
+
+
+#avr4
+ac_config_files="$ac_config_files avr/lib/avr4/Makefile avr/lib/avr4/ata6285/Makefile avr/lib/avr4/ata6286/Makefile avr/lib/avr4/ata6289/Makefile avr/lib/avr4/ata6612c/Makefile avr/lib/avr4/atmega48/Makefile avr/lib/avr4/atmega48a/Makefile avr/lib/avr4/atmega48pa/Makefile avr/lib/avr4/atmega48pb/Makefile avr/lib/avr4/atmega48p/Makefile avr/lib/avr4/atmega8/Makefile avr/lib/avr4/atmega8a/Makefile avr/lib/avr4/atmega88/Makefile avr/lib/avr4/atmega88a/Makefile avr/lib/avr4/atmega88p/Makefile avr/lib/avr4/atmega88pa/Makefile avr/lib/avr4/atmega88pb/Makefile avr/lib/avr4/atmega8515/Makefile avr/lib/avr4/atmega8535/Makefile avr/lib/avr4/atmega8hva/Makefile avr/lib/avr4/at90pwm1/Makefile avr/lib/avr4/at90pwm2/Makefile avr/lib/avr4/at90pwm2b/Makefile avr/lib/avr4/at90pwm3/Makefile avr/lib/avr4/at90pwm3b/Makefile avr/lib/avr4/at90pwm81/Makefile"
+
+
+#avr5
+ac_config_files="$ac_config_files avr/lib/avr5/Makefile avr/lib/avr5/at90can32/Makefile avr/lib/avr5/at90can64/Makefile avr/lib/avr5/at90pwm216/Makefile avr/lib/avr5/at90pwm316/Makefile avr/lib/avr5/at90pwm161/Makefile avr/lib/avr5/at90scr100/Makefile avr/lib/avr5/at90usb646/Makefile avr/lib/avr5/at90usb647/Makefile avr/lib/avr5/at94k/Makefile avr/lib/avr5/ata5702m322/Makefile avr/lib/avr5/ata5782/Makefile avr/lib/avr5/ata5790/Makefile avr/lib/avr5/ata5790n/Makefile avr/lib/avr5/ata5791/Makefile avr/lib/avr5/ata5795/Makefile avr/lib/avr5/ata5831/Makefile avr/lib/avr5/ata6613c/Makefile avr/lib/avr5/ata6614q/Makefile avr/lib/avr5/ata8210/Makefile avr/lib/avr5/ata8510/Makefile avr/lib/avr5/atmega16/Makefile avr/lib/avr5/atmega16a/Makefile avr/lib/avr5/atmega161/Makefile avr/lib/avr5/atmega162/Makefile avr/lib/avr5/atmega163/Makefile avr/lib/avr5/atmega164a/Makefile avr/lib/avr5/atmega164p/Makefile avr/lib/avr5/atmega164pa/Makefile avr/lib/avr5/atmega165/Makefile avr/lib/avr5/atmega165a/Makefile avr/lib/avr5/atmega165p/Makefile avr/lib/avr5/atmega165pa/Makefile avr/lib/avr5/atmega168/Makefile avr/lib/avr5/atmega168a/Makefile avr/lib/avr5/atmega168p/Makefile avr/lib/avr5/atmega168pa/Makefile avr/lib/avr5/atmega168pb/Makefile avr/lib/avr5/atmega169/Makefile avr/lib/avr5/atmega169a/Makefile avr/lib/avr5/atmega169p/Makefile avr/lib/avr5/atmega169pa/Makefile avr/lib/avr5/atmega16hva/Makefile avr/lib/avr5/atmega16hva2/Makefile avr/lib/avr5/atmega16hvb/Makefile avr/lib/avr5/atmega16hvbrevb/Makefile avr/lib/avr5/atmega16m1/Makefile avr/lib/avr5/atmega16u4/Makefile avr/lib/avr5/atmega32/Makefile avr/lib/avr5/atmega32a/Makefile avr/lib/avr5/atmega323/Makefile avr/lib/avr5/atmega324a/Makefile avr/lib/avr5/atmega324p/Makefile avr/lib/avr5/atmega324pa/Makefile avr/lib/avr5/atmega325/Makefile avr/lib/avr5/atmega325a/Makefile avr/lib/avr5/atmega325p/Makefile avr/lib/avr5/atmega325pa/Makefile avr/lib/avr5/atmega3250/Makefile avr/lib/avr5/atmega3250a/Makefile avr/lib/avr5/atmega3250p/Makefile avr/lib/avr5/atmega3250pa/Makefile avr/lib/avr5/atmega328/Makefile avr/lib/avr5/atmega328p/Makefile avr/lib/avr5/atmega329/Makefile avr/lib/avr5/atmega329a/Makefile avr/lib/avr5/atmega329p/Makefile avr/lib/avr5/atmega329pa/Makefile avr/lib/avr5/atmega3290/Makefile avr/lib/avr5/atmega3290a/Makefile avr/lib/avr5/atmega3290p/Makefile avr/lib/avr5/atmega3290pa/Makefile avr/lib/avr5/atmega32c1/Makefile avr/lib/avr5/atmega32hvb/Makefile avr/lib/avr5/atmega32hvbrevb/Makefile avr/lib/avr5/atmega32m1/Makefile avr/lib/avr5/atmega32u4/Makefile avr/lib/avr5/atmega32u6/Makefile avr/lib/avr5/atmega406/Makefile avr/lib/avr5/atmega64rfr2/Makefile avr/lib/avr5/atmega644rfr2/Makefile avr/lib/avr5/atmega64/Makefile avr/lib/avr5/atmega64a/Makefile avr/lib/avr5/atmega640/Makefile avr/lib/avr5/atmega644/Makefile avr/lib/avr5/atmega644a/Makefile avr/lib/avr5/atmega644p/Makefile avr/lib/avr5/atmega644pa/Makefile avr/lib/avr5/atmega645/Makefile avr/lib/avr5/atmega645a/Makefile avr/lib/avr5/atmega645p/Makefile avr/lib/avr5/atmega6450/Makefile avr/lib/avr5/atmega6450a/Makefile avr/lib/avr5/atmega6450p/Makefile avr/lib/avr5/atmega649/Makefile avr/lib/avr5/atmega649a/Makefile avr/lib/avr5/atmega649p/Makefile avr/lib/avr5/atmega6490/Makefile avr/lib/avr5/atmega6490a/Makefile avr/lib/avr5/atmega6490p/Makefile avr/lib/avr5/atmega64c1/Makefile avr/lib/avr5/atmega64hve/Makefile avr/lib/avr5/atmega64hve2/Makefile avr/lib/avr5/atmega64m1/Makefile avr/lib/avr5/m3000/Makefile"
+
+
+#avr51
+ac_config_files="$ac_config_files avr/lib/avr51/Makefile avr/lib/avr51/atmega128/Makefile avr/lib/avr51/atmega128a/Makefile avr/lib/avr51/atmega1280/Makefile avr/lib/avr51/atmega1281/Makefile avr/lib/avr51/atmega1284/Makefile avr/lib/avr51/atmega1284p/Makefile avr/lib/avr51/atmega128rfa1/Makefile avr/lib/avr51/atmega128rfr2/Makefile avr/lib/avr51/atmega1284rfr2/Makefile avr/lib/avr51/at90can128/Makefile avr/lib/avr51/at90usb1286/Makefile avr/lib/avr51/at90usb1287/Makefile"
+
+
+#avr6
+ac_config_files="$ac_config_files avr/lib/avr6/Makefile avr/lib/avr6/atmega2560/Makefile avr/lib/avr6/atmega2561/Makefile avr/lib/avr6/atmega256rfr2/Makefile avr/lib/avr6/atmega2564rfr2/Makefile"
+
+
+# avrxmega2
+ac_config_files="$ac_config_files avr/lib/avrxmega2/Makefile avr/lib/avrxmega2/atxmega8e5/Makefile avr/lib/avrxmega2/atxmega16a4/Makefile avr/lib/avrxmega2/atxmega16a4u/Makefile avr/lib/avrxmega2/atxmega16c4/Makefile avr/lib/avrxmega2/atxmega16d4/Makefile avr/lib/avrxmega2/atxmega16e5/Makefile avr/lib/avrxmega2/atxmega32a4/Makefile avr/lib/avrxmega2/atxmega32a4u/Makefile avr/lib/avrxmega2/atxmega32c3/Makefile avr/lib/avrxmega2/atxmega32c4/Makefile avr/lib/avrxmega2/atxmega32d3/Makefile avr/lib/avrxmega2/atxmega32d4/Makefile avr/lib/avrxmega2/atxmega32e5/Makefile"
+
+
+# avrxmega3
+ac_config_files="$ac_config_files avr/lib/avrxmega3/Makefile"
+
+
+# avrxmega3/short-calls
+ac_config_files="$ac_config_files avr/lib/avrxmega3/short-calls/Makefile"
+
+
+# avrxmega4
+ac_config_files="$ac_config_files avr/lib/avrxmega4/Makefile avr/lib/avrxmega4/atxmega64a3/Makefile avr/lib/avrxmega4/atxmega64a3u/Makefile avr/lib/avrxmega4/atxmega64a4u/Makefile avr/lib/avrxmega4/atxmega64b1/Makefile avr/lib/avrxmega4/atxmega64b3/Makefile avr/lib/avrxmega4/atxmega64c3/Makefile avr/lib/avrxmega4/atxmega64d3/Makefile avr/lib/avrxmega4/atxmega64d4/Makefile"
+
+
+# avrxmega5
+ac_config_files="$ac_config_files avr/lib/avrxmega5/Makefile avr/lib/avrxmega5/atxmega64a1/Makefile avr/lib/avrxmega5/atxmega64a1u/Makefile"
+
+
+# avrxmega6
+ac_config_files="$ac_config_files avr/lib/avrxmega6/Makefile avr/lib/avrxmega6/atxmega128a3/Makefile avr/lib/avrxmega6/atxmega128a3u/Makefile avr/lib/avrxmega6/atxmega128b1/Makefile avr/lib/avrxmega6/atxmega128b3/Makefile avr/lib/avrxmega6/atxmega128c3/Makefile avr/lib/avrxmega6/atxmega128d3/Makefile avr/lib/avrxmega6/atxmega128d4/Makefile avr/lib/avrxmega6/atxmega192a3/Makefile avr/lib/avrxmega6/atxmega192a3u/Makefile avr/lib/avrxmega6/atxmega192c3/Makefile avr/lib/avrxmega6/atxmega192d3/Makefile avr/lib/avrxmega6/atxmega256a3/Makefile avr/lib/avrxmega6/atxmega256a3u/Makefile avr/lib/avrxmega6/atxmega256a3b/Makefile avr/lib/avrxmega6/atxmega256a3bu/Makefile avr/lib/avrxmega6/atxmega256c3/Makefile avr/lib/avrxmega6/atxmega256d3/Makefile avr/lib/avrxmega6/atxmega384c3/Makefile avr/lib/avrxmega6/atxmega384d3/Makefile"
+
+
+# avrxmega7
+ac_config_files="$ac_config_files avr/lib/avrxmega7/Makefile avr/lib/avrxmega7/atxmega128a1/Makefile avr/lib/avrxmega7/atxmega128a1u/Makefile avr/lib/avrxmega7/atxmega128a4u/Makefile"
+
+
+
+# avrtiny
+ac_config_files="$ac_config_files avr/lib/avrtiny/Makefile avr/lib/avrtiny/attiny4/Makefile avr/lib/avrtiny/attiny5/Makefile avr/lib/avrtiny/attiny9/Makefile avr/lib/avrtiny/attiny10/Makefile avr/lib/avrtiny/attiny20/Makefile avr/lib/avrtiny/attiny40/Makefile"
+
+
+
+cat >confcache <<\_ACEOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs, see configure's option --config-cache.
+# It is not useful on other systems.  If it contains results you don't
+# want to keep, you may remove or edit it.
+#
+# config.status only pays attention to the cache file if you give it
+# the --recheck option to rerun configure.
+#
+# `ac_cv_env_foo' variables (set or unset) will be overridden when
+# loading this file, other *unset* `ac_cv_foo' will be assigned the
+# following values.
+
+_ACEOF
+
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, we kill variables containing newlines.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+(
+  for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do
+    eval ac_val=\$$ac_var
+    case $ac_val in #(
+    *${as_nl}*)
+      case $ac_var in #(
+      *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5
+$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
+      esac
+      case $ac_var in #(
+      _ | IFS | as_nl) ;; #(
+      BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
+      *) { eval $ac_var=; unset $ac_var;} ;;
+      esac ;;
+    esac
+  done
+
+  (set) 2>&1 |
+    case $as_nl`(ac_space=' '; set) 2>&1` in #(
+    *${as_nl}ac_space=\ *)
+      # `set' does not quote correctly, so add quotes: double-quote
+      # substitution turns \\\\ into \\, and sed turns \\ into \.
+      sed -n \
+	"s/'/'\\\\''/g;
+	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
+      ;; #(
+    *)
+      # `set' quotes correctly as required by POSIX, so do not add quotes.
+      sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
+      ;;
+    esac |
+    sort
+) |
+  sed '
+     /^ac_cv_env_/b end
+     t clear
+     :clear
+     s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
+     t end
+     s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
+     :end' >>confcache
+if diff "$cache_file" confcache >/dev/null 2>&1; then :; else
+  if test -w "$cache_file"; then
+    if test "x$cache_file" != "x/dev/null"; then
+      { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5
+$as_echo "$as_me: updating cache $cache_file" >&6;}
+      if test ! -f "$cache_file" || test -h "$cache_file"; then
+	cat confcache >"$cache_file"
+      else
+        case $cache_file in #(
+        */* | ?:*)
+	  mv -f confcache "$cache_file"$$ &&
+	  mv -f "$cache_file"$$ "$cache_file" ;; #(
+        *)
+	  mv -f confcache "$cache_file" ;;
+	esac
+      fi
+    fi
+  else
+    { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5
+$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;}
+  fi
+fi
+rm -f confcache
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+DEFS=-DHAVE_CONFIG_H
+
+ac_libobjs=
+ac_ltlibobjs=
+U=
+for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
+  # 1. Remove the extension, and $U if already installed.
+  ac_script='s/\$U\././;s/\.o$//;s/\.obj$//'
+  ac_i=`$as_echo "$ac_i" | sed "$ac_script"`
+  # 2. Prepend LIBOBJDIR.  When used with automake>=1.10 LIBOBJDIR
+  #    will be set to the directory where LIBOBJS objects are built.
+  as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext"
+  as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo'
+done
+LIBOBJS=$ac_libobjs
+
+LTLIBOBJS=$ac_ltlibobjs
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking that generated files are newer than configure" >&5
+$as_echo_n "checking that generated files are newer than configure... " >&6; }
+   if test -n "$am_sleep_pid"; then
+     # Hide warnings about reused PIDs.
+     wait $am_sleep_pid 2>/dev/null
+   fi
+   { $as_echo "$as_me:${as_lineno-$LINENO}: result: done" >&5
+$as_echo "done" >&6; }
+ if test -n "$EXEEXT"; then
+  am__EXEEXT_TRUE=
+  am__EXEEXT_FALSE='#'
+else
+  am__EXEEXT_TRUE='#'
+  am__EXEEXT_FALSE=
+fi
+
+if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then
+  as_fn_error $? "conditional \"AMDEP\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then
+  as_fn_error $? "conditional \"am__fastdepCC\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${am__fastdepCCAS_TRUE}" && test -z "${am__fastdepCCAS_FALSE}"; then
+  as_fn_error $? "conditional \"am__fastdepCCAS\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_GCC_5_1_TRUE}" && test -z "${HAS_GCC_5_1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_GCC_5_1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_DEV_LIB_TRUE}" && test -z "${HAS_DEV_LIB_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_DEV_LIB\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avr1_TRUE}" && test -z "${HAS_avr1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avr1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90s1200_TRUE}" && test -z "${HAS_at90s1200_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90s1200\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny11_TRUE}" && test -z "${HAS_attiny11_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny11\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny12_TRUE}" && test -z "${HAS_attiny12_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny12\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny15_TRUE}" && test -z "${HAS_attiny15_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny15\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny28_TRUE}" && test -z "${HAS_attiny28_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny28\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avr2_TRUE}" && test -z "${HAS_avr2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avr2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90s2313_TRUE}" && test -z "${HAS_at90s2313_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90s2313\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90s2323_TRUE}" && test -z "${HAS_at90s2323_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90s2323\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90s2333_TRUE}" && test -z "${HAS_at90s2333_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90s2333\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90s2343_TRUE}" && test -z "${HAS_at90s2343_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90s2343\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90s4414_TRUE}" && test -z "${HAS_at90s4414_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90s4414\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90s4433_TRUE}" && test -z "${HAS_at90s4433_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90s4433\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90s4434_TRUE}" && test -z "${HAS_at90s4434_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90s4434\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90s8515_TRUE}" && test -z "${HAS_at90s8515_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90s8515\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90c8534_TRUE}" && test -z "${HAS_at90c8534_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90c8534\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90s8535_TRUE}" && test -z "${HAS_at90s8535_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90s8535\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny22_TRUE}" && test -z "${HAS_attiny22_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny22\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny26_TRUE}" && test -z "${HAS_attiny26_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny26\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avr25_TRUE}" && test -z "${HAS_avr25_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avr25\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata5272_TRUE}" && test -z "${HAS_ata5272_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata5272\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata6616c_TRUE}" && test -z "${HAS_ata6616c_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata6616c\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny13_TRUE}" && test -z "${HAS_attiny13_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny13\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny13a_TRUE}" && test -z "${HAS_attiny13a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny13a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny2313_TRUE}" && test -z "${HAS_attiny2313_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny2313\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny2313a_TRUE}" && test -z "${HAS_attiny2313a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny2313a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny24_TRUE}" && test -z "${HAS_attiny24_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny24\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny24a_TRUE}" && test -z "${HAS_attiny24a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny24a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny25_TRUE}" && test -z "${HAS_attiny25_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny25\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny261_TRUE}" && test -z "${HAS_attiny261_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny261\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny261a_TRUE}" && test -z "${HAS_attiny261a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny261a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny43u_TRUE}" && test -z "${HAS_attiny43u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny43u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny4313_TRUE}" && test -z "${HAS_attiny4313_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny4313\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny44_TRUE}" && test -z "${HAS_attiny44_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny44\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny441_TRUE}" && test -z "${HAS_attiny441_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny441\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny44a_TRUE}" && test -z "${HAS_attiny44a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny44a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny45_TRUE}" && test -z "${HAS_attiny45_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny45\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny461_TRUE}" && test -z "${HAS_attiny461_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny461\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny461a_TRUE}" && test -z "${HAS_attiny461a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny461a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny48_TRUE}" && test -z "${HAS_attiny48_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny48\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny828_TRUE}" && test -z "${HAS_attiny828_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny828\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny84_TRUE}" && test -z "${HAS_attiny84_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny84\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny841_TRUE}" && test -z "${HAS_attiny841_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny841\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny84a_TRUE}" && test -z "${HAS_attiny84a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny84a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny85_TRUE}" && test -z "${HAS_attiny85_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny85\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny861_TRUE}" && test -z "${HAS_attiny861_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny861\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny861a_TRUE}" && test -z "${HAS_attiny861a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny861a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny87_TRUE}" && test -z "${HAS_attiny87_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny87\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny88_TRUE}" && test -z "${HAS_attiny88_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny88\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at86rf401_TRUE}" && test -z "${HAS_at86rf401_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at86rf401\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avr3_TRUE}" && test -z "${HAS_avr3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avr3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at43usb320_TRUE}" && test -z "${HAS_at43usb320_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at43usb320\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at43usb355_TRUE}" && test -z "${HAS_at43usb355_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at43usb355\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at76c711_TRUE}" && test -z "${HAS_at76c711_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at76c711\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avr31_TRUE}" && test -z "${HAS_avr31_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avr31\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega103_TRUE}" && test -z "${HAS_atmega103_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega103\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avr35_TRUE}" && test -z "${HAS_avr35_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avr35\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90usb82_TRUE}" && test -z "${HAS_at90usb82_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90usb82\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90usb162_TRUE}" && test -z "${HAS_at90usb162_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90usb162\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata5505_TRUE}" && test -z "${HAS_ata5505_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata5505\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata6617c_TRUE}" && test -z "${HAS_ata6617c_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata6617c\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata664251_TRUE}" && test -z "${HAS_ata664251_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata664251\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega8u2_TRUE}" && test -z "${HAS_atmega8u2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega8u2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega16u2_TRUE}" && test -z "${HAS_atmega16u2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega16u2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega32u2_TRUE}" && test -z "${HAS_atmega32u2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega32u2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny167_TRUE}" && test -z "${HAS_attiny167_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny167\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny1634_TRUE}" && test -z "${HAS_attiny1634_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny1634\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avr4_TRUE}" && test -z "${HAS_avr4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avr4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega8_TRUE}" && test -z "${HAS_atmega8_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega8\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega8515_TRUE}" && test -z "${HAS_atmega8515_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega8515\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega8535_TRUE}" && test -z "${HAS_atmega8535_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega8535\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata6285_TRUE}" && test -z "${HAS_ata6285_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata6285\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata6286_TRUE}" && test -z "${HAS_ata6286_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata6286\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata6289_TRUE}" && test -z "${HAS_ata6289_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata6289\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata6612c_TRUE}" && test -z "${HAS_ata6612c_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata6612c\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega8a_TRUE}" && test -z "${HAS_atmega8a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega8a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega48_TRUE}" && test -z "${HAS_atmega48_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega48\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega48a_TRUE}" && test -z "${HAS_atmega48a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega48a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega48pa_TRUE}" && test -z "${HAS_atmega48pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega48pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega48pb_TRUE}" && test -z "${HAS_atmega48pb_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega48pb\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega48p_TRUE}" && test -z "${HAS_atmega48p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega48p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega88_TRUE}" && test -z "${HAS_atmega88_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega88\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega88a_TRUE}" && test -z "${HAS_atmega88a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega88a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega88p_TRUE}" && test -z "${HAS_atmega88p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega88p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega88pa_TRUE}" && test -z "${HAS_atmega88pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega88pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega88pb_TRUE}" && test -z "${HAS_atmega88pb_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega88pb\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega8hva_TRUE}" && test -z "${HAS_atmega8hva_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega8hva\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90pwm1_TRUE}" && test -z "${HAS_at90pwm1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90pwm1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90pwm2_TRUE}" && test -z "${HAS_at90pwm2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90pwm2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90pwm2b_TRUE}" && test -z "${HAS_at90pwm2b_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90pwm2b\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90pwm3_TRUE}" && test -z "${HAS_at90pwm3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90pwm3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90pwm3b_TRUE}" && test -z "${HAS_at90pwm3b_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90pwm3b\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90pwm81_TRUE}" && test -z "${HAS_at90pwm81_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90pwm81\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avr5_TRUE}" && test -z "${HAS_avr5_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avr5\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90can32_TRUE}" && test -z "${HAS_at90can32_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90can32\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90can64_TRUE}" && test -z "${HAS_at90can64_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90can64\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90scr100_TRUE}" && test -z "${HAS_at90scr100_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90scr100\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90usb646_TRUE}" && test -z "${HAS_at90usb646_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90usb646\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90usb647_TRUE}" && test -z "${HAS_at90usb647_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90usb647\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90pwm316_TRUE}" && test -z "${HAS_at90pwm316_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90pwm316\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90pwm216_TRUE}" && test -z "${HAS_at90pwm216_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90pwm216\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90pwm161_TRUE}" && test -z "${HAS_at90pwm161_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90pwm161\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at94k_TRUE}" && test -z "${HAS_at94k_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at94k\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata5702m322_TRUE}" && test -z "${HAS_ata5702m322_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata5702m322\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata5782_TRUE}" && test -z "${HAS_ata5782_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata5782\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata5790_TRUE}" && test -z "${HAS_ata5790_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata5790\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata5790n_TRUE}" && test -z "${HAS_ata5790n_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata5790n\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata5791_TRUE}" && test -z "${HAS_ata5791_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata5791\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata5795_TRUE}" && test -z "${HAS_ata5795_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata5795\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata5831_TRUE}" && test -z "${HAS_ata5831_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata5831\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata6613c_TRUE}" && test -z "${HAS_ata6613c_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata6613c\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata6614q_TRUE}" && test -z "${HAS_ata6614q_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata6614q\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata8210_TRUE}" && test -z "${HAS_ata8210_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata8210\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_ata8510_TRUE}" && test -z "${HAS_ata8510_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_ata8510\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega16_TRUE}" && test -z "${HAS_atmega16_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega16\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega16a_TRUE}" && test -z "${HAS_atmega16a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega16a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega161_TRUE}" && test -z "${HAS_atmega161_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega161\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega162_TRUE}" && test -z "${HAS_atmega162_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega162\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega163_TRUE}" && test -z "${HAS_atmega163_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega163\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega164a_TRUE}" && test -z "${HAS_atmega164a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega164a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega164p_TRUE}" && test -z "${HAS_atmega164p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega164p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega164pa_TRUE}" && test -z "${HAS_atmega164pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega164pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega165_TRUE}" && test -z "${HAS_atmega165_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega165\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega165a_TRUE}" && test -z "${HAS_atmega165a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega165a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega165p_TRUE}" && test -z "${HAS_atmega165p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega165p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega165pa_TRUE}" && test -z "${HAS_atmega165pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega165pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega168_TRUE}" && test -z "${HAS_atmega168_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega168\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega168a_TRUE}" && test -z "${HAS_atmega168a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega168a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega168p_TRUE}" && test -z "${HAS_atmega168p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega168p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega168pa_TRUE}" && test -z "${HAS_atmega168pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega168pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega168pb_TRUE}" && test -z "${HAS_atmega168pb_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega168pb\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega169_TRUE}" && test -z "${HAS_atmega169_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega169\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega169a_TRUE}" && test -z "${HAS_atmega169a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega169a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega169p_TRUE}" && test -z "${HAS_atmega169p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega169p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega169pa_TRUE}" && test -z "${HAS_atmega169pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega169pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega16hva_TRUE}" && test -z "${HAS_atmega16hva_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega16hva\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega16hva2_TRUE}" && test -z "${HAS_atmega16hva2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega16hva2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega16hvb_TRUE}" && test -z "${HAS_atmega16hvb_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega16hvb\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega16hvbrevb_TRUE}" && test -z "${HAS_atmega16hvbrevb_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega16hvbrevb\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega16m1_TRUE}" && test -z "${HAS_atmega16m1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega16m1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega16u4_TRUE}" && test -z "${HAS_atmega16u4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega16u4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega32_TRUE}" && test -z "${HAS_atmega32_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega32\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega32a_TRUE}" && test -z "${HAS_atmega32a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega32a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega323_TRUE}" && test -z "${HAS_atmega323_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega323\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega324a_TRUE}" && test -z "${HAS_atmega324a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega324a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega324p_TRUE}" && test -z "${HAS_atmega324p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega324p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega324pa_TRUE}" && test -z "${HAS_atmega324pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega324pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega325_TRUE}" && test -z "${HAS_atmega325_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega325\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega325a_TRUE}" && test -z "${HAS_atmega325a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega325a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega325p_TRUE}" && test -z "${HAS_atmega325p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega325p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega325pa_TRUE}" && test -z "${HAS_atmega325pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega325pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega3250_TRUE}" && test -z "${HAS_atmega3250_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega3250\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega3250a_TRUE}" && test -z "${HAS_atmega3250a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega3250a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega3250p_TRUE}" && test -z "${HAS_atmega3250p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega3250p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega3250pa_TRUE}" && test -z "${HAS_atmega3250pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega3250pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega328_TRUE}" && test -z "${HAS_atmega328_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega328\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega328p_TRUE}" && test -z "${HAS_atmega328p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega328p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega329_TRUE}" && test -z "${HAS_atmega329_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega329\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega329a_TRUE}" && test -z "${HAS_atmega329a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega329a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega329p_TRUE}" && test -z "${HAS_atmega329p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega329p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega329pa_TRUE}" && test -z "${HAS_atmega329pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega329pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega3290_TRUE}" && test -z "${HAS_atmega3290_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega3290\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega3290a_TRUE}" && test -z "${HAS_atmega3290a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega3290a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega3290p_TRUE}" && test -z "${HAS_atmega3290p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega3290p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega3290pa_TRUE}" && test -z "${HAS_atmega3290pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega3290pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega32c1_TRUE}" && test -z "${HAS_atmega32c1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega32c1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega32hvb_TRUE}" && test -z "${HAS_atmega32hvb_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega32hvb\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega32hvbrevb_TRUE}" && test -z "${HAS_atmega32hvbrevb_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega32hvbrevb\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega32m1_TRUE}" && test -z "${HAS_atmega32m1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega32m1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega32u4_TRUE}" && test -z "${HAS_atmega32u4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega32u4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega32u6_TRUE}" && test -z "${HAS_atmega32u6_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega32u6\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega406_TRUE}" && test -z "${HAS_atmega406_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega406\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega644rfr2_TRUE}" && test -z "${HAS_atmega644rfr2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega644rfr2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega64rfr2_TRUE}" && test -z "${HAS_atmega64rfr2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega64rfr2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega64_TRUE}" && test -z "${HAS_atmega64_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega64\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega64a_TRUE}" && test -z "${HAS_atmega64a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega64a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega640_TRUE}" && test -z "${HAS_atmega640_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega640\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega644_TRUE}" && test -z "${HAS_atmega644_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega644\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega644a_TRUE}" && test -z "${HAS_atmega644a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega644a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega644p_TRUE}" && test -z "${HAS_atmega644p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega644p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega644pa_TRUE}" && test -z "${HAS_atmega644pa_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega644pa\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega645_TRUE}" && test -z "${HAS_atmega645_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega645\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega645a_TRUE}" && test -z "${HAS_atmega645a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega645a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega645p_TRUE}" && test -z "${HAS_atmega645p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega645p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega6450_TRUE}" && test -z "${HAS_atmega6450_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega6450\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega6450a_TRUE}" && test -z "${HAS_atmega6450a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega6450a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega6450p_TRUE}" && test -z "${HAS_atmega6450p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega6450p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega649_TRUE}" && test -z "${HAS_atmega649_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega649\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega649a_TRUE}" && test -z "${HAS_atmega649a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega649a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega649p_TRUE}" && test -z "${HAS_atmega649p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega649p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega6490_TRUE}" && test -z "${HAS_atmega6490_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega6490\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega6490a_TRUE}" && test -z "${HAS_atmega6490a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega6490a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega6490p_TRUE}" && test -z "${HAS_atmega6490p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega6490p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega64c1_TRUE}" && test -z "${HAS_atmega64c1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega64c1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega64hve_TRUE}" && test -z "${HAS_atmega64hve_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega64hve\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega64hve2_TRUE}" && test -z "${HAS_atmega64hve2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega64hve2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega64m1_TRUE}" && test -z "${HAS_atmega64m1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega64m1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega128rfa1_TRUE}" && test -z "${HAS_atmega128rfa1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega128rfa1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_m3000_TRUE}" && test -z "${HAS_m3000_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_m3000\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avr51_TRUE}" && test -z "${HAS_avr51_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avr51\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega128_TRUE}" && test -z "${HAS_atmega128_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega128\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega128a_TRUE}" && test -z "${HAS_atmega128a_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega128a\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega1280_TRUE}" && test -z "${HAS_atmega1280_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega1280\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega1281_TRUE}" && test -z "${HAS_atmega1281_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega1281\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega1284_TRUE}" && test -z "${HAS_atmega1284_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega1284\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega1284p_TRUE}" && test -z "${HAS_atmega1284p_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega1284p\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90can128_TRUE}" && test -z "${HAS_at90can128_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90can128\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90usb1286_TRUE}" && test -z "${HAS_at90usb1286_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90usb1286\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_at90usb1287_TRUE}" && test -z "${HAS_at90usb1287_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_at90usb1287\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega1284rfr2_TRUE}" && test -z "${HAS_atmega1284rfr2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega1284rfr2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega128rfr2_TRUE}" && test -z "${HAS_atmega128rfr2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega128rfr2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avr6_TRUE}" && test -z "${HAS_avr6_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avr6\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega2560_TRUE}" && test -z "${HAS_atmega2560_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega2560\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega2561_TRUE}" && test -z "${HAS_atmega2561_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega2561\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega2564rfr2_TRUE}" && test -z "${HAS_atmega2564rfr2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega2564rfr2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atmega256rfr2_TRUE}" && test -z "${HAS_atmega256rfr2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atmega256rfr2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avrxmega2_TRUE}" && test -z "${HAS_avrxmega2_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avrxmega2\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega8e5_TRUE}" && test -z "${HAS_atxmega8e5_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega8e5\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega16a4_TRUE}" && test -z "${HAS_atxmega16a4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega16a4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega16a4u_TRUE}" && test -z "${HAS_atxmega16a4u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega16a4u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega16c4_TRUE}" && test -z "${HAS_atxmega16c4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega16c4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega16d4_TRUE}" && test -z "${HAS_atxmega16d4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega16d4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega32a4_TRUE}" && test -z "${HAS_atxmega32a4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega32a4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega32a4u_TRUE}" && test -z "${HAS_atxmega32a4u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega32a4u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega32c3_TRUE}" && test -z "${HAS_atxmega32c3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega32c3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega32c4_TRUE}" && test -z "${HAS_atxmega32c4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega32c4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega32d3_TRUE}" && test -z "${HAS_atxmega32d3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega32d3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega32d4_TRUE}" && test -z "${HAS_atxmega32d4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega32d4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega16e5_TRUE}" && test -z "${HAS_atxmega16e5_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega16e5\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega32e5_TRUE}" && test -z "${HAS_atxmega32e5_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega32e5\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avrxmega3_TRUE}" && test -z "${HAS_avrxmega3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avrxmega3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avrxmega4_TRUE}" && test -z "${HAS_avrxmega4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avrxmega4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega64a3_TRUE}" && test -z "${HAS_atxmega64a3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega64a3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega64a3u_TRUE}" && test -z "${HAS_atxmega64a3u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega64a3u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega64a4u_TRUE}" && test -z "${HAS_atxmega64a4u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega64a4u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega64b1_TRUE}" && test -z "${HAS_atxmega64b1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega64b1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega64b3_TRUE}" && test -z "${HAS_atxmega64b3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega64b3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega64c3_TRUE}" && test -z "${HAS_atxmega64c3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega64c3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega64d3_TRUE}" && test -z "${HAS_atxmega64d3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega64d3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega64d4_TRUE}" && test -z "${HAS_atxmega64d4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega64d4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avrxmega5_TRUE}" && test -z "${HAS_avrxmega5_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avrxmega5\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega64a1_TRUE}" && test -z "${HAS_atxmega64a1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega64a1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega64a1u_TRUE}" && test -z "${HAS_atxmega64a1u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega64a1u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avrxmega6_TRUE}" && test -z "${HAS_avrxmega6_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avrxmega6\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega128a3_TRUE}" && test -z "${HAS_atxmega128a3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega128a3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega128a3u_TRUE}" && test -z "${HAS_atxmega128a3u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega128a3u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega128b1_TRUE}" && test -z "${HAS_atxmega128b1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega128b1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega128b3_TRUE}" && test -z "${HAS_atxmega128b3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega128b3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega128c3_TRUE}" && test -z "${HAS_atxmega128c3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega128c3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega128d3_TRUE}" && test -z "${HAS_atxmega128d3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega128d3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega128d4_TRUE}" && test -z "${HAS_atxmega128d4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega128d4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega192a3_TRUE}" && test -z "${HAS_atxmega192a3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega192a3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega192a3u_TRUE}" && test -z "${HAS_atxmega192a3u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega192a3u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega192c3_TRUE}" && test -z "${HAS_atxmega192c3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega192c3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega192d3_TRUE}" && test -z "${HAS_atxmega192d3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega192d3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega256a3_TRUE}" && test -z "${HAS_atxmega256a3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega256a3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega256a3u_TRUE}" && test -z "${HAS_atxmega256a3u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega256a3u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega256a3b_TRUE}" && test -z "${HAS_atxmega256a3b_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega256a3b\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega256a3bu_TRUE}" && test -z "${HAS_atxmega256a3bu_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega256a3bu\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega256c3_TRUE}" && test -z "${HAS_atxmega256c3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega256c3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega256d3_TRUE}" && test -z "${HAS_atxmega256d3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega256d3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega384c3_TRUE}" && test -z "${HAS_atxmega384c3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega384c3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega384d3_TRUE}" && test -z "${HAS_atxmega384d3_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega384d3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avrxmega7_TRUE}" && test -z "${HAS_avrxmega7_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avrxmega7\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega128a1_TRUE}" && test -z "${HAS_atxmega128a1_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega128a1\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega128a1u_TRUE}" && test -z "${HAS_atxmega128a1u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega128a1u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_atxmega128a4u_TRUE}" && test -z "${HAS_atxmega128a4u_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_atxmega128a4u\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_avrtiny_TRUE}" && test -z "${HAS_avrtiny_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_avrtiny\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny4_TRUE}" && test -z "${HAS_attiny4_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny4\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny5_TRUE}" && test -z "${HAS_attiny5_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny5\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny9_TRUE}" && test -z "${HAS_attiny9_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny9\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny10_TRUE}" && test -z "${HAS_attiny10_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny10\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny20_TRUE}" && test -z "${HAS_attiny20_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny20\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAS_attiny40_TRUE}" && test -z "${HAS_attiny40_FALSE}"; then
+  as_fn_error $? "conditional \"HAS_attiny40\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+
+: "${CONFIG_STATUS=./config.status}"
+ac_write_fail=0
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files $CONFIG_STATUS"
+{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5
+$as_echo "$as_me: creating $CONFIG_STATUS" >&6;}
+as_write_fail=0
+cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1
+#! $SHELL
+# Generated by $as_me.
+# Run this file to recreate the current configuration.
+# Compiler output produced by configure, useful for debugging
+# configure, is in config.log if it exists.
+
+debug=false
+ac_cs_recheck=false
+ac_cs_silent=false
+
+SHELL=\${CONFIG_SHELL-$SHELL}
+export SHELL
+_ASEOF
+cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1
+## -------------------- ##
+## M4sh Initialization. ##
+## -------------------- ##
+
+# Be more Bourne compatible
+DUALCASE=1; export DUALCASE # for MKS sh
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
+  emulate sh
+  NULLCMD=:
+  # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '${1+"$@"}'='"$@"'
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in #(
+  *posix*) :
+    set -o posix ;; #(
+  *) :
+     ;;
+esac
+fi
+
+
+as_nl='
+'
+export as_nl
+# Printing a long string crashes Solaris 7 /usr/bin/printf.
+as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
+# Prefer a ksh shell builtin over an external printf program on Solaris,
+# but without wasting forks for bash or zsh.
+if test -z "$BASH_VERSION$ZSH_VERSION" \
+    && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
+  as_echo='print -r --'
+  as_echo_n='print -rn --'
+elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
+  as_echo='printf %s\n'
+  as_echo_n='printf %s'
+else
+  if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
+    as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
+    as_echo_n='/usr/ucb/echo -n'
+  else
+    as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
+    as_echo_n_body='eval
+      arg=$1;
+      case $arg in #(
+      *"$as_nl"*)
+	expr "X$arg" : "X\\(.*\\)$as_nl";
+	arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
+      esac;
+      expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
+    '
+    export as_echo_n_body
+    as_echo_n='sh -c $as_echo_n_body as_echo'
+  fi
+  export as_echo_body
+  as_echo='sh -c $as_echo_body as_echo'
+fi
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  PATH_SEPARATOR=:
+  (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
+    (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
+      PATH_SEPARATOR=';'
+  }
+fi
+
+
+# IFS
+# We need space, tab and new line, in precisely that order.  Quoting is
+# there to prevent editors from complaining about space-tab.
+# (If _AS_PATH_WALK were called with IFS unset, it would disable word
+# splitting by setting IFS to empty value.)
+IFS=" ""	$as_nl"
+
+# Find who we are.  Look in the path if we contain no directory separator.
+as_myself=
+case $0 in #((
+  *[\\/]* ) as_myself=$0 ;;
+  *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+  done
+IFS=$as_save_IFS
+
+     ;;
+esac
+# We did not find ourselves, most probably we were run as `sh COMMAND'
+# in which case we are not to be found in the path.
+if test "x$as_myself" = x; then
+  as_myself=$0
+fi
+if test ! -f "$as_myself"; then
+  $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
+  exit 1
+fi
+
+# Unset variables that we do not need and which cause bugs (e.g. in
+# pre-3.0 UWIN ksh).  But do not cause bugs in bash 2.01; the "|| exit 1"
+# suppresses any "Segmentation fault" message there.  '((' could
+# trigger a bug in pdksh 5.2.14.
+for as_var in BASH_ENV ENV MAIL MAILPATH
+do eval test x\${$as_var+set} = xset \
+  && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
+done
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+LC_ALL=C
+export LC_ALL
+LANGUAGE=C
+export LANGUAGE
+
+# CDPATH.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+
+# as_fn_error STATUS ERROR [LINENO LOG_FD]
+# ----------------------------------------
+# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
+# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
+# script with STATUS, using 1 if that was 0.
+as_fn_error ()
+{
+  as_status=$1; test $as_status -eq 0 && as_status=1
+  if test "$4"; then
+    as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+    $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4
+  fi
+  $as_echo "$as_me: error: $2" >&2
+  as_fn_exit $as_status
+} # as_fn_error
+
+
+# as_fn_set_status STATUS
+# -----------------------
+# Set $? to STATUS, without forking.
+as_fn_set_status ()
+{
+  return $1
+} # as_fn_set_status
+
+# as_fn_exit STATUS
+# -----------------
+# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
+as_fn_exit ()
+{
+  set +e
+  as_fn_set_status $1
+  exit $1
+} # as_fn_exit
+
+# as_fn_unset VAR
+# ---------------
+# Portably unset VAR.
+as_fn_unset ()
+{
+  { eval $1=; unset $1;}
+}
+as_unset=as_fn_unset
+# as_fn_append VAR VALUE
+# ----------------------
+# Append the text in VALUE to the end of the definition contained in VAR. Take
+# advantage of any shell optimizations that allow amortized linear growth over
+# repeated appends, instead of the typical quadratic growth present in naive
+# implementations.
+if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
+  eval 'as_fn_append ()
+  {
+    eval $1+=\$2
+  }'
+else
+  as_fn_append ()
+  {
+    eval $1=\$$1\$2
+  }
+fi # as_fn_append
+
+# as_fn_arith ARG...
+# ------------------
+# Perform arithmetic evaluation on the ARGs, and store the result in the
+# global $as_val. Take advantage of shells that can avoid forks. The arguments
+# must be portable across $(()) and expr.
+if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
+  eval 'as_fn_arith ()
+  {
+    as_val=$(( $* ))
+  }'
+else
+  as_fn_arith ()
+  {
+    as_val=`expr "$@" || test $? -eq 1`
+  }
+fi # as_fn_arith
+
+
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+   test "X`expr 00001 : '.*\(...\)'`" = X001; then
+  as_expr=expr
+else
+  as_expr=false
+fi
+
+if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
+  as_basename=basename
+else
+  as_basename=false
+fi
+
+if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
+  as_dirname=dirname
+else
+  as_dirname=false
+fi
+
+as_me=`$as_basename -- "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+	 X"$0" : 'X\(//\)$' \| \
+	 X"$0" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X/"$0" |
+    sed '/^.*\/\([^/][^/]*\)\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\/\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\/\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+ECHO_C= ECHO_N= ECHO_T=
+case `echo -n x` in #(((((
+-n*)
+  case `echo 'xy\c'` in
+  *c*) ECHO_T='	';;	# ECHO_T is single tab character.
+  xy)  ECHO_C='\c';;
+  *)   echo `echo ksh88 bug on AIX 6.1` > /dev/null
+       ECHO_T='	';;
+  esac;;
+*)
+  ECHO_N='-n';;
+esac
+
+rm -f conf$$ conf$$.exe conf$$.file
+if test -d conf$$.dir; then
+  rm -f conf$$.dir/conf$$.file
+else
+  rm -f conf$$.dir
+  mkdir conf$$.dir 2>/dev/null
+fi
+if (echo >conf$$.file) 2>/dev/null; then
+  if ln -s conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s='ln -s'
+    # ... but there are two gotchas:
+    # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
+    # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
+    # In both cases, we have to default to `cp -pR'.
+    ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
+      as_ln_s='cp -pR'
+  elif ln conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s=ln
+  else
+    as_ln_s='cp -pR'
+  fi
+else
+  as_ln_s='cp -pR'
+fi
+rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
+rmdir conf$$.dir 2>/dev/null
+
+
+# as_fn_mkdir_p
+# -------------
+# Create "$as_dir" as a directory, including parents if necessary.
+as_fn_mkdir_p ()
+{
+
+  case $as_dir in #(
+  -*) as_dir=./$as_dir;;
+  esac
+  test -d "$as_dir" || eval $as_mkdir_p || {
+    as_dirs=
+    while :; do
+      case $as_dir in #(
+      *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
+      *) as_qdir=$as_dir;;
+      esac
+      as_dirs="'$as_qdir' $as_dirs"
+      as_dir=`$as_dirname -- "$as_dir" ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$as_dir" : 'X\(//\)[^/]' \| \
+	 X"$as_dir" : 'X\(//\)$' \| \
+	 X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$as_dir" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+      test -d "$as_dir" && break
+    done
+    test -z "$as_dirs" || eval "mkdir $as_dirs"
+  } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir"
+
+
+} # as_fn_mkdir_p
+if mkdir -p . 2>/dev/null; then
+  as_mkdir_p='mkdir -p "$as_dir"'
+else
+  test -d ./-p && rmdir ./-p
+  as_mkdir_p=false
+fi
+
+
+# as_fn_executable_p FILE
+# -----------------------
+# Test if FILE is an executable regular file.
+as_fn_executable_p ()
+{
+  test -f "$1" && test -x "$1"
+} # as_fn_executable_p
+as_test_x='test -x'
+as_executable_p=as_fn_executable_p
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+exec 6>&1
+## ----------------------------------- ##
+## Main body of $CONFIG_STATUS script. ##
+## ----------------------------------- ##
+_ASEOF
+test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# Save the log message, to keep $0 and so on meaningful, and to
+# report actual input values of CONFIG_FILES etc. instead of their
+# values after options handling.
+ac_log="
+This file was extended by avr-libc $as_me 2.0.0, which was
+generated by GNU Autoconf 2.69.  Invocation command line was
+
+  CONFIG_FILES    = $CONFIG_FILES
+  CONFIG_HEADERS  = $CONFIG_HEADERS
+  CONFIG_LINKS    = $CONFIG_LINKS
+  CONFIG_COMMANDS = $CONFIG_COMMANDS
+  $ $0 $@
+
+on `(hostname || uname -n) 2>/dev/null | sed 1q`
+"
+
+_ACEOF
+
+case $ac_config_files in *"
+"*) set x $ac_config_files; shift; ac_config_files=$*;;
+esac
+
+case $ac_config_headers in *"
+"*) set x $ac_config_headers; shift; ac_config_headers=$*;;
+esac
+
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+# Files that config.status was made for.
+config_files="$ac_config_files"
+config_headers="$ac_config_headers"
+config_commands="$ac_config_commands"
+
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+ac_cs_usage="\
+\`$as_me' instantiates files and other configuration actions
+from templates according to the current configuration.  Unless the files
+and actions are specified as TAGs, all are instantiated by default.
+
+Usage: $0 [OPTION]... [TAG]...
+
+  -h, --help       print this help, then exit
+  -V, --version    print version number and configuration settings, then exit
+      --config     print configuration, then exit
+  -q, --quiet, --silent
+                   do not print progress messages
+  -d, --debug      don't remove temporary files
+      --recheck    update $as_me by reconfiguring in the same conditions
+      --file=FILE[:TEMPLATE]
+                   instantiate the configuration file FILE
+      --header=FILE[:TEMPLATE]
+                   instantiate the configuration header FILE
+
+Configuration files:
+$config_files
+
+Configuration headers:
+$config_headers
+
+Configuration commands:
+$config_commands
+
+Report bugs to <avr-libc-dev@nongnu.org>."
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ac_cs_version="\\
+avr-libc config.status 2.0.0
+configured by $0, generated by GNU Autoconf 2.69,
+  with options \\"\$ac_cs_config\\"
+
+Copyright (C) 2012 Free Software Foundation, Inc.
+This config.status script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it."
+
+ac_pwd='$ac_pwd'
+srcdir='$srcdir'
+INSTALL='$INSTALL'
+MKDIR_P='$MKDIR_P'
+AWK='$AWK'
+test -n "\$AWK" || AWK=awk
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# The default lists apply if the user does not specify any file.
+ac_need_defaults=:
+while test $# != 0
+do
+  case $1 in
+  --*=?*)
+    ac_option=`expr "X$1" : 'X\([^=]*\)='`
+    ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
+    ac_shift=:
+    ;;
+  --*=)
+    ac_option=`expr "X$1" : 'X\([^=]*\)='`
+    ac_optarg=
+    ac_shift=:
+    ;;
+  *)
+    ac_option=$1
+    ac_optarg=$2
+    ac_shift=shift
+    ;;
+  esac
+
+  case $ac_option in
+  # Handling of the options.
+  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+    ac_cs_recheck=: ;;
+  --version | --versio | --versi | --vers | --ver | --ve | --v | -V )
+    $as_echo "$ac_cs_version"; exit ;;
+  --config | --confi | --conf | --con | --co | --c )
+    $as_echo "$ac_cs_config"; exit ;;
+  --debug | --debu | --deb | --de | --d | -d )
+    debug=: ;;
+  --file | --fil | --fi | --f )
+    $ac_shift
+    case $ac_optarg in
+    *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
+    '') as_fn_error $? "missing file argument" ;;
+    esac
+    as_fn_append CONFIG_FILES " '$ac_optarg'"
+    ac_need_defaults=false;;
+  --header | --heade | --head | --hea )
+    $ac_shift
+    case $ac_optarg in
+    *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
+    esac
+    as_fn_append CONFIG_HEADERS " '$ac_optarg'"
+    ac_need_defaults=false;;
+  --he | --h)
+    # Conflict between --help and --header
+    as_fn_error $? "ambiguous option: \`$1'
+Try \`$0 --help' for more information.";;
+  --help | --hel | -h )
+    $as_echo "$ac_cs_usage"; exit ;;
+  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+  | -silent | --silent | --silen | --sile | --sil | --si | --s)
+    ac_cs_silent=: ;;
+
+  # This is an error.
+  -*) as_fn_error $? "unrecognized option: \`$1'
+Try \`$0 --help' for more information." ;;
+
+  *) as_fn_append ac_config_targets " $1"
+     ac_need_defaults=false ;;
+
+  esac
+  shift
+done
+
+ac_configure_extra_args=
+
+if $ac_cs_silent; then
+  exec 6>/dev/null
+  ac_configure_extra_args="$ac_configure_extra_args --silent"
+fi
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+if \$ac_cs_recheck; then
+  set X $SHELL '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
+  shift
+  \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6
+  CONFIG_SHELL='$SHELL'
+  export CONFIG_SHELL
+  exec "\$@"
+fi
+
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+exec 5>>config.log
+{
+  echo
+  sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
+## Running $as_me. ##
+_ASBOX
+  $as_echo "$ac_log"
+} >&5
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+#
+# INIT-COMMANDS
+#
+AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"
+
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+
+# Handling of arguments.
+for ac_config_target in $ac_config_targets
+do
+  case $ac_config_target in
+    "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h" ;;
+    "depfiles") CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;;
+    "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;;
+    "avr-libc.spec") CONFIG_FILES="$CONFIG_FILES avr-libc.spec" ;;
+    "avr/Makefile") CONFIG_FILES="$CONFIG_FILES avr/Makefile" ;;
+    "avr/lib/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/Makefile" ;;
+    "common/Makefile") CONFIG_FILES="$CONFIG_FILES common/Makefile" ;;
+    "crt1/Makefile") CONFIG_FILES="$CONFIG_FILES crt1/Makefile" ;;
+    "crt1/iosym/Makefile") CONFIG_FILES="$CONFIG_FILES crt1/iosym/Makefile" ;;
+    "doc/Makefile") CONFIG_FILES="$CONFIG_FILES doc/Makefile" ;;
+    "doc/api/Makefile") CONFIG_FILES="$CONFIG_FILES doc/api/Makefile" ;;
+    "doc/examples/Makefile") CONFIG_FILES="$CONFIG_FILES doc/examples/Makefile" ;;
+    "include/Makefile") CONFIG_FILES="$CONFIG_FILES include/Makefile" ;;
+    "include/avr/Makefile") CONFIG_FILES="$CONFIG_FILES include/avr/Makefile" ;;
+    "include/avr/builtins.h") CONFIG_FILES="$CONFIG_FILES include/avr/builtins.h" ;;
+    "include/compat/Makefile") CONFIG_FILES="$CONFIG_FILES include/compat/Makefile" ;;
+    "include/util/Makefile") CONFIG_FILES="$CONFIG_FILES include/util/Makefile" ;;
+    "include/util/delay.h") CONFIG_FILES="$CONFIG_FILES include/util/delay.h" ;;
+    "include/sys/Makefile") CONFIG_FILES="$CONFIG_FILES include/sys/Makefile" ;;
+    "libc/Makefile") CONFIG_FILES="$CONFIG_FILES libc/Makefile" ;;
+    "libc/misc/Makefile") CONFIG_FILES="$CONFIG_FILES libc/misc/Makefile" ;;
+    "libc/pmstring/Makefile") CONFIG_FILES="$CONFIG_FILES libc/pmstring/Makefile" ;;
+    "libc/stdio/Makefile") CONFIG_FILES="$CONFIG_FILES libc/stdio/Makefile" ;;
+    "libc/stdlib/Makefile") CONFIG_FILES="$CONFIG_FILES libc/stdlib/Makefile" ;;
+    "libc/string/Makefile") CONFIG_FILES="$CONFIG_FILES libc/string/Makefile" ;;
+    "libc/time/Makefile") CONFIG_FILES="$CONFIG_FILES libc/time/Makefile" ;;
+    "libm/Makefile") CONFIG_FILES="$CONFIG_FILES libm/Makefile" ;;
+    "libm/fplib/Makefile") CONFIG_FILES="$CONFIG_FILES libm/fplib/Makefile" ;;
+    "scripts/Makefile") CONFIG_FILES="$CONFIG_FILES scripts/Makefile" ;;
+    "devtools/Makefile") CONFIG_FILES="$CONFIG_FILES devtools/Makefile" ;;
+    "avr/lib/avr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/Makefile" ;;
+    "avr/lib/avr2/at90s1200/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90s1200/Makefile" ;;
+    "avr/lib/avr2/at90s4414/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90s4414/Makefile" ;;
+    "avr/lib/avr2/at90s4434/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90s4434/Makefile" ;;
+    "avr/lib/avr2/at90s8515/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90s8515/Makefile" ;;
+    "avr/lib/avr2/at90c8534/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90c8534/Makefile" ;;
+    "avr/lib/avr2/at90s8535/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90s8535/Makefile" ;;
+    "avr/lib/avr2/attiny11/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/attiny11/Makefile" ;;
+    "avr/lib/avr2/attiny12/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/attiny12/Makefile" ;;
+    "avr/lib/avr2/attiny15/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/attiny15/Makefile" ;;
+    "avr/lib/avr2/attiny28/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/attiny28/Makefile" ;;
+    "avr/lib/avr2/tiny-stack/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/Makefile" ;;
+    "avr/lib/avr2/tiny-stack/at90s2313/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/at90s2313/Makefile" ;;
+    "avr/lib/avr2/tiny-stack/at90s2323/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/at90s2323/Makefile" ;;
+    "avr/lib/avr2/tiny-stack/at90s2333/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/at90s2333/Makefile" ;;
+    "avr/lib/avr2/tiny-stack/at90s2343/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/at90s2343/Makefile" ;;
+    "avr/lib/avr2/tiny-stack/attiny22/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/attiny22/Makefile" ;;
+    "avr/lib/avr2/tiny-stack/attiny26/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/attiny26/Makefile" ;;
+    "avr/lib/avr2/tiny-stack/at90s4433/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/at90s4433/Makefile" ;;
+    "avr/lib/avr25/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/Makefile" ;;
+    "avr/lib/avr25/at86rf401/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/at86rf401/Makefile" ;;
+    "avr/lib/avr25/ata5272/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/ata5272/Makefile" ;;
+    "avr/lib/avr25/ata6616c/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/ata6616c/Makefile" ;;
+    "avr/lib/avr25/attiny4313/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny4313/Makefile" ;;
+    "avr/lib/avr25/attiny43u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny43u/Makefile" ;;
+    "avr/lib/avr25/attiny44/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny44/Makefile" ;;
+    "avr/lib/avr25/attiny44a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny44a/Makefile" ;;
+    "avr/lib/avr25/attiny441/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny441/Makefile" ;;
+    "avr/lib/avr25/attiny45/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny45/Makefile" ;;
+    "avr/lib/avr25/attiny461/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny461/Makefile" ;;
+    "avr/lib/avr25/attiny461a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny461a/Makefile" ;;
+    "avr/lib/avr25/attiny48/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny48/Makefile" ;;
+    "avr/lib/avr25/attiny828/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny828/Makefile" ;;
+    "avr/lib/avr25/attiny84/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny84/Makefile" ;;
+    "avr/lib/avr25/attiny84a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny84a/Makefile" ;;
+    "avr/lib/avr25/attiny841/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny841/Makefile" ;;
+    "avr/lib/avr25/attiny85/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny85/Makefile" ;;
+    "avr/lib/avr25/attiny861/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny861/Makefile" ;;
+    "avr/lib/avr25/attiny861a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny861a/Makefile" ;;
+    "avr/lib/avr25/attiny87/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny87/Makefile" ;;
+    "avr/lib/avr25/attiny88/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny88/Makefile" ;;
+    "avr/lib/avr25/tiny-stack/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/Makefile" ;;
+    "avr/lib/avr25/tiny-stack/attiny13/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny13/Makefile" ;;
+    "avr/lib/avr25/tiny-stack/attiny13a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny13a/Makefile" ;;
+    "avr/lib/avr25/tiny-stack/attiny2313/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny2313/Makefile" ;;
+    "avr/lib/avr25/tiny-stack/attiny2313a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny2313a/Makefile" ;;
+    "avr/lib/avr25/tiny-stack/attiny24/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny24/Makefile" ;;
+    "avr/lib/avr25/tiny-stack/attiny24a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny24a/Makefile" ;;
+    "avr/lib/avr25/tiny-stack/attiny25/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny25/Makefile" ;;
+    "avr/lib/avr25/tiny-stack/attiny261/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny261/Makefile" ;;
+    "avr/lib/avr25/tiny-stack/attiny261a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny261a/Makefile" ;;
+    "avr/lib/avr3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/Makefile" ;;
+    "avr/lib/avr3/at43usb355/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/at43usb355/Makefile" ;;
+    "avr/lib/avr3/at76c711/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/at76c711/Makefile" ;;
+    "avr/lib/avr31/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr31/Makefile" ;;
+    "avr/lib/avr31/atmega103/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr31/atmega103/Makefile" ;;
+    "avr/lib/avr31/at43usb320/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr31/at43usb320/Makefile" ;;
+    "avr/lib/avr35/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/Makefile" ;;
+    "avr/lib/avr35/at90usb82/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/at90usb82/Makefile" ;;
+    "avr/lib/avr35/at90usb162/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/at90usb162/Makefile" ;;
+    "avr/lib/avr35/ata5505/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/ata5505/Makefile" ;;
+    "avr/lib/avr35/ata6617c/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/ata6617c/Makefile" ;;
+    "avr/lib/avr35/ata664251/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/ata664251/Makefile" ;;
+    "avr/lib/avr35/atmega8u2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/atmega8u2/Makefile" ;;
+    "avr/lib/avr35/atmega16u2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/atmega16u2/Makefile" ;;
+    "avr/lib/avr35/atmega32u2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/atmega32u2/Makefile" ;;
+    "avr/lib/avr35/attiny167/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/attiny167/Makefile" ;;
+    "avr/lib/avr35/attiny1634/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/attiny1634/Makefile" ;;
+    "avr/lib/avr4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/Makefile" ;;
+    "avr/lib/avr4/ata6285/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/ata6285/Makefile" ;;
+    "avr/lib/avr4/ata6286/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/ata6286/Makefile" ;;
+    "avr/lib/avr4/ata6289/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/ata6289/Makefile" ;;
+    "avr/lib/avr4/ata6612c/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/ata6612c/Makefile" ;;
+    "avr/lib/avr4/atmega48/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48/Makefile" ;;
+    "avr/lib/avr4/atmega48a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48a/Makefile" ;;
+    "avr/lib/avr4/atmega48pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48pa/Makefile" ;;
+    "avr/lib/avr4/atmega48pb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48pb/Makefile" ;;
+    "avr/lib/avr4/atmega48p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48p/Makefile" ;;
+    "avr/lib/avr4/atmega8/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8/Makefile" ;;
+    "avr/lib/avr4/atmega8a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8a/Makefile" ;;
+    "avr/lib/avr4/atmega88/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88/Makefile" ;;
+    "avr/lib/avr4/atmega88a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88a/Makefile" ;;
+    "avr/lib/avr4/atmega88p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88p/Makefile" ;;
+    "avr/lib/avr4/atmega88pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88pa/Makefile" ;;
+    "avr/lib/avr4/atmega88pb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88pb/Makefile" ;;
+    "avr/lib/avr4/atmega8515/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8515/Makefile" ;;
+    "avr/lib/avr4/atmega8535/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8535/Makefile" ;;
+    "avr/lib/avr4/atmega8hva/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8hva/Makefile" ;;
+    "avr/lib/avr4/at90pwm1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm1/Makefile" ;;
+    "avr/lib/avr4/at90pwm2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm2/Makefile" ;;
+    "avr/lib/avr4/at90pwm2b/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm2b/Makefile" ;;
+    "avr/lib/avr4/at90pwm3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm3/Makefile" ;;
+    "avr/lib/avr4/at90pwm3b/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm3b/Makefile" ;;
+    "avr/lib/avr4/at90pwm81/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm81/Makefile" ;;
+    "avr/lib/avr5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/Makefile" ;;
+    "avr/lib/avr5/at90can32/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90can32/Makefile" ;;
+    "avr/lib/avr5/at90can64/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90can64/Makefile" ;;
+    "avr/lib/avr5/at90pwm216/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90pwm216/Makefile" ;;
+    "avr/lib/avr5/at90pwm316/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90pwm316/Makefile" ;;
+    "avr/lib/avr5/at90pwm161/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90pwm161/Makefile" ;;
+    "avr/lib/avr5/at90scr100/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90scr100/Makefile" ;;
+    "avr/lib/avr5/at90usb646/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90usb646/Makefile" ;;
+    "avr/lib/avr5/at90usb647/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90usb647/Makefile" ;;
+    "avr/lib/avr5/at94k/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at94k/Makefile" ;;
+    "avr/lib/avr5/ata5702m322/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5702m322/Makefile" ;;
+    "avr/lib/avr5/ata5782/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5782/Makefile" ;;
+    "avr/lib/avr5/ata5790/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5790/Makefile" ;;
+    "avr/lib/avr5/ata5790n/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5790n/Makefile" ;;
+    "avr/lib/avr5/ata5791/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5791/Makefile" ;;
+    "avr/lib/avr5/ata5795/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5795/Makefile" ;;
+    "avr/lib/avr5/ata5831/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5831/Makefile" ;;
+    "avr/lib/avr5/ata6613c/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata6613c/Makefile" ;;
+    "avr/lib/avr5/ata6614q/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata6614q/Makefile" ;;
+    "avr/lib/avr5/ata8210/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata8210/Makefile" ;;
+    "avr/lib/avr5/ata8510/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata8510/Makefile" ;;
+    "avr/lib/avr5/atmega16/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16/Makefile" ;;
+    "avr/lib/avr5/atmega16a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16a/Makefile" ;;
+    "avr/lib/avr5/atmega161/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega161/Makefile" ;;
+    "avr/lib/avr5/atmega162/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega162/Makefile" ;;
+    "avr/lib/avr5/atmega163/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega163/Makefile" ;;
+    "avr/lib/avr5/atmega164a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega164a/Makefile" ;;
+    "avr/lib/avr5/atmega164p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega164p/Makefile" ;;
+    "avr/lib/avr5/atmega164pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega164pa/Makefile" ;;
+    "avr/lib/avr5/atmega165/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165/Makefile" ;;
+    "avr/lib/avr5/atmega165a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165a/Makefile" ;;
+    "avr/lib/avr5/atmega165p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165p/Makefile" ;;
+    "avr/lib/avr5/atmega165pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165pa/Makefile" ;;
+    "avr/lib/avr5/atmega168/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168/Makefile" ;;
+    "avr/lib/avr5/atmega168a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168a/Makefile" ;;
+    "avr/lib/avr5/atmega168p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168p/Makefile" ;;
+    "avr/lib/avr5/atmega168pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168pa/Makefile" ;;
+    "avr/lib/avr5/atmega168pb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168pb/Makefile" ;;
+    "avr/lib/avr5/atmega169/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169/Makefile" ;;
+    "avr/lib/avr5/atmega169a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169a/Makefile" ;;
+    "avr/lib/avr5/atmega169p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169p/Makefile" ;;
+    "avr/lib/avr5/atmega169pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169pa/Makefile" ;;
+    "avr/lib/avr5/atmega16hva/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hva/Makefile" ;;
+    "avr/lib/avr5/atmega16hva2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hva2/Makefile" ;;
+    "avr/lib/avr5/atmega16hvb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hvb/Makefile" ;;
+    "avr/lib/avr5/atmega16hvbrevb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hvbrevb/Makefile" ;;
+    "avr/lib/avr5/atmega16m1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16m1/Makefile" ;;
+    "avr/lib/avr5/atmega16u4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16u4/Makefile" ;;
+    "avr/lib/avr5/atmega32/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32/Makefile" ;;
+    "avr/lib/avr5/atmega32a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32a/Makefile" ;;
+    "avr/lib/avr5/atmega323/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega323/Makefile" ;;
+    "avr/lib/avr5/atmega324a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega324a/Makefile" ;;
+    "avr/lib/avr5/atmega324p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega324p/Makefile" ;;
+    "avr/lib/avr5/atmega324pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega324pa/Makefile" ;;
+    "avr/lib/avr5/atmega325/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325/Makefile" ;;
+    "avr/lib/avr5/atmega325a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325a/Makefile" ;;
+    "avr/lib/avr5/atmega325p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325p/Makefile" ;;
+    "avr/lib/avr5/atmega325pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325pa/Makefile" ;;
+    "avr/lib/avr5/atmega3250/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250/Makefile" ;;
+    "avr/lib/avr5/atmega3250a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250a/Makefile" ;;
+    "avr/lib/avr5/atmega3250p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250p/Makefile" ;;
+    "avr/lib/avr5/atmega3250pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250pa/Makefile" ;;
+    "avr/lib/avr5/atmega328/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega328/Makefile" ;;
+    "avr/lib/avr5/atmega328p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega328p/Makefile" ;;
+    "avr/lib/avr5/atmega329/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329/Makefile" ;;
+    "avr/lib/avr5/atmega329a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329a/Makefile" ;;
+    "avr/lib/avr5/atmega329p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329p/Makefile" ;;
+    "avr/lib/avr5/atmega329pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329pa/Makefile" ;;
+    "avr/lib/avr5/atmega3290/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290/Makefile" ;;
+    "avr/lib/avr5/atmega3290a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290a/Makefile" ;;
+    "avr/lib/avr5/atmega3290p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290p/Makefile" ;;
+    "avr/lib/avr5/atmega3290pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290pa/Makefile" ;;
+    "avr/lib/avr5/atmega32c1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32c1/Makefile" ;;
+    "avr/lib/avr5/atmega32hvb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32hvb/Makefile" ;;
+    "avr/lib/avr5/atmega32hvbrevb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32hvbrevb/Makefile" ;;
+    "avr/lib/avr5/atmega32m1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32m1/Makefile" ;;
+    "avr/lib/avr5/atmega32u4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32u4/Makefile" ;;
+    "avr/lib/avr5/atmega32u6/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32u6/Makefile" ;;
+    "avr/lib/avr5/atmega406/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega406/Makefile" ;;
+    "avr/lib/avr5/atmega64rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64rfr2/Makefile" ;;
+    "avr/lib/avr5/atmega644rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644rfr2/Makefile" ;;
+    "avr/lib/avr5/atmega64/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64/Makefile" ;;
+    "avr/lib/avr5/atmega64a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64a/Makefile" ;;
+    "avr/lib/avr5/atmega640/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega640/Makefile" ;;
+    "avr/lib/avr5/atmega644/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644/Makefile" ;;
+    "avr/lib/avr5/atmega644a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644a/Makefile" ;;
+    "avr/lib/avr5/atmega644p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644p/Makefile" ;;
+    "avr/lib/avr5/atmega644pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644pa/Makefile" ;;
+    "avr/lib/avr5/atmega645/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega645/Makefile" ;;
+    "avr/lib/avr5/atmega645a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega645a/Makefile" ;;
+    "avr/lib/avr5/atmega645p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega645p/Makefile" ;;
+    "avr/lib/avr5/atmega6450/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6450/Makefile" ;;
+    "avr/lib/avr5/atmega6450a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6450a/Makefile" ;;
+    "avr/lib/avr5/atmega6450p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6450p/Makefile" ;;
+    "avr/lib/avr5/atmega649/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega649/Makefile" ;;
+    "avr/lib/avr5/atmega649a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega649a/Makefile" ;;
+    "avr/lib/avr5/atmega649p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega649p/Makefile" ;;
+    "avr/lib/avr5/atmega6490/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6490/Makefile" ;;
+    "avr/lib/avr5/atmega6490a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6490a/Makefile" ;;
+    "avr/lib/avr5/atmega6490p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6490p/Makefile" ;;
+    "avr/lib/avr5/atmega64c1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64c1/Makefile" ;;
+    "avr/lib/avr5/atmega64hve/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64hve/Makefile" ;;
+    "avr/lib/avr5/atmega64hve2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64hve2/Makefile" ;;
+    "avr/lib/avr5/atmega64m1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64m1/Makefile" ;;
+    "avr/lib/avr5/m3000/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/m3000/Makefile" ;;
+    "avr/lib/avr51/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/Makefile" ;;
+    "avr/lib/avr51/atmega128/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega128/Makefile" ;;
+    "avr/lib/avr51/atmega128a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega128a/Makefile" ;;
+    "avr/lib/avr51/atmega1280/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1280/Makefile" ;;
+    "avr/lib/avr51/atmega1281/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1281/Makefile" ;;
+    "avr/lib/avr51/atmega1284/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1284/Makefile" ;;
+    "avr/lib/avr51/atmega1284p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1284p/Makefile" ;;
+    "avr/lib/avr51/atmega128rfa1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega128rfa1/Makefile" ;;
+    "avr/lib/avr51/atmega128rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega128rfr2/Makefile" ;;
+    "avr/lib/avr51/atmega1284rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1284rfr2/Makefile" ;;
+    "avr/lib/avr51/at90can128/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/at90can128/Makefile" ;;
+    "avr/lib/avr51/at90usb1286/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/at90usb1286/Makefile" ;;
+    "avr/lib/avr51/at90usb1287/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/at90usb1287/Makefile" ;;
+    "avr/lib/avr6/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/Makefile" ;;
+    "avr/lib/avr6/atmega2560/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/atmega2560/Makefile" ;;
+    "avr/lib/avr6/atmega2561/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/atmega2561/Makefile" ;;
+    "avr/lib/avr6/atmega256rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/atmega256rfr2/Makefile" ;;
+    "avr/lib/avr6/atmega2564rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/atmega2564rfr2/Makefile" ;;
+    "avr/lib/avrxmega2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega8e5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega8e5/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega16a4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16a4/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega16a4u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16a4u/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega16c4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16c4/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega16d4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16d4/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega16e5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16e5/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega32a4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32a4/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega32a4u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32a4u/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega32c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32c3/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega32c4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32c4/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega32d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32d3/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega32d4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32d4/Makefile" ;;
+    "avr/lib/avrxmega2/atxmega32e5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32e5/Makefile" ;;
+    "avr/lib/avrxmega3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega3/Makefile" ;;
+    "avr/lib/avrxmega3/short-calls/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega3/short-calls/Makefile" ;;
+    "avr/lib/avrxmega4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/Makefile" ;;
+    "avr/lib/avrxmega4/atxmega64a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64a3/Makefile" ;;
+    "avr/lib/avrxmega4/atxmega64a3u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64a3u/Makefile" ;;
+    "avr/lib/avrxmega4/atxmega64a4u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64a4u/Makefile" ;;
+    "avr/lib/avrxmega4/atxmega64b1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64b1/Makefile" ;;
+    "avr/lib/avrxmega4/atxmega64b3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64b3/Makefile" ;;
+    "avr/lib/avrxmega4/atxmega64c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64c3/Makefile" ;;
+    "avr/lib/avrxmega4/atxmega64d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64d3/Makefile" ;;
+    "avr/lib/avrxmega4/atxmega64d4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64d4/Makefile" ;;
+    "avr/lib/avrxmega5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega5/Makefile" ;;
+    "avr/lib/avrxmega5/atxmega64a1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega5/atxmega64a1/Makefile" ;;
+    "avr/lib/avrxmega5/atxmega64a1u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega5/atxmega64a1u/Makefile" ;;
+    "avr/lib/avrxmega6/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega128a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128a3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega128a3u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128a3u/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega128b1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128b1/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega128b3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128b3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega128c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128c3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega128d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128d3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega128d4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128d4/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega192a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega192a3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega192a3u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega192a3u/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega192c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega192c3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega192d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega192d3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega256a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256a3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega256a3u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256a3u/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega256a3b/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256a3b/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega256a3bu/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256a3bu/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega256c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256c3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega256d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256d3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega384c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega384c3/Makefile" ;;
+    "avr/lib/avrxmega6/atxmega384d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega384d3/Makefile" ;;
+    "avr/lib/avrxmega7/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/Makefile" ;;
+    "avr/lib/avrxmega7/atxmega128a1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/atxmega128a1/Makefile" ;;
+    "avr/lib/avrxmega7/atxmega128a1u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/atxmega128a1u/Makefile" ;;
+    "avr/lib/avrxmega7/atxmega128a4u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/atxmega128a4u/Makefile" ;;
+    "avr/lib/avrtiny/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/Makefile" ;;
+    "avr/lib/avrtiny/attiny4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny4/Makefile" ;;
+    "avr/lib/avrtiny/attiny5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny5/Makefile" ;;
+    "avr/lib/avrtiny/attiny9/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny9/Makefile" ;;
+    "avr/lib/avrtiny/attiny10/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny10/Makefile" ;;
+    "avr/lib/avrtiny/attiny20/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny20/Makefile" ;;
+    "avr/lib/avrtiny/attiny40/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny40/Makefile" ;;
+
+  *) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;;
+  esac
+done
+
+
+# If the user did not use the arguments to specify the items to instantiate,
+# then the envvar interface is used.  Set only those that are not.
+# We use the long form for the default assignment because of an extremely
+# bizarre bug on SunOS 4.1.3.
+if $ac_need_defaults; then
+  test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
+  test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
+  test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
+fi
+
+# Have a temporary directory for convenience.  Make it in the build tree
+# simply because there is no reason against having it here, and in addition,
+# creating and moving files from /tmp can sometimes cause problems.
+# Hook for its removal unless debugging.
+# Note that there is a small window in which the directory will not be cleaned:
+# after its creation but before its name has been assigned to `$tmp'.
+$debug ||
+{
+  tmp= ac_tmp=
+  trap 'exit_status=$?
+  : "${ac_tmp:=$tmp}"
+  { test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status
+' 0
+  trap 'as_fn_exit 1' 1 2 13 15
+}
+# Create a (secure) tmp directory for tmp files.
+
+{
+  tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` &&
+  test -d "$tmp"
+}  ||
+{
+  tmp=./conf$$-$RANDOM
+  (umask 077 && mkdir "$tmp")
+} || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5
+ac_tmp=$tmp
+
+# Set up the scripts for CONFIG_FILES section.
+# No need to generate them if there are no CONFIG_FILES.
+# This happens for instance with `./config.status config.h'.
+if test -n "$CONFIG_FILES"; then
+
+
+ac_cr=`echo X | tr X '\015'`
+# On cygwin, bash can eat \r inside `` if the user requested igncr.
+# But we know of no other shell where ac_cr would be empty at this
+# point, so we can use a bashism as a fallback.
+if test "x$ac_cr" = x; then
+  eval ac_cr=\$\'\\r\'
+fi
+ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' </dev/null 2>/dev/null`
+if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then
+  ac_cs_awk_cr='\\r'
+else
+  ac_cs_awk_cr=$ac_cr
+fi
+
+echo 'BEGIN {' >"$ac_tmp/subs1.awk" &&
+_ACEOF
+
+
+{
+  echo "cat >conf$$subs.awk <<_ACEOF" &&
+  echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' &&
+  echo "_ACEOF"
+} >conf$$subs.sh ||
+  as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5
+ac_delim_num=`echo "$ac_subst_vars" | grep -c '^'`
+ac_delim='%!_!# '
+for ac_last_try in false false false false false :; do
+  . ./conf$$subs.sh ||
+    as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5
+
+  ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X`
+  if test $ac_delim_n = $ac_delim_num; then
+    break
+  elif $ac_last_try; then
+    as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5
+  else
+    ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
+  fi
+done
+rm -f conf$$subs.sh
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+cat >>"\$ac_tmp/subs1.awk" <<\\_ACAWK &&
+_ACEOF
+sed -n '
+h
+s/^/S["/; s/!.*/"]=/
+p
+g
+s/^[^!]*!//
+:repl
+t repl
+s/'"$ac_delim"'$//
+t delim
+:nl
+h
+s/\(.\{148\}\)..*/\1/
+t more1
+s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/
+p
+n
+b repl
+:more1
+s/["\\]/\\&/g; s/^/"/; s/$/"\\/
+p
+g
+s/.\{148\}//
+t nl
+:delim
+h
+s/\(.\{148\}\)..*/\1/
+t more2
+s/["\\]/\\&/g; s/^/"/; s/$/"/
+p
+b
+:more2
+s/["\\]/\\&/g; s/^/"/; s/$/"\\/
+p
+g
+s/.\{148\}//
+t delim
+' <conf$$subs.awk | sed '
+/^[^""]/{
+  N
+  s/\n//
+}
+' >>$CONFIG_STATUS || ac_write_fail=1
+rm -f conf$$subs.awk
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+_ACAWK
+cat >>"\$ac_tmp/subs1.awk" <<_ACAWK &&
+  for (key in S) S_is_set[key] = 1
+  FS = ""
+
+}
+{
+  line = $ 0
+  nfields = split(line, field, "@")
+  substed = 0
+  len = length(field[1])
+  for (i = 2; i < nfields; i++) {
+    key = field[i]
+    keylen = length(key)
+    if (S_is_set[key]) {
+      value = S[key]
+      line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3)
+      len += length(value) + length(field[++i])
+      substed = 1
+    } else
+      len += 1 + keylen
+  }
+
+  print line
+}
+
+_ACAWK
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then
+  sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g"
+else
+  cat
+fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \
+  || as_fn_error $? "could not setup config files machinery" "$LINENO" 5
+_ACEOF
+
+# VPATH may cause trouble with some makes, so we remove sole $(srcdir),
+# ${srcdir} and @srcdir@ entries from VPATH if srcdir is ".", strip leading and
+# trailing colons and then remove the whole line if VPATH becomes empty
+# (actually we leave an empty line to preserve line numbers).
+if test "x$srcdir" = x.; then
+  ac_vpsub='/^[	 ]*VPATH[	 ]*=[	 ]*/{
+h
+s///
+s/^/:/
+s/[	 ]*$/:/
+s/:\$(srcdir):/:/g
+s/:\${srcdir}:/:/g
+s/:@srcdir@:/:/g
+s/^:*//
+s/:*$//
+x
+s/\(=[	 ]*\).*/\1/
+G
+s/\n//
+s/^[^=]*=[	 ]*$//
+}'
+fi
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+fi # test -n "$CONFIG_FILES"
+
+# Set up the scripts for CONFIG_HEADERS section.
+# No need to generate them if there are no CONFIG_HEADERS.
+# This happens for instance with `./config.status Makefile'.
+if test -n "$CONFIG_HEADERS"; then
+cat >"$ac_tmp/defines.awk" <<\_ACAWK ||
+BEGIN {
+_ACEOF
+
+# Transform confdefs.h into an awk script `defines.awk', embedded as
+# here-document in config.status, that substitutes the proper values into
+# config.h.in to produce config.h.
+
+# Create a delimiter string that does not exist in confdefs.h, to ease
+# handling of long lines.
+ac_delim='%!_!# '
+for ac_last_try in false false :; do
+  ac_tt=`sed -n "/$ac_delim/p" confdefs.h`
+  if test -z "$ac_tt"; then
+    break
+  elif $ac_last_try; then
+    as_fn_error $? "could not make $CONFIG_HEADERS" "$LINENO" 5
+  else
+    ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
+  fi
+done
+
+# For the awk script, D is an array of macro values keyed by name,
+# likewise P contains macro parameters if any.  Preserve backslash
+# newline sequences.
+
+ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]*
+sed -n '
+s/.\{148\}/&'"$ac_delim"'/g
+t rset
+:rset
+s/^[	 ]*#[	 ]*define[	 ][	 ]*/ /
+t def
+d
+:def
+s/\\$//
+t bsnl
+s/["\\]/\\&/g
+s/^ \('"$ac_word_re"'\)\(([^()]*)\)[	 ]*\(.*\)/P["\1"]="\2"\
+D["\1"]=" \3"/p
+s/^ \('"$ac_word_re"'\)[	 ]*\(.*\)/D["\1"]=" \2"/p
+d
+:bsnl
+s/["\\]/\\&/g
+s/^ \('"$ac_word_re"'\)\(([^()]*)\)[	 ]*\(.*\)/P["\1"]="\2"\
+D["\1"]=" \3\\\\\\n"\\/p
+t cont
+s/^ \('"$ac_word_re"'\)[	 ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p
+t cont
+d
+:cont
+n
+s/.\{148\}/&'"$ac_delim"'/g
+t clear
+:clear
+s/\\$//
+t bsnlc
+s/["\\]/\\&/g; s/^/"/; s/$/"/p
+d
+:bsnlc
+s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p
+b cont
+' <confdefs.h | sed '
+s/'"$ac_delim"'/"\\\
+"/g' >>$CONFIG_STATUS || ac_write_fail=1
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+  for (key in D) D_is_set[key] = 1
+  FS = ""
+}
+/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ {
+  line = \$ 0
+  split(line, arg, " ")
+  if (arg[1] == "#") {
+    defundef = arg[2]
+    mac1 = arg[3]
+  } else {
+    defundef = substr(arg[1], 2)
+    mac1 = arg[2]
+  }
+  split(mac1, mac2, "(") #)
+  macro = mac2[1]
+  prefix = substr(line, 1, index(line, defundef) - 1)
+  if (D_is_set[macro]) {
+    # Preserve the white space surrounding the "#".
+    print prefix "define", macro P[macro] D[macro]
+    next
+  } else {
+    # Replace #undef with comments.  This is necessary, for example,
+    # in the case of _POSIX_SOURCE, which is predefined and required
+    # on some systems where configure will not decide to define it.
+    if (defundef == "undef") {
+      print "/*", prefix defundef, macro, "*/"
+      next
+    }
+  }
+}
+{ print }
+_ACAWK
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+  as_fn_error $? "could not setup config headers machinery" "$LINENO" 5
+fi # test -n "$CONFIG_HEADERS"
+
+
+eval set X "  :F $CONFIG_FILES  :H $CONFIG_HEADERS    :C $CONFIG_COMMANDS"
+shift
+for ac_tag
+do
+  case $ac_tag in
+  :[FHLC]) ac_mode=$ac_tag; continue;;
+  esac
+  case $ac_mode$ac_tag in
+  :[FHL]*:*);;
+  :L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5;;
+  :[FH]-) ac_tag=-:-;;
+  :[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
+  esac
+  ac_save_IFS=$IFS
+  IFS=:
+  set x $ac_tag
+  IFS=$ac_save_IFS
+  shift
+  ac_file=$1
+  shift
+
+  case $ac_mode in
+  :L) ac_source=$1;;
+  :[FH])
+    ac_file_inputs=
+    for ac_f
+    do
+      case $ac_f in
+      -) ac_f="$ac_tmp/stdin";;
+      *) # Look for the file first in the build tree, then in the source tree
+	 # (if the path is not absolute).  The absolute path cannot be DOS-style,
+	 # because $ac_f cannot contain `:'.
+	 test -f "$ac_f" ||
+	   case $ac_f in
+	   [\\/$]*) false;;
+	   *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
+	   esac ||
+	   as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;;
+      esac
+      case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
+      as_fn_append ac_file_inputs " '$ac_f'"
+    done
+
+    # Let's still pretend it is `configure' which instantiates (i.e., don't
+    # use $as_me), people would be surprised to read:
+    #    /* config.h.  Generated by config.status.  */
+    configure_input='Generated from '`
+	  $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g'
+	`' by configure.'
+    if test x"$ac_file" != x-; then
+      configure_input="$ac_file.  $configure_input"
+      { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5
+$as_echo "$as_me: creating $ac_file" >&6;}
+    fi
+    # Neutralize special characters interpreted by sed in replacement strings.
+    case $configure_input in #(
+    *\&* | *\|* | *\\* )
+       ac_sed_conf_input=`$as_echo "$configure_input" |
+       sed 's/[\\\\&|]/\\\\&/g'`;; #(
+    *) ac_sed_conf_input=$configure_input;;
+    esac
+
+    case $ac_tag in
+    *:-:* | *:-) cat >"$ac_tmp/stdin" \
+      || as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;;
+    esac
+    ;;
+  esac
+
+  ac_dir=`$as_dirname -- "$ac_file" ||
+$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$ac_file" : 'X\(//\)[^/]' \| \
+	 X"$ac_file" : 'X\(//\)$' \| \
+	 X"$ac_file" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$ac_file" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+  as_dir="$ac_dir"; as_fn_mkdir_p
+  ac_builddir=.
+
+case "$ac_dir" in
+.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
+*)
+  ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
+  # A ".." for each directory in $ac_dir_suffix.
+  ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
+  case $ac_top_builddir_sub in
+  "") ac_top_builddir_sub=. ac_top_build_prefix= ;;
+  *)  ac_top_build_prefix=$ac_top_builddir_sub/ ;;
+  esac ;;
+esac
+ac_abs_top_builddir=$ac_pwd
+ac_abs_builddir=$ac_pwd$ac_dir_suffix
+# for backward compatibility:
+ac_top_builddir=$ac_top_build_prefix
+
+case $srcdir in
+  .)  # We are building in place.
+    ac_srcdir=.
+    ac_top_srcdir=$ac_top_builddir_sub
+    ac_abs_top_srcdir=$ac_pwd ;;
+  [\\/]* | ?:[\\/]* )  # Absolute name.
+    ac_srcdir=$srcdir$ac_dir_suffix;
+    ac_top_srcdir=$srcdir
+    ac_abs_top_srcdir=$srcdir ;;
+  *) # Relative name.
+    ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
+    ac_top_srcdir=$ac_top_build_prefix$srcdir
+    ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
+esac
+ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
+
+
+  case $ac_mode in
+  :F)
+  #
+  # CONFIG_FILE
+  #
+
+  case $INSTALL in
+  [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
+  *) ac_INSTALL=$ac_top_build_prefix$INSTALL ;;
+  esac
+  ac_MKDIR_P=$MKDIR_P
+  case $MKDIR_P in
+  [\\/$]* | ?:[\\/]* ) ;;
+  */*) ac_MKDIR_P=$ac_top_build_prefix$MKDIR_P ;;
+  esac
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# If the template does not know about datarootdir, expand it.
+# FIXME: This hack should be removed a few years after 2.60.
+ac_datarootdir_hack=; ac_datarootdir_seen=
+ac_sed_dataroot='
+/datarootdir/ {
+  p
+  q
+}
+/@datadir@/p
+/@docdir@/p
+/@infodir@/p
+/@localedir@/p
+/@mandir@/p'
+case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in
+*datarootdir*) ac_datarootdir_seen=yes;;
+*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*)
+  { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5
+$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;}
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+  ac_datarootdir_hack='
+  s&@datadir@&$datadir&g
+  s&@docdir@&$docdir&g
+  s&@infodir@&$infodir&g
+  s&@localedir@&$localedir&g
+  s&@mandir@&$mandir&g
+  s&\\\${datarootdir}&$datarootdir&g' ;;
+esac
+_ACEOF
+
+# Neutralize VPATH when `$srcdir' = `.'.
+# Shell code in configure.ac might set extrasub.
+# FIXME: do we really want to maintain this feature?
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ac_sed_extra="$ac_vpsub
+$extrasub
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+:t
+/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
+s|@configure_input@|$ac_sed_conf_input|;t t
+s&@top_builddir@&$ac_top_builddir_sub&;t t
+s&@top_build_prefix@&$ac_top_build_prefix&;t t
+s&@srcdir@&$ac_srcdir&;t t
+s&@abs_srcdir@&$ac_abs_srcdir&;t t
+s&@top_srcdir@&$ac_top_srcdir&;t t
+s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t
+s&@builddir@&$ac_builddir&;t t
+s&@abs_builddir@&$ac_abs_builddir&;t t
+s&@abs_top_builddir@&$ac_abs_top_builddir&;t t
+s&@INSTALL@&$ac_INSTALL&;t t
+s&@MKDIR_P@&$ac_MKDIR_P&;t t
+$ac_datarootdir_hack
+"
+eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$ac_tmp/subs.awk" \
+  >$ac_tmp/out || as_fn_error $? "could not create $ac_file" "$LINENO" 5
+
+test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
+  { ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } &&
+  { ac_out=`sed -n '/^[	 ]*datarootdir[	 ]*:*=/p' \
+      "$ac_tmp/out"`; test -z "$ac_out"; } &&
+  { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir'
+which seems to be undefined.  Please make sure it is defined" >&5
+$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir'
+which seems to be undefined.  Please make sure it is defined" >&2;}
+
+  rm -f "$ac_tmp/stdin"
+  case $ac_file in
+  -) cat "$ac_tmp/out" && rm -f "$ac_tmp/out";;
+  *) rm -f "$ac_file" && mv "$ac_tmp/out" "$ac_file";;
+  esac \
+  || as_fn_error $? "could not create $ac_file" "$LINENO" 5
+ ;;
+  :H)
+  #
+  # CONFIG_HEADER
+  #
+  if test x"$ac_file" != x-; then
+    {
+      $as_echo "/* $configure_input  */" \
+      && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs"
+    } >"$ac_tmp/config.h" \
+      || as_fn_error $? "could not create $ac_file" "$LINENO" 5
+    if diff "$ac_file" "$ac_tmp/config.h" >/dev/null 2>&1; then
+      { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5
+$as_echo "$as_me: $ac_file is unchanged" >&6;}
+    else
+      rm -f "$ac_file"
+      mv "$ac_tmp/config.h" "$ac_file" \
+	|| as_fn_error $? "could not create $ac_file" "$LINENO" 5
+    fi
+  else
+    $as_echo "/* $configure_input  */" \
+      && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" \
+      || as_fn_error $? "could not create -" "$LINENO" 5
+  fi
+# Compute "$ac_file"'s index in $config_headers.
+_am_arg="$ac_file"
+_am_stamp_count=1
+for _am_header in $config_headers :; do
+  case $_am_header in
+    $_am_arg | $_am_arg:* )
+      break ;;
+    * )
+      _am_stamp_count=`expr $_am_stamp_count + 1` ;;
+  esac
+done
+echo "timestamp for $_am_arg" >`$as_dirname -- "$_am_arg" ||
+$as_expr X"$_am_arg" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$_am_arg" : 'X\(//\)[^/]' \| \
+	 X"$_am_arg" : 'X\(//\)$' \| \
+	 X"$_am_arg" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$_am_arg" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`/stamp-h$_am_stamp_count
+ ;;
+
+  :C)  { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5
+$as_echo "$as_me: executing $ac_file commands" >&6;}
+ ;;
+  esac
+
+
+  case $ac_file$ac_mode in
+    "depfiles":C) test x"$AMDEP_TRUE" != x"" || {
+  # Older Autoconf quotes --file arguments for eval, but not when files
+  # are listed without --file.  Let's play safe and only enable the eval
+  # if we detect the quoting.
+  case $CONFIG_FILES in
+  *\'*) eval set x "$CONFIG_FILES" ;;
+  *)   set x $CONFIG_FILES ;;
+  esac
+  shift
+  for mf
+  do
+    # Strip MF so we end up with the name of the file.
+    mf=`echo "$mf" | sed -e 's/:.*$//'`
+    # Check whether this is an Automake generated Makefile or not.
+    # We used to match only the files named 'Makefile.in', but
+    # some people rename them; so instead we look at the file content.
+    # Grep'ing the first line is not enough: some people post-process
+    # each Makefile.in and add a new line on top of each file to say so.
+    # Grep'ing the whole file is not good either: AIX grep has a line
+    # limit of 2048, but all sed's we know have understand at least 4000.
+    if sed -n 's,^#.*generated by automake.*,X,p' "$mf" | grep X >/dev/null 2>&1; then
+      dirpart=`$as_dirname -- "$mf" ||
+$as_expr X"$mf" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$mf" : 'X\(//\)[^/]' \| \
+	 X"$mf" : 'X\(//\)$' \| \
+	 X"$mf" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$mf" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+    else
+      continue
+    fi
+    # Extract the definition of DEPDIR, am__include, and am__quote
+    # from the Makefile without running 'make'.
+    DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"`
+    test -z "$DEPDIR" && continue
+    am__include=`sed -n 's/^am__include = //p' < "$mf"`
+    test -z "$am__include" && continue
+    am__quote=`sed -n 's/^am__quote = //p' < "$mf"`
+    # Find all dependency output files, they are included files with
+    # $(DEPDIR) in their names.  We invoke sed twice because it is the
+    # simplest approach to changing $(DEPDIR) to its actual value in the
+    # expansion.
+    for file in `sed -n "
+      s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \
+	 sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g'`; do
+      # Make sure the directory exists.
+      test -f "$dirpart/$file" && continue
+      fdir=`$as_dirname -- "$file" ||
+$as_expr X"$file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$file" : 'X\(//\)[^/]' \| \
+	 X"$file" : 'X\(//\)$' \| \
+	 X"$file" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$file" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+      as_dir=$dirpart/$fdir; as_fn_mkdir_p
+      # echo "creating $dirpart/$file"
+      echo '# dummy' > "$dirpart/$file"
+    done
+  done
+}
+ ;;
+
+  esac
+done # for ac_tag
+
+
+as_fn_exit 0
+_ACEOF
+ac_clean_files=$ac_clean_files_save
+
+test $ac_write_fail = 0 ||
+  as_fn_error $? "write failure creating $CONFIG_STATUS" "$LINENO" 5
+
+
+# configure is writing to config.log, and then calls config.status.
+# config.status does its own redirection, appending to config.log.
+# Unfortunately, on DOS this fails, as config.log is still kept open
+# by configure, so config.status won't be able to write to it; its
+# output is simply discarded.  So we exec the FD to /dev/null,
+# effectively closing config.log, so it can be properly (re)opened and
+# appended to by config.status.  When coming back to configure, we
+# need to make the FD available again.
+if test "$no_create" != yes; then
+  ac_cs_success=:
+  ac_config_status_args=
+  test "$silent" = yes &&
+    ac_config_status_args="$ac_config_status_args --quiet"
+  exec 5>/dev/null
+  $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
+  exec 5>>config.log
+  # Use ||, not &&, to avoid exiting from the if with $? = 1, which
+  # would make configure fail if this is the last instruction.
+  $ac_cs_success || as_fn_exit 1
+fi
+if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5
+$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;}
+fi
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/depcomp
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/depcomp
@@ -0,0 +1,791 @@
+#! /bin/sh
+# depcomp - compile a program generating dependencies as side-effects
+
+scriptversion=2013-05-30.07; # UTC
+
+# Copyright (C) 1999-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# As a special exception to the GNU General Public License, if you
+# distribute this file as part of a program that contains a
+# configuration script generated by Autoconf, you may include it under
+# the same distribution terms that you use for the rest of that program.
+
+# Originally written by Alexandre Oliva <oliva@dcc.unicamp.br>.
+
+case $1 in
+  '')
+    echo "$0: No command.  Try '$0 --help' for more information." 1>&2
+    exit 1;
+    ;;
+  -h | --h*)
+    cat <<\EOF
+Usage: depcomp [--help] [--version] PROGRAM [ARGS]
+
+Run PROGRAMS ARGS to compile a file, generating dependencies
+as side-effects.
+
+Environment variables:
+  depmode     Dependency tracking mode.
+  source      Source file read by 'PROGRAMS ARGS'.
+  object      Object file output by 'PROGRAMS ARGS'.
+  DEPDIR      directory where to store dependencies.
+  depfile     Dependency file to output.
+  tmpdepfile  Temporary file to use when outputting dependencies.
+  libtool     Whether libtool is used (yes/no).
+
+Report bugs to <bug-automake@gnu.org>.
+EOF
+    exit $?
+    ;;
+  -v | --v*)
+    echo "depcomp $scriptversion"
+    exit $?
+    ;;
+esac
+
+# Get the directory component of the given path, and save it in the
+# global variables '$dir'.  Note that this directory component will
+# be either empty or ending with a '/' character.  This is deliberate.
+set_dir_from ()
+{
+  case $1 in
+    */*) dir=`echo "$1" | sed -e 's|/[^/]*$|/|'`;;
+      *) dir=;;
+  esac
+}
+
+# Get the suffix-stripped basename of the given path, and save it the
+# global variable '$base'.
+set_base_from ()
+{
+  base=`echo "$1" | sed -e 's|^.*/||' -e 's/\.[^.]*$//'`
+}
+
+# If no dependency file was actually created by the compiler invocation,
+# we still have to create a dummy depfile, to avoid errors with the
+# Makefile "include basename.Plo" scheme.
+make_dummy_depfile ()
+{
+  echo "#dummy" > "$depfile"
+}
+
+# Factor out some common post-processing of the generated depfile.
+# Requires the auxiliary global variable '$tmpdepfile' to be set.
+aix_post_process_depfile ()
+{
+  # If the compiler actually managed to produce a dependency file,
+  # post-process it.
+  if test -f "$tmpdepfile"; then
+    # Each line is of the form 'foo.o: dependency.h'.
+    # Do two passes, one to just change these to
+    #   $object: dependency.h
+    # and one to simply output
+    #   dependency.h:
+    # which is needed to avoid the deleted-header problem.
+    { sed -e "s,^.*\.[$lower]*:,$object:," < "$tmpdepfile"
+      sed -e "s,^.*\.[$lower]*:[$tab ]*,," -e 's,$,:,' < "$tmpdepfile"
+    } > "$depfile"
+    rm -f "$tmpdepfile"
+  else
+    make_dummy_depfile
+  fi
+}
+
+# A tabulation character.
+tab='	'
+# A newline character.
+nl='
+'
+# Character ranges might be problematic outside the C locale.
+# These definitions help.
+upper=ABCDEFGHIJKLMNOPQRSTUVWXYZ
+lower=abcdefghijklmnopqrstuvwxyz
+digits=0123456789
+alpha=${upper}${lower}
+
+if test -z "$depmode" || test -z "$source" || test -z "$object"; then
+  echo "depcomp: Variables source, object and depmode must be set" 1>&2
+  exit 1
+fi
+
+# Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po.
+depfile=${depfile-`echo "$object" |
+  sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`}
+tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`}
+
+rm -f "$tmpdepfile"
+
+# Avoid interferences from the environment.
+gccflag= dashmflag=
+
+# Some modes work just like other modes, but use different flags.  We
+# parameterize here, but still list the modes in the big case below,
+# to make depend.m4 easier to write.  Note that we *cannot* use a case
+# here, because this file can only contain one case statement.
+if test "$depmode" = hp; then
+  # HP compiler uses -M and no extra arg.
+  gccflag=-M
+  depmode=gcc
+fi
+
+if test "$depmode" = dashXmstdout; then
+  # This is just like dashmstdout with a different argument.
+  dashmflag=-xM
+  depmode=dashmstdout
+fi
+
+cygpath_u="cygpath -u -f -"
+if test "$depmode" = msvcmsys; then
+  # This is just like msvisualcpp but w/o cygpath translation.
+  # Just convert the backslash-escaped backslashes to single forward
+  # slashes to satisfy depend.m4
+  cygpath_u='sed s,\\\\,/,g'
+  depmode=msvisualcpp
+fi
+
+if test "$depmode" = msvc7msys; then
+  # This is just like msvc7 but w/o cygpath translation.
+  # Just convert the backslash-escaped backslashes to single forward
+  # slashes to satisfy depend.m4
+  cygpath_u='sed s,\\\\,/,g'
+  depmode=msvc7
+fi
+
+if test "$depmode" = xlc; then
+  # IBM C/C++ Compilers xlc/xlC can output gcc-like dependency information.
+  gccflag=-qmakedep=gcc,-MF
+  depmode=gcc
+fi
+
+case "$depmode" in
+gcc3)
+## gcc 3 implements dependency tracking that does exactly what
+## we want.  Yay!  Note: for some reason libtool 1.4 doesn't like
+## it if -MD -MP comes after the -MF stuff.  Hmm.
+## Unfortunately, FreeBSD c89 acceptance of flags depends upon
+## the command line argument order; so add the flags where they
+## appear in depend2.am.  Note that the slowdown incurred here
+## affects only configure: in makefiles, %FASTDEP% shortcuts this.
+  for arg
+  do
+    case $arg in
+    -c) set fnord "$@" -MT "$object" -MD -MP -MF "$tmpdepfile" "$arg" ;;
+    *)  set fnord "$@" "$arg" ;;
+    esac
+    shift # fnord
+    shift # $arg
+  done
+  "$@"
+  stat=$?
+  if test $stat -ne 0; then
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+  mv "$tmpdepfile" "$depfile"
+  ;;
+
+gcc)
+## Note that this doesn't just cater to obsosete pre-3.x GCC compilers.
+## but also to in-use compilers like IMB xlc/xlC and the HP C compiler.
+## (see the conditional assignment to $gccflag above).
+## There are various ways to get dependency output from gcc.  Here's
+## why we pick this rather obscure method:
+## - Don't want to use -MD because we'd like the dependencies to end
+##   up in a subdir.  Having to rename by hand is ugly.
+##   (We might end up doing this anyway to support other compilers.)
+## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like
+##   -MM, not -M (despite what the docs say).  Also, it might not be
+##   supported by the other compilers which use the 'gcc' depmode.
+## - Using -M directly means running the compiler twice (even worse
+##   than renaming).
+  if test -z "$gccflag"; then
+    gccflag=-MD,
+  fi
+  "$@" -Wp,"$gccflag$tmpdepfile"
+  stat=$?
+  if test $stat -ne 0; then
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+  rm -f "$depfile"
+  echo "$object : \\" > "$depfile"
+  # The second -e expression handles DOS-style file names with drive
+  # letters.
+  sed -e 's/^[^:]*: / /' \
+      -e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile"
+## This next piece of magic avoids the "deleted header file" problem.
+## The problem is that when a header file which appears in a .P file
+## is deleted, the dependency causes make to die (because there is
+## typically no way to rebuild the header).  We avoid this by adding
+## dummy dependencies for each header file.  Too bad gcc doesn't do
+## this for us directly.
+## Some versions of gcc put a space before the ':'.  On the theory
+## that the space means something, we add a space to the output as
+## well.  hp depmode also adds that space, but also prefixes the VPATH
+## to the object.  Take care to not repeat it in the output.
+## Some versions of the HPUX 10.20 sed can't process this invocation
+## correctly.  Breaking it into two sed invocations is a workaround.
+  tr ' ' "$nl" < "$tmpdepfile" \
+    | sed -e 's/^\\$//' -e '/^$/d' -e "s|.*$object$||" -e '/:$/d' \
+    | sed -e 's/$/ :/' >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+hp)
+  # This case exists only to let depend.m4 do its work.  It works by
+  # looking at the text of this script.  This case will never be run,
+  # since it is checked for above.
+  exit 1
+  ;;
+
+sgi)
+  if test "$libtool" = yes; then
+    "$@" "-Wp,-MDupdate,$tmpdepfile"
+  else
+    "$@" -MDupdate "$tmpdepfile"
+  fi
+  stat=$?
+  if test $stat -ne 0; then
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+  rm -f "$depfile"
+
+  if test -f "$tmpdepfile"; then  # yes, the sourcefile depend on other files
+    echo "$object : \\" > "$depfile"
+    # Clip off the initial element (the dependent).  Don't try to be
+    # clever and replace this with sed code, as IRIX sed won't handle
+    # lines with more than a fixed number of characters (4096 in
+    # IRIX 6.2 sed, 8192 in IRIX 6.5).  We also remove comment lines;
+    # the IRIX cc adds comments like '#:fec' to the end of the
+    # dependency line.
+    tr ' ' "$nl" < "$tmpdepfile" \
+      | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' \
+      | tr "$nl" ' ' >> "$depfile"
+    echo >> "$depfile"
+    # The second pass generates a dummy entry for each header file.
+    tr ' ' "$nl" < "$tmpdepfile" \
+      | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' -e 's/$/:/' \
+      >> "$depfile"
+  else
+    make_dummy_depfile
+  fi
+  rm -f "$tmpdepfile"
+  ;;
+
+xlc)
+  # This case exists only to let depend.m4 do its work.  It works by
+  # looking at the text of this script.  This case will never be run,
+  # since it is checked for above.
+  exit 1
+  ;;
+
+aix)
+  # The C for AIX Compiler uses -M and outputs the dependencies
+  # in a .u file.  In older versions, this file always lives in the
+  # current directory.  Also, the AIX compiler puts '$object:' at the
+  # start of each line; $object doesn't have directory information.
+  # Version 6 uses the directory in both cases.
+  set_dir_from "$object"
+  set_base_from "$object"
+  if test "$libtool" = yes; then
+    tmpdepfile1=$dir$base.u
+    tmpdepfile2=$base.u
+    tmpdepfile3=$dir.libs/$base.u
+    "$@" -Wc,-M
+  else
+    tmpdepfile1=$dir$base.u
+    tmpdepfile2=$dir$base.u
+    tmpdepfile3=$dir$base.u
+    "$@" -M
+  fi
+  stat=$?
+  if test $stat -ne 0; then
+    rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3"
+    exit $stat
+  fi
+
+  for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3"
+  do
+    test -f "$tmpdepfile" && break
+  done
+  aix_post_process_depfile
+  ;;
+
+tcc)
+  # tcc (Tiny C Compiler) understand '-MD -MF file' since version 0.9.26
+  # FIXME: That version still under development at the moment of writing.
+  #        Make that this statement remains true also for stable, released
+  #        versions.
+  # It will wrap lines (doesn't matter whether long or short) with a
+  # trailing '\', as in:
+  #
+  #   foo.o : \
+  #    foo.c \
+  #    foo.h \
+  #
+  # It will put a trailing '\' even on the last line, and will use leading
+  # spaces rather than leading tabs (at least since its commit 0394caf7
+  # "Emit spaces for -MD").
+  "$@" -MD -MF "$tmpdepfile"
+  stat=$?
+  if test $stat -ne 0; then
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+  rm -f "$depfile"
+  # Each non-empty line is of the form 'foo.o : \' or ' dep.h \'.
+  # We have to change lines of the first kind to '$object: \'.
+  sed -e "s|.*:|$object :|" < "$tmpdepfile" > "$depfile"
+  # And for each line of the second kind, we have to emit a 'dep.h:'
+  # dummy dependency, to avoid the deleted-header problem.
+  sed -n -e 's|^  *\(.*\) *\\$|\1:|p' < "$tmpdepfile" >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+## The order of this option in the case statement is important, since the
+## shell code in configure will try each of these formats in the order
+## listed in this file.  A plain '-MD' option would be understood by many
+## compilers, so we must ensure this comes after the gcc and icc options.
+pgcc)
+  # Portland's C compiler understands '-MD'.
+  # Will always output deps to 'file.d' where file is the root name of the
+  # source file under compilation, even if file resides in a subdirectory.
+  # The object file name does not affect the name of the '.d' file.
+  # pgcc 10.2 will output
+  #    foo.o: sub/foo.c sub/foo.h
+  # and will wrap long lines using '\' :
+  #    foo.o: sub/foo.c ... \
+  #     sub/foo.h ... \
+  #     ...
+  set_dir_from "$object"
+  # Use the source, not the object, to determine the base name, since
+  # that's sadly what pgcc will do too.
+  set_base_from "$source"
+  tmpdepfile=$base.d
+
+  # For projects that build the same source file twice into different object
+  # files, the pgcc approach of using the *source* file root name can cause
+  # problems in parallel builds.  Use a locking strategy to avoid stomping on
+  # the same $tmpdepfile.
+  lockdir=$base.d-lock
+  trap "
+    echo '$0: caught signal, cleaning up...' >&2
+    rmdir '$lockdir'
+    exit 1
+  " 1 2 13 15
+  numtries=100
+  i=$numtries
+  while test $i -gt 0; do
+    # mkdir is a portable test-and-set.
+    if mkdir "$lockdir" 2>/dev/null; then
+      # This process acquired the lock.
+      "$@" -MD
+      stat=$?
+      # Release the lock.
+      rmdir "$lockdir"
+      break
+    else
+      # If the lock is being held by a different process, wait
+      # until the winning process is done or we timeout.
+      while test -d "$lockdir" && test $i -gt 0; do
+        sleep 1
+        i=`expr $i - 1`
+      done
+    fi
+    i=`expr $i - 1`
+  done
+  trap - 1 2 13 15
+  if test $i -le 0; then
+    echo "$0: failed to acquire lock after $numtries attempts" >&2
+    echo "$0: check lockdir '$lockdir'" >&2
+    exit 1
+  fi
+
+  if test $stat -ne 0; then
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+  rm -f "$depfile"
+  # Each line is of the form `foo.o: dependent.h',
+  # or `foo.o: dep1.h dep2.h \', or ` dep3.h dep4.h \'.
+  # Do two passes, one to just change these to
+  # `$object: dependent.h' and one to simply `dependent.h:'.
+  sed "s,^[^:]*:,$object :," < "$tmpdepfile" > "$depfile"
+  # Some versions of the HPUX 10.20 sed can't process this invocation
+  # correctly.  Breaking it into two sed invocations is a workaround.
+  sed 's,^[^:]*: \(.*\)$,\1,;s/^\\$//;/^$/d;/:$/d' < "$tmpdepfile" \
+    | sed -e 's/$/ :/' >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+hp2)
+  # The "hp" stanza above does not work with aCC (C++) and HP's ia64
+  # compilers, which have integrated preprocessors.  The correct option
+  # to use with these is +Maked; it writes dependencies to a file named
+  # 'foo.d', which lands next to the object file, wherever that
+  # happens to be.
+  # Much of this is similar to the tru64 case; see comments there.
+  set_dir_from  "$object"
+  set_base_from "$object"
+  if test "$libtool" = yes; then
+    tmpdepfile1=$dir$base.d
+    tmpdepfile2=$dir.libs/$base.d
+    "$@" -Wc,+Maked
+  else
+    tmpdepfile1=$dir$base.d
+    tmpdepfile2=$dir$base.d
+    "$@" +Maked
+  fi
+  stat=$?
+  if test $stat -ne 0; then
+     rm -f "$tmpdepfile1" "$tmpdepfile2"
+     exit $stat
+  fi
+
+  for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2"
+  do
+    test -f "$tmpdepfile" && break
+  done
+  if test -f "$tmpdepfile"; then
+    sed -e "s,^.*\.[$lower]*:,$object:," "$tmpdepfile" > "$depfile"
+    # Add 'dependent.h:' lines.
+    sed -ne '2,${
+               s/^ *//
+               s/ \\*$//
+               s/$/:/
+               p
+             }' "$tmpdepfile" >> "$depfile"
+  else
+    make_dummy_depfile
+  fi
+  rm -f "$tmpdepfile" "$tmpdepfile2"
+  ;;
+
+tru64)
+  # The Tru64 compiler uses -MD to generate dependencies as a side
+  # effect.  'cc -MD -o foo.o ...' puts the dependencies into 'foo.o.d'.
+  # At least on Alpha/Redhat 6.1, Compaq CCC V6.2-504 seems to put
+  # dependencies in 'foo.d' instead, so we check for that too.
+  # Subdirectories are respected.
+  set_dir_from  "$object"
+  set_base_from "$object"
+
+  if test "$libtool" = yes; then
+    # Libtool generates 2 separate objects for the 2 libraries.  These
+    # two compilations output dependencies in $dir.libs/$base.o.d and
+    # in $dir$base.o.d.  We have to check for both files, because
+    # one of the two compilations can be disabled.  We should prefer
+    # $dir$base.o.d over $dir.libs/$base.o.d because the latter is
+    # automatically cleaned when .libs/ is deleted, while ignoring
+    # the former would cause a distcleancheck panic.
+    tmpdepfile1=$dir$base.o.d          # libtool 1.5
+    tmpdepfile2=$dir.libs/$base.o.d    # Likewise.
+    tmpdepfile3=$dir.libs/$base.d      # Compaq CCC V6.2-504
+    "$@" -Wc,-MD
+  else
+    tmpdepfile1=$dir$base.d
+    tmpdepfile2=$dir$base.d
+    tmpdepfile3=$dir$base.d
+    "$@" -MD
+  fi
+
+  stat=$?
+  if test $stat -ne 0; then
+    rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3"
+    exit $stat
+  fi
+
+  for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3"
+  do
+    test -f "$tmpdepfile" && break
+  done
+  # Same post-processing that is required for AIX mode.
+  aix_post_process_depfile
+  ;;
+
+msvc7)
+  if test "$libtool" = yes; then
+    showIncludes=-Wc,-showIncludes
+  else
+    showIncludes=-showIncludes
+  fi
+  "$@" $showIncludes > "$tmpdepfile"
+  stat=$?
+  grep -v '^Note: including file: ' "$tmpdepfile"
+  if test $stat -ne 0; then
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+  rm -f "$depfile"
+  echo "$object : \\" > "$depfile"
+  # The first sed program below extracts the file names and escapes
+  # backslashes for cygpath.  The second sed program outputs the file
+  # name when reading, but also accumulates all include files in the
+  # hold buffer in order to output them again at the end.  This only
+  # works with sed implementations that can handle large buffers.
+  sed < "$tmpdepfile" -n '
+/^Note: including file:  *\(.*\)/ {
+  s//\1/
+  s/\\/\\\\/g
+  p
+}' | $cygpath_u | sort -u | sed -n '
+s/ /\\ /g
+s/\(.*\)/'"$tab"'\1 \\/p
+s/.\(.*\) \\/\1:/
+H
+$ {
+  s/.*/'"$tab"'/
+  G
+  p
+}' >> "$depfile"
+  echo >> "$depfile" # make sure the fragment doesn't end with a backslash
+  rm -f "$tmpdepfile"
+  ;;
+
+msvc7msys)
+  # This case exists only to let depend.m4 do its work.  It works by
+  # looking at the text of this script.  This case will never be run,
+  # since it is checked for above.
+  exit 1
+  ;;
+
+#nosideeffect)
+  # This comment above is used by automake to tell side-effect
+  # dependency tracking mechanisms from slower ones.
+
+dashmstdout)
+  # Important note: in order to support this mode, a compiler *must*
+  # always write the preprocessed file to stdout, regardless of -o.
+  "$@" || exit $?
+
+  # Remove the call to Libtool.
+  if test "$libtool" = yes; then
+    while test "X$1" != 'X--mode=compile'; do
+      shift
+    done
+    shift
+  fi
+
+  # Remove '-o $object'.
+  IFS=" "
+  for arg
+  do
+    case $arg in
+    -o)
+      shift
+      ;;
+    $object)
+      shift
+      ;;
+    *)
+      set fnord "$@" "$arg"
+      shift # fnord
+      shift # $arg
+      ;;
+    esac
+  done
+
+  test -z "$dashmflag" && dashmflag=-M
+  # Require at least two characters before searching for ':'
+  # in the target name.  This is to cope with DOS-style filenames:
+  # a dependency such as 'c:/foo/bar' could be seen as target 'c' otherwise.
+  "$@" $dashmflag |
+    sed "s|^[$tab ]*[^:$tab ][^:][^:]*:[$tab ]*|$object: |" > "$tmpdepfile"
+  rm -f "$depfile"
+  cat < "$tmpdepfile" > "$depfile"
+  # Some versions of the HPUX 10.20 sed can't process this sed invocation
+  # correctly.  Breaking it into two sed invocations is a workaround.
+  tr ' ' "$nl" < "$tmpdepfile" \
+    | sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' \
+    | sed -e 's/$/ :/' >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+dashXmstdout)
+  # This case only exists to satisfy depend.m4.  It is never actually
+  # run, as this mode is specially recognized in the preamble.
+  exit 1
+  ;;
+
+makedepend)
+  "$@" || exit $?
+  # Remove any Libtool call
+  if test "$libtool" = yes; then
+    while test "X$1" != 'X--mode=compile'; do
+      shift
+    done
+    shift
+  fi
+  # X makedepend
+  shift
+  cleared=no eat=no
+  for arg
+  do
+    case $cleared in
+    no)
+      set ""; shift
+      cleared=yes ;;
+    esac
+    if test $eat = yes; then
+      eat=no
+      continue
+    fi
+    case "$arg" in
+    -D*|-I*)
+      set fnord "$@" "$arg"; shift ;;
+    # Strip any option that makedepend may not understand.  Remove
+    # the object too, otherwise makedepend will parse it as a source file.
+    -arch)
+      eat=yes ;;
+    -*|$object)
+      ;;
+    *)
+      set fnord "$@" "$arg"; shift ;;
+    esac
+  done
+  obj_suffix=`echo "$object" | sed 's/^.*\././'`
+  touch "$tmpdepfile"
+  ${MAKEDEPEND-makedepend} -o"$obj_suffix" -f"$tmpdepfile" "$@"
+  rm -f "$depfile"
+  # makedepend may prepend the VPATH from the source file name to the object.
+  # No need to regex-escape $object, excess matching of '.' is harmless.
+  sed "s|^.*\($object *:\)|\1|" "$tmpdepfile" > "$depfile"
+  # Some versions of the HPUX 10.20 sed can't process the last invocation
+  # correctly.  Breaking it into two sed invocations is a workaround.
+  sed '1,2d' "$tmpdepfile" \
+    | tr ' ' "$nl" \
+    | sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' \
+    | sed -e 's/$/ :/' >> "$depfile"
+  rm -f "$tmpdepfile" "$tmpdepfile".bak
+  ;;
+
+cpp)
+  # Important note: in order to support this mode, a compiler *must*
+  # always write the preprocessed file to stdout.
+  "$@" || exit $?
+
+  # Remove the call to Libtool.
+  if test "$libtool" = yes; then
+    while test "X$1" != 'X--mode=compile'; do
+      shift
+    done
+    shift
+  fi
+
+  # Remove '-o $object'.
+  IFS=" "
+  for arg
+  do
+    case $arg in
+    -o)
+      shift
+      ;;
+    $object)
+      shift
+      ;;
+    *)
+      set fnord "$@" "$arg"
+      shift # fnord
+      shift # $arg
+      ;;
+    esac
+  done
+
+  "$@" -E \
+    | sed -n -e '/^# [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \
+             -e '/^#line [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \
+    | sed '$ s: \\$::' > "$tmpdepfile"
+  rm -f "$depfile"
+  echo "$object : \\" > "$depfile"
+  cat < "$tmpdepfile" >> "$depfile"
+  sed < "$tmpdepfile" '/^$/d;s/^ //;s/ \\$//;s/$/ :/' >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+msvisualcpp)
+  # Important note: in order to support this mode, a compiler *must*
+  # always write the preprocessed file to stdout.
+  "$@" || exit $?
+
+  # Remove the call to Libtool.
+  if test "$libtool" = yes; then
+    while test "X$1" != 'X--mode=compile'; do
+      shift
+    done
+    shift
+  fi
+
+  IFS=" "
+  for arg
+  do
+    case "$arg" in
+    -o)
+      shift
+      ;;
+    $object)
+      shift
+      ;;
+    "-Gm"|"/Gm"|"-Gi"|"/Gi"|"-ZI"|"/ZI")
+        set fnord "$@"
+        shift
+        shift
+        ;;
+    *)
+        set fnord "$@" "$arg"
+        shift
+        shift
+        ;;
+    esac
+  done
+  "$@" -E 2>/dev/null |
+  sed -n '/^#line [0-9][0-9]* "\([^"]*\)"/ s::\1:p' | $cygpath_u | sort -u > "$tmpdepfile"
+  rm -f "$depfile"
+  echo "$object : \\" > "$depfile"
+  sed < "$tmpdepfile" -n -e 's% %\\ %g' -e '/^\(.*\)$/ s::'"$tab"'\1 \\:p' >> "$depfile"
+  echo "$tab" >> "$depfile"
+  sed < "$tmpdepfile" -n -e 's% %\\ %g' -e '/^\(.*\)$/ s::\1\::p' >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+msvcmsys)
+  # This case exists only to let depend.m4 do its work.  It works by
+  # looking at the text of this script.  This case will never be run,
+  # since it is checked for above.
+  exit 1
+  ;;
+
+none)
+  exec "$@"
+  ;;
+
+*)
+  echo "Unknown depmode $depmode" 1>&2
+  exit 1
+  ;;
+esac
+
+exit 0
+
+# Local Variables:
+# mode: shell-script
+# sh-indentation: 2
+# eval: (add-hook 'write-file-hooks 'time-stamp)
+# time-stamp-start: "scriptversion="
+# time-stamp-format: "%:y-%02m-%02d.%02H"
+# time-stamp-time-zone: "UTC"
+# time-stamp-end: "; # UTC"
+# End:
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/doc/api/Makefile.am
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/doc/api/Makefile.am
@@ -201,6 +201,8 @@
 		sed -e '/renewcommand.*cftchap.*font/s/renew/new/' \
 		doxygen.sty > tmp.$$ && \
 		mv -f tmp.$$ doxygen.sty
+	cd latex_src && sed -e  's/\(longtabu.*\)X\[-1\]/\1l/'  -i *.tex *.sty
+	cd latex_src && sed -e  's/X\[-1,\(.\)\]/\1/g' -i doxygen.sty
 
 #doxygen.config: doxygen.config.in $(top_srcdir)/stamp-h1
 doxygen.config: doxygen.config.in
@@ -227,7 +229,7 @@
 dox-pdf: $(USER_MANUAL).pdf
 
 $(USER_MANUAL).pdf: latex_src/refman.tex
-	cd latex_src && ${MAKE} refman.pdf
+	-cd latex_src && ${MAKE} refman.pdf
 	cp latex_src/refman.pdf $(USER_MANUAL).pdf
 
 # Install rules for the various documentation parts.  The actual
@@ -258,7 +260,7 @@
 
 install-dox-man: dox-html
 	$(mkinstalldirs) $(DESTDIR)$(mandir)/man3
-	$(INSTALL_DATA) man/man3/*.3 $(DESTDIR)$(mandir)/man3
+	$(INSTALL_DATA) man/man3/*.3avr $(DESTDIR)$(mandir)/man3
 
 .PHONY: html xml latex pdf demo demodox \
 	dox-html dox-xml dox-pdf install-pdf install-html install-xml \
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/doc/api/doxygen.config.in
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/doc/api/doxygen.config.in
@@ -1848,14 +1848,14 @@
 # The default value is: .3.
 # This tag requires that the tag GENERATE_MAN is set to YES.
 
-MAN_EXTENSION          = .3
+MAN_EXTENSION = .3avr
 
 # The MAN_SUBDIR tag determines the name of the directory created within
 # MAN_OUTPUT in which the man pages are placed. If defaults to man followed by
 # MAN_EXTENSION with the initial . removed.
 # This tag requires that the tag GENERATE_MAN is set to YES.
 
-MAN_SUBDIR             =
+#MAN_SUBDIR             =
 
 # If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
 # will generate one additional man file for each entity documented in the real
@@ -2386,3 +2386,4 @@
 # This tag requires that the tag HAVE_DOT is set to YES.
 
 DOT_CLEANUP            = YES
+MAN_SUBDIR = man3
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io1200.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io1200.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io1200.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io1200.h - definitions for AT90S1200 */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io2313.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io2313.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io2313.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io2313.h - definitions for AT90S2313 */
 
@@ -378,7 +378,6 @@
 #define SIGNATURE_1 0x91
 #define SIGNATURE_2 0x01
 
-
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_PWR_DOWN     _BV(SM)
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io2323.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io2323.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io2323.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io2323.h - definitions for AT90S2323 */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io2333.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io2333.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io2333.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io2333.h - definitions for AT90S2333 */
 
@@ -458,5 +458,4 @@
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_PWR_DOWN     _BV(SM)
 
-
 #endif /* _AVR_IO2333_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io2343.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io2343.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io2343.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io2343.h - definitions for AT90S2343 */
 
@@ -208,9 +208,7 @@
 #define SIGNATURE_1 0x91
 #define SIGNATURE_2 0x03
 
-
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_PWR_DOWN     _BV(SM)
 
-
 #endif /* _AVR_IO2343_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io43u32x.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io43u32x.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io43u32x.h 1873 2009-02-11 17:53:39Z arcanum $ */
 
 /* avr/io43u32x.h - definitions for AT43USB32x */
 
@@ -437,5 +437,4 @@
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_PWR_DOWN     _BV(SM)
 
-
 #endif /* _AVR_43USB32X_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io43u35x.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io43u35x.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io43u35x.h 1873 2009-02-11 17:53:39Z arcanum $ */
 
 /* avr/io43u35x.h - definitions for AT43USB35x */
 
@@ -429,5 +429,4 @@
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_PWR_DOWN     _BV(SM)
 
-
 #endif /* _AVR_43USB355_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io4414.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io4414.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io4414.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io4414.h - definitions for AT90S4414 */
 
@@ -494,9 +494,7 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x01
 
-
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_PWR_DOWN     _BV(SM)
 
-
 #endif /* _AVR_IO4414_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io4433.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io4433.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io4433.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io4433.h - definitions for AT90S4433 */
 
@@ -483,9 +483,7 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x03
 
-
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_PWR_DOWN     _BV(SM)
 
-
 #endif /* _AVR_IO4433_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io4434.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io4434.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io4434.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io4434.h - definitions for AT90S4434 */
 
@@ -580,11 +580,9 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x03
 
-
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_ADC          _BV(SM0)
 #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
 #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
 
-
 #endif /* _AVR_IO4434_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io76c711.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io76c711.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io76c711.h 1873 2009-02-11 17:53:39Z arcanum $ */
 
 /* avr/io76c711.h - definitions for AT76C711 */
 
@@ -477,6 +477,11 @@
 #define E2END		0
 #define FLASHEND	0x3FFF
 
+#define SLEEP_MODE_IDLE         0
+#define SLEEP_MODE_ADC          _BV(SM0)
+#define SLEEP_MODE_PWR_DOWN     _BV(SM1)
+#define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
+
 /*
    AT76C711 data space memory map (ranges not listed are reserved):
    0x0000 - 0x001F - AVR registers
@@ -490,12 +495,5 @@
    0x3000 - 0x37FF - DPRAM
    0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other
                      AVR devices did that as well (no need to use LPM!)
-
  */
-
-#define SLEEP_MODE_IDLE         0
-#define SLEEP_MODE_ADC          _BV(SM0)
-#define SLEEP_MODE_PWR_DOWN     _BV(SM1)
-#define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
-
 #endif /* _AVR_IO76C711_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io8515.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io8515.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io8515.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io8515.h - definitions for AT90S8515 */
 
@@ -495,9 +495,7 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x01
 
-
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_PWR_DOWN     _BV(SM)
 
-
 #endif /* _AVR_IO8515_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io8534.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io8534.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io8534.h 1873 2009-02-11 17:53:39Z arcanum $ */
 
 /* avr/io8534.h - definitions for AT90C8534 */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io8535.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io8535.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io8535.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io8535.h - definitions for AT90S8535 */
 
@@ -581,11 +581,9 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x03
 
-
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_ADC          _BV(SM0)
 #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
 #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
 
-
 #endif /* _AVR_IO8535_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io86r401.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io86r401.h
@@ -30,8 +30,6 @@
 
 /* avr/io86r401.h - definitions for AT86RF401 */
 
-/* $Id$ */
-
 #ifndef _AVR_IO86RF401_H_
 #define _AVR_IO86RF401_H_ 1
 
@@ -288,7 +286,7 @@
 #define ZH      r31
 
 /* Constants */
-#define RAMSTART    0x60
+#define RAMSTART	0x60
 #define RAMEND      0xDF
 #define XRAMEND     RAMEND
 #define E2END       0x7F
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io90pwm1.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io90pwm1.h
@@ -29,7 +29,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io90pwm1.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/iopwm1.h - definitions for AT90PWM1 device */
 
@@ -1149,11 +1149,9 @@
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOPWM1_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io90pwm161.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io90pwm161.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_AT90PWM161_H_INCLUDED
 #define _AVR_AT90PWM161_H_INCLUDED
 
@@ -78,13 +61,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -136,13 +135,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -161,8 +176,14 @@
 
 #define DDRE    _SFR_IO8(0x0D)
 #define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
 #define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
 #define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
 
 #define PORTE   _SFR_IO8(0x0E)
 #define PORTE2  2
@@ -721,6 +742,14 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* PSC2 Capture Event */
@@ -799,21 +828,44 @@
 #define SPM_READY_vect            _VECTOR(19)
 #define SPM_READY_vect_num        19
 
-#define _VECTORS_SIZE 80
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 80
+#else
+#  define _VECTORS_SIZE 80U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      1024
-#define RAMEND       0x04FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      1024
+#  define RAMEND       0x04FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x04FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -830,6 +882,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -840,6 +894,8 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_DWEN        (unsigned char)~_BV(6)
 #define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
@@ -850,6 +906,8 @@
 #define FUSE_PSC0RB      (unsigned char)~_BV(5)
 #define FUSE_PSC2RBA     (unsigned char)~_BV(6)
 #define FUSE_PSC2RB      (unsigned char)~_BV(7)
+#define EFUSE_DEFAULT    (FUSE_BODLEVEL1)
+
 
 
 /* Lock Bits */
@@ -865,10 +923,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
 
 #endif /* #ifdef _AVR_AT90PWM161_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io90pwm216.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io90pwm216.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io90pwm216.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io90pwm216.h - definitions for AT90PWM216 */
 
@@ -1217,11 +1217,9 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x83
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IO90PWM216_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io90pwm2b.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io90pwm2b.h
@@ -26,10 +26,10 @@
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
+  POSSIBILITY OF SUCH DAMAGE.
 */
 
-/* $Id$ */
+/* $Id: io90pwm2b.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io90pwm2b.h - definitions for AT90PWM2B */
 
@@ -43,7 +43,7 @@
 #  define _AVR_IOXXX_H_ "io90pwm2b.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_IO90PWM2B_H_
@@ -80,7 +80,7 @@
 #define PORTB5 5
 #define PORTB6 6
 #define PORTB7 7
-      
+
 #define PINC _SFR_IO8(0x06)
 #define PINC0 0
 #define PINC1 1
@@ -258,8 +258,8 @@
 #define GTCCR _SFR_IO8(0x23)
 #define PSR10 0
 #define PSRSYNC 0
-#define ICPSEL1 2
-#define TSM 3
+#define ICPSEL1 6
+#define TSM 7
 
 #define TCCR0A _SFR_IO8(0x24)
 #define WGM00 0
@@ -828,7 +828,7 @@
 #define STP0 0
 #define STP1 1
 #define F1617 2
-#define FEM 3 
+#define FEM 3
 
 #define MUBRR _SFR_MEM16(0xCC)
 
@@ -1433,7 +1433,7 @@
 #define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
 #define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
 #define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)    
+#define HFUSE_DEFAULT (FUSE_SPIEN)
 
 
 /* Extended Fuse Byte */
@@ -1450,7 +1450,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -1458,11 +1458,9 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x83
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IO90PWM2B_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io90pwm316.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io90pwm316.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io90pwm316.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io90pwm316.h - definitions for AT90PWM316 */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io90pwm3b.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io90pwm3b.h
@@ -26,10 +26,10 @@
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
+  POSSIBILITY OF SUCH DAMAGE.
 */
 
-/* $Id$ */
+/* $Id: io90pwm3b.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io90pwm3b.h - definitions for AT90PWM3B */
 
@@ -43,7 +43,7 @@
 #  define _AVR_IOXXX_H_ "io90pwm3b.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_IO90PWM3B_H_
@@ -80,7 +80,7 @@
 #define PORTB5 5
 #define PORTB6 6
 #define PORTB7 7
-      
+
 #define PINC _SFR_IO8(0x06)
 #define PINC0 0
 #define PINC1 1
@@ -258,8 +258,8 @@
 #define GTCCR _SFR_IO8(0x23)
 #define PSR10 0
 #define PSRSYNC 0
-#define ICPSEL1 2
-#define TSM 3
+#define ICPSEL1 6
+#define TSM 7
 
 #define TCCR0A _SFR_IO8(0x24)
 #define WGM00 0
@@ -828,7 +828,7 @@
 #define STP0 0
 #define STP1 1
 #define F1617 2
-#define FEM 3 
+#define FEM 3
 
 #define MUBRR _SFR_MEM16(0xCC)
 
@@ -1433,7 +1433,7 @@
 #define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
 #define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
 #define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)    
+#define HFUSE_DEFAULT (FUSE_SPIEN)
 
 
 /* Extended Fuse Byte */
@@ -1450,7 +1450,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -1458,11 +1458,9 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x83
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IO90PWM3B_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io90pwm81.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io90pwm81.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io90pwm81.h 2206 2011-02-11 06:58:02Z aboyapati $ */
 
 /* avr/io90pwm81.h - definitions for AT90PWM81 */
 
@@ -1028,11 +1028,9 @@
 #define SIGNATURE_2 0x88
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
-
 #endif /* _AVR_AT90PWM81_H_ */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io90pwmx.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io90pwmx.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io90pwmx.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/io90pwmx.h - definitions for AT90PWM2(B) and AT90PWM3(B) */
 
@@ -1407,11 +1407,9 @@
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
 
-
 #define SLEEP_MODE_IDLE         (0)
 #define SLEEP_MODE_ADC          _BV(SM0)
 #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
 #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
 
-
 #endif /* _AVR_IO90PWMX_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/io90scr100.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/io90scr100.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: io90scr100.h 1910 2009-03-04 17:45:30Z arcanum $ */
 
 /* avr/io90scr100.h - definitions for AT90SCR100 */
 
@@ -1709,8 +1709,6 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0xC1
 
-
-
 #define SLEEP_MODE_IDLE         (0)
 #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
 #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa5272.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa5272.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATA5272_H_INCLUDED
 #define _AVR_ATA5272_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRA    _SFR_IO8(0x01)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x02)
 #define PORTA7  7
@@ -92,13 +91,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -113,6 +128,10 @@
 /* Reserved [0x06..0x11] */
 
 #define PORTCR  _SFR_IO8(0x12)
+#define PUDA    0
+#define PUDB    1
+#define BBMA    4
+#define BBMB    5
 
 /* Reserved [0x13..0x14] */
 
@@ -233,8 +252,8 @@
 
 #define MCUCR   _SFR_IO8(0x35)
 #define PUD     4
-#define BODS    5
-#define BODSE   6
+#define BODSE   5
+#define BODS    6
 
 /* Reserved [0x36] */
 
@@ -617,6 +636,14 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -695,21 +722,44 @@
 #define USI_START_vect            _VECTOR(36)
 #define USI_START_vect_num        36
 
-#define _VECTORS_SIZE 74
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 74
+#else
+#  define _VECTORS_SIZE 74U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -726,6 +776,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
@@ -736,9 +788,13 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_DWEN        (unsigned char)~_BV(6)
 #define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -752,10 +808,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
 
 #endif /* #ifdef _AVR_ATA5272_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa5505.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa5505.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATA5505_H_INCLUDED
 #define _AVR_ATA5505_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRA    _SFR_IO8(0x01)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x02)
 #define PORTA7  7
@@ -92,13 +91,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -113,6 +128,10 @@
 /* Reserved [0x06..0x11] */
 
 #define PORTCR  _SFR_IO8(0x12)
+#define PUDA    0
+#define PUDB    1
+#define BBMA    4
+#define BBMB    5
 
 /* Reserved [0x13..0x14] */
 
@@ -233,8 +252,8 @@
 
 #define MCUCR   _SFR_IO8(0x35)
 #define PUD     4
-#define BODS    5
-#define BODSE   6
+#define BODSE   5
+#define BODS    6
 
 /* Reserved [0x36] */
 
@@ -617,6 +636,14 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -695,21 +722,44 @@
 #define USI_OVF_vect            _VECTOR(19)
 #define USI_OVF_vect_num        19
 
-#define _VECTORS_SIZE 80
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 80
+#else
+#  define _VECTORS_SIZE 80U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -726,6 +776,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
@@ -736,9 +788,13 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_DWEN        (unsigned char)~_BV(6)
 #define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -752,10 +808,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
 
 #endif /* #ifdef _AVR_ATA5505_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa5702m322.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa5702m322.h
@@ -1,2591 +1,2617 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATA5702M322_H_INCLUDED
-#define _AVR_ATA5702M322_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa5702m322.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define GPIOR0  _SFR_IO8(0x00)
-
-#define PRR1    _SFR_IO8(0x01)
-#define PRT1    0
-#define PRT2    1
-#define PRT3    2
-#define PRT4    3
-#define PRT5    4
-#define PRLFR   5
-#define PRLFTP  6
-#define PRLFPH  7
-
-#define __AVR_HAVE_PRR1	((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5)|(1<<PRLFR)|(1<<PRLFTP)|(1<<PRLFPH))
-#define __AVR_HAVE_PRR1_PRT1
-#define __AVR_HAVE_PRR1_PRT2
-#define __AVR_HAVE_PRR1_PRT3
-#define __AVR_HAVE_PRR1_PRT4
-#define __AVR_HAVE_PRR1_PRT5
-#define __AVR_HAVE_PRR1_PRLFR
-#define __AVR_HAVE_PRR1_PRLFTP
-#define __AVR_HAVE_PRR1_PRLFPH
-
-#define PRR2    _SFR_IO8(0x02)
-#define PRSPI2  0
-#define PRTWI2  1
-#define PRSF    2
-#define PRDF    3
-#define PRTM    6
-#define PRSSM   7
-
-#define __AVR_HAVE_PRR2	((1<<PRSPI2)|(1<<PRTWI2)|(1<<PRSF)|(1<<PRDF)|(1<<PRTM)|(1<<PRSSM))
-#define __AVR_HAVE_PRR2_PRSPI2
-#define __AVR_HAVE_PRR2_PRTWI2
-#define __AVR_HAVE_PRR2_PRSF
-#define __AVR_HAVE_PRR2_PRDF
-#define __AVR_HAVE_PRR2_PRTM
-#define __AVR_HAVE_PRR2_PRSSM
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDRB7   7
-// Inserted "DDB7" from "DDRB7" due to compatibility
-#define DDB7    7
-#define DDRB6   6
-// Inserted "DDB6" from "DDRB6" due to compatibility
-#define DDB6    6
-#define DDRB5   5
-// Inserted "DDB5" from "DDRB5" due to compatibility
-#define DDB5    5
-#define DDRB4   4
-// Inserted "DDB4" from "DDRB4" due to compatibility
-#define DDB4    4
-#define DDRB3   3
-// Inserted "DDB3" from "DDRB3" due to compatibility
-#define DDB3    3
-#define DDRB2   2
-// Inserted "DDB2" from "DDRB2" due to compatibility
-#define DDB2    2
-#define DDRB1   1
-// Inserted "DDB1" from "DDRB1" due to compatibility
-#define DDB1    1
-#define DDRB0   0
-// Inserted "DDB0" from "DDRB0" due to compatibility
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDRC2   2
-// Inserted "DDC2" from "DDRC2" due to compatibility
-#define DDC2    2
-#define DDRC1   1
-// Inserted "DDC1" from "DDRC1" due to compatibility
-#define DDC1    1
-#define DDRC0   0
-// Inserted "DDC0" from "DDRC0" due to compatibility
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PORTC2  2
-#define PORTC1  1
-#define PORTC0  0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDRD7   7
-// Inserted "DDD7" from "DDRD7" due to compatibility
-#define DDD7    7
-#define DDRD6   6
-// Inserted "DDD6" from "DDRD6" due to compatibility
-#define DDD6    6
-#define DDRD5   5
-// Inserted "DDD5" from "DDRD5" due to compatibility
-#define DDD5    5
-#define DDRD4   4
-// Inserted "DDD4" from "DDRD4" due to compatibility
-#define DDD4    4
-#define DDRD3   3
-// Inserted "DDD3" from "DDRD3" due to compatibility
-#define DDD3    3
-#define DDRD2   2
-// Inserted "DDD2" from "DDRD2" due to compatibility
-#define DDD2    2
-#define DDRD1   1
-// Inserted "DDD1" from "DDRD1" due to compatibility
-#define DDD1    1
-#define DDRD0   0
-// Inserted "DDD0" from "DDRD0" due to compatibility
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PORTD7  7
-#define PORTD6  6
-#define PORTD5  5
-#define PORTD4  4
-#define PORTD3  3
-#define PORTD2  2
-#define PORTD1  1
-#define PORTD0  0
-
-#define TPCR2   _SFR_IO8(0x0C)
-#define TPMA    0
-#define TPMOD   1
-#define TPPSD   2
-#define TPD     3
-#define TPNFTO  4
-#define TPWDLV0 5
-#define TPWDLV1 6
-
-#define TPFR    _SFR_IO8(0x0D)
-#define TPF     0
-#define TPFTF   1
-#define TPNFTF  2
-#define TPBERF  3
-
-#define MCUCR   _SFR_IO8(0x0E)
-#define IVL0    0
-#define IVL1    1
-#define SPIIO   2
-#define ENPS    3
-#define PUD     4
-#define TRCCE   5
-#define TRCEN   6
-#define IVSEL   7
-
-#define FSCR    _SFR_IO8(0x0F)
-#define TXMOD   0
-#define SFM     1
-#define TXMS0   2
-#define TXMS1   3
-#define PAOER   4
-#define PAON    7
-
-/* Reserved [0x10] */
-
-#define T1CR    _SFR_IO8(0x11)
-#define T1OTM   0
-#define T1CTM   1
-#define T1CRM   2
-#define T1TOP   4
-#define T1RES   5
-#define T1TOS   6
-#define T1ENA   7
-
-#define T2CR    _SFR_IO8(0x12)
-#define T2OTM   0
-#define T2CTM   1
-#define T2CRM   2
-#define T2TOP   4
-#define T2RES   5
-#define T2TOS   6
-#define T2ENA   7
-
-#define T3CR    _SFR_IO8(0x13)
-#define T3OTM   0
-#define T3CTM   1
-#define T3CRM   2
-#define T3CPRM  3
-#define T3TOP   4
-#define T3RES   5
-#define T3TOS   6
-#define T3ENA   7
-
-#define T4CR    _SFR_IO8(0x14)
-#define T4OTM   0
-#define T4CTM   1
-#define T4CRM   2
-#define T4CPRM  3
-#define T4TOP   4
-#define T4RES   5
-#define T4TOS   6
-#define T4ENA   7
-
-#define LTCMR   _SFR_IO8(0x15)
-#define LTPS0   0
-#define LTPS1   1
-#define LTPS2   2
-#define LTCRM   3
-#define LTCIM   4
-#define LTCM    5
-#define LTSM    6
-#define LTENA   7
-
-#define EECR2   _SFR_IO8(0x16)
-#define EEBRE   0
-#define E2CIM   1
-#define E2AVF   5
-#define E2FF    6
-#define E2CF    7
-
-#define PHTCR   _SFR_IO8(0x17)
-#define FRFIFO  5
-#define CPM     6
-#define CSM     7
-
-#define LDFFL   _SFR_IO8(0x18)
-#define LDFFL0  0
-#define LDFFL1  1
-#define LDFFL2  2
-#define LDFFL3  3
-#define LDFFL4  4
-#define LDFFL5  5
-#define LDFCLR  7
-
-#define LDFD    _SFR_IO8(0x19)
-
-#define PRR0    _SFR_IO8(0x1A)
-#define PRSPI   0
-#define PRLFRS  1
-#define PRTXDC  2
-#define PRCRC   3
-#define PRVM    4
-#define PRCO    5
-#define PRCU    6
-#define PRTWI1  7
-
-#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRLFRS)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO)|(1<<PRCU)|(1<<PRTWI1))
-#define __AVR_HAVE_PRR0_PRSPI
-#define __AVR_HAVE_PRR0_PRLFRS
-#define __AVR_HAVE_PRR0_PRTXDC
-#define __AVR_HAVE_PRR0_PRCRC
-#define __AVR_HAVE_PRR0_PRVM
-#define __AVR_HAVE_PRR0_PRCO
-#define __AVR_HAVE_PRR0_PRCU
-#define __AVR_HAVE_PRR0_PRTWI1
-
-#define PHFR    _SFR_IO8(0x1B)
-#define CRCEF   0
-#define PHTBLF  1
-#define PHDFF   2
-#define PHIDFF  3
-#define PHID0F  4
-#define PHID1F  5
-
-#define LFFR    _SFR_IO8(0x1C)
-#define LFSYDF  0
-#define LFDEF   1
-#define LFEOF   2
-#define LFTOF   3
-#define LFSD    6
-#define LFES    7
-
-#define AESCR   _SFR_IO8(0x1D)
-#define AESWK   0
-#define AESWD   1
-#define AESIM   2
-#define AESD    3
-#define AESXOR  4
-#define AESRES  5
-#define AESLKM  6
-#define AESE    7
-
-#define AESSR   _SFR_IO8(0x1E)
-#define AESRF   0
-#define AESERF  7
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-#define EEPAGE  6
-#define NVMBSY  7
-
-#define EEDR    _SFR_IO8(0x20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define EEPR    _SFR_IO8(0x23)
-#define EEAP0   0
-#define EEAP1   1
-#define EEAP2   2
-#define EEAP3   3
-
-#define GPIOR1  _SFR_IO8(0x24)
-
-#define GPIOR2  _SFR_IO8(0x25)
-
-#define PCICR   _SFR_IO8(0x26)
-#define PCIE0   0
-#define PCIE1   1
-
-#define EIMSK   _SFR_IO8(0x27)
-#define INT0    0
-#define INT1    1
-
-#define EIFR    _SFR_IO8(0x28)
-#define INTF0   0
-#define INTF1   1
-
-#define LDFCKSW _SFR_IO8(0x29)
-#define LDFSCSW 0
-#define LDFSCKS 1
-
-#define VMSCR   _SFR_IO8(0x2A)
-#define VMF     0
-#define VMDIH   1
-
-#define MCUSR   _SFR_IO8(0x2B)
-#define PORF    0
-#define EXTRF   1
-#define WDRF    3
-#define DWRF    4
-#define TPRF    5
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define RXIF    4
-#define TXIF    5
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-#define LFCR0   _SFR_IO8(0x2F)
-#define LFCE1   0
-#define LFCE2   1
-#define LFCE3   2
-#define LFBR0   3
-#define LFBR1   4
-#define LFMG    5
-#define LFRRT0  6
-#define LFRRT1  7
-
-#define LFCR1   _SFR_IO8(0x30)
-#define RSST0   0
-#define RSST1   1
-#define LFFM1   2
-#define ARMDE   3
-#define FLLEN   4
-#define ADTHEN  5
-#define LFPEEN  6
-#define LFRE    7
-
-#define DWDR    _SFR_IO8(0x31)
-
-#define T0IFR   _SFR_IO8(0x32)
-#define T0F     0
-
-/* Reserved [0x33..0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS   1
-#define PGWRT   2
-#define FLSEL0  3
-#define FLSEL1  4
-#define FLSEL2  5
-#define RWWSB   6
-#define SPMIE   7
-
-#define SMCR    _SFR_IO8(0x38)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define TPSR    _SFR_IO8(0x39)
-#define TPA     0
-#define TPGAP   1
-#define TPPSW   2
-#define TPBCOK  3
-
-#define LFCR2   _SFR_IO8(0x3A)
-#define LFSEN0  0
-#define LFSEN1  1
-#define LFDAMP  2
-#define LFVC0   5
-#define LFVC1   6
-#define LFVC2   7
-
-#define LFCR3   _SFR_IO8(0x3B)
-#define LFRCTEN 0
-#define LFRCPCEN 1
-#define LFRCPM  2
-#define LFTON   3
-#define LFTS0   4
-#define LFTS1   5
-#define LFTS2   6
-#define LFSBEN  7
-
-/* Reserved [0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define FSEN    _SFR_MEM8(0x60)
-#define SDPU    0
-#define SDEN    1
-#define GAEN    2
-#define PEEN    3
-#define ASEN    4
-#define ANTT    5
-
-#define FSFCR   _SFR_MEM8(0x61)
-#define BTSEL0  0
-#define BTSEL1  1
-#define ASDIV0  4
-#define ASDIV1  5
-#define ASDIV2  6
-#define ASDIV3  7
-
-/* Combine GACDIVL and GACDIVH */
-#define GACDIV  _SFR_MEM16(0x62)
-
-#define GACDIVL _SFR_MEM8(0x62)
-#define GACDIVH _SFR_MEM8(0x63)
-
-#define FFREQ1L _SFR_MEM8(0x64)
-
-#define FFREQ1M _SFR_MEM8(0x65)
-
-#define FFREQ1H _SFR_MEM8(0x66)
-
-#define FFREQ2L _SFR_MEM8(0x67)
-
-#define FFREQ2M _SFR_MEM8(0x68)
-
-#define FFREQ2H _SFR_MEM8(0x69)
-
-#define BBTE2   _SFR_MEM8(0x6A)
-#define TDEPO   0
-#define DITDIS  1
-
-#define EICRA   _SFR_MEM8(0x6B)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-#define PCMSK0  _SFR_MEM8(0x6C)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6D)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define WDTCR   _SFR_MEM8(0x6E)
-#define WDPS0   0
-#define WDPS1   1
-#define WDPS2   2
-#define WDE     3
-#define WDCE    4
-
-#define T1CNT   _SFR_MEM8(0x6F)
-
-#define T1COR   _SFR_MEM8(0x70)
-
-#define T1MR    _SFR_MEM8(0x71)
-#define T1CS0   0
-#define T1CS1   1
-#define T1PS0   2
-#define T1PS1   3
-#define T1PS2   4
-#define T1PS3   5
-#define T1DC0   6
-#define T1DC1   7
-
-#define T1IMR   _SFR_MEM8(0x72)
-#define T1OIM   0
-#define T1CIM   1
-
-#define T2CNT   _SFR_MEM8(0x73)
-
-#define T2COR   _SFR_MEM8(0x74)
-
-#define T2MR    _SFR_MEM8(0x75)
-#define T2CS0   0
-#define T2CS1   1
-#define T2PS0   2
-#define T2PS1   3
-#define T2PS2   4
-#define T2PS3   5
-#define T2DC0   6
-#define T2DC1   7
-
-#define T2IMR   _SFR_MEM8(0x76)
-#define T2OIM   0
-#define T2CIM   1
-
-/* Combine T3CNTL and T3CNTH */
-#define T3CNT   _SFR_MEM16(0x77)
-
-#define T3CNTL  _SFR_MEM8(0x77)
-#define T3CNTH  _SFR_MEM8(0x78)
-
-/* Combine T3CORL and T3CORH */
-#define T3COR   _SFR_MEM16(0x79)
-
-#define T3CORL  _SFR_MEM8(0x79)
-#define T3CORH  _SFR_MEM8(0x7A)
-
-/* Combine T3ICRL and T3ICRH */
-#define T3ICR   _SFR_MEM16(0x7B)
-
-#define T3ICRL  _SFR_MEM8(0x7B)
-#define T3ICRH  _SFR_MEM8(0x7C)
-
-#define T3MRA   _SFR_MEM8(0x7D)
-#define T3CS0   0
-#define T3CS1   1
-#define T3PS0   2
-#define T3PS1   3
-#define T3PS2   4
-
-#define T3MRB   _SFR_MEM8(0x7E)
-#define T3SCE   1
-#define T3CNC   2
-#define T3CE0   3
-#define T3CE1   4
-#define T3ICS0  5
-#define T3ICS1  6
-#define T3ICS2  7
-
-#define T3IMR   _SFR_MEM8(0x7F)
-#define T3OIM   0
-#define T3CIM   1
-#define T3CPIM  2
-
-/* Combine T4CNTL and T4CNTH */
-#define T4CNT   _SFR_MEM16(0x80)
-
-#define T4CNTL  _SFR_MEM8(0x80)
-#define T4CNTH  _SFR_MEM8(0x81)
-
-/* Combine T4CORL and T4CORH */
-#define T4COR   _SFR_MEM16(0x82)
-
-#define T4CORL  _SFR_MEM8(0x82)
-#define T4CORH  _SFR_MEM8(0x83)
-
-/* Combine T4ICRL and T4ICRH */
-#define T4ICR   _SFR_MEM16(0x84)
-
-#define T4ICRL  _SFR_MEM8(0x84)
-#define T4ICRH  _SFR_MEM8(0x85)
-
-#define T4MRA   _SFR_MEM8(0x86)
-#define T4CS0   0
-#define T4CS1   1
-#define T4PS0   2
-#define T4PS1   3
-#define T4PS2   4
-
-#define T4MRB   _SFR_MEM8(0x87)
-#define T4SCE   1
-#define T4CNC   2
-#define T4CE0   3
-#define T4CE1   4
-#define T4ICS0  5
-#define T4ICS1  6
-#define T4ICS2  7
-
-#define T4IMR   _SFR_MEM8(0x88)
-#define T4OIM   0
-#define T4CIM   1
-#define T4CPIM  2
-
-#define T5TEMP  _SFR_MEM8(0x89)
-
-/* Combine T5OCRL and T5OCRH */
-#define T5OCR   _SFR_MEM16(0x8A)
-
-#define T5OCRL  _SFR_MEM8(0x8A)
-#define T5OCRH  _SFR_MEM8(0x8B)
-
-#define T5CCR   _SFR_MEM8(0x8C)
-#define T5CS0   0
-#define T5CS1   1
-#define T5CS2   2
-#define T5CTC   3
-
-/* Combine T5CNTL and T5CNTH */
-#define T5CNT   _SFR_MEM16(0x8D)
-
-#define T5CNTL  _SFR_MEM8(0x8D)
-#define T5CNTH  _SFR_MEM8(0x8E)
-
-#define T5IMR   _SFR_MEM8(0x8F)
-#define T5OIM   0
-#define T5CIM   1
-
-#define LFCALR1 _SFR_MEM8(0x90)
-#define LFSTC0  0
-#define LFSTC1  1
-#define LFSTC2  2
-#define ICOMPRT0 3
-#define ICOMPRT1 4
-#define SEL150M0 5
-#define SEL150M1 6
-#define SEL150M2 7
-
-#define LFCALR2 _SFR_MEM8(0x91)
-#define LFSTRES0 0
-#define LFSTRES1 1
-#define LFSTRES2 2
-#define LFSTRES3 3
-#define LFSTRES4 4
-#define LFSTRES5 5
-#define LFSRM   6
-#define TIKOMPD 7
-
-#define LFCALR3 _SFR_MEM8(0x92)
-#define TCGAIN10 0
-#define TCGAIN11 1
-#define TCGAIN12 2
-#define TCGAIN13 3
-#define TCGAIN14 4
-#define TCGAIN15 5
-#define TCGAIN16 6
-#define TCGAIN17 7
-
-#define LFCALR4 _SFR_MEM8(0x93)
-#define TCGAIN20 0
-#define TCGAIN21 1
-#define TCGAIN22 2
-#define TCGAIN23 3
-#define TCGAIN24 4
-#define TCGAIN25 5
-#define TCGAIN26 6
-#define TCGAIN27 7
-
-#define LFCALR5 _SFR_MEM8(0x94)
-#define TCGAIN30 0
-#define TCGAIN31 1
-#define TCGAIN32 2
-#define TCGAIN34 4
-#define TCGAIN35 5
-#define TCGAIN36 6
-#define TCGAIN37 7
-
-#define LFCALR6 _SFR_MEM8(0x95)
-#define TCGAIN40 0
-#define TCGAIN41 1
-#define TCGAIN42 2
-#define TCGAIN43 3
-#define TCGAIN44 4
-
-#define LFCALR7 _SFR_MEM8(0x96)
-
-#define LFCALR8 _SFR_MEM8(0x97)
-
-#define LFCALR9 _SFR_MEM8(0x98)
-
-#define LFCALR10 _SFR_MEM8(0x99)
-
-#define LFCALR11 _SFR_MEM8(0x9A)
-
-#define LFCALR12 _SFR_MEM8(0x9B)
-
-#define LFCALR13 _SFR_MEM8(0x9C)
-
-#define LFCALR14 _SFR_MEM8(0x9D)
-
-#define LFCALR15 _SFR_MEM8(0x9E)
-
-#define LFCALR16 _SFR_MEM8(0x9F)
-
-#define LFCALR17 _SFR_MEM8(0xA0)
-
-#define LFCALR18 _SFR_MEM8(0xA1)
-
-#define LFCALR19 _SFR_MEM8(0xA2)
-
-#define LFCALR20 _SFR_MEM8(0xA3)
-
-#define LFCALR21 _SFR_MEM8(0xA4)
-
-#define LFCALR22 _SFR_MEM8(0xA5)
-
-#define LFCALR23 _SFR_MEM8(0xA6)
-
-#define LFCALR24 _SFR_MEM8(0xA7)
-
-#define LFCALR25 _SFR_MEM8(0xA8)
-
-#define LFCALR26 _SFR_MEM8(0xA9)
-
-#define LFCALR27 _SFR_MEM8(0xAA)
-
-#define LFCALR28 _SFR_MEM8(0xAB)
-
-#define LFCALR29 _SFR_MEM8(0xAC)
-
-#define LFCALR30 _SFR_MEM8(0xAD)
-
-#define LFCALR31 _SFR_MEM8(0xAE)
-
-#define LFCALR32 _SFR_MEM8(0xAF)
-
-#define LFCALR33 _SFR_MEM8(0xB0)
-
-#define LFCALR34 _SFR_MEM8(0xB1)
-
-#define LFCALR35 _SFR_MEM8(0xB2)
-
-#define LFCALR36 _SFR_MEM8(0xB3)
-
-#define LFCALR37 _SFR_MEM8(0xB4)
-
-#define LFCALR38 _SFR_MEM8(0xB5)
-
-#define LFCALR39 _SFR_MEM8(0xB6)
-
-#define LFCALR40 _SFR_MEM8(0xB7)
-
-#define LFCALR41 _SFR_MEM8(0xB8)
-
-#define LFCALR42 _SFR_MEM8(0xB9)
-
-#define LFCALR43 _SFR_MEM8(0xBA)
-
-#define LFCALR44 _SFR_MEM8(0xBB)
-
-#define LFCALR45 _SFR_MEM8(0xBC)
-
-#define LFCALR46 _SFR_MEM8(0xBD)
-
-#define LFCALR47 _SFR_MEM8(0xBE)
-
-#define LFCALR48 _SFR_MEM8(0xBF)
-
-#define LFCALR49 _SFR_MEM8(0xC0)
-
-#define LFCALR50 _SFR_MEM8(0xC1)
-
-#define LFCALR51 _SFR_MEM8(0xC2)
-
-#define LFCALR52 _SFR_MEM8(0xC3)
-
-#define LFCALR53 _SFR_MEM8(0xC4)
-
-#define XFUSE   _SFR_MEM8(0xC5)
-
-#define MRCCAL  _SFR_MEM8(0xC6)
-
-#define FRCCAL  _SFR_MEM8(0xC7)
-
-#define RCTCAL  _SFR_MEM8(0xC8)
-#define FRCTC   0
-#define MRCTC0  1
-#define MRCTC1  2
-#define MRCTC2  3
-#define DI_MRCBG 4
-
-#define CMSR    _SFR_MEM8(0xC9)
-#define ECF     0
-
-#define CMOCR   _SFR_MEM8(0xCA)
-#define FRCAO   0
-#define MRCAO   1
-#define FRCACT  2
-
-#define SUPFR   _SFR_MEM8(0xCB)
-#define AVCCRF  0
-#define AVCCLF  1
-
-#define SUPCR   _SFR_MEM8(0xCC)
-#define AVCCRM  0
-#define AVCCLM  1
-#define PVEN    2
-#define AVDIC   3
-#define AVEN    4
-#define DVHEN   5
-#define VMRESM  6
-#define VMEMEN  7
-
-#define SUPCA1  _SFR_MEM8(0xCD)
-#define PV22    2
-#define PVDIC   3
-#define PVCAL0  4
-#define PVCAL1  5
-#define PVCAL2  6
-#define PVCAL3  7
-
-#define SUPCA2  _SFR_MEM8(0xCE)
-#define BGCAL0  0
-#define BGCAL1  1
-#define BGCAL2  2
-#define BGCAL3  3
-
-#define SUPCA3  _SFR_MEM8(0xCF)
-#define ACAL0   0
-#define ACAL1   1
-#define ACAL2   2
-#define ACAL3   3
-#define ACAL4   4
-#define ACAL5   5
-#define ACAL6   6
-#define ACAL7   7
-
-#define SUPCA4  _SFR_MEM8(0xD0)
-#define ICONST0 0
-#define ICONST1 1
-#define ICONST2 2
-#define ICONST3 3
-#define ICONST4 4
-#define ICONST5 5
-
-#define CALRDY  _SFR_MEM8(0xD1)
-
-#define DFS     _SFR_MEM8(0xD2)
-#define DFFLRF  0
-#define DFUFL   1
-#define DFOFL   2
-
-/* Reserved [0xD3..0xD4] */
-
-#define DFL     _SFR_MEM8(0xD5)
-#define DFFLS0  0
-#define DFFLS1  1
-#define DFFLS2  2
-#define DFFLS3  3
-#define DFFLS4  4
-#define DFFLS5  5
-#define DFCLR   7
-
-#define DFWP    _SFR_MEM8(0xD6)
-
-#define DFRP    _SFR_MEM8(0xD7)
-
-#define DFD     _SFR_MEM8(0xD8)
-
-#define DFI     _SFR_MEM8(0xD9)
-#define DFFLIM  0
-#define DFERIM  1
-
-#define DFC     _SFR_MEM8(0xDA)
-#define DFFLC0  0
-#define DFFLC1  1
-#define DFFLC2  2
-#define DFFLC3  3
-#define DFFLC4  4
-#define DFFLC5  5
-#define DFDRA   7
-
-#define SFS     _SFR_MEM8(0xDB)
-#define SFFLRF  0
-#define SFUFL   1
-#define SFOFL   2
-
-#define SFL     _SFR_MEM8(0xDC)
-#define SFFLS0  0
-#define SFFLS1  1
-#define SFFLS2  2
-#define SFFLS3  3
-#define SFFLS4  4
-#define SFCLR   7
-
-#define SFWP    _SFR_MEM8(0xDD)
-
-#define SFRP    _SFR_MEM8(0xDE)
-
-#define SFD     _SFR_MEM8(0xDF)
-
-#define SFI     _SFR_MEM8(0xE0)
-#define SFFLIM  0
-#define SFERIM  1
-
-#define SFC     _SFR_MEM8(0xE1)
-#define SFFLC0  0
-#define SFFLC1  1
-#define SFFLC2  2
-#define SFFLC3  3
-#define SFFLC4  4
-#define SFDRA   7
-
-#define SSMCR   _SFR_MEM8(0xE2)
-#define SSMTGE  2
-#define SSMTPE  3
-#define SSMPVE  4
-#define SSMTAE  5
-
-#define GTCCR   _SFR_MEM8(0xE3)
-#define PSR10   0
-#define TSM     7
-
-#define SSMFBR  _SFR_MEM8(0xE4)
-#define SSMPLDT 5
-
-#define SSMRR   _SFR_MEM8(0xE5)
-#define SSMR    0
-#define SSMST   1
-
-#define SSMSR   _SFR_MEM8(0xE6)
-#define SSMESM0 0
-#define SSMESM1 1
-#define SSMESM2 2
-#define SSMESM3 3
-#define SSMERR  7
-
-#define SSMIFR  _SFR_MEM8(0xE7)
-#define SSMIF   0
-
-#define SSMIMR  _SFR_MEM8(0xE8)
-#define SSMIM   0
-
-#define MSMSTR  _SFR_MEM8(0xE9)
-#define SSMMST0 0
-#define SSMMST1 1
-#define SSMMST2 2
-#define SSMMST3 3
-#define SSMMST4 4
-
-#define SSMSTR  _SFR_MEM8(0xEA)
-#define SSMSTA0 0
-#define SSMSTA1 1
-#define SSMSTA2 2
-#define SSMSTA3 3
-#define SSMSTA4 4
-#define SSMSTA5 5
-
-#define VXMCTRL _SFR_MEM8(0xEB)
-#define VX_SEL0 0
-#define VX_SEL1 1
-#define EN_VX   2
-#define EN_VX_OUT 3
-#define EN_VX_IN 4
-
-#define MSMCR1  _SFR_MEM8(0xEC)
-#define MSMSM00 0
-#define MSMSM01 1
-#define MSMSM02 2
-#define MSMSM03 3
-#define MSMSM10 4
-#define MSMSM11 5
-#define MSMSM12 6
-#define MSMSM13 7
-
-#define MSMCR2  _SFR_MEM8(0xED)
-#define MSMSM20 0
-#define MSMSM21 1
-#define MSMSM22 2
-#define MSMSM23 3
-#define MSMSM30 4
-#define MSMSM31 5
-#define MSMSM32 6
-#define MSMSM33 7
-
-#define MSMCR3  _SFR_MEM8(0xEE)
-#define MSMSM40 0
-#define MSMSM41 1
-#define MSMSM42 2
-#define MSMSM43 3
-#define MSMSM50 4
-#define MSMSM51 5
-#define MSMSM52 6
-#define MSMSM53 7
-
-#define MSMCR4  _SFR_MEM8(0xEF)
-#define MSMSM60 0
-#define MSMSM61 1
-#define MSMSM62 2
-#define MSMSM63 3
-#define MSMSM70 4
-#define MSMSM71 5
-#define MSMSM72 6
-#define MSMSM73 7
-
-/* Reserved [0xF0..0xF6] */
-
-#define SP2CR   _SFR_MEM8(0xF7)
-#define SP2R0   0
-#define SP2R1   1
-#define CPHA2   2
-#define CPOL2   3
-#define MSTR2   4
-#define DORD2   5
-#define SP2E    6
-#define SP2IE   7
-
-#define SP2DR   _SFR_MEM8(0xF8)
-
-#define SP2SR   _SFR_MEM8(0xF9)
-#define SPI22X  0
-#define WCOL2   6
-#define SP2IF   7
-
-/* Reserved [0xFA..0xFB] */
-
-/* Combine TRCIDL and TRCIDH */
-#define TRCID   _SFR_MEM16(0xFC)
-
-#define TRCIDL  _SFR_MEM8(0xFC)
-#define TRCIDH  _SFR_MEM8(0xFD)
-
-/* Reserved [0xFE] */
-
-#define TRCDR   _SFR_MEM8(0xFF)
-
-#define FESR    _SFR_MEM8(0x100)
-#define XRDY    2
-#define PLCK    3
-#define ANTS    4
-
-#define FEEN1   _SFR_MEM8(0x101)
-#define PLEN    0
-#define PLCAL   1
-#define XTOEN   2
-#define PLSP1   6
-#define ATEN    7
-
-#define FEEN2   _SFR_MEM8(0x102)
-#define PAEN    2
-#define PLPEN   4
-#define CPBIA   6
-
-#define FELNA   _SFR_MEM8(0x103)
-
-#define FEAT    _SFR_MEM8(0x104)
-#define ANTN0   0
-#define ANTN1   1
-#define ANTN2   2
-#define ANTN3   3
-
-#define FEPAC   _SFR_MEM8(0x105)
-#define PACR0   0
-#define PACR1   1
-#define PACR2   2
-#define PACR3   3
-#define PACR4   4
-#define PACR5   5
-#define PACR6   6
-#define PACR7   7
-
-#define FEVCT   _SFR_MEM8(0x106)
-
-#define FEBT    _SFR_MEM8(0x107)
-#define CTN20   0
-#define CTN21   1
-#define RTN20   2
-#define RTN21   3
-
-#define FEMS    _SFR_MEM8(0x108)
-#define PLLS0   0
-#define PLLS1   1
-#define PLLS2   2
-#define PLLS3   3
-#define PLLM0   4
-#define PLLM1   5
-#define PLLM2   6
-#define PLLM3   7
-
-#define FETN4   _SFR_MEM8(0x109)
-#define CTN40   0
-#define CTN41   1
-#define CTN42   2
-#define CTN43   3
-#define RTN40   4
-#define RTN41   5
-#define RTN42   6
-#define RTN43   7
-
-#define FECR    _SFR_MEM8(0x10A)
-#define LBNHB   0
-#define S4N3    1
-#define PLCKG   4
-#define ANPS    5
-
-#define FEVCO   _SFR_MEM8(0x10B)
-#define CPCC0   0
-#define CPCC1   1
-#define CPCC2   2
-#define CPCC3   3
-#define VCOB0   4
-#define VCOB1   5
-#define VCOB2   6
-#define VCOB3   7
-
-#define FEALR   _SFR_MEM8(0x10C)
-#define RNGE0   0
-#define RNGE1   1
-
-#define FEANT   _SFR_MEM8(0x10D)
-#define LVLC0   0
-#define LVLC1   1
-#define LVLC2   2
-#define LVLC3   3
-
-#define FEBIA   _SFR_MEM8(0x10E)
-
-/* Reserved [0x10F..0x114] */
-
-#define CLKOD   _SFR_MEM8(0x115)
-
-#define CLKOCR  _SFR_MEM8(0x116)
-#define CLKOS0  0
-#define CLKOS1  1
-#define CLKOEN  2
-
-/* Reserved [0x117..0x11B] */
-
-#define FETE1   _SFR_MEM8(0x11C)
-#define ADCT    0
-#define XTOT    1
-#define LNLT    2
-#define LNHT    3
-#define PATE    4
-#define AMPT    5
-#define VCOT    6
-#define ANTN    7
-
-#define FETE2   _SFR_MEM8(0x11D)
-#define RCCT    0
-#define PPFT    1
-#define LFT     2
-#define CPT     3
-#define PFDT    4
-#define DADCT   5
-#define PRET    6
-#define SWALT   7
-
-#define FETE3   _SFR_MEM8(0x11E)
-#define BIOUT   0
-#define RMPTST  1
-
-#define FETD    _SFR_MEM8(0x11F)
-
-#define TMFSM   _SFR_MEM8(0x120)
-#define TMSSM0  0
-#define TMSSM1  1
-#define TMSSM2  2
-#define TMSSM3  3
-#define TMMSM0  4
-#define TMMSM1  5
-#define TMMSM2  6
-
-/* Combine TMCRCL and TMCRCH */
-#define TMCRC   _SFR_MEM16(0x121)
-
-#define TMCRCL  _SFR_MEM8(0x121)
-#define TMCRCH  _SFR_MEM8(0x122)
-
-#define TMCSB   _SFR_MEM8(0x123)
-
-/* Combine TMCIL and TMCIH */
-#define TMCI    _SFR_MEM16(0x124)
-
-#define TMCIL   _SFR_MEM8(0x124)
-#define TMCIH   _SFR_MEM8(0x125)
-
-/* Combine TMCPL and TMCPH */
-#define TMCP    _SFR_MEM16(0x126)
-
-#define TMCPL   _SFR_MEM8(0x126)
-#define TMCPH   _SFR_MEM8(0x127)
-
-#define TMSHR   _SFR_MEM8(0x128)
-
-/* Combine TMTLLL and TMTLLH */
-#define TMTLL   _SFR_MEM16(0x129)
-
-#define TMTLLL  _SFR_MEM8(0x129)
-#define TMTLLH  _SFR_MEM8(0x12A)
-
-#define TMSSC   _SFR_MEM8(0x12B)
-#define TMSSP0  0
-#define TMSSP1  1
-#define TMSSP2  2
-#define TMSSP3  3
-#define TMSSL0  4
-#define TMSSL1  5
-#define TMSSL2  6
-#define TMSSH   7
-
-#define TMSR    _SFR_MEM8(0x12C)
-#define TMTCF   0
-
-#define TMCR2   _SFR_MEM8(0x12D)
-#define TMCRCE  0
-#define TMCRCSE0 1
-#define TMCRCSE1 2
-#define TMNRZE  3
-#define TMPOL   4
-#define TMSSE   5
-#define TMLSB   6
-
-#define TMCR1   _SFR_MEM8(0x12E)
-#define TMPIS0  0
-#define TMPIS1  1
-#define TMPIS2  2
-#define TMSCS   3
-#define TMCIM   4
-
-/* Reserved [0x12F] */
-
-#define LFDSR1  _SFR_MEM8(0x130)
-#define LOTHA0  0
-#define LOTHA1  1
-#define HITHA0  2
-#define HITHA1  3
-#define CTTHA0  4
-#define CTTHA1  5
-
-#define LFDSR2  _SFR_MEM8(0x131)
-#define LOTHB0  0
-#define LOTHB1  1
-#define HITHB0  2
-#define HITHB1  3
-#define CTTHB0  4
-#define CTTHB1  5
-
-#define LFDSR3  _SFR_MEM8(0x132)
-#define PBDTH0  0
-#define PBDTH1  1
-#define QCTH0   3
-#define QCTH1   4
-#define QCTH2   5
-
-#define LFDSR4  _SFR_MEM8(0x133)
-#define SDTHA0  0
-#define SDTHA1  1
-#define SDTHA2  2
-#define SCTHA0  3
-#define SCTHA1  4
-#define SCTHA2  5
-#define SRSTC0  6
-#define SRSTC1  7
-
-#define LFDSR5  _SFR_MEM8(0x134)
-#define SDTHB0  0
-#define SDTHB1  1
-#define SDTHB2  2
-#define SCTHB0  3
-#define SCTHB1  4
-#define SCTHB2  5
-#define SSUTA   6
-#define SSUTB   7
-
-#define LFDSR6  _SFR_MEM8(0x135)
-#define TODU0   0
-#define TODU1   1
-#define TODU2   2
-#define TODS0   3
-#define TODS1   4
-#define TODS2   5
-
-#define LFDSR7  _SFR_MEM8(0x136)
-#define PBSP0   0
-#define PBSP1   1
-#define PBG0    2
-#define PBG1    3
-#define MDSP0   4
-#define MDSP1   5
-#define MDG0    6
-#define MDG1    7
-
-#define LFDSR8  _SFR_MEM8(0x137)
-#define CLD0    0
-#define CLD1    1
-#define CLD2    2
-#define LGFE    3
-#define ASWTH0  4
-#define ASWTH1  5
-#define ASWTH2  6
-
-#define LFDSR9  _SFR_MEM8(0x138)
-#define STW0    0
-#define STW1    1
-#define STW2    2
-#define STW3    3
-#define STW4    4
-
-#define LFDSR10 _SFR_MEM8(0x139)
-#define FCL0    0
-#define FCL1    1
-#define FCL2    2
-#define FCL3    3
-#define FCL4    4
-#define FCL5    5
-#define STBTH0  6
-#define STBTH1  7
-
-#define LFDSR11 _SFR_MEM8(0x13A)
-#define TINITA0 0
-#define TINITA1 1
-#define TINITA2 2
-#define TINITA3 3
-#define TINITB0 4
-#define TINITB1 5
-#define TINITB2 6
-#define TINITB3 7
-
-#define EEPR1   _SFR_MEM8(0x13B)
-#define EEPS4WD 0
-#define EEPS4RD 1
-#define EEPS5WD 2
-#define EEPS5RD 3
-#define EEPS6WD 4
-#define EEPS6RD 5
-#define EEPS7WD 6
-#define EEPS7RD 7
-
-#define EEPR2   _SFR_MEM8(0x13C)
-#define EEPS8WD 0
-#define EEPS8RD 1
-#define EEPS9WD 2
-#define EEPS9RD 3
-#define EEPS10WD 4
-#define EEPS10RD 5
-#define EEPS11WD 6
-#define EEPS11RD 7
-
-#define EEPR3   _SFR_MEM8(0x13D)
-#define EEPS12WD 0
-#define EEPS12RD 1
-
-/* Reserved [0x13E..0x144] */
-
-#define CRCCR   _SFR_MEM8(0x145)
-#define CRCRS   0
-#define REFLI   1
-#define REFLO   2
-
-#define CRCDOR  _SFR_MEM8(0x146)
-
-/* Reserved [0x147..0x150] */
-
-#define LFSRCTM _SFR_MEM8(0x151)
-#define LFSRCT1 0
-#define LFSRCT2 1
-#define LFSRCT3 2
-#define LFSRCT4 3
-#define LFSRCT5 4
-#define LFSRCT6 5
-#define LFSRCT7 6
-#define LFSRCT8 7
-
-#define DBCR    _SFR_MEM8(0x152)
-#define DBMD    0
-#define DBCS    1
-#define DBTMS   2
-#define DBHA    3
-
-#define DBTC    _SFR_MEM8(0x153)
-
-#define DBENB   _SFR_MEM8(0x154)
-
-#define DBENC   _SFR_MEM8(0x155)
-
-#define DBGSW   _SFR_MEM8(0x156)
-#define DBGGS0  0
-#define DBGGS1  1
-#define DBGGS2  2
-#define DBGGS3  3
-#define CPBFOS0 4
-#define CPBFOS1 5
-#define CPBF    6
-#define ATEST   7
-
-#define SFFR    _SFR_MEM8(0x157)
-#define RFL0    0
-#define RFL1    1
-#define RFL2    2
-#define RFC     3
-#define TFL0    4
-#define TFL1    5
-#define TFL2    6
-#define TFC     7
-
-#define SFIR    _SFR_MEM8(0x158)
-#define RIL0    0
-#define RIL1    1
-#define RIL2    2
-#define SRIE    3
-#define TIL0    4
-#define TIL1    5
-#define TIL2    6
-#define STIE    7
-
-#define T2IFR   _SFR_MEM8(0x159)
-#define T2OFF   0
-#define T2COF   1
-
-#define PGMST   _SFR_MEM8(0x15A)
-#define PGMSYN0 0
-#define PGMSYN1 1
-#define PGMSYN2 2
-#define PGMSYN3 3
-#define PGMSYN4 4
-
-#define EEST    _SFR_MEM8(0x15B)
-#define EESYN0  0
-#define EESYN1  1
-#define EESYN2  2
-#define EESYN3  3
-
-#define LFSRCTL _SFR_MEM8(0x15C)
-#define LFSRCT0 0
-
-/* Reserved [0x15D..0x160] */
-
-#define PCIFR   _SFR_MEM8(0x161)
-#define PCIF0   0
-#define PCIF1   1
-
-#define T0CR    _SFR_MEM8(0x162)
-#define T0PS0   0
-#define T0PS1   1
-#define T0PS2   2
-#define T0IE    3
-#define T0PR    4
-
-/* Reserved [0x163] */
-
-#define DBEND   _SFR_MEM8(0x164)
-
-#define TPCR1   _SFR_MEM8(0x165)
-#define TPQPLM  2
-#define TPBR    4
-#define TPDFCP0 5
-#define TPDFCP1 6
-#define TPMODE  7
-
-#define TPIMR   _SFR_MEM8(0x166)
-#define TPIM    0
-#define TPFTIM  1
-#define TPNFTIM 2
-#define TPBERIM 3
-
-#define TPDCR1  _SFR_MEM8(0x167)
-#define TPDCL10 0
-#define TPDCL11 1
-#define TPDCL12 2
-#define TPDCL13 3
-#define TPDCL14 4
-#define TPDCL15 5
-
-#define TPDCR2  _SFR_MEM8(0x168)
-#define TPDCL20 0
-#define TPDCL21 1
-#define TPDCL22 2
-#define TPDCL23 3
-#define TPDCL24 4
-#define TPDCL25 5
-
-#define TPDCR3  _SFR_MEM8(0x169)
-#define TPDCL30 0
-#define TPDCL31 1
-#define TPDCL32 2
-#define TPDCL33 3
-#define TPDCL34 4
-#define TPDCL35 5
-
-#define TPDCR4  _SFR_MEM8(0x16A)
-#define TPDCL40 0
-#define TPDCL41 1
-#define TPDCL42 2
-#define TPDCL43 3
-#define TPDCL44 4
-#define TPDCL45 5
-
-#define TPDCR5  _SFR_MEM8(0x16B)
-#define TPDCL50 0
-#define TPDCL51 1
-#define TPDCL52 2
-#define TPDCL53 3
-#define TPDCL54 4
-#define TPDCL55 5
-
-#define TPECR1  _SFR_MEM8(0x16C)
-#define TPECL10 0
-#define TPECL11 1
-#define TPECL12 2
-#define TPECL13 3
-#define TPECL14 4
-#define TPECL15 5
-#define TPECL16 6
-#define TPECL17 7
-
-#define TPECR2  _SFR_MEM8(0x16D)
-#define TPECL20 0
-#define TPECL21 1
-#define TPECL22 2
-#define TPECL23 3
-#define TPECL24 4
-#define TPECL25 5
-#define TPECL26 6
-#define TPECL27 7
-
-#define TPECR3  _SFR_MEM8(0x16E)
-#define TPECL30 0
-#define TPECL31 1
-#define TPECL32 2
-#define TPECL33 3
-#define TPECL34 4
-#define TPECL35 5
-#define TPECL36 6
-#define TPECL37 7
-
-#define TPECR4  _SFR_MEM8(0x16F)
-#define TPECL40 0
-#define TPECL41 1
-#define TPECL42 2
-#define TPECL43 3
-#define TPECL44 4
-#define TPECL45 5
-#define TPECL46 6
-#define TPECL47 7
-
-#define TPECMR  _SFR_MEM8(0x170)
-#define TPECM10 0
-#define TPECM11 1
-#define TPECM20 2
-#define TPECM21 3
-#define TPECM30 4
-#define TPECM31 5
-#define TPECM40 6
-#define TPECM41 7
-
-#define TPCR3   _SFR_MEM8(0x171)
-#define TPTD    0
-#define TPRD    1
-#define TPTLIW  2
-#define TPRCD   5
-
-#define TPCR4   _SFR_MEM8(0x172)
-#define TPBCCS0 0
-#define TPBCCS1 1
-#define TPBCCS2 2
-#define TPBCCS3 3
-#define TPBCM   4
-
-#define TPCR5   _SFR_MEM8(0x173)
-#define TPMUD0  0
-#define TPMUD1  1
-#define TPMUD2  2
-#define TPMD0   4
-#define TPMD1   5
-#define TPMD2   6
-
-/* Reserved [0x174] */
-
-#define TPCALR1 _SFR_MEM8(0x175)
-#define TPBG_IREF0 0
-#define TPBG_IREF1 1
-#define TPBG_IREF2 2
-#define TPBG_IREF3 3
-#define TPBG_IREF4 4
-#define TPBG_IREF5 5
-
-#define TPCALR2 _SFR_MEM8(0x176)
-#define TPBG_UREF0 0
-#define TPBG_UREF1 1
-#define TPBG_UREF2 2
-#define TPBG_UREF3 3
-#define TPBG_UREF4 4
-#define TPBG_UREF5 5
-#define TPBG_UREF6 6
-
-#define TPCALR3 _SFR_MEM8(0x177)
-#define LFVCC_TPCAL0 0
-#define LFVCC_TPCAL1 1
-#define LFVCC_TPCAL2 2
-#define TPORTH0 3
-#define TPORTH1 4
-
-#define TPCALR4 _SFR_MEM8(0x178)
-#define TPINIT_CAL0 0
-#define TPINIT_CAL1 1
-#define TPINIT_CAL2 2
-#define COMPVC_CAL0 3
-#define COMPVC_CAL1 4
-
-#define TPCALR5 _SFR_MEM8(0x179)
-
-#define TPCALR6 _SFR_MEM8(0x17A)
-
-#define TPCALR7 _SFR_MEM8(0x17B)
-
-#define TPCALR8 _SFR_MEM8(0x17C)
-
-#define TPCALR9 _SFR_MEM8(0x17D)
-
-#define TPCALR10 _SFR_MEM8(0x17E)
-
-#define AESDPR  _SFR_MEM8(0x17F)
-
-#define AESKR   _SFR_MEM8(0x180)
-
-#define AESDR   _SFR_MEM8(0x181)
-
-#define GPIOR3  _SFR_MEM8(0x182)
-
-#define GPIOR4  _SFR_MEM8(0x183)
-
-#define GPIOR5  _SFR_MEM8(0x184)
-
-#define GPIOR6  _SFR_MEM8(0x185)
-
-#define GPIOR7  _SFR_MEM8(0x186)
-
-#define GPIOR8  _SFR_MEM8(0x187)
-
-#define PHBCRR  _SFR_MEM8(0x188)
-
-/* Reserved [0x189..0x18D] */
-
-#define LFCPR   _SFR_MEM8(0x18E)
-#define LFCALP  0
-#define LFCALRY 1
-#define TPCD    6
-#define LFCPCE  7
-
-#define LFIMR   _SFR_MEM8(0x18F)
-#define LFSYDIM 0
-#define LFDEIM  1
-#define LFEOIM  2
-
-#define PHID0   _SFR_MEM16(0x190)
-
-#define PHID0L  _SFR_MEM8(0x194)
-
-#define PHID1   _SFR_MEM16(0x195)
-
-#define PHID1L  _SFR_MEM8(0x199)
-
-#define PHIDFR  _SFR_MEM8(0x19A)
-
-#define LFSYSY  _SFR_MEM16(0x19B)
-
-#define LFSYLE  _SFR_MEM8(0x19F)
-#define LFSYLE0 0
-#define LFSYLE1 1
-#define LFSYLE2 2
-#define LFSYLE3 3
-#define LFSYLE4 4
-#define LFSYLE5 5
-
-#define LFSTOP  _SFR_MEM8(0x1A0)
-#define LFSTSY0 0
-#define LFSTSY1 1
-#define LFSTSY2 2
-#define LFSTSY3 3
-#define LFSTL0  4
-#define LFSTL1  5
-#define LFSTL2  6
-
-#define LTCOR   _SFR_MEM8(0x1A1)
-
-#define T1IFR   _SFR_MEM8(0x1A2)
-#define T1OFF   0
-#define T1COF   1
-
-/* Reserved [0x1A3] */
-
-#define PHTBLR  _SFR_MEM8(0x1A4)
-
-#define PHDFR   _SFR_MEM8(0x1A5)
-
-#define LTEMR   _SFR_MEM8(0x1A6)
-#define ID0EM   0
-#define ID1EM   1
-#define IDFEM   2
-#define DFEM    3
-#define TBLEM   4
-#define FLEM    5
-#define EOFEM   6
-#define LTCOF   7
-
-#define LFQC3   _SFR_MEM8(0x1A7)
-#define LFQS30  0
-#define LFQS31  1
-#define LFQS32  2
-#define LFQS33  3
-#define LFCS30  4
-#define LFCS31  5
-#define LFCS32  6
-#define LFCS33  7
-
-#define LFQC2   _SFR_MEM8(0x1A8)
-#define LFQS20  0
-#define LFQS21  1
-#define LFQS22  2
-#define LFQS23  3
-#define LFCS20  4
-#define LFCS21  5
-#define LFCS22  6
-#define LFCS23  7
-
-#define LFQC1   _SFR_MEM8(0x1A9)
-#define LFQS10  0
-#define LFQS11  1
-#define LFQS12  2
-#define LFQS13  3
-#define LFCS10  4
-#define LFCS11  5
-#define LFCS12  6
-#define LFCS13  7
-
-#define TW2BR   _SFR_MEM8(0x1AA)
-
-#define TW2CR   _SFR_MEM8(0x1AB)
-#define TW2IE   0
-#define TW2EN   2
-#define TW2WC   3
-#define TW2STO  4
-#define TW2STA  5
-#define TW2EA   6
-#define TW2INT  7
-
-#define TW2SR   _SFR_MEM8(0x1AC)
-#define TW2PS0  0
-#define TW2PS1  1
-#define TW2S0   3
-#define TW2S1   4
-#define TW2S2   5
-#define TW2S3   6
-#define TW2S4   7
-
-#define TW2DR   _SFR_MEM8(0x1AD)
-
-#define TW2AR   _SFR_MEM8(0x1AE)
-#define TW2GCE  0
-#define TW2A0   1
-#define TW2A1   2
-#define TW2A2   3
-#define TW2A3   4
-#define TW2A4   5
-#define TW2A5   6
-#define TW2A6   7
-
-#define TW2AMR  _SFR_MEM8(0x1AF)
-#define TW2AM0  1
-#define TW2AM1  2
-#define TW2AM2  3
-#define TW2AM3  4
-#define TW2AM4  5
-#define TW2AM5  6
-#define TW2AM6  7
-
-#define RSCR    _SFR_MEM8(0x1B0)
-#define RSSDEN  0
-#define RSOS    1
-#define RSEOR   2
-#define RSOFM   3
-#define RSMODE0 4
-#define RSMODE1 5
-#define RSRES   7
-
-#define RSSR    _SFR_MEM8(0x1B1)
-#define RSRDY   0
-#define RSSVLD  1
-
-#define RSMS1R  _SFR_MEM8(0x1B2)
-#define RSCH1E  0
-#define RSCH2E  1
-#define RSCH3E  2
-#define RSINTM  3
-#define RSSTIM  4
-#define RSCMS   5
-#define RSSSV   6
-#define RSSCAL  7
-
-#define RSMS2R  _SFR_MEM8(0x1B3)
-#define RSSADR0 0
-#define RSSADR1 1
-#define RSSADR2 2
-#define RSSADR3 3
-#define RSAVGS0 4
-#define RSAVGS1 5
-#define RSAVGS2 6
-#define RSAVGS3 7
-
-#define RSFR    _SFR_MEM8(0x1B4)
-#define RSOOR1  0
-#define RSOOR2  1
-#define RSOOR3  2
-#define RSOFF   3
-#define RSAOOR1 5
-#define RSAOOR2 6
-#define RSAOOR3 7
-
-/* Reserved [0x1B5] */
-
-#define RSCALIB _SFR_MEM8(0x1B6)
-#define RSCALIB0 0
-#define RSCALIB1 1
-#define RSCALIB2 2
-#define RSCALIB3 3
-#define RSCALIB4 4
-#define RSCALIB5 5
-#define RSCALIB6 6
-#define RSCALIB7 7
-
-#define RSDLYR  _SFR_MEM8(0x1B7)
-#define RSTRD0  0
-#define RSTRD1  1
-#define RSTRD2  2
-#define RSTRD3  3
-#define RSTRD4  4
-#define RSTRD5  5
-#define RSRD0   6
-#define RSRD1   7
-
-#define RSRES1L _SFR_MEM8(0x1B8)
-#define RSRES1L0 0
-#define RSRES1L1 1
-#define RSRES1L2 2
-#define RSRES1L3 3
-#define RSRES1L4 4
-#define RSRES1L5 5
-#define RSRES1L6 6
-#define RSRES1L7 7
-
-#define RSRES1H _SFR_MEM8(0x1B9)
-#define RSRES1H0 0
-#define RSRES1H1 1
-#define RSRES1H2 2
-#define RSRES1H3 3
-#define RSRES1H4 4
-#define RSRES1H5 5
-#define RSRES1H6 6
-#define RSRES1H7 7
-
-#define RSRES2L _SFR_MEM8(0x1BA)
-#define RSRES2L0 0
-#define RSRES2L1 1
-#define RSRES2L2 2
-#define RSRES2L3 3
-#define RSRES2L4 4
-#define RSRES2L5 5
-#define RSRES2L6 6
-#define RSRES2L7 7
-
-#define RSRES2H _SFR_MEM8(0x1BB)
-#define RSRES2H0 0
-#define RSRES2H1 1
-#define RSRES2H2 2
-#define RSRES2H3 3
-#define RSRES2H4 4
-#define RSRES2H5 5
-#define RSRES2H6 6
-#define RSRES2H7 7
-
-#define RSRES3L _SFR_MEM8(0x1BC)
-#define RSRES3L0 0
-#define RSRES3L1 1
-#define RSRES3L2 2
-#define RSRES3L3 3
-#define RSRES3L4 4
-#define RSRES3L5 5
-#define RSRES3L6 6
-#define RSRES3L7 7
-
-#define RSRES3H _SFR_MEM8(0x1BD)
-#define RSRES3H0 0
-#define RSRES3H1 1
-#define RSRES3H2 2
-#define RSRES3H3 3
-#define RSRES3H4 4
-#define RSRES3H5 5
-#define RSRES3H6 6
-#define RSRES3H7 7
-
-#define RSRES4L _SFR_MEM8(0x1BE)
-#define RSRES4L0 0
-#define RSRES4L1 1
-#define RSRES4L2 2
-#define RSRES4L3 3
-#define RSRES4L4 4
-#define RSRES4L5 5
-#define RSRES4L6 6
-#define RSRES4L7 7
-
-#define RSRES4H _SFR_MEM8(0x1BF)
-#define RSRES4H0 0
-#define RSRES4H1 1
-#define RSRES4H2 2
-#define RSRES4H3 3
-#define RSRES4H4 4
-#define RSRES4H5 5
-#define RSRES4H6 6
-#define RSRES4H7 7
-
-#define RSSRCR  _SFR_MEM8(0x1C0)
-#define SRCMODE0 0
-#define SRCMODE1 1
-#define SRCMIN0 2
-#define SRCMIN1 3
-#define SRCCLR  4
-#define SRCSTEP0 6
-#define SRCSTEP1 7
-
-#define SD12RR  _SFR_MEM8(0x1C1)
-#define SD12RR0 0
-#define SD12RR1 1
-#define SD12RR2 2
-#define SD12RR3 3
-#define SD12RR4 4
-#define SD12RR5 5
-#define SD12RR6 6
-#define SD12RR7 7
-
-#define SD13RR  _SFR_MEM8(0x1C2)
-#define SD13RR0 0
-#define SD13RR1 1
-#define SD13RR2 2
-#define SD13RR3 3
-#define SD13RR4 4
-#define SD13RR5 5
-#define SD13RR6 6
-#define SD13RR7 7
-
-#define SD23RR  _SFR_MEM8(0x1C3)
-#define SD23RR0 0
-#define SD23RR1 1
-#define SD23RR2 2
-#define SD23RR3 3
-#define SD23RR4 4
-#define SD23RR5 5
-#define SD23RR6 6
-#define SD23RR7 7
-
-#define SD360R  _SFR_MEM8(0x1C4)
-#define SD360R0 0
-#define SD360R1 1
-#define SD360R2 2
-#define SD360R3 3
-#define SD360R4 4
-#define SD360R5 5
-#define SD360R6 6
-#define SD360R7 7
-
-#define RSDBGR  _SFR_MEM8(0x1C5)
-#define RSSANA  0
-#define RSINFM  2
-#define RSFPD   3
-#define RSHOME  4
-#define RSDBGS0 5
-#define RSDBGS1 6
-#define RSDBGEN 7
-
-/* Reserved [0x1C6..0x1D0] */
-
-#define LDFS    _SFR_MEM8(0x1D1)
-#define LDFFLR  0
-#define LDFUF   1
-#define LDFOF   2
-
-#define T4IFR   _SFR_MEM8(0x1D2)
-#define T4OFF   0
-#define T4COF   1
-#define T4ICF   2
-
-#define LDFWP   _SFR_MEM8(0x1D3)
-#define LDFWP0  0
-#define LDFWP1  1
-#define LDFWP2  2
-#define LDFWP3  3
-#define LDFWP4  4
-#define LDFWP5  5
-
-#define LDFRP   _SFR_MEM8(0x1D4)
-#define LDFRP0  0
-#define LDFRP1  1
-#define LDFRP2  2
-#define LDFRP3  3
-#define LDFRP4  4
-#define LDFRP5  5
-
-#define T5IFR   _SFR_MEM8(0x1D5)
-#define T5OFF   0
-#define T5COF   1
-
-#define LDFIM   _SFR_MEM8(0x1D6)
-#define LDFFLIM 0
-#define LDFEIM  1
-
-#define LDFC    _SFR_MEM8(0x1D7)
-#define LDFFLC0 0
-#define LDFFLC1 1
-#define LDFFLC2 2
-#define LDFFLC3 3
-#define LDFFLC4 4
-#define LDFFLC5 5
-#define LDFMSB  6
-
-#define PHIMR   _SFR_MEM8(0x1D8)
-#define PHTBLIM 1
-#define PHDFIM  2
-#define PHIDFIM 3
-#define PHID0IM 4
-#define PHID1IM 5
-
-#define PHCRCR  _SFR_MEM8(0x1D9)
-#define CRCFR   2
-#define CRCSE0  4
-#define CRCSE1  5
-#define CRCEN   7
-
-#define PHCST   _SFR_MEM8(0x1DA)
-
-/* Reserved [0x1DB] */
-
-/* Combine PHCRPL and PHCRPH */
-#define PHCRP   _SFR_MEM16(0x1DC)
-
-#define PHCRPL  _SFR_MEM8(0x1DC)
-#define PHCRPH  _SFR_MEM8(0x1DD)
-
-#define PHCSR   _SFR_MEM8(0x1DE)
-
-/* Reserved [0x1DF] */
-
-#define CRCDIR  _SFR_MEM8(0x1E0)
-
-#define T3IFR   _SFR_MEM8(0x1E1)
-#define T3OFF   0
-#define T3COF   1
-#define T3ICF   2
-
-/* Reserved [0x1E2] */
-
-#define CMCR    _SFR_MEM8(0x1E3)
-#define CMM0    0
-#define CMM1    1
-#define CMM2    2
-#define CCS     3
-#define CMONEN  6
-#define CMCCE   7
-
-#define CMIMR   _SFR_MEM8(0x1E4)
-#define ECIE    0
-
-#define CLPR    _SFR_MEM8(0x1E5)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLTPS0  3
-#define CLTPS1  4
-#define CLTPS2  5
-#define CLPCE   7
-
-#define VMCR    _SFR_MEM8(0x1E6)
-#define VMLS0   0
-#define VMLS1   1
-#define VMLS2   2
-#define VMLS3   3
-#define VMIM    4
-#define VMPS0   5
-#define VMPS1   6
-#define VMRS    7
-
-#define DBONDR  _SFR_MEM8(0x1E7)
-#define BBESD   0
-#define AGND_BB 1
-#define ISO_GND 2
-#define AGND_LF 3
-#define BTEST4  4
-#define BTEST5  5
-#define BTEST6  6
-
-#define CALRDYLF _SFR_MEM8(0x1E8)
-
-#define TW1BR   _SFR_MEM8(0x1E9)
-
-#define TW1CR   _SFR_MEM8(0x1EA)
-#define TW1IE   0
-#define TW1EN   2
-#define TW1WC   3
-#define TW1STO  4
-#define TW1STA  5
-#define TW1EA   6
-#define TW1INT  7
-
-#define TW1SR   _SFR_MEM8(0x1EB)
-#define TW1PS0  0
-#define TW1PS1  1
-#define TW1S0   3
-#define TW1S1   4
-#define TW1S2   5
-#define TW1S3   6
-#define TW1S4   7
-
-#define TW1DR   _SFR_MEM8(0x1EC)
-
-#define TW1AR   _SFR_MEM8(0x1ED)
-#define TW1GCE  0
-#define TW1A0   1
-#define TW1A1   2
-#define TW1A2   3
-#define TW1A3   4
-#define TW1A4   5
-#define TW1A5   6
-#define TW1A6   7
-
-#define TW1AMR  _SFR_MEM8(0x1EE)
-#define TW1AM0  1
-#define TW1AM1  2
-#define TW1AM2  3
-#define TW1AM3  4
-#define TW1AM4  5
-#define TW1AM5  6
-#define TW1AM6  7
-
-#define PDSCR   _SFR_MEM8(0x1EF)
-#define PDSC0   0
-#define PDSC1   1
-#define PDSC2   2
-#define PDSC3   3
-#define PDSC4   4
-#define STBTEST 5
-#define RSSISEL 6
-#define ATBSEL  7
-
-#define TMOCR   _SFR_MEM8(0x1F0)
-#define TO1PIS0 0
-#define TO1PIS1 1
-#define TO2PIS0 2
-#define TO2PIS1 3
-#define TO3PIS0 4
-#define TO3PIS1 5
-#define TO4PIS0 6
-#define TO4PIS1 7
-
-#define SRCCAL  _SFR_MEM8(0x1F1)
-#define SRCCAL1 0
-#define SRCCAL2 1
-#define SRCCAL3 2
-#define SRCCAL4 3
-#define SRCCAL5 4
-#define SRCCAL6 5
-#define SRCCAL7 6
-#define SRCCAL8 7
-
-#define SRCTCAL _SFR_MEM8(0x1F2)
-#define SRCTC0  0
-#define SRCTC1  1
-#define SRCTC2  2
-#define SRCS0   3
-#define SRCS1   4
-#define DIS_SRC 6
-#define HOLD_SRC 7
-
-#define SUPCA5  _SFR_MEM8(0x1F3)
-#define IPTAT0  0
-#define IPTAT1  1
-#define IPTAT2  2
-#define IPTAT3  3
-#define IPTAT4  4
-#define IPTAT5  5
-
-#define SUPCA6  _SFR_MEM8(0x1F4)
-#define VBGTR0  0
-#define VBGTR1  1
-#define VBGTR2  2
-#define VBGTR3  3
-#define VBGTR4  4
-#define VBGTR5  5
-#define VBGTR6  6
-#define VBGTR7  7
-
-#define SUPCA7  _SFR_MEM8(0x1F5)
-#define VCCCAL0 0
-#define VCCCAL1 1
-#define VCCCAL2 2
-#define LFVCCBD0 3
-#define LFVCCBD1 4
-#define LFVCCBD2 5
-
-#define SUPCA8  _SFR_MEM8(0x1F6)
-#define VSWBD0  0
-#define VSWBD1  1
-#define VSWBD2  2
-#define DVCCBD0 3
-#define DVCCBD1 4
-#define DVCCBD2 5
-
-#define SUPCA9  _SFR_MEM8(0x1F7)
-#define VMEM0   0
-#define VMEM1   1
-#define VMEM2   2
-#define VMEM3   3
-#define VMEM4   4
-#define VMEM5   5
-#define VMEM6   6
-#define VMEM7   7
-
-#define SUPCA10 _SFR_MEM8(0x1F8)
-
-#define TPCALR11 _SFR_MEM8(0x1F9)
-#define MTBTR0  0
-#define MTBTR1  1
-#define ENDVBD  2
-#define ENLFBD  3
-#define ENVSWBD 4
-#define TPCALR115 5
-#define TPCALR116 6
-#define TPCALR117 7
-
-#define TPCALR12 _SFR_MEM8(0x1FA)
-#define TPDMOD  0
-#define TPCALR121 1
-#define TPCALR122 2
-#define TPCALR123 3
-#define TPCALR124 4
-#define TPCALR125 5
-#define TPCALR126 6
-#define TPCALR127 7
-
-#define TPCALR13 _SFR_MEM8(0x1FB)
-
-/* Reserved [0x1FC..0x1FD] */
-
-#define PMTER   _SFR_MEM8(0x1FE)
-
-#define SRCCALL _SFR_MEM8(0x1FF)
-#define SRCCAL0 0
-
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCI0_vect            _VECTOR(3)
-#define PCI0_vect_num        3
-
-/* Pin Change Interrupt Request 1 */
-#define PCI1_vect            _VECTOR(4)
-#define PCI1_vect_num        4
-
-/* Voltage Monitoring Interrupt */
-#define VMON_vect            _VECTOR(5)
-#define VMON_vect_num        5
-
-/* AVCC Reset Interrupt */
-#define AVCCR_vect            _VECTOR(6)
-#define AVCCR_vect_num        6
-
-/* AVCC Low Interrupt */
-#define AVCCL_vect            _VECTOR(7)
-#define AVCCL_vect_num        7
-
-/* Timer0 Interval Interrupt */
-#define T0INT_vect            _VECTOR(8)
-#define T0INT_vect_num        8
-
-/* Timer/Counter1 Compare Match Interrupt */
-#define T1COMP_vect            _VECTOR(9)
-#define T1COMP_vect_num        9
-
-/* Timer/Counter1 Overflow Interrupt */
-#define T1OVF_vect            _VECTOR(10)
-#define T1OVF_vect_num        10
-
-/* Timer/Counter2 Compare Match Interrupt */
-#define T2COMP_vect            _VECTOR(11)
-#define T2COMP_vect_num        11
-
-/* Timer/Counter2 Overflow Interrupt */
-#define T2OVF_vect            _VECTOR(12)
-#define T2OVF_vect_num        12
-
-/* Timer/Counter3 Capture Event Interrupt */
-#define T3CAP_vect            _VECTOR(13)
-#define T3CAP_vect_num        13
-
-/* Timer/Counter3 Compare Match Interrupt */
-#define T3COMP_vect            _VECTOR(14)
-#define T3COMP_vect_num        14
-
-/* Timer/Counter3 Overflow Interrupt */
-#define T3OVF_vect            _VECTOR(15)
-#define T3OVF_vect_num        15
-
-/* Timer/Counter4 Capture Event Interrupt */
-#define T4CAP_vect            _VECTOR(16)
-#define T4CAP_vect_num        16
-
-/* Timer/Counter4 Compare Match Interrupt */
-#define T4COMP_vect            _VECTOR(17)
-#define T4COMP_vect_num        17
-
-/* Timer/Counter4 Overflow Interrupt */
-#define T4OVF_vect            _VECTOR(18)
-#define T4OVF_vect_num        18
-
-/* Timer/Counter5 Compare Match Interrupt */
-#define T5COMP_vect            _VECTOR(19)
-#define T5COMP_vect_num        19
-
-/* Timer/Counter5 Overflow Interrupt */
-#define T5OVF_vect            _VECTOR(20)
-#define T5OVF_vect_num        20
-
-/* SPI Serial Transfer Complete Interrupt */
-#define SPI_vect            _VECTOR(21)
-#define SPI_vect_num        21
-
-/* SPI Rx Buffer Interrupt */
-#define SRX_FIFO_vect            _VECTOR(22)
-#define SRX_FIFO_vect_num        22
-
-/* SPI Tx Buffer Interrupt */
-#define STX_FIFO_vect            _VECTOR(23)
-#define STX_FIFO_vect_num        23
-
-/* Sequencer State Machine Interrupt */
-#define SSM_vect            _VECTOR(24)
-#define SSM_vect_num        24
-
-/* Data FIFO fill level reached Interrupt */
-#define DFFLR_vect            _VECTOR(25)
-#define DFFLR_vect_num        25
-
-/* Data FIFO overflow or underflow error Interrupt */
-#define DFOUE_vect            _VECTOR(26)
-#define DFOUE_vect_num        26
-
-/* RSSI/Preamble FIFO fill level reached Interrupt */
-#define SFFLR_vect            _VECTOR(27)
-#define SFFLR_vect_num        27
-
-/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
-#define SFOUE_vect            _VECTOR(28)
-#define SFOUE_vect_num        28
-
-/* Tx Modulator Telegram Finish Interrupt */
-#define TMTCF_vect            _VECTOR(29)
-#define TMTCF_vect_num        29
-
-/* AES Krypto Unit Interrupt */
-#define AES_vect            _VECTOR(30)
-#define AES_vect_num        30
-
-/* Transponder Mode Interrupt */
-#define TPINT_vect            _VECTOR(31)
-#define TPINT_vect_num        31
-
-/* Transponder Timeout Error Interrupt */
-#define TPTOERR_vect            _VECTOR(32)
-#define TPTOERR_vect_num        32
-
-/* LF receiver Identifier 0 Interrupt */
-#define LFID0INT_vect            _VECTOR(33)
-#define LFID0INT_vect_num        33
-
-/* LF receiver Identifier 1 Interrupt */
-#define LFID1INT_vect            _VECTOR(34)
-#define LFID1INT_vect_num        34
-
-/* LF receiver Frame End Interrupt */
-#define LFFEINT_vect            _VECTOR(35)
-#define LFFEINT_vect_num        35
-
-/* LF receiver Bit Count Reached Interrupt */
-#define LFBCR_vect            _VECTOR(36)
-#define LFBCR_vect_num        36
-
-/* LF receiver PreBurst Detected Interrupt */
-#define LFPBD_vect            _VECTOR(37)
-#define LFPBD_vect_num        37
-
-/* LF receiver Decoder Error Interrupt */
-#define LFDE_vect            _VECTOR(38)
-#define LFDE_vect_num        38
-
-/* LF receiver End of Telegram Interrupt */
-#define LFEOT_vect            _VECTOR(39)
-#define LFEOT_vect_num        39
-
-/* LF receiver Timer Compare Match Interrupt */
-#define LFTCOR_vect            _VECTOR(40)
-#define LFTCOR_vect_num        40
-
-/* LF receiver RSSI measurement Interrupt */
-#define LFRSCO_vect            _VECTOR(41)
-#define LFRSCO_vect_num        41
-
-/* LF Data FIFO Fill Level Reached Interrupt */
-#define LDFFLR_vect            _VECTOR(42)
-#define LDFFLR_vect_num        42
-
-/* LF Data FIFO Overflow or Underflow Error Interrupt */
-#define LDFOUE_vect            _VECTOR(43)
-#define LDFOUE_vect_num        43
-
-/* External input Clock monitoring Interrupt */
-#define EXCM_vect            _VECTOR(44)
-#define EXCM_vect_num        44
-
-/* EEPROM Error Correction Interrupt */
-#define E2CINT_vect            _VECTOR(45)
-#define E2CINT_vect_num        45
-
-/* EEPROM Ready Interrupt */
-#define ERDY_vect            _VECTOR(46)
-#define ERDY_vect_num        46
-
-/* Store Program Memory Ready */
-#define SPMR_vect            _VECTOR(47)
-#define SPMR_vect_num        47
-
-/* TWI1 Interrupt */
-#define TWI1_vect            _VECTOR(48)
-#define TWI1_vect_num        48
-
-/* SPI2 Interrupt */
-#define SPI2_vect            _VECTOR(49)
-#define SPI2_vect_num        49
-
-/* TWI2 Interrupt */
-#define TWI2_vect            _VECTOR(50)
-#define TWI2_vect_num        50
-
-#define _VECTORS_SIZE 204
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x8000
-#define FLASHEND     0xFFFF
-#define RAMSTART     0x0200
-#define RAMSIZE      1024
-#define RAMEND       0x05FF
-#define E2START     0
-#define E2SIZE      2304
-#define E2PAGESIZE  16
-#define E2END       0x08FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Fuse Byte */
-#define FUSE_EXTCLKEN    (unsigned char)~_BV(0)
-#define FUSE_EEACC       (unsigned char)~_BV(1)
-#define FUSE_BOOTRST     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x69
-
-
-#endif /* #ifdef _AVR_ATA5702M322_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5702M322_H_INCLUDED
+#define _AVR_ATA5702M322_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5702m322.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define GPIOR0  _SFR_IO8(0x00)
+
+#define PRR1    _SFR_IO8(0x01)
+#define PRT1    0
+#define PRT2    1
+#define PRT3    2
+#define PRT4    3
+#define PRT5    4
+#define PRLFR   5
+#define PRLFTP  6
+#define PRLFPH  7
+
+#define __AVR_HAVE_PRR1	((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5)|(1<<PRLFR)|(1<<PRLFTP)|(1<<PRLFPH))
+#define __AVR_HAVE_PRR1_PRT1
+#define __AVR_HAVE_PRR1_PRT2
+#define __AVR_HAVE_PRR1_PRT3
+#define __AVR_HAVE_PRR1_PRT4
+#define __AVR_HAVE_PRR1_PRT5
+#define __AVR_HAVE_PRR1_PRLFR
+#define __AVR_HAVE_PRR1_PRLFTP
+#define __AVR_HAVE_PRR1_PRLFPH
+
+#define PRR2    _SFR_IO8(0x02)
+#define PRSPI2  0
+#define PRTWI2  1
+#define PRSF    2
+#define PRDF    3
+#define VXTSDI  4
+#define PRTM    6
+#define PRSSM   7
+
+#define __AVR_HAVE_PRR2	((1<<PRSPI2)|(1<<PRTWI2)|(1<<PRSF)|(1<<PRDF)|(1<<VXTSDI)|(1<<PRTM)|(1<<PRSSM))
+#define __AVR_HAVE_PRR2_PRSPI2
+#define __AVR_HAVE_PRR2_PRTWI2
+#define __AVR_HAVE_PRR2_PRSF
+#define __AVR_HAVE_PRR2_PRDF
+#define __AVR_HAVE_PRR2_VXTSDI
+#define __AVR_HAVE_PRR2_PRTM
+#define __AVR_HAVE_PRR2_PRSSM
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define TPCR2   _SFR_IO8(0x0C)
+#define TPMA    0
+#define TPMOD   1
+#define TPPSD   2
+#define TPD     3
+#define TPNFTO  4
+#define TPWDLV0 5
+#define TPWDLV1 6
+
+#define TPFR    _SFR_IO8(0x0D)
+#define TPF     0
+#define TPFTF   1
+#define TPNFTF  2
+#define TPBERF  3
+
+#define MCUCR   _SFR_IO8(0x0E)
+#define IVL0    0
+#define IVL1    1
+#define SPIIO   2
+#define ENPS    3
+#define PUD     4
+#define TRCCE   5
+#define TRCEN   6
+#define IVSEL   7
+
+#define FSCR    _SFR_IO8(0x0F)
+#define TXMOD   0
+#define SFM     1
+#define TXMS0   2
+#define TXMS1   3
+#define PAOER   4
+#define PAON    7
+
+/* Reserved [0x10] */
+
+#define T1CR    _SFR_IO8(0x11)
+#define T1OTM   0
+#define T1CTM   1
+#define T1CRM   2
+#define T1TOP   4
+#define T1RES   5
+#define T1TOS   6
+#define T1ENA   7
+
+#define T2CR    _SFR_IO8(0x12)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2TOP   4
+#define T2RES   5
+#define T2TOS   6
+#define T2ENA   7
+
+#define T3CR    _SFR_IO8(0x13)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3TOS   6
+#define T3ENA   7
+
+#define T4CR    _SFR_IO8(0x14)
+#define T4OTM   0
+#define T4CTM   1
+#define T4CRM   2
+#define T4CPRM  3
+#define T4TOP   4
+#define T4RES   5
+#define T4TOS   6
+#define T4ENA   7
+
+#define LTCMR   _SFR_IO8(0x15)
+#define LTPS0   0
+#define LTPS1   1
+#define LTPS2   2
+#define LTCRM   3
+#define LTCIM   4
+#define LTCM    5
+#define LTSM    6
+#define LTENA   7
+
+#define EECR2   _SFR_IO8(0x16)
+#define EEBRE   0
+#define E2CIM   1
+#define E2AVF   5
+#define E2FF    6
+#define E2CF    7
+
+#define PHTCR   _SFR_IO8(0x17)
+#define FRFIFO  5
+#define CPM     6
+#define CSM     7
+
+#define LDFFL   _SFR_IO8(0x18)
+#define LDFFL0  0
+#define LDFFL1  1
+#define LDFFL2  2
+#define LDFFL3  3
+#define LDFFL4  4
+#define LDFFL5  5
+#define LDFCLR  7
+
+#define LDFD    _SFR_IO8(0x19)
+
+#define PRR0    _SFR_IO8(0x1A)
+#define PRSPI   0
+#define PRLFRS  1
+#define PRTXDC  2
+#define PRCRC   3
+#define PRVM    4
+#define PRCO    5
+#define PRCU    6
+#define PRTWI1  7
+
+#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRLFRS)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO)|(1<<PRCU)|(1<<PRTWI1))
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRLFRS
+#define __AVR_HAVE_PRR0_PRTXDC
+#define __AVR_HAVE_PRR0_PRCRC
+#define __AVR_HAVE_PRR0_PRVM
+#define __AVR_HAVE_PRR0_PRCO
+#define __AVR_HAVE_PRR0_PRCU
+#define __AVR_HAVE_PRR0_PRTWI1
+
+#define PHFR    _SFR_IO8(0x1B)
+#define CRCEF   0
+#define PHTBLF  1
+#define PHDFF   2
+#define PHIDFF  3
+#define PHID0F  4
+#define PHID1F  5
+
+#define LFFR    _SFR_IO8(0x1C)
+#define LFSYDF  0
+#define LFDEF   1
+#define LFEOF   2
+#define LFTOF   3
+#define LFSD    6
+#define LFES    7
+
+#define AESCR   _SFR_IO8(0x1D)
+#define AESWK   0
+#define AESWD   1
+#define AESIM   2
+#define AESD    3
+#define AESXOR  4
+#define AESRES  5
+#define AESLKM  6
+#define AESE    7
+
+#define AESSR   _SFR_IO8(0x1E)
+#define AESRF   0
+#define AESERF  7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EEPAGE  6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define GPIOR1  _SFR_IO8(0x24)
+
+#define GPIOR2  _SFR_IO8(0x25)
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+#define INT1    1
+
+#define EIFR    _SFR_IO8(0x28)
+#define INTF0   0
+#define INTF1   1
+
+#define LDFCKSW _SFR_IO8(0x29)
+#define LDFSCSW 0
+#define LDFSCKS 1
+
+#define VMSCR   _SFR_IO8(0x2A)
+#define VMF     0
+#define VMDIH   1
+
+#define MCUSR   _SFR_IO8(0x2B)
+#define PORF    0
+#define EXTRF   1
+#define WDRF    3
+#define DWRF    4
+#define TPRF    5
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define RXIF    4
+#define TXIF    5
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define LFCR0   _SFR_IO8(0x2F)
+#define LFCE1   0
+#define LFCE2   1
+#define LFCE3   2
+#define LFBR0   3
+#define LFBR1   4
+#define LFMG    5
+#define LFRRT0  6
+#define LFRRT1  7
+
+#define LFCR1   _SFR_IO8(0x30)
+#define RSST0   0
+#define RSST1   1
+#define LFFM1   2
+#define ARMDE   3
+#define FLLEN   4
+#define ADTHEN  5
+#define LFPEEN  6
+#define LFRE    7
+
+#define DWDR    _SFR_IO8(0x31)
+
+#define T0IFR   _SFR_IO8(0x32)
+#define T0F     0
+
+/* Reserved [0x33..0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define FLSEL0  3
+#define FLSEL1  4
+#define FLSEL2  5
+#define RWWSB   6
+#define SPMIE   7
+
+#define SMCR    _SFR_IO8(0x38)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define TPSR    _SFR_IO8(0x39)
+#define TPA     0
+#define TPGAP   1
+#define TPPSW   2
+#define TPBCOK  3
+
+#define LFCR2   _SFR_IO8(0x3A)
+#define LFSEN0  0
+#define LFSEN1  1
+#define LFDAMP  2
+#define LFVC0   5
+#define LFVC1   6
+#define LFVC2   7
+
+#define LFCR3   _SFR_IO8(0x3B)
+#define LFRCTEN 0
+#define LFRCPCEN 1
+#define LFRCPM  2
+#define LFTON   3
+#define LFTS0   4
+#define LFTS1   5
+#define LFTS2   6
+#define LFSBEN  7
+
+/* Reserved [0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define FSEN    _SFR_MEM8(0x60)
+#define SDPU    0
+#define SDEN    1
+#define GAEN    2
+#define PEEN    3
+#define ASEN    4
+#define ANTT    5
+
+#define FSFCR   _SFR_MEM8(0x61)
+#define BTSEL0  0
+#define BTSEL1  1
+#define ASDIV0  4
+#define ASDIV1  5
+#define ASDIV2  6
+#define ASDIV3  7
+
+/* Combine GACDIVL and GACDIVH */
+#define GACDIV  _SFR_MEM16(0x62)
+
+#define GACDIVL _SFR_MEM8(0x62)
+#define GACDIVH _SFR_MEM8(0x63)
+
+#define FFREQ1L _SFR_MEM8(0x64)
+
+#define FFREQ1M _SFR_MEM8(0x65)
+
+#define FFREQ1H _SFR_MEM8(0x66)
+
+#define FFREQ2L _SFR_MEM8(0x67)
+
+#define FFREQ2M _SFR_MEM8(0x68)
+
+#define FFREQ2H _SFR_MEM8(0x69)
+
+#define BBTE2   _SFR_MEM8(0x6A)
+#define TDEPO   0
+#define DITDIS  1
+
+#define EICRA   _SFR_MEM8(0x6B)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+#define PCMSK0  _SFR_MEM8(0x6C)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6D)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define WDTCR   _SFR_MEM8(0x6E)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+#define T1CNT   _SFR_MEM8(0x6F)
+
+#define T1COR   _SFR_MEM8(0x70)
+
+#define T1MR    _SFR_MEM8(0x71)
+#define T1CS0   0
+#define T1CS1   1
+#define T1PS0   2
+#define T1PS1   3
+#define T1PS2   4
+#define T1PS3   5
+#define T1DC0   6
+#define T1DC1   7
+
+#define T1IMR   _SFR_MEM8(0x72)
+#define T1OIM   0
+#define T1CIM   1
+
+#define T2CNT   _SFR_MEM8(0x73)
+
+#define T2COR   _SFR_MEM8(0x74)
+
+#define T2MR    _SFR_MEM8(0x75)
+#define T2CS0   0
+#define T2CS1   1
+#define T2PS0   2
+#define T2PS1   3
+#define T2PS2   4
+#define T2PS3   5
+#define T2DC0   6
+#define T2DC1   7
+
+#define T2IMR   _SFR_MEM8(0x76)
+#define T2OIM   0
+#define T2CIM   1
+
+/* Combine T3CNTL and T3CNTH */
+#define T3CNT   _SFR_MEM16(0x77)
+
+#define T3CNTL  _SFR_MEM8(0x77)
+#define T3CNTH  _SFR_MEM8(0x78)
+
+/* Combine T3CORL and T3CORH */
+#define T3COR   _SFR_MEM16(0x79)
+
+#define T3CORL  _SFR_MEM8(0x79)
+#define T3CORH  _SFR_MEM8(0x7A)
+
+/* Combine T3ICRL and T3ICRH */
+#define T3ICR   _SFR_MEM16(0x7B)
+
+#define T3ICRL  _SFR_MEM8(0x7B)
+#define T3ICRH  _SFR_MEM8(0x7C)
+
+#define T3MRA   _SFR_MEM8(0x7D)
+#define T3CS0   0
+#define T3CS1   1
+#define T3PS0   2
+#define T3PS1   3
+#define T3PS2   4
+
+#define T3MRB   _SFR_MEM8(0x7E)
+#define T3SCE   1
+#define T3CNC   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3ICS0  5
+#define T3ICS1  6
+#define T3ICS2  7
+
+#define T3IMR   _SFR_MEM8(0x7F)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+
+/* Combine T4CNTL and T4CNTH */
+#define T4CNT   _SFR_MEM16(0x80)
+
+#define T4CNTL  _SFR_MEM8(0x80)
+#define T4CNTH  _SFR_MEM8(0x81)
+
+/* Combine T4CORL and T4CORH */
+#define T4COR   _SFR_MEM16(0x82)
+
+#define T4CORL  _SFR_MEM8(0x82)
+#define T4CORH  _SFR_MEM8(0x83)
+
+/* Combine T4ICRL and T4ICRH */
+#define T4ICR   _SFR_MEM16(0x84)
+
+#define T4ICRL  _SFR_MEM8(0x84)
+#define T4ICRH  _SFR_MEM8(0x85)
+
+#define T4MRA   _SFR_MEM8(0x86)
+#define T4CS0   0
+#define T4CS1   1
+#define T4PS0   2
+#define T4PS1   3
+#define T4PS2   4
+
+#define T4MRB   _SFR_MEM8(0x87)
+#define T4SCE   1
+#define T4CNC   2
+#define T4CE0   3
+#define T4CE1   4
+#define T4ICS0  5
+#define T4ICS1  6
+#define T4ICS2  7
+
+#define T4IMR   _SFR_MEM8(0x88)
+#define T4OIM   0
+#define T4CIM   1
+#define T4CPIM  2
+
+#define T5TEMP  _SFR_MEM8(0x89)
+
+/* Combine T5OCRL and T5OCRH */
+#define T5OCR   _SFR_MEM16(0x8A)
+
+#define T5OCRL  _SFR_MEM8(0x8A)
+#define T5OCRH  _SFR_MEM8(0x8B)
+
+#define T5CCR   _SFR_MEM8(0x8C)
+#define T5CS0   0
+#define T5CS1   1
+#define T5CS2   2
+#define T5CTC   3
+
+/* Combine T5CNTL and T5CNTH */
+#define T5CNT   _SFR_MEM16(0x8D)
+
+#define T5CNTL  _SFR_MEM8(0x8D)
+#define T5CNTH  _SFR_MEM8(0x8E)
+
+#define T5IMR   _SFR_MEM8(0x8F)
+#define T5OIM   0
+#define T5CIM   1
+
+#define LFCALR1 _SFR_MEM8(0x90)
+#define LFSTC0  0
+#define LFSTC1  1
+#define LFSTC2  2
+#define ICOMPRT0 3
+#define ICOMPRT1 4
+#define SEL150M0 5
+#define SEL150M1 6
+#define SEL150M2 7
+
+#define LFCALR2 _SFR_MEM8(0x91)
+#define LFSTRES0 0
+#define LFSTRES1 1
+#define LFSTRES2 2
+#define LFSTRES3 3
+#define LFSTRES4 4
+#define LFSTRES5 5
+#define LFSRM   6
+#define TIKOMPD 7
+
+#define LFCALR3 _SFR_MEM8(0x92)
+#define TCGAIN10 0
+#define TCGAIN11 1
+#define TCGAIN12 2
+#define TCGAIN13 3
+#define TCGAIN14 4
+#define TCGAIN15 5
+#define TCGAIN16 6
+#define TCGAIN17 7
+
+#define LFCALR4 _SFR_MEM8(0x93)
+#define TCGAIN20 0
+#define TCGAIN21 1
+#define TCGAIN22 2
+#define TCGAIN23 3
+#define TCGAIN24 4
+#define TCGAIN25 5
+#define TCGAIN26 6
+#define TCGAIN27 7
+
+#define LFCALR5 _SFR_MEM8(0x94)
+#define TCGAIN30 0
+#define TCGAIN31 1
+#define TCGAIN32 2
+#define TCGAIN34 4
+#define TCGAIN35 5
+#define TCGAIN36 6
+#define TCGAIN37 7
+
+#define LFCALR6 _SFR_MEM8(0x95)
+#define TCGAIN40 0
+#define TCGAIN41 1
+#define TCGAIN42 2
+#define TCGAIN43 3
+#define TCGAIN44 4
+
+#define LFCALR7 _SFR_MEM8(0x96)
+
+#define LFCALR8 _SFR_MEM8(0x97)
+
+#define LFCALR9 _SFR_MEM8(0x98)
+
+#define LFCALR10 _SFR_MEM8(0x99)
+
+#define LFCALR11 _SFR_MEM8(0x9A)
+
+#define LFCALR12 _SFR_MEM8(0x9B)
+
+#define LFCALR13 _SFR_MEM8(0x9C)
+
+#define LFCALR14 _SFR_MEM8(0x9D)
+
+#define LFCALR15 _SFR_MEM8(0x9E)
+
+#define LFCALR16 _SFR_MEM8(0x9F)
+
+#define LFCALR17 _SFR_MEM8(0xA0)
+
+#define LFCALR18 _SFR_MEM8(0xA1)
+
+#define LFCALR19 _SFR_MEM8(0xA2)
+
+#define LFCALR20 _SFR_MEM8(0xA3)
+
+#define LFCALR21 _SFR_MEM8(0xA4)
+
+#define LFCALR22 _SFR_MEM8(0xA5)
+
+#define LFCALR23 _SFR_MEM8(0xA6)
+
+#define LFCALR24 _SFR_MEM8(0xA7)
+
+#define LFCALR25 _SFR_MEM8(0xA8)
+
+#define LFCALR26 _SFR_MEM8(0xA9)
+
+#define LFCALR27 _SFR_MEM8(0xAA)
+
+#define LFCALR28 _SFR_MEM8(0xAB)
+
+#define LFCALR29 _SFR_MEM8(0xAC)
+
+#define LFCALR30 _SFR_MEM8(0xAD)
+
+#define LFCALR31 _SFR_MEM8(0xAE)
+
+#define LFCALR32 _SFR_MEM8(0xAF)
+
+#define LFCALR33 _SFR_MEM8(0xB0)
+
+#define LFCALR34 _SFR_MEM8(0xB1)
+
+#define LFCALR35 _SFR_MEM8(0xB2)
+
+#define LFCALR36 _SFR_MEM8(0xB3)
+
+#define LFCALR37 _SFR_MEM8(0xB4)
+
+#define LFCALR38 _SFR_MEM8(0xB5)
+
+#define LFCALR39 _SFR_MEM8(0xB6)
+
+#define LFCALR40 _SFR_MEM8(0xB7)
+
+#define LFCALR41 _SFR_MEM8(0xB8)
+
+#define LFCALR42 _SFR_MEM8(0xB9)
+
+#define LFCALR43 _SFR_MEM8(0xBA)
+
+#define LFCALR44 _SFR_MEM8(0xBB)
+
+#define LFCALR45 _SFR_MEM8(0xBC)
+
+#define LFCALR46 _SFR_MEM8(0xBD)
+
+#define LFCALR47 _SFR_MEM8(0xBE)
+
+#define LFCALR48 _SFR_MEM8(0xBF)
+
+#define LFCALR49 _SFR_MEM8(0xC0)
+
+#define LFCALR50 _SFR_MEM8(0xC1)
+
+#define LFCALR51 _SFR_MEM8(0xC2)
+
+#define LFCALR52 _SFR_MEM8(0xC3)
+
+#define LFCALR53 _SFR_MEM8(0xC4)
+
+#define XFUSE   _SFR_MEM8(0xC5)
+
+#define MRCCAL  _SFR_MEM8(0xC6)
+
+#define FRCCAL  _SFR_MEM8(0xC7)
+
+#define RCTCAL  _SFR_MEM8(0xC8)
+#define FRCTC   0
+#define MRCTC0  1
+#define MRCTC1  2
+#define MRCTC2  3
+#define DI_MRCBG 4
+
+#define CMSR    _SFR_MEM8(0xC9)
+#define ECF     0
+
+#define CMOCR   _SFR_MEM8(0xCA)
+#define FRCAO   0
+#define MRCAO   1
+#define FRCACT  2
+
+#define SUPFR   _SFR_MEM8(0xCB)
+#define AVCCRF  0
+#define AVCCLF  1
+
+#define SUPCR   _SFR_MEM8(0xCC)
+#define AVCCRM  0
+#define AVCCLM  1
+#define PVEN    2
+#define AVDIC   3
+#define AVEN    4
+#define DVHEN   5
+#define VMRESM  6
+#define VMEMEN  7
+
+#define SUPCA1  _SFR_MEM8(0xCD)
+#define PV22    2
+#define PVDIC   3
+#define PVCAL0  4
+#define PVCAL1  5
+#define PVCAL2  6
+#define PVCAL3  7
+
+#define SUPCA2  _SFR_MEM8(0xCE)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL3  3
+
+#define SUPCA3  _SFR_MEM8(0xCF)
+#define ACAL0   0
+#define ACAL1   1
+#define ACAL2   2
+#define ACAL3   3
+#define ACAL4   4
+#define ACAL5   5
+#define ACAL6   6
+#define ACAL7   7
+
+#define SUPCA4  _SFR_MEM8(0xD0)
+#define ICONST0 0
+#define ICONST1 1
+#define ICONST2 2
+#define ICONST3 3
+#define ICONST4 4
+#define ICONST5 5
+
+#define CALRDY  _SFR_MEM8(0xD1)
+
+#define DFS     _SFR_MEM8(0xD2)
+#define DFFLRF  0
+#define DFUFL   1
+#define DFOFL   2
+
+/* Reserved [0xD3..0xD4] */
+
+#define DFL     _SFR_MEM8(0xD5)
+#define DFFLS0  0
+#define DFFLS1  1
+#define DFFLS2  2
+#define DFFLS3  3
+#define DFFLS4  4
+#define DFFLS5  5
+#define DFCLR   7
+
+#define DFWP    _SFR_MEM8(0xD6)
+
+#define DFRP    _SFR_MEM8(0xD7)
+
+#define DFD     _SFR_MEM8(0xD8)
+
+#define DFI     _SFR_MEM8(0xD9)
+#define DFFLIM  0
+#define DFERIM  1
+
+#define DFC     _SFR_MEM8(0xDA)
+#define DFFLC0  0
+#define DFFLC1  1
+#define DFFLC2  2
+#define DFFLC3  3
+#define DFFLC4  4
+#define DFFLC5  5
+#define DFDRA   7
+
+#define SFS     _SFR_MEM8(0xDB)
+#define SFFLRF  0
+#define SFUFL   1
+#define SFOFL   2
+
+#define SFL     _SFR_MEM8(0xDC)
+#define SFFLS0  0
+#define SFFLS1  1
+#define SFFLS2  2
+#define SFFLS3  3
+#define SFFLS4  4
+#define SFCLR   7
+
+#define SFWP    _SFR_MEM8(0xDD)
+
+#define SFRP    _SFR_MEM8(0xDE)
+
+#define SFD     _SFR_MEM8(0xDF)
+
+#define SFI     _SFR_MEM8(0xE0)
+#define SFFLIM  0
+#define SFERIM  1
+
+#define SFC     _SFR_MEM8(0xE1)
+#define SFFLC0  0
+#define SFFLC1  1
+#define SFFLC2  2
+#define SFFLC3  3
+#define SFFLC4  4
+#define SFDRA   7
+
+#define SSMCR   _SFR_MEM8(0xE2)
+#define SSMTGE  2
+#define SSMTPE  3
+#define SSMPVE  4
+#define SSMTAE  5
+
+#define GTCCR   _SFR_MEM8(0xE3)
+#define PSR10   0
+#define TSM     7
+
+#define SSMFBR  _SFR_MEM8(0xE4)
+#define SSMPLDT 5
+
+#define SSMRR   _SFR_MEM8(0xE5)
+#define SSMR    0
+#define SSMST   1
+
+#define SSMSR   _SFR_MEM8(0xE6)
+#define SSMESM0 0
+#define SSMESM1 1
+#define SSMESM2 2
+#define SSMESM3 3
+#define SSMERR  7
+
+#define SSMIFR  _SFR_MEM8(0xE7)
+#define SSMIF   0
+
+#define SSMIMR  _SFR_MEM8(0xE8)
+#define SSMIM   0
+
+#define MSMSTR  _SFR_MEM8(0xE9)
+#define SSMMST0 0
+#define SSMMST1 1
+#define SSMMST2 2
+#define SSMMST3 3
+#define SSMMST4 4
+
+#define SSMSTR  _SFR_MEM8(0xEA)
+#define SSMSTA0 0
+#define SSMSTA1 1
+#define SSMSTA2 2
+#define SSMSTA3 3
+#define SSMSTA4 4
+#define SSMSTA5 5
+
+#define VXMCTRL _SFR_MEM8(0xEB)
+#define VX_SEL0 0
+#define VX_SEL1 1
+#define EN_VX   2
+#define EN_VX_OUT 3
+#define EN_VX_IN 4
+
+#define MSMCR1  _SFR_MEM8(0xEC)
+#define MSMSM00 0
+#define MSMSM01 1
+#define MSMSM02 2
+#define MSMSM03 3
+#define MSMSM10 4
+#define MSMSM11 5
+#define MSMSM12 6
+#define MSMSM13 7
+
+#define MSMCR2  _SFR_MEM8(0xED)
+#define MSMSM20 0
+#define MSMSM21 1
+#define MSMSM22 2
+#define MSMSM23 3
+#define MSMSM30 4
+#define MSMSM31 5
+#define MSMSM32 6
+#define MSMSM33 7
+
+#define MSMCR3  _SFR_MEM8(0xEE)
+#define MSMSM40 0
+#define MSMSM41 1
+#define MSMSM42 2
+#define MSMSM43 3
+#define MSMSM50 4
+#define MSMSM51 5
+#define MSMSM52 6
+#define MSMSM53 7
+
+#define MSMCR4  _SFR_MEM8(0xEF)
+#define MSMSM60 0
+#define MSMSM61 1
+#define MSMSM62 2
+#define MSMSM63 3
+#define MSMSM70 4
+#define MSMSM71 5
+#define MSMSM72 6
+#define MSMSM73 7
+
+/* Reserved [0xF0..0xF6] */
+
+#define SP2CR   _SFR_MEM8(0xF7)
+#define SP2R0   0
+#define SP2R1   1
+#define CPHA2   2
+#define CPOL2   3
+#define MSTR2   4
+#define DORD2   5
+#define SP2E    6
+#define SP2IE   7
+
+#define SP2DR   _SFR_MEM8(0xF8)
+
+#define SP2SR   _SFR_MEM8(0xF9)
+#define SPI22X  0
+#define WCOL2   6
+#define SP2IF   7
+
+/* Reserved [0xFA..0xFB] */
+
+/* Combine TRCIDL and TRCIDH */
+#define TRCID   _SFR_MEM16(0xFC)
+
+#define TRCIDL  _SFR_MEM8(0xFC)
+#define TRCIDH  _SFR_MEM8(0xFD)
+
+/* Reserved [0xFE] */
+
+#define TRCDR   _SFR_MEM8(0xFF)
+
+#define FESR    _SFR_MEM8(0x100)
+#define XRDY    2
+#define PLCK    3
+#define ANTS    4
+
+#define FEEN1   _SFR_MEM8(0x101)
+#define PLEN    0
+#define PLCAL   1
+#define XTOEN   2
+#define PLSP1   6
+#define ATEN    7
+
+#define FEEN2   _SFR_MEM8(0x102)
+#define PAEN    2
+#define PLPEN   4
+#define CPBIA   6
+
+#define FELNA   _SFR_MEM8(0x103)
+
+#define FEAT    _SFR_MEM8(0x104)
+#define ANTN0   0
+#define ANTN1   1
+#define ANTN2   2
+#define ANTN3   3
+
+#define FEPAC   _SFR_MEM8(0x105)
+#define PACR0   0
+#define PACR1   1
+#define PACR2   2
+#define PACR3   3
+#define PACR4   4
+#define PACR5   5
+#define PACR6   6
+#define PACR7   7
+
+#define FEVCT   _SFR_MEM8(0x106)
+
+#define FEBT    _SFR_MEM8(0x107)
+#define CTN20   0
+#define CTN21   1
+#define RTN20   2
+#define RTN21   3
+
+#define FEMS    _SFR_MEM8(0x108)
+#define PLLS0   0
+#define PLLS1   1
+#define PLLS2   2
+#define PLLS3   3
+#define PLLM0   4
+#define PLLM1   5
+#define PLLM2   6
+#define PLLM3   7
+
+#define FETN4   _SFR_MEM8(0x109)
+#define CTN40   0
+#define CTN41   1
+#define CTN42   2
+#define CTN43   3
+#define RTN40   4
+#define RTN41   5
+#define RTN42   6
+#define RTN43   7
+
+#define FECR    _SFR_MEM8(0x10A)
+#define LBNHB   0
+#define S4N3    1
+#define PLCKG   4
+#define ANPS    5
+
+#define FEVCO   _SFR_MEM8(0x10B)
+#define CPCC0   0
+#define CPCC1   1
+#define CPCC2   2
+#define CPCC3   3
+#define VCOB0   4
+#define VCOB1   5
+#define VCOB2   6
+#define VCOB3   7
+
+#define FEALR   _SFR_MEM8(0x10C)
+#define RNGE0   0
+#define RNGE1   1
+
+#define FEANT   _SFR_MEM8(0x10D)
+#define LVLC0   0
+#define LVLC1   1
+#define LVLC2   2
+#define LVLC3   3
+
+#define FEBIA   _SFR_MEM8(0x10E)
+
+/* Reserved [0x10F..0x114] */
+
+#define CLKOD   _SFR_MEM8(0x115)
+
+#define CLKOCR  _SFR_MEM8(0x116)
+#define CLKOS0  0
+#define CLKOS1  1
+#define CLKOEN  2
+
+/* Reserved [0x117..0x11B] */
+
+#define FETE1   _SFR_MEM8(0x11C)
+#define ADCT    0
+#define XTOT    1
+#define LNLT    2
+#define LNHT    3
+#define PATE    4
+#define AMPT    5
+#define VCOT    6
+#define ANTN    7
+
+#define FETE2   _SFR_MEM8(0x11D)
+#define RCCT    0
+#define PPFT    1
+#define LFT     2
+#define CPT     3
+#define PFDT    4
+#define DADCT   5
+#define PRET    6
+#define SWALT   7
+
+#define FETE3   _SFR_MEM8(0x11E)
+#define BIOUT   0
+#define RMPTST  1
+
+#define FETD    _SFR_MEM8(0x11F)
+
+#define TMFSM   _SFR_MEM8(0x120)
+#define TMSSM0  0
+#define TMSSM1  1
+#define TMSSM2  2
+#define TMSSM3  3
+#define TMMSM0  4
+#define TMMSM1  5
+#define TMMSM2  6
+
+/* Combine TMCRCL and TMCRCH */
+#define TMCRC   _SFR_MEM16(0x121)
+
+#define TMCRCL  _SFR_MEM8(0x121)
+#define TMCRCH  _SFR_MEM8(0x122)
+
+#define TMCSB   _SFR_MEM8(0x123)
+
+/* Combine TMCIL and TMCIH */
+#define TMCI    _SFR_MEM16(0x124)
+
+#define TMCIL   _SFR_MEM8(0x124)
+#define TMCIH   _SFR_MEM8(0x125)
+
+/* Combine TMCPL and TMCPH */
+#define TMCP    _SFR_MEM16(0x126)
+
+#define TMCPL   _SFR_MEM8(0x126)
+#define TMCPH   _SFR_MEM8(0x127)
+
+#define TMSHR   _SFR_MEM8(0x128)
+
+/* Combine TMTLLL and TMTLLH */
+#define TMTLL   _SFR_MEM16(0x129)
+
+#define TMTLLL  _SFR_MEM8(0x129)
+#define TMTLLH  _SFR_MEM8(0x12A)
+
+#define TMSSC   _SFR_MEM8(0x12B)
+#define TMSSP0  0
+#define TMSSP1  1
+#define TMSSP2  2
+#define TMSSP3  3
+#define TMSSL0  4
+#define TMSSL1  5
+#define TMSSL2  6
+#define TMSSH   7
+
+#define TMSR    _SFR_MEM8(0x12C)
+#define TMTCF   0
+
+#define TMCR2   _SFR_MEM8(0x12D)
+#define TMCRCE  0
+#define TMCRCSE0 1
+#define TMCRCSE1 2
+#define TMNRZE  3
+#define TMPOL   4
+#define TMSSE   5
+#define TMLSB   6
+
+#define TMCR1   _SFR_MEM8(0x12E)
+#define TMPIS0  0
+#define TMPIS1  1
+#define TMPIS2  2
+#define TMSCS   3
+#define TMCIM   4
+
+/* Reserved [0x12F] */
+
+#define LFDSR1  _SFR_MEM8(0x130)
+#define LOTHA0  0
+#define LOTHA1  1
+#define HITHA0  2
+#define HITHA1  3
+#define CTTHA0  4
+#define CTTHA1  5
+
+#define LFDSR2  _SFR_MEM8(0x131)
+#define LOTHB0  0
+#define LOTHB1  1
+#define HITHB0  2
+#define HITHB1  3
+#define CTTHB0  4
+#define CTTHB1  5
+
+#define LFDSR3  _SFR_MEM8(0x132)
+#define PBDTH0  0
+#define PBDTH1  1
+#define QCTH0   3
+#define QCTH1   4
+#define QCTH2   5
+
+#define LFDSR4  _SFR_MEM8(0x133)
+#define SDTHA0  0
+#define SDTHA1  1
+#define SDTHA2  2
+#define SCTHA0  3
+#define SCTHA1  4
+#define SCTHA2  5
+#define SRSTC0  6
+#define SRSTC1  7
+
+#define LFDSR5  _SFR_MEM8(0x134)
+#define SDTHB0  0
+#define SDTHB1  1
+#define SDTHB2  2
+#define SCTHB0  3
+#define SCTHB1  4
+#define SCTHB2  5
+#define SSUTA   6
+#define SSUTB   7
+
+#define LFDSR6  _SFR_MEM8(0x135)
+#define TODU0   0
+#define TODU1   1
+#define TODU2   2
+#define TODS0   3
+#define TODS1   4
+#define TODS2   5
+
+#define LFDSR7  _SFR_MEM8(0x136)
+#define PBSP0   0
+#define PBSP1   1
+#define PBG0    2
+#define PBG1    3
+#define MDSP0   4
+#define MDSP1   5
+#define MDG0    6
+#define MDG1    7
+
+#define LFDSR8  _SFR_MEM8(0x137)
+#define CLD0    0
+#define CLD1    1
+#define CLD2    2
+#define LGFE    3
+#define ASWTH0  4
+#define ASWTH1  5
+#define ASWTH2  6
+
+#define LFDSR9  _SFR_MEM8(0x138)
+#define STW0    0
+#define STW1    1
+#define STW2    2
+#define STW3    3
+#define STW4    4
+
+#define LFDSR10 _SFR_MEM8(0x139)
+#define FCL0    0
+#define FCL1    1
+#define FCL2    2
+#define FCL3    3
+#define FCL4    4
+#define FCL5    5
+#define STBTH0  6
+#define STBTH1  7
+
+#define LFDSR11 _SFR_MEM8(0x13A)
+#define TINITA0 0
+#define TINITA1 1
+#define TINITA2 2
+#define TINITA3 3
+#define TINITB0 4
+#define TINITB1 5
+#define TINITB2 6
+#define TINITB3 7
+
+#define EEPR1   _SFR_MEM8(0x13B)
+#define EEPS4WD 0
+#define EEPS4RD 1
+#define EEPS5WD 2
+#define EEPS5RD 3
+#define EEPS6WD 4
+#define EEPS6RD 5
+#define EEPS7WD 6
+#define EEPS7RD 7
+
+#define EEPR2   _SFR_MEM8(0x13C)
+#define EEPS8WD 0
+#define EEPS8RD 1
+#define EEPS9WD 2
+#define EEPS9RD 3
+#define EEPS10WD 4
+#define EEPS10RD 5
+#define EEPS11WD 6
+#define EEPS11RD 7
+
+#define EEPR3   _SFR_MEM8(0x13D)
+#define EEPS12WD 0
+#define EEPS12RD 1
+
+/* Reserved [0x13E..0x144] */
+
+#define CRCCR   _SFR_MEM8(0x145)
+#define CRCRS   0
+#define REFLI   1
+#define REFLO   2
+
+#define CRCDOR  _SFR_MEM8(0x146)
+
+/* Reserved [0x147..0x150] */
+
+#define LFSRCTM _SFR_MEM8(0x151)
+#define LFSRCT1 0
+#define LFSRCT2 1
+#define LFSRCT3 2
+#define LFSRCT4 3
+#define LFSRCT5 4
+#define LFSRCT6 5
+#define LFSRCT7 6
+#define LFSRCT8 7
+
+#define DBCR    _SFR_MEM8(0x152)
+#define DBMD    0
+#define DBCS    1
+#define DBTMS   2
+#define DBHA    3
+
+#define DBTC    _SFR_MEM8(0x153)
+
+#define DBENB   _SFR_MEM8(0x154)
+
+#define DBENC   _SFR_MEM8(0x155)
+
+#define DBGSW   _SFR_MEM8(0x156)
+#define DBGGS0  0
+#define DBGGS1  1
+#define DBGGS2  2
+#define DBGGS3  3
+#define CPBFOS0 4
+#define CPBFOS1 5
+#define CPBF    6
+#define ATEST   7
+
+#define SFFR    _SFR_MEM8(0x157)
+#define RFL0    0
+#define RFL1    1
+#define RFL2    2
+#define RFC     3
+#define TFL0    4
+#define TFL1    5
+#define TFL2    6
+#define TFC     7
+
+#define SFIR    _SFR_MEM8(0x158)
+#define RIL0    0
+#define RIL1    1
+#define RIL2    2
+#define SRIE    3
+#define TIL0    4
+#define TIL1    5
+#define TIL2    6
+#define STIE    7
+
+#define T2IFR   _SFR_MEM8(0x159)
+#define T2OFF   0
+#define T2COF   1
+
+#define PGMST   _SFR_MEM8(0x15A)
+#define PGMSYN0 0
+#define PGMSYN1 1
+#define PGMSYN2 2
+#define PGMSYN3 3
+#define PGMSYN4 4
+
+#define EEST    _SFR_MEM8(0x15B)
+#define EESYN0  0
+#define EESYN1  1
+#define EESYN2  2
+#define EESYN3  3
+
+#define LFSRCTL _SFR_MEM8(0x15C)
+#define LFSRCT0 0
+
+/* Reserved [0x15D..0x160] */
+
+#define PCIFR   _SFR_MEM8(0x161)
+#define PCIF0   0
+#define PCIF1   1
+
+#define T0CR    _SFR_MEM8(0x162)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+/* Reserved [0x163] */
+
+#define DBEND   _SFR_MEM8(0x164)
+
+#define TPCR1   _SFR_MEM8(0x165)
+#define TPQPLM  2
+#define TPBR    4
+#define TPDFCP0 5
+#define TPDFCP1 6
+#define TPMODE  7
+
+#define TPIMR   _SFR_MEM8(0x166)
+#define TPIM    0
+#define TPFTIM  1
+#define TPNFTIM 2
+#define TPBERIM 3
+
+#define TPDCR1  _SFR_MEM8(0x167)
+#define TPDCL10 0
+#define TPDCL11 1
+#define TPDCL12 2
+#define TPDCL13 3
+#define TPDCL14 4
+#define TPDCL15 5
+
+#define TPDCR2  _SFR_MEM8(0x168)
+#define TPDCL20 0
+#define TPDCL21 1
+#define TPDCL22 2
+#define TPDCL23 3
+#define TPDCL24 4
+#define TPDCL25 5
+
+#define TPDCR3  _SFR_MEM8(0x169)
+#define TPDCL30 0
+#define TPDCL31 1
+#define TPDCL32 2
+#define TPDCL33 3
+#define TPDCL34 4
+#define TPDCL35 5
+
+#define TPDCR4  _SFR_MEM8(0x16A)
+#define TPDCL40 0
+#define TPDCL41 1
+#define TPDCL42 2
+#define TPDCL43 3
+#define TPDCL44 4
+#define TPDCL45 5
+
+#define TPDCR5  _SFR_MEM8(0x16B)
+#define TPDCL50 0
+#define TPDCL51 1
+#define TPDCL52 2
+#define TPDCL53 3
+#define TPDCL54 4
+#define TPDCL55 5
+
+#define TPECR1  _SFR_MEM8(0x16C)
+#define TPECL10 0
+#define TPECL11 1
+#define TPECL12 2
+#define TPECL13 3
+#define TPECL14 4
+#define TPECL15 5
+#define TPECL16 6
+#define TPECL17 7
+
+#define TPECR2  _SFR_MEM8(0x16D)
+#define TPECL20 0
+#define TPECL21 1
+#define TPECL22 2
+#define TPECL23 3
+#define TPECL24 4
+#define TPECL25 5
+#define TPECL26 6
+#define TPECL27 7
+
+#define TPECR3  _SFR_MEM8(0x16E)
+#define TPECL30 0
+#define TPECL31 1
+#define TPECL32 2
+#define TPECL33 3
+#define TPECL34 4
+#define TPECL35 5
+#define TPECL36 6
+#define TPECL37 7
+
+#define TPECR4  _SFR_MEM8(0x16F)
+#define TPECL40 0
+#define TPECL41 1
+#define TPECL42 2
+#define TPECL43 3
+#define TPECL44 4
+#define TPECL45 5
+#define TPECL46 6
+#define TPECL47 7
+
+#define TPECMR  _SFR_MEM8(0x170)
+#define TPECM10 0
+#define TPECM11 1
+#define TPECM20 2
+#define TPECM21 3
+#define TPECM30 4
+#define TPECM31 5
+#define TPECM40 6
+#define TPECM41 7
+
+#define TPCR3   _SFR_MEM8(0x171)
+#define TPTD    0
+#define TPRD    1
+#define TPTLIW  2
+#define TPRCD   5
+
+#define TPCR4   _SFR_MEM8(0x172)
+#define TPBCCS0 0
+#define TPBCCS1 1
+#define TPBCCS2 2
+#define TPBCCS3 3
+#define TPBCM   4
+
+#define TPCR5   _SFR_MEM8(0x173)
+#define TPMUD0  0
+#define TPMUD1  1
+#define TPMUD2  2
+#define TPMD0   4
+#define TPMD1   5
+#define TPMD2   6
+
+/* Reserved [0x174] */
+
+#define TPCALR1 _SFR_MEM8(0x175)
+#define TPBG_IREF0 0
+#define TPBG_IREF1 1
+#define TPBG_IREF2 2
+#define TPBG_IREF3 3
+#define TPBG_IREF4 4
+#define TPBG_IREF5 5
+
+#define TPCALR2 _SFR_MEM8(0x176)
+#define TPBG_UREF0 0
+#define TPBG_UREF1 1
+#define TPBG_UREF2 2
+#define TPBG_UREF3 3
+#define TPBG_UREF4 4
+#define TPBG_UREF5 5
+#define TPBG_UREF6 6
+
+#define TPCALR3 _SFR_MEM8(0x177)
+#define LFVCC_TPCAL0 0
+#define LFVCC_TPCAL1 1
+#define LFVCC_TPCAL2 2
+#define TPORTH0 3
+#define TPORTH1 4
+
+#define TPCALR4 _SFR_MEM8(0x178)
+#define TPINIT_CAL0 0
+#define TPINIT_CAL1 1
+#define TPINIT_CAL2 2
+#define COMPVC_CAL0 3
+#define COMPVC_CAL1 4
+
+#define TPCALR5 _SFR_MEM8(0x179)
+
+#define TPCALR6 _SFR_MEM8(0x17A)
+
+#define TPCALR7 _SFR_MEM8(0x17B)
+
+#define TPCALR8 _SFR_MEM8(0x17C)
+
+#define TPCALR9 _SFR_MEM8(0x17D)
+
+#define TPCALR10 _SFR_MEM8(0x17E)
+
+#define AESDPR  _SFR_MEM8(0x17F)
+
+#define AESKR   _SFR_MEM8(0x180)
+
+#define AESDR   _SFR_MEM8(0x181)
+
+#define GPIOR3  _SFR_MEM8(0x182)
+
+#define GPIOR4  _SFR_MEM8(0x183)
+
+#define GPIOR5  _SFR_MEM8(0x184)
+
+#define GPIOR6  _SFR_MEM8(0x185)
+
+#define GPIOR7  _SFR_MEM8(0x186)
+
+#define GPIOR8  _SFR_MEM8(0x187)
+
+#define PHBCRR  _SFR_MEM8(0x188)
+
+/* Reserved [0x189..0x18D] */
+
+#define LFCPR   _SFR_MEM8(0x18E)
+#define LFCALP  0
+#define LFCALRY 1
+#define TPCD    6
+#define LFCPCE  7
+
+#define LFIMR   _SFR_MEM8(0x18F)
+#define LFSYDIM 0
+#define LFDEIM  1
+#define LFEOIM  2
+
+#define PHID0   _SFR_MEM16(0x190)
+
+#define PHID0L  _SFR_MEM8(0x194)
+
+#define PHID1   _SFR_MEM16(0x195)
+
+#define PHID1L  _SFR_MEM8(0x199)
+
+#define PHIDFR  _SFR_MEM8(0x19A)
+
+#define LFSYSY  _SFR_MEM16(0x19B)
+
+#define LFSYLE  _SFR_MEM8(0x19F)
+#define LFSYLE0 0
+#define LFSYLE1 1
+#define LFSYLE2 2
+#define LFSYLE3 3
+#define LFSYLE4 4
+#define LFSYLE5 5
+
+#define LFSTOP  _SFR_MEM8(0x1A0)
+#define LFSTSY0 0
+#define LFSTSY1 1
+#define LFSTSY2 2
+#define LFSTSY3 3
+#define LFSTL0  4
+#define LFSTL1  5
+#define LFSTL2  6
+
+#define LTCOR   _SFR_MEM8(0x1A1)
+
+#define T1IFR   _SFR_MEM8(0x1A2)
+#define T1OFF   0
+#define T1COF   1
+
+/* Reserved [0x1A3] */
+
+#define PHTBLR  _SFR_MEM8(0x1A4)
+
+#define PHDFR   _SFR_MEM8(0x1A5)
+
+#define LTEMR   _SFR_MEM8(0x1A6)
+#define ID0EM   0
+#define ID1EM   1
+#define IDFEM   2
+#define DFEM    3
+#define TBLEM   4
+#define FLEM    5
+#define EOFEM   6
+#define LTCOF   7
+
+#define LFQC3   _SFR_MEM8(0x1A7)
+#define LFQS30  0
+#define LFQS31  1
+#define LFQS32  2
+#define LFQS33  3
+#define LFCS30  4
+#define LFCS31  5
+#define LFCS32  6
+#define LFCS33  7
+
+#define LFQC2   _SFR_MEM8(0x1A8)
+#define LFQS20  0
+#define LFQS21  1
+#define LFQS22  2
+#define LFQS23  3
+#define LFCS20  4
+#define LFCS21  5
+#define LFCS22  6
+#define LFCS23  7
+
+#define LFQC1   _SFR_MEM8(0x1A9)
+#define LFQS10  0
+#define LFQS11  1
+#define LFQS12  2
+#define LFQS13  3
+#define LFCS10  4
+#define LFCS11  5
+#define LFCS12  6
+#define LFCS13  7
+
+#define TW2BR   _SFR_MEM8(0x1AA)
+
+#define TW2CR   _SFR_MEM8(0x1AB)
+#define TW2IE   0
+#define TW2EN   2
+#define TW2WC   3
+#define TW2STO  4
+#define TW2STA  5
+#define TW2EA   6
+#define TW2INT  7
+
+#define TW2SR   _SFR_MEM8(0x1AC)
+#define TW2PS0  0
+#define TW2PS1  1
+#define TW2S0   3
+#define TW2S1   4
+#define TW2S2   5
+#define TW2S3   6
+#define TW2S4   7
+
+#define TW2DR   _SFR_MEM8(0x1AD)
+
+#define TW2AR   _SFR_MEM8(0x1AE)
+#define TW2GCE  0
+#define TW2A0   1
+#define TW2A1   2
+#define TW2A2   3
+#define TW2A3   4
+#define TW2A4   5
+#define TW2A5   6
+#define TW2A6   7
+
+#define TW2AMR  _SFR_MEM8(0x1AF)
+#define TW2AM0  1
+#define TW2AM1  2
+#define TW2AM2  3
+#define TW2AM3  4
+#define TW2AM4  5
+#define TW2AM5  6
+#define TW2AM6  7
+
+#define RSCR    _SFR_MEM8(0x1B0)
+#define RSSDEN  0
+#define RSOS    1
+#define RSEOR   2
+#define RSOFM   3
+#define RSMODE0 4
+#define RSMODE1 5
+#define RSRES   7
+
+#define RSSR    _SFR_MEM8(0x1B1)
+#define RSRDY   0
+#define RSSVLD  1
+
+#define RSMS1R  _SFR_MEM8(0x1B2)
+#define RSCH1E  0
+#define RSCH2E  1
+#define RSCH3E  2
+#define RSINTM  3
+#define RSSTIM  4
+#define RSCMS   5
+#define RSSSV   6
+#define RSSCAL  7
+
+#define RSMS2R  _SFR_MEM8(0x1B3)
+#define RSSADR0 0
+#define RSSADR1 1
+#define RSSADR2 2
+#define RSSADR3 3
+#define RSAVGS0 4
+#define RSAVGS1 5
+#define RSAVGS2 6
+#define RSAVGS3 7
+
+#define RSFR    _SFR_MEM8(0x1B4)
+#define RSOOR1  0
+#define RSOOR2  1
+#define RSOOR3  2
+#define RSOFF   3
+#define RSAOOR1 5
+#define RSAOOR2 6
+#define RSAOOR3 7
+
+/* Reserved [0x1B5] */
+
+#define RSCALIB _SFR_MEM8(0x1B6)
+#define RSCALIB0 0
+#define RSCALIB1 1
+#define RSCALIB2 2
+#define RSCALIB3 3
+#define RSCALIB4 4
+#define RSCALIB5 5
+#define RSCALIB6 6
+#define RSCALIB7 7
+
+#define RSDLYR  _SFR_MEM8(0x1B7)
+#define RSTRD0  0
+#define RSTRD1  1
+#define RSTRD2  2
+#define RSTRD3  3
+#define RSTRD4  4
+#define RSTRD5  5
+#define RSRD0   6
+#define RSRD1   7
+
+#define RSRES1L _SFR_MEM8(0x1B8)
+#define RSRES1L0 0
+#define RSRES1L1 1
+#define RSRES1L2 2
+#define RSRES1L3 3
+#define RSRES1L4 4
+#define RSRES1L5 5
+#define RSRES1L6 6
+#define RSRES1L7 7
+
+#define RSRES1H _SFR_MEM8(0x1B9)
+#define RSRES1H0 0
+#define RSRES1H1 1
+#define RSRES1H2 2
+#define RSRES1H3 3
+#define RSRES1H4 4
+#define RSRES1H5 5
+#define RSRES1H6 6
+#define RSRES1H7 7
+
+#define RSRES2L _SFR_MEM8(0x1BA)
+#define RSRES2L0 0
+#define RSRES2L1 1
+#define RSRES2L2 2
+#define RSRES2L3 3
+#define RSRES2L4 4
+#define RSRES2L5 5
+#define RSRES2L6 6
+#define RSRES2L7 7
+
+#define RSRES2H _SFR_MEM8(0x1BB)
+#define RSRES2H0 0
+#define RSRES2H1 1
+#define RSRES2H2 2
+#define RSRES2H3 3
+#define RSRES2H4 4
+#define RSRES2H5 5
+#define RSRES2H6 6
+#define RSRES2H7 7
+
+#define RSRES3L _SFR_MEM8(0x1BC)
+#define RSRES3L0 0
+#define RSRES3L1 1
+#define RSRES3L2 2
+#define RSRES3L3 3
+#define RSRES3L4 4
+#define RSRES3L5 5
+#define RSRES3L6 6
+#define RSRES3L7 7
+
+#define RSRES3H _SFR_MEM8(0x1BD)
+#define RSRES3H0 0
+#define RSRES3H1 1
+#define RSRES3H2 2
+#define RSRES3H3 3
+#define RSRES3H4 4
+#define RSRES3H5 5
+#define RSRES3H6 6
+#define RSRES3H7 7
+
+#define RSRES4L _SFR_MEM8(0x1BE)
+#define RSRES4L0 0
+#define RSRES4L1 1
+#define RSRES4L2 2
+#define RSRES4L3 3
+#define RSRES4L4 4
+#define RSRES4L5 5
+#define RSRES4L6 6
+#define RSRES4L7 7
+
+#define RSRES4H _SFR_MEM8(0x1BF)
+#define RSRES4H0 0
+#define RSRES4H1 1
+#define RSRES4H2 2
+#define RSRES4H3 3
+#define RSRES4H4 4
+#define RSRES4H5 5
+#define RSRES4H6 6
+#define RSRES4H7 7
+
+#define RSSRCR  _SFR_MEM8(0x1C0)
+#define SRCMODE0 0
+#define SRCMODE1 1
+#define SRCMIN0 2
+#define SRCMIN1 3
+#define SRCCLR  4
+#define SRCSTEP0 6
+#define SRCSTEP1 7
+
+#define SD12RR  _SFR_MEM8(0x1C1)
+#define SD12RR0 0
+#define SD12RR1 1
+#define SD12RR2 2
+#define SD12RR3 3
+#define SD12RR4 4
+#define SD12RR5 5
+#define SD12RR6 6
+#define SD12RR7 7
+
+#define SD13RR  _SFR_MEM8(0x1C2)
+#define SD13RR0 0
+#define SD13RR1 1
+#define SD13RR2 2
+#define SD13RR3 3
+#define SD13RR4 4
+#define SD13RR5 5
+#define SD13RR6 6
+#define SD13RR7 7
+
+#define SD23RR  _SFR_MEM8(0x1C3)
+#define SD23RR0 0
+#define SD23RR1 1
+#define SD23RR2 2
+#define SD23RR3 3
+#define SD23RR4 4
+#define SD23RR5 5
+#define SD23RR6 6
+#define SD23RR7 7
+
+#define SD360R  _SFR_MEM8(0x1C4)
+#define SD360R0 0
+#define SD360R1 1
+#define SD360R2 2
+#define SD360R3 3
+#define SD360R4 4
+#define SD360R5 5
+#define SD360R6 6
+#define SD360R7 7
+
+#define RSDBGR  _SFR_MEM8(0x1C5)
+#define RSSANA  0
+#define RSINFM  2
+#define RSFPD   3
+#define RSHOME  4
+#define RSDBGS0 5
+#define RSDBGS1 6
+#define RSDBGEN 7
+
+/* Reserved [0x1C6..0x1D0] */
+
+#define LDFS    _SFR_MEM8(0x1D1)
+#define LDFFLR  0
+#define LDFUF   1
+#define LDFOF   2
+
+#define T4IFR   _SFR_MEM8(0x1D2)
+#define T4OFF   0
+#define T4COF   1
+#define T4ICF   2
+
+#define LDFWP   _SFR_MEM8(0x1D3)
+#define LDFWP0  0
+#define LDFWP1  1
+#define LDFWP2  2
+#define LDFWP3  3
+#define LDFWP4  4
+#define LDFWP5  5
+
+#define LDFRP   _SFR_MEM8(0x1D4)
+#define LDFRP0  0
+#define LDFRP1  1
+#define LDFRP2  2
+#define LDFRP3  3
+#define LDFRP4  4
+#define LDFRP5  5
+
+#define T5IFR   _SFR_MEM8(0x1D5)
+#define T5OFF   0
+#define T5COF   1
+
+#define LDFIM   _SFR_MEM8(0x1D6)
+#define LDFFLIM 0
+#define LDFEIM  1
+
+#define LDFC    _SFR_MEM8(0x1D7)
+#define LDFFLC0 0
+#define LDFFLC1 1
+#define LDFFLC2 2
+#define LDFFLC3 3
+#define LDFFLC4 4
+#define LDFFLC5 5
+#define LDFMSB  6
+
+#define PHIMR   _SFR_MEM8(0x1D8)
+#define PHTBLIM 1
+#define PHDFIM  2
+#define PHIDFIM 3
+#define PHID0IM 4
+#define PHID1IM 5
+
+#define PHCRCR  _SFR_MEM8(0x1D9)
+#define CRCFR   2
+#define CRCSE0  4
+#define CRCSE1  5
+#define CRCEN   7
+
+/* Combine PHCSTL and PHCSTH */
+#define PHCST   _SFR_MEM16(0x1DA)
+
+#define PHCSTL  _SFR_MEM8(0x1DA)
+#define PHCSTH  _SFR_MEM8(0x1DB)
+
+/* Combine PHCRPL and PHCRPH */
+#define PHCRP   _SFR_MEM16(0x1DC)
+
+#define PHCRPL  _SFR_MEM8(0x1DC)
+#define PHCRPH  _SFR_MEM8(0x1DD)
+
+/* Combine PHCSRL and PHCSRH */
+#define PHCSR   _SFR_MEM16(0x1DE)
+
+#define PHCSRL  _SFR_MEM8(0x1DE)
+#define PHCSRH  _SFR_MEM8(0x1DF)
+
+#define CRCDIR  _SFR_MEM8(0x1E0)
+
+#define T3IFR   _SFR_MEM8(0x1E1)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+
+/* Reserved [0x1E2] */
+
+#define CMCR    _SFR_MEM8(0x1E3)
+#define CMM0    0
+#define CMM1    1
+#define CMM2    2
+#define CCS     3
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMIMR   _SFR_MEM8(0x1E4)
+#define ECIE    0
+
+#define CLPR    _SFR_MEM8(0x1E5)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLPCE   7
+
+#define VMCR    _SFR_MEM8(0x1E6)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMPS0   5
+#define VMPS1   6
+#define VMRS    7
+
+#define DBONDR  _SFR_MEM8(0x1E7)
+#define BBESD   0
+#define AGND_BB 1
+#define ISO_GND 2
+#define AGND_LF 3
+#define BTEST4  4
+#define BTEST5  5
+#define BTEST6  6
+
+#define CALRDYLF _SFR_MEM8(0x1E8)
+
+#define TW1BR   _SFR_MEM8(0x1E9)
+
+#define TW1CR   _SFR_MEM8(0x1EA)
+#define TW1IE   0
+#define TW1EN   2
+#define TW1WC   3
+#define TW1STO  4
+#define TW1STA  5
+#define TW1EA   6
+#define TW1INT  7
+
+#define TW1SR   _SFR_MEM8(0x1EB)
+#define TW1PS0  0
+#define TW1PS1  1
+#define TW1S0   3
+#define TW1S1   4
+#define TW1S2   5
+#define TW1S3   6
+#define TW1S4   7
+
+#define TW1DR   _SFR_MEM8(0x1EC)
+
+#define TW1AR   _SFR_MEM8(0x1ED)
+#define TW1GCE  0
+#define TW1A0   1
+#define TW1A1   2
+#define TW1A2   3
+#define TW1A3   4
+#define TW1A4   5
+#define TW1A5   6
+#define TW1A6   7
+
+#define TW1AMR  _SFR_MEM8(0x1EE)
+#define TW1AM0  1
+#define TW1AM1  2
+#define TW1AM2  3
+#define TW1AM3  4
+#define TW1AM4  5
+#define TW1AM5  6
+#define TW1AM6  7
+
+#define PDSCR   _SFR_MEM8(0x1EF)
+#define PDSC0   0
+#define PDSC1   1
+#define PDSC2   2
+#define PDSC3   3
+#define PDSC4   4
+#define STBTEST 5
+#define RSSISEL 6
+#define ATBSEL  7
+
+#define TMOCR   _SFR_MEM8(0x1F0)
+#define TO1PIS0 0
+#define TO1PIS1 1
+#define TO2PIS0 2
+#define TO2PIS1 3
+#define TO3PIS0 4
+#define TO3PIS1 5
+#define TO4PIS0 6
+#define TO4PIS1 7
+
+#define SRCCAL  _SFR_MEM8(0x1F1)
+#define SRCCAL1 0
+#define SRCCAL2 1
+#define SRCCAL3 2
+#define SRCCAL4 3
+#define SRCCAL5 4
+#define SRCCAL6 5
+#define SRCCAL7 6
+#define SRCCAL8 7
+
+#define SRCTCAL _SFR_MEM8(0x1F2)
+#define SRCTC0  0
+#define SRCTC1  1
+#define SRCTC2  2
+#define SRCS0   3
+#define SRCS1   4
+#define DIS_SRC 6
+#define HOLD_SRC 7
+
+#define SUPCA5  _SFR_MEM8(0x1F3)
+#define IPTAT0  0
+#define IPTAT1  1
+#define IPTAT2  2
+#define IPTAT3  3
+#define IPTAT4  4
+#define IPTAT5  5
+
+#define SUPCA6  _SFR_MEM8(0x1F4)
+#define VBGTR0  0
+#define VBGTR1  1
+#define VBGTR2  2
+#define VBGTR3  3
+#define VBGTR4  4
+#define VBGTR5  5
+#define VBGTR6  6
+#define VBGTR7  7
+
+#define SUPCA7  _SFR_MEM8(0x1F5)
+#define VCCCAL0 0
+#define VCCCAL1 1
+#define VCCCAL2 2
+#define LFVCCBD0 3
+#define LFVCCBD1 4
+#define LFVCCBD2 5
+
+#define SUPCA8  _SFR_MEM8(0x1F6)
+#define VSWBD0  0
+#define VSWBD1  1
+#define VSWBD2  2
+#define DVCCBD0 3
+#define DVCCBD1 4
+#define DVCCBD2 5
+
+#define SUPCA9  _SFR_MEM8(0x1F7)
+#define VMEM0   0
+#define VMEM1   1
+#define VMEM2   2
+#define VMEM3   3
+#define VMEM4   4
+#define VMEM5   5
+#define VMEM6   6
+#define VMEM7   7
+
+#define SUPCA10 _SFR_MEM8(0x1F8)
+
+#define TPCALR11 _SFR_MEM8(0x1F9)
+#define MTBTR0  0
+#define MTBTR1  1
+#define ENDVBD  2
+#define ENLFBD  3
+#define ENVSWBD 4
+#define TPCALR115 5
+#define TPCALR116 6
+#define TPCALR117 7
+
+#define TPCALR12 _SFR_MEM8(0x1FA)
+#define TPDMOD  0
+#define TPCALR121 1
+#define TPCALR122 2
+#define TPCALR123 3
+#define TPCALR124 4
+#define TPCALR125 5
+#define TPCALR126 6
+#define TPCALR127 7
+
+#define TPCALR13 _SFR_MEM8(0x1FB)
+
+/* Reserved [0x1FC..0x1FD] */
+
+#define PMTER   _SFR_MEM8(0x1FE)
+
+#define SRCCALL _SFR_MEM8(0x1FF)
+#define SRCCAL0 0
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_PWR_SAVE (0x01<<1)
+#define SLEEP_MODE_EXT_PWR_SAVE (0x02<<1)
+#define SLEEP_MODE_PWR_DOWN (0x03<<1)
+#define SLEEP_MODE_EXT_PWR_DOWN (0x04<<1)
+#define SLEEP_MODE_PWR_OFF (0x05<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCI0_vect            _VECTOR(3)
+#define PCI0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCI1_vect            _VECTOR(4)
+#define PCI1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMON_vect            _VECTOR(5)
+#define VMON_vect_num        5
+
+/* AVCC Reset Interrupt */
+#define AVCCR_vect            _VECTOR(6)
+#define AVCCR_vect_num        6
+
+/* AVCC Low Interrupt */
+#define AVCCL_vect            _VECTOR(7)
+#define AVCCL_vect_num        7
+
+/* Timer0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(8)
+#define T0INT_vect_num        8
+
+/* Timer/Counter1 Compare Match Interrupt */
+#define T1COMP_vect            _VECTOR(9)
+#define T1COMP_vect_num        9
+
+/* Timer/Counter1 Overflow Interrupt */
+#define T1OVF_vect            _VECTOR(10)
+#define T1OVF_vect_num        10
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMP_vect            _VECTOR(11)
+#define T2COMP_vect_num        11
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVF_vect            _VECTOR(12)
+#define T2OVF_vect_num        12
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAP_vect            _VECTOR(13)
+#define T3CAP_vect_num        13
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMP_vect            _VECTOR(14)
+#define T3COMP_vect_num        14
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVF_vect            _VECTOR(15)
+#define T3OVF_vect_num        15
+
+/* Timer/Counter4 Capture Event Interrupt */
+#define T4CAP_vect            _VECTOR(16)
+#define T4CAP_vect_num        16
+
+/* Timer/Counter4 Compare Match Interrupt */
+#define T4COMP_vect            _VECTOR(17)
+#define T4COMP_vect_num        17
+
+/* Timer/Counter4 Overflow Interrupt */
+#define T4OVF_vect            _VECTOR(18)
+#define T4OVF_vect_num        18
+
+/* Timer/Counter5 Compare Match Interrupt */
+#define T5COMP_vect            _VECTOR(19)
+#define T5COMP_vect_num        19
+
+/* Timer/Counter5 Overflow Interrupt */
+#define T5OVF_vect            _VECTOR(20)
+#define T5OVF_vect_num        20
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPI_vect            _VECTOR(21)
+#define SPI_vect_num        21
+
+/* SPI Rx Buffer Interrupt */
+#define SRX_FIFO_vect            _VECTOR(22)
+#define SRX_FIFO_vect_num        22
+
+/* SPI Tx Buffer Interrupt */
+#define STX_FIFO_vect            _VECTOR(23)
+#define STX_FIFO_vect_num        23
+
+/* Sequencer State Machine Interrupt */
+#define SSM_vect            _VECTOR(24)
+#define SSM_vect_num        24
+
+/* Data FIFO fill level reached Interrupt */
+#define DFFLR_vect            _VECTOR(25)
+#define DFFLR_vect_num        25
+
+/* Data FIFO overflow or underflow error Interrupt */
+#define DFOUE_vect            _VECTOR(26)
+#define DFOUE_vect_num        26
+
+/* RSSI/Preamble FIFO fill level reached Interrupt */
+#define SFFLR_vect            _VECTOR(27)
+#define SFFLR_vect_num        27
+
+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
+#define SFOUE_vect            _VECTOR(28)
+#define SFOUE_vect_num        28
+
+/* Tx Modulator Telegram Finish Interrupt */
+#define TMTCF_vect            _VECTOR(29)
+#define TMTCF_vect_num        29
+
+/* AES Krypto Unit Interrupt */
+#define AES_vect            _VECTOR(30)
+#define AES_vect_num        30
+
+/* Transponder Mode Interrupt */
+#define TPINT_vect            _VECTOR(31)
+#define TPINT_vect_num        31
+
+/* Transponder Timeout Error Interrupt */
+#define TPTOERR_vect            _VECTOR(32)
+#define TPTOERR_vect_num        32
+
+/* LF receiver Identifier 0 Interrupt */
+#define LFID0INT_vect            _VECTOR(33)
+#define LFID0INT_vect_num        33
+
+/* LF receiver Identifier 1 Interrupt */
+#define LFID1INT_vect            _VECTOR(34)
+#define LFID1INT_vect_num        34
+
+/* LF receiver Frame End Interrupt */
+#define LFFEINT_vect            _VECTOR(35)
+#define LFFEINT_vect_num        35
+
+/* LF receiver Bit Count Reached Interrupt */
+#define LFBCR_vect            _VECTOR(36)
+#define LFBCR_vect_num        36
+
+/* LF receiver PreBurst Detected Interrupt */
+#define LFPBD_vect            _VECTOR(37)
+#define LFPBD_vect_num        37
+
+/* LF receiver Decoder Error Interrupt */
+#define LFDE_vect            _VECTOR(38)
+#define LFDE_vect_num        38
+
+/* LF receiver End of Telegram Interrupt */
+#define LFEOT_vect            _VECTOR(39)
+#define LFEOT_vect_num        39
+
+/* LF receiver Timer Compare Match Interrupt */
+#define LFTCOR_vect            _VECTOR(40)
+#define LFTCOR_vect_num        40
+
+/* LF receiver RSSI measurement Interrupt */
+#define LFRSCO_vect            _VECTOR(41)
+#define LFRSCO_vect_num        41
+
+/* LF Data FIFO Fill Level Reached Interrupt */
+#define LDFFLR_vect            _VECTOR(42)
+#define LDFFLR_vect_num        42
+
+/* LF Data FIFO Overflow or Underflow Error Interrupt */
+#define LDFOUE_vect            _VECTOR(43)
+#define LDFOUE_vect_num        43
+
+/* External input Clock monitoring Interrupt */
+#define EXCM_vect            _VECTOR(44)
+#define EXCM_vect_num        44
+
+/* EEPROM Error Correction Interrupt */
+#define E2CINT_vect            _VECTOR(45)
+#define E2CINT_vect_num        45
+
+/* EEPROM Ready Interrupt */
+#define ERDY_vect            _VECTOR(46)
+#define ERDY_vect_num        46
+
+/* Store Program Memory Ready */
+#define SPMR_vect            _VECTOR(47)
+#define SPMR_vect_num        47
+
+/* TWI1 Interrupt */
+#define TWI1_vect            _VECTOR(48)
+#define TWI1_vect_num        48
+
+/* SPI2 Interrupt */
+#define SPI2_vect            _VECTOR(49)
+#define SPI2_vect_num        49
+
+/* TWI2 Interrupt */
+#define TWI2_vect            _VECTOR(50)
+#define TWI2_vect_num        50
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 204
+#else
+#  define _VECTORS_SIZE 204U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x8000
+#  define FLASHEND     0xFFFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x8000U
+#  define FLASHEND     0xFFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      1024
+#  define RAMEND       0x05FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x05FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      2176
+#  define E2PAGESIZE  16
+#  define E2END       0x087F
+#else
+#  define E2START     0U
+#  define E2SIZE      2176U
+#  define E2PAGESIZE  16U
+#  define E2END       0x087FU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_PCEE1       (unsigned char)~_BV(0)
+#define FUSE_EEACC       (unsigned char)~_BV(1)
+#define FUSE_BOOTRST     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_CKSTART     (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x69
+
+
+
+
+#endif /* #ifdef _AVR_ATA5702M322_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa5782.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa5782.h
@@ -1,1843 +1,1853 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATA5782_H_INCLUDED
-#define _AVR_ATA5782_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa5782.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PRR0    _SFR_IO8(0x01)
-#define PRSPI   0
-#define PRRXDC  1
-#define PRTXDC  2
-#define PRCRC   3
-#define PRVM    4
-#define PRCO    5
-
-#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRRXDC)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO))
-#define __AVR_HAVE_PRR0_PRSPI
-#define __AVR_HAVE_PRR0_PRRXDC
-#define __AVR_HAVE_PRR0_PRTXDC
-#define __AVR_HAVE_PRR0_PRCRC
-#define __AVR_HAVE_PRR0_PRVM
-#define __AVR_HAVE_PRR0_PRCO
-
-#define PRR1    _SFR_IO8(0x02)
-#define PRT1    0
-#define PRT2    1
-#define PRT3    2
-#define PRT4    3
-#define PRT5    4
-
-#define __AVR_HAVE_PRR1	((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5))
-#define __AVR_HAVE_PRR1_PRT1
-#define __AVR_HAVE_PRR1_PRT2
-#define __AVR_HAVE_PRR1_PRT3
-#define __AVR_HAVE_PRR1_PRT4
-#define __AVR_HAVE_PRR1_PRT5
-
-#define PRR2    _SFR_IO8(0x03)
-#define PRXB    0
-#define PRXA    1
-#define PRSF    2
-#define PRDF    3
-#define PRIDS   4
-#define PRRS    5
-#define PRSSM   7
-
-#define __AVR_HAVE_PRR2	((1<<PRXB)|(1<<PRXA)|(1<<PRSF)|(1<<PRDF)|(1<<PRIDS)|(1<<PRRS)|(1<<PRSSM))
-#define __AVR_HAVE_PRR2_PRXB
-#define __AVR_HAVE_PRR2_PRXA
-#define __AVR_HAVE_PRR2_PRSF
-#define __AVR_HAVE_PRR2_PRDF
-#define __AVR_HAVE_PRR2_PRIDS
-#define __AVR_HAVE_PRR2_PRRS
-#define __AVR_HAVE_PRR2_PRSSM
-
-#define RDPR    _SFR_IO8(0x04)
-#define PRPTB   0
-#define PRPTA   1
-#define PRFLT   2
-#define PRTMP   3
-#define APRPTB  4
-#define APRPTA  5
-#define ARDPRF  6
-#define RDPRF   7
-
-#define PINB    _SFR_IO8(0x05)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x06)
-#define DDRB7   7
-// Inserted "DDB7" from "DDRB7" due to compatibility
-#define DDB7    7
-#define DDRB6   6
-// Inserted "DDB6" from "DDRB6" due to compatibility
-#define DDB6    6
-#define DDRB5   5
-// Inserted "DDB5" from "DDRB5" due to compatibility
-#define DDB5    5
-#define DDRB4   4
-// Inserted "DDB4" from "DDRB4" due to compatibility
-#define DDB4    4
-#define DDRB3   3
-// Inserted "DDB3" from "DDRB3" due to compatibility
-#define DDB3    3
-#define DDRB2   2
-// Inserted "DDB2" from "DDRB2" due to compatibility
-#define DDB2    2
-#define DDRB1   1
-// Inserted "DDB1" from "DDRB1" due to compatibility
-#define DDB1    1
-#define DDRB0   0
-// Inserted "DDB0" from "DDRB0" due to compatibility
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x07)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINC    _SFR_IO8(0x08)
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x09)
-#define DDRC5   5
-// Inserted "DDC5" from "DDRC5" due to compatibility
-#define DDC5    5
-#define DDRC4   4
-// Inserted "DDC4" from "DDRC4" due to compatibility
-#define DDC4    4
-#define DDRC3   3
-// Inserted "DDC3" from "DDRC3" due to compatibility
-#define DDC3    3
-#define DDRC2   2
-// Inserted "DDC2" from "DDRC2" due to compatibility
-#define DDC2    2
-#define DDRC1   1
-// Inserted "DDC1" from "DDRC1" due to compatibility
-#define DDC1    1
-#define DDRC0   0
-// Inserted "DDC0" from "DDRC0" due to compatibility
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x0A)
-#define PORTC5  5
-#define PORTC4  4
-#define PORTC3  3
-#define PORTC2  2
-#define PORTC1  1
-#define PORTC0  0
-
-/* Reserved [0x0B..0x0C] */
-
-#define RDSIFR  _SFR_IO8(0x0D)
-#define NBITA   0
-#define NBITB   1
-#define EOTA    2
-#define EOTB    3
-#define SOTA    4
-#define SOTB    5
-#define WCOA    6
-#define WCOB    7
-
-#define MCUCR   _SFR_IO8(0x0E)
-#define IVCE    0
-#define IVSEL   1
-#define SPIIO   2
-#define ENPS    3
-#define PUD     4
-#define PB4HS   5
-#define PB7LS   6
-#define PB7HS   7
-
-#define PCIFR   _SFR_IO8(0x0F)
-#define PCIF0   0
-#define PCIF1   1
-
-#define T0CR    _SFR_IO8(0x10)
-#define T0PS0   0
-#define T0PS1   1
-#define T0PS2   2
-#define T0IE    3
-#define T0PR    4
-
-#define T1CR    _SFR_IO8(0x11)
-#define T1OTM   0
-#define T1CTM   1
-#define T1CRM   2
-#define T1TOP   4
-#define T1RES   5
-#define T1TOS   6
-#define T1ENA   7
-
-#define T2CR    _SFR_IO8(0x12)
-#define T2OTM   0
-#define T2CTM   1
-#define T2CRM   2
-#define T2TOP   4
-#define T2RES   5
-#define T2TOS   6
-#define T2ENA   7
-
-#define T3CR    _SFR_IO8(0x13)
-#define T3OTM   0
-#define T3CTM   1
-#define T3CRM   2
-#define T3CPRM  3
-#define T3TOP   4
-#define T3RES   5
-#define T3TOS   6
-#define T3ENA   7
-
-#define T4CR    _SFR_IO8(0x14)
-#define T4OTM   0
-#define T4CTM   1
-#define T4CRM   2
-#define T4CPRM  3
-#define T4TOP   4
-#define T4RES   5
-#define T4TOS   6
-#define T4ENA   7
-
-#define T1IFR   _SFR_IO8(0x15)
-#define T1OFF   0
-#define T1COF   1
-
-#define T2IFR   _SFR_IO8(0x16)
-#define T2OFF   0
-#define T2COF   1
-
-#define T3IFR   _SFR_IO8(0x17)
-#define T3OFF   0
-#define T3COF   1
-#define T3ICF   2
-
-#define T4IFR   _SFR_IO8(0x18)
-#define T4OFF   0
-#define T4COF   1
-#define T4ICF   2
-
-#define T5IFR   _SFR_IO8(0x19)
-#define T5OFF   0
-#define T5COF   1
-
-#define GPIOR0  _SFR_IO8(0x1A)
-
-#define GPIOR3  _SFR_IO8(0x1B)
-
-#define GPIOR4  _SFR_IO8(0x1C)
-
-#define GPIOR5  _SFR_IO8(0x1D)
-
-#define GPIOR6  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-#define EEPAGE  6
-#define NVMBSY  7
-
-#define EEDR    _SFR_IO8(0x20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define EEPR    _SFR_IO8(0x23)
-#define EEAP0   0
-#define EEAP1   1
-#define EEAP2   2
-#define EEAP3   3
-
-#define GPIOR1  _SFR_IO8(0x24)
-
-#define GPIOR2  _SFR_IO8(0x25)
-
-#define PCICR   _SFR_IO8(0x26)
-#define PCIE0   0
-#define PCIE1   1
-
-#define EIMSK   _SFR_IO8(0x27)
-#define INT0    0
-#define INT1    1
-
-#define EIFR    _SFR_IO8(0x28)
-#define INTF0   0
-#define INTF1   1
-
-#define CRCDIR  _SFR_IO8(0x29)
-
-#define VMCSR   _SFR_IO8(0x2A)
-#define VMLS0   0
-#define VMLS1   1
-#define VMLS2   2
-#define VMLS3   3
-#define VMIM    4
-#define VMF     5
-
-#define MCUSR   _SFR_IO8(0x2B)
-#define PORF    0
-#define EXTRF   1
-#define WDRF    3
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define RXIF    4
-#define TXIF    5
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-#define T0IFR   _SFR_IO8(0x2F)
-#define T0F     0
-
-/* Reserved [0x30] */
-
-#define DWDR    _SFR_IO8(0x31)
-
-/* Reserved [0x32] */
-
-#define RDCR    _SFR_IO8(0x33)
-#define RDPU    0
-#define ADIVEN  1
-#define RDEN    2
-
-#define EOTSA   _SFR_IO8(0x34)
-#define CARFA   0
-#define AMPFA   1
-#define SYTFA   2
-#define MANFA   3
-#define TMOFA   4
-#define TELRA   5
-#define RRFA    6
-#define EOTBF   7
-
-#define EOTCA   _SFR_IO8(0x35)
-#define CARFEA  0
-#define AMPFEA  1
-#define SYTFEA  2
-#define MANFEA  3
-#define TMOFEA  4
-#define TELREA  5
-#define RRFEA   6
-#define EOTBFE  7
-
-#define EOTSB   _SFR_IO8(0x36)
-#define CARFB   0
-#define AMPFB   1
-#define SYTFB   2
-#define MANFB   3
-#define TMOFB   4
-#define TELRB   5
-#define RRFB    6
-#define EOTAF   7
-
-#define EOTCB   _SFR_IO8(0x37)
-#define CARFEB  0
-#define AMPFEB  1
-#define SYTFEB  2
-#define MANFEB  3
-#define TMOFEB  4
-#define TELREB  5
-#define RRFEB   6
-#define EOTAFE  7
-
-#define SMCR    _SFR_IO8(0x38)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define CMCR    _SFR_IO8(0x39)
-#define CMM0    0
-#define CMM1    1
-#define CMM2    2
-#define CCS     3
-#define SRCD    4
-#define CMONEN  6
-#define CMCCE   7
-
-#define CMIMR   _SFR_IO8(0x3A)
-#define ECIE    0
-
-#define CLPR    _SFR_IO8(0x3B)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLTPS0  3
-#define CLTPS1  4
-#define CLTPS2  5
-#define CLPCE   7
-
-#define SPMCSR  _SFR_IO8(0x3C)
-#define SELFPRGEN 0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define SPMIE   7
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define FSEN    _SFR_MEM8(0x60)
-#define SDPU    0
-#define SDEN    1
-
-/* Reserved [0x61..0x63] */
-
-#define FFREQ1L _SFR_MEM8(0x64)
-
-#define FFREQ1M _SFR_MEM8(0x65)
-
-#define FFREQ1H _SFR_MEM8(0x66)
-
-#define FFREQ2L _SFR_MEM8(0x67)
-
-#define FFREQ2M _SFR_MEM8(0x68)
-
-#define FFREQ2H _SFR_MEM8(0x69)
-
-/* Reserved [0x6A] */
-
-#define EICRA   _SFR_MEM8(0x6B)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-#define PCMSK0  _SFR_MEM8(0x6C)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6D)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-
-#define WDTCR   _SFR_MEM8(0x6E)
-#define WDPS0   0
-#define WDPS1   1
-#define WDPS2   2
-#define WDE     3
-#define WDCE    4
-
-#define T1CNT   _SFR_MEM8(0x6F)
-
-#define T1COR   _SFR_MEM8(0x70)
-
-#define T1MR    _SFR_MEM8(0x71)
-#define T1CS0   0
-#define T1CS1   1
-#define T1PS0   2
-#define T1PS1   3
-#define T1PS2   4
-#define T1PS3   5
-#define T1DC0   6
-#define T1DC1   7
-
-#define T1IMR   _SFR_MEM8(0x72)
-#define T1OIM   0
-#define T1CIM   1
-
-#define T2CNT   _SFR_MEM8(0x73)
-
-#define T2COR   _SFR_MEM8(0x74)
-
-#define T2MR    _SFR_MEM8(0x75)
-#define T2CS0   0
-#define T2CS1   1
-#define T2PS0   2
-#define T2PS1   3
-#define T2PS2   4
-#define T2PS3   5
-#define T2DC0   6
-#define T2DC1   7
-
-#define T2IMR   _SFR_MEM8(0x76)
-#define T2OIM   0
-#define T2CIM   1
-
-/* Combine T3CNTL and T3CNTH */
-#define T3CNT   _SFR_MEM16(0x77)
-
-#define T3CNTL  _SFR_MEM8(0x77)
-#define T3CNTH  _SFR_MEM8(0x78)
-
-/* Combine T3CORL and T3CORH */
-#define T3COR   _SFR_MEM16(0x79)
-
-#define T3CORL  _SFR_MEM8(0x79)
-#define T3CORH  _SFR_MEM8(0x7A)
-
-/* Combine T3ICRL and T3ICRH */
-#define T3ICR   _SFR_MEM16(0x7B)
-
-#define T3ICRL  _SFR_MEM8(0x7B)
-#define T3ICRH  _SFR_MEM8(0x7C)
-
-#define T3MRA   _SFR_MEM8(0x7D)
-#define T3CS0   0
-#define T3CS1   1
-#define T3PS0   2
-#define T3PS1   3
-#define T3PS2   4
-
-#define T3MRB   _SFR_MEM8(0x7E)
-#define T3SCE   1
-#define T3CNC   2
-#define T3CE0   3
-#define T3CE1   4
-#define T3ICS0  5
-#define T3ICS1  6
-#define T3ICS2  7
-
-#define T3IMR   _SFR_MEM8(0x7F)
-#define T3OIM   0
-#define T3CIM   1
-#define T3CPIM  2
-
-/* Combine T4CNTL and T4CNTH */
-#define T4CNT   _SFR_MEM16(0x80)
-
-#define T4CNTL  _SFR_MEM8(0x80)
-#define T4CNTH  _SFR_MEM8(0x81)
-
-/* Combine T4CORL and T4CORH */
-#define T4COR   _SFR_MEM16(0x82)
-
-#define T4CORL  _SFR_MEM8(0x82)
-#define T4CORH  _SFR_MEM8(0x83)
-
-/* Combine T4ICRL and T4ICRH */
-#define T4ICR   _SFR_MEM16(0x84)
-
-#define T4ICRL  _SFR_MEM8(0x84)
-#define T4ICRH  _SFR_MEM8(0x85)
-
-#define T4MRA   _SFR_MEM8(0x86)
-#define T4CS0   0
-#define T4CS1   1
-#define T4PS0   2
-#define T4PS1   3
-#define T4PS2   4
-
-#define T4MRB   _SFR_MEM8(0x87)
-#define T4SCE   1
-#define T4CNC   2
-#define T4CE0   3
-#define T4CE1   4
-#define T4ICS0  5
-#define T4ICS1  6
-#define T4ICS2  7
-
-#define T4IMR   _SFR_MEM8(0x88)
-#define T4OIM   0
-#define T4CIM   1
-#define T4CPIM  2
-
-/* Reserved [0x89] */
-
-/* Combine T5OCRL and T5OCRH */
-#define T5OCR   _SFR_MEM16(0x8A)
-
-#define T5OCRL  _SFR_MEM8(0x8A)
-#define T5OCRH  _SFR_MEM8(0x8B)
-
-#define T5CCR   _SFR_MEM8(0x8C)
-#define T5CS0   0
-#define T5CS1   1
-#define T5CS2   2
-#define T5CTC   3
-
-/* Combine T5CNTL and T5CNTH */
-#define T5CNT   _SFR_MEM16(0x8D)
-
-#define T5CNTL  _SFR_MEM8(0x8D)
-#define T5CNTH  _SFR_MEM8(0x8E)
-
-#define T5IMR   _SFR_MEM8(0x8F)
-#define T5OIM   0
-#define T5CIM   1
-
-#define GTCCR   _SFR_MEM8(0x90)
-#define PSR10   0
-#define TSM     7
-
-#define SOTSB   _SFR_MEM8(0x91)
-#define CAROB   0
-#define AMPOB   1
-#define SYTOB   2
-#define MANOB   3
-#define WUPOB   4
-#define SFIDOB  5
-#define RROB    6
-#define WCOAO   7
-
-#define SOTSA   _SFR_MEM8(0x92)
-#define CAROA   0
-#define AMPOA   1
-#define SYTOA   2
-#define MANOA   3
-#define WUPOA   4
-#define SFIDOA  5
-#define RROA    6
-#define WCOBO   7
-
-#define SOTCB   _SFR_MEM8(0x93)
-#define CAROEB  0
-#define AMPOEB  1
-#define SYTOEB  2
-#define MANOEB  3
-#define WUPEB   4
-#define SFIDEB  5
-#define RROEB   6
-#define WCOAOE  7
-
-#define SOTCA   _SFR_MEM8(0x94)
-#define CAROEA  0
-#define AMPOEA  1
-#define SYTOEA  2
-#define MANOEA  3
-#define WUPEA   4
-#define SFIDEA  5
-#define RROEA   6
-#define WCOBOE  7
-
-#define TESRB   _SFR_MEM8(0x95)
-#define CRCOB   0
-#define EOTLB0  1
-#define EOTLB1  2
-
-#define TESRA   _SFR_MEM8(0x96)
-#define CRCOA   0
-#define EOTLA0  1
-#define EOTLA1  2
-
-/* Reserved [0x97] */
-
-#define RDSIMR  _SFR_MEM8(0x98)
-#define NBITAM  0
-#define NBITBM  1
-#define EOTAM   2
-#define EOTBM   3
-#define SOTAM   4
-#define SOTBM   5
-#define WCOAM   6
-#define WCOBM   7
-
-#define RDOCR   _SFR_MEM8(0x99)
-#define TMDS0   1
-#define TMDS1   2
-#define ETRPA   3
-#define ETRPB   4
-#define RDSIDA  5
-#define RDSIDB  6
-
-/* Reserved [0x9A] */
-
-#define TEMPL   _SFR_MEM8(0x9B)
-
-#define TEMPH   _SFR_MEM8(0x9C)
-
-#define SYCB    _SFR_MEM8(0x9D)
-#define SYCSB0  0
-#define SYCSB1  1
-#define SYCSB2  2
-#define SYCSB3  3
-#define SYTLB0  4
-#define SYTLB1  5
-#define SYTLB2  6
-#define SYTLB3  7
-
-#define SYCA    _SFR_MEM8(0x9E)
-#define SYCSA0  0
-#define SYCSA1  1
-#define SYCSA2  2
-#define SYCSA3  3
-#define SYTLA0  4
-#define SYTLA1  5
-#define SYTLA2  6
-#define SYTLA3  7
-
-#define RXFOB   _SFR_MEM8(0x9F)
-
-#define RXFOA   _SFR_MEM8(0xA0)
-
-#define DMMB    _SFR_MEM8(0xA1)
-#define DMATB0  0
-#define DMATB1  1
-#define DMATB2  2
-#define DMATB3  3
-#define DMATB4  4
-#define DMPB    5
-#define DMHB    6
-#define DMNEB   7
-
-#define DMMA    _SFR_MEM8(0xA2)
-#define DMATA0  0
-#define DMATA1  1
-#define DMATA2  2
-#define DMATA3  3
-#define DMATA4  4
-#define DMPA    5
-#define DMHA    6
-#define DMNEA   7
-
-#define DMCDB   _SFR_MEM8(0xA3)
-#define DMCLB0  0
-#define DMCLB1  1
-#define DMCLB2  2
-#define DMCLB3  3
-#define DMCLB4  4
-#define DMCTB0  5
-#define DMCTB1  6
-#define DMCTB2  7
-
-#define DMCDA   _SFR_MEM8(0xA4)
-#define DMCLA0  0
-#define DMCLA1  1
-#define DMCLA2  2
-#define DMCLA3  3
-#define DMCLA4  4
-#define DMCTA0  5
-#define DMCTA1  6
-#define DMCTA2  7
-
-#define DMCRB   _SFR_MEM8(0xA5)
-#define DMPGB0  0
-#define DMPGB1  1
-#define DMPGB2  2
-#define DMPGB3  3
-#define DMPGB4  4
-#define SASKB   5
-#define SY1TB   6
-#define DMARB   7
-
-#define DMCRA   _SFR_MEM8(0xA6)
-#define DMPGA0  0
-#define DMPGA1  1
-#define DMPGA2  2
-#define DMPGA3  3
-#define DMPGA4  4
-#define SASKA   5
-#define SY1TA   6
-#define DMARA   7
-
-#define DMDRB   _SFR_MEM8(0xA7)
-#define DMAB0   0
-#define DMAB1   1
-#define DMAB2   2
-#define DMAB3   3
-#define DMDNB0  4
-#define DMDNB1  5
-#define DMDNB2  6
-#define DMDNB3  7
-
-#define DMDRA   _SFR_MEM8(0xA8)
-#define DMAA0   0
-#define DMAA1   1
-#define DMAA2   2
-#define DMAA3   3
-#define DMDNA0  4
-#define DMDNA1  5
-#define DMDNA2  6
-#define DMDNA3  7
-
-#define CHCR    _SFR_MEM8(0xA9)
-#define BWM0    0
-#define BWM1    1
-#define BWM2    2
-#define BWM3    3
-
-#define CHDN    _SFR_MEM8(0xAA)
-#define BBDN0   0
-#define BBDN1   1
-#define BBDN2   2
-#define BBDN3   3
-#define BBDN4   4
-#define ADCDN   5
-
-#define SFIDCB  _SFR_MEM8(0xAB)
-#define SFIDTB0 0
-#define SFIDTB1 1
-#define SFIDTB2 2
-#define SFIDTB3 3
-#define SFIDTB4 4
-#define SEMEB   7
-
-#define SFIDLB  _SFR_MEM8(0xAC)
-#define SFIDLB0 0
-#define SFIDLB1 1
-#define SFIDLB2 2
-#define SFIDLB3 3
-#define SFIDLB4 4
-#define SFIDLB5 5
-
-#define WUPTB   _SFR_MEM8(0xAD)
-#define WUPTB0  0
-#define WUPTB1  1
-#define WUPTB2  2
-#define WUPTB3  3
-#define WUPTB4  4
-
-#define WUPLB   _SFR_MEM8(0xAE)
-#define WUPLB0  0
-#define WUPLB1  1
-#define WUPLB2  2
-#define WUPLB3  3
-#define WUPLB4  4
-#define WUPLB5  5
-
-#define SFID1B  _SFR_MEM8(0xAF)
-
-#define SFID2B  _SFR_MEM8(0xB0)
-
-#define SFID3B  _SFR_MEM8(0xB1)
-
-#define SFID4B  _SFR_MEM8(0xB2)
-
-#define WUP1B   _SFR_MEM8(0xB3)
-
-#define WUP2B   _SFR_MEM8(0xB4)
-
-#define WUP3B   _SFR_MEM8(0xB5)
-
-#define WUP4B   _SFR_MEM8(0xB6)
-
-#define SFIDCA  _SFR_MEM8(0xB7)
-#define SFIDTA0 0
-#define SFIDTA1 1
-#define SFIDTA2 2
-#define SFIDTA3 3
-#define SFIDTA4 4
-#define SEMEA   7
-
-#define SFIDLA  _SFR_MEM8(0xB8)
-#define SFIDLA0 0
-#define SFIDLA1 1
-#define SFIDLA2 2
-#define SFIDLA3 3
-#define SFIDLA4 4
-#define SFIDLA5 5
-
-#define WUPTA   _SFR_MEM8(0xB9)
-#define WUPTA0  0
-#define WUPTA1  1
-#define WUPTA2  2
-#define WUPTA3  3
-#define WUPTA4  4
-
-#define WUPLA   _SFR_MEM8(0xBA)
-#define WUPLA0  0
-#define WUPLA1  1
-#define WUPLA2  2
-#define WUPLA3  3
-#define WUPLA4  4
-#define WUPLA5  5
-
-#define SFID1A  _SFR_MEM8(0xBB)
-
-#define SFID2A  _SFR_MEM8(0xBC)
-
-#define SFID3A  _SFR_MEM8(0xBD)
-
-#define SFID4A  _SFR_MEM8(0xBE)
-
-#define WUP1A   _SFR_MEM8(0xBF)
-
-#define WUP2A   _SFR_MEM8(0xC0)
-
-#define WUP3A   _SFR_MEM8(0xC1)
-
-#define WUP4A   _SFR_MEM8(0xC2)
-
-#define CLKOD   _SFR_MEM8(0xC3)
-
-#define CLKOCR  _SFR_MEM8(0xC4)
-#define CLKOS0  0
-#define CLKOS1  1
-#define CLKOEN  2
-
-#define XFUSE   _SFR_MEM8(0xC5)
-
-#define SRCCAL  _SFR_MEM8(0xC6)
-#define SRCCAL0 0
-#define SRCCAL1 1
-#define SRCCAL2 2
-#define SRCCAL3 3
-#define SRCCAL4 4
-#define SRCCAL5 5
-#define SRCTC0  6
-#define SRCTC1  7
-
-#define FRCCAL  _SFR_MEM8(0xC7)
-#define FRCCAL0 0
-#define FRCCAL1 1
-#define FRCCAL2 2
-#define FRCCAL3 3
-#define FRCCAL4 4
-#define FRCTC   5
-
-#define CMSR    _SFR_MEM8(0xC8)
-#define ECF     0
-
-#define CMOCR   _SFR_MEM8(0xC9)
-#define FRCAO   0
-#define SRCAO   1
-#define FRCACT  2
-#define SRCACT  3
-
-#define SUPFR   _SFR_MEM8(0xCA)
-#define AVCCRF  0
-#define AVCCLF  1
-
-#define SUPCR   _SFR_MEM8(0xCB)
-#define AVCCRM  0
-#define AVCCLM  1
-#define PVEN    2
-#define DVDIS   4
-#define AVEN    5
-#define AVDIC   6
-
-/* Reserved [0xCC] */
-
-#define SUPCA2  _SFR_MEM8(0xCD)
-#define BGCAL0  0
-#define BGCAL1  1
-#define BGCAL2  2
-#define BGCAL3  3
-
-#define SUPCA3  _SFR_MEM8(0xCE)
-#define ACAL4   0
-#define ACAL5   1
-#define ACAL6   2
-#define ACAL7   3
-#define DCAL4   4
-#define DCAL5   5
-#define DCAL6   6
-
-#define SUPCA4  _SFR_MEM8(0xCF)
-#define ACAL0   0
-#define ACAL1   1
-#define ACAL2   2
-#define ACAL3   3
-#define DCAL0   4
-#define DCAL1   5
-#define DCAL2   6
-#define DCAL3   7
-
-#define CALRDY  _SFR_MEM8(0xD0)
-
-#define VMCAL   _SFR_MEM8(0xD1)
-#define VMCAL0  0
-#define VMCAL1  1
-#define VMCAL2  2
-
-#define DFS     _SFR_MEM8(0xD2)
-#define DFFLRF  0
-#define DFUFL   1
-#define DFOFL   2
-
-/* Combine DFTLL and DFTLH */
-#define DFTL    _SFR_MEM16(0xD3)
-
-#define DFTLL   _SFR_MEM8(0xD3)
-#define DFTLH   _SFR_MEM8(0xD4)
-
-#define DFL     _SFR_MEM8(0xD5)
-#define DFFLS0  0
-#define DFFLS1  1
-#define DFFLS2  2
-#define DFFLS3  3
-#define DFFLS4  4
-#define DFFLS5  5
-#define DFCLR   7
-
-#define DFWP    _SFR_MEM8(0xD6)
-#define DFWP0   0
-#define DFWP1   1
-#define DFWP2   2
-#define DFWP3   3
-#define DFWP4   4
-#define DFWP5   5
-
-#define DFRP    _SFR_MEM8(0xD7)
-#define DFRP0   0
-#define DFRP1   1
-#define DFRP2   2
-#define DFRP3   3
-#define DFRP4   4
-#define DFRP5   5
-
-#define DFD     _SFR_MEM8(0xD8)
-
-#define DFI     _SFR_MEM8(0xD9)
-#define DFFLIM  0
-#define DFERIM  1
-
-#define DFC     _SFR_MEM8(0xDA)
-#define DFFLC0  0
-#define DFFLC1  1
-#define DFFLC2  2
-#define DFFLC3  3
-#define DFFLC4  4
-#define DFFLC5  5
-#define DFDRA   7
-
-#define SFS     _SFR_MEM8(0xDB)
-#define SFFLRF  0
-#define SFUFL   1
-#define SFOFL   2
-
-#define SFL     _SFR_MEM8(0xDC)
-#define SFFLS0  0
-#define SFFLS1  1
-#define SFFLS2  2
-#define SFFLS3  3
-#define SFFLS4  4
-#define SFCLR   7
-
-#define SFWP    _SFR_MEM8(0xDD)
-#define SFWP0   0
-#define SFWP1   1
-#define SFWP2   2
-#define SFWP3   3
-#define SFWP4   4
-
-#define SFRP    _SFR_MEM8(0xDE)
-#define SFRP0   0
-#define SFRP1   1
-#define SFRP2   2
-#define SFRP3   3
-#define SFRP4   4
-
-#define SFD     _SFR_MEM8(0xDF)
-
-#define SFI     _SFR_MEM8(0xE0)
-#define SFFLIM  0
-#define SFERIM  1
-
-#define SFC     _SFR_MEM8(0xE1)
-#define SFFLC0  0
-#define SFFLC1  1
-#define SFFLC2  2
-#define SFFLC3  3
-#define SFFLC4  4
-#define SFDRA   7
-
-#define SSMCR   _SFR_MEM8(0xE2)
-#define SSMTX   0
-#define SSMTM   1
-#define SSMTGE  2
-#define SSMTPE  3
-#define SSMPVE  4
-#define SSMTAE  5
-#define SETRPA  6
-#define SETRPB  7
-
-#define SSMRCR  _SFR_MEM8(0xE3)
-#define SSMPA   0
-#define SSMPB   1
-#define SSMADA  2
-#define SSMADB  3
-#define SSMPVS  4
-#define SSMIFA  5
-#define SSMIDSE 6
-#define SSMTMOE 7
-
-#define SSMFBR  _SFR_MEM8(0xE4)
-#define SSMFID0 0
-#define SSMFID1 1
-#define SSMFID2 2
-#define SSMDFDT 3
-#define SSMHADT 4
-#define SSMPLDT 5
-
-#define SSMRR   _SFR_MEM8(0xE5)
-#define SSMR    0
-#define SSMST   1
-
-#define SSMSR   _SFR_MEM8(0xE6)
-#define SSMESM0 0
-#define SSMESM1 1
-#define SSMESM2 2
-#define SSMESM3 3
-#define SSMERR  7
-
-#define SSMIFR  _SFR_MEM8(0xE7)
-#define SSMIF   0
-
-#define SSMIMR  _SFR_MEM8(0xE8)
-#define SSMIM   0
-
-#define MSMSTR  _SFR_MEM8(0xE9)
-#define SSMMST0 0
-#define SSMMST1 1
-#define SSMMST2 2
-#define SSMMST3 3
-#define SSMMST4 4
-
-#define SSMSTR  _SFR_MEM8(0xEA)
-#define SSMSTA0 0
-#define SSMSTA1 1
-#define SSMSTA2 2
-#define SSMSTA3 3
-#define SSMSTA4 4
-#define SSMSTA5 5
-
-#define SSMXSR  _SFR_MEM8(0xEB)
-#define SSMSTB0 0
-#define SSMSTB1 1
-#define SSMSTB2 2
-#define SSMSTB3 3
-#define SSMSTB4 4
-#define SSMSTB5 5
-
-#define MSMCR1  _SFR_MEM8(0xEC)
-#define MSMSM00 0
-#define MSMSM01 1
-#define MSMSM02 2
-#define MSMSM03 3
-#define MSMSM10 4
-#define MSMSM11 5
-#define MSMSM12 6
-#define MSMSM13 7
-
-#define MSMCR2  _SFR_MEM8(0xED)
-#define MSMSM20 0
-#define MSMSM21 1
-#define MSMSM22 2
-#define MSMSM23 3
-#define MSMSM30 4
-#define MSMSM31 5
-#define MSMSM32 6
-#define MSMSM33 7
-
-#define MSMCR3  _SFR_MEM8(0xEE)
-#define MSMSM40 0
-#define MSMSM41 1
-#define MSMSM42 2
-#define MSMSM43 3
-#define MSMSM50 4
-#define MSMSM51 5
-#define MSMSM52 6
-#define MSMSM53 7
-
-#define MSMCR4  _SFR_MEM8(0xEF)
-#define MSMSM60 0
-#define MSMSM61 1
-#define MSMSM62 2
-#define MSMSM63 3
-#define MSMSM70 4
-#define MSMSM71 5
-#define MSMSM72 6
-#define MSMSM73 7
-
-#define GTCR    _SFR_MEM8(0xF0)
-#define RXTEHA  0
-#define GAPMA   1
-#define DARA    2
-#define IWUPA   3
-#define RXTEHB  4
-#define GAPMB   5
-#define DARB    6
-#define IWUPB   7
-
-#define SOTC1A  _SFR_MEM8(0xF1)
-#define CAROEA1 0
-#define AMPOEA1 1
-#define SYTOEA1 2
-#define MANOEA1 3
-#define WUPEA1  4
-#define SFIDEA1 5
-#define RROEA1  6
-#define WCOBOE1 7
-
-#define SOTC2A  _SFR_MEM8(0xF2)
-#define CAROEA2 0
-#define AMPOEA2 1
-#define SYTOEA2 2
-#define MANOEA2 3
-#define WUPEA2  4
-#define SFIDEA2 5
-#define RROEA2  6
-#define WCOBOE2 7
-
-#define SOTC1B  _SFR_MEM8(0xF3)
-#define CAROEB1 0
-#define AMPOEB1 1
-#define SYTOEB1 2
-#define MANOEB1 3
-#define WUPEB1  4
-#define SFIDEB1 5
-#define RROEB1  6
-#define WCOAOE1 7
-
-#define SOTC2B  _SFR_MEM8(0xF4)
-#define CAROEB2 0
-#define AMPOEB2 1
-#define SYTOEB2 2
-#define MANOEB2 3
-#define WUPEB2  4
-#define SFIDEB2 5
-#define RROEB2  6
-#define WCOAOE2 7
-
-#define EOTC1A  _SFR_MEM8(0xF5)
-#define CARFEA1 0
-#define AMPFEA1 1
-#define SYTFEA1 2
-#define MANFEA1 3
-#define TMOFEA1 4
-#define TELREA1 5
-#define RRFEA1  6
-#define EOTBFE1 7
-
-#define EOTC2A  _SFR_MEM8(0xF6)
-#define CARFEA2 0
-#define AMPFEA2 1
-#define SYTFEA2 2
-#define MANFEA2 3
-#define TMOFEA2 4
-#define TELREA2 5
-#define RRFEA2  6
-#define EOTBFE2 7
-
-#define EOTC3A  _SFR_MEM8(0xF7)
-#define CARFEA3 0
-#define AMPFEA3 1
-#define SYTFEA3 2
-#define MANFEA3 3
-#define TMOFEA3 4
-#define TELREA3 5
-#define RRFEA3  6
-#define EOTBFE3 7
-
-#define EOTC1B  _SFR_MEM8(0xF8)
-#define CARFEB1 0
-#define AMPFEB1 1
-#define SYTFEB1 2
-#define MANFEB1 3
-#define TMOFEB1 4
-#define TELREB1 5
-#define RRFEB1  6
-#define EOTAFE1 7
-
-#define EOTC2B  _SFR_MEM8(0xF9)
-#define CARFEB2 0
-#define AMPFEB2 1
-#define SYTFEB2 2
-#define MANFEB2 3
-#define TMOFEB2 4
-#define TELREB2 5
-#define RRFEB2  6
-#define EOTAFE2 7
-
-#define EOTC3B  _SFR_MEM8(0xFA)
-#define CARFEB3 0
-#define AMPFEB3 1
-#define SYTFEB3 2
-#define MANFEB3 3
-#define TMOFEB3 4
-#define TELREB3 5
-#define RRFEB3  6
-#define EOTAFE3 7
-
-#define WCOTOA  _SFR_MEM8(0xFB)
-
-#define WCOTOB  _SFR_MEM8(0xFC)
-
-#define SOTTOA  _SFR_MEM8(0xFD)
-
-#define SOTTOB  _SFR_MEM8(0xFE)
-
-#define SSMFCR  _SFR_MEM8(0xFF)
-#define SSMIDSO 0
-#define SSMIDSF 1
-
-#define FESR    _SFR_MEM8(0x100)
-#define LBSAT   0
-#define HBSAT   1
-#define XRDY    2
-#define PLCK    3
-
-#define FEEN1   _SFR_MEM8(0x101)
-#define PLEN    0
-#define PLCAL   1
-#define XTOEN   2
-#define LNAEN   3
-#define ADEN    4
-#define ADCLK   5
-#define PLSP1   6
-#define ATEN    7
-
-#define FEEN2   _SFR_MEM8(0x102)
-#define SDRX    0
-#define SDRX2   1
-#define PAEN    2
-#define TMPM    3
-#define PLPEN   4
-#define XTPEN   5
-
-#define FELNA   _SFR_MEM8(0x103)
-#define LBH0    0
-#define LBH1    1
-#define LBH2    2
-#define LBH3    3
-#define LBL0    4
-#define LBL1    5
-#define LBL2    6
-#define LBL3    7
-
-/* Reserved [0x104..0x105] */
-
-#define FEVCT   _SFR_MEM8(0x106)
-#define FEVCT0  0
-#define FEVCT1  1
-#define FEVCT2  2
-#define FEVCT3  3
-
-#define FEBT    _SFR_MEM8(0x107)
-#define CTN20   0
-#define CTN21   1
-#define RTN20   2
-#define RTN21   3
-
-#define FEMS    _SFR_MEM8(0x108)
-#define PLLS0   0
-#define PLLS1   1
-#define PLLS2   2
-#define PLLS3   3
-#define PLLM0   4
-#define PLLM1   5
-#define PLLM2   6
-#define PLLM3   7
-
-#define FETN4   _SFR_MEM8(0x109)
-#define CTN40   0
-#define CTN41   1
-#define CTN42   2
-#define CTN43   3
-#define RTN40   4
-#define RTN41   5
-#define RTN42   6
-#define RTN43   7
-
-#define FECR    _SFR_MEM8(0x10A)
-#define LBNHB   0
-#define S4N3    1
-#define ANDP    2
-#define ADHS    3
-#define PLCKG   4
-#define ANPS    5
-
-#define FEVCO   _SFR_MEM8(0x10B)
-#define CPCC0   0
-#define CPCC1   1
-#define CPCC2   2
-#define CPCC3   3
-#define VCOB0   4
-#define VCOB1   5
-#define VCOB2   6
-#define VCOB3   7
-
-#define FEALR   _SFR_MEM8(0x10C)
-#define RNGE0   0
-#define RNGE1   1
-
-#define FEANT   _SFR_MEM8(0x10D)
-#define LVLC0   0
-#define LVLC1   1
-#define LVLC2   2
-#define LVLC3   3
-
-#define FEBIA   _SFR_MEM8(0x10E)
-#define IFAEN   7
-
-/* Reserved [0x10F..0x12E] */
-
-#define RXBC1   _SFR_MEM8(0x12F)
-#define RXCEA   0
-#define RXCBLA0 1
-#define RXCBLA1 2
-#define RXMSBA  3
-#define RXCEB   4
-#define RXCBLB0 5
-#define RXCBLB1 6
-#define RXMSBB  7
-
-#define RXBC2   _SFR_MEM8(0x130)
-#define RXBPB   0
-#define RXBF    1
-#define RXBCLR  2
-
-#define RXTLLB  _SFR_MEM8(0x131)
-
-#define RXTLHB  _SFR_MEM8(0x132)
-#define RXTLHB0 0
-#define RXTLHB1 1
-#define RXTLHB2 2
-#define RXTLHB3 3
-
-#define RXCRLB  _SFR_MEM8(0x133)
-
-#define RXCRHB  _SFR_MEM8(0x134)
-
-#define RXCSBB  _SFR_MEM8(0x135)
-
-#define RXCILB  _SFR_MEM8(0x136)
-
-#define RXCIHB  _SFR_MEM8(0x137)
-
-#define RXCPLB  _SFR_MEM8(0x138)
-
-#define RXCPHB  _SFR_MEM8(0x139)
-
-#define RXDSB   _SFR_MEM8(0x13A)
-
-#define RXTLLA  _SFR_MEM8(0x13B)
-
-#define RXTLHA  _SFR_MEM8(0x13C)
-#define RXTLHA0 0
-#define RXTLHA1 1
-#define RXTLHA2 2
-#define RXTLHA3 3
-
-#define RXCRLA  _SFR_MEM8(0x13D)
-
-#define RXCRHA  _SFR_MEM8(0x13E)
-
-#define RXCSBA  _SFR_MEM8(0x13F)
-
-#define RXCILA  _SFR_MEM8(0x140)
-
-#define RXCIHA  _SFR_MEM8(0x141)
-
-#define RXCPLA  _SFR_MEM8(0x142)
-
-#define RXCPHA  _SFR_MEM8(0x143)
-
-#define RXDSA   _SFR_MEM8(0x144)
-
-#define CRCCR   _SFR_MEM8(0x145)
-#define CRCRS   0
-#define REFLI   1
-#define REFLO   2
-
-#define CRCDOR  _SFR_MEM8(0x146)
-
-#define IDB0    _SFR_MEM8(0x147)
-
-#define IDB1    _SFR_MEM8(0x148)
-
-#define IDB2    _SFR_MEM8(0x149)
-
-#define IDB3    _SFR_MEM8(0x14A)
-
-#define IDC     _SFR_MEM8(0x14B)
-#define IDL0    0
-#define IDL1    1
-#define IDBO0   2
-#define IDBO1   3
-#define IDFIM   5
-#define IDCLR   6
-#define IDCE    7
-
-#define IDS     _SFR_MEM8(0x14C)
-#define IDOK    0
-#define IDFULL  1
-
-#define RSSAV   _SFR_MEM8(0x14D)
-
-#define RSSPK   _SFR_MEM8(0x14E)
-
-#define RSSL    _SFR_MEM8(0x14F)
-
-#define RSSH    _SFR_MEM8(0x150)
-
-#define RSSC    _SFR_MEM8(0x151)
-#define RSUP0   0
-#define RSUP1   1
-#define RSUP2   2
-#define RSUP3   3
-#define RSWLH   4
-#define RSHRX   5
-#define RSPKF   6
-
-#define DBCR    _SFR_MEM8(0x152)
-#define DBMD    0
-#define DBCS    1
-#define DBTMS   2
-#define DBHA    3
-
-#define DBTC    _SFR_MEM8(0x153)
-
-#define DBENB   _SFR_MEM8(0x154)
-
-#define DBENC   _SFR_MEM8(0x155)
-
-#define DBGSW   _SFR_MEM8(0x156)
-#define DBGGS0  0
-#define DBGGS1  1
-#define DBGGS2  2
-#define DBGGS3  3
-#define CPBFOS0 4
-#define CPBFOS1 5
-#define CPBF    6
-#define DBGSE   7
-
-#define SFFR    _SFR_MEM8(0x157)
-#define RFL0    0
-#define RFL1    1
-#define RFL2    2
-#define RFC     3
-#define TFL0    4
-#define TFL1    5
-#define TFL2    6
-#define TFC     7
-
-#define SFIR    _SFR_MEM8(0x158)
-#define RIL0    0
-#define RIL1    1
-#define RIL2    2
-#define SRIE    3
-#define TIL0    4
-#define TIL1    5
-#define TIL2    6
-#define STIE    7
-
-#define EECR2   _SFR_MEM8(0x159)
-#define EEBRE   0
-
-#define PGMST   _SFR_MEM8(0x15A)
-#define PGMSYN0 0
-#define PGMSYN1 1
-#define PGMSYN2 2
-#define PGMSYN3 3
-#define PGMSYN4 4
-
-#define EEST    _SFR_MEM8(0x15B)
-#define EESYN0  0
-#define EESYN1  1
-#define EESYN2  2
-#define EESYN3  3
-
-#define RSIFG   _SFR_MEM8(0x15C)
-
-#define RSLDV   _SFR_MEM8(0x15D)
-
-#define RSHDV   _SFR_MEM8(0x15E)
-
-#define RSCOM   _SFR_MEM8(0x15F)
-#define RSDC    0
-#define RSIFC   1
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCI0_vect            _VECTOR(3)
-#define PCI0_vect_num        3
-
-/* Pin Change Interrupt Request 1 */
-#define PCI1_vect            _VECTOR(4)
-#define PCI1_vect_num        4
-
-/* Voltage Monitoring Interrupt */
-#define VMON_vect            _VECTOR(5)
-#define VMON_vect_num        5
-
-/* AVCC Reset Interrupt */
-#define AVCCR_vect            _VECTOR(6)
-#define AVCCR_vect_num        6
-
-/* AVCC Low Interrupt */
-#define AVCCL_vect            _VECTOR(7)
-#define AVCCL_vect_num        7
-
-/* Timer 0 Interval Interrupt */
-#define T0INT_vect            _VECTOR(8)
-#define T0INT_vect_num        8
-
-/* Timer/Counter1 Compare Match Interrupt */
-#define T1COMP_vect            _VECTOR(9)
-#define T1COMP_vect_num        9
-
-/* Timer/Counter1 Overflow Interrupt */
-#define T1OVF_vect            _VECTOR(10)
-#define T1OVF_vect_num        10
-
-/* Timer/Counter2 Compare Match Interrupt */
-#define T2COMP_vect            _VECTOR(11)
-#define T2COMP_vect_num        11
-
-/* Timer/Counter2 Overflow Interrupt */
-#define T2OVF_vect            _VECTOR(12)
-#define T2OVF_vect_num        12
-
-/* Timer/Counter3 Capture Event Interrupt */
-#define T3CAP_vect            _VECTOR(13)
-#define T3CAP_vect_num        13
-
-/* Timer/Counter3 Compare Match Interrupt */
-#define T3COMP_vect            _VECTOR(14)
-#define T3COMP_vect_num        14
-
-/* Timer/Counter3 Overflow Interrupt */
-#define T3OVF_vect            _VECTOR(15)
-#define T3OVF_vect_num        15
-
-/* Timer/Counter4 Capture Event Interrupt */
-#define T4CAP_vect            _VECTOR(16)
-#define T4CAP_vect_num        16
-
-/* Timer/Counter4 Compare Match Interrupt */
-#define T4COMP_vect            _VECTOR(17)
-#define T4COMP_vect_num        17
-
-/* Timer/Counter4 Overflow Interrupt */
-#define T4OVF_vect            _VECTOR(18)
-#define T4OVF_vect_num        18
-
-/* Timer/Counter5 Compare Match Interrupt */
-#define T5COMP_vect            _VECTOR(19)
-#define T5COMP_vect_num        19
-
-/* Timer/Counter5 Overflow Interrupt */
-#define T5OVF_vect            _VECTOR(20)
-#define T5OVF_vect_num        20
-
-/* SPI Serial Transfer Complete Interrupt */
-#define SPI_vect            _VECTOR(21)
-#define SPI_vect_num        21
-
-/* SPI Rx Buffer Interrupt */
-#define SRX_FIFO_vect            _VECTOR(22)
-#define SRX_FIFO_vect_num        22
-
-/* SPI Tx Buffer Interrupt */
-#define STX_FIFO_vect            _VECTOR(23)
-#define STX_FIFO_vect_num        23
-
-/* Sequencer State Machine Interrupt */
-#define SSM_vect            _VECTOR(24)
-#define SSM_vect_num        24
-
-/* Data FIFO fill level reached Interrupt */
-#define DFFLR_vect            _VECTOR(25)
-#define DFFLR_vect_num        25
-
-/* Data FIFO overflow or underflow error Interrupt */
-#define DFOUE_vect            _VECTOR(26)
-#define DFOUE_vect_num        26
-
-/* RSSI/Preamble FIFO fill level reached Interrupt */
-#define SFFLR_vect            _VECTOR(27)
-#define SFFLR_vect_num        27
-
-/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
-#define SFOUE_vect            _VECTOR(28)
-#define SFOUE_vect_num        28
-
-/* Tx Modulator Telegram Finish Interrupt */
-#define TMTCF_vect            _VECTOR(29)
-#define TMTCF_vect_num        29
-
-/* UHF receiver wake up ok on Rx path B */
-#define UHF_WCOB_vect            _VECTOR(30)
-#define UHF_WCOB_vect_num        30
-
-/* UHF receiver wake up ok on Rx path A */
-#define UHF_WCOA_vect            _VECTOR(31)
-#define UHF_WCOA_vect_num        31
-
-/* UHF receiver start of telegram ok on Rx path B */
-#define UHF_SOTB_vect            _VECTOR(32)
-#define UHF_SOTB_vect_num        32
-
-/* UHF receiver start of telegram ok on Rx path A */
-#define UHF_SOTA_vect            _VECTOR(33)
-#define UHF_SOTA_vect_num        33
-
-/* UHF receiver end of telegram on Rx path B */
-#define UHF_EOTB_vect            _VECTOR(34)
-#define UHF_EOTB_vect_num        34
-
-/* UHF receiver end of telegram on Rx path A */
-#define UHF_EOTA_vect            _VECTOR(35)
-#define UHF_EOTA_vect_num        35
-
-/* UHF receiver new bit on Rx path B */
-#define UHF_NBITB_vect            _VECTOR(36)
-#define UHF_NBITB_vect_num        36
-
-/* UHF receiver new bit on Rx path A */
-#define UHF_NBITA_vect            _VECTOR(37)
-#define UHF_NBITA_vect_num        37
-
-/* External input Clock monitoring Interrupt */
-#define EXCM_vect            _VECTOR(38)
-#define EXCM_vect_num        38
-
-/* EEPROM Ready Interrupt */
-#define ERDY_vect            _VECTOR(39)
-#define ERDY_vect_num        39
-
-/* Store Program Memory Ready */
-#define SPMR_vect            _VECTOR(40)
-#define SPMR_vect_num        40
-
-/* IDSCAN Full Interrupt */
-#define IDFULL_vect            _VECTOR(41)
-#define IDFULL_vect_num        41
-
-#define _VECTORS_SIZE 168
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x8000
-#define FLASHEND     0xCFFF
-#define RAMSTART     0x0200
-#define RAMSIZE      1024
-#define RAMEND       0x05FF
-#define E2START     0
-#define E2SIZE      1024
-#define E2PAGESIZE  16
-#define E2END       0x03FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Fuse Byte */
-#define FUSE_EXTCLKEN    (unsigned char)~_BV(0)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(1)
-#define FUSE_BOOTRST     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x65
-
-
-#endif /* #ifdef _AVR_ATA5782_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5782_H_INCLUDED
+#define _AVR_ATA5782_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5782.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PRR0    _SFR_IO8(0x01)
+#define PRSPI   0
+#define PRRXDC  1
+#define PRTXDC  2
+#define PRCRC   3
+#define PRVM    4
+#define PRCO    5
+
+#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRRXDC)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO))
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRRXDC
+#define __AVR_HAVE_PRR0_PRTXDC
+#define __AVR_HAVE_PRR0_PRCRC
+#define __AVR_HAVE_PRR0_PRVM
+#define __AVR_HAVE_PRR0_PRCO
+
+#define PRR1    _SFR_IO8(0x02)
+#define PRT1    0
+#define PRT2    1
+#define PRT3    2
+#define PRT4    3
+#define PRT5    4
+
+#define __AVR_HAVE_PRR1	((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5))
+#define __AVR_HAVE_PRR1_PRT1
+#define __AVR_HAVE_PRR1_PRT2
+#define __AVR_HAVE_PRR1_PRT3
+#define __AVR_HAVE_PRR1_PRT4
+#define __AVR_HAVE_PRR1_PRT5
+
+#define PRR2    _SFR_IO8(0x03)
+#define PRXB    0
+#define PRXA    1
+#define PRSF    2
+#define PRDF    3
+#define PRIDS   4
+#define PRRS    5
+#define PRSSM   7
+
+#define __AVR_HAVE_PRR2	((1<<PRXB)|(1<<PRXA)|(1<<PRSF)|(1<<PRDF)|(1<<PRIDS)|(1<<PRRS)|(1<<PRSSM))
+#define __AVR_HAVE_PRR2_PRXB
+#define __AVR_HAVE_PRR2_PRXA
+#define __AVR_HAVE_PRR2_PRSF
+#define __AVR_HAVE_PRR2_PRDF
+#define __AVR_HAVE_PRR2_PRIDS
+#define __AVR_HAVE_PRR2_PRRS
+#define __AVR_HAVE_PRR2_PRSSM
+
+#define RDPR    _SFR_IO8(0x04)
+#define PRPTB   0
+#define PRPTA   1
+#define PRFLT   2
+#define PRTMP   3
+#define APRPTB  4
+#define APRPTA  5
+#define ARDPRF  6
+#define RDPRF   7
+
+#define PINB    _SFR_IO8(0x05)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x06)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x07)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x08)
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x09)
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x0A)
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+/* Reserved [0x0B..0x0C] */
+
+#define RDSIFR  _SFR_IO8(0x0D)
+#define NBITA   0
+#define NBITB   1
+#define EOTA    2
+#define EOTB    3
+#define SOTA    4
+#define SOTB    5
+#define WCOA    6
+#define WCOB    7
+
+#define MCUCR   _SFR_IO8(0x0E)
+#define IVCE    0
+#define IVSEL   1
+#define SPIIO   2
+#define ENPS    3
+#define PUD     4
+#define PB4HS   5
+#define PB7LS   6
+#define PB7HS   7
+
+#define PCIFR   _SFR_IO8(0x0F)
+#define PCIF0   0
+#define PCIF1   1
+
+#define T0CR    _SFR_IO8(0x10)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+#define T1CR    _SFR_IO8(0x11)
+#define T1OTM   0
+#define T1CTM   1
+#define T1CRM   2
+#define T1TOP   4
+#define T1RES   5
+#define T1TOS   6
+#define T1ENA   7
+
+#define T2CR    _SFR_IO8(0x12)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2TOP   4
+#define T2RES   5
+#define T2TOS   6
+#define T2ENA   7
+
+#define T3CR    _SFR_IO8(0x13)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3TOS   6
+#define T3ENA   7
+
+#define T4CR    _SFR_IO8(0x14)
+#define T4OTM   0
+#define T4CTM   1
+#define T4CRM   2
+#define T4CPRM  3
+#define T4TOP   4
+#define T4RES   5
+#define T4TOS   6
+#define T4ENA   7
+
+#define T1IFR   _SFR_IO8(0x15)
+#define T1OFF   0
+#define T1COF   1
+
+#define T2IFR   _SFR_IO8(0x16)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x17)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+
+#define T4IFR   _SFR_IO8(0x18)
+#define T4OFF   0
+#define T4COF   1
+#define T4ICF   2
+
+#define T5IFR   _SFR_IO8(0x19)
+#define T5OFF   0
+#define T5COF   1
+
+#define GPIOR0  _SFR_IO8(0x1A)
+
+#define GPIOR3  _SFR_IO8(0x1B)
+
+#define GPIOR4  _SFR_IO8(0x1C)
+
+#define GPIOR5  _SFR_IO8(0x1D)
+
+#define GPIOR6  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EEPAGE  6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define GPIOR1  _SFR_IO8(0x24)
+
+#define GPIOR2  _SFR_IO8(0x25)
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+#define INT1    1
+
+#define EIFR    _SFR_IO8(0x28)
+#define INTF0   0
+#define INTF1   1
+
+#define CRCDIR  _SFR_IO8(0x29)
+
+#define VMCSR   _SFR_IO8(0x2A)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMF     5
+
+#define MCUSR   _SFR_IO8(0x2B)
+#define PORF    0
+#define EXTRF   1
+#define WDRF    3
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define RXIF    4
+#define TXIF    5
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define T0IFR   _SFR_IO8(0x2F)
+#define T0F     0
+
+/* Reserved [0x30] */
+
+#define DWDR    _SFR_IO8(0x31)
+
+/* Reserved [0x32] */
+
+#define RDCR    _SFR_IO8(0x33)
+#define RDPU    0
+#define ADIVEN  1
+#define RDEN    2
+
+#define EOTSA   _SFR_IO8(0x34)
+#define CARFA   0
+#define AMPFA   1
+#define SYTFA   2
+#define MANFA   3
+#define TMOFA   4
+#define TELRA   5
+#define RRFA    6
+#define EOTBF   7
+
+#define EOTCA   _SFR_IO8(0x35)
+#define CARFEA  0
+#define AMPFEA  1
+#define SYTFEA  2
+#define MANFEA  3
+#define TMOFEA  4
+#define TELREA  5
+#define RRFEA   6
+#define EOTBFE  7
+
+#define EOTSB   _SFR_IO8(0x36)
+#define CARFB   0
+#define AMPFB   1
+#define SYTFB   2
+#define MANFB   3
+#define TMOFB   4
+#define TELRB   5
+#define RRFB    6
+#define EOTAF   7
+
+#define EOTCB   _SFR_IO8(0x37)
+#define CARFEB  0
+#define AMPFEB  1
+#define SYTFEB  2
+#define MANFEB  3
+#define TMOFEB  4
+#define TELREB  5
+#define RRFEB   6
+#define EOTAFE  7
+
+#define SMCR    _SFR_IO8(0x38)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define CMCR    _SFR_IO8(0x39)
+#define CMM0    0
+#define CMM1    1
+#define CMM2    2
+#define CCS     3
+#define SRCD    4
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMIMR   _SFR_IO8(0x3A)
+#define ECIE    0
+
+#define CLPR    _SFR_IO8(0x3B)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLPCE   7
+
+#define SPMCSR  _SFR_IO8(0x3C)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define SPMIE   7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define FSEN    _SFR_MEM8(0x60)
+#define SDPU    0
+#define SDEN    1
+
+/* Reserved [0x61..0x63] */
+
+#define FFREQ1L _SFR_MEM8(0x64)
+
+#define FFREQ1M _SFR_MEM8(0x65)
+
+#define FFREQ1H _SFR_MEM8(0x66)
+
+#define FFREQ2L _SFR_MEM8(0x67)
+
+#define FFREQ2M _SFR_MEM8(0x68)
+
+#define FFREQ2H _SFR_MEM8(0x69)
+
+/* Reserved [0x6A] */
+
+#define EICRA   _SFR_MEM8(0x6B)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+#define PCMSK0  _SFR_MEM8(0x6C)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6D)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+
+#define WDTCR   _SFR_MEM8(0x6E)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+#define T1CNT   _SFR_MEM8(0x6F)
+
+#define T1COR   _SFR_MEM8(0x70)
+
+#define T1MR    _SFR_MEM8(0x71)
+#define T1CS0   0
+#define T1CS1   1
+#define T1PS0   2
+#define T1PS1   3
+#define T1PS2   4
+#define T1PS3   5
+#define T1DC0   6
+#define T1DC1   7
+
+#define T1IMR   _SFR_MEM8(0x72)
+#define T1OIM   0
+#define T1CIM   1
+
+#define T2CNT   _SFR_MEM8(0x73)
+
+#define T2COR   _SFR_MEM8(0x74)
+
+#define T2MR    _SFR_MEM8(0x75)
+#define T2CS0   0
+#define T2CS1   1
+#define T2PS0   2
+#define T2PS1   3
+#define T2PS2   4
+#define T2PS3   5
+#define T2DC0   6
+#define T2DC1   7
+
+#define T2IMR   _SFR_MEM8(0x76)
+#define T2OIM   0
+#define T2CIM   1
+
+/* Combine T3CNTL and T3CNTH */
+#define T3CNT   _SFR_MEM16(0x77)
+
+#define T3CNTL  _SFR_MEM8(0x77)
+#define T3CNTH  _SFR_MEM8(0x78)
+
+/* Combine T3CORL and T3CORH */
+#define T3COR   _SFR_MEM16(0x79)
+
+#define T3CORL  _SFR_MEM8(0x79)
+#define T3CORH  _SFR_MEM8(0x7A)
+
+/* Combine T3ICRL and T3ICRH */
+#define T3ICR   _SFR_MEM16(0x7B)
+
+#define T3ICRL  _SFR_MEM8(0x7B)
+#define T3ICRH  _SFR_MEM8(0x7C)
+
+#define T3MRA   _SFR_MEM8(0x7D)
+#define T3CS0   0
+#define T3CS1   1
+#define T3PS0   2
+#define T3PS1   3
+#define T3PS2   4
+
+#define T3MRB   _SFR_MEM8(0x7E)
+#define T3SCE   1
+#define T3CNC   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3ICS0  5
+#define T3ICS1  6
+#define T3ICS2  7
+
+#define T3IMR   _SFR_MEM8(0x7F)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+
+/* Combine T4CNTL and T4CNTH */
+#define T4CNT   _SFR_MEM16(0x80)
+
+#define T4CNTL  _SFR_MEM8(0x80)
+#define T4CNTH  _SFR_MEM8(0x81)
+
+/* Combine T4CORL and T4CORH */
+#define T4COR   _SFR_MEM16(0x82)
+
+#define T4CORL  _SFR_MEM8(0x82)
+#define T4CORH  _SFR_MEM8(0x83)
+
+/* Combine T4ICRL and T4ICRH */
+#define T4ICR   _SFR_MEM16(0x84)
+
+#define T4ICRL  _SFR_MEM8(0x84)
+#define T4ICRH  _SFR_MEM8(0x85)
+
+#define T4MRA   _SFR_MEM8(0x86)
+#define T4CS0   0
+#define T4CS1   1
+#define T4PS0   2
+#define T4PS1   3
+#define T4PS2   4
+
+#define T4MRB   _SFR_MEM8(0x87)
+#define T4SCE   1
+#define T4CNC   2
+#define T4CE0   3
+#define T4CE1   4
+#define T4ICS0  5
+#define T4ICS1  6
+#define T4ICS2  7
+
+#define T4IMR   _SFR_MEM8(0x88)
+#define T4OIM   0
+#define T4CIM   1
+#define T4CPIM  2
+
+/* Reserved [0x89] */
+
+/* Combine T5OCRL and T5OCRH */
+#define T5OCR   _SFR_MEM16(0x8A)
+
+#define T5OCRL  _SFR_MEM8(0x8A)
+#define T5OCRH  _SFR_MEM8(0x8B)
+
+#define T5CCR   _SFR_MEM8(0x8C)
+#define T5CS0   0
+#define T5CS1   1
+#define T5CS2   2
+#define T5CTC   3
+
+/* Combine T5CNTL and T5CNTH */
+#define T5CNT   _SFR_MEM16(0x8D)
+
+#define T5CNTL  _SFR_MEM8(0x8D)
+#define T5CNTH  _SFR_MEM8(0x8E)
+
+#define T5IMR   _SFR_MEM8(0x8F)
+#define T5OIM   0
+#define T5CIM   1
+
+#define GTCCR   _SFR_MEM8(0x90)
+#define PSR10   0
+#define TSM     7
+
+#define SOTSB   _SFR_MEM8(0x91)
+#define CAROB   0
+#define AMPOB   1
+#define SYTOB   2
+#define MANOB   3
+#define WUPOB   4
+#define SFIDOB  5
+#define RROB    6
+#define WCOAO   7
+
+#define SOTSA   _SFR_MEM8(0x92)
+#define CAROA   0
+#define AMPOA   1
+#define SYTOA   2
+#define MANOA   3
+#define WUPOA   4
+#define SFIDOA  5
+#define RROA    6
+#define WCOBO   7
+
+#define SOTCB   _SFR_MEM8(0x93)
+#define CAROEB  0
+#define AMPOEB  1
+#define SYTOEB  2
+#define MANOEB  3
+#define WUPEB   4
+#define SFIDEB  5
+#define RROEB   6
+#define WCOAOE  7
+
+#define SOTCA   _SFR_MEM8(0x94)
+#define CAROEA  0
+#define AMPOEA  1
+#define SYTOEA  2
+#define MANOEA  3
+#define WUPEA   4
+#define SFIDEA  5
+#define RROEA   6
+#define WCOBOE  7
+
+#define TESRB   _SFR_MEM8(0x95)
+#define CRCOB   0
+#define EOTLB0  1
+#define EOTLB1  2
+
+#define TESRA   _SFR_MEM8(0x96)
+#define CRCOA   0
+#define EOTLA0  1
+#define EOTLA1  2
+
+/* Reserved [0x97] */
+
+#define RDSIMR  _SFR_MEM8(0x98)
+#define NBITAM  0
+#define NBITBM  1
+#define EOTAM   2
+#define EOTBM   3
+#define SOTAM   4
+#define SOTBM   5
+#define WCOAM   6
+#define WCOBM   7
+
+#define RDOCR   _SFR_MEM8(0x99)
+#define TMDS0   1
+#define TMDS1   2
+#define ETRPA   3
+#define ETRPB   4
+#define RDSIDA  5
+#define RDSIDB  6
+
+/* Reserved [0x9A] */
+
+#define TEMPL   _SFR_MEM8(0x9B)
+
+#define TEMPH   _SFR_MEM8(0x9C)
+
+#define SYCB    _SFR_MEM8(0x9D)
+#define SYCSB0  0
+#define SYCSB1  1
+#define SYCSB2  2
+#define SYCSB3  3
+#define SYTLB0  4
+#define SYTLB1  5
+#define SYTLB2  6
+#define SYTLB3  7
+
+#define SYCA    _SFR_MEM8(0x9E)
+#define SYCSA0  0
+#define SYCSA1  1
+#define SYCSA2  2
+#define SYCSA3  3
+#define SYTLA0  4
+#define SYTLA1  5
+#define SYTLA2  6
+#define SYTLA3  7
+
+#define RXFOB   _SFR_MEM8(0x9F)
+
+#define RXFOA   _SFR_MEM8(0xA0)
+
+#define DMMB    _SFR_MEM8(0xA1)
+#define DMATB0  0
+#define DMATB1  1
+#define DMATB2  2
+#define DMATB3  3
+#define DMATB4  4
+#define DMPB    5
+#define DMHB    6
+#define DMNEB   7
+
+#define DMMA    _SFR_MEM8(0xA2)
+#define DMATA0  0
+#define DMATA1  1
+#define DMATA2  2
+#define DMATA3  3
+#define DMATA4  4
+#define DMPA    5
+#define DMHA    6
+#define DMNEA   7
+
+#define DMCDB   _SFR_MEM8(0xA3)
+#define DMCLB0  0
+#define DMCLB1  1
+#define DMCLB2  2
+#define DMCLB3  3
+#define DMCLB4  4
+#define DMCTB0  5
+#define DMCTB1  6
+#define DMCTB2  7
+
+#define DMCDA   _SFR_MEM8(0xA4)
+#define DMCLA0  0
+#define DMCLA1  1
+#define DMCLA2  2
+#define DMCLA3  3
+#define DMCLA4  4
+#define DMCTA0  5
+#define DMCTA1  6
+#define DMCTA2  7
+
+#define DMCRB   _SFR_MEM8(0xA5)
+#define DMPGB0  0
+#define DMPGB1  1
+#define DMPGB2  2
+#define DMPGB3  3
+#define DMPGB4  4
+#define SASKB   5
+#define SY1TB   6
+#define DMARB   7
+
+#define DMCRA   _SFR_MEM8(0xA6)
+#define DMPGA0  0
+#define DMPGA1  1
+#define DMPGA2  2
+#define DMPGA3  3
+#define DMPGA4  4
+#define SASKA   5
+#define SY1TA   6
+#define DMARA   7
+
+#define DMDRB   _SFR_MEM8(0xA7)
+#define DMAB0   0
+#define DMAB1   1
+#define DMAB2   2
+#define DMAB3   3
+#define DMDNB0  4
+#define DMDNB1  5
+#define DMDNB2  6
+#define DMDNB3  7
+
+#define DMDRA   _SFR_MEM8(0xA8)
+#define DMAA0   0
+#define DMAA1   1
+#define DMAA2   2
+#define DMAA3   3
+#define DMDNA0  4
+#define DMDNA1  5
+#define DMDNA2  6
+#define DMDNA3  7
+
+#define CHCR    _SFR_MEM8(0xA9)
+#define BWM0    0
+#define BWM1    1
+#define BWM2    2
+#define BWM3    3
+
+#define CHDN    _SFR_MEM8(0xAA)
+#define BBDN0   0
+#define BBDN1   1
+#define BBDN2   2
+#define BBDN3   3
+#define BBDN4   4
+#define ADCDN   5
+
+#define SFIDCB  _SFR_MEM8(0xAB)
+#define SFIDTB0 0
+#define SFIDTB1 1
+#define SFIDTB2 2
+#define SFIDTB3 3
+#define SFIDTB4 4
+#define SEMEB   7
+
+#define SFIDLB  _SFR_MEM8(0xAC)
+#define SFIDLB0 0
+#define SFIDLB1 1
+#define SFIDLB2 2
+#define SFIDLB3 3
+#define SFIDLB4 4
+#define SFIDLB5 5
+
+#define WUPTB   _SFR_MEM8(0xAD)
+#define WUPTB0  0
+#define WUPTB1  1
+#define WUPTB2  2
+#define WUPTB3  3
+#define WUPTB4  4
+
+#define WUPLB   _SFR_MEM8(0xAE)
+#define WUPLB0  0
+#define WUPLB1  1
+#define WUPLB2  2
+#define WUPLB3  3
+#define WUPLB4  4
+#define WUPLB5  5
+
+#define SFID1B  _SFR_MEM8(0xAF)
+
+#define SFID2B  _SFR_MEM8(0xB0)
+
+#define SFID3B  _SFR_MEM8(0xB1)
+
+#define SFID4B  _SFR_MEM8(0xB2)
+
+#define WUP1B   _SFR_MEM8(0xB3)
+
+#define WUP2B   _SFR_MEM8(0xB4)
+
+#define WUP3B   _SFR_MEM8(0xB5)
+
+#define WUP4B   _SFR_MEM8(0xB6)
+
+#define SFIDCA  _SFR_MEM8(0xB7)
+#define SFIDTA0 0
+#define SFIDTA1 1
+#define SFIDTA2 2
+#define SFIDTA3 3
+#define SFIDTA4 4
+#define SEMEA   7
+
+#define SFIDLA  _SFR_MEM8(0xB8)
+#define SFIDLA0 0
+#define SFIDLA1 1
+#define SFIDLA2 2
+#define SFIDLA3 3
+#define SFIDLA4 4
+#define SFIDLA5 5
+
+#define WUPTA   _SFR_MEM8(0xB9)
+#define WUPTA0  0
+#define WUPTA1  1
+#define WUPTA2  2
+#define WUPTA3  3
+#define WUPTA4  4
+
+#define WUPLA   _SFR_MEM8(0xBA)
+#define WUPLA0  0
+#define WUPLA1  1
+#define WUPLA2  2
+#define WUPLA3  3
+#define WUPLA4  4
+#define WUPLA5  5
+
+#define SFID1A  _SFR_MEM8(0xBB)
+
+#define SFID2A  _SFR_MEM8(0xBC)
+
+#define SFID3A  _SFR_MEM8(0xBD)
+
+#define SFID4A  _SFR_MEM8(0xBE)
+
+#define WUP1A   _SFR_MEM8(0xBF)
+
+#define WUP2A   _SFR_MEM8(0xC0)
+
+#define WUP3A   _SFR_MEM8(0xC1)
+
+#define WUP4A   _SFR_MEM8(0xC2)
+
+#define CLKOD   _SFR_MEM8(0xC3)
+
+#define CLKOCR  _SFR_MEM8(0xC4)
+#define CLKOS0  0
+#define CLKOS1  1
+#define CLKOEN  2
+
+#define XFUSE   _SFR_MEM8(0xC5)
+
+#define SRCCAL  _SFR_MEM8(0xC6)
+#define SRCCAL0 0
+#define SRCCAL1 1
+#define SRCCAL2 2
+#define SRCCAL3 3
+#define SRCCAL4 4
+#define SRCCAL5 5
+#define SRCTC0  6
+#define SRCTC1  7
+
+#define FRCCAL  _SFR_MEM8(0xC7)
+#define FRCCAL0 0
+#define FRCCAL1 1
+#define FRCCAL2 2
+#define FRCCAL3 3
+#define FRCCAL4 4
+#define FRCTC   5
+
+#define CMSR    _SFR_MEM8(0xC8)
+#define ECF     0
+
+#define CMOCR   _SFR_MEM8(0xC9)
+#define FRCAO   0
+#define SRCAO   1
+#define FRCACT  2
+#define SRCACT  3
+
+#define SUPFR   _SFR_MEM8(0xCA)
+#define AVCCRF  0
+#define AVCCLF  1
+
+#define SUPCR   _SFR_MEM8(0xCB)
+#define AVCCRM  0
+#define AVCCLM  1
+#define PVEN    2
+#define DVDIS   4
+#define AVEN    5
+#define AVDIC   6
+
+/* Reserved [0xCC] */
+
+#define SUPCA2  _SFR_MEM8(0xCD)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL3  3
+
+#define SUPCA3  _SFR_MEM8(0xCE)
+#define ACAL4   0
+#define ACAL5   1
+#define ACAL6   2
+#define ACAL7   3
+#define DCAL4   4
+#define DCAL5   5
+#define DCAL6   6
+
+#define SUPCA4  _SFR_MEM8(0xCF)
+#define ACAL0   0
+#define ACAL1   1
+#define ACAL2   2
+#define ACAL3   3
+#define DCAL0   4
+#define DCAL1   5
+#define DCAL2   6
+#define DCAL3   7
+
+#define CALRDY  _SFR_MEM8(0xD0)
+
+#define VMCAL   _SFR_MEM8(0xD1)
+#define VMCAL0  0
+#define VMCAL1  1
+#define VMCAL2  2
+
+#define DFS     _SFR_MEM8(0xD2)
+#define DFFLRF  0
+#define DFUFL   1
+#define DFOFL   2
+
+/* Combine DFTLL and DFTLH */
+#define DFTL    _SFR_MEM16(0xD3)
+
+#define DFTLL   _SFR_MEM8(0xD3)
+#define DFTLH   _SFR_MEM8(0xD4)
+
+#define DFL     _SFR_MEM8(0xD5)
+#define DFFLS0  0
+#define DFFLS1  1
+#define DFFLS2  2
+#define DFFLS3  3
+#define DFFLS4  4
+#define DFFLS5  5
+#define DFCLR   7
+
+#define DFWP    _SFR_MEM8(0xD6)
+#define DFWP0   0
+#define DFWP1   1
+#define DFWP2   2
+#define DFWP3   3
+#define DFWP4   4
+#define DFWP5   5
+
+#define DFRP    _SFR_MEM8(0xD7)
+#define DFRP0   0
+#define DFRP1   1
+#define DFRP2   2
+#define DFRP3   3
+#define DFRP4   4
+#define DFRP5   5
+
+#define DFD     _SFR_MEM8(0xD8)
+
+#define DFI     _SFR_MEM8(0xD9)
+#define DFFLIM  0
+#define DFERIM  1
+
+#define DFC     _SFR_MEM8(0xDA)
+#define DFFLC0  0
+#define DFFLC1  1
+#define DFFLC2  2
+#define DFFLC3  3
+#define DFFLC4  4
+#define DFFLC5  5
+#define DFDRA   7
+
+#define SFS     _SFR_MEM8(0xDB)
+#define SFFLRF  0
+#define SFUFL   1
+#define SFOFL   2
+
+#define SFL     _SFR_MEM8(0xDC)
+#define SFFLS0  0
+#define SFFLS1  1
+#define SFFLS2  2
+#define SFFLS3  3
+#define SFFLS4  4
+#define SFCLR   7
+
+#define SFWP    _SFR_MEM8(0xDD)
+#define SFWP0   0
+#define SFWP1   1
+#define SFWP2   2
+#define SFWP3   3
+#define SFWP4   4
+
+#define SFRP    _SFR_MEM8(0xDE)
+#define SFRP0   0
+#define SFRP1   1
+#define SFRP2   2
+#define SFRP3   3
+#define SFRP4   4
+
+#define SFD     _SFR_MEM8(0xDF)
+
+#define SFI     _SFR_MEM8(0xE0)
+#define SFFLIM  0
+#define SFERIM  1
+
+#define SFC     _SFR_MEM8(0xE1)
+#define SFFLC0  0
+#define SFFLC1  1
+#define SFFLC2  2
+#define SFFLC3  3
+#define SFFLC4  4
+#define SFDRA   7
+
+#define SSMCR   _SFR_MEM8(0xE2)
+#define SSMTX   0
+#define SSMTM   1
+#define SSMTGE  2
+#define SSMTPE  3
+#define SSMPVE  4
+#define SSMTAE  5
+#define SETRPA  6
+#define SETRPB  7
+
+#define SSMRCR  _SFR_MEM8(0xE3)
+#define SSMPA   0
+#define SSMPB   1
+#define SSMADA  2
+#define SSMADB  3
+#define SSMPVS  4
+#define SSMIFA  5
+#define SSMIDSE 6
+#define SSMTMOE 7
+
+#define SSMFBR  _SFR_MEM8(0xE4)
+#define SSMFID0 0
+#define SSMFID1 1
+#define SSMFID2 2
+#define SSMDFDT 3
+#define SSMHADT 4
+#define SSMPLDT 5
+
+#define SSMRR   _SFR_MEM8(0xE5)
+#define SSMR    0
+#define SSMST   1
+
+#define SSMSR   _SFR_MEM8(0xE6)
+#define SSMESM0 0
+#define SSMESM1 1
+#define SSMESM2 2
+#define SSMESM3 3
+#define SSMERR  7
+
+#define SSMIFR  _SFR_MEM8(0xE7)
+#define SSMIF   0
+
+#define SSMIMR  _SFR_MEM8(0xE8)
+#define SSMIM   0
+
+#define MSMSTR  _SFR_MEM8(0xE9)
+#define SSMMST0 0
+#define SSMMST1 1
+#define SSMMST2 2
+#define SSMMST3 3
+#define SSMMST4 4
+
+#define SSMSTR  _SFR_MEM8(0xEA)
+#define SSMSTA0 0
+#define SSMSTA1 1
+#define SSMSTA2 2
+#define SSMSTA3 3
+#define SSMSTA4 4
+#define SSMSTA5 5
+
+#define SSMXSR  _SFR_MEM8(0xEB)
+#define SSMSTB0 0
+#define SSMSTB1 1
+#define SSMSTB2 2
+#define SSMSTB3 3
+#define SSMSTB4 4
+#define SSMSTB5 5
+
+#define MSMCR1  _SFR_MEM8(0xEC)
+#define MSMSM00 0
+#define MSMSM01 1
+#define MSMSM02 2
+#define MSMSM03 3
+#define MSMSM10 4
+#define MSMSM11 5
+#define MSMSM12 6
+#define MSMSM13 7
+
+#define MSMCR2  _SFR_MEM8(0xED)
+#define MSMSM20 0
+#define MSMSM21 1
+#define MSMSM22 2
+#define MSMSM23 3
+#define MSMSM30 4
+#define MSMSM31 5
+#define MSMSM32 6
+#define MSMSM33 7
+
+#define MSMCR3  _SFR_MEM8(0xEE)
+#define MSMSM40 0
+#define MSMSM41 1
+#define MSMSM42 2
+#define MSMSM43 3
+#define MSMSM50 4
+#define MSMSM51 5
+#define MSMSM52 6
+#define MSMSM53 7
+
+#define MSMCR4  _SFR_MEM8(0xEF)
+#define MSMSM60 0
+#define MSMSM61 1
+#define MSMSM62 2
+#define MSMSM63 3
+#define MSMSM70 4
+#define MSMSM71 5
+#define MSMSM72 6
+#define MSMSM73 7
+
+#define GTCR    _SFR_MEM8(0xF0)
+#define RXTEHA  0
+#define GAPMA   1
+#define DARA    2
+#define IWUPA   3
+#define RXTEHB  4
+#define GAPMB   5
+#define DARB    6
+#define IWUPB   7
+
+#define SOTC1A  _SFR_MEM8(0xF1)
+#define CAROEA1 0
+#define AMPOEA1 1
+#define SYTOEA1 2
+#define MANOEA1 3
+#define WUPEA1  4
+#define SFIDEA1 5
+#define RROEA1  6
+#define WCOBOE1 7
+
+#define SOTC2A  _SFR_MEM8(0xF2)
+#define CAROEA2 0
+#define AMPOEA2 1
+#define SYTOEA2 2
+#define MANOEA2 3
+#define WUPEA2  4
+#define SFIDEA2 5
+#define RROEA2  6
+#define WCOBOE2 7
+
+#define SOTC1B  _SFR_MEM8(0xF3)
+#define CAROEB1 0
+#define AMPOEB1 1
+#define SYTOEB1 2
+#define MANOEB1 3
+#define WUPEB1  4
+#define SFIDEB1 5
+#define RROEB1  6
+#define WCOAOE1 7
+
+#define SOTC2B  _SFR_MEM8(0xF4)
+#define CAROEB2 0
+#define AMPOEB2 1
+#define SYTOEB2 2
+#define MANOEB2 3
+#define WUPEB2  4
+#define SFIDEB2 5
+#define RROEB2  6
+#define WCOAOE2 7
+
+#define EOTC1A  _SFR_MEM8(0xF5)
+#define CARFEA1 0
+#define AMPFEA1 1
+#define SYTFEA1 2
+#define MANFEA1 3
+#define TMOFEA1 4
+#define TELREA1 5
+#define RRFEA1  6
+#define EOTBFE1 7
+
+#define EOTC2A  _SFR_MEM8(0xF6)
+#define CARFEA2 0
+#define AMPFEA2 1
+#define SYTFEA2 2
+#define MANFEA2 3
+#define TMOFEA2 4
+#define TELREA2 5
+#define RRFEA2  6
+#define EOTBFE2 7
+
+#define EOTC3A  _SFR_MEM8(0xF7)
+#define CARFEA3 0
+#define AMPFEA3 1
+#define SYTFEA3 2
+#define MANFEA3 3
+#define TMOFEA3 4
+#define TELREA3 5
+#define RRFEA3  6
+#define EOTBFE3 7
+
+#define EOTC1B  _SFR_MEM8(0xF8)
+#define CARFEB1 0
+#define AMPFEB1 1
+#define SYTFEB1 2
+#define MANFEB1 3
+#define TMOFEB1 4
+#define TELREB1 5
+#define RRFEB1  6
+#define EOTAFE1 7
+
+#define EOTC2B  _SFR_MEM8(0xF9)
+#define CARFEB2 0
+#define AMPFEB2 1
+#define SYTFEB2 2
+#define MANFEB2 3
+#define TMOFEB2 4
+#define TELREB2 5
+#define RRFEB2  6
+#define EOTAFE2 7
+
+#define EOTC3B  _SFR_MEM8(0xFA)
+#define CARFEB3 0
+#define AMPFEB3 1
+#define SYTFEB3 2
+#define MANFEB3 3
+#define TMOFEB3 4
+#define TELREB3 5
+#define RRFEB3  6
+#define EOTAFE3 7
+
+#define WCOTOA  _SFR_MEM8(0xFB)
+
+#define WCOTOB  _SFR_MEM8(0xFC)
+
+#define SOTTOA  _SFR_MEM8(0xFD)
+
+#define SOTTOB  _SFR_MEM8(0xFE)
+
+#define SSMFCR  _SFR_MEM8(0xFF)
+#define SSMIDSO 0
+#define SSMIDSF 1
+
+#define FESR    _SFR_MEM8(0x100)
+#define LBSAT   0
+#define HBSAT   1
+#define XRDY    2
+#define PLCK    3
+
+#define FEEN1   _SFR_MEM8(0x101)
+#define PLEN    0
+#define PLCAL   1
+#define XTOEN   2
+#define LNAEN   3
+#define ADEN    4
+#define ADCLK   5
+#define PLSP1   6
+#define ATEN    7
+
+#define FEEN2   _SFR_MEM8(0x102)
+#define SDRX    0
+#define SDRX2   1
+#define PAEN    2
+#define TMPM    3
+#define PLPEN   4
+#define XTPEN   5
+
+#define FELNA   _SFR_MEM8(0x103)
+#define LBH0    0
+#define LBH1    1
+#define LBH2    2
+#define LBH3    3
+#define LBL0    4
+#define LBL1    5
+#define LBL2    6
+#define LBL3    7
+
+/* Reserved [0x104..0x105] */
+
+#define FEVCT   _SFR_MEM8(0x106)
+#define FEVCT0  0
+#define FEVCT1  1
+#define FEVCT2  2
+#define FEVCT3  3
+
+#define FEBT    _SFR_MEM8(0x107)
+#define CTN20   0
+#define CTN21   1
+#define RTN20   2
+#define RTN21   3
+
+#define FEMS    _SFR_MEM8(0x108)
+#define PLLS0   0
+#define PLLS1   1
+#define PLLS2   2
+#define PLLS3   3
+#define PLLM0   4
+#define PLLM1   5
+#define PLLM2   6
+#define PLLM3   7
+
+#define FETN4   _SFR_MEM8(0x109)
+#define CTN40   0
+#define CTN41   1
+#define CTN42   2
+#define CTN43   3
+#define RTN40   4
+#define RTN41   5
+#define RTN42   6
+#define RTN43   7
+
+#define FECR    _SFR_MEM8(0x10A)
+#define LBNHB   0
+#define S4N3    1
+#define ANDP    2
+#define ADHS    3
+#define PLCKG   4
+#define ANPS    5
+
+#define FEVCO   _SFR_MEM8(0x10B)
+#define CPCC0   0
+#define CPCC1   1
+#define CPCC2   2
+#define CPCC3   3
+#define VCOB0   4
+#define VCOB1   5
+#define VCOB2   6
+#define VCOB3   7
+
+#define FEALR   _SFR_MEM8(0x10C)
+#define RNGE0   0
+#define RNGE1   1
+
+#define FEANT   _SFR_MEM8(0x10D)
+#define LVLC0   0
+#define LVLC1   1
+#define LVLC2   2
+#define LVLC3   3
+
+#define FEBIA   _SFR_MEM8(0x10E)
+#define IFAEN   7
+
+/* Reserved [0x10F..0x12E] */
+
+#define RXBC1   _SFR_MEM8(0x12F)
+#define RXCEA   0
+#define RXCBLA0 1
+#define RXCBLA1 2
+#define RXMSBA  3
+#define RXCEB   4
+#define RXCBLB0 5
+#define RXCBLB1 6
+#define RXMSBB  7
+
+#define RXBC2   _SFR_MEM8(0x130)
+#define RXBPB   0
+#define RXBF    1
+#define RXBCLR  2
+
+#define RXTLLB  _SFR_MEM8(0x131)
+
+#define RXTLHB  _SFR_MEM8(0x132)
+#define RXTLHB0 0
+#define RXTLHB1 1
+#define RXTLHB2 2
+#define RXTLHB3 3
+
+#define RXCRLB  _SFR_MEM8(0x133)
+
+#define RXCRHB  _SFR_MEM8(0x134)
+
+#define RXCSBB  _SFR_MEM8(0x135)
+
+#define RXCILB  _SFR_MEM8(0x136)
+
+#define RXCIHB  _SFR_MEM8(0x137)
+
+#define RXCPLB  _SFR_MEM8(0x138)
+
+#define RXCPHB  _SFR_MEM8(0x139)
+
+#define RXDSB   _SFR_MEM8(0x13A)
+
+#define RXTLLA  _SFR_MEM8(0x13B)
+
+#define RXTLHA  _SFR_MEM8(0x13C)
+#define RXTLHA0 0
+#define RXTLHA1 1
+#define RXTLHA2 2
+#define RXTLHA3 3
+
+#define RXCRLA  _SFR_MEM8(0x13D)
+
+#define RXCRHA  _SFR_MEM8(0x13E)
+
+#define RXCSBA  _SFR_MEM8(0x13F)
+
+#define RXCILA  _SFR_MEM8(0x140)
+
+#define RXCIHA  _SFR_MEM8(0x141)
+
+#define RXCPLA  _SFR_MEM8(0x142)
+
+#define RXCPHA  _SFR_MEM8(0x143)
+
+#define RXDSA   _SFR_MEM8(0x144)
+
+#define CRCCR   _SFR_MEM8(0x145)
+#define CRCRS   0
+#define REFLI   1
+#define REFLO   2
+
+#define CRCDOR  _SFR_MEM8(0x146)
+
+#define IDB0    _SFR_MEM8(0x147)
+
+#define IDB1    _SFR_MEM8(0x148)
+
+#define IDB2    _SFR_MEM8(0x149)
+
+#define IDB3    _SFR_MEM8(0x14A)
+
+#define IDC     _SFR_MEM8(0x14B)
+#define IDL0    0
+#define IDL1    1
+#define IDBO0   2
+#define IDBO1   3
+#define IDFIM   5
+#define IDCLR   6
+#define IDCE    7
+
+#define IDS     _SFR_MEM8(0x14C)
+#define IDOK    0
+#define IDFULL  1
+
+#define RSSAV   _SFR_MEM8(0x14D)
+
+#define RSSPK   _SFR_MEM8(0x14E)
+
+#define RSSL    _SFR_MEM8(0x14F)
+
+#define RSSH    _SFR_MEM8(0x150)
+
+#define RSSC    _SFR_MEM8(0x151)
+#define RSUP0   0
+#define RSUP1   1
+#define RSUP2   2
+#define RSUP3   3
+#define RSWLH   4
+#define RSHRX   5
+#define RSPKF   6
+
+#define DBCR    _SFR_MEM8(0x152)
+#define DBMD    0
+#define DBCS    1
+#define DBTMS   2
+#define DBHA    3
+
+#define DBTC    _SFR_MEM8(0x153)
+
+#define DBENB   _SFR_MEM8(0x154)
+
+#define DBENC   _SFR_MEM8(0x155)
+
+#define DBGSW   _SFR_MEM8(0x156)
+#define DBGGS0  0
+#define DBGGS1  1
+#define DBGGS2  2
+#define DBGGS3  3
+#define CPBFOS0 4
+#define CPBFOS1 5
+#define CPBF    6
+#define DBGSE   7
+
+#define SFFR    _SFR_MEM8(0x157)
+#define RFL0    0
+#define RFL1    1
+#define RFL2    2
+#define RFC     3
+#define TFL0    4
+#define TFL1    5
+#define TFL2    6
+#define TFC     7
+
+#define SFIR    _SFR_MEM8(0x158)
+#define RIL0    0
+#define RIL1    1
+#define RIL2    2
+#define SRIE    3
+#define TIL0    4
+#define TIL1    5
+#define TIL2    6
+#define STIE    7
+
+#define EECR2   _SFR_MEM8(0x159)
+#define EEBRE   0
+
+#define PGMST   _SFR_MEM8(0x15A)
+#define PGMSYN0 0
+#define PGMSYN1 1
+#define PGMSYN2 2
+#define PGMSYN3 3
+#define PGMSYN4 4
+
+#define EEST    _SFR_MEM8(0x15B)
+#define EESYN0  0
+#define EESYN1  1
+#define EESYN2  2
+#define EESYN3  3
+
+#define RSIFG   _SFR_MEM8(0x15C)
+
+#define RSLDV   _SFR_MEM8(0x15D)
+
+#define RSHDV   _SFR_MEM8(0x15E)
+
+#define RSCOM   _SFR_MEM8(0x15F)
+#define RSDC    0
+#define RSIFC   1
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCI0_vect            _VECTOR(3)
+#define PCI0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCI1_vect            _VECTOR(4)
+#define PCI1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMON_vect            _VECTOR(5)
+#define VMON_vect_num        5
+
+/* AVCC Reset Interrupt */
+#define AVCCR_vect            _VECTOR(6)
+#define AVCCR_vect_num        6
+
+/* AVCC Low Interrupt */
+#define AVCCL_vect            _VECTOR(7)
+#define AVCCL_vect_num        7
+
+/* Timer 0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(8)
+#define T0INT_vect_num        8
+
+/* Timer/Counter1 Compare Match Interrupt */
+#define T1COMP_vect            _VECTOR(9)
+#define T1COMP_vect_num        9
+
+/* Timer/Counter1 Overflow Interrupt */
+#define T1OVF_vect            _VECTOR(10)
+#define T1OVF_vect_num        10
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMP_vect            _VECTOR(11)
+#define T2COMP_vect_num        11
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVF_vect            _VECTOR(12)
+#define T2OVF_vect_num        12
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAP_vect            _VECTOR(13)
+#define T3CAP_vect_num        13
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMP_vect            _VECTOR(14)
+#define T3COMP_vect_num        14
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVF_vect            _VECTOR(15)
+#define T3OVF_vect_num        15
+
+/* Timer/Counter4 Capture Event Interrupt */
+#define T4CAP_vect            _VECTOR(16)
+#define T4CAP_vect_num        16
+
+/* Timer/Counter4 Compare Match Interrupt */
+#define T4COMP_vect            _VECTOR(17)
+#define T4COMP_vect_num        17
+
+/* Timer/Counter4 Overflow Interrupt */
+#define T4OVF_vect            _VECTOR(18)
+#define T4OVF_vect_num        18
+
+/* Timer/Counter5 Compare Match Interrupt */
+#define T5COMP_vect            _VECTOR(19)
+#define T5COMP_vect_num        19
+
+/* Timer/Counter5 Overflow Interrupt */
+#define T5OVF_vect            _VECTOR(20)
+#define T5OVF_vect_num        20
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPI_vect            _VECTOR(21)
+#define SPI_vect_num        21
+
+/* SPI Rx Buffer Interrupt */
+#define SRX_FIFO_vect            _VECTOR(22)
+#define SRX_FIFO_vect_num        22
+
+/* SPI Tx Buffer Interrupt */
+#define STX_FIFO_vect            _VECTOR(23)
+#define STX_FIFO_vect_num        23
+
+/* Sequencer State Machine Interrupt */
+#define SSM_vect            _VECTOR(24)
+#define SSM_vect_num        24
+
+/* Data FIFO fill level reached Interrupt */
+#define DFFLR_vect            _VECTOR(25)
+#define DFFLR_vect_num        25
+
+/* Data FIFO overflow or underflow error Interrupt */
+#define DFOUE_vect            _VECTOR(26)
+#define DFOUE_vect_num        26
+
+/* RSSI/Preamble FIFO fill level reached Interrupt */
+#define SFFLR_vect            _VECTOR(27)
+#define SFFLR_vect_num        27
+
+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
+#define SFOUE_vect            _VECTOR(28)
+#define SFOUE_vect_num        28
+
+/* Tx Modulator Telegram Finish Interrupt */
+#define TMTCF_vect            _VECTOR(29)
+#define TMTCF_vect_num        29
+
+/* UHF receiver wake up ok on Rx path B */
+#define UHF_WCOB_vect            _VECTOR(30)
+#define UHF_WCOB_vect_num        30
+
+/* UHF receiver wake up ok on Rx path A */
+#define UHF_WCOA_vect            _VECTOR(31)
+#define UHF_WCOA_vect_num        31
+
+/* UHF receiver start of telegram ok on Rx path B */
+#define UHF_SOTB_vect            _VECTOR(32)
+#define UHF_SOTB_vect_num        32
+
+/* UHF receiver start of telegram ok on Rx path A */
+#define UHF_SOTA_vect            _VECTOR(33)
+#define UHF_SOTA_vect_num        33
+
+/* UHF receiver end of telegram on Rx path B */
+#define UHF_EOTB_vect            _VECTOR(34)
+#define UHF_EOTB_vect_num        34
+
+/* UHF receiver end of telegram on Rx path A */
+#define UHF_EOTA_vect            _VECTOR(35)
+#define UHF_EOTA_vect_num        35
+
+/* UHF receiver new bit on Rx path B */
+#define UHF_NBITB_vect            _VECTOR(36)
+#define UHF_NBITB_vect_num        36
+
+/* UHF receiver new bit on Rx path A */
+#define UHF_NBITA_vect            _VECTOR(37)
+#define UHF_NBITA_vect_num        37
+
+/* External input Clock monitoring Interrupt */
+#define EXCM_vect            _VECTOR(38)
+#define EXCM_vect_num        38
+
+/* EEPROM Ready Interrupt */
+#define ERDY_vect            _VECTOR(39)
+#define ERDY_vect_num        39
+
+/* Store Program Memory Ready */
+#define SPMR_vect            _VECTOR(40)
+#define SPMR_vect_num        40
+
+/* IDSCAN Full Interrupt */
+#define IDFULL_vect            _VECTOR(41)
+#define IDFULL_vect_num        41
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 168
+#else
+#  define _VECTORS_SIZE 168U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x8000
+#  define FLASHEND     0xCFFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x8000U
+#  define FLASHEND     0xCFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      1024
+#  define RAMEND       0x05FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x05FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  16
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  16U
+#  define E2END       0x03FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_EXTCLKEN    (unsigned char)~_BV(0)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(1)
+#define FUSE_BOOTRST     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x65
+
+
+
+
+#endif /* #ifdef _AVR_ATA5782_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa5790.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa5790.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATA5790_H_INCLUDED
 #define _AVR_ATA5790_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -92,13 +91,29 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC7  7
@@ -122,13 +137,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -684,6 +715,14 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* Transponder Mode Interrupt */
@@ -802,21 +841,44 @@
 #define SPMREADY_vect            _VECTOR(29)
 #define SPMREADY_vect_num        29
 
-#define _VECTORS_SIZE 120
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 120
+#else
+#  define _VECTORS_SIZE 120U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      2048
-#define E2PAGESIZE  16
-#define E2END       0x07FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      2048
+#  define E2PAGESIZE  16
+#  define E2END       0x07FF
+#else
+#  define E2START     0U
+#  define E2SIZE      2048U
+#  define E2PAGESIZE  16U
+#  define E2END       0x07FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -825,14 +887,17 @@
 #define FUSE_MEMORY_SIZE 1
 
 /* Fuse Byte */
-#define FUSE_CKDIV8 (unsigned char)~_BV(128)
-#define FUSE_DWEN (unsigned char)~_BV(64)
-#define FUSE_SPIEN (unsigned char)~_BV(32)
-#define FUSE_WDTON (unsigned char)~_BV(16)
-#define FUSE_EESAVE (unsigned char)~_BV(8)
-#define FUSE_Reserved (unsigned char)~_BV(4)
-#define FUSE__32OEN (unsigned char)~_BV(2)
-#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
+#define FUSE_EXTCLKEN    (unsigned char)~_BV(0)
+#define FUSE__32OEN      (unsigned char)~_BV(1)
+#define FUSE_Reserved    (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
+
+
 
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
@@ -847,10 +912,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
 
 #endif /* #ifdef _AVR_ATA5790_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa5790n.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa5790n.h
@@ -1,922 +1,932 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATA5790N_H_INCLUDED
-#define _AVR_ATA5790N_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa5790n.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDRB7   7
-// Inserted "DDB7" from "DDRB7" due to compatibility
-#define DDB7    7
-#define DDRB6   6
-// Inserted "DDB6" from "DDRB6" due to compatibility
-#define DDB6    6
-#define DDRB5   5
-// Inserted "DDB5" from "DDRB5" due to compatibility
-#define DDB5    5
-#define DDRB4   4
-// Inserted "DDB4" from "DDRB4" due to compatibility
-#define DDB4    4
-#define DDRB3   3
-// Inserted "DDB3" from "DDRB3" due to compatibility
-#define DDB3    3
-#define DDRB2   2
-// Inserted "DDB2" from "DDRB2" due to compatibility
-#define DDB2    2
-#define DDRB1   1
-// Inserted "DDB1" from "DDRB1" due to compatibility
-#define DDB1    1
-#define DDRB0   0
-// Inserted "DDB0" from "DDRB0" due to compatibility
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDRC7   7
-// Inserted "DDC7" from "DDRC7" due to compatibility
-#define DDC7    7
-#define DDRC6   6
-// Inserted "DDC6" from "DDRC6" due to compatibility
-#define DDC6    6
-#define DDRC5   5
-// Inserted "DDC5" from "DDRC5" due to compatibility
-#define DDC5    5
-#define DDRC4   4
-// Inserted "DDC4" from "DDRC4" due to compatibility
-#define DDC4    4
-#define DDRC3   3
-// Inserted "DDC3" from "DDRC3" due to compatibility
-#define DDC3    3
-#define DDRC2   2
-// Inserted "DDC2" from "DDRC2" due to compatibility
-#define DDC2    2
-#define DDRC1   1
-// Inserted "DDC1" from "DDRC1" due to compatibility
-#define DDC1    1
-#define DDRC0   0
-// Inserted "DDC0" from "DDRC0" due to compatibility
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PORTC7  7
-#define PORTC6  6
-#define PORTC5  5
-#define PORTC4  4
-#define PORTC3  3
-#define PORTC2  2
-#define PORTC1  1
-#define PORTC0  0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDRD7   7
-// Inserted "DDD7" from "DDRD7" due to compatibility
-#define DDD7    7
-#define DDRD6   6
-// Inserted "DDD6" from "DDRD6" due to compatibility
-#define DDD6    6
-#define DDRD5   5
-// Inserted "DDD5" from "DDRD5" due to compatibility
-#define DDD5    5
-#define DDRD4   4
-// Inserted "DDD4" from "DDRD4" due to compatibility
-#define DDD4    4
-#define DDRD3   3
-// Inserted "DDD3" from "DDRD3" due to compatibility
-#define DDD3    3
-#define DDRD2   2
-// Inserted "DDD2" from "DDRD2" due to compatibility
-#define DDD2    2
-#define DDRD1   1
-// Inserted "DDD1" from "DDRD1" due to compatibility
-#define DDD1    1
-#define DDRD0   0
-// Inserted "DDD0" from "DDRD0" due to compatibility
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PORTD7  7
-#define PORTD6  6
-#define PORTD5  5
-#define PORTD4  4
-#define PORTD3  3
-#define PORTD2  2
-#define PORTD1  1
-#define PORTD0  0
-
-#define T3CR2   _SFR_IO8(0x0C)
-#define T3GRES  0
-#define T3C2TM  1
-#define T3C2RM  2
-
-#define TPCR    _SFR_IO8(0x0D)
-#define TPMA    0
-#define TPMOD   1
-#define TPMS0   2
-#define TPMS1   3
-#define TPMD0   4
-#define TPMD1   5
-#define TPPSD   6
-#define TPD     7
-
-#define TPFR    _SFR_IO8(0x0E)
-#define TPF     0
-#define TPA     1
-#define TPGAP   2
-#define TPPSW   3
-
-#define CMCR    _SFR_IO8(0x0F)
-#define CMM0    0
-#define CMM1    1
-#define SRCD    2
-#define CO32D   3
-#define CCS     4
-#define ECINS   5
-#define CMONEN  6
-#define CMCCE   7
-
-#define CMSR    _SFR_IO8(0x10)
-#define ECF     0
-#define SXF     1
-#define RTCF    2
-
-#define T2CR    _SFR_IO8(0x11)
-#define T2OTM   0
-#define T2CTM   1
-#define T2CRM   2
-#define T2GRM   3
-#define T2TOP   4
-#define T2RES   5
-#define T2TS    6
-#define T2E     7
-
-#define T3CR    _SFR_IO8(0x12)
-#define T3OTM   0
-#define T3CTM   1
-#define T3CRM   2
-#define T3CPRM  3
-#define T3TOP   4
-#define T3RES   5
-#define T3CPTM  6
-#define T3E     7
-
-#define AESCR   _SFR_IO8(0x13)
-#define AESWK   0
-#define AESWD   1
-#define AESIM   2
-#define AESD    3
-#define AESXOR  4
-#define AESRES  5
-#define AESE    7
-
-#define AESSR   _SFR_IO8(0x14)
-#define AESRF   0
-#define AESERF  7
-
-#define TMIFR   _SFR_IO8(0x15)
-#define TMRXF   0
-#define TMTXF   1
-#define TMTCF   2
-#define TMRXS   3
-#define TMTXS   4
-
-#define VMSR    _SFR_IO8(0x16)
-#define VMF     0
-
-#define PCIFR   _SFR_IO8(0x17)
-#define PCIF0   0
-#define PCIF1   1
-
-#define LFFR    _SFR_IO8(0x18)
-#define LFID0F  0
-#define LFID1F  1
-#define LFFEF   2
-#define LFDBF   3
-#define LFRSF   4
-#define LFSDF   5
-#define LFMDF   6
-#define LFCAF   7
-
-#define T0IFR   _SFR_IO8(0x19)
-#define T0F     0
-
-#define T1IFR   _SFR_IO8(0x1A)
-#define T1F     0
-
-#define T2IFR   _SFR_IO8(0x1B)
-#define T2OFF   0
-#define T2COF   1
-
-#define T3IFR   _SFR_IO8(0x1C)
-#define T3OFF   0
-#define T3COF   1
-#define T3ICF   2
-#define T3CO2F  3
-
-#define EIFR    _SFR_IO8(0x1D)
-#define INTF0   0
-
-#define GPIOR   _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-#define EELP    6
-#define NVMBSY  7
-
-#define EEDR    _SFR_IO8(0x20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define EEPR    _SFR_IO8(0x23)
-#define EEAP0   0
-#define EEAP1   1
-#define EEAP2   2
-#define EEAP3   3
-
-#define EECCR   _SFR_IO8(0x24)
-#define EEL0    0
-#define EEL1    1
-#define EEL2    2
-#define EEL3    3
-
-#define EECR2   _SFR_IO8(0x25)
-#define EEBRE   0
-#define EEPAGE  1
-
-#define PCICR   _SFR_IO8(0x26)
-#define PCIE0   0
-#define PCIE1   1
-
-#define EIMSK   _SFR_IO8(0x27)
-#define INT0    0
-
-#define TMDR    _SFR_IO8(0x28)
-
-#define AESDR   _SFR_IO8(0x29)
-
-#define AESKR   _SFR_IO8(0x2A)
-#define AESKR0  0
-#define AESKR1  1
-#define AESKR2  2
-#define AESKR3  3
-#define AESKR4  4
-#define AESKR5  5
-#define AESKR6  6
-#define AESKR7  7
-
-#define VMCR    _SFR_IO8(0x2B)
-#define VMLS0   0
-#define VMLS1   1
-#define VMLS2   2
-#define VMLS3   3
-#define VMIM    4
-#define VMPS    5
-#define BODPD   6
-#define BODLS   7
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-#define LFCR0   _SFR_IO8(0x2F)
-#define LFCE1   0
-#define LFCE2   1
-#define LFCE3   2
-#define LFBRS   3
-#define LFRBS   4
-#define LFMG    5
-#define LFVC0   6
-#define LFVC1   7
-
-#define LFCR1   _SFR_IO8(0x30)
-#define LFM0    0
-#define LFM1    1
-#define LFFM0   2
-#define LFFM1   3
-#define LFRMS   4
-#define LFRMSA  5
-#define LFQCE   6
-#define LFRE    7
-
-/* Reserved [0x31] */
-
-#define LFRDB   _SFR_IO8(0x32)
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define TPRF    5
-
-#define MCUCR   _SFR_IO8(0x35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-
-#define LFSR    _SFR_IO8(0x36)
-#define LFES    0
-#define LFSD    1
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define SIGRD   5
-#define RWWSB   6
-#define SPMIE   7
-
-#define T1CR    _SFR_IO8(0x38)
-#define T1PS0   0
-#define T1PS1   1
-#define T1IE    2
-#define T1CS0   3
-#define T1CS1   4
-#define T1E     7
-
-#define T0CR    _SFR_IO8(0x39)
-#define T0PS0   0
-#define T0PS1   1
-#define T0PS2   2
-#define T0IE    3
-#define T0PR    4
-
-/* Reserved [0x3A] */
-
-#define CMIMR   _SFR_IO8(0x3B)
-#define ECIE    0
-#define SXIE    1
-#define RTCIE   2
-
-#define CLKPR   _SFR_IO8(0x3C)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLTPS0  3
-#define CLTPS1  4
-#define CLTPS2  5
-#define CLKPCE  7
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDPS0   0
-#define WDPS1   1
-#define WDPS2   2
-#define WDE     3
-#define WDCE    4
-
-/* Reserved [0x61..0x62] */
-
-#define PRR0    _SFR_MEM8(0x63)
-#define PRLFR   0
-#define PRT1    1
-#define PRT2    2
-#define PRT3    3
-#define PRTM    4
-#define PRCU    5
-#define PRDS    6
-#define PRVM    7
-
-#define __AVR_HAVE_PRR0	((1<<PRLFR)|(1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRTM)|(1<<PRCU)|(1<<PRDS)|(1<<PRVM))
-#define __AVR_HAVE_PRR0_PRLFR
-#define __AVR_HAVE_PRR0_PRT1
-#define __AVR_HAVE_PRR0_PRT2
-#define __AVR_HAVE_PRR0_PRT3
-#define __AVR_HAVE_PRR0_PRTM
-#define __AVR_HAVE_PRR0_PRCU
-#define __AVR_HAVE_PRR0_PRDS
-#define __AVR_HAVE_PRR0_PRVM
-
-#define PRR1    _SFR_MEM8(0x64)
-#define PRCI    0
-#define PRSPI   1
-
-#define __AVR_HAVE_PRR1	((1<<PRCI)|(1<<PRSPI))
-#define __AVR_HAVE_PRR1_PRCI
-#define __AVR_HAVE_PRR1_PRSPI
-
-#define SRCCAL  _SFR_MEM8(0x65)
-
-#define FRCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-#define PCMSK0  _SFR_MEM8(0x6A)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6B)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6C] */
-
-#define LDCR    _SFR_MEM8(0x6D)
-#define LDE     0
-#define LDCS0   1
-#define LDCS1   2
-
-/* Reserved [0x6E..0x6F] */
-
-#define T2CNT   _SFR_MEM8(0x70)
-
-#define T2COR   _SFR_MEM8(0x71)
-
-/* Reserved [0x72] */
-
-#define T2MR    _SFR_MEM8(0x73)
-#define T2CS0   0
-#define T2CS1   1
-#define T2CS2   2
-#define T2PS0   3
-#define T2PS1   4
-#define T2PS2   5
-#define T2D0    6
-#define T2D1    7
-
-#define T2IMR   _SFR_MEM8(0x74)
-#define T2OIM   0
-#define T2CIM   1
-
-#define T3CO2R  _SFR_MEM8(0x75)
-
-#define T3CNT   _SFR_MEM8(0x76)
-
-#define T3COR   _SFR_MEM8(0x77)
-
-#define T3ICR   _SFR_MEM8(0x78)
-
-#define T3MRA   _SFR_MEM8(0x79)
-#define T3CS0   0
-#define T3CS1   1
-#define T3SCE   2
-#define T3CE0   3
-#define T3CE1   4
-#define T3CNC   5
-#define T3ICS0  6
-#define T3ICS1  7
-
-#define T3MRB   _SFR_MEM8(0x7A)
-#define T3PS0   0
-#define T3PS1   1
-#define T3PS2   2
-
-#define T3IMR   _SFR_MEM8(0x7B)
-#define T3OIM   0
-#define T3CIM   1
-#define T3CPIM  2
-#define T3C2IM  3
-
-/* Reserved [0x7C] */
-
-#define TMCR    _SFR_MEM8(0x7D)
-#define MI1S0   0
-#define MI1S1   1
-#define MI2S0   2
-#define MI2S1   3
-#define MI4S0   4
-#define MI4S1   5
-#define TMCPOL  6
-#define TMSSIE  7
-
-#define TMMR    _SFR_MEM8(0x7E)
-#define MOS0    0
-#define MOS1    1
-#define MSCS0   2
-#define MSCS1   3
-#define MOUTC   4
-#define TMMS0   5
-#define TMMS1   6
-#define TM12S   7
-
-#define TMIMR   _SFR_MEM8(0x7F)
-#define TMRXIM  0
-#define TMTXIM  1
-#define TMTCIM  2
-
-/* Reserved [0x80..0x81] */
-
-#define LFIMR   _SFR_MEM8(0x82)
-#define LFID0IM 0
-#define LFID1IM 1
-#define LFFEIM  2
-#define LFDBIM  3
-#define LFRSIM  4
-#define LFSDIM  5
-#define LFMDIM  6
-
-#define LFCAD   _SFR_MEM8(0x83)
-
-#define LFID00  _SFR_MEM8(0x84)
-
-#define LFID01  _SFR_MEM8(0x85)
-
-#define LFID02  _SFR_MEM8(0x86)
-
-#define LFID03  _SFR_MEM8(0x87)
-
-#define LFID10  _SFR_MEM8(0x88)
-
-#define LFID11  _SFR_MEM8(0x89)
-
-#define LFID12  _SFR_MEM8(0x8A)
-
-#define LFID13  _SFR_MEM8(0x8B)
-
-#define LFRD0   _SFR_MEM8(0x8C)
-
-#define LFRD1   _SFR_MEM8(0x8D)
-
-#define LFRD2   _SFR_MEM8(0x8E)
-
-#define LFRD3   _SFR_MEM8(0x8F)
-
-#define LFID0M  _SFR_MEM8(0x90)
-#define ID0FS0  0
-#define ID0FS1  1
-#define ID0FS2  2
-#define ID0FS3  3
-#define ID0FS4  4
-#define ID0E    7
-
-#define LFID1M  _SFR_MEM8(0x91)
-#define ID1FS0  0
-#define ID1FS1  1
-#define ID1FS2  2
-#define ID1FS3  3
-#define ID1FS4  4
-#define ID1E    7
-
-#define LFRDF   _SFR_MEM8(0x92)
-#define RDFS0   0
-#define RDFS1   1
-#define RDFS2   2
-#define RDFS3   3
-#define RDFS4   4
-#define RDFE    7
-
-#define LFRSD1  _SFR_MEM8(0x93)
-
-#define LFRSD2  _SFR_MEM8(0x94)
-
-#define LFRSD3  _SFR_MEM8(0x95)
-
-#define LFCC1   _SFR_MEM8(0x96)
-
-#define LFCC2   _SFR_MEM8(0x97)
-
-#define LFCC3   _SFR_MEM8(0x98)
-
-#define LFQCR   _SFR_MEM8(0x99)
-#define LFQCLL  0
-
-/* Reserved [0x9A..0x9B] */
-
-#define TPIMR   _SFR_MEM8(0x9C)
-#define TPIM    0
-
-/* Reserved [0x9D] */
-
-#define RTCCR   _SFR_MEM8(0x9E)
-#define RTCR    0
-
-#define RTCDR   _SFR_MEM8(0x9F)
-
-/* Reserved [0xA0..0xA7] */
-
-#define TMMDR   _SFR_MEM8(0xA8)
-
-#define TMBDR   _SFR_MEM8(0xA9)
-
-#define TMTDR   _SFR_MEM8(0xAA)
-
-#define TMSR    _SFR_MEM8(0xAB)
-
-#define CRCPOL  _SFR_MEM8(0xAC)
-
-#define CRCDR   _SFR_MEM8(0xAD)
-
-#define CRCCR   _SFR_MEM8(0xAE)
-#define CRCN0   0
-#define CRCN1   1
-#define CRCN2   2
-#define CRCSEL  3
-#define REFLI   4
-#define REFLO   5
-#define STVAL   6
-#define CRCRS   7
-
-#define CRCSR   _SFR_MEM8(0xAF)
-#define CRCBF   0
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* Transponder Mode Interrupt */
-#define TPINT_vect            _VECTOR(1)
-#define TPINT_vect_num        1
-
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(2)
-#define INT0_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(3)
-#define PCINT0_vect_num        3
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect            _VECTOR(4)
-#define PCINT1_vect_num        4
-
-/* Voltage Monitoring Interrupt */
-#define VMINT_vect            _VECTOR(5)
-#define VMINT_vect_num        5
-
-/* Timer0 Interval Interrupt */
-#define T0INT_vect            _VECTOR(6)
-#define T0INT_vect_num        6
-
-/* LF-Receiver Identifier 0 Interrupt */
-#define LFID0INT_vect            _VECTOR(7)
-#define LFID0INT_vect_num        7
-
-/* LF-Receiver Identifier 1 Interrupt */
-#define LFID1INT_vect            _VECTOR(8)
-#define LFID1INT_vect_num        8
-
-/* LF-Receiver Frame End Interrupt */
-#define LFFEINT_vect            _VECTOR(9)
-#define LFFEINT_vect_num        9
-
-/* LF-Receiver Data Buffer full Interrupt */
-#define LFDBINT_vect            _VECTOR(10)
-#define LFDBINT_vect_num        10
-
-/* Timer/Counter3 Capture Event Interrupt */
-#define T3CAPINT_vect            _VECTOR(11)
-#define T3CAPINT_vect_num        11
-
-/* Timer/Counter3 Compare Match Interrupt */
-#define T3COMINT_vect            _VECTOR(12)
-#define T3COMINT_vect_num        12
-
-/* Timer/Counter3 Overflow Interrupt */
-#define T3OVFINT_vect            _VECTOR(13)
-#define T3OVFINT_vect_num        13
-
-/* Timer/Counter3 Compare Match 2 Interrupt */
-#define T3COM2INT_vect            _VECTOR(14)
-#define T3COM2INT_vect_num        14
-
-/* Timer/Counter2 Compare Match Interrupt */
-#define T2COMINT_vect            _VECTOR(15)
-#define T2COMINT_vect_num        15
-
-/* Timer/Counter2 Overflow Interrupt */
-#define T2OVFINT_vect            _VECTOR(16)
-#define T2OVFINT_vect_num        16
-
-/* Timer 1 Interval Interrupt */
-#define T1INT_vect            _VECTOR(17)
-#define T1INT_vect_num        17
-
-/* SPI Serial Transfer Complete Interrupt */
-#define SPISTC_vect            _VECTOR(18)
-#define SPISTC_vect_num        18
-
-/* Timer Modulator SSI Receive Buffer Interrupt */
-#define TMRXBINT_vect            _VECTOR(19)
-#define TMRXBINT_vect_num        19
-
-/* Timer Modulator SSI Transmit Buffer Interrupt */
-#define TMTXBINT_vect            _VECTOR(20)
-#define TMTXBINT_vect_num        20
-
-/* Timer Modulator Transmit Complete Interrupt */
-#define TMTXCINT_vect            _VECTOR(21)
-#define TMTXCINT_vect_num        21
-
-/* AES Interrupt */
-#define AESINT_vect            _VECTOR(22)
-#define AESINT_vect_num        22
-
-/* LF-Receiver RSSi measurement Interrupt */
-#define LFRSSINT_vect            _VECTOR(23)
-#define LFRSSINT_vect_num        23
-
-/* LF-Receiver Signal Detect Interrupt */
-#define LFSDINT_vect            _VECTOR(24)
-#define LFSDINT_vect_num        24
-
-/* LF-Receiver Manchester Decoder error Interrupt  */
-#define LFMDINT_vect            _VECTOR(25)
-#define LFMDINT_vect_num        25
-
-/* External Input Clock Monitoring Interrupt */
-#define EXCMINT_vect            _VECTOR(26)
-#define EXCMINT_vect_num        26
-
-/* External XTAL Oscillator Break Down Interrupt */
-#define EXXMINT_vect            _VECTOR(27)
-#define EXXMINT_vect_num        27
-
-/* Real Time Clock Interrupt */
-#define RTCINT_vect            _VECTOR(28)
-#define RTCINT_vect_num        28
-
-/* EEPROM Ready Interrupt */
-#define EEREADY_vect            _VECTOR(29)
-#define EEREADY_vect_num        29
-
-/* Store Program Memory Ready  */
-#define SPMREADY_vect            _VECTOR(30)
-#define SPMREADY_vect_num        30
-
-#define _VECTORS_SIZE 124
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      2048
-#define E2PAGESIZE  16
-#define E2END       0x07FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Fuse Byte */
-#define FUSE__32OEN      (unsigned char)~_BV(1)
-#define FUSE_Reserved    (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x62
-
-
-#endif /* #ifdef _AVR_ATA5790N_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5790N_H_INCLUDED
+#define _AVR_ATA5790N_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5790n.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define T3CR2   _SFR_IO8(0x0C)
+#define T3GRES  0
+#define T3C2TM  1
+#define T3C2RM  2
+
+#define TPCR    _SFR_IO8(0x0D)
+#define TPMA    0
+#define TPMOD   1
+#define TPMS0   2
+#define TPMS1   3
+#define TPMD0   4
+#define TPMD1   5
+#define TPPSD   6
+#define TPD     7
+
+#define TPFR    _SFR_IO8(0x0E)
+#define TPF     0
+#define TPA     1
+#define TPGAP   2
+#define TPPSW   3
+
+#define CMCR    _SFR_IO8(0x0F)
+#define CMM0    0
+#define CMM1    1
+#define SRCD    2
+#define CO32D   3
+#define CCS     4
+#define ECINS   5
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMSR    _SFR_IO8(0x10)
+#define ECF     0
+#define SXF     1
+#define RTCF    2
+
+#define T2CR    _SFR_IO8(0x11)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2GRM   3
+#define T2TOP   4
+#define T2RES   5
+#define T2TS    6
+#define T2E     7
+
+#define T3CR    _SFR_IO8(0x12)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3CPTM  6
+#define T3E     7
+
+#define AESCR   _SFR_IO8(0x13)
+#define AESWK   0
+#define AESWD   1
+#define AESIM   2
+#define AESD    3
+#define AESXOR  4
+#define AESRES  5
+#define AESE    7
+
+#define AESSR   _SFR_IO8(0x14)
+#define AESRF   0
+#define AESERF  7
+
+#define TMIFR   _SFR_IO8(0x15)
+#define TMRXF   0
+#define TMTXF   1
+#define TMTCF   2
+#define TMRXS   3
+#define TMTXS   4
+
+#define VMSR    _SFR_IO8(0x16)
+#define VMF     0
+
+#define PCIFR   _SFR_IO8(0x17)
+#define PCIF0   0
+#define PCIF1   1
+
+#define LFFR    _SFR_IO8(0x18)
+#define LFID0F  0
+#define LFID1F  1
+#define LFFEF   2
+#define LFDBF   3
+#define LFRSF   4
+#define LFSDF   5
+#define LFMDF   6
+#define LFCAF   7
+
+#define T0IFR   _SFR_IO8(0x19)
+#define T0F     0
+
+#define T1IFR   _SFR_IO8(0x1A)
+#define T1F     0
+
+#define T2IFR   _SFR_IO8(0x1B)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x1C)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+#define T3CO2F  3
+
+#define EIFR    _SFR_IO8(0x1D)
+#define INTF0   0
+
+#define GPIOR   _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EELP    6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define EECCR   _SFR_IO8(0x24)
+#define EEL0    0
+#define EEL1    1
+#define EEL2    2
+#define EEL3    3
+
+#define EECR2   _SFR_IO8(0x25)
+#define EEBRE   0
+#define EEPAGE  1
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+
+#define TMDR    _SFR_IO8(0x28)
+
+#define AESDR   _SFR_IO8(0x29)
+
+#define AESKR   _SFR_IO8(0x2A)
+#define AESKR0  0
+#define AESKR1  1
+#define AESKR2  2
+#define AESKR3  3
+#define AESKR4  4
+#define AESKR5  5
+#define AESKR6  6
+#define AESKR7  7
+
+#define VMCR    _SFR_IO8(0x2B)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMPS    5
+#define BODPD   6
+#define BODLS   7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define LFCR0   _SFR_IO8(0x2F)
+#define LFCE1   0
+#define LFCE2   1
+#define LFCE3   2
+#define LFBRS   3
+#define LFRBS   4
+#define LFMG    5
+#define LFVC0   6
+#define LFVC1   7
+
+#define LFCR1   _SFR_IO8(0x30)
+#define LFM0    0
+#define LFM1    1
+#define LFFM0   2
+#define LFFM1   3
+#define LFRMS   4
+#define LFRMSA  5
+#define LFQCE   6
+#define LFRE    7
+
+/* Reserved [0x31] */
+
+#define LFRDB   _SFR_IO8(0x32)
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+#define TPRF    5
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+#define LFSR    _SFR_IO8(0x36)
+#define LFES    0
+#define LFSD    1
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+#define T1CR    _SFR_IO8(0x38)
+#define T1PS0   0
+#define T1PS1   1
+#define T1IE    2
+#define T1CS0   3
+#define T1CS1   4
+#define T1E     7
+
+#define T0CR    _SFR_IO8(0x39)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+/* Reserved [0x3A] */
+
+#define CMIMR   _SFR_IO8(0x3B)
+#define ECIE    0
+#define SXIE    1
+#define RTCIE   2
+
+#define CLKPR   _SFR_IO8(0x3C)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLKPCE  7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+/* Reserved [0x61..0x62] */
+
+#define PRR0    _SFR_MEM8(0x63)
+#define PRLFR   0
+#define PRT1    1
+#define PRT2    2
+#define PRT3    3
+#define PRTM    4
+#define PRCU    5
+#define PRDS    6
+#define PRVM    7
+
+#define __AVR_HAVE_PRR0	((1<<PRLFR)|(1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRTM)|(1<<PRCU)|(1<<PRDS)|(1<<PRVM))
+#define __AVR_HAVE_PRR0_PRLFR
+#define __AVR_HAVE_PRR0_PRT1
+#define __AVR_HAVE_PRR0_PRT2
+#define __AVR_HAVE_PRR0_PRT3
+#define __AVR_HAVE_PRR0_PRTM
+#define __AVR_HAVE_PRR0_PRCU
+#define __AVR_HAVE_PRR0_PRDS
+#define __AVR_HAVE_PRR0_PRVM
+
+#define PRR1    _SFR_MEM8(0x64)
+#define PRCI    0
+#define PRSPI   1
+
+#define __AVR_HAVE_PRR1	((1<<PRCI)|(1<<PRSPI))
+#define __AVR_HAVE_PRR1_PRCI
+#define __AVR_HAVE_PRR1_PRSPI
+
+#define SRCCAL  _SFR_MEM8(0x65)
+
+#define FRCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67..0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+
+#define PCMSK0  _SFR_MEM8(0x6A)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6B)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6C] */
+
+#define LDCR    _SFR_MEM8(0x6D)
+#define LDE     0
+#define LDCS0   1
+#define LDCS1   2
+
+/* Reserved [0x6E..0x6F] */
+
+#define T2CNT   _SFR_MEM8(0x70)
+
+#define T2COR   _SFR_MEM8(0x71)
+
+/* Reserved [0x72] */
+
+#define T2MR    _SFR_MEM8(0x73)
+#define T2CS0   0
+#define T2CS1   1
+#define T2CS2   2
+#define T2PS0   3
+#define T2PS1   4
+#define T2PS2   5
+#define T2D0    6
+#define T2D1    7
+
+#define T2IMR   _SFR_MEM8(0x74)
+#define T2OIM   0
+#define T2CIM   1
+
+#define T3CO2R  _SFR_MEM8(0x75)
+
+#define T3CNT   _SFR_MEM8(0x76)
+
+#define T3COR   _SFR_MEM8(0x77)
+
+#define T3ICR   _SFR_MEM8(0x78)
+
+#define T3MRA   _SFR_MEM8(0x79)
+#define T3CS0   0
+#define T3CS1   1
+#define T3SCE   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3CNC   5
+#define T3ICS0  6
+#define T3ICS1  7
+
+#define T3MRB   _SFR_MEM8(0x7A)
+#define T3PS0   0
+#define T3PS1   1
+#define T3PS2   2
+
+#define T3IMR   _SFR_MEM8(0x7B)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+#define T3C2IM  3
+
+/* Reserved [0x7C] */
+
+#define TMCR    _SFR_MEM8(0x7D)
+#define MI1S0   0
+#define MI1S1   1
+#define MI2S0   2
+#define MI2S1   3
+#define MI4S0   4
+#define MI4S1   5
+#define TMCPOL  6
+#define TMSSIE  7
+
+#define TMMR    _SFR_MEM8(0x7E)
+#define MOS0    0
+#define MOS1    1
+#define MSCS0   2
+#define MSCS1   3
+#define MOUTC   4
+#define TMMS0   5
+#define TMMS1   6
+#define TM12S   7
+
+#define TMIMR   _SFR_MEM8(0x7F)
+#define TMRXIM  0
+#define TMTXIM  1
+#define TMTCIM  2
+
+/* Reserved [0x80..0x81] */
+
+#define LFIMR   _SFR_MEM8(0x82)
+#define LFID0IM 0
+#define LFID1IM 1
+#define LFFEIM  2
+#define LFDBIM  3
+#define LFRSIM  4
+#define LFSDIM  5
+#define LFMDIM  6
+
+#define LFCAD   _SFR_MEM8(0x83)
+
+#define LFID00  _SFR_MEM8(0x84)
+
+#define LFID01  _SFR_MEM8(0x85)
+
+#define LFID02  _SFR_MEM8(0x86)
+
+#define LFID03  _SFR_MEM8(0x87)
+
+#define LFID10  _SFR_MEM8(0x88)
+
+#define LFID11  _SFR_MEM8(0x89)
+
+#define LFID12  _SFR_MEM8(0x8A)
+
+#define LFID13  _SFR_MEM8(0x8B)
+
+#define LFRD0   _SFR_MEM8(0x8C)
+
+#define LFRD1   _SFR_MEM8(0x8D)
+
+#define LFRD2   _SFR_MEM8(0x8E)
+
+#define LFRD3   _SFR_MEM8(0x8F)
+
+#define LFID0M  _SFR_MEM8(0x90)
+#define ID0FS0  0
+#define ID0FS1  1
+#define ID0FS2  2
+#define ID0FS3  3
+#define ID0FS4  4
+#define ID0E    7
+
+#define LFID1M  _SFR_MEM8(0x91)
+#define ID1FS0  0
+#define ID1FS1  1
+#define ID1FS2  2
+#define ID1FS3  3
+#define ID1FS4  4
+#define ID1E    7
+
+#define LFRDF   _SFR_MEM8(0x92)
+#define RDFS0   0
+#define RDFS1   1
+#define RDFS2   2
+#define RDFS3   3
+#define RDFS4   4
+#define RDFE    7
+
+#define LFRSD1  _SFR_MEM8(0x93)
+
+#define LFRSD2  _SFR_MEM8(0x94)
+
+#define LFRSD3  _SFR_MEM8(0x95)
+
+#define LFCC1   _SFR_MEM8(0x96)
+
+#define LFCC2   _SFR_MEM8(0x97)
+
+#define LFCC3   _SFR_MEM8(0x98)
+
+#define LFQCR   _SFR_MEM8(0x99)
+#define LFQCLL  0
+
+/* Reserved [0x9A..0x9B] */
+
+#define TPIMR   _SFR_MEM8(0x9C)
+#define TPIM    0
+
+/* Reserved [0x9D] */
+
+#define RTCCR   _SFR_MEM8(0x9E)
+#define RTCR    0
+
+#define RTCDR   _SFR_MEM8(0x9F)
+
+/* Reserved [0xA0..0xA7] */
+
+#define TMMDR   _SFR_MEM8(0xA8)
+
+#define TMBDR   _SFR_MEM8(0xA9)
+
+#define TMTDR   _SFR_MEM8(0xAA)
+
+#define TMSR    _SFR_MEM8(0xAB)
+
+#define CRCPOL  _SFR_MEM8(0xAC)
+
+#define CRCDR   _SFR_MEM8(0xAD)
+
+#define CRCCR   _SFR_MEM8(0xAE)
+#define CRCN0   0
+#define CRCN1   1
+#define CRCN2   2
+#define CRCSEL  3
+#define REFLI   4
+#define REFLO   5
+#define STVAL   6
+#define CRCRS   7
+
+#define CRCSR   _SFR_MEM8(0xAF)
+#define CRCBF   0
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* Transponder Mode Interrupt */
+#define TPINT_vect            _VECTOR(1)
+#define TPINT_vect_num        1
+
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(2)
+#define INT0_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMINT_vect            _VECTOR(5)
+#define VMINT_vect_num        5
+
+/* Timer0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(6)
+#define T0INT_vect_num        6
+
+/* LF-Receiver Identifier 0 Interrupt */
+#define LFID0INT_vect            _VECTOR(7)
+#define LFID0INT_vect_num        7
+
+/* LF-Receiver Identifier 1 Interrupt */
+#define LFID1INT_vect            _VECTOR(8)
+#define LFID1INT_vect_num        8
+
+/* LF-Receiver Frame End Interrupt */
+#define LFFEINT_vect            _VECTOR(9)
+#define LFFEINT_vect_num        9
+
+/* LF-Receiver Data Buffer full Interrupt */
+#define LFDBINT_vect            _VECTOR(10)
+#define LFDBINT_vect_num        10
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAPINT_vect            _VECTOR(11)
+#define T3CAPINT_vect_num        11
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMINT_vect            _VECTOR(12)
+#define T3COMINT_vect_num        12
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVFINT_vect            _VECTOR(13)
+#define T3OVFINT_vect_num        13
+
+/* Timer/Counter3 Compare Match 2 Interrupt */
+#define T3COM2INT_vect            _VECTOR(14)
+#define T3COM2INT_vect_num        14
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMINT_vect            _VECTOR(15)
+#define T2COMINT_vect_num        15
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVFINT_vect            _VECTOR(16)
+#define T2OVFINT_vect_num        16
+
+/* Timer 1 Interval Interrupt */
+#define T1INT_vect            _VECTOR(17)
+#define T1INT_vect_num        17
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPISTC_vect            _VECTOR(18)
+#define SPISTC_vect_num        18
+
+/* Timer Modulator SSI Receive Buffer Interrupt */
+#define TMRXBINT_vect            _VECTOR(19)
+#define TMRXBINT_vect_num        19
+
+/* Timer Modulator SSI Transmit Buffer Interrupt */
+#define TMTXBINT_vect            _VECTOR(20)
+#define TMTXBINT_vect_num        20
+
+/* Timer Modulator Transmit Complete Interrupt */
+#define TMTXCINT_vect            _VECTOR(21)
+#define TMTXCINT_vect_num        21
+
+/* AES Interrupt */
+#define AESINT_vect            _VECTOR(22)
+#define AESINT_vect_num        22
+
+/* LF-Receiver RSSi measurement Interrupt */
+#define LFRSSINT_vect            _VECTOR(23)
+#define LFRSSINT_vect_num        23
+
+/* LF-Receiver Signal Detect Interrupt */
+#define LFSDINT_vect            _VECTOR(24)
+#define LFSDINT_vect_num        24
+
+/* LF-Receiver Manchester Decoder error Interrupt  */
+#define LFMDINT_vect            _VECTOR(25)
+#define LFMDINT_vect_num        25
+
+/* External Input Clock Monitoring Interrupt */
+#define EXCMINT_vect            _VECTOR(26)
+#define EXCMINT_vect_num        26
+
+/* External XTAL Oscillator Break Down Interrupt */
+#define EXXMINT_vect            _VECTOR(27)
+#define EXXMINT_vect_num        27
+
+/* Real Time Clock Interrupt */
+#define RTCINT_vect            _VECTOR(28)
+#define RTCINT_vect_num        28
+
+/* EEPROM Ready Interrupt */
+#define EEREADY_vect            _VECTOR(29)
+#define EEREADY_vect_num        29
+
+/* Store Program Memory Ready  */
+#define SPMREADY_vect            _VECTOR(30)
+#define SPMREADY_vect_num        30
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 124
+#else
+#  define _VECTORS_SIZE 124U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      2048
+#  define E2PAGESIZE  16
+#  define E2END       0x07FF
+#else
+#  define E2START     0U
+#  define E2SIZE      2048U
+#  define E2PAGESIZE  16U
+#  define E2END       0x07FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE__32OEN      (unsigned char)~_BV(1)
+#define FUSE_Reserved    (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x62
+
+
+
+
+#endif /* #ifdef _AVR_ATA5790N_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa5791.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa5791.h
@@ -0,0 +1,933 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5791_H_INCLUDED
+#define _AVR_ATA5791_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5791.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define T3CR2   _SFR_IO8(0x0C)
+#define T3GRES  0
+#define T3C2TM  1
+#define T3C2RM  2
+
+#define TPCR    _SFR_IO8(0x0D)
+#define TPMA    0
+#define TPMOD   1
+#define TPMS0   2
+#define TPMS1   3
+#define TPMD0   4
+#define TPMD1   5
+#define TPPSD   6
+#define TPD     7
+
+#define TPFR    _SFR_IO8(0x0E)
+#define TPF     0
+#define TPA     1
+#define TPGAP   2
+#define TPPSW   3
+
+#define CMCR    _SFR_IO8(0x0F)
+#define CMM0    0
+#define CMM1    1
+#define SRCD    2
+#define CO32D   3
+#define CCS     4
+#define ECINS   5
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMSR    _SFR_IO8(0x10)
+#define ECF     0
+#define SXF     1
+#define RTCF    2
+
+#define T2CR    _SFR_IO8(0x11)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2GRM   3
+#define T2TOP   4
+#define T2RES   5
+#define T2TS    6
+#define T2E     7
+
+#define T3CR    _SFR_IO8(0x12)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3CPTM  6
+#define T3E     7
+
+#define AESCR   _SFR_IO8(0x13)
+#define AESWK   0
+#define AESWD   1
+#define AESIM   2
+#define AESD    3
+#define AESXOR  4
+#define AESRES  5
+#define AESE    7
+
+#define AESSR   _SFR_IO8(0x14)
+#define AESRF   0
+#define AESERF  7
+
+#define TMIFR   _SFR_IO8(0x15)
+#define TMRXF   0
+#define TMTXF   1
+#define TMTCF   2
+#define TMRXS   3
+#define TMTXS   4
+
+#define VMSR    _SFR_IO8(0x16)
+#define VMF     0
+
+#define PCIFR   _SFR_IO8(0x17)
+#define PCIF0   0
+#define PCIF1   1
+
+#define LFFR    _SFR_IO8(0x18)
+#define LFID0F  0
+#define LFID1F  1
+#define LFFEF   2
+#define LFDBF   3
+#define LFRSF   4
+#define LFSDF   5
+#define LFMDF   6
+#define LFCAF   7
+
+#define T0IFR   _SFR_IO8(0x19)
+#define T0F     0
+
+#define T1IFR   _SFR_IO8(0x1A)
+#define T1F     0
+
+#define T2IFR   _SFR_IO8(0x1B)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x1C)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+#define T3CO2F  3
+
+#define EIFR    _SFR_IO8(0x1D)
+#define INTF0   0
+
+#define GPIOR   _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EELP    6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define EECCR   _SFR_IO8(0x24)
+#define EEL0    0
+#define EEL1    1
+#define EEL2    2
+#define EEL3    3
+
+#define EECR2   _SFR_IO8(0x25)
+#define EEBRE   0
+#define EEPAGE  1
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+
+#define TMDR    _SFR_IO8(0x28)
+
+#define AESDR   _SFR_IO8(0x29)
+
+#define AESKR   _SFR_IO8(0x2A)
+#define AESKR0  0
+#define AESKR1  1
+#define AESKR2  2
+#define AESKR3  3
+#define AESKR4  4
+#define AESKR5  5
+#define AESKR6  6
+#define AESKR7  7
+
+#define VMCR    _SFR_IO8(0x2B)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMPS    5
+#define BODPD   6
+#define BODLS   7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define LFCR0   _SFR_IO8(0x2F)
+#define LFCE1   0
+#define LFCE2   1
+#define LFCE3   2
+#define LFBRS   3
+#define LFRBS   4
+#define LFMG    5
+#define LFVC0   6
+#define LFVC1   7
+
+#define LFCR1   _SFR_IO8(0x30)
+#define LFM0    0
+#define LFM1    1
+#define LFFM0   2
+#define LFFM1   3
+#define LFRMS   4
+#define LFRMSA  5
+#define LFQCE   6
+#define LFRE    7
+
+/* Reserved [0x31] */
+
+#define LFRDB   _SFR_IO8(0x32)
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+#define TPRF    5
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+#define LFSR    _SFR_IO8(0x36)
+#define LFES    0
+#define LFSD    1
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+#define T1CR    _SFR_IO8(0x38)
+#define T1PS0   0
+#define T1PS1   1
+#define T1IE    2
+#define T1CS0   3
+#define T1CS1   4
+#define T1E     7
+
+#define T0CR    _SFR_IO8(0x39)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+/* Reserved [0x3A] */
+
+#define CMIMR   _SFR_IO8(0x3B)
+#define ECIE    0
+#define SXIE    1
+#define RTCIE   2
+
+#define CLKPR   _SFR_IO8(0x3C)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLKPCE  7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+/* Reserved [0x61..0x62] */
+
+#define PRR0    _SFR_MEM8(0x63)
+#define PRLFR   0
+#define PRT1    1
+#define PRT2    2
+#define PRT3    3
+#define PRTM    4
+#define PRCU    5
+#define PRDS    6
+#define PRVM    7
+
+#define __AVR_HAVE_PRR0	((1<<PRLFR)|(1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRTM)|(1<<PRCU)|(1<<PRDS)|(1<<PRVM))
+#define __AVR_HAVE_PRR0_PRLFR
+#define __AVR_HAVE_PRR0_PRT1
+#define __AVR_HAVE_PRR0_PRT2
+#define __AVR_HAVE_PRR0_PRT3
+#define __AVR_HAVE_PRR0_PRTM
+#define __AVR_HAVE_PRR0_PRCU
+#define __AVR_HAVE_PRR0_PRDS
+#define __AVR_HAVE_PRR0_PRVM
+
+#define PRR1    _SFR_MEM8(0x64)
+#define PRCI    0
+#define PRSPI   1
+
+#define __AVR_HAVE_PRR1	((1<<PRCI)|(1<<PRSPI))
+#define __AVR_HAVE_PRR1_PRCI
+#define __AVR_HAVE_PRR1_PRSPI
+
+#define SRCCAL  _SFR_MEM8(0x65)
+
+#define FRCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67..0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+
+#define PCMSK0  _SFR_MEM8(0x6A)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6B)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6C] */
+
+#define LDCR    _SFR_MEM8(0x6D)
+#define LDE     0
+#define LDCS0   1
+#define LDCS1   2
+
+/* Reserved [0x6E..0x6F] */
+
+#define T2CNT   _SFR_MEM8(0x70)
+
+#define T2COR   _SFR_MEM8(0x71)
+
+/* Reserved [0x72] */
+
+#define T2MR    _SFR_MEM8(0x73)
+#define T2CS0   0
+#define T2CS1   1
+#define T2CS2   2
+#define T2PS0   3
+#define T2PS1   4
+#define T2PS2   5
+#define T2D0    6
+#define T2D1    7
+
+#define T2IMR   _SFR_MEM8(0x74)
+#define T2OIM   0
+#define T2CIM   1
+
+#define T3CO2R  _SFR_MEM8(0x75)
+
+#define T3CNT   _SFR_MEM8(0x76)
+
+#define T3COR   _SFR_MEM8(0x77)
+
+#define T3ICR   _SFR_MEM8(0x78)
+
+#define T3MRA   _SFR_MEM8(0x79)
+#define T3CS0   0
+#define T3CS1   1
+#define T3SCE   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3CNC   5
+#define T3ICS0  6
+#define T3ICS1  7
+
+#define T3MRB   _SFR_MEM8(0x7A)
+#define T3PS0   0
+#define T3PS1   1
+#define T3PS2   2
+
+#define T3IMR   _SFR_MEM8(0x7B)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+#define T3C2IM  3
+
+/* Reserved [0x7C] */
+
+#define TMCR    _SFR_MEM8(0x7D)
+#define MI1S0   0
+#define MI1S1   1
+#define MI2S0   2
+#define MI2S1   3
+#define MI4S0   4
+#define MI4S1   5
+#define TMCPOL  6
+#define TMSSIE  7
+
+#define TMMR    _SFR_MEM8(0x7E)
+#define MOS0    0
+#define MOS1    1
+#define MSCS0   2
+#define MSCS1   3
+#define MOUTC   4
+#define TMMS0   5
+#define TMMS1   6
+#define TM12S   7
+
+#define TMIMR   _SFR_MEM8(0x7F)
+#define TMRXIM  0
+#define TMTXIM  1
+#define TMTCIM  2
+
+/* Reserved [0x80..0x81] */
+
+#define LFIMR   _SFR_MEM8(0x82)
+#define LFID0IM 0
+#define LFID1IM 1
+#define LFFEIM  2
+#define LFDBIM  3
+#define LFRSIM  4
+#define LFSDIM  5
+#define LFMDIM  6
+
+#define LFCAD   _SFR_MEM8(0x83)
+
+#define LFID00  _SFR_MEM8(0x84)
+
+#define LFID01  _SFR_MEM8(0x85)
+
+#define LFID02  _SFR_MEM8(0x86)
+
+#define LFID03  _SFR_MEM8(0x87)
+
+#define LFID10  _SFR_MEM8(0x88)
+
+#define LFID11  _SFR_MEM8(0x89)
+
+#define LFID12  _SFR_MEM8(0x8A)
+
+#define LFID13  _SFR_MEM8(0x8B)
+
+#define LFRD0   _SFR_MEM8(0x8C)
+
+#define LFRD1   _SFR_MEM8(0x8D)
+
+#define LFRD2   _SFR_MEM8(0x8E)
+
+#define LFRD3   _SFR_MEM8(0x8F)
+
+#define LFID0M  _SFR_MEM8(0x90)
+#define ID0FS0  0
+#define ID0FS1  1
+#define ID0FS2  2
+#define ID0FS3  3
+#define ID0FS4  4
+#define ID0E    7
+
+#define LFID1M  _SFR_MEM8(0x91)
+#define ID1FS0  0
+#define ID1FS1  1
+#define ID1FS2  2
+#define ID1FS3  3
+#define ID1FS4  4
+#define ID1E    7
+
+#define LFRDF   _SFR_MEM8(0x92)
+#define RDFS0   0
+#define RDFS1   1
+#define RDFS2   2
+#define RDFS3   3
+#define RDFS4   4
+#define RDFE    7
+
+#define LFRSD1  _SFR_MEM8(0x93)
+
+#define LFRSD2  _SFR_MEM8(0x94)
+
+#define LFRSD3  _SFR_MEM8(0x95)
+
+#define LFCC1   _SFR_MEM8(0x96)
+
+#define LFCC2   _SFR_MEM8(0x97)
+
+#define LFCC3   _SFR_MEM8(0x98)
+
+#define LFQCR   _SFR_MEM8(0x99)
+#define LFQCLL  0
+
+/* Reserved [0x9A..0x9B] */
+
+#define TPIMR   _SFR_MEM8(0x9C)
+#define TPIM    0
+
+/* Reserved [0x9D] */
+
+#define RTCCR   _SFR_MEM8(0x9E)
+#define RTCR    0
+
+#define RTCDR   _SFR_MEM8(0x9F)
+
+/* Reserved [0xA0..0xA7] */
+
+#define TMMDR   _SFR_MEM8(0xA8)
+
+#define TMBDR   _SFR_MEM8(0xA9)
+
+#define TMTDR   _SFR_MEM8(0xAA)
+
+#define TMSR    _SFR_MEM8(0xAB)
+
+#define CRCPOL  _SFR_MEM8(0xAC)
+
+#define CRCDR   _SFR_MEM8(0xAD)
+
+#define CRCCR   _SFR_MEM8(0xAE)
+#define CRCN0   0
+#define CRCN1   1
+#define CRCN2   2
+#define CRCSEL  3
+#define REFLI   4
+#define REFLO   5
+#define STVAL   6
+#define CRCRS   7
+
+#define CRCSR   _SFR_MEM8(0xAF)
+#define CRCBF   0
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* Transponder Mode Interrupt */
+#define TPINT_vect            _VECTOR(1)
+#define TPINT_vect_num        1
+
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(2)
+#define INT0_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMINT_vect            _VECTOR(5)
+#define VMINT_vect_num        5
+
+/* Timer0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(6)
+#define T0INT_vect_num        6
+
+/* LF-Receiver Identifier 0 Interrupt */
+#define LFID0INT_vect            _VECTOR(7)
+#define LFID0INT_vect_num        7
+
+/* LF-Receiver Identifier 1 Interrupt */
+#define LFID1INT_vect            _VECTOR(8)
+#define LFID1INT_vect_num        8
+
+/* LF-Receiver Frame End Interrupt */
+#define LFFEINT_vect            _VECTOR(9)
+#define LFFEINT_vect_num        9
+
+/* LF-Receiver Data Buffer full Interrupt */
+#define LFDBINT_vect            _VECTOR(10)
+#define LFDBINT_vect_num        10
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAPINT_vect            _VECTOR(11)
+#define T3CAPINT_vect_num        11
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMINT_vect            _VECTOR(12)
+#define T3COMINT_vect_num        12
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVFINT_vect            _VECTOR(13)
+#define T3OVFINT_vect_num        13
+
+/* Timer/Counter3 Compare Match 2 Interrupt */
+#define T3COM2INT_vect            _VECTOR(14)
+#define T3COM2INT_vect_num        14
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMINT_vect            _VECTOR(15)
+#define T2COMINT_vect_num        15
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVFINT_vect            _VECTOR(16)
+#define T2OVFINT_vect_num        16
+
+/* Timer 1 Interval Interrupt */
+#define T1INT_vect            _VECTOR(17)
+#define T1INT_vect_num        17
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPISTC_vect            _VECTOR(18)
+#define SPISTC_vect_num        18
+
+/* Timer Modulator SSI Receive Buffer Interrupt */
+#define TMRXBINT_vect            _VECTOR(19)
+#define TMRXBINT_vect_num        19
+
+/* Timer Modulator SSI Transmit Buffer Interrupt */
+#define TMTXBINT_vect            _VECTOR(20)
+#define TMTXBINT_vect_num        20
+
+/* Timer Modulator Transmit Complete Interrupt */
+#define TMTXCINT_vect            _VECTOR(21)
+#define TMTXCINT_vect_num        21
+
+/* AES Interrupt */
+#define AESINT_vect            _VECTOR(22)
+#define AESINT_vect_num        22
+
+/* LF-Receiver RSSi measurement Interrupt */
+#define LFRSSINT_vect            _VECTOR(23)
+#define LFRSSINT_vect_num        23
+
+/* LF-Receiver Signal Detect Interrupt */
+#define LFSDINT_vect            _VECTOR(24)
+#define LFSDINT_vect_num        24
+
+/* LF-Receiver Manchester Decoder error Interrupt  */
+#define LFMDINT_vect            _VECTOR(25)
+#define LFMDINT_vect_num        25
+
+/* External Input Clock Monitoring Interrupt */
+#define EXCMINT_vect            _VECTOR(26)
+#define EXCMINT_vect_num        26
+
+/* External XTAL Oscillator Break Down Interrupt */
+#define EXXMINT_vect            _VECTOR(27)
+#define EXXMINT_vect_num        27
+
+/* Real Time Clock Interrupt */
+#define RTCINT_vect            _VECTOR(28)
+#define RTCINT_vect_num        28
+
+/* EEPROM Ready Interrupt */
+#define EEREADY_vect            _VECTOR(29)
+#define EEREADY_vect_num        29
+
+/* Store Program Memory Ready  */
+#define SPMREADY_vect            _VECTOR(30)
+#define SPMREADY_vect_num        30
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 124
+#else
+#  define _VECTORS_SIZE 124U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      2048
+#  define E2PAGESIZE  16
+#  define E2END       0x07FF
+#else
+#  define E2START     0U
+#  define E2SIZE      2048U
+#  define E2PAGESIZE  16U
+#  define E2END       0x07FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_EXTCLKEN    (unsigned char)~_BV(0)
+#define FUSE__32OEN      (unsigned char)~_BV(1)
+#define FUSE_Reserved    (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x62
+
+
+
+
+#endif /* #ifdef _AVR_ATA5791_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa5795.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa5795.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATA5795_H_INCLUDED
 #define _AVR_ATA5795_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -89,10 +88,20 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC4  4
@@ -113,13 +122,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -568,111 +593,142 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* Transponder Mode Interrupt */
-#define TPINT_vect            _VECTOR(2)
-#define TPINT_vect_num        2
+#define TPINT_vect            _VECTOR(1)
+#define TPINT_vect_num        1
 
 /* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(4)
-#define INT0_vect_num        4
+#define INT0_vect            _VECTOR(2)
+#define INT0_vect_num        2
 
 /* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(6)
-#define PCINT0_vect_num        6
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
 
 /* Pin Change Interrupt Request 1 */
-#define PCINT1_vect            _VECTOR(8)
-#define PCINT1_vect_num        8
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
 
 /* Voltage Monitor Interrupt */
-#define VMINT_vect            _VECTOR(10)
-#define VMINT_vect_num        10
+#define VMINT_vect            _VECTOR(5)
+#define VMINT_vect_num        5
 
 /* Timer0 Interval Interrupt */
-#define T0INT_vect            _VECTOR(12)
-#define T0INT_vect_num        12
+#define T0INT_vect            _VECTOR(6)
+#define T0INT_vect_num        6
 
 /* Timer3 Capture Interrupt */
-#define T3CAPINT_vect            _VECTOR(14)
-#define T3CAPINT_vect_num        14
+#define T3CAPINT_vect            _VECTOR(7)
+#define T3CAPINT_vect_num        7
 
 /* Timer3 Compare Match Interrupt */
-#define T3COMINT_vect            _VECTOR(16)
-#define T3COMINT_vect_num        16
+#define T3COMINT_vect            _VECTOR(8)
+#define T3COMINT_vect_num        8
 
 /* Timer3 Overflow Interrupt */
-#define T3OVFINT_vect            _VECTOR(18)
-#define T3OVFINT_vect_num        18
+#define T3OVFINT_vect            _VECTOR(9)
+#define T3OVFINT_vect_num        9
 
 /* Timer2 Compare Match Interrupt */
-#define T2COMINT_vect            _VECTOR(20)
-#define T2COMINT_vect_num        20
+#define T2COMINT_vect            _VECTOR(10)
+#define T2COMINT_vect_num        10
 
 /* Timer2 Overflow Interrupt */
-#define T2OVFINT_vect            _VECTOR(22)
-#define T2OVFINT_vect_num        22
+#define T2OVFINT_vect            _VECTOR(11)
+#define T2OVFINT_vect_num        11
 
 /* Timer1 Interval Interrupt */
-#define T1INT_vect            _VECTOR(24)
-#define T1INT_vect_num        24
+#define T1INT_vect            _VECTOR(12)
+#define T1INT_vect_num        12
 
 /* SPI Serial Transfer Complete */
-#define SPISTC_vect            _VECTOR(26)
-#define SPISTC_vect_num        26
+#define SPISTC_vect            _VECTOR(13)
+#define SPISTC_vect_num        13
 
 /* Timer Modulator SSI Receive Buffer Interrupt */
-#define TMRXBINT_vect            _VECTOR(28)
-#define TMRXBINT_vect_num        28
+#define TMRXBINT_vect            _VECTOR(14)
+#define TMRXBINT_vect_num        14
 
 /* Timer Modulator SSI Transmit Buffer Interrupt */
-#define TMTXBINT_vect            _VECTOR(30)
-#define TMTXBINT_vect_num        30
+#define TMTXBINT_vect            _VECTOR(15)
+#define TMTXBINT_vect_num        15
 
 /* Timer Modulator Transmit Complete Interrupt */
-#define TMTXCINT_vect            _VECTOR(32)
-#define TMTXCINT_vect_num        32
+#define TMTXCINT_vect            _VECTOR(16)
+#define TMTXCINT_vect_num        16
 
 /* AES Interrupt */
-#define AESINT_vect            _VECTOR(34)
-#define AESINT_vect_num        34
+#define AESINT_vect            _VECTOR(17)
+#define AESINT_vect_num        17
 
 /* External Input Clock Monitoring Interrupt */
-#define EXCMINT_vect            _VECTOR(36)
-#define EXCMINT_vect_num        36
+#define EXCMINT_vect            _VECTOR(18)
+#define EXCMINT_vect_num        18
 
 /* External XTAL Oscillator Break Down Interrupt */
-#define EXXMINT_vect            _VECTOR(38)
-#define EXXMINT_vect_num        38
+#define EXXMINT_vect            _VECTOR(19)
+#define EXXMINT_vect_num        19
 
 /* Real Time Clock Interrupt */
-#define RTCINT_vect            _VECTOR(40)
-#define RTCINT_vect_num        40
+#define RTCINT_vect            _VECTOR(20)
+#define RTCINT_vect_num        20
 
 /* EEPROM Ready Interrupt */
-#define EEREADY_vect            _VECTOR(42)
-#define EEREADY_vect_num        42
+#define EEREADY_vect            _VECTOR(21)
+#define EEREADY_vect_num        21
 
 /* Store Program Memory Ready  */
-#define SPMREADY_vect            _VECTOR(44)
-#define SPMREADY_vect_num        44
+#define SPMREADY_vect            _VECTOR(22)
+#define SPMREADY_vect_num        22
 
-#define _VECTORS_SIZE 90
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 46
+#else
+#  define _VECTORS_SIZE 46U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      2048
-#define E2PAGESIZE  16
-#define E2END       0x07FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      2048
+#  define E2PAGESIZE  16
+#  define E2END       0x07FF
+#else
+#  define E2START     0U
+#  define E2SIZE      2048U
+#  define E2PAGESIZE  16U
+#  define E2END       0x07FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -681,14 +737,16 @@
 #define FUSE_MEMORY_SIZE 1
 
 /* Fuse Byte */
-#define FUSE_CKDIV8 (unsigned char)~_BV(128)
-#define FUSE_DWEN (unsigned char)~_BV(64)
-#define FUSE_SPIEN (unsigned char)~_BV(32)
-#define FUSE_WDTON (unsigned char)~_BV(16)
-#define FUSE_EESAVE (unsigned char)~_BV(8)
-#define FUSE_Reserved (unsigned char)~_BV(4)
-#define FUSE__32OEN (unsigned char)~_BV(2)
-#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
+#define FUSE__32OEN      (unsigned char)~_BV(1)
+#define FUSE_Reserved    (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
+
+
 
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
@@ -703,10 +761,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
 
 #endif /* #ifdef _AVR_ATA5795_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa5831.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa5831.h
@@ -1,1949 +1,1959 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATA5831_H_INCLUDED
-#define _AVR_ATA5831_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa5831.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PRR0    _SFR_IO8(0x01)
-#define PRSPI   0
-#define PRRXDC  1
-#define PRTXDC  2
-#define PRCRC   3
-#define PRVM    4
-#define PRCO    5
-
-#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRRXDC)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO))
-#define __AVR_HAVE_PRR0_PRSPI
-#define __AVR_HAVE_PRR0_PRRXDC
-#define __AVR_HAVE_PRR0_PRTXDC
-#define __AVR_HAVE_PRR0_PRCRC
-#define __AVR_HAVE_PRR0_PRVM
-#define __AVR_HAVE_PRR0_PRCO
-
-#define PRR1    _SFR_IO8(0x02)
-#define PRT1    0
-#define PRT2    1
-#define PRT3    2
-#define PRT4    3
-#define PRT5    4
-
-#define __AVR_HAVE_PRR1	((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5))
-#define __AVR_HAVE_PRR1_PRT1
-#define __AVR_HAVE_PRR1_PRT2
-#define __AVR_HAVE_PRR1_PRT3
-#define __AVR_HAVE_PRR1_PRT4
-#define __AVR_HAVE_PRR1_PRT5
-
-#define PRR2    _SFR_IO8(0x03)
-#define PRXB    0
-#define PRXA    1
-#define PRSF    2
-#define PRDF    3
-#define PRIDS   4
-#define PRRS    5
-#define PRTM    6
-#define PRSSM   7
-
-#define __AVR_HAVE_PRR2	((1<<PRXB)|(1<<PRXA)|(1<<PRSF)|(1<<PRDF)|(1<<PRIDS)|(1<<PRRS)|(1<<PRTM)|(1<<PRSSM))
-#define __AVR_HAVE_PRR2_PRXB
-#define __AVR_HAVE_PRR2_PRXA
-#define __AVR_HAVE_PRR2_PRSF
-#define __AVR_HAVE_PRR2_PRDF
-#define __AVR_HAVE_PRR2_PRIDS
-#define __AVR_HAVE_PRR2_PRRS
-#define __AVR_HAVE_PRR2_PRTM
-#define __AVR_HAVE_PRR2_PRSSM
-
-#define RDPR    _SFR_IO8(0x04)
-#define PRPTB   0
-#define PRPTA   1
-#define PRFLT   2
-#define PRTMP   3
-#define APRPTB  4
-#define APRPTA  5
-#define ARDPRF  6
-#define RDPRF   7
-
-#define PINB    _SFR_IO8(0x05)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x06)
-#define DDRB7   7
-// Inserted "DDB7" from "DDRB7" due to compatibility
-#define DDB7    7
-#define DDRB6   6
-// Inserted "DDB6" from "DDRB6" due to compatibility
-#define DDB6    6
-#define DDRB5   5
-// Inserted "DDB5" from "DDRB5" due to compatibility
-#define DDB5    5
-#define DDRB4   4
-// Inserted "DDB4" from "DDRB4" due to compatibility
-#define DDB4    4
-#define DDRB3   3
-// Inserted "DDB3" from "DDRB3" due to compatibility
-#define DDB3    3
-#define DDRB2   2
-// Inserted "DDB2" from "DDRB2" due to compatibility
-#define DDB2    2
-#define DDRB1   1
-// Inserted "DDB1" from "DDRB1" due to compatibility
-#define DDB1    1
-#define DDRB0   0
-// Inserted "DDB0" from "DDRB0" due to compatibility
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x07)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINC    _SFR_IO8(0x08)
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x09)
-#define DDRC5   5
-// Inserted "DDC5" from "DDRC5" due to compatibility
-#define DDC5    5
-#define DDRC4   4
-// Inserted "DDC4" from "DDRC4" due to compatibility
-#define DDC4    4
-#define DDRC3   3
-// Inserted "DDC3" from "DDRC3" due to compatibility
-#define DDC3    3
-#define DDRC2   2
-// Inserted "DDC2" from "DDRC2" due to compatibility
-#define DDC2    2
-#define DDRC1   1
-// Inserted "DDC1" from "DDRC1" due to compatibility
-#define DDC1    1
-#define DDRC0   0
-// Inserted "DDC0" from "DDRC0" due to compatibility
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x0A)
-#define PORTC5  5
-#define PORTC4  4
-#define PORTC3  3
-#define PORTC2  2
-#define PORTC1  1
-#define PORTC0  0
-
-#define FSCR    _SFR_IO8(0x0B)
-#define TXMOD   0
-#define SFM     1
-#define TXMS0   2
-#define TXMS1   3
-#define PAOER   4
-#define PAON    7
-
-/* Reserved [0x0C] */
-
-#define RDSIFR  _SFR_IO8(0x0D)
-#define NBITA   0
-#define NBITB   1
-#define EOTA    2
-#define EOTB    3
-#define SOTA    4
-#define SOTB    5
-#define WCOA    6
-#define WCOB    7
-
-#define MCUCR   _SFR_IO8(0x0E)
-#define IVCE    0
-#define IVSEL   1
-#define SPIIO   2
-#define ENPS    3
-#define PUD     4
-#define PB4HS   5
-#define PB7LS   6
-#define PB7HS   7
-
-#define PCIFR   _SFR_IO8(0x0F)
-#define PCIF0   0
-#define PCIF1   1
-
-#define T0CR    _SFR_IO8(0x10)
-#define T0PS0   0
-#define T0PS1   1
-#define T0PS2   2
-#define T0IE    3
-#define T0PR    4
-
-#define T1CR    _SFR_IO8(0x11)
-#define T1OTM   0
-#define T1CTM   1
-#define T1CRM   2
-#define T1TOP   4
-#define T1RES   5
-#define T1TOS   6
-#define T1ENA   7
-
-#define T2CR    _SFR_IO8(0x12)
-#define T2OTM   0
-#define T2CTM   1
-#define T2CRM   2
-#define T2TOP   4
-#define T2RES   5
-#define T2TOS   6
-#define T2ENA   7
-
-#define T3CR    _SFR_IO8(0x13)
-#define T3OTM   0
-#define T3CTM   1
-#define T3CRM   2
-#define T3CPRM  3
-#define T3TOP   4
-#define T3RES   5
-#define T3TOS   6
-#define T3ENA   7
-
-#define T4CR    _SFR_IO8(0x14)
-#define T4OTM   0
-#define T4CTM   1
-#define T4CRM   2
-#define T4CPRM  3
-#define T4TOP   4
-#define T4RES   5
-#define T4TOS   6
-#define T4ENA   7
-
-#define T1IFR   _SFR_IO8(0x15)
-#define T1OFF   0
-#define T1COF   1
-
-#define T2IFR   _SFR_IO8(0x16)
-#define T2OFF   0
-#define T2COF   1
-
-#define T3IFR   _SFR_IO8(0x17)
-#define T3OFF   0
-#define T3COF   1
-#define T3ICF   2
-
-#define T4IFR   _SFR_IO8(0x18)
-#define T4OFF   0
-#define T4COF   1
-#define T4ICF   2
-
-#define T5IFR   _SFR_IO8(0x19)
-#define T5OFF   0
-#define T5COF   1
-
-#define GPIOR0  _SFR_IO8(0x1A)
-
-#define GPIOR3  _SFR_IO8(0x1B)
-
-#define GPIOR4  _SFR_IO8(0x1C)
-
-#define GPIOR5  _SFR_IO8(0x1D)
-
-#define GPIOR6  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-#define EEPAGE  6
-#define NVMBSY  7
-
-#define EEDR    _SFR_IO8(0x20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define EEPR    _SFR_IO8(0x23)
-#define EEAP0   0
-#define EEAP1   1
-#define EEAP2   2
-#define EEAP3   3
-
-#define GPIOR1  _SFR_IO8(0x24)
-
-#define GPIOR2  _SFR_IO8(0x25)
-
-#define PCICR   _SFR_IO8(0x26)
-#define PCIE0   0
-#define PCIE1   1
-
-#define EIMSK   _SFR_IO8(0x27)
-#define INT0    0
-#define INT1    1
-
-#define EIFR    _SFR_IO8(0x28)
-#define INTF0   0
-#define INTF1   1
-
-#define CRCDIR  _SFR_IO8(0x29)
-
-#define VMCSR   _SFR_IO8(0x2A)
-#define VMLS0   0
-#define VMLS1   1
-#define VMLS2   2
-#define VMLS3   3
-#define VMIM    4
-#define VMF     5
-
-#define MCUSR   _SFR_IO8(0x2B)
-#define PORF    0
-#define EXTRF   1
-#define WDRF    3
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define RXIF    4
-#define TXIF    5
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-#define T0IFR   _SFR_IO8(0x2F)
-#define T0F     0
-
-/* Reserved [0x30] */
-
-#define DWDR    _SFR_IO8(0x31)
-
-/* Reserved [0x32] */
-
-#define RDCR    _SFR_IO8(0x33)
-#define RDPU    0
-#define ADIVEN  1
-#define RDEN    2
-
-#define EOTSA   _SFR_IO8(0x34)
-#define CARFA   0
-#define AMPFA   1
-#define SYTFA   2
-#define MANFA   3
-#define TMOFA   4
-#define TELRA   5
-#define RRFA    6
-#define EOTBF   7
-
-#define EOTCA   _SFR_IO8(0x35)
-#define CARFEA  0
-#define AMPFEA  1
-#define SYTFEA  2
-#define MANFEA  3
-#define TMOFEA  4
-#define TELREA  5
-#define RRFEA   6
-#define EOTBFE  7
-
-#define EOTSB   _SFR_IO8(0x36)
-#define CARFB   0
-#define AMPFB   1
-#define SYTFB   2
-#define MANFB   3
-#define TMOFB   4
-#define TELRB   5
-#define RRFB    6
-#define EOTAF   7
-
-#define EOTCB   _SFR_IO8(0x37)
-#define CARFEB  0
-#define AMPFEB  1
-#define SYTFEB  2
-#define MANFEB  3
-#define TMOFEB  4
-#define TELREB  5
-#define RRFEB   6
-#define EOTAFE  7
-
-#define SMCR    _SFR_IO8(0x38)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define CMCR    _SFR_IO8(0x39)
-#define CMM0    0
-#define CMM1    1
-#define CMM2    2
-#define CCS     3
-#define SRCD    4
-#define CMONEN  6
-#define CMCCE   7
-
-#define CMIMR   _SFR_IO8(0x3A)
-#define ECIE    0
-
-#define CLPR    _SFR_IO8(0x3B)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLTPS0  3
-#define CLTPS1  4
-#define CLTPS2  5
-#define CLPCE   7
-
-#define SPMCSR  _SFR_IO8(0x3C)
-#define SELFPRGEN 0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define SPMIE   7
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define FSEN    _SFR_MEM8(0x60)
-#define SDPU    0
-#define SDEN    1
-#define GAEN    2
-#define PEEN    3
-#define ASEN    4
-#define ANTT    5
-
-#define FSFCR   _SFR_MEM8(0x61)
-#define BTSEL0  0
-#define BTSEL1  1
-#define ASDIV0  4
-#define ASDIV1  5
-#define ASDIV2  6
-#define ASDIV3  7
-
-/* Combine GACDIVL and GACDIVH */
-#define GACDIV  _SFR_MEM16(0x62)
-
-#define GACDIVL _SFR_MEM8(0x62)
-#define GACDIVH _SFR_MEM8(0x63)
-
-#define FFREQ1L _SFR_MEM8(0x64)
-
-#define FFREQ1M _SFR_MEM8(0x65)
-
-#define FFREQ1H _SFR_MEM8(0x66)
-
-#define FFREQ2L _SFR_MEM8(0x67)
-
-#define FFREQ2M _SFR_MEM8(0x68)
-
-#define FFREQ2H _SFR_MEM8(0x69)
-
-/* Reserved [0x6A] */
-
-#define EICRA   _SFR_MEM8(0x6B)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-#define PCMSK0  _SFR_MEM8(0x6C)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6D)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-
-#define WDTCR   _SFR_MEM8(0x6E)
-#define WDPS0   0
-#define WDPS1   1
-#define WDPS2   2
-#define WDE     3
-#define WDCE    4
-
-#define T1CNT   _SFR_MEM8(0x6F)
-
-#define T1COR   _SFR_MEM8(0x70)
-
-#define T1MR    _SFR_MEM8(0x71)
-#define T1CS0   0
-#define T1CS1   1
-#define T1PS0   2
-#define T1PS1   3
-#define T1PS2   4
-#define T1PS3   5
-#define T1DC0   6
-#define T1DC1   7
-
-#define T1IMR   _SFR_MEM8(0x72)
-#define T1OIM   0
-#define T1CIM   1
-
-#define T2CNT   _SFR_MEM8(0x73)
-
-#define T2COR   _SFR_MEM8(0x74)
-
-#define T2MR    _SFR_MEM8(0x75)
-#define T2CS0   0
-#define T2CS1   1
-#define T2PS0   2
-#define T2PS1   3
-#define T2PS2   4
-#define T2PS3   5
-#define T2DC0   6
-#define T2DC1   7
-
-#define T2IMR   _SFR_MEM8(0x76)
-#define T2OIM   0
-#define T2CIM   1
-
-/* Combine T3CNTL and T3CNTH */
-#define T3CNT   _SFR_MEM16(0x77)
-
-#define T3CNTL  _SFR_MEM8(0x77)
-#define T3CNTH  _SFR_MEM8(0x78)
-
-/* Combine T3CORL and T3CORH */
-#define T3COR   _SFR_MEM16(0x79)
-
-#define T3CORL  _SFR_MEM8(0x79)
-#define T3CORH  _SFR_MEM8(0x7A)
-
-/* Combine T3ICRL and T3ICRH */
-#define T3ICR   _SFR_MEM16(0x7B)
-
-#define T3ICRL  _SFR_MEM8(0x7B)
-#define T3ICRH  _SFR_MEM8(0x7C)
-
-#define T3MRA   _SFR_MEM8(0x7D)
-#define T3CS0   0
-#define T3CS1   1
-#define T3PS0   2
-#define T3PS1   3
-#define T3PS2   4
-
-#define T3MRB   _SFR_MEM8(0x7E)
-#define T3SCE   1
-#define T3CNC   2
-#define T3CE0   3
-#define T3CE1   4
-#define T3ICS0  5
-#define T3ICS1  6
-#define T3ICS2  7
-
-#define T3IMR   _SFR_MEM8(0x7F)
-#define T3OIM   0
-#define T3CIM   1
-#define T3CPIM  2
-
-/* Combine T4CNTL and T4CNTH */
-#define T4CNT   _SFR_MEM16(0x80)
-
-#define T4CNTL  _SFR_MEM8(0x80)
-#define T4CNTH  _SFR_MEM8(0x81)
-
-/* Combine T4CORL and T4CORH */
-#define T4COR   _SFR_MEM16(0x82)
-
-#define T4CORL  _SFR_MEM8(0x82)
-#define T4CORH  _SFR_MEM8(0x83)
-
-/* Combine T4ICRL and T4ICRH */
-#define T4ICR   _SFR_MEM16(0x84)
-
-#define T4ICRL  _SFR_MEM8(0x84)
-#define T4ICRH  _SFR_MEM8(0x85)
-
-#define T4MRA   _SFR_MEM8(0x86)
-#define T4CS0   0
-#define T4CS1   1
-#define T4PS0   2
-#define T4PS1   3
-#define T4PS2   4
-
-#define T4MRB   _SFR_MEM8(0x87)
-#define T4SCE   1
-#define T4CNC   2
-#define T4CE0   3
-#define T4CE1   4
-#define T4ICS0  5
-#define T4ICS1  6
-#define T4ICS2  7
-
-#define T4IMR   _SFR_MEM8(0x88)
-#define T4OIM   0
-#define T4CIM   1
-#define T4CPIM  2
-
-/* Reserved [0x89] */
-
-/* Combine T5OCRL and T5OCRH */
-#define T5OCR   _SFR_MEM16(0x8A)
-
-#define T5OCRL  _SFR_MEM8(0x8A)
-#define T5OCRH  _SFR_MEM8(0x8B)
-
-#define T5CCR   _SFR_MEM8(0x8C)
-#define T5CS0   0
-#define T5CS1   1
-#define T5CS2   2
-#define T5CTC   3
-
-/* Combine T5CNTL and T5CNTH */
-#define T5CNT   _SFR_MEM16(0x8D)
-
-#define T5CNTL  _SFR_MEM8(0x8D)
-#define T5CNTH  _SFR_MEM8(0x8E)
-
-#define T5IMR   _SFR_MEM8(0x8F)
-#define T5OIM   0
-#define T5CIM   1
-
-#define GTCCR   _SFR_MEM8(0x90)
-#define PSR10   0
-#define TSM     7
-
-#define SOTSB   _SFR_MEM8(0x91)
-#define CAROB   0
-#define AMPOB   1
-#define SYTOB   2
-#define MANOB   3
-#define WUPOB   4
-#define SFIDOB  5
-#define RROB    6
-#define WCOAO   7
-
-#define SOTSA   _SFR_MEM8(0x92)
-#define CAROA   0
-#define AMPOA   1
-#define SYTOA   2
-#define MANOA   3
-#define WUPOA   4
-#define SFIDOA  5
-#define RROA    6
-#define WCOBO   7
-
-#define SOTCB   _SFR_MEM8(0x93)
-#define CAROEB  0
-#define AMPOEB  1
-#define SYTOEB  2
-#define MANOEB  3
-#define WUPEB   4
-#define SFIDEB  5
-#define RROEB   6
-#define WCOAOE  7
-
-#define SOTCA   _SFR_MEM8(0x94)
-#define CAROEA  0
-#define AMPOEA  1
-#define SYTOEA  2
-#define MANOEA  3
-#define WUPEA   4
-#define SFIDEA  5
-#define RROEA   6
-#define WCOBOE  7
-
-#define TESRB   _SFR_MEM8(0x95)
-#define CRCOB   0
-#define EOTLB0  1
-#define EOTLB1  2
-
-#define TESRA   _SFR_MEM8(0x96)
-#define CRCOA   0
-#define EOTLA0  1
-#define EOTLA1  2
-
-/* Reserved [0x97] */
-
-#define RDSIMR  _SFR_MEM8(0x98)
-#define NBITAM  0
-#define NBITBM  1
-#define EOTAM   2
-#define EOTBM   3
-#define SOTAM   4
-#define SOTBM   5
-#define WCOAM   6
-#define WCOBM   7
-
-#define RDOCR   _SFR_MEM8(0x99)
-#define TMDS0   1
-#define TMDS1   2
-#define ETRPA   3
-#define ETRPB   4
-#define RDSIDA  5
-#define RDSIDB  6
-
-/* Reserved [0x9A] */
-
-#define TEMPL   _SFR_MEM8(0x9B)
-
-#define TEMPH   _SFR_MEM8(0x9C)
-
-#define SYCB    _SFR_MEM8(0x9D)
-#define SYCSB0  0
-#define SYCSB1  1
-#define SYCSB2  2
-#define SYCSB3  3
-#define SYTLB0  4
-#define SYTLB1  5
-#define SYTLB2  6
-#define SYTLB3  7
-
-#define SYCA    _SFR_MEM8(0x9E)
-#define SYCSA0  0
-#define SYCSA1  1
-#define SYCSA2  2
-#define SYCSA3  3
-#define SYTLA0  4
-#define SYTLA1  5
-#define SYTLA2  6
-#define SYTLA3  7
-
-#define RXFOB   _SFR_MEM8(0x9F)
-
-#define RXFOA   _SFR_MEM8(0xA0)
-
-#define DMMB    _SFR_MEM8(0xA1)
-#define DMATB0  0
-#define DMATB1  1
-#define DMATB2  2
-#define DMATB3  3
-#define DMATB4  4
-#define DMPB    5
-#define DMHB    6
-#define DMNEB   7
-
-#define DMMA    _SFR_MEM8(0xA2)
-#define DMATA0  0
-#define DMATA1  1
-#define DMATA2  2
-#define DMATA3  3
-#define DMATA4  4
-#define DMPA    5
-#define DMHA    6
-#define DMNEA   7
-
-#define DMCDB   _SFR_MEM8(0xA3)
-#define DMCLB0  0
-#define DMCLB1  1
-#define DMCLB2  2
-#define DMCLB3  3
-#define DMCLB4  4
-#define DMCTB0  5
-#define DMCTB1  6
-#define DMCTB2  7
-
-#define DMCDA   _SFR_MEM8(0xA4)
-#define DMCLA0  0
-#define DMCLA1  1
-#define DMCLA2  2
-#define DMCLA3  3
-#define DMCLA4  4
-#define DMCTA0  5
-#define DMCTA1  6
-#define DMCTA2  7
-
-#define DMCRB   _SFR_MEM8(0xA5)
-#define DMPGB0  0
-#define DMPGB1  1
-#define DMPGB2  2
-#define DMPGB3  3
-#define DMPGB4  4
-#define SASKB   5
-#define SY1TB   6
-#define DMARB   7
-
-#define DMCRA   _SFR_MEM8(0xA6)
-#define DMPGA0  0
-#define DMPGA1  1
-#define DMPGA2  2
-#define DMPGA3  3
-#define DMPGA4  4
-#define SASKA   5
-#define SY1TA   6
-#define DMARA   7
-
-#define DMDRB   _SFR_MEM8(0xA7)
-#define DMAB0   0
-#define DMAB1   1
-#define DMAB2   2
-#define DMAB3   3
-#define DMDNB0  4
-#define DMDNB1  5
-#define DMDNB2  6
-#define DMDNB3  7
-
-#define DMDRA   _SFR_MEM8(0xA8)
-#define DMAA0   0
-#define DMAA1   1
-#define DMAA2   2
-#define DMAA3   3
-#define DMDNA0  4
-#define DMDNA1  5
-#define DMDNA2  6
-#define DMDNA3  7
-
-#define CHCR    _SFR_MEM8(0xA9)
-#define BWM0    0
-#define BWM1    1
-#define BWM2    2
-#define BWM3    3
-
-#define CHDN    _SFR_MEM8(0xAA)
-#define BBDN0   0
-#define BBDN1   1
-#define BBDN2   2
-#define BBDN3   3
-#define BBDN4   4
-#define ADCDN   5
-
-#define SFIDCB  _SFR_MEM8(0xAB)
-#define SFIDTB0 0
-#define SFIDTB1 1
-#define SFIDTB2 2
-#define SFIDTB3 3
-#define SFIDTB4 4
-#define SEMEB   7
-
-#define SFIDLB  _SFR_MEM8(0xAC)
-#define SFIDLB0 0
-#define SFIDLB1 1
-#define SFIDLB2 2
-#define SFIDLB3 3
-#define SFIDLB4 4
-#define SFIDLB5 5
-
-#define WUPTB   _SFR_MEM8(0xAD)
-#define WUPTB0  0
-#define WUPTB1  1
-#define WUPTB2  2
-#define WUPTB3  3
-#define WUPTB4  4
-
-#define WUPLB   _SFR_MEM8(0xAE)
-#define WUPLB0  0
-#define WUPLB1  1
-#define WUPLB2  2
-#define WUPLB3  3
-#define WUPLB4  4
-#define WUPLB5  5
-
-#define SFID1B  _SFR_MEM8(0xAF)
-
-#define SFID2B  _SFR_MEM8(0xB0)
-
-#define SFID3B  _SFR_MEM8(0xB1)
-
-#define SFID4B  _SFR_MEM8(0xB2)
-
-#define WUP1B   _SFR_MEM8(0xB3)
-
-#define WUP2B   _SFR_MEM8(0xB4)
-
-#define WUP3B   _SFR_MEM8(0xB5)
-
-#define WUP4B   _SFR_MEM8(0xB6)
-
-#define SFIDCA  _SFR_MEM8(0xB7)
-#define SFIDTA0 0
-#define SFIDTA1 1
-#define SFIDTA2 2
-#define SFIDTA3 3
-#define SFIDTA4 4
-#define SEMEA   7
-
-#define SFIDLA  _SFR_MEM8(0xB8)
-#define SFIDLA0 0
-#define SFIDLA1 1
-#define SFIDLA2 2
-#define SFIDLA3 3
-#define SFIDLA4 4
-#define SFIDLA5 5
-
-#define WUPTA   _SFR_MEM8(0xB9)
-#define WUPTA0  0
-#define WUPTA1  1
-#define WUPTA2  2
-#define WUPTA3  3
-#define WUPTA4  4
-
-#define WUPLA   _SFR_MEM8(0xBA)
-#define WUPLA0  0
-#define WUPLA1  1
-#define WUPLA2  2
-#define WUPLA3  3
-#define WUPLA4  4
-#define WUPLA5  5
-
-#define SFID1A  _SFR_MEM8(0xBB)
-
-#define SFID2A  _SFR_MEM8(0xBC)
-
-#define SFID3A  _SFR_MEM8(0xBD)
-
-#define SFID4A  _SFR_MEM8(0xBE)
-
-#define WUP1A   _SFR_MEM8(0xBF)
-
-#define WUP2A   _SFR_MEM8(0xC0)
-
-#define WUP3A   _SFR_MEM8(0xC1)
-
-#define WUP4A   _SFR_MEM8(0xC2)
-
-#define CLKOD   _SFR_MEM8(0xC3)
-
-#define CLKOCR  _SFR_MEM8(0xC4)
-#define CLKOS0  0
-#define CLKOS1  1
-#define CLKOEN  2
-
-#define XFUSE   _SFR_MEM8(0xC5)
-
-#define SRCCAL  _SFR_MEM8(0xC6)
-#define SRCCAL0 0
-#define SRCCAL1 1
-#define SRCCAL2 2
-#define SRCCAL3 3
-#define SRCCAL4 4
-#define SRCCAL5 5
-#define SRCTC0  6
-#define SRCTC1  7
-
-#define FRCCAL  _SFR_MEM8(0xC7)
-#define FRCCAL0 0
-#define FRCCAL1 1
-#define FRCCAL2 2
-#define FRCCAL3 3
-#define FRCCAL4 4
-#define FRCTC   5
-
-#define CMSR    _SFR_MEM8(0xC8)
-#define ECF     0
-
-#define CMOCR   _SFR_MEM8(0xC9)
-#define FRCAO   0
-#define SRCAO   1
-#define FRCACT  2
-#define SRCACT  3
-
-#define SUPFR   _SFR_MEM8(0xCA)
-#define AVCCRF  0
-#define AVCCLF  1
-
-#define SUPCR   _SFR_MEM8(0xCB)
-#define AVCCRM  0
-#define AVCCLM  1
-#define PVEN    2
-#define DVDIS   4
-#define AVEN    5
-#define AVDIC   6
-
-#define SUPCA1  _SFR_MEM8(0xCC)
-#define PV22    2
-#define PVDIC   3
-#define PVCAL0  4
-#define PVCAL1  5
-#define PVCAL2  6
-#define PVCAL3  7
-
-#define SUPCA2  _SFR_MEM8(0xCD)
-#define BGCAL0  0
-#define BGCAL1  1
-#define BGCAL2  2
-#define BGCAL3  3
-
-#define SUPCA3  _SFR_MEM8(0xCE)
-#define ACAL4   0
-#define ACAL5   1
-#define ACAL6   2
-#define ACAL7   3
-#define DCAL4   4
-#define DCAL5   5
-#define DCAL6   6
-
-#define SUPCA4  _SFR_MEM8(0xCF)
-#define ACAL0   0
-#define ACAL1   1
-#define ACAL2   2
-#define ACAL3   3
-#define DCAL0   4
-#define DCAL1   5
-#define DCAL2   6
-#define DCAL3   7
-
-#define CALRDY  _SFR_MEM8(0xD0)
-
-#define VMCAL   _SFR_MEM8(0xD1)
-#define VMCAL0  0
-#define VMCAL1  1
-#define VMCAL2  2
-
-#define DFS     _SFR_MEM8(0xD2)
-#define DFFLRF  0
-#define DFUFL   1
-#define DFOFL   2
-
-/* Combine DFTLL and DFTLH */
-#define DFTL    _SFR_MEM16(0xD3)
-
-#define DFTLL   _SFR_MEM8(0xD3)
-#define DFTLH   _SFR_MEM8(0xD4)
-
-#define DFL     _SFR_MEM8(0xD5)
-#define DFFLS0  0
-#define DFFLS1  1
-#define DFFLS2  2
-#define DFFLS3  3
-#define DFFLS4  4
-#define DFFLS5  5
-#define DFCLR   7
-
-#define DFWP    _SFR_MEM8(0xD6)
-#define DFWP0   0
-#define DFWP1   1
-#define DFWP2   2
-#define DFWP3   3
-#define DFWP4   4
-#define DFWP5   5
-
-#define DFRP    _SFR_MEM8(0xD7)
-#define DFRP0   0
-#define DFRP1   1
-#define DFRP2   2
-#define DFRP3   3
-#define DFRP4   4
-#define DFRP5   5
-
-#define DFD     _SFR_MEM8(0xD8)
-
-#define DFI     _SFR_MEM8(0xD9)
-#define DFFLIM  0
-#define DFERIM  1
-
-#define DFC     _SFR_MEM8(0xDA)
-#define DFFLC0  0
-#define DFFLC1  1
-#define DFFLC2  2
-#define DFFLC3  3
-#define DFFLC4  4
-#define DFFLC5  5
-#define DFDRA   7
-
-#define SFS     _SFR_MEM8(0xDB)
-#define SFFLRF  0
-#define SFUFL   1
-#define SFOFL   2
-
-#define SFL     _SFR_MEM8(0xDC)
-#define SFFLS0  0
-#define SFFLS1  1
-#define SFFLS2  2
-#define SFFLS3  3
-#define SFFLS4  4
-#define SFCLR   7
-
-#define SFWP    _SFR_MEM8(0xDD)
-#define SFWP0   0
-#define SFWP1   1
-#define SFWP2   2
-#define SFWP3   3
-#define SFWP4   4
-
-#define SFRP    _SFR_MEM8(0xDE)
-#define SFRP0   0
-#define SFRP1   1
-#define SFRP2   2
-#define SFRP3   3
-#define SFRP4   4
-
-#define SFD     _SFR_MEM8(0xDF)
-
-#define SFI     _SFR_MEM8(0xE0)
-#define SFFLIM  0
-#define SFERIM  1
-
-#define SFC     _SFR_MEM8(0xE1)
-#define SFFLC0  0
-#define SFFLC1  1
-#define SFFLC2  2
-#define SFFLC3  3
-#define SFFLC4  4
-#define SFDRA   7
-
-#define SSMCR   _SFR_MEM8(0xE2)
-#define SSMTX   0
-#define SSMTM   1
-#define SSMTGE  2
-#define SSMTPE  3
-#define SSMPVE  4
-#define SSMTAE  5
-#define SETRPA  6
-#define SETRPB  7
-
-#define SSMRCR  _SFR_MEM8(0xE3)
-#define SSMPA   0
-#define SSMPB   1
-#define SSMADA  2
-#define SSMADB  3
-#define SSMPVS  4
-#define SSMIFA  5
-#define SSMIDSE 6
-#define SSMTMOE 7
-
-#define SSMFBR  _SFR_MEM8(0xE4)
-#define SSMFID0 0
-#define SSMFID1 1
-#define SSMFID2 2
-#define SSMDFDT 3
-#define SSMHADT 4
-#define SSMPLDT 5
-
-#define SSMRR   _SFR_MEM8(0xE5)
-#define SSMR    0
-#define SSMST   1
-
-#define SSMSR   _SFR_MEM8(0xE6)
-#define SSMESM0 0
-#define SSMESM1 1
-#define SSMESM2 2
-#define SSMESM3 3
-#define SSMERR  7
-
-#define SSMIFR  _SFR_MEM8(0xE7)
-#define SSMIF   0
-
-#define SSMIMR  _SFR_MEM8(0xE8)
-#define SSMIM   0
-
-#define MSMSTR  _SFR_MEM8(0xE9)
-#define SSMMST0 0
-#define SSMMST1 1
-#define SSMMST2 2
-#define SSMMST3 3
-#define SSMMST4 4
-
-#define SSMSTR  _SFR_MEM8(0xEA)
-#define SSMSTA0 0
-#define SSMSTA1 1
-#define SSMSTA2 2
-#define SSMSTA3 3
-#define SSMSTA4 4
-#define SSMSTA5 5
-
-#define SSMXSR  _SFR_MEM8(0xEB)
-#define SSMSTB0 0
-#define SSMSTB1 1
-#define SSMSTB2 2
-#define SSMSTB3 3
-#define SSMSTB4 4
-#define SSMSTB5 5
-
-#define MSMCR1  _SFR_MEM8(0xEC)
-#define MSMSM00 0
-#define MSMSM01 1
-#define MSMSM02 2
-#define MSMSM03 3
-#define MSMSM10 4
-#define MSMSM11 5
-#define MSMSM12 6
-#define MSMSM13 7
-
-#define MSMCR2  _SFR_MEM8(0xED)
-#define MSMSM20 0
-#define MSMSM21 1
-#define MSMSM22 2
-#define MSMSM23 3
-#define MSMSM30 4
-#define MSMSM31 5
-#define MSMSM32 6
-#define MSMSM33 7
-
-#define MSMCR3  _SFR_MEM8(0xEE)
-#define MSMSM40 0
-#define MSMSM41 1
-#define MSMSM42 2
-#define MSMSM43 3
-#define MSMSM50 4
-#define MSMSM51 5
-#define MSMSM52 6
-#define MSMSM53 7
-
-#define MSMCR4  _SFR_MEM8(0xEF)
-#define MSMSM60 0
-#define MSMSM61 1
-#define MSMSM62 2
-#define MSMSM63 3
-#define MSMSM70 4
-#define MSMSM71 5
-#define MSMSM72 6
-#define MSMSM73 7
-
-#define GTCR    _SFR_MEM8(0xF0)
-#define RXTEHA  0
-#define GAPMA   1
-#define DARA    2
-#define IWUPA   3
-#define RXTEHB  4
-#define GAPMB   5
-#define DARB    6
-#define IWUPB   7
-
-#define SOTC1A  _SFR_MEM8(0xF1)
-#define CAROEA1 0
-#define AMPOEA1 1
-#define SYTOEA1 2
-#define MANOEA1 3
-#define WUPEA1  4
-#define SFIDEA1 5
-#define RROEA1  6
-#define WCOBOE1 7
-
-#define SOTC2A  _SFR_MEM8(0xF2)
-#define CAROEA2 0
-#define AMPOEA2 1
-#define SYTOEA2 2
-#define MANOEA2 3
-#define WUPEA2  4
-#define SFIDEA2 5
-#define RROEA2  6
-#define WCOBOE2 7
-
-#define SOTC1B  _SFR_MEM8(0xF3)
-#define CAROEB1 0
-#define AMPOEB1 1
-#define SYTOEB1 2
-#define MANOEB1 3
-#define WUPEB1  4
-#define SFIDEB1 5
-#define RROEB1  6
-#define WCOAOE1 7
-
-#define SOTC2B  _SFR_MEM8(0xF4)
-#define CAROEB2 0
-#define AMPOEB2 1
-#define SYTOEB2 2
-#define MANOEB2 3
-#define WUPEB2  4
-#define SFIDEB2 5
-#define RROEB2  6
-#define WCOAOE2 7
-
-#define EOTC1A  _SFR_MEM8(0xF5)
-#define CARFEA1 0
-#define AMPFEA1 1
-#define SYTFEA1 2
-#define MANFEA1 3
-#define TMOFEA1 4
-#define TELREA1 5
-#define RRFEA1  6
-#define EOTBFE1 7
-
-#define EOTC2A  _SFR_MEM8(0xF6)
-#define CARFEA2 0
-#define AMPFEA2 1
-#define SYTFEA2 2
-#define MANFEA2 3
-#define TMOFEA2 4
-#define TELREA2 5
-#define RRFEA2  6
-#define EOTBFE2 7
-
-#define EOTC3A  _SFR_MEM8(0xF7)
-#define CARFEA3 0
-#define AMPFEA3 1
-#define SYTFEA3 2
-#define MANFEA3 3
-#define TMOFEA3 4
-#define TELREA3 5
-#define RRFEA3  6
-#define EOTBFE3 7
-
-#define EOTC1B  _SFR_MEM8(0xF8)
-#define CARFEB1 0
-#define AMPFEB1 1
-#define SYTFEB1 2
-#define MANFEB1 3
-#define TMOFEB1 4
-#define TELREB1 5
-#define RRFEB1  6
-#define EOTAFE1 7
-
-#define EOTC2B  _SFR_MEM8(0xF9)
-#define CARFEB2 0
-#define AMPFEB2 1
-#define SYTFEB2 2
-#define MANFEB2 3
-#define TMOFEB2 4
-#define TELREB2 5
-#define RRFEB2  6
-#define EOTAFE2 7
-
-#define EOTC3B  _SFR_MEM8(0xFA)
-#define CARFEB3 0
-#define AMPFEB3 1
-#define SYTFEB3 2
-#define MANFEB3 3
-#define TMOFEB3 4
-#define TELREB3 5
-#define RRFEB3  6
-#define EOTAFE3 7
-
-#define WCOTOA  _SFR_MEM8(0xFB)
-
-#define WCOTOB  _SFR_MEM8(0xFC)
-
-#define SOTTOA  _SFR_MEM8(0xFD)
-
-#define SOTTOB  _SFR_MEM8(0xFE)
-
-#define SSMFCR  _SFR_MEM8(0xFF)
-#define SSMIDSO 0
-#define SSMIDSF 1
-
-#define FESR    _SFR_MEM8(0x100)
-#define LBSAT   0
-#define HBSAT   1
-#define XRDY    2
-#define PLCK    3
-#define ANTS    4
-
-#define FEEN1   _SFR_MEM8(0x101)
-#define PLEN    0
-#define PLCAL   1
-#define XTOEN   2
-#define LNAEN   3
-#define ADEN    4
-#define ADCLK   5
-#define PLSP1   6
-#define ATEN    7
-
-#define FEEN2   _SFR_MEM8(0x102)
-#define SDRX    0
-#define SDTX    1
-#define PAEN    2
-#define TMPM    3
-#define PLPEN   4
-#define XTPEN   5
-#define CPBIA   6
-
-#define FELNA   _SFR_MEM8(0x103)
-#define LBH0    0
-#define LBH1    1
-#define LBH2    2
-#define LBH3    3
-#define LBL0    4
-#define LBL1    5
-#define LBL2    6
-#define LBL3    7
-
-#define FEAT    _SFR_MEM8(0x104)
-#define ANTN0   0
-#define ANTN1   1
-#define ANTN2   2
-#define ANTN3   3
-
-#define FEPAC   _SFR_MEM8(0x105)
-
-#define FEVCT   _SFR_MEM8(0x106)
-#define FEVCT0  0
-#define FEVCT1  1
-#define FEVCT2  2
-#define FEVCT3  3
-
-#define FEBT    _SFR_MEM8(0x107)
-#define CTN20   0
-#define CTN21   1
-#define RTN20   2
-#define RTN21   3
-
-#define FEMS    _SFR_MEM8(0x108)
-#define PLLS0   0
-#define PLLS1   1
-#define PLLS2   2
-#define PLLS3   3
-#define PLLM0   4
-#define PLLM1   5
-#define PLLM2   6
-#define PLLM3   7
-
-#define FETN4   _SFR_MEM8(0x109)
-#define CTN40   0
-#define CTN41   1
-#define CTN42   2
-#define CTN43   3
-#define RTN40   4
-#define RTN41   5
-#define RTN42   6
-#define RTN43   7
-
-#define FECR    _SFR_MEM8(0x10A)
-#define LBNHB   0
-#define S4N3    1
-#define ANDP    2
-#define ADHS    3
-#define PLCKG   4
-#define ANPS    5
-
-#define FEVCO   _SFR_MEM8(0x10B)
-#define CPCC0   0
-#define CPCC1   1
-#define CPCC2   2
-#define CPCC3   3
-#define VCOB0   4
-#define VCOB1   5
-#define VCOB2   6
-#define VCOB3   7
-
-#define FEALR   _SFR_MEM8(0x10C)
-#define RNGE0   0
-#define RNGE1   1
-
-#define FEANT   _SFR_MEM8(0x10D)
-#define LVLC0   0
-#define LVLC1   1
-#define LVLC2   2
-#define LVLC3   3
-
-#define FEBIA   _SFR_MEM8(0x10E)
-#define IFAEN   7
-
-/* Reserved [0x10F..0x11F] */
-
-#define TMFSM   _SFR_MEM8(0x120)
-#define TMSSM0  0
-#define TMSSM1  1
-#define TMSSM2  2
-#define TMSSM3  3
-#define TMMSM0  4
-#define TMMSM1  5
-#define TMMSM2  6
-
-/* Combine TMCRL and TMCRH */
-#define TMCR    _SFR_MEM16(0x121)
-
-#define TMCRL   _SFR_MEM8(0x121)
-#define TMCRH   _SFR_MEM8(0x122)
-
-#define TMCSB   _SFR_MEM8(0x123)
-
-/* Combine TMCIL and TMCIH */
-#define TMCI    _SFR_MEM16(0x124)
-
-#define TMCIL   _SFR_MEM8(0x124)
-#define TMCIH   _SFR_MEM8(0x125)
-
-/* Combine TMCPL and TMCPH */
-#define TMCP    _SFR_MEM16(0x126)
-
-#define TMCPL   _SFR_MEM8(0x126)
-#define TMCPH   _SFR_MEM8(0x127)
-
-#define TMSHR   _SFR_MEM8(0x128)
-
-/* Combine TMTLL and TMTLH */
-#define TMTL    _SFR_MEM16(0x129)
-
-#define TMTLL   _SFR_MEM8(0x129)
-#define TMTLH   _SFR_MEM8(0x12A)
-
-#define TMSSC   _SFR_MEM8(0x12B)
-#define TMSSP0  0
-#define TMSSP1  1
-#define TMSSP2  2
-#define TMSSP3  3
-#define TMSSL0  4
-#define TMSSL1  5
-#define TMSSL2  6
-#define TMSSH   7
-
-#define TMSR    _SFR_MEM8(0x12C)
-#define TMTCF   0
-
-#define TMCR2   _SFR_MEM8(0x12D)
-#define TMCRCE  0
-#define TMCRCL0 1
-#define TMCRCL1 2
-#define TMNRZE  3
-#define TMPOL   4
-#define TMSSE   5
-#define TMMSB   6
-
-#define TMCR1   _SFR_MEM8(0x12E)
-#define TMPIS0  0
-#define TMPIS1  1
-#define TMPIS2  2
-#define TMSCS   3
-#define TMCIM   4
-
-#define RXBC1   _SFR_MEM8(0x12F)
-#define RXCEA   0
-#define RXCBLA0 1
-#define RXCBLA1 2
-#define RXMSBA  3
-#define RXCEB   4
-#define RXCBLB0 5
-#define RXCBLB1 6
-#define RXMSBB  7
-
-#define RXBC2   _SFR_MEM8(0x130)
-#define RXBPB   0
-#define RXBF    1
-#define RXBCLR  2
-
-#define RXTLLB  _SFR_MEM8(0x131)
-
-#define RXTLHB  _SFR_MEM8(0x132)
-#define RXTLHB0 0
-#define RXTLHB1 1
-#define RXTLHB2 2
-#define RXTLHB3 3
-
-#define RXCRLB  _SFR_MEM8(0x133)
-
-#define RXCRHB  _SFR_MEM8(0x134)
-
-#define RXCSBB  _SFR_MEM8(0x135)
-
-#define RXCILB  _SFR_MEM8(0x136)
-
-#define RXCIHB  _SFR_MEM8(0x137)
-
-#define RXCPLB  _SFR_MEM8(0x138)
-
-#define RXCPHB  _SFR_MEM8(0x139)
-
-#define RXDSB   _SFR_MEM8(0x13A)
-
-#define RXTLLA  _SFR_MEM8(0x13B)
-
-#define RXTLHA  _SFR_MEM8(0x13C)
-#define RXTLHA0 0
-#define RXTLHA1 1
-#define RXTLHA2 2
-#define RXTLHA3 3
-
-#define RXCRLA  _SFR_MEM8(0x13D)
-
-#define RXCRHA  _SFR_MEM8(0x13E)
-
-#define RXCSBA  _SFR_MEM8(0x13F)
-
-#define RXCILA  _SFR_MEM8(0x140)
-
-#define RXCIHA  _SFR_MEM8(0x141)
-
-#define RXCPLA  _SFR_MEM8(0x142)
-
-#define RXCPHA  _SFR_MEM8(0x143)
-
-#define RXDSA   _SFR_MEM8(0x144)
-
-#define CRCCR   _SFR_MEM8(0x145)
-#define CRCRS   0
-#define REFLI   1
-#define REFLO   2
-
-#define CRCDOR  _SFR_MEM8(0x146)
-
-#define IDB0    _SFR_MEM8(0x147)
-
-#define IDB1    _SFR_MEM8(0x148)
-
-#define IDB2    _SFR_MEM8(0x149)
-
-#define IDB3    _SFR_MEM8(0x14A)
-
-#define IDC     _SFR_MEM8(0x14B)
-#define IDL0    0
-#define IDL1    1
-#define IDBO0   2
-#define IDBO1   3
-#define IDFIM   5
-#define IDCLR   6
-#define IDCE    7
-
-#define IDS     _SFR_MEM8(0x14C)
-#define IDOK    0
-#define IDFULL  1
-
-#define RSSAV   _SFR_MEM8(0x14D)
-
-#define RSSPK   _SFR_MEM8(0x14E)
-
-#define RSSL    _SFR_MEM8(0x14F)
-
-#define RSSH    _SFR_MEM8(0x150)
-
-#define RSSC    _SFR_MEM8(0x151)
-#define RSUP0   0
-#define RSUP1   1
-#define RSUP2   2
-#define RSUP3   3
-#define RSWLH   4
-#define RSHRX   5
-#define RSPKF   6
-
-#define DBCR    _SFR_MEM8(0x152)
-#define DBMD    0
-#define DBCS    1
-#define DBTMS   2
-#define DBHA    3
-
-#define DBTC    _SFR_MEM8(0x153)
-
-#define DBENB   _SFR_MEM8(0x154)
-
-#define DBENC   _SFR_MEM8(0x155)
-
-#define DBGSW   _SFR_MEM8(0x156)
-#define DBGGS0  0
-#define DBGGS1  1
-#define DBGGS2  2
-#define DBGGS3  3
-#define CPBFOS0 4
-#define CPBFOS1 5
-#define CPBF    6
-#define DBGSE   7
-
-#define SFFR    _SFR_MEM8(0x157)
-#define RFL0    0
-#define RFL1    1
-#define RFL2    2
-#define RFC     3
-#define TFL0    4
-#define TFL1    5
-#define TFL2    6
-#define TFC     7
-
-#define SFIR    _SFR_MEM8(0x158)
-#define RIL0    0
-#define RIL1    1
-#define RIL2    2
-#define SRIE    3
-#define TIL0    4
-#define TIL1    5
-#define TIL2    6
-#define STIE    7
-
-#define EECR2   _SFR_MEM8(0x159)
-#define EEBRE   0
-
-#define PGMST   _SFR_MEM8(0x15A)
-#define PGMSYN0 0
-#define PGMSYN1 1
-#define PGMSYN2 2
-#define PGMSYN3 3
-#define PGMSYN4 4
-
-#define EEST    _SFR_MEM8(0x15B)
-#define EESYN0  0
-#define EESYN1  1
-#define EESYN2  2
-#define EESYN3  3
-
-#define RSIFG   _SFR_MEM8(0x15C)
-
-#define RSLDV   _SFR_MEM8(0x15D)
-
-#define RSHDV   _SFR_MEM8(0x15E)
-
-#define RSCOM   _SFR_MEM8(0x15F)
-#define RSDC    0
-#define RSIFC   1
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCI0_vect            _VECTOR(3)
-#define PCI0_vect_num        3
-
-/* Pin Change Interrupt Request 1 */
-#define PCI1_vect            _VECTOR(4)
-#define PCI1_vect_num        4
-
-/* Voltage Monitoring Interrupt */
-#define VMON_vect            _VECTOR(5)
-#define VMON_vect_num        5
-
-/* AVCC Reset Interrupt */
-#define AVCCR_vect            _VECTOR(6)
-#define AVCCR_vect_num        6
-
-/* AVCC Low Interrupt */
-#define AVCCL_vect            _VECTOR(7)
-#define AVCCL_vect_num        7
-
-/* Timer 0 Interval Interrupt */
-#define T0INT_vect            _VECTOR(8)
-#define T0INT_vect_num        8
-
-/* Timer/Counter1 Compare Match Interrupt */
-#define T1COMP_vect            _VECTOR(9)
-#define T1COMP_vect_num        9
-
-/* Timer/Counter1 Overflow Interrupt */
-#define T1OVF_vect            _VECTOR(10)
-#define T1OVF_vect_num        10
-
-/* Timer/Counter2 Compare Match Interrupt */
-#define T2COMP_vect            _VECTOR(11)
-#define T2COMP_vect_num        11
-
-/* Timer/Counter2 Overflow Interrupt */
-#define T2OVF_vect            _VECTOR(12)
-#define T2OVF_vect_num        12
-
-/* Timer/Counter3 Capture Event Interrupt */
-#define T3CAP_vect            _VECTOR(13)
-#define T3CAP_vect_num        13
-
-/* Timer/Counter3 Compare Match Interrupt */
-#define T3COMP_vect            _VECTOR(14)
-#define T3COMP_vect_num        14
-
-/* Timer/Counter3 Overflow Interrupt */
-#define T3OVF_vect            _VECTOR(15)
-#define T3OVF_vect_num        15
-
-/* Timer/Counter4 Capture Event Interrupt */
-#define T4CAP_vect            _VECTOR(16)
-#define T4CAP_vect_num        16
-
-/* Timer/Counter4 Compare Match Interrupt */
-#define T4COMP_vect            _VECTOR(17)
-#define T4COMP_vect_num        17
-
-/* Timer/Counter4 Overflow Interrupt */
-#define T4OVF_vect            _VECTOR(18)
-#define T4OVF_vect_num        18
-
-/* Timer/Counter5 Compare Match Interrupt */
-#define T5COMP_vect            _VECTOR(19)
-#define T5COMP_vect_num        19
-
-/* Timer/Counter5 Overflow Interrupt */
-#define T5OVF_vect            _VECTOR(20)
-#define T5OVF_vect_num        20
-
-/* SPI Serial Transfer Complete Interrupt */
-#define SPI_vect            _VECTOR(21)
-#define SPI_vect_num        21
-
-/* SPI Rx Buffer Interrupt */
-#define SRX_FIFO_vect            _VECTOR(22)
-#define SRX_FIFO_vect_num        22
-
-/* SPI Tx Buffer Interrupt */
-#define STX_FIFO_vect            _VECTOR(23)
-#define STX_FIFO_vect_num        23
-
-/* Sequencer State Machine Interrupt */
-#define SSM_vect            _VECTOR(24)
-#define SSM_vect_num        24
-
-/* Data FIFO fill level reached Interrupt */
-#define DFFLR_vect            _VECTOR(25)
-#define DFFLR_vect_num        25
-
-/* Data FIFO overflow or underflow error Interrupt */
-#define DFOUE_vect            _VECTOR(26)
-#define DFOUE_vect_num        26
-
-/* RSSI/Preamble FIFO fill level reached Interrupt */
-#define SFFLR_vect            _VECTOR(27)
-#define SFFLR_vect_num        27
-
-/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
-#define SFOUE_vect            _VECTOR(28)
-#define SFOUE_vect_num        28
-
-/* Tx Modulator Telegram Finish Interrupt */
-#define TMTCF_vect            _VECTOR(29)
-#define TMTCF_vect_num        29
-
-/* UHF receiver wake up ok on Rx path B */
-#define UHF_WCOB_vect            _VECTOR(30)
-#define UHF_WCOB_vect_num        30
-
-/* UHF receiver wake up ok on Rx path A */
-#define UHF_WCOA_vect            _VECTOR(31)
-#define UHF_WCOA_vect_num        31
-
-/* UHF receiver start of telegram ok on Rx path B */
-#define UHF_SOTB_vect            _VECTOR(32)
-#define UHF_SOTB_vect_num        32
-
-/* UHF receiver start of telegram ok on Rx path A */
-#define UHF_SOTA_vect            _VECTOR(33)
-#define UHF_SOTA_vect_num        33
-
-/* UHF receiver end of telegram on Rx path B */
-#define UHF_EOTB_vect            _VECTOR(34)
-#define UHF_EOTB_vect_num        34
-
-/* UHF receiver end of telegram on Rx path A */
-#define UHF_EOTA_vect            _VECTOR(35)
-#define UHF_EOTA_vect_num        35
-
-/* UHF receiver new bit on Rx path B */
-#define UHF_NBITB_vect            _VECTOR(36)
-#define UHF_NBITB_vect_num        36
-
-/* UHF receiver new bit on Rx path A */
-#define UHF_NBITA_vect            _VECTOR(37)
-#define UHF_NBITA_vect_num        37
-
-/* External input Clock monitoring Interrupt */
-#define EXCM_vect            _VECTOR(38)
-#define EXCM_vect_num        38
-
-/* EEPROM Ready Interrupt */
-#define ERDY_vect            _VECTOR(39)
-#define ERDY_vect_num        39
-
-/* Store Program Memory Ready */
-#define SPMR_vect            _VECTOR(40)
-#define SPMR_vect_num        40
-
-/* IDSCAN Full Interrupt */
-#define IDFULL_vect            _VECTOR(41)
-#define IDFULL_vect_num        41
-
-#define _VECTORS_SIZE 168
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x8000
-#define FLASHEND     0xCFFF
-#define RAMSTART     0x0200
-#define RAMSIZE      1024
-#define RAMEND       0x05FF
-#define E2START     0
-#define E2SIZE      1024
-#define E2PAGESIZE  16
-#define E2END       0x03FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Fuse Byte */
-#define FUSE_EXTCLKEN    (unsigned char)~_BV(0)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(1)
-#define FUSE_BOOTRST     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x61
-
-
-#endif /* #ifdef _AVR_ATA5831_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5831_H_INCLUDED
+#define _AVR_ATA5831_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5831.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PRR0    _SFR_IO8(0x01)
+#define PRSPI   0
+#define PRRXDC  1
+#define PRTXDC  2
+#define PRCRC   3
+#define PRVM    4
+#define PRCO    5
+
+#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRRXDC)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO))
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRRXDC
+#define __AVR_HAVE_PRR0_PRTXDC
+#define __AVR_HAVE_PRR0_PRCRC
+#define __AVR_HAVE_PRR0_PRVM
+#define __AVR_HAVE_PRR0_PRCO
+
+#define PRR1    _SFR_IO8(0x02)
+#define PRT1    0
+#define PRT2    1
+#define PRT3    2
+#define PRT4    3
+#define PRT5    4
+
+#define __AVR_HAVE_PRR1	((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5))
+#define __AVR_HAVE_PRR1_PRT1
+#define __AVR_HAVE_PRR1_PRT2
+#define __AVR_HAVE_PRR1_PRT3
+#define __AVR_HAVE_PRR1_PRT4
+#define __AVR_HAVE_PRR1_PRT5
+
+#define PRR2    _SFR_IO8(0x03)
+#define PRXB    0
+#define PRXA    1
+#define PRSF    2
+#define PRDF    3
+#define PRIDS   4
+#define PRRS    5
+#define PRTM    6
+#define PRSSM   7
+
+#define __AVR_HAVE_PRR2	((1<<PRXB)|(1<<PRXA)|(1<<PRSF)|(1<<PRDF)|(1<<PRIDS)|(1<<PRRS)|(1<<PRTM)|(1<<PRSSM))
+#define __AVR_HAVE_PRR2_PRXB
+#define __AVR_HAVE_PRR2_PRXA
+#define __AVR_HAVE_PRR2_PRSF
+#define __AVR_HAVE_PRR2_PRDF
+#define __AVR_HAVE_PRR2_PRIDS
+#define __AVR_HAVE_PRR2_PRRS
+#define __AVR_HAVE_PRR2_PRTM
+#define __AVR_HAVE_PRR2_PRSSM
+
+#define RDPR    _SFR_IO8(0x04)
+#define PRPTB   0
+#define PRPTA   1
+#define PRFLT   2
+#define PRTMP   3
+#define APRPTB  4
+#define APRPTA  5
+#define ARDPRF  6
+#define RDPRF   7
+
+#define PINB    _SFR_IO8(0x05)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x06)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x07)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x08)
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x09)
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x0A)
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define FSCR    _SFR_IO8(0x0B)
+#define TXMOD   0
+#define SFM     1
+#define TXMS0   2
+#define TXMS1   3
+#define PAOER   4
+#define PAON    7
+
+/* Reserved [0x0C] */
+
+#define RDSIFR  _SFR_IO8(0x0D)
+#define NBITA   0
+#define NBITB   1
+#define EOTA    2
+#define EOTB    3
+#define SOTA    4
+#define SOTB    5
+#define WCOA    6
+#define WCOB    7
+
+#define MCUCR   _SFR_IO8(0x0E)
+#define IVCE    0
+#define IVSEL   1
+#define SPIIO   2
+#define ENPS    3
+#define PUD     4
+#define PB4HS   5
+#define PB7LS   6
+#define PB7HS   7
+
+#define PCIFR   _SFR_IO8(0x0F)
+#define PCIF0   0
+#define PCIF1   1
+
+#define T0CR    _SFR_IO8(0x10)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+#define T1CR    _SFR_IO8(0x11)
+#define T1OTM   0
+#define T1CTM   1
+#define T1CRM   2
+#define T1TOP   4
+#define T1RES   5
+#define T1TOS   6
+#define T1ENA   7
+
+#define T2CR    _SFR_IO8(0x12)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2TOP   4
+#define T2RES   5
+#define T2TOS   6
+#define T2ENA   7
+
+#define T3CR    _SFR_IO8(0x13)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3TOS   6
+#define T3ENA   7
+
+#define T4CR    _SFR_IO8(0x14)
+#define T4OTM   0
+#define T4CTM   1
+#define T4CRM   2
+#define T4CPRM  3
+#define T4TOP   4
+#define T4RES   5
+#define T4TOS   6
+#define T4ENA   7
+
+#define T1IFR   _SFR_IO8(0x15)
+#define T1OFF   0
+#define T1COF   1
+
+#define T2IFR   _SFR_IO8(0x16)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x17)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+
+#define T4IFR   _SFR_IO8(0x18)
+#define T4OFF   0
+#define T4COF   1
+#define T4ICF   2
+
+#define T5IFR   _SFR_IO8(0x19)
+#define T5OFF   0
+#define T5COF   1
+
+#define GPIOR0  _SFR_IO8(0x1A)
+
+#define GPIOR3  _SFR_IO8(0x1B)
+
+#define GPIOR4  _SFR_IO8(0x1C)
+
+#define GPIOR5  _SFR_IO8(0x1D)
+
+#define GPIOR6  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EEPAGE  6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define GPIOR1  _SFR_IO8(0x24)
+
+#define GPIOR2  _SFR_IO8(0x25)
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+#define INT1    1
+
+#define EIFR    _SFR_IO8(0x28)
+#define INTF0   0
+#define INTF1   1
+
+#define CRCDIR  _SFR_IO8(0x29)
+
+#define VMCSR   _SFR_IO8(0x2A)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMF     5
+
+#define MCUSR   _SFR_IO8(0x2B)
+#define PORF    0
+#define EXTRF   1
+#define WDRF    3
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define RXIF    4
+#define TXIF    5
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define T0IFR   _SFR_IO8(0x2F)
+#define T0F     0
+
+/* Reserved [0x30] */
+
+#define DWDR    _SFR_IO8(0x31)
+
+/* Reserved [0x32] */
+
+#define RDCR    _SFR_IO8(0x33)
+#define RDPU    0
+#define ADIVEN  1
+#define RDEN    2
+
+#define EOTSA   _SFR_IO8(0x34)
+#define CARFA   0
+#define AMPFA   1
+#define SYTFA   2
+#define MANFA   3
+#define TMOFA   4
+#define TELRA   5
+#define RRFA    6
+#define EOTBF   7
+
+#define EOTCA   _SFR_IO8(0x35)
+#define CARFEA  0
+#define AMPFEA  1
+#define SYTFEA  2
+#define MANFEA  3
+#define TMOFEA  4
+#define TELREA  5
+#define RRFEA   6
+#define EOTBFE  7
+
+#define EOTSB   _SFR_IO8(0x36)
+#define CARFB   0
+#define AMPFB   1
+#define SYTFB   2
+#define MANFB   3
+#define TMOFB   4
+#define TELRB   5
+#define RRFB    6
+#define EOTAF   7
+
+#define EOTCB   _SFR_IO8(0x37)
+#define CARFEB  0
+#define AMPFEB  1
+#define SYTFEB  2
+#define MANFEB  3
+#define TMOFEB  4
+#define TELREB  5
+#define RRFEB   6
+#define EOTAFE  7
+
+#define SMCR    _SFR_IO8(0x38)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define CMCR    _SFR_IO8(0x39)
+#define CMM0    0
+#define CMM1    1
+#define CMM2    2
+#define CCS     3
+#define SRCD    4
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMIMR   _SFR_IO8(0x3A)
+#define ECIE    0
+
+#define CLPR    _SFR_IO8(0x3B)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLPCE   7
+
+#define SPMCSR  _SFR_IO8(0x3C)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define SPMIE   7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define FSEN    _SFR_MEM8(0x60)
+#define SDPU    0
+#define SDEN    1
+#define GAEN    2
+#define PEEN    3
+#define ASEN    4
+#define ANTT    5
+
+#define FSFCR   _SFR_MEM8(0x61)
+#define BTSEL0  0
+#define BTSEL1  1
+#define ASDIV0  4
+#define ASDIV1  5
+#define ASDIV2  6
+#define ASDIV3  7
+
+/* Combine GACDIVL and GACDIVH */
+#define GACDIV  _SFR_MEM16(0x62)
+
+#define GACDIVL _SFR_MEM8(0x62)
+#define GACDIVH _SFR_MEM8(0x63)
+
+#define FFREQ1L _SFR_MEM8(0x64)
+
+#define FFREQ1M _SFR_MEM8(0x65)
+
+#define FFREQ1H _SFR_MEM8(0x66)
+
+#define FFREQ2L _SFR_MEM8(0x67)
+
+#define FFREQ2M _SFR_MEM8(0x68)
+
+#define FFREQ2H _SFR_MEM8(0x69)
+
+/* Reserved [0x6A] */
+
+#define EICRA   _SFR_MEM8(0x6B)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+#define PCMSK0  _SFR_MEM8(0x6C)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6D)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+
+#define WDTCR   _SFR_MEM8(0x6E)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+#define T1CNT   _SFR_MEM8(0x6F)
+
+#define T1COR   _SFR_MEM8(0x70)
+
+#define T1MR    _SFR_MEM8(0x71)
+#define T1CS0   0
+#define T1CS1   1
+#define T1PS0   2
+#define T1PS1   3
+#define T1PS2   4
+#define T1PS3   5
+#define T1DC0   6
+#define T1DC1   7
+
+#define T1IMR   _SFR_MEM8(0x72)
+#define T1OIM   0
+#define T1CIM   1
+
+#define T2CNT   _SFR_MEM8(0x73)
+
+#define T2COR   _SFR_MEM8(0x74)
+
+#define T2MR    _SFR_MEM8(0x75)
+#define T2CS0   0
+#define T2CS1   1
+#define T2PS0   2
+#define T2PS1   3
+#define T2PS2   4
+#define T2PS3   5
+#define T2DC0   6
+#define T2DC1   7
+
+#define T2IMR   _SFR_MEM8(0x76)
+#define T2OIM   0
+#define T2CIM   1
+
+/* Combine T3CNTL and T3CNTH */
+#define T3CNT   _SFR_MEM16(0x77)
+
+#define T3CNTL  _SFR_MEM8(0x77)
+#define T3CNTH  _SFR_MEM8(0x78)
+
+/* Combine T3CORL and T3CORH */
+#define T3COR   _SFR_MEM16(0x79)
+
+#define T3CORL  _SFR_MEM8(0x79)
+#define T3CORH  _SFR_MEM8(0x7A)
+
+/* Combine T3ICRL and T3ICRH */
+#define T3ICR   _SFR_MEM16(0x7B)
+
+#define T3ICRL  _SFR_MEM8(0x7B)
+#define T3ICRH  _SFR_MEM8(0x7C)
+
+#define T3MRA   _SFR_MEM8(0x7D)
+#define T3CS0   0
+#define T3CS1   1
+#define T3PS0   2
+#define T3PS1   3
+#define T3PS2   4
+
+#define T3MRB   _SFR_MEM8(0x7E)
+#define T3SCE   1
+#define T3CNC   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3ICS0  5
+#define T3ICS1  6
+#define T3ICS2  7
+
+#define T3IMR   _SFR_MEM8(0x7F)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+
+/* Combine T4CNTL and T4CNTH */
+#define T4CNT   _SFR_MEM16(0x80)
+
+#define T4CNTL  _SFR_MEM8(0x80)
+#define T4CNTH  _SFR_MEM8(0x81)
+
+/* Combine T4CORL and T4CORH */
+#define T4COR   _SFR_MEM16(0x82)
+
+#define T4CORL  _SFR_MEM8(0x82)
+#define T4CORH  _SFR_MEM8(0x83)
+
+/* Combine T4ICRL and T4ICRH */
+#define T4ICR   _SFR_MEM16(0x84)
+
+#define T4ICRL  _SFR_MEM8(0x84)
+#define T4ICRH  _SFR_MEM8(0x85)
+
+#define T4MRA   _SFR_MEM8(0x86)
+#define T4CS0   0
+#define T4CS1   1
+#define T4PS0   2
+#define T4PS1   3
+#define T4PS2   4
+
+#define T4MRB   _SFR_MEM8(0x87)
+#define T4SCE   1
+#define T4CNC   2
+#define T4CE0   3
+#define T4CE1   4
+#define T4ICS0  5
+#define T4ICS1  6
+#define T4ICS2  7
+
+#define T4IMR   _SFR_MEM8(0x88)
+#define T4OIM   0
+#define T4CIM   1
+#define T4CPIM  2
+
+/* Reserved [0x89] */
+
+/* Combine T5OCRL and T5OCRH */
+#define T5OCR   _SFR_MEM16(0x8A)
+
+#define T5OCRL  _SFR_MEM8(0x8A)
+#define T5OCRH  _SFR_MEM8(0x8B)
+
+#define T5CCR   _SFR_MEM8(0x8C)
+#define T5CS0   0
+#define T5CS1   1
+#define T5CS2   2
+#define T5CTC   3
+
+/* Combine T5CNTL and T5CNTH */
+#define T5CNT   _SFR_MEM16(0x8D)
+
+#define T5CNTL  _SFR_MEM8(0x8D)
+#define T5CNTH  _SFR_MEM8(0x8E)
+
+#define T5IMR   _SFR_MEM8(0x8F)
+#define T5OIM   0
+#define T5CIM   1
+
+#define GTCCR   _SFR_MEM8(0x90)
+#define PSR10   0
+#define TSM     7
+
+#define SOTSB   _SFR_MEM8(0x91)
+#define CAROB   0
+#define AMPOB   1
+#define SYTOB   2
+#define MANOB   3
+#define WUPOB   4
+#define SFIDOB  5
+#define RROB    6
+#define WCOAO   7
+
+#define SOTSA   _SFR_MEM8(0x92)
+#define CAROA   0
+#define AMPOA   1
+#define SYTOA   2
+#define MANOA   3
+#define WUPOA   4
+#define SFIDOA  5
+#define RROA    6
+#define WCOBO   7
+
+#define SOTCB   _SFR_MEM8(0x93)
+#define CAROEB  0
+#define AMPOEB  1
+#define SYTOEB  2
+#define MANOEB  3
+#define WUPEB   4
+#define SFIDEB  5
+#define RROEB   6
+#define WCOAOE  7
+
+#define SOTCA   _SFR_MEM8(0x94)
+#define CAROEA  0
+#define AMPOEA  1
+#define SYTOEA  2
+#define MANOEA  3
+#define WUPEA   4
+#define SFIDEA  5
+#define RROEA   6
+#define WCOBOE  7
+
+#define TESRB   _SFR_MEM8(0x95)
+#define CRCOB   0
+#define EOTLB0  1
+#define EOTLB1  2
+
+#define TESRA   _SFR_MEM8(0x96)
+#define CRCOA   0
+#define EOTLA0  1
+#define EOTLA1  2
+
+/* Reserved [0x97] */
+
+#define RDSIMR  _SFR_MEM8(0x98)
+#define NBITAM  0
+#define NBITBM  1
+#define EOTAM   2
+#define EOTBM   3
+#define SOTAM   4
+#define SOTBM   5
+#define WCOAM   6
+#define WCOBM   7
+
+#define RDOCR   _SFR_MEM8(0x99)
+#define TMDS0   1
+#define TMDS1   2
+#define ETRPA   3
+#define ETRPB   4
+#define RDSIDA  5
+#define RDSIDB  6
+
+/* Reserved [0x9A] */
+
+#define TEMPL   _SFR_MEM8(0x9B)
+
+#define TEMPH   _SFR_MEM8(0x9C)
+
+#define SYCB    _SFR_MEM8(0x9D)
+#define SYCSB0  0
+#define SYCSB1  1
+#define SYCSB2  2
+#define SYCSB3  3
+#define SYTLB0  4
+#define SYTLB1  5
+#define SYTLB2  6
+#define SYTLB3  7
+
+#define SYCA    _SFR_MEM8(0x9E)
+#define SYCSA0  0
+#define SYCSA1  1
+#define SYCSA2  2
+#define SYCSA3  3
+#define SYTLA0  4
+#define SYTLA1  5
+#define SYTLA2  6
+#define SYTLA3  7
+
+#define RXFOB   _SFR_MEM8(0x9F)
+
+#define RXFOA   _SFR_MEM8(0xA0)
+
+#define DMMB    _SFR_MEM8(0xA1)
+#define DMATB0  0
+#define DMATB1  1
+#define DMATB2  2
+#define DMATB3  3
+#define DMATB4  4
+#define DMPB    5
+#define DMHB    6
+#define DMNEB   7
+
+#define DMMA    _SFR_MEM8(0xA2)
+#define DMATA0  0
+#define DMATA1  1
+#define DMATA2  2
+#define DMATA3  3
+#define DMATA4  4
+#define DMPA    5
+#define DMHA    6
+#define DMNEA   7
+
+#define DMCDB   _SFR_MEM8(0xA3)
+#define DMCLB0  0
+#define DMCLB1  1
+#define DMCLB2  2
+#define DMCLB3  3
+#define DMCLB4  4
+#define DMCTB0  5
+#define DMCTB1  6
+#define DMCTB2  7
+
+#define DMCDA   _SFR_MEM8(0xA4)
+#define DMCLA0  0
+#define DMCLA1  1
+#define DMCLA2  2
+#define DMCLA3  3
+#define DMCLA4  4
+#define DMCTA0  5
+#define DMCTA1  6
+#define DMCTA2  7
+
+#define DMCRB   _SFR_MEM8(0xA5)
+#define DMPGB0  0
+#define DMPGB1  1
+#define DMPGB2  2
+#define DMPGB3  3
+#define DMPGB4  4
+#define SASKB   5
+#define SY1TB   6
+#define DMARB   7
+
+#define DMCRA   _SFR_MEM8(0xA6)
+#define DMPGA0  0
+#define DMPGA1  1
+#define DMPGA2  2
+#define DMPGA3  3
+#define DMPGA4  4
+#define SASKA   5
+#define SY1TA   6
+#define DMARA   7
+
+#define DMDRB   _SFR_MEM8(0xA7)
+#define DMAB0   0
+#define DMAB1   1
+#define DMAB2   2
+#define DMAB3   3
+#define DMDNB0  4
+#define DMDNB1  5
+#define DMDNB2  6
+#define DMDNB3  7
+
+#define DMDRA   _SFR_MEM8(0xA8)
+#define DMAA0   0
+#define DMAA1   1
+#define DMAA2   2
+#define DMAA3   3
+#define DMDNA0  4
+#define DMDNA1  5
+#define DMDNA2  6
+#define DMDNA3  7
+
+#define CHCR    _SFR_MEM8(0xA9)
+#define BWM0    0
+#define BWM1    1
+#define BWM2    2
+#define BWM3    3
+
+#define CHDN    _SFR_MEM8(0xAA)
+#define BBDN0   0
+#define BBDN1   1
+#define BBDN2   2
+#define BBDN3   3
+#define BBDN4   4
+#define ADCDN   5
+
+#define SFIDCB  _SFR_MEM8(0xAB)
+#define SFIDTB0 0
+#define SFIDTB1 1
+#define SFIDTB2 2
+#define SFIDTB3 3
+#define SFIDTB4 4
+#define SEMEB   7
+
+#define SFIDLB  _SFR_MEM8(0xAC)
+#define SFIDLB0 0
+#define SFIDLB1 1
+#define SFIDLB2 2
+#define SFIDLB3 3
+#define SFIDLB4 4
+#define SFIDLB5 5
+
+#define WUPTB   _SFR_MEM8(0xAD)
+#define WUPTB0  0
+#define WUPTB1  1
+#define WUPTB2  2
+#define WUPTB3  3
+#define WUPTB4  4
+
+#define WUPLB   _SFR_MEM8(0xAE)
+#define WUPLB0  0
+#define WUPLB1  1
+#define WUPLB2  2
+#define WUPLB3  3
+#define WUPLB4  4
+#define WUPLB5  5
+
+#define SFID1B  _SFR_MEM8(0xAF)
+
+#define SFID2B  _SFR_MEM8(0xB0)
+
+#define SFID3B  _SFR_MEM8(0xB1)
+
+#define SFID4B  _SFR_MEM8(0xB2)
+
+#define WUP1B   _SFR_MEM8(0xB3)
+
+#define WUP2B   _SFR_MEM8(0xB4)
+
+#define WUP3B   _SFR_MEM8(0xB5)
+
+#define WUP4B   _SFR_MEM8(0xB6)
+
+#define SFIDCA  _SFR_MEM8(0xB7)
+#define SFIDTA0 0
+#define SFIDTA1 1
+#define SFIDTA2 2
+#define SFIDTA3 3
+#define SFIDTA4 4
+#define SEMEA   7
+
+#define SFIDLA  _SFR_MEM8(0xB8)
+#define SFIDLA0 0
+#define SFIDLA1 1
+#define SFIDLA2 2
+#define SFIDLA3 3
+#define SFIDLA4 4
+#define SFIDLA5 5
+
+#define WUPTA   _SFR_MEM8(0xB9)
+#define WUPTA0  0
+#define WUPTA1  1
+#define WUPTA2  2
+#define WUPTA3  3
+#define WUPTA4  4
+
+#define WUPLA   _SFR_MEM8(0xBA)
+#define WUPLA0  0
+#define WUPLA1  1
+#define WUPLA2  2
+#define WUPLA3  3
+#define WUPLA4  4
+#define WUPLA5  5
+
+#define SFID1A  _SFR_MEM8(0xBB)
+
+#define SFID2A  _SFR_MEM8(0xBC)
+
+#define SFID3A  _SFR_MEM8(0xBD)
+
+#define SFID4A  _SFR_MEM8(0xBE)
+
+#define WUP1A   _SFR_MEM8(0xBF)
+
+#define WUP2A   _SFR_MEM8(0xC0)
+
+#define WUP3A   _SFR_MEM8(0xC1)
+
+#define WUP4A   _SFR_MEM8(0xC2)
+
+#define CLKOD   _SFR_MEM8(0xC3)
+
+#define CLKOCR  _SFR_MEM8(0xC4)
+#define CLKOS0  0
+#define CLKOS1  1
+#define CLKOEN  2
+
+#define XFUSE   _SFR_MEM8(0xC5)
+
+#define SRCCAL  _SFR_MEM8(0xC6)
+#define SRCCAL0 0
+#define SRCCAL1 1
+#define SRCCAL2 2
+#define SRCCAL3 3
+#define SRCCAL4 4
+#define SRCCAL5 5
+#define SRCTC0  6
+#define SRCTC1  7
+
+#define FRCCAL  _SFR_MEM8(0xC7)
+#define FRCCAL0 0
+#define FRCCAL1 1
+#define FRCCAL2 2
+#define FRCCAL3 3
+#define FRCCAL4 4
+#define FRCTC   5
+
+#define CMSR    _SFR_MEM8(0xC8)
+#define ECF     0
+
+#define CMOCR   _SFR_MEM8(0xC9)
+#define FRCAO   0
+#define SRCAO   1
+#define FRCACT  2
+#define SRCACT  3
+
+#define SUPFR   _SFR_MEM8(0xCA)
+#define AVCCRF  0
+#define AVCCLF  1
+
+#define SUPCR   _SFR_MEM8(0xCB)
+#define AVCCRM  0
+#define AVCCLM  1
+#define PVEN    2
+#define DVDIS   4
+#define AVEN    5
+#define AVDIC   6
+
+#define SUPCA1  _SFR_MEM8(0xCC)
+#define PV22    2
+#define PVDIC   3
+#define PVCAL0  4
+#define PVCAL1  5
+#define PVCAL2  6
+#define PVCAL3  7
+
+#define SUPCA2  _SFR_MEM8(0xCD)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL3  3
+
+#define SUPCA3  _SFR_MEM8(0xCE)
+#define ACAL4   0
+#define ACAL5   1
+#define ACAL6   2
+#define ACAL7   3
+#define DCAL4   4
+#define DCAL5   5
+#define DCAL6   6
+
+#define SUPCA4  _SFR_MEM8(0xCF)
+#define ACAL0   0
+#define ACAL1   1
+#define ACAL2   2
+#define ACAL3   3
+#define DCAL0   4
+#define DCAL1   5
+#define DCAL2   6
+#define DCAL3   7
+
+#define CALRDY  _SFR_MEM8(0xD0)
+
+#define VMCAL   _SFR_MEM8(0xD1)
+#define VMCAL0  0
+#define VMCAL1  1
+#define VMCAL2  2
+
+#define DFS     _SFR_MEM8(0xD2)
+#define DFFLRF  0
+#define DFUFL   1
+#define DFOFL   2
+
+/* Combine DFTLL and DFTLH */
+#define DFTL    _SFR_MEM16(0xD3)
+
+#define DFTLL   _SFR_MEM8(0xD3)
+#define DFTLH   _SFR_MEM8(0xD4)
+
+#define DFL     _SFR_MEM8(0xD5)
+#define DFFLS0  0
+#define DFFLS1  1
+#define DFFLS2  2
+#define DFFLS3  3
+#define DFFLS4  4
+#define DFFLS5  5
+#define DFCLR   7
+
+#define DFWP    _SFR_MEM8(0xD6)
+#define DFWP0   0
+#define DFWP1   1
+#define DFWP2   2
+#define DFWP3   3
+#define DFWP4   4
+#define DFWP5   5
+
+#define DFRP    _SFR_MEM8(0xD7)
+#define DFRP0   0
+#define DFRP1   1
+#define DFRP2   2
+#define DFRP3   3
+#define DFRP4   4
+#define DFRP5   5
+
+#define DFD     _SFR_MEM8(0xD8)
+
+#define DFI     _SFR_MEM8(0xD9)
+#define DFFLIM  0
+#define DFERIM  1
+
+#define DFC     _SFR_MEM8(0xDA)
+#define DFFLC0  0
+#define DFFLC1  1
+#define DFFLC2  2
+#define DFFLC3  3
+#define DFFLC4  4
+#define DFFLC5  5
+#define DFDRA   7
+
+#define SFS     _SFR_MEM8(0xDB)
+#define SFFLRF  0
+#define SFUFL   1
+#define SFOFL   2
+
+#define SFL     _SFR_MEM8(0xDC)
+#define SFFLS0  0
+#define SFFLS1  1
+#define SFFLS2  2
+#define SFFLS3  3
+#define SFFLS4  4
+#define SFCLR   7
+
+#define SFWP    _SFR_MEM8(0xDD)
+#define SFWP0   0
+#define SFWP1   1
+#define SFWP2   2
+#define SFWP3   3
+#define SFWP4   4
+
+#define SFRP    _SFR_MEM8(0xDE)
+#define SFRP0   0
+#define SFRP1   1
+#define SFRP2   2
+#define SFRP3   3
+#define SFRP4   4
+
+#define SFD     _SFR_MEM8(0xDF)
+
+#define SFI     _SFR_MEM8(0xE0)
+#define SFFLIM  0
+#define SFERIM  1
+
+#define SFC     _SFR_MEM8(0xE1)
+#define SFFLC0  0
+#define SFFLC1  1
+#define SFFLC2  2
+#define SFFLC3  3
+#define SFFLC4  4
+#define SFDRA   7
+
+#define SSMCR   _SFR_MEM8(0xE2)
+#define SSMTX   0
+#define SSMTM   1
+#define SSMTGE  2
+#define SSMTPE  3
+#define SSMPVE  4
+#define SSMTAE  5
+#define SETRPA  6
+#define SETRPB  7
+
+#define SSMRCR  _SFR_MEM8(0xE3)
+#define SSMPA   0
+#define SSMPB   1
+#define SSMADA  2
+#define SSMADB  3
+#define SSMPVS  4
+#define SSMIFA  5
+#define SSMIDSE 6
+#define SSMTMOE 7
+
+#define SSMFBR  _SFR_MEM8(0xE4)
+#define SSMFID0 0
+#define SSMFID1 1
+#define SSMFID2 2
+#define SSMDFDT 3
+#define SSMHADT 4
+#define SSMPLDT 5
+
+#define SSMRR   _SFR_MEM8(0xE5)
+#define SSMR    0
+#define SSMST   1
+
+#define SSMSR   _SFR_MEM8(0xE6)
+#define SSMESM0 0
+#define SSMESM1 1
+#define SSMESM2 2
+#define SSMESM3 3
+#define SSMERR  7
+
+#define SSMIFR  _SFR_MEM8(0xE7)
+#define SSMIF   0
+
+#define SSMIMR  _SFR_MEM8(0xE8)
+#define SSMIM   0
+
+#define MSMSTR  _SFR_MEM8(0xE9)
+#define SSMMST0 0
+#define SSMMST1 1
+#define SSMMST2 2
+#define SSMMST3 3
+#define SSMMST4 4
+
+#define SSMSTR  _SFR_MEM8(0xEA)
+#define SSMSTA0 0
+#define SSMSTA1 1
+#define SSMSTA2 2
+#define SSMSTA3 3
+#define SSMSTA4 4
+#define SSMSTA5 5
+
+#define SSMXSR  _SFR_MEM8(0xEB)
+#define SSMSTB0 0
+#define SSMSTB1 1
+#define SSMSTB2 2
+#define SSMSTB3 3
+#define SSMSTB4 4
+#define SSMSTB5 5
+
+#define MSMCR1  _SFR_MEM8(0xEC)
+#define MSMSM00 0
+#define MSMSM01 1
+#define MSMSM02 2
+#define MSMSM03 3
+#define MSMSM10 4
+#define MSMSM11 5
+#define MSMSM12 6
+#define MSMSM13 7
+
+#define MSMCR2  _SFR_MEM8(0xED)
+#define MSMSM20 0
+#define MSMSM21 1
+#define MSMSM22 2
+#define MSMSM23 3
+#define MSMSM30 4
+#define MSMSM31 5
+#define MSMSM32 6
+#define MSMSM33 7
+
+#define MSMCR3  _SFR_MEM8(0xEE)
+#define MSMSM40 0
+#define MSMSM41 1
+#define MSMSM42 2
+#define MSMSM43 3
+#define MSMSM50 4
+#define MSMSM51 5
+#define MSMSM52 6
+#define MSMSM53 7
+
+#define MSMCR4  _SFR_MEM8(0xEF)
+#define MSMSM60 0
+#define MSMSM61 1
+#define MSMSM62 2
+#define MSMSM63 3
+#define MSMSM70 4
+#define MSMSM71 5
+#define MSMSM72 6
+#define MSMSM73 7
+
+#define GTCR    _SFR_MEM8(0xF0)
+#define RXTEHA  0
+#define GAPMA   1
+#define DARA    2
+#define IWUPA   3
+#define RXTEHB  4
+#define GAPMB   5
+#define DARB    6
+#define IWUPB   7
+
+#define SOTC1A  _SFR_MEM8(0xF1)
+#define CAROEA1 0
+#define AMPOEA1 1
+#define SYTOEA1 2
+#define MANOEA1 3
+#define WUPEA1  4
+#define SFIDEA1 5
+#define RROEA1  6
+#define WCOBOE1 7
+
+#define SOTC2A  _SFR_MEM8(0xF2)
+#define CAROEA2 0
+#define AMPOEA2 1
+#define SYTOEA2 2
+#define MANOEA2 3
+#define WUPEA2  4
+#define SFIDEA2 5
+#define RROEA2  6
+#define WCOBOE2 7
+
+#define SOTC1B  _SFR_MEM8(0xF3)
+#define CAROEB1 0
+#define AMPOEB1 1
+#define SYTOEB1 2
+#define MANOEB1 3
+#define WUPEB1  4
+#define SFIDEB1 5
+#define RROEB1  6
+#define WCOAOE1 7
+
+#define SOTC2B  _SFR_MEM8(0xF4)
+#define CAROEB2 0
+#define AMPOEB2 1
+#define SYTOEB2 2
+#define MANOEB2 3
+#define WUPEB2  4
+#define SFIDEB2 5
+#define RROEB2  6
+#define WCOAOE2 7
+
+#define EOTC1A  _SFR_MEM8(0xF5)
+#define CARFEA1 0
+#define AMPFEA1 1
+#define SYTFEA1 2
+#define MANFEA1 3
+#define TMOFEA1 4
+#define TELREA1 5
+#define RRFEA1  6
+#define EOTBFE1 7
+
+#define EOTC2A  _SFR_MEM8(0xF6)
+#define CARFEA2 0
+#define AMPFEA2 1
+#define SYTFEA2 2
+#define MANFEA2 3
+#define TMOFEA2 4
+#define TELREA2 5
+#define RRFEA2  6
+#define EOTBFE2 7
+
+#define EOTC3A  _SFR_MEM8(0xF7)
+#define CARFEA3 0
+#define AMPFEA3 1
+#define SYTFEA3 2
+#define MANFEA3 3
+#define TMOFEA3 4
+#define TELREA3 5
+#define RRFEA3  6
+#define EOTBFE3 7
+
+#define EOTC1B  _SFR_MEM8(0xF8)
+#define CARFEB1 0
+#define AMPFEB1 1
+#define SYTFEB1 2
+#define MANFEB1 3
+#define TMOFEB1 4
+#define TELREB1 5
+#define RRFEB1  6
+#define EOTAFE1 7
+
+#define EOTC2B  _SFR_MEM8(0xF9)
+#define CARFEB2 0
+#define AMPFEB2 1
+#define SYTFEB2 2
+#define MANFEB2 3
+#define TMOFEB2 4
+#define TELREB2 5
+#define RRFEB2  6
+#define EOTAFE2 7
+
+#define EOTC3B  _SFR_MEM8(0xFA)
+#define CARFEB3 0
+#define AMPFEB3 1
+#define SYTFEB3 2
+#define MANFEB3 3
+#define TMOFEB3 4
+#define TELREB3 5
+#define RRFEB3  6
+#define EOTAFE3 7
+
+#define WCOTOA  _SFR_MEM8(0xFB)
+
+#define WCOTOB  _SFR_MEM8(0xFC)
+
+#define SOTTOA  _SFR_MEM8(0xFD)
+
+#define SOTTOB  _SFR_MEM8(0xFE)
+
+#define SSMFCR  _SFR_MEM8(0xFF)
+#define SSMIDSO 0
+#define SSMIDSF 1
+
+#define FESR    _SFR_MEM8(0x100)
+#define LBSAT   0
+#define HBSAT   1
+#define XRDY    2
+#define PLCK    3
+#define ANTS    4
+
+#define FEEN1   _SFR_MEM8(0x101)
+#define PLEN    0
+#define PLCAL   1
+#define XTOEN   2
+#define LNAEN   3
+#define ADEN    4
+#define ADCLK   5
+#define PLSP1   6
+#define ATEN    7
+
+#define FEEN2   _SFR_MEM8(0x102)
+#define SDRX    0
+#define SDTX    1
+#define PAEN    2
+#define TMPM    3
+#define PLPEN   4
+#define XTPEN   5
+#define CPBIA   6
+
+#define FELNA   _SFR_MEM8(0x103)
+#define LBH0    0
+#define LBH1    1
+#define LBH2    2
+#define LBH3    3
+#define LBL0    4
+#define LBL1    5
+#define LBL2    6
+#define LBL3    7
+
+#define FEAT    _SFR_MEM8(0x104)
+#define ANTN0   0
+#define ANTN1   1
+#define ANTN2   2
+#define ANTN3   3
+
+#define FEPAC   _SFR_MEM8(0x105)
+
+#define FEVCT   _SFR_MEM8(0x106)
+#define FEVCT0  0
+#define FEVCT1  1
+#define FEVCT2  2
+#define FEVCT3  3
+
+#define FEBT    _SFR_MEM8(0x107)
+#define CTN20   0
+#define CTN21   1
+#define RTN20   2
+#define RTN21   3
+
+#define FEMS    _SFR_MEM8(0x108)
+#define PLLS0   0
+#define PLLS1   1
+#define PLLS2   2
+#define PLLS3   3
+#define PLLM0   4
+#define PLLM1   5
+#define PLLM2   6
+#define PLLM3   7
+
+#define FETN4   _SFR_MEM8(0x109)
+#define CTN40   0
+#define CTN41   1
+#define CTN42   2
+#define CTN43   3
+#define RTN40   4
+#define RTN41   5
+#define RTN42   6
+#define RTN43   7
+
+#define FECR    _SFR_MEM8(0x10A)
+#define LBNHB   0
+#define S4N3    1
+#define ANDP    2
+#define ADHS    3
+#define PLCKG   4
+#define ANPS    5
+
+#define FEVCO   _SFR_MEM8(0x10B)
+#define CPCC0   0
+#define CPCC1   1
+#define CPCC2   2
+#define CPCC3   3
+#define VCOB0   4
+#define VCOB1   5
+#define VCOB2   6
+#define VCOB3   7
+
+#define FEALR   _SFR_MEM8(0x10C)
+#define RNGE0   0
+#define RNGE1   1
+
+#define FEANT   _SFR_MEM8(0x10D)
+#define LVLC0   0
+#define LVLC1   1
+#define LVLC2   2
+#define LVLC3   3
+
+#define FEBIA   _SFR_MEM8(0x10E)
+#define IFAEN   7
+
+/* Reserved [0x10F..0x11F] */
+
+#define TMFSM   _SFR_MEM8(0x120)
+#define TMSSM0  0
+#define TMSSM1  1
+#define TMSSM2  2
+#define TMSSM3  3
+#define TMMSM0  4
+#define TMMSM1  5
+#define TMMSM2  6
+
+/* Combine TMCRL and TMCRH */
+#define TMCR    _SFR_MEM16(0x121)
+
+#define TMCRL   _SFR_MEM8(0x121)
+#define TMCRH   _SFR_MEM8(0x122)
+
+#define TMCSB   _SFR_MEM8(0x123)
+
+/* Combine TMCIL and TMCIH */
+#define TMCI    _SFR_MEM16(0x124)
+
+#define TMCIL   _SFR_MEM8(0x124)
+#define TMCIH   _SFR_MEM8(0x125)
+
+/* Combine TMCPL and TMCPH */
+#define TMCP    _SFR_MEM16(0x126)
+
+#define TMCPL   _SFR_MEM8(0x126)
+#define TMCPH   _SFR_MEM8(0x127)
+
+#define TMSHR   _SFR_MEM8(0x128)
+
+/* Combine TMTLL and TMTLH */
+#define TMTL    _SFR_MEM16(0x129)
+
+#define TMTLL   _SFR_MEM8(0x129)
+#define TMTLH   _SFR_MEM8(0x12A)
+
+#define TMSSC   _SFR_MEM8(0x12B)
+#define TMSSP0  0
+#define TMSSP1  1
+#define TMSSP2  2
+#define TMSSP3  3
+#define TMSSL0  4
+#define TMSSL1  5
+#define TMSSL2  6
+#define TMSSH   7
+
+#define TMSR    _SFR_MEM8(0x12C)
+#define TMTCF   0
+
+#define TMCR2   _SFR_MEM8(0x12D)
+#define TMCRCE  0
+#define TMCRCL0 1
+#define TMCRCL1 2
+#define TMNRZE  3
+#define TMPOL   4
+#define TMSSE   5
+#define TMMSB   6
+
+#define TMCR1   _SFR_MEM8(0x12E)
+#define TMPIS0  0
+#define TMPIS1  1
+#define TMPIS2  2
+#define TMSCS   3
+#define TMCIM   4
+
+#define RXBC1   _SFR_MEM8(0x12F)
+#define RXCEA   0
+#define RXCBLA0 1
+#define RXCBLA1 2
+#define RXMSBA  3
+#define RXCEB   4
+#define RXCBLB0 5
+#define RXCBLB1 6
+#define RXMSBB  7
+
+#define RXBC2   _SFR_MEM8(0x130)
+#define RXBPB   0
+#define RXBF    1
+#define RXBCLR  2
+
+#define RXTLLB  _SFR_MEM8(0x131)
+
+#define RXTLHB  _SFR_MEM8(0x132)
+#define RXTLHB0 0
+#define RXTLHB1 1
+#define RXTLHB2 2
+#define RXTLHB3 3
+
+#define RXCRLB  _SFR_MEM8(0x133)
+
+#define RXCRHB  _SFR_MEM8(0x134)
+
+#define RXCSBB  _SFR_MEM8(0x135)
+
+#define RXCILB  _SFR_MEM8(0x136)
+
+#define RXCIHB  _SFR_MEM8(0x137)
+
+#define RXCPLB  _SFR_MEM8(0x138)
+
+#define RXCPHB  _SFR_MEM8(0x139)
+
+#define RXDSB   _SFR_MEM8(0x13A)
+
+#define RXTLLA  _SFR_MEM8(0x13B)
+
+#define RXTLHA  _SFR_MEM8(0x13C)
+#define RXTLHA0 0
+#define RXTLHA1 1
+#define RXTLHA2 2
+#define RXTLHA3 3
+
+#define RXCRLA  _SFR_MEM8(0x13D)
+
+#define RXCRHA  _SFR_MEM8(0x13E)
+
+#define RXCSBA  _SFR_MEM8(0x13F)
+
+#define RXCILA  _SFR_MEM8(0x140)
+
+#define RXCIHA  _SFR_MEM8(0x141)
+
+#define RXCPLA  _SFR_MEM8(0x142)
+
+#define RXCPHA  _SFR_MEM8(0x143)
+
+#define RXDSA   _SFR_MEM8(0x144)
+
+#define CRCCR   _SFR_MEM8(0x145)
+#define CRCRS   0
+#define REFLI   1
+#define REFLO   2
+
+#define CRCDOR  _SFR_MEM8(0x146)
+
+#define IDB0    _SFR_MEM8(0x147)
+
+#define IDB1    _SFR_MEM8(0x148)
+
+#define IDB2    _SFR_MEM8(0x149)
+
+#define IDB3    _SFR_MEM8(0x14A)
+
+#define IDC     _SFR_MEM8(0x14B)
+#define IDL0    0
+#define IDL1    1
+#define IDBO0   2
+#define IDBO1   3
+#define IDFIM   5
+#define IDCLR   6
+#define IDCE    7
+
+#define IDS     _SFR_MEM8(0x14C)
+#define IDOK    0
+#define IDFULL  1
+
+#define RSSAV   _SFR_MEM8(0x14D)
+
+#define RSSPK   _SFR_MEM8(0x14E)
+
+#define RSSL    _SFR_MEM8(0x14F)
+
+#define RSSH    _SFR_MEM8(0x150)
+
+#define RSSC    _SFR_MEM8(0x151)
+#define RSUP0   0
+#define RSUP1   1
+#define RSUP2   2
+#define RSUP3   3
+#define RSWLH   4
+#define RSHRX   5
+#define RSPKF   6
+
+#define DBCR    _SFR_MEM8(0x152)
+#define DBMD    0
+#define DBCS    1
+#define DBTMS   2
+#define DBHA    3
+
+#define DBTC    _SFR_MEM8(0x153)
+
+#define DBENB   _SFR_MEM8(0x154)
+
+#define DBENC   _SFR_MEM8(0x155)
+
+#define DBGSW   _SFR_MEM8(0x156)
+#define DBGGS0  0
+#define DBGGS1  1
+#define DBGGS2  2
+#define DBGGS3  3
+#define CPBFOS0 4
+#define CPBFOS1 5
+#define CPBF    6
+#define DBGSE   7
+
+#define SFFR    _SFR_MEM8(0x157)
+#define RFL0    0
+#define RFL1    1
+#define RFL2    2
+#define RFC     3
+#define TFL0    4
+#define TFL1    5
+#define TFL2    6
+#define TFC     7
+
+#define SFIR    _SFR_MEM8(0x158)
+#define RIL0    0
+#define RIL1    1
+#define RIL2    2
+#define SRIE    3
+#define TIL0    4
+#define TIL1    5
+#define TIL2    6
+#define STIE    7
+
+#define EECR2   _SFR_MEM8(0x159)
+#define EEBRE   0
+
+#define PGMST   _SFR_MEM8(0x15A)
+#define PGMSYN0 0
+#define PGMSYN1 1
+#define PGMSYN2 2
+#define PGMSYN3 3
+#define PGMSYN4 4
+
+#define EEST    _SFR_MEM8(0x15B)
+#define EESYN0  0
+#define EESYN1  1
+#define EESYN2  2
+#define EESYN3  3
+
+#define RSIFG   _SFR_MEM8(0x15C)
+
+#define RSLDV   _SFR_MEM8(0x15D)
+
+#define RSHDV   _SFR_MEM8(0x15E)
+
+#define RSCOM   _SFR_MEM8(0x15F)
+#define RSDC    0
+#define RSIFC   1
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCI0_vect            _VECTOR(3)
+#define PCI0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCI1_vect            _VECTOR(4)
+#define PCI1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMON_vect            _VECTOR(5)
+#define VMON_vect_num        5
+
+/* AVCC Reset Interrupt */
+#define AVCCR_vect            _VECTOR(6)
+#define AVCCR_vect_num        6
+
+/* AVCC Low Interrupt */
+#define AVCCL_vect            _VECTOR(7)
+#define AVCCL_vect_num        7
+
+/* Timer 0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(8)
+#define T0INT_vect_num        8
+
+/* Timer/Counter1 Compare Match Interrupt */
+#define T1COMP_vect            _VECTOR(9)
+#define T1COMP_vect_num        9
+
+/* Timer/Counter1 Overflow Interrupt */
+#define T1OVF_vect            _VECTOR(10)
+#define T1OVF_vect_num        10
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMP_vect            _VECTOR(11)
+#define T2COMP_vect_num        11
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVF_vect            _VECTOR(12)
+#define T2OVF_vect_num        12
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAP_vect            _VECTOR(13)
+#define T3CAP_vect_num        13
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMP_vect            _VECTOR(14)
+#define T3COMP_vect_num        14
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVF_vect            _VECTOR(15)
+#define T3OVF_vect_num        15
+
+/* Timer/Counter4 Capture Event Interrupt */
+#define T4CAP_vect            _VECTOR(16)
+#define T4CAP_vect_num        16
+
+/* Timer/Counter4 Compare Match Interrupt */
+#define T4COMP_vect            _VECTOR(17)
+#define T4COMP_vect_num        17
+
+/* Timer/Counter4 Overflow Interrupt */
+#define T4OVF_vect            _VECTOR(18)
+#define T4OVF_vect_num        18
+
+/* Timer/Counter5 Compare Match Interrupt */
+#define T5COMP_vect            _VECTOR(19)
+#define T5COMP_vect_num        19
+
+/* Timer/Counter5 Overflow Interrupt */
+#define T5OVF_vect            _VECTOR(20)
+#define T5OVF_vect_num        20
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPI_vect            _VECTOR(21)
+#define SPI_vect_num        21
+
+/* SPI Rx Buffer Interrupt */
+#define SRX_FIFO_vect            _VECTOR(22)
+#define SRX_FIFO_vect_num        22
+
+/* SPI Tx Buffer Interrupt */
+#define STX_FIFO_vect            _VECTOR(23)
+#define STX_FIFO_vect_num        23
+
+/* Sequencer State Machine Interrupt */
+#define SSM_vect            _VECTOR(24)
+#define SSM_vect_num        24
+
+/* Data FIFO fill level reached Interrupt */
+#define DFFLR_vect            _VECTOR(25)
+#define DFFLR_vect_num        25
+
+/* Data FIFO overflow or underflow error Interrupt */
+#define DFOUE_vect            _VECTOR(26)
+#define DFOUE_vect_num        26
+
+/* RSSI/Preamble FIFO fill level reached Interrupt */
+#define SFFLR_vect            _VECTOR(27)
+#define SFFLR_vect_num        27
+
+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
+#define SFOUE_vect            _VECTOR(28)
+#define SFOUE_vect_num        28
+
+/* Tx Modulator Telegram Finish Interrupt */
+#define TMTCF_vect            _VECTOR(29)
+#define TMTCF_vect_num        29
+
+/* UHF receiver wake up ok on Rx path B */
+#define UHF_WCOB_vect            _VECTOR(30)
+#define UHF_WCOB_vect_num        30
+
+/* UHF receiver wake up ok on Rx path A */
+#define UHF_WCOA_vect            _VECTOR(31)
+#define UHF_WCOA_vect_num        31
+
+/* UHF receiver start of telegram ok on Rx path B */
+#define UHF_SOTB_vect            _VECTOR(32)
+#define UHF_SOTB_vect_num        32
+
+/* UHF receiver start of telegram ok on Rx path A */
+#define UHF_SOTA_vect            _VECTOR(33)
+#define UHF_SOTA_vect_num        33
+
+/* UHF receiver end of telegram on Rx path B */
+#define UHF_EOTB_vect            _VECTOR(34)
+#define UHF_EOTB_vect_num        34
+
+/* UHF receiver end of telegram on Rx path A */
+#define UHF_EOTA_vect            _VECTOR(35)
+#define UHF_EOTA_vect_num        35
+
+/* UHF receiver new bit on Rx path B */
+#define UHF_NBITB_vect            _VECTOR(36)
+#define UHF_NBITB_vect_num        36
+
+/* UHF receiver new bit on Rx path A */
+#define UHF_NBITA_vect            _VECTOR(37)
+#define UHF_NBITA_vect_num        37
+
+/* External input Clock monitoring Interrupt */
+#define EXCM_vect            _VECTOR(38)
+#define EXCM_vect_num        38
+
+/* EEPROM Ready Interrupt */
+#define ERDY_vect            _VECTOR(39)
+#define ERDY_vect_num        39
+
+/* Store Program Memory Ready */
+#define SPMR_vect            _VECTOR(40)
+#define SPMR_vect_num        40
+
+/* IDSCAN Full Interrupt */
+#define IDFULL_vect            _VECTOR(41)
+#define IDFULL_vect_num        41
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 168
+#else
+#  define _VECTORS_SIZE 168U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x8000
+#  define FLASHEND     0xCFFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x8000U
+#  define FLASHEND     0xCFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      1024
+#  define RAMEND       0x05FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x05FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  16
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  16U
+#  define E2END       0x03FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_EXTCLKEN    (unsigned char)~_BV(0)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(1)
+#define FUSE_BOOTRST     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x61
+
+
+
+
+#endif /* #ifdef _AVR_ATA5831_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa6285.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa6285.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATA6285_H_INCLUDED
 #define _AVR_ATA6285_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -87,8 +86,14 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC2  2
@@ -107,13 +112,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -528,6 +549,13 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -634,21 +662,44 @@
 #define SPM_RDY_vect            _VECTOR(26)
 #define SPM_RDY_vect_num        26
 
-#define _VECTORS_SIZE 54
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 54
+#else
+#  define _VECTORS_SIZE 54U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      320
-#define E2PAGESIZE  4
-#define E2END       0x013F
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      320
+#  define E2PAGESIZE  4
+#  define E2END       0x013F
+#else
+#  define E2START     0U
+#  define E2SIZE      320U
+#  define E2PAGESIZE  4U
+#  define E2END       0x013FU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -665,6 +716,8 @@
 #define FUSE_SUT_CKSEL1  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_BODEN & FUSE_FRCFS & FUSE_WDRCON & FUSE_SUT_CKSEL0 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -675,6 +728,8 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_DWEN        (unsigned char)~_BV(6)
 #define FUSE_EELOCK      (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
+
 
 
 /* Lock Bits */
@@ -690,9 +745,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
 
 #endif /* #ifdef _AVR_ATA6285_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa6286.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa6286.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATA6286_H_INCLUDED
 #define _AVR_ATA6286_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -87,8 +86,14 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC2  2
@@ -107,13 +112,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -528,6 +549,13 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -634,21 +662,44 @@
 #define SPM_RDY_vect            _VECTOR(26)
 #define SPM_RDY_vect_num        26
 
-#define _VECTORS_SIZE 54
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 54
+#else
+#  define _VECTORS_SIZE 54U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      320
-#define E2PAGESIZE  4
-#define E2END       0x013F
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      320
+#  define E2PAGESIZE  4
+#  define E2END       0x013F
+#else
+#  define E2START     0U
+#  define E2SIZE      320U
+#  define E2PAGESIZE  4U
+#  define E2END       0x013FU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -665,6 +716,8 @@
 #define FUSE_SUT_CKSEL1  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_BODEN & FUSE_FRCFS & FUSE_WDRCON & FUSE_SUT_CKSEL0 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -675,6 +728,8 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_DWEN        (unsigned char)~_BV(6)
 #define FUSE_EELOCK      (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
+
 
 
 /* Lock Bits */
@@ -690,9 +745,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
 
 #endif /* #ifdef _AVR_ATA6286_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa6289.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa6289.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: ioa6289.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* avr/ioa6289.h - definitions for ATA6289 */
 
@@ -839,8 +839,6 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x82
 
-
-
 #define SLEEP_MODE_IDLE                     (0)
 #define SLEEP_MODE_SENSOR_NOISE_REDUCTION   (_BV(SM0))
 #define SLEEP_MODE_PWR_DOWN                 (_BV(SM1))
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa6612c.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa6612c.h
@@ -1,795 +1,805 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATA6612C_H_INCLUDED
-#define _AVR_ATA6612C_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa6612c.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC0    0
-#define DDC1    1
-#define DDC2    2
-#define DDC3    3
-#define DDC4    4
-#define DDC5    5
-#define DDC6    6
-
-#define PORTC   _SFR_IO8(0x08)
-#define PORTC6  6
-#define PORTC5  5
-#define PORTC4  4
-#define PORTC3  3
-#define PORTC2  2
-#define PORTC1  1
-#define PORTC0  0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD0    0
-#define DDD1    1
-#define DDD2    2
-#define DDD3    3
-#define DDD4    4
-#define DDD5    5
-#define DDD6    6
-#define DDD7    7
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PORTD7  7
-#define PORTD6  6
-#define PORTD5  5
-#define PORTD4  4
-#define PORTD3  3
-#define PORTD2  2
-#define PORTD1  1
-#define PORTD0  0
-
-/* Reserved [0x0C..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-#define OCF0B   2
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-#define OCF2B   2
-
-/* Reserved [0x18..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-#define PCIF1   1
-#define PCIF2   2
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define INT1    1
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM     7
-#define PSRASY  1
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0
-#define WGM01   1
-#define COM0B0  4
-#define COM0B1  5
-#define COM0A0  6
-#define COM0A1  7
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM02   3
-#define FOC0B   6
-#define FOC0A   7
-
-#define TCNT0   _SFR_IO8(0x26)
-
-#define OCR0A   _SFR_IO8(0x27)
-
-#define OCR0B   _SFR_IO8(0x28)
-
-/* Reserved [0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-/* Reserved [0x31..0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDE     3
-#define WDCE    4
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0
-#define PRUSART0 1
-#define PRSPI   2
-#define PRTIM1  3
-#define PRTIM0  5
-#define PRTIM2  6
-#define PRTWI   7
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRUSART0
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRTIM1
-#define __AVR_HAVE_PRR_PRTIM0
-#define __AVR_HAVE_PRR_PRTIM2
-#define __AVR_HAVE_PRR_PRTWI
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-#define OSCCAL0 0
-#define OSCCAL1 1
-#define OSCCAL2 2
-#define OSCCAL3 3
-#define OSCCAL4 4
-#define OSCCAL5 5
-#define OSCCAL6 6
-#define OSCCAL7 7
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-#define PCIE1   1
-#define PCIE2   2
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2  _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-#define OCIE0B  2
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-#define OCIE2B  2
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define WGM20   0
-#define WGM21   1
-#define COM2B0  4
-#define COM2B1  5
-#define COM2A0  6
-#define COM2A1  7
-
-#define TCCR2B  _SFR_MEM8(0xB1)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM22   3
-#define FOC2B   6
-#define FOC2A   7
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-#define OCR2B   _SFR_MEM8(0xB4)
-
-/* Reserved [0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB  4
-#define AS2     5
-#define EXCLK   6
-
-/* Reserved [0xB7] */
-
-#define TWBR    _SFR_MEM8(0xB8)
-
-#define TWSR    _SFR_MEM8(0xB9)
-#define TWPS0   0
-#define TWPS1   1
-#define TWS3    3
-#define TWS4    4
-#define TWS5    5
-#define TWS6    6
-#define TWS7    7
-
-#define TWAR    _SFR_MEM8(0xBA)
-#define TWGCE   0
-#define TWA0    1
-#define TWA1    2
-#define TWA2    3
-#define TWA3    4
-#define TWA4    5
-#define TWA5    6
-#define TWA6    7
-
-#define TWDR    _SFR_MEM8(0xBB)
-
-#define TWCR    _SFR_MEM8(0xBC)
-#define TWIE    0
-#define TWEN    2
-#define TWWC    3
-#define TWSTO   4
-#define TWSTA   5
-#define TWEA    6
-#define TWINT   7
-
-#define TWAMR   _SFR_MEM8(0xBD)
-#define TWAM0   1
-#define TWAM1   2
-#define TWAM2   3
-#define TWAM3   4
-#define TWAM4   5
-#define TWAM5   6
-#define TWAM6   7
-
-/* Reserved [0xBE..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0xC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCPHA0  1
-#define UDORD0  2
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL00 6
-#define UMSEL01 7
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0xC6)
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(3)
-#define PCINT0_vect_num        3
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT1_vect            _VECTOR(4)
-#define PCINT1_vect_num        4
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT2_vect            _VECTOR(5)
-#define PCINT2_vect_num        5
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect            _VECTOR(6)
-#define WDT_vect_num        6
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect            _VECTOR(7)
-#define TIMER2_COMPA_vect_num        7
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect            _VECTOR(8)
-#define TIMER2_COMPB_vect_num        8
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect            _VECTOR(9)
-#define TIMER2_OVF_vect_num        9
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(10)
-#define TIMER1_CAPT_vect_num        10
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect            _VECTOR(11)
-#define TIMER1_COMPA_vect_num        11
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect            _VECTOR(12)
-#define TIMER1_COMPB_vect_num        12
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(13)
-#define TIMER1_OVF_vect_num        13
-
-/* TimerCounter0 Compare Match A */
-#define TIMER0_COMPA_vect            _VECTOR(14)
-#define TIMER0_COMPA_vect_num        14
-
-/* TimerCounter0 Compare Match B */
-#define TIMER0_COMPB_vect            _VECTOR(15)
-#define TIMER0_COMPB_vect_num        15
-
-/* Timer/Couner0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(16)
-#define TIMER0_OVF_vect_num        16
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect            _VECTOR(17)
-#define SPI_STC_vect_num        17
-
-/* USART Rx Complete */
-#define USART_RX_vect            _VECTOR(18)
-#define USART_RX_vect_num        18
-
-/* USART, Data Register Empty */
-#define USART_UDRE_vect            _VECTOR(19)
-#define USART_UDRE_vect_num        19
-
-/* USART Tx Complete */
-#define USART_TX_vect            _VECTOR(20)
-#define USART_TX_vect_num        20
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(21)
-#define ADC_vect_num        21
-
-/* EEPROM Ready */
-#define EE_READY_vect            _VECTOR(22)
-#define EE_READY_vect_num        22
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect            _VECTOR(23)
-#define ANALOG_COMP_vect_num        23
-
-/* Two-wire Serial Interface */
-#define TWI_vect            _VECTOR(24)
-#define TWI_vect_num        24
-
-/* Store Program Memory Read */
-#define SPM_Ready_vect            _VECTOR(25)
-#define SPM_Ready_vect_num        25
-
-#define _VECTORS_SIZE 52
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      1024
-#define RAMEND       0x04FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x0A
-
-
-#endif /* #ifdef _AVR_ATA6612C_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA6612C_H_INCLUDED
+#define _AVR_ATA6612C_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa6612c.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB0    0
+#define DDB1    1
+#define DDB2    2
+#define DDB3    3
+#define DDB4    4
+#define DDB5    5
+#define DDB6    6
+#define DDB7    7
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC0    0
+#define DDC1    1
+#define DDC2    2
+#define DDC3    3
+#define DDC4    4
+#define DDC5    5
+#define DDC6    6
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD0    0
+#define DDD1    1
+#define DDD2    2
+#define DDD3    3
+#define DDD4    4
+#define DDD5    5
+#define DDD6    6
+#define DDD7    7
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+/* Reserved [0x0C..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM     7
+#define PSRASY  1
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+/* Reserved [0x31..0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62..0x63] */
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+/* Reserved [0x71..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCPHA0  1
+#define UDORD0  2
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT2_vect            _VECTOR(5)
+#define PCINT2_vect_num        5
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(6)
+#define WDT_vect_num        6
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(7)
+#define TIMER2_COMPA_vect_num        7
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect            _VECTOR(8)
+#define TIMER2_COMPB_vect_num        8
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(9)
+#define TIMER2_OVF_vect_num        9
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(10)
+#define TIMER1_CAPT_vect_num        10
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(11)
+#define TIMER1_COMPA_vect_num        11
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(12)
+#define TIMER1_COMPB_vect_num        12
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(13)
+#define TIMER1_OVF_vect_num        13
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(14)
+#define TIMER0_COMPA_vect_num        14
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(15)
+#define TIMER0_COMPB_vect_num        15
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(16)
+#define TIMER0_OVF_vect_num        16
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(17)
+#define SPI_STC_vect_num        17
+
+/* USART Rx Complete */
+#define USART_RX_vect            _VECTOR(18)
+#define USART_RX_vect_num        18
+
+/* USART, Data Register Empty */
+#define USART_UDRE_vect            _VECTOR(19)
+#define USART_UDRE_vect_num        19
+
+/* USART Tx Complete */
+#define USART_TX_vect            _VECTOR(20)
+#define USART_TX_vect_num        20
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(21)
+#define ADC_vect_num        21
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(22)
+#define EE_READY_vect_num        22
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect            _VECTOR(23)
+#define ANALOG_COMP_vect_num        23
+
+/* Two-wire Serial Interface */
+#define TWI_vect            _VECTOR(24)
+#define TWI_vect_num        24
+
+/* Store Program Memory Read */
+#define SPM_Ready_vect            _VECTOR(25)
+#define SPM_Ready_vect_num        25
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 52
+#else
+#  define _VECTORS_SIZE 52U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      1024
+#  define RAMEND       0x04FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x04FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x0A
+
+
+
+
+#endif /* #ifdef _AVR_ATA6612C_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa6613c.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa6613c.h
@@ -1,795 +1,805 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATA6613C_H_INCLUDED
-#define _AVR_ATA6613C_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa6613c.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC0    0
-#define DDC1    1
-#define DDC2    2
-#define DDC3    3
-#define DDC4    4
-#define DDC5    5
-#define DDC6    6
-
-#define PORTC   _SFR_IO8(0x08)
-#define PORTC6  6
-#define PORTC5  5
-#define PORTC4  4
-#define PORTC3  3
-#define PORTC2  2
-#define PORTC1  1
-#define PORTC0  0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD0    0
-#define DDD1    1
-#define DDD2    2
-#define DDD3    3
-#define DDD4    4
-#define DDD5    5
-#define DDD6    6
-#define DDD7    7
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PORTD7  7
-#define PORTD6  6
-#define PORTD5  5
-#define PORTD4  4
-#define PORTD3  3
-#define PORTD2  2
-#define PORTD1  1
-#define PORTD0  0
-
-/* Reserved [0x0C..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-#define OCF0B   2
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-#define OCF2B   2
-
-/* Reserved [0x18..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-#define PCIF1   1
-#define PCIF2   2
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define INT1    1
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM     7
-#define PSRASY  1
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0
-#define WGM01   1
-#define COM0B0  4
-#define COM0B1  5
-#define COM0A0  6
-#define COM0A1  7
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM02   3
-#define FOC0B   6
-#define FOC0A   7
-
-#define TCNT0   _SFR_IO8(0x26)
-
-#define OCR0A   _SFR_IO8(0x27)
-
-#define OCR0B   _SFR_IO8(0x28)
-
-/* Reserved [0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-/* Reserved [0x31..0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDE     3
-#define WDCE    4
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0
-#define PRUSART0 1
-#define PRSPI   2
-#define PRTIM1  3
-#define PRTIM0  5
-#define PRTIM2  6
-#define PRTWI   7
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRUSART0
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRTIM1
-#define __AVR_HAVE_PRR_PRTIM0
-#define __AVR_HAVE_PRR_PRTIM2
-#define __AVR_HAVE_PRR_PRTWI
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-#define OSCCAL0 0
-#define OSCCAL1 1
-#define OSCCAL2 2
-#define OSCCAL3 3
-#define OSCCAL4 4
-#define OSCCAL5 5
-#define OSCCAL6 6
-#define OSCCAL7 7
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-#define PCIE1   1
-#define PCIE2   2
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2  _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-#define OCIE0B  2
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-#define OCIE2B  2
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define WGM20   0
-#define WGM21   1
-#define COM2B0  4
-#define COM2B1  5
-#define COM2A0  6
-#define COM2A1  7
-
-#define TCCR2B  _SFR_MEM8(0xB1)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM22   3
-#define FOC2B   6
-#define FOC2A   7
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-#define OCR2B   _SFR_MEM8(0xB4)
-
-/* Reserved [0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB  4
-#define AS2     5
-#define EXCLK   6
-
-/* Reserved [0xB7] */
-
-#define TWBR    _SFR_MEM8(0xB8)
-
-#define TWSR    _SFR_MEM8(0xB9)
-#define TWPS0   0
-#define TWPS1   1
-#define TWS3    3
-#define TWS4    4
-#define TWS5    5
-#define TWS6    6
-#define TWS7    7
-
-#define TWAR    _SFR_MEM8(0xBA)
-#define TWGCE   0
-#define TWA0    1
-#define TWA1    2
-#define TWA2    3
-#define TWA3    4
-#define TWA4    5
-#define TWA5    6
-#define TWA6    7
-
-#define TWDR    _SFR_MEM8(0xBB)
-
-#define TWCR    _SFR_MEM8(0xBC)
-#define TWIE    0
-#define TWEN    2
-#define TWWC    3
-#define TWSTO   4
-#define TWSTA   5
-#define TWEA    6
-#define TWINT   7
-
-#define TWAMR   _SFR_MEM8(0xBD)
-#define TWAM0   1
-#define TWAM1   2
-#define TWAM2   3
-#define TWAM3   4
-#define TWAM4   5
-#define TWAM5   6
-#define TWAM6   7
-
-/* Reserved [0xBE..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0xC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCPHA0  1
-#define UDORD0  2
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL00 6
-#define UMSEL01 7
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0xC6)
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(3)
-#define PCINT0_vect_num        3
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT1_vect            _VECTOR(4)
-#define PCINT1_vect_num        4
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT2_vect            _VECTOR(5)
-#define PCINT2_vect_num        5
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect            _VECTOR(6)
-#define WDT_vect_num        6
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect            _VECTOR(7)
-#define TIMER2_COMPA_vect_num        7
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect            _VECTOR(8)
-#define TIMER2_COMPB_vect_num        8
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect            _VECTOR(9)
-#define TIMER2_OVF_vect_num        9
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(10)
-#define TIMER1_CAPT_vect_num        10
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect            _VECTOR(11)
-#define TIMER1_COMPA_vect_num        11
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect            _VECTOR(12)
-#define TIMER1_COMPB_vect_num        12
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(13)
-#define TIMER1_OVF_vect_num        13
-
-/* TimerCounter0 Compare Match A */
-#define TIMER0_COMPA_vect            _VECTOR(14)
-#define TIMER0_COMPA_vect_num        14
-
-/* TimerCounter0 Compare Match B */
-#define TIMER0_COMPB_vect            _VECTOR(15)
-#define TIMER0_COMPB_vect_num        15
-
-/* Timer/Couner0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(16)
-#define TIMER0_OVF_vect_num        16
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect            _VECTOR(17)
-#define SPI_STC_vect_num        17
-
-/* USART Rx Complete */
-#define USART_RX_vect            _VECTOR(18)
-#define USART_RX_vect_num        18
-
-/* USART, Data Register Empty */
-#define USART_UDRE_vect            _VECTOR(19)
-#define USART_UDRE_vect_num        19
-
-/* USART Tx Complete */
-#define USART_TX_vect            _VECTOR(20)
-#define USART_TX_vect_num        20
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(21)
-#define ADC_vect_num        21
-
-/* EEPROM Ready */
-#define EE_READY_vect            _VECTOR(22)
-#define EE_READY_vect_num        22
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect            _VECTOR(23)
-#define ANALOG_COMP_vect_num        23
-
-/* Two-wire Serial Interface */
-#define TWI_vect            _VECTOR(24)
-#define TWI_vect_num        24
-
-/* Store Program Memory Read */
-#define SPM_Ready_vect            _VECTOR(25)
-#define SPM_Ready_vect_num        25
-
-#define _VECTORS_SIZE 104
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      1024
-#define RAMEND       0x04FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x06
-
-
-#endif /* #ifdef _AVR_ATA6613C_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA6613C_H_INCLUDED
+#define _AVR_ATA6613C_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa6613c.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB0    0
+#define DDB1    1
+#define DDB2    2
+#define DDB3    3
+#define DDB4    4
+#define DDB5    5
+#define DDB6    6
+#define DDB7    7
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC0    0
+#define DDC1    1
+#define DDC2    2
+#define DDC3    3
+#define DDC4    4
+#define DDC5    5
+#define DDC6    6
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD0    0
+#define DDD1    1
+#define DDD2    2
+#define DDD3    3
+#define DDD4    4
+#define DDD5    5
+#define DDD6    6
+#define DDD7    7
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+/* Reserved [0x0C..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM     7
+#define PSRASY  1
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+/* Reserved [0x31..0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62..0x63] */
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+/* Reserved [0x71..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCPHA0  1
+#define UDORD0  2
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT2_vect            _VECTOR(5)
+#define PCINT2_vect_num        5
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(6)
+#define WDT_vect_num        6
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(7)
+#define TIMER2_COMPA_vect_num        7
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect            _VECTOR(8)
+#define TIMER2_COMPB_vect_num        8
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(9)
+#define TIMER2_OVF_vect_num        9
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(10)
+#define TIMER1_CAPT_vect_num        10
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(11)
+#define TIMER1_COMPA_vect_num        11
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(12)
+#define TIMER1_COMPB_vect_num        12
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(13)
+#define TIMER1_OVF_vect_num        13
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(14)
+#define TIMER0_COMPA_vect_num        14
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(15)
+#define TIMER0_COMPB_vect_num        15
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(16)
+#define TIMER0_OVF_vect_num        16
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(17)
+#define SPI_STC_vect_num        17
+
+/* USART Rx Complete */
+#define USART_RX_vect            _VECTOR(18)
+#define USART_RX_vect_num        18
+
+/* USART, Data Register Empty */
+#define USART_UDRE_vect            _VECTOR(19)
+#define USART_UDRE_vect_num        19
+
+/* USART Tx Complete */
+#define USART_TX_vect            _VECTOR(20)
+#define USART_TX_vect_num        20
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(21)
+#define ADC_vect_num        21
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(22)
+#define EE_READY_vect_num        22
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect            _VECTOR(23)
+#define ANALOG_COMP_vect_num        23
+
+/* Two-wire Serial Interface */
+#define TWI_vect            _VECTOR(24)
+#define TWI_vect_num        24
+
+/* Store Program Memory Read */
+#define SPM_Ready_vect            _VECTOR(25)
+#define SPM_Ready_vect_num        25
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 104
+#else
+#  define _VECTORS_SIZE 104U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      1024
+#  define RAMEND       0x04FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x04FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x06
+
+
+
+
+#endif /* #ifdef _AVR_ATA6613C_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa6614q.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa6614q.h
@@ -1,798 +1,808 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATA6614Q_H_INCLUDED
-#define _AVR_ATA6614Q_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa6614q.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC0    0
-#define DDC1    1
-#define DDC2    2
-#define DDC3    3
-#define DDC4    4
-#define DDC5    5
-#define DDC6    6
-
-#define PORTC   _SFR_IO8(0x08)
-#define PORTC6  6
-#define PORTC5  5
-#define PORTC4  4
-#define PORTC3  3
-#define PORTC2  2
-#define PORTC1  1
-#define PORTC0  0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD0    0
-#define DDD1    1
-#define DDD2    2
-#define DDD3    3
-#define DDD4    4
-#define DDD5    5
-#define DDD6    6
-#define DDD7    7
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PORTD7  7
-#define PORTD6  6
-#define PORTD5  5
-#define PORTD4  4
-#define PORTD3  3
-#define PORTD2  2
-#define PORTD1  1
-#define PORTD0  0
-
-/* Reserved [0x0C..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-#define OCF0B   2
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-#define OCF2B   2
-
-/* Reserved [0x18..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-#define PCIF1   1
-#define PCIF2   2
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define INT1    1
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM     7
-#define PSRASY  1
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0
-#define WGM01   1
-#define COM0B0  4
-#define COM0B1  5
-#define COM0A0  6
-#define COM0A1  7
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM02   3
-#define FOC0B   6
-#define FOC0A   7
-
-#define TCNT0   _SFR_IO8(0x26)
-
-#define OCR0A   _SFR_IO8(0x27)
-
-#define OCR0B   _SFR_IO8(0x28)
-
-/* Reserved [0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-/* Reserved [0x31..0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define BODSE   5
-#define BODS    6
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDE     3
-#define WDCE    4
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0
-#define PRUSART0 1
-#define PRSPI   2
-#define PRTIM1  3
-#define PRTIM0  5
-#define PRTIM2  6
-#define PRTWI   7
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRUSART0
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRTIM1
-#define __AVR_HAVE_PRR_PRTIM0
-#define __AVR_HAVE_PRR_PRTIM2
-#define __AVR_HAVE_PRR_PRTWI
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-#define OSCCAL0 0
-#define OSCCAL1 1
-#define OSCCAL2 2
-#define OSCCAL3 3
-#define OSCCAL4 4
-#define OSCCAL5 5
-#define OSCCAL6 6
-#define OSCCAL7 7
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-#define PCIE1   1
-#define PCIE2   2
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2  _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-#define OCIE0B  2
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-#define OCIE2B  2
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define WGM20   0
-#define WGM21   1
-#define COM2B0  4
-#define COM2B1  5
-#define COM2A0  6
-#define COM2A1  7
-
-#define TCCR2B  _SFR_MEM8(0xB1)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM22   3
-#define FOC2B   6
-#define FOC2A   7
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-#define OCR2B   _SFR_MEM8(0xB4)
-
-/* Reserved [0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB  4
-#define AS2     5
-#define EXCLK   6
-
-/* Reserved [0xB7] */
-
-#define TWBR    _SFR_MEM8(0xB8)
-
-#define TWSR    _SFR_MEM8(0xB9)
-#define TWPS0   0
-#define TWPS1   1
-#define TWS3    3
-#define TWS4    4
-#define TWS5    5
-#define TWS6    6
-#define TWS7    7
-
-#define TWAR    _SFR_MEM8(0xBA)
-#define TWGCE   0
-#define TWA0    1
-#define TWA1    2
-#define TWA2    3
-#define TWA3    4
-#define TWA4    5
-#define TWA5    6
-#define TWA6    7
-
-#define TWDR    _SFR_MEM8(0xBB)
-
-#define TWCR    _SFR_MEM8(0xBC)
-#define TWIE    0
-#define TWEN    2
-#define TWWC    3
-#define TWSTO   4
-#define TWSTA   5
-#define TWEA    6
-#define TWINT   7
-
-#define TWAMR   _SFR_MEM8(0xBD)
-#define TWAM0   1
-#define TWAM1   2
-#define TWAM2   3
-#define TWAM3   4
-#define TWAM4   5
-#define TWAM5   6
-#define TWAM6   7
-
-/* Reserved [0xBE..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0xC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCPHA0  1
-#define UDORD0  2
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL00 6
-#define UMSEL01 7
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0xC6)
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(3)
-#define PCINT0_vect_num        3
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT1_vect            _VECTOR(4)
-#define PCINT1_vect_num        4
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT2_vect            _VECTOR(5)
-#define PCINT2_vect_num        5
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect            _VECTOR(6)
-#define WDT_vect_num        6
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect            _VECTOR(7)
-#define TIMER2_COMPA_vect_num        7
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect            _VECTOR(8)
-#define TIMER2_COMPB_vect_num        8
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect            _VECTOR(9)
-#define TIMER2_OVF_vect_num        9
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(10)
-#define TIMER1_CAPT_vect_num        10
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect            _VECTOR(11)
-#define TIMER1_COMPA_vect_num        11
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect            _VECTOR(12)
-#define TIMER1_COMPB_vect_num        12
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(13)
-#define TIMER1_OVF_vect_num        13
-
-/* TimerCounter0 Compare Match A */
-#define TIMER0_COMPA_vect            _VECTOR(14)
-#define TIMER0_COMPA_vect_num        14
-
-/* TimerCounter0 Compare Match B */
-#define TIMER0_COMPB_vect            _VECTOR(15)
-#define TIMER0_COMPB_vect_num        15
-
-/* Timer/Couner0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(16)
-#define TIMER0_OVF_vect_num        16
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect            _VECTOR(17)
-#define SPI_STC_vect_num        17
-
-/* USART Rx Complete */
-#define USART_RX_vect            _VECTOR(18)
-#define USART_RX_vect_num        18
-
-/* USART, Data Register Empty */
-#define USART_UDRE_vect            _VECTOR(19)
-#define USART_UDRE_vect_num        19
-
-/* USART Tx Complete */
-#define USART_TX_vect            _VECTOR(20)
-#define USART_TX_vect_num        20
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(21)
-#define ADC_vect_num        21
-
-/* EEPROM Ready */
-#define EE_READY_vect            _VECTOR(22)
-#define EE_READY_vect_num        22
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect            _VECTOR(23)
-#define ANALOG_COMP_vect_num        23
-
-/* Two-wire Serial Interface */
-#define TWI_vect            _VECTOR(24)
-#define TWI_vect_num        24
-
-/* Store Program Memory Read */
-#define SPM_Ready_vect            _VECTOR(25)
-#define SPM_Ready_vect_num        25
-
-#define _VECTORS_SIZE 104
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x7FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      2048
-#define RAMEND       0x08FF
-#define E2START     0
-#define E2SIZE      1024
-#define E2PAGESIZE  4
-#define E2END       0x03FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT    (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x0F
-
-
-#endif /* #ifdef _AVR_ATA6614Q_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA6614Q_H_INCLUDED
+#define _AVR_ATA6614Q_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa6614q.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB0    0
+#define DDB1    1
+#define DDB2    2
+#define DDB3    3
+#define DDB4    4
+#define DDB5    5
+#define DDB6    6
+#define DDB7    7
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC0    0
+#define DDC1    1
+#define DDC2    2
+#define DDC3    3
+#define DDC4    4
+#define DDC5    5
+#define DDC6    6
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD0    0
+#define DDD1    1
+#define DDD2    2
+#define DDD3    3
+#define DDD4    4
+#define DDD5    5
+#define DDD6    6
+#define DDD7    7
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+/* Reserved [0x0C..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM     7
+#define PSRASY  1
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+/* Reserved [0x31..0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+#define BODSE   5
+#define BODS    6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62..0x63] */
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+/* Reserved [0x71..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCPHA0  1
+#define UDORD0  2
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT2_vect            _VECTOR(5)
+#define PCINT2_vect_num        5
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(6)
+#define WDT_vect_num        6
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(7)
+#define TIMER2_COMPA_vect_num        7
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect            _VECTOR(8)
+#define TIMER2_COMPB_vect_num        8
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(9)
+#define TIMER2_OVF_vect_num        9
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(10)
+#define TIMER1_CAPT_vect_num        10
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(11)
+#define TIMER1_COMPA_vect_num        11
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(12)
+#define TIMER1_COMPB_vect_num        12
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(13)
+#define TIMER1_OVF_vect_num        13
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(14)
+#define TIMER0_COMPA_vect_num        14
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(15)
+#define TIMER0_COMPB_vect_num        15
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(16)
+#define TIMER0_OVF_vect_num        16
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(17)
+#define SPI_STC_vect_num        17
+
+/* USART Rx Complete */
+#define USART_RX_vect            _VECTOR(18)
+#define USART_RX_vect_num        18
+
+/* USART, Data Register Empty */
+#define USART_UDRE_vect            _VECTOR(19)
+#define USART_UDRE_vect_num        19
+
+/* USART Tx Complete */
+#define USART_TX_vect            _VECTOR(20)
+#define USART_TX_vect_num        20
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(21)
+#define ADC_vect_num        21
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(22)
+#define EE_READY_vect_num        22
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect            _VECTOR(23)
+#define ANALOG_COMP_vect_num        23
+
+/* Two-wire Serial Interface */
+#define TWI_vect            _VECTOR(24)
+#define TWI_vect_num        24
+
+/* Store Program Memory Read */
+#define SPM_Ready_vect            _VECTOR(25)
+#define SPM_Ready_vect_num        25
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 104
+#else
+#  define _VECTORS_SIZE 104U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x7FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x7FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      2048
+#  define RAMEND       0x08FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      2048U
+#  define RAMEND       0x08FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  4
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  4U
+#  define E2END       0x03FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x0F
+
+
+
+
+#endif /* #ifdef _AVR_ATA6614Q_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa6616c.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa6616c.h
@@ -1,865 +1,875 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATA6616C_H_INCLUDED
-#define _AVR_ATA6616C_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa6616c.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA0    0
-#define DDA1    1
-#define DDA2    2
-#define DDA3    3
-#define DDA4    4
-#define DDA5    5
-#define DDA6    6
-#define DDA7    7
-
-#define PORTA   _SFR_IO8(0x02)
-#define PORTA7  7
-#define PORTA6  6
-#define PORTA5  5
-#define PORTA4  4
-#define PORTA3  3
-#define PORTA2  2
-#define PORTA1  1
-#define PORTA0  0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-/* Reserved [0x06..0x11] */
-
-#define PORTCR  _SFR_IO8(0x12)
-#define PUDA    0
-#define PUDB    1
-#define BBMA    4
-#define BBMB    5
-
-/* Reserved [0x13..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-/* Reserved [0x17..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-#define PCIF1   1
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define INT1    1
-
-#define GPIOR0  _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x20)
-#define EEDR0   0
-#define EEDR1   1
-#define EEDR2   2
-#define EEDR3   3
-#define EEDR4   4
-#define EEDR5   5
-#define EEDR6   6
-#define EEDR7   7
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR1    0
-#define PSR0    1
-#define TSM     7
-
-/* Reserved [0x24] */
-
-#define TCCR0A  _SFR_IO8(0x25)
-#define WGM00   0
-#define WGM01   1
-#define COM0A0  6
-#define COM0A1  7
-
-#define TCCR0B  _SFR_IO8(0x26)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define FOC0A   7
-
-#define TCNT0   _SFR_IO8(0x27)
-#define TCNT00  0
-#define TCNT01  1
-#define TCNT02  2
-#define TCNT03  3
-#define TCNT04  4
-#define TCNT05  5
-#define TCNT06  6
-#define TCNT07  7
-
-#define OCR0A   _SFR_IO8(0x28)
-#define OCR00   0
-#define OCR01   1
-#define OCR02   2
-#define OCR03   3
-#define OCR04   4
-#define OCR05   5
-#define OCR06   6
-#define OCR07   7
-
-/* Reserved [0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2  _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-#define SPDR0   0
-#define SPDR1   1
-#define SPDR2   2
-#define SPDR3   3
-#define SPDR4   4
-#define SPDR5   5
-#define SPDR6   6
-#define SPDR7   7
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACIRS   6
-#define ACD     7
-
-#define DWDR    _SFR_IO8(0x31)
-#define DWDR0   0
-#define DWDR1   1
-#define DWDR2   2
-#define DWDR3   3
-#define DWDR4   4
-#define DWDR5   5
-#define DWDR6   6
-#define DWDR7   7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define PUD     4
-#define BODSE   5
-#define BODS    6
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define RFLB    3
-#define CTPB    4
-#define SIGRD   5
-#define RWWSB   6
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDE     3
-#define WDCE    4
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-#define CLKCSR  _SFR_MEM8(0x62)
-#define CLKC0   0
-#define CLKC1   1
-#define CLKC2   2
-#define CLKC3   3
-#define CLKRDY  4
-#define CLKCCE  7
-
-#define CLKSELR _SFR_MEM8(0x63)
-#define CSEL0   0
-#define CSEL1   1
-#define CSEL2   2
-#define CSEL3   3
-#define CSUT0   4
-#define CSUT1   5
-#define COUT    6
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0
-#define PRUSI   1
-#define PRTIM0  2
-#define PRTIM1  3
-#define PRSPI   4
-#define PRLIN   5
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRUSI
-#define __AVR_HAVE_PRR_PRTIM0
-#define __AVR_HAVE_PRR_PRTIM1
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRLIN
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-#define CAL0    0
-#define CAL1    1
-#define CAL2    2
-#define CAL3    3
-#define CAL4    4
-#define CAL5    5
-#define CAL6    6
-#define CAL7    7
-#define OSCCAL0 0
-#define OSCCAL1 1
-#define OSCCAL2 2
-#define OSCCAL3 3
-#define OSCCAL4 4
-#define OSCCAL5 5
-#define OSCCAL6 6
-#define OSCCAL7 7
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-#define PCIE1   1
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-/* Reserved [0x70..0x76] */
-
-#define AMISCR  _SFR_MEM8(0x77)
-#define XREFEN  1
-#define AREFEN  2
-#define ISRCEN  0
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define BIN     7
-#define ACIR0   4
-#define ACIR1   5
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define ADC8D   4
-#define ADC9D   5
-#define ADC10D  6
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-#define TCCR1D  _SFR_MEM8(0x83)
-#define OC1AU   0
-#define OC1AV   1
-#define OC1AW   2
-#define OC1AX   3
-#define OC1BU   4
-#define OC1BV   5
-#define OC1BW   6
-#define OC1BX   7
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR0BUB 0
-#define TCR0AUB 1
-#define OCR0AUB 3
-#define TCN0UB  4
-#define AS0     5
-#define EXCLK   6
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-#define USIDR0  0
-#define USIDR1  1
-#define USIDR2  2
-#define USIDR3  3
-#define USIDR4  4
-#define USIDR5  5
-#define USIDR6  6
-#define USIDR7  7
-
-#define USIBR   _SFR_MEM8(0xBB)
-#define USIBR0  0
-#define USIBR1  1
-#define USIBR2  2
-#define USIBR3  3
-#define USIBR4  4
-#define USIBR5  5
-#define USIBR6  6
-#define USIBR7  7
-
-#define USIPP   _SFR_MEM8(0xBC)
-#define USIPOS  0
-
-/* Reserved [0xBD..0xC7] */
-
-#define LINCR   _SFR_MEM8(0xC8)
-#define LCMD0   0
-#define LCMD1   1
-#define LCMD2   2
-#define LENA    3
-#define LCONF0  4
-#define LCONF1  5
-#define LIN13   6
-#define LSWRES  7
-
-#define LINSIR  _SFR_MEM8(0xC9)
-#define LRXOK   0
-#define LTXOK   1
-#define LIDOK   2
-#define LERR    3
-#define LBUSY   4
-#define LIDST0  5
-#define LIDST1  6
-#define LIDST2  7
-
-#define LINENIR _SFR_MEM8(0xCA)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR  3
-
-#define LINERR  _SFR_MEM8(0xCB)
-#define LBERR   0
-#define LCERR   1
-#define LPERR   2
-#define LSERR   3
-#define LFERR   4
-#define LOVERR  5
-#define LTOERR  6
-#define LABORT  7
-
-#define LINBTR  _SFR_MEM8(0xCC)
-#define LBT0    0
-#define LBT1    1
-#define LBT2    2
-#define LBT3    3
-#define LBT4    4
-#define LBT5    5
-#define LDISR   7
-
-/* Combine LINBRRL and LINBRRH */
-#define LINBRR  _SFR_MEM16(0xCD)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LINBRRH _SFR_MEM8(0xCE)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LDIV0   0
-#define LDIV1   1
-#define LDIV2   2
-#define LDIV3   3
-#define LDIV4   4
-#define LDIV5   5
-#define LDIV6   6
-#define LDIV7   7
-
-#define LINBRRH _SFR_MEM8(0xCE)
-#define LDIV8   0
-#define LDIV9   1
-#define LDIV10  2
-#define LDIV11  3
-
-#define LINDLR  _SFR_MEM8(0xCF)
-#define LRXDL0  0
-#define LRXDL1  1
-#define LRXDL2  2
-#define LRXDL3  3
-#define LTXDL0  4
-#define LTXDL1  5
-#define LTXDL2  6
-#define LTXDL3  7
-
-#define LINIDR  _SFR_MEM8(0xD0)
-#define LID0    0
-#define LID1    1
-#define LID2    2
-#define LID3    3
-#define LID4    4
-#define LID5    5
-#define LP0     6
-#define LP1     7
-
-#define LINSEL  _SFR_MEM8(0xD1)
-#define LINDX0  0
-#define LINDX1  1
-#define LINDX2  2
-#define LAINC   3
-
-#define LINDAT  _SFR_MEM8(0xD2)
-#define LDATA0  0
-#define LDATA1  1
-#define LDATA2  2
-#define LDATA3  3
-#define LDATA4  4
-#define LDATA5  5
-#define LDATA6  6
-#define LDATA7  7
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(3)
-#define PCINT0_vect_num        3
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect            _VECTOR(4)
-#define PCINT1_vect_num        4
-
-/* Watchdog Time-Out Interrupt */
-#define WDT_vect            _VECTOR(5)
-#define WDT_vect_num        5
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(6)
-#define TIMER1_CAPT_vect_num        6
-
-/* Timer/Counter1 Compare Match 1A */
-#define TIMER1_COMPA_vect            _VECTOR(7)
-#define TIMER1_COMPA_vect_num        7
-
-/* Timer/Counter1 Compare Match 1B */
-#define TIMER1_COMPB_vect            _VECTOR(8)
-#define TIMER1_COMPB_vect_num        8
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(9)
-#define TIMER1_OVF_vect_num        9
-
-/* Timer/Counter0 Compare Match 0A */
-#define TIMER0_COMPA_vect            _VECTOR(10)
-#define TIMER0_COMPA_vect_num        10
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(11)
-#define TIMER0_OVF_vect_num        11
-
-/* LIN Transfer Complete */
-#define LIN_TC_vect            _VECTOR(12)
-#define LIN_TC_vect_num        12
-
-/* LIN Error */
-#define LIN_ERR_vect            _VECTOR(13)
-#define LIN_ERR_vect_num        13
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect            _VECTOR(14)
-#define SPI_STC_vect_num        14
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(15)
-#define ADC_vect_num        15
-
-/* EEPROM Ready */
-#define EE_RDY_vect            _VECTOR(16)
-#define EE_RDY_vect_num        16
-
-/* Analog Comparator */
-#define ANA_COMP_vect            _VECTOR(17)
-#define ANA_COMP_vect_num        17
-
-/* USI Start Condition Detection */
-#define USI_START_vect            _VECTOR(18)
-#define USI_START_vect_num        18
-
-/* USI Counter Overflow */
-#define USI_OVF_vect            _VECTOR(19)
-#define USI_OVF_vect_num        19
-
-#define _VECTORS_SIZE 40
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT    (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x87
-
-
-#endif /* #ifdef _AVR_ATA6616C_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA6616C_H_INCLUDED
+#define _AVR_ATA6616C_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa6616c.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDA0    0
+#define DDA1    1
+#define DDA2    2
+#define DDA3    3
+#define DDA4    4
+#define DDA5    5
+#define DDA6    6
+#define DDA7    7
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB0    0
+#define DDB1    1
+#define DDB2    2
+#define DDB3    3
+#define DDB4    4
+#define DDB5    5
+#define DDB6    6
+#define DDB7    7
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+/* Reserved [0x06..0x11] */
+
+#define PORTCR  _SFR_IO8(0x12)
+#define PUDA    0
+#define PUDB    1
+#define BBMA    4
+#define BBMB    5
+
+/* Reserved [0x13..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+/* Reserved [0x17..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+#define EEDR0   0
+#define EEDR1   1
+#define EEDR2   2
+#define EEDR3   3
+#define EEDR4   4
+#define EEDR5   5
+#define EEDR6   6
+#define EEDR7   7
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSR1    0
+#define PSR0    1
+#define TSM     7
+
+/* Reserved [0x24] */
+
+#define TCCR0A  _SFR_IO8(0x25)
+#define WGM00   0
+#define WGM01   1
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x26)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x27)
+#define TCNT00  0
+#define TCNT01  1
+#define TCNT02  2
+#define TCNT03  3
+#define TCNT04  4
+#define TCNT05  5
+#define TCNT06  6
+#define TCNT07  7
+
+#define OCR0A   _SFR_IO8(0x28)
+#define OCR00   0
+#define OCR01   1
+#define OCR02   2
+#define OCR03   3
+#define OCR04   4
+#define OCR05   5
+#define OCR06   6
+#define OCR07   7
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+#define SPDR0   0
+#define SPDR1   1
+#define SPDR2   2
+#define SPDR3   3
+#define SPDR4   4
+#define SPDR5   5
+#define SPDR6   6
+#define SPDR7   7
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACIRS   6
+#define ACD     7
+
+#define DWDR    _SFR_IO8(0x31)
+#define DWDR0   0
+#define DWDR1   1
+#define DWDR2   2
+#define DWDR3   3
+#define DWDR4   4
+#define DWDR5   5
+#define DWDR6   6
+#define DWDR7   7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define PUD     4
+#define BODSE   5
+#define BODS    6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define RFLB    3
+#define CTPB    4
+#define SIGRD   5
+#define RWWSB   6
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+#define CLKCSR  _SFR_MEM8(0x62)
+#define CLKC0   0
+#define CLKC1   1
+#define CLKC2   2
+#define CLKC3   3
+#define CLKRDY  4
+#define CLKCCE  7
+
+#define CLKSELR _SFR_MEM8(0x63)
+#define CSEL0   0
+#define CSEL1   1
+#define CSEL2   2
+#define CSEL3   3
+#define CSUT0   4
+#define CSUT1   5
+#define COUT    6
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSI   1
+#define PRTIM0  2
+#define PRTIM1  3
+#define PRSPI   4
+#define PRLIN   5
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRLIN
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define CAL0    0
+#define CAL1    1
+#define CAL2    2
+#define CAL3    3
+#define CAL4    4
+#define CAL5    5
+#define CAL6    6
+#define CAL7    7
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+/* Reserved [0x70..0x76] */
+
+#define AMISCR  _SFR_MEM8(0x77)
+#define XREFEN  1
+#define AREFEN  2
+#define ISRCEN  0
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define BIN     7
+#define ACIR0   4
+#define ACIR1   5
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define ADC8D   4
+#define ADC9D   5
+#define ADC10D  6
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+#define TCCR1D  _SFR_MEM8(0x83)
+#define OC1AU   0
+#define OC1AV   1
+#define OC1AW   2
+#define OC1AX   3
+#define OC1BU   4
+#define OC1BV   5
+#define OC1BW   6
+#define OC1BX   7
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR0BUB 0
+#define TCR0AUB 1
+#define OCR0AUB 3
+#define TCN0UB  4
+#define AS0     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define USICR   _SFR_MEM8(0xB8)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_MEM8(0xB9)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_MEM8(0xBA)
+#define USIDR0  0
+#define USIDR1  1
+#define USIDR2  2
+#define USIDR3  3
+#define USIDR4  4
+#define USIDR5  5
+#define USIDR6  6
+#define USIDR7  7
+
+#define USIBR   _SFR_MEM8(0xBB)
+#define USIBR0  0
+#define USIBR1  1
+#define USIBR2  2
+#define USIBR3  3
+#define USIBR4  4
+#define USIBR5  5
+#define USIBR6  6
+#define USIBR7  7
+
+#define USIPP   _SFR_MEM8(0xBC)
+#define USIPOS  0
+
+/* Reserved [0xBD..0xC7] */
+
+#define LINCR   _SFR_MEM8(0xC8)
+#define LCMD0   0
+#define LCMD1   1
+#define LCMD2   2
+#define LENA    3
+#define LCONF0  4
+#define LCONF1  5
+#define LIN13   6
+#define LSWRES  7
+
+#define LINSIR  _SFR_MEM8(0xC9)
+#define LRXOK   0
+#define LTXOK   1
+#define LIDOK   2
+#define LERR    3
+#define LBUSY   4
+#define LIDST0  5
+#define LIDST1  6
+#define LIDST2  7
+
+#define LINENIR _SFR_MEM8(0xCA)
+#define LENRXOK 0
+#define LENTXOK 1
+#define LENIDOK 2
+#define LENERR  3
+
+#define LINERR  _SFR_MEM8(0xCB)
+#define LBERR   0
+#define LCERR   1
+#define LPERR   2
+#define LSERR   3
+#define LFERR   4
+#define LOVERR  5
+#define LTOERR  6
+#define LABORT  7
+
+#define LINBTR  _SFR_MEM8(0xCC)
+#define LBT0    0
+#define LBT1    1
+#define LBT2    2
+#define LBT3    3
+#define LBT4    4
+#define LBT5    5
+#define LDISR   7
+
+/* Combine LINBRRL and LINBRRH */
+#define LINBRR  _SFR_MEM16(0xCD)
+
+#define LINBRRL _SFR_MEM8(0xCD)
+#define LINBRRH _SFR_MEM8(0xCE)
+
+#define LINBRRL _SFR_MEM8(0xCD)
+#define LDIV0   0
+#define LDIV1   1
+#define LDIV2   2
+#define LDIV3   3
+#define LDIV4   4
+#define LDIV5   5
+#define LDIV6   6
+#define LDIV7   7
+
+#define LINBRRH _SFR_MEM8(0xCE)
+#define LDIV8   0
+#define LDIV9   1
+#define LDIV10  2
+#define LDIV11  3
+
+#define LINDLR  _SFR_MEM8(0xCF)
+#define LRXDL0  0
+#define LRXDL1  1
+#define LRXDL2  2
+#define LRXDL3  3
+#define LTXDL0  4
+#define LTXDL1  5
+#define LTXDL2  6
+#define LTXDL3  7
+
+#define LINIDR  _SFR_MEM8(0xD0)
+#define LID0    0
+#define LID1    1
+#define LID2    2
+#define LID3    3
+#define LID4    4
+#define LID5    5
+#define LP0     6
+#define LP1     7
+
+#define LINSEL  _SFR_MEM8(0xD1)
+#define LINDX0  0
+#define LINDX1  1
+#define LINDX2  2
+#define LAINC   3
+
+#define LINDAT  _SFR_MEM8(0xD2)
+#define LDATA0  0
+#define LDATA1  1
+#define LDATA2  2
+#define LDATA3  3
+#define LDATA4  4
+#define LDATA5  5
+#define LDATA6  6
+#define LDATA7  7
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Watchdog Time-Out Interrupt */
+#define WDT_vect            _VECTOR(5)
+#define WDT_vect_num        5
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(6)
+#define TIMER1_CAPT_vect_num        6
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPA_vect            _VECTOR(7)
+#define TIMER1_COMPA_vect_num        7
+
+/* Timer/Counter1 Compare Match 1B */
+#define TIMER1_COMPB_vect            _VECTOR(8)
+#define TIMER1_COMPB_vect_num        8
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(9)
+#define TIMER1_OVF_vect_num        9
+
+/* Timer/Counter0 Compare Match 0A */
+#define TIMER0_COMPA_vect            _VECTOR(10)
+#define TIMER0_COMPA_vect_num        10
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(11)
+#define TIMER0_OVF_vect_num        11
+
+/* LIN Transfer Complete */
+#define LIN_TC_vect            _VECTOR(12)
+#define LIN_TC_vect_num        12
+
+/* LIN Error */
+#define LIN_ERR_vect            _VECTOR(13)
+#define LIN_ERR_vect_num        13
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(14)
+#define SPI_STC_vect_num        14
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(15)
+#define ADC_vect_num        15
+
+/* EEPROM Ready */
+#define EE_RDY_vect            _VECTOR(16)
+#define EE_RDY_vect_num        16
+
+/* Analog Comparator */
+#define ANA_COMP_vect            _VECTOR(17)
+#define ANA_COMP_vect_num        17
+
+/* USI Start Condition Detection */
+#define USI_START_vect            _VECTOR(18)
+#define USI_START_vect_num        18
+
+/* USI Counter Overflow */
+#define USI_OVF_vect            _VECTOR(19)
+#define USI_OVF_vect_num        19
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 40
+#else
+#  define _VECTORS_SIZE 40U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x87
+
+
+
+
+#endif /* #ifdef _AVR_ATA6616C_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa6617c.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa6617c.h
@@ -1,865 +1,875 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATA6617C_H_INCLUDED
-#define _AVR_ATA6617C_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa6617c.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA0    0
-#define DDA1    1
-#define DDA2    2
-#define DDA3    3
-#define DDA4    4
-#define DDA5    5
-#define DDA6    6
-#define DDA7    7
-
-#define PORTA   _SFR_IO8(0x02)
-#define PORTA7  7
-#define PORTA6  6
-#define PORTA5  5
-#define PORTA4  4
-#define PORTA3  3
-#define PORTA2  2
-#define PORTA1  1
-#define PORTA0  0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-/* Reserved [0x06..0x11] */
-
-#define PORTCR  _SFR_IO8(0x12)
-#define PUDA    0
-#define PUDB    1
-#define BBMA    4
-#define BBMB    5
-
-/* Reserved [0x13..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-/* Reserved [0x17..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-#define PCIF1   1
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define INT1    1
-
-#define GPIOR0  _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x20)
-#define EEDR0   0
-#define EEDR1   1
-#define EEDR2   2
-#define EEDR3   3
-#define EEDR4   4
-#define EEDR5   5
-#define EEDR6   6
-#define EEDR7   7
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR1    0
-#define PSR0    1
-#define TSM     7
-
-/* Reserved [0x24] */
-
-#define TCCR0A  _SFR_IO8(0x25)
-#define WGM00   0
-#define WGM01   1
-#define COM0A0  6
-#define COM0A1  7
-
-#define TCCR0B  _SFR_IO8(0x26)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define FOC0A   7
-
-#define TCNT0   _SFR_IO8(0x27)
-#define TCNT00  0
-#define TCNT01  1
-#define TCNT02  2
-#define TCNT03  3
-#define TCNT04  4
-#define TCNT05  5
-#define TCNT06  6
-#define TCNT07  7
-
-#define OCR0A   _SFR_IO8(0x28)
-#define OCR00   0
-#define OCR01   1
-#define OCR02   2
-#define OCR03   3
-#define OCR04   4
-#define OCR05   5
-#define OCR06   6
-#define OCR07   7
-
-/* Reserved [0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2  _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-#define SPDR0   0
-#define SPDR1   1
-#define SPDR2   2
-#define SPDR3   3
-#define SPDR4   4
-#define SPDR5   5
-#define SPDR6   6
-#define SPDR7   7
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACIRS   6
-#define ACD     7
-
-#define DWDR    _SFR_IO8(0x31)
-#define DWDR0   0
-#define DWDR1   1
-#define DWDR2   2
-#define DWDR3   3
-#define DWDR4   4
-#define DWDR5   5
-#define DWDR6   6
-#define DWDR7   7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define PUD     4
-#define BODSE   5
-#define BODS    6
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define RFLB    3
-#define CTPB    4
-#define SIGRD   5
-#define RWWSB   6
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDE     3
-#define WDCE    4
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-#define CLKCSR  _SFR_MEM8(0x62)
-#define CLKC0   0
-#define CLKC1   1
-#define CLKC2   2
-#define CLKC3   3
-#define CLKRDY  4
-#define CLKCCE  7
-
-#define CLKSELR _SFR_MEM8(0x63)
-#define CSEL0   0
-#define CSEL1   1
-#define CSEL2   2
-#define CSEL3   3
-#define CSUT0   4
-#define CSUT1   5
-#define COUT    6
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0
-#define PRUSI   1
-#define PRTIM0  2
-#define PRTIM1  3
-#define PRSPI   4
-#define PRLIN   5
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRUSI
-#define __AVR_HAVE_PRR_PRTIM0
-#define __AVR_HAVE_PRR_PRTIM1
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRLIN
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-#define CAL0    0
-#define CAL1    1
-#define CAL2    2
-#define CAL3    3
-#define CAL4    4
-#define CAL5    5
-#define CAL6    6
-#define CAL7    7
-#define OSCCAL0 0
-#define OSCCAL1 1
-#define OSCCAL2 2
-#define OSCCAL3 3
-#define OSCCAL4 4
-#define OSCCAL5 5
-#define OSCCAL6 6
-#define OSCCAL7 7
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-#define PCIE1   1
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-/* Reserved [0x70..0x76] */
-
-#define AMISCR  _SFR_MEM8(0x77)
-#define XREFEN  1
-#define AREFEN  2
-#define ISRCEN  0
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define BIN     7
-#define ACIR0   4
-#define ACIR1   5
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define ADC8D   4
-#define ADC9D   5
-#define ADC10D  6
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-#define TCCR1D  _SFR_MEM8(0x83)
-#define OC1AU   0
-#define OC1AV   1
-#define OC1AW   2
-#define OC1AX   3
-#define OC1BU   4
-#define OC1BV   5
-#define OC1BW   6
-#define OC1BX   7
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR0BUB 0
-#define TCR0AUB 1
-#define OCR0AUB 3
-#define TCN0UB  4
-#define AS0     5
-#define EXCLK   6
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-#define USIDR0  0
-#define USIDR1  1
-#define USIDR2  2
-#define USIDR3  3
-#define USIDR4  4
-#define USIDR5  5
-#define USIDR6  6
-#define USIDR7  7
-
-#define USIBR   _SFR_MEM8(0xBB)
-#define USIBR0  0
-#define USIBR1  1
-#define USIBR2  2
-#define USIBR3  3
-#define USIBR4  4
-#define USIBR5  5
-#define USIBR6  6
-#define USIBR7  7
-
-#define USIPP   _SFR_MEM8(0xBC)
-#define USIPOS  0
-
-/* Reserved [0xBD..0xC7] */
-
-#define LINCR   _SFR_MEM8(0xC8)
-#define LCMD0   0
-#define LCMD1   1
-#define LCMD2   2
-#define LENA    3
-#define LCONF0  4
-#define LCONF1  5
-#define LIN13   6
-#define LSWRES  7
-
-#define LINSIR  _SFR_MEM8(0xC9)
-#define LRXOK   0
-#define LTXOK   1
-#define LIDOK   2
-#define LERR    3
-#define LBUSY   4
-#define LIDST0  5
-#define LIDST1  6
-#define LIDST2  7
-
-#define LINENIR _SFR_MEM8(0xCA)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR  3
-
-#define LINERR  _SFR_MEM8(0xCB)
-#define LBERR   0
-#define LCERR   1
-#define LPERR   2
-#define LSERR   3
-#define LFERR   4
-#define LOVERR  5
-#define LTOERR  6
-#define LABORT  7
-
-#define LINBTR  _SFR_MEM8(0xCC)
-#define LBT0    0
-#define LBT1    1
-#define LBT2    2
-#define LBT3    3
-#define LBT4    4
-#define LBT5    5
-#define LDISR   7
-
-/* Combine LINBRRL and LINBRRH */
-#define LINBRR  _SFR_MEM16(0xCD)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LINBRRH _SFR_MEM8(0xCE)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LDIV0   0
-#define LDIV1   1
-#define LDIV2   2
-#define LDIV3   3
-#define LDIV4   4
-#define LDIV5   5
-#define LDIV6   6
-#define LDIV7   7
-
-#define LINBRRH _SFR_MEM8(0xCE)
-#define LDIV8   0
-#define LDIV9   1
-#define LDIV10  2
-#define LDIV11  3
-
-#define LINDLR  _SFR_MEM8(0xCF)
-#define LRXDL0  0
-#define LRXDL1  1
-#define LRXDL2  2
-#define LRXDL3  3
-#define LTXDL0  4
-#define LTXDL1  5
-#define LTXDL2  6
-#define LTXDL3  7
-
-#define LINIDR  _SFR_MEM8(0xD0)
-#define LID0    0
-#define LID1    1
-#define LID2    2
-#define LID3    3
-#define LID4    4
-#define LID5    5
-#define LP0     6
-#define LP1     7
-
-#define LINSEL  _SFR_MEM8(0xD1)
-#define LINDX0  0
-#define LINDX1  1
-#define LINDX2  2
-#define LAINC   3
-
-#define LINDAT  _SFR_MEM8(0xD2)
-#define LDATA0  0
-#define LDATA1  1
-#define LDATA2  2
-#define LDATA3  3
-#define LDATA4  4
-#define LDATA5  5
-#define LDATA6  6
-#define LDATA7  7
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(3)
-#define PCINT0_vect_num        3
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect            _VECTOR(4)
-#define PCINT1_vect_num        4
-
-/* Watchdog Time-Out Interrupt */
-#define WDT_vect            _VECTOR(5)
-#define WDT_vect_num        5
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(6)
-#define TIMER1_CAPT_vect_num        6
-
-/* Timer/Counter1 Compare Match 1A */
-#define TIMER1_COMPA_vect            _VECTOR(7)
-#define TIMER1_COMPA_vect_num        7
-
-/* Timer/Counter1 Compare Match 1B */
-#define TIMER1_COMPB_vect            _VECTOR(8)
-#define TIMER1_COMPB_vect_num        8
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(9)
-#define TIMER1_OVF_vect_num        9
-
-/* Timer/Counter0 Compare Match 0A */
-#define TIMER0_COMPA_vect            _VECTOR(10)
-#define TIMER0_COMPA_vect_num        10
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(11)
-#define TIMER0_OVF_vect_num        11
-
-/* LIN Transfer Complete */
-#define LIN_TC_vect            _VECTOR(12)
-#define LIN_TC_vect_num        12
-
-/* LIN Error */
-#define LIN_ERR_vect            _VECTOR(13)
-#define LIN_ERR_vect_num        13
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect            _VECTOR(14)
-#define SPI_STC_vect_num        14
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(15)
-#define ADC_vect_num        15
-
-/* EEPROM Ready */
-#define EE_RDY_vect            _VECTOR(16)
-#define EE_RDY_vect_num        16
-
-/* Analog Comparator */
-#define ANA_COMP_vect            _VECTOR(17)
-#define ANA_COMP_vect_num        17
-
-/* USI Start Condition Detection */
-#define USI_START_vect            _VECTOR(18)
-#define USI_START_vect_num        18
-
-/* USI Counter Overflow */
-#define USI_OVF_vect            _VECTOR(19)
-#define USI_OVF_vect_num        19
-
-#define _VECTORS_SIZE 80
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT    (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x87
-
-
-#endif /* #ifdef _AVR_ATA6617C_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA6617C_H_INCLUDED
+#define _AVR_ATA6617C_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa6617c.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDA0    0
+#define DDA1    1
+#define DDA2    2
+#define DDA3    3
+#define DDA4    4
+#define DDA5    5
+#define DDA6    6
+#define DDA7    7
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB0    0
+#define DDB1    1
+#define DDB2    2
+#define DDB3    3
+#define DDB4    4
+#define DDB5    5
+#define DDB6    6
+#define DDB7    7
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+/* Reserved [0x06..0x11] */
+
+#define PORTCR  _SFR_IO8(0x12)
+#define PUDA    0
+#define PUDB    1
+#define BBMA    4
+#define BBMB    5
+
+/* Reserved [0x13..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+/* Reserved [0x17..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+#define EEDR0   0
+#define EEDR1   1
+#define EEDR2   2
+#define EEDR3   3
+#define EEDR4   4
+#define EEDR5   5
+#define EEDR6   6
+#define EEDR7   7
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSR1    0
+#define PSR0    1
+#define TSM     7
+
+/* Reserved [0x24] */
+
+#define TCCR0A  _SFR_IO8(0x25)
+#define WGM00   0
+#define WGM01   1
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x26)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x27)
+#define TCNT00  0
+#define TCNT01  1
+#define TCNT02  2
+#define TCNT03  3
+#define TCNT04  4
+#define TCNT05  5
+#define TCNT06  6
+#define TCNT07  7
+
+#define OCR0A   _SFR_IO8(0x28)
+#define OCR00   0
+#define OCR01   1
+#define OCR02   2
+#define OCR03   3
+#define OCR04   4
+#define OCR05   5
+#define OCR06   6
+#define OCR07   7
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+#define SPDR0   0
+#define SPDR1   1
+#define SPDR2   2
+#define SPDR3   3
+#define SPDR4   4
+#define SPDR5   5
+#define SPDR6   6
+#define SPDR7   7
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACIRS   6
+#define ACD     7
+
+#define DWDR    _SFR_IO8(0x31)
+#define DWDR0   0
+#define DWDR1   1
+#define DWDR2   2
+#define DWDR3   3
+#define DWDR4   4
+#define DWDR5   5
+#define DWDR6   6
+#define DWDR7   7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define PUD     4
+#define BODSE   5
+#define BODS    6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define RFLB    3
+#define CTPB    4
+#define SIGRD   5
+#define RWWSB   6
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+#define CLKCSR  _SFR_MEM8(0x62)
+#define CLKC0   0
+#define CLKC1   1
+#define CLKC2   2
+#define CLKC3   3
+#define CLKRDY  4
+#define CLKCCE  7
+
+#define CLKSELR _SFR_MEM8(0x63)
+#define CSEL0   0
+#define CSEL1   1
+#define CSEL2   2
+#define CSEL3   3
+#define CSUT0   4
+#define CSUT1   5
+#define COUT    6
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSI   1
+#define PRTIM0  2
+#define PRTIM1  3
+#define PRSPI   4
+#define PRLIN   5
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRLIN
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define CAL0    0
+#define CAL1    1
+#define CAL2    2
+#define CAL3    3
+#define CAL4    4
+#define CAL5    5
+#define CAL6    6
+#define CAL7    7
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+/* Reserved [0x70..0x76] */
+
+#define AMISCR  _SFR_MEM8(0x77)
+#define XREFEN  1
+#define AREFEN  2
+#define ISRCEN  0
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define BIN     7
+#define ACIR0   4
+#define ACIR1   5
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define ADC8D   4
+#define ADC9D   5
+#define ADC10D  6
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+#define TCCR1D  _SFR_MEM8(0x83)
+#define OC1AU   0
+#define OC1AV   1
+#define OC1AW   2
+#define OC1AX   3
+#define OC1BU   4
+#define OC1BV   5
+#define OC1BW   6
+#define OC1BX   7
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR0BUB 0
+#define TCR0AUB 1
+#define OCR0AUB 3
+#define TCN0UB  4
+#define AS0     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define USICR   _SFR_MEM8(0xB8)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_MEM8(0xB9)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_MEM8(0xBA)
+#define USIDR0  0
+#define USIDR1  1
+#define USIDR2  2
+#define USIDR3  3
+#define USIDR4  4
+#define USIDR5  5
+#define USIDR6  6
+#define USIDR7  7
+
+#define USIBR   _SFR_MEM8(0xBB)
+#define USIBR0  0
+#define USIBR1  1
+#define USIBR2  2
+#define USIBR3  3
+#define USIBR4  4
+#define USIBR5  5
+#define USIBR6  6
+#define USIBR7  7
+
+#define USIPP   _SFR_MEM8(0xBC)
+#define USIPOS  0
+
+/* Reserved [0xBD..0xC7] */
+
+#define LINCR   _SFR_MEM8(0xC8)
+#define LCMD0   0
+#define LCMD1   1
+#define LCMD2   2
+#define LENA    3
+#define LCONF0  4
+#define LCONF1  5
+#define LIN13   6
+#define LSWRES  7
+
+#define LINSIR  _SFR_MEM8(0xC9)
+#define LRXOK   0
+#define LTXOK   1
+#define LIDOK   2
+#define LERR    3
+#define LBUSY   4
+#define LIDST0  5
+#define LIDST1  6
+#define LIDST2  7
+
+#define LINENIR _SFR_MEM8(0xCA)
+#define LENRXOK 0
+#define LENTXOK 1
+#define LENIDOK 2
+#define LENERR  3
+
+#define LINERR  _SFR_MEM8(0xCB)
+#define LBERR   0
+#define LCERR   1
+#define LPERR   2
+#define LSERR   3
+#define LFERR   4
+#define LOVERR  5
+#define LTOERR  6
+#define LABORT  7
+
+#define LINBTR  _SFR_MEM8(0xCC)
+#define LBT0    0
+#define LBT1    1
+#define LBT2    2
+#define LBT3    3
+#define LBT4    4
+#define LBT5    5
+#define LDISR   7
+
+/* Combine LINBRRL and LINBRRH */
+#define LINBRR  _SFR_MEM16(0xCD)
+
+#define LINBRRL _SFR_MEM8(0xCD)
+#define LINBRRH _SFR_MEM8(0xCE)
+
+#define LINBRRL _SFR_MEM8(0xCD)
+#define LDIV0   0
+#define LDIV1   1
+#define LDIV2   2
+#define LDIV3   3
+#define LDIV4   4
+#define LDIV5   5
+#define LDIV6   6
+#define LDIV7   7
+
+#define LINBRRH _SFR_MEM8(0xCE)
+#define LDIV8   0
+#define LDIV9   1
+#define LDIV10  2
+#define LDIV11  3
+
+#define LINDLR  _SFR_MEM8(0xCF)
+#define LRXDL0  0
+#define LRXDL1  1
+#define LRXDL2  2
+#define LRXDL3  3
+#define LTXDL0  4
+#define LTXDL1  5
+#define LTXDL2  6
+#define LTXDL3  7
+
+#define LINIDR  _SFR_MEM8(0xD0)
+#define LID0    0
+#define LID1    1
+#define LID2    2
+#define LID3    3
+#define LID4    4
+#define LID5    5
+#define LP0     6
+#define LP1     7
+
+#define LINSEL  _SFR_MEM8(0xD1)
+#define LINDX0  0
+#define LINDX1  1
+#define LINDX2  2
+#define LAINC   3
+
+#define LINDAT  _SFR_MEM8(0xD2)
+#define LDATA0  0
+#define LDATA1  1
+#define LDATA2  2
+#define LDATA3  3
+#define LDATA4  4
+#define LDATA5  5
+#define LDATA6  6
+#define LDATA7  7
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Watchdog Time-Out Interrupt */
+#define WDT_vect            _VECTOR(5)
+#define WDT_vect_num        5
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(6)
+#define TIMER1_CAPT_vect_num        6
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPA_vect            _VECTOR(7)
+#define TIMER1_COMPA_vect_num        7
+
+/* Timer/Counter1 Compare Match 1B */
+#define TIMER1_COMPB_vect            _VECTOR(8)
+#define TIMER1_COMPB_vect_num        8
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(9)
+#define TIMER1_OVF_vect_num        9
+
+/* Timer/Counter0 Compare Match 0A */
+#define TIMER0_COMPA_vect            _VECTOR(10)
+#define TIMER0_COMPA_vect_num        10
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(11)
+#define TIMER0_OVF_vect_num        11
+
+/* LIN Transfer Complete */
+#define LIN_TC_vect            _VECTOR(12)
+#define LIN_TC_vect_num        12
+
+/* LIN Error */
+#define LIN_ERR_vect            _VECTOR(13)
+#define LIN_ERR_vect_num        13
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(14)
+#define SPI_STC_vect_num        14
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(15)
+#define ADC_vect_num        15
+
+/* EEPROM Ready */
+#define EE_RDY_vect            _VECTOR(16)
+#define EE_RDY_vect_num        16
+
+/* Analog Comparator */
+#define ANA_COMP_vect            _VECTOR(17)
+#define ANA_COMP_vect_num        17
+
+/* USI Start Condition Detection */
+#define USI_START_vect            _VECTOR(18)
+#define USI_START_vect_num        18
+
+/* USI Counter Overflow */
+#define USI_OVF_vect            _VECTOR(19)
+#define USI_OVF_vect_num        19
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 80
+#else
+#  define _VECTORS_SIZE 80U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x87
+
+
+
+
+#endif /* #ifdef _AVR_ATA6617C_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa664251.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa664251.h
@@ -1,857 +1,867 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATA664251_H_INCLUDED
-#define _AVR_ATA664251_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa664251.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA0    0
-#define DDA1    1
-#define DDA2    2
-#define DDA3    3
-#define DDA4    4
-#define DDA5    5
-#define DDA6    6
-#define DDA7    7
-
-#define PORTA   _SFR_IO8(0x02)
-#define PORTA7  7
-#define PORTA6  6
-#define PORTA5  5
-#define PORTA4  4
-#define PORTA3  3
-#define PORTA2  2
-#define PORTA1  1
-#define PORTA0  0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-/* Reserved [0x06..0x11] */
-
-#define PORTCR  _SFR_IO8(0x12)
-#define PUDA    0
-#define PUDB    1
-#define BBMA    4
-#define BBMB    5
-
-/* Reserved [0x13..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-/* Reserved [0x17..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-#define PCIF1   1
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define INT1    1
-
-#define GPIOR0  _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x20)
-#define EEDR0   0
-#define EEDR1   1
-#define EEDR2   2
-#define EEDR3   3
-#define EEDR4   4
-#define EEDR5   5
-#define EEDR6   6
-#define EEDR7   7
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR1    0
-#define PSR0    1
-#define TSM     7
-
-/* Reserved [0x24] */
-
-#define TCCR0A  _SFR_IO8(0x25)
-#define WGM00   0
-#define WGM01   1
-#define COM0A0  6
-#define COM0A1  7
-
-#define TCCR0B  _SFR_IO8(0x26)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define FOC0A   7
-
-#define TCNT0   _SFR_IO8(0x27)
-#define TCNT00  0
-#define TCNT01  1
-#define TCNT02  2
-#define TCNT03  3
-#define TCNT04  4
-#define TCNT05  5
-#define TCNT06  6
-#define TCNT07  7
-
-#define OCR0A   _SFR_IO8(0x28)
-#define OCR00   0
-#define OCR01   1
-#define OCR02   2
-#define OCR03   3
-#define OCR04   4
-#define OCR05   5
-#define OCR06   6
-#define OCR07   7
-
-/* Reserved [0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2  _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-#define SPDR0   0
-#define SPDR1   1
-#define SPDR2   2
-#define SPDR3   3
-#define SPDR4   4
-#define SPDR5   5
-#define SPDR6   6
-#define SPDR7   7
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACIRS   6
-#define ACD     7
-
-#define DWDR    _SFR_IO8(0x31)
-#define DWDR0   0
-#define DWDR1   1
-#define DWDR2   2
-#define DWDR3   3
-#define DWDR4   4
-#define DWDR5   5
-#define DWDR6   6
-#define DWDR7   7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define PUD     4
-#define BODSE   5
-#define BODS    6
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define RFLB    3
-#define CTPB    4
-#define SIGRD   5
-#define RWWSB   6
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDE     3
-#define WDCE    4
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-#define CLKCSR  _SFR_MEM8(0x62)
-#define CLKC0   0
-#define CLKC1   1
-#define CLKC2   2
-#define CLKC3   3
-#define CLKRDY  4
-#define CLKCCE  7
-
-#define CLKSELR _SFR_MEM8(0x63)
-#define CSEL0   0
-#define CSEL1   1
-#define CSEL2   2
-#define CSEL3   3
-#define CSUT0   4
-#define CSUT1   5
-#define COUT    6
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0
-#define PRUSI   1
-#define PRTIM0  2
-#define PRTIM1  3
-#define PRSPI   4
-#define PRLIN   5
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRUSI
-#define __AVR_HAVE_PRR_PRTIM0
-#define __AVR_HAVE_PRR_PRTIM1
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRLIN
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-#define OSCCAL0 0
-#define OSCCAL1 1
-#define OSCCAL2 2
-#define OSCCAL3 3
-#define OSCCAL4 4
-#define OSCCAL5 5
-#define OSCCAL6 6
-#define OSCCAL7 7
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-#define PCIE1   1
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-/* Reserved [0x70..0x76] */
-
-#define AMISCR  _SFR_MEM8(0x77)
-#define XREFEN  1
-#define AREFEN  2
-#define ISRCEN  0
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define BIN     7
-#define ACIR0   4
-#define ACIR1   5
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define ADC8D   4
-#define ADC9D   5
-#define ADC10D  6
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-#define TCCR1D  _SFR_MEM8(0x83)
-#define OC1AU   0
-#define OC1AV   1
-#define OC1AW   2
-#define OC1AX   3
-#define OC1BU   4
-#define OC1BV   5
-#define OC1BW   6
-#define OC1BX   7
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR0BUB 0
-#define TCR0AUB 1
-#define OCR0AUB 3
-#define TCN0UB  4
-#define AS0     5
-#define EXCLK   6
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-#define USIDR0  0
-#define USIDR1  1
-#define USIDR2  2
-#define USIDR3  3
-#define USIDR4  4
-#define USIDR5  5
-#define USIDR6  6
-#define USIDR7  7
-
-#define USIBR   _SFR_MEM8(0xBB)
-#define USIBR0  0
-#define USIBR1  1
-#define USIBR2  2
-#define USIBR3  3
-#define USIBR4  4
-#define USIBR5  5
-#define USIBR6  6
-#define USIBR7  7
-
-#define USIPP   _SFR_MEM8(0xBC)
-#define USIPOS  0
-
-/* Reserved [0xBD..0xC7] */
-
-#define LINCR   _SFR_MEM8(0xC8)
-#define LCMD0   0
-#define LCMD1   1
-#define LCMD2   2
-#define LENA    3
-#define LCONF0  4
-#define LCONF1  5
-#define LIN13   6
-#define LSWRES  7
-
-#define LINSIR  _SFR_MEM8(0xC9)
-#define LRXOK   0
-#define LTXOK   1
-#define LIDOK   2
-#define LERR    3
-#define LBUSY   4
-#define LIDST0  5
-#define LIDST1  6
-#define LIDST2  7
-
-#define LINENIR _SFR_MEM8(0xCA)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR  3
-
-#define LINERR  _SFR_MEM8(0xCB)
-#define LBERR   0
-#define LCERR   1
-#define LPERR   2
-#define LSERR   3
-#define LFERR   4
-#define LOVERR  5
-#define LTOERR  6
-#define LABORT  7
-
-#define LINBTR  _SFR_MEM8(0xCC)
-#define LBT0    0
-#define LBT1    1
-#define LBT2    2
-#define LBT3    3
-#define LBT4    4
-#define LBT5    5
-#define LDISR   7
-
-/* Combine LINBRRL and LINBRRH */
-#define LINBRR  _SFR_MEM16(0xCD)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LINBRRH _SFR_MEM8(0xCE)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LDIV0   0
-#define LDIV1   1
-#define LDIV2   2
-#define LDIV3   3
-#define LDIV4   4
-#define LDIV5   5
-#define LDIV6   6
-#define LDIV7   7
-
-#define LINBRRH _SFR_MEM8(0xCE)
-#define LDIV8   0
-#define LDIV9   1
-#define LDIV10  2
-#define LDIV11  3
-
-#define LINDLR  _SFR_MEM8(0xCF)
-#define LRXDL0  0
-#define LRXDL1  1
-#define LRXDL2  2
-#define LRXDL3  3
-#define LTXDL0  4
-#define LTXDL1  5
-#define LTXDL2  6
-#define LTXDL3  7
-
-#define LINIDR  _SFR_MEM8(0xD0)
-#define LID0    0
-#define LID1    1
-#define LID2    2
-#define LID3    3
-#define LID4    4
-#define LID5    5
-#define LP0     6
-#define LP1     7
-
-#define LINSEL  _SFR_MEM8(0xD1)
-#define LINDX0  0
-#define LINDX1  1
-#define LINDX2  2
-#define LAINC   3
-
-#define LINDAT  _SFR_MEM8(0xD2)
-#define LDATA0  0
-#define LDATA1  1
-#define LDATA2  2
-#define LDATA3  3
-#define LDATA4  4
-#define LDATA5  5
-#define LDATA6  6
-#define LDATA7  7
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(3)
-#define PCINT0_vect_num        3
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect            _VECTOR(4)
-#define PCINT1_vect_num        4
-
-/* Watchdog Time-Out Interrupt */
-#define WDT_vect            _VECTOR(5)
-#define WDT_vect_num        5
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(6)
-#define TIMER1_CAPT_vect_num        6
-
-/* Timer/Counter1 Compare Match 1A */
-#define TIMER1_COMPA_vect            _VECTOR(7)
-#define TIMER1_COMPA_vect_num        7
-
-/* Timer/Counter1 Compare Match 1B */
-#define TIMER1_COMPB_vect            _VECTOR(8)
-#define TIMER1_COMPB_vect_num        8
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(9)
-#define TIMER1_OVF_vect_num        9
-
-/* Timer/Counter0 Compare Match 0A */
-#define TIMER0_COMPA_vect            _VECTOR(10)
-#define TIMER0_COMPA_vect_num        10
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(11)
-#define TIMER0_OVF_vect_num        11
-
-/* LIN Transfer Complete */
-#define LIN_TC_vect            _VECTOR(12)
-#define LIN_TC_vect_num        12
-
-/* LIN Error */
-#define LIN_ERR_vect            _VECTOR(13)
-#define LIN_ERR_vect_num        13
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect            _VECTOR(14)
-#define SPI_STC_vect_num        14
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(15)
-#define ADC_vect_num        15
-
-/* EEPROM Ready */
-#define EE_RDY_vect            _VECTOR(16)
-#define EE_RDY_vect_num        16
-
-/* Analog Comparator */
-#define ANA_COMP_vect            _VECTOR(17)
-#define ANA_COMP_vect_num        17
-
-/* USI Start Condition Detection */
-#define USI_START_vect            _VECTOR(18)
-#define USI_START_vect_num        18
-
-/* USI Counter Overflow */
-#define USI_OVF_vect            _VECTOR(19)
-#define USI_OVF_vect_num        19
-
-#define _VECTORS_SIZE 80
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT    (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x87
-
-
-#endif /* #ifdef _AVR_ATA664251_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA664251_H_INCLUDED
+#define _AVR_ATA664251_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa664251.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDA0    0
+#define DDA1    1
+#define DDA2    2
+#define DDA3    3
+#define DDA4    4
+#define DDA5    5
+#define DDA6    6
+#define DDA7    7
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB0    0
+#define DDB1    1
+#define DDB2    2
+#define DDB3    3
+#define DDB4    4
+#define DDB5    5
+#define DDB6    6
+#define DDB7    7
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+/* Reserved [0x06..0x11] */
+
+#define PORTCR  _SFR_IO8(0x12)
+#define PUDA    0
+#define PUDB    1
+#define BBMA    4
+#define BBMB    5
+
+/* Reserved [0x13..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+/* Reserved [0x17..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+#define EEDR0   0
+#define EEDR1   1
+#define EEDR2   2
+#define EEDR3   3
+#define EEDR4   4
+#define EEDR5   5
+#define EEDR6   6
+#define EEDR7   7
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSR1    0
+#define PSR0    1
+#define TSM     7
+
+/* Reserved [0x24] */
+
+#define TCCR0A  _SFR_IO8(0x25)
+#define WGM00   0
+#define WGM01   1
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x26)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x27)
+#define TCNT00  0
+#define TCNT01  1
+#define TCNT02  2
+#define TCNT03  3
+#define TCNT04  4
+#define TCNT05  5
+#define TCNT06  6
+#define TCNT07  7
+
+#define OCR0A   _SFR_IO8(0x28)
+#define OCR00   0
+#define OCR01   1
+#define OCR02   2
+#define OCR03   3
+#define OCR04   4
+#define OCR05   5
+#define OCR06   6
+#define OCR07   7
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+#define SPDR0   0
+#define SPDR1   1
+#define SPDR2   2
+#define SPDR3   3
+#define SPDR4   4
+#define SPDR5   5
+#define SPDR6   6
+#define SPDR7   7
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACIRS   6
+#define ACD     7
+
+#define DWDR    _SFR_IO8(0x31)
+#define DWDR0   0
+#define DWDR1   1
+#define DWDR2   2
+#define DWDR3   3
+#define DWDR4   4
+#define DWDR5   5
+#define DWDR6   6
+#define DWDR7   7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define PUD     4
+#define BODSE   5
+#define BODS    6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define RFLB    3
+#define CTPB    4
+#define SIGRD   5
+#define RWWSB   6
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+#define CLKCSR  _SFR_MEM8(0x62)
+#define CLKC0   0
+#define CLKC1   1
+#define CLKC2   2
+#define CLKC3   3
+#define CLKRDY  4
+#define CLKCCE  7
+
+#define CLKSELR _SFR_MEM8(0x63)
+#define CSEL0   0
+#define CSEL1   1
+#define CSEL2   2
+#define CSEL3   3
+#define CSUT0   4
+#define CSUT1   5
+#define COUT    6
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSI   1
+#define PRTIM0  2
+#define PRTIM1  3
+#define PRSPI   4
+#define PRLIN   5
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRLIN
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+/* Reserved [0x70..0x76] */
+
+#define AMISCR  _SFR_MEM8(0x77)
+#define XREFEN  1
+#define AREFEN  2
+#define ISRCEN  0
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define BIN     7
+#define ACIR0   4
+#define ACIR1   5
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define ADC8D   4
+#define ADC9D   5
+#define ADC10D  6
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+#define TCCR1D  _SFR_MEM8(0x83)
+#define OC1AU   0
+#define OC1AV   1
+#define OC1AW   2
+#define OC1AX   3
+#define OC1BU   4
+#define OC1BV   5
+#define OC1BW   6
+#define OC1BX   7
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR0BUB 0
+#define TCR0AUB 1
+#define OCR0AUB 3
+#define TCN0UB  4
+#define AS0     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define USICR   _SFR_MEM8(0xB8)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_MEM8(0xB9)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_MEM8(0xBA)
+#define USIDR0  0
+#define USIDR1  1
+#define USIDR2  2
+#define USIDR3  3
+#define USIDR4  4
+#define USIDR5  5
+#define USIDR6  6
+#define USIDR7  7
+
+#define USIBR   _SFR_MEM8(0xBB)
+#define USIBR0  0
+#define USIBR1  1
+#define USIBR2  2
+#define USIBR3  3
+#define USIBR4  4
+#define USIBR5  5
+#define USIBR6  6
+#define USIBR7  7
+
+#define USIPP   _SFR_MEM8(0xBC)
+#define USIPOS  0
+
+/* Reserved [0xBD..0xC7] */
+
+#define LINCR   _SFR_MEM8(0xC8)
+#define LCMD0   0
+#define LCMD1   1
+#define LCMD2   2
+#define LENA    3
+#define LCONF0  4
+#define LCONF1  5
+#define LIN13   6
+#define LSWRES  7
+
+#define LINSIR  _SFR_MEM8(0xC9)
+#define LRXOK   0
+#define LTXOK   1
+#define LIDOK   2
+#define LERR    3
+#define LBUSY   4
+#define LIDST0  5
+#define LIDST1  6
+#define LIDST2  7
+
+#define LINENIR _SFR_MEM8(0xCA)
+#define LENRXOK 0
+#define LENTXOK 1
+#define LENIDOK 2
+#define LENERR  3
+
+#define LINERR  _SFR_MEM8(0xCB)
+#define LBERR   0
+#define LCERR   1
+#define LPERR   2
+#define LSERR   3
+#define LFERR   4
+#define LOVERR  5
+#define LTOERR  6
+#define LABORT  7
+
+#define LINBTR  _SFR_MEM8(0xCC)
+#define LBT0    0
+#define LBT1    1
+#define LBT2    2
+#define LBT3    3
+#define LBT4    4
+#define LBT5    5
+#define LDISR   7
+
+/* Combine LINBRRL and LINBRRH */
+#define LINBRR  _SFR_MEM16(0xCD)
+
+#define LINBRRL _SFR_MEM8(0xCD)
+#define LINBRRH _SFR_MEM8(0xCE)
+
+#define LINBRRL _SFR_MEM8(0xCD)
+#define LDIV0   0
+#define LDIV1   1
+#define LDIV2   2
+#define LDIV3   3
+#define LDIV4   4
+#define LDIV5   5
+#define LDIV6   6
+#define LDIV7   7
+
+#define LINBRRH _SFR_MEM8(0xCE)
+#define LDIV8   0
+#define LDIV9   1
+#define LDIV10  2
+#define LDIV11  3
+
+#define LINDLR  _SFR_MEM8(0xCF)
+#define LRXDL0  0
+#define LRXDL1  1
+#define LRXDL2  2
+#define LRXDL3  3
+#define LTXDL0  4
+#define LTXDL1  5
+#define LTXDL2  6
+#define LTXDL3  7
+
+#define LINIDR  _SFR_MEM8(0xD0)
+#define LID0    0
+#define LID1    1
+#define LID2    2
+#define LID3    3
+#define LID4    4
+#define LID5    5
+#define LP0     6
+#define LP1     7
+
+#define LINSEL  _SFR_MEM8(0xD1)
+#define LINDX0  0
+#define LINDX1  1
+#define LINDX2  2
+#define LAINC   3
+
+#define LINDAT  _SFR_MEM8(0xD2)
+#define LDATA0  0
+#define LDATA1  1
+#define LDATA2  2
+#define LDATA3  3
+#define LDATA4  4
+#define LDATA5  5
+#define LDATA6  6
+#define LDATA7  7
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Watchdog Time-Out Interrupt */
+#define WDT_vect            _VECTOR(5)
+#define WDT_vect_num        5
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(6)
+#define TIMER1_CAPT_vect_num        6
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPA_vect            _VECTOR(7)
+#define TIMER1_COMPA_vect_num        7
+
+/* Timer/Counter1 Compare Match 1B */
+#define TIMER1_COMPB_vect            _VECTOR(8)
+#define TIMER1_COMPB_vect_num        8
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(9)
+#define TIMER1_OVF_vect_num        9
+
+/* Timer/Counter0 Compare Match 0A */
+#define TIMER0_COMPA_vect            _VECTOR(10)
+#define TIMER0_COMPA_vect_num        10
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(11)
+#define TIMER0_OVF_vect_num        11
+
+/* LIN Transfer Complete */
+#define LIN_TC_vect            _VECTOR(12)
+#define LIN_TC_vect_num        12
+
+/* LIN Error */
+#define LIN_ERR_vect            _VECTOR(13)
+#define LIN_ERR_vect_num        13
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(14)
+#define SPI_STC_vect_num        14
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(15)
+#define ADC_vect_num        15
+
+/* EEPROM Ready */
+#define EE_RDY_vect            _VECTOR(16)
+#define EE_RDY_vect_num        16
+
+/* Analog Comparator */
+#define ANA_COMP_vect            _VECTOR(17)
+#define ANA_COMP_vect_num        17
+
+/* USI Start Condition Detection */
+#define USI_START_vect            _VECTOR(18)
+#define USI_START_vect_num        18
+
+/* USI Counter Overflow */
+#define USI_OVF_vect            _VECTOR(19)
+#define USI_OVF_vect_num        19
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 80
+#else
+#  define _VECTORS_SIZE 80U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x87
+
+
+
+
+#endif /* #ifdef _AVR_ATA664251_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa8210.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa8210.h
@@ -0,0 +1,1853 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA8210_H_INCLUDED
+#define _AVR_ATA8210_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa8210.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PRR0    _SFR_IO8(0x01)
+#define PRSPI   0
+#define PRRXDC  1
+#define PRTXDC  2
+#define PRCRC   3
+#define PRVM    4
+#define PRCO    5
+
+#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRRXDC)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO))
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRRXDC
+#define __AVR_HAVE_PRR0_PRTXDC
+#define __AVR_HAVE_PRR0_PRCRC
+#define __AVR_HAVE_PRR0_PRVM
+#define __AVR_HAVE_PRR0_PRCO
+
+#define PRR1    _SFR_IO8(0x02)
+#define PRT1    0
+#define PRT2    1
+#define PRT3    2
+#define PRT4    3
+#define PRT5    4
+
+#define __AVR_HAVE_PRR1	((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5))
+#define __AVR_HAVE_PRR1_PRT1
+#define __AVR_HAVE_PRR1_PRT2
+#define __AVR_HAVE_PRR1_PRT3
+#define __AVR_HAVE_PRR1_PRT4
+#define __AVR_HAVE_PRR1_PRT5
+
+#define PRR2    _SFR_IO8(0x03)
+#define PRXB    0
+#define PRXA    1
+#define PRSF    2
+#define PRDF    3
+#define PRIDS   4
+#define PRRS    5
+#define PRSSM   7
+
+#define __AVR_HAVE_PRR2	((1<<PRXB)|(1<<PRXA)|(1<<PRSF)|(1<<PRDF)|(1<<PRIDS)|(1<<PRRS)|(1<<PRSSM))
+#define __AVR_HAVE_PRR2_PRXB
+#define __AVR_HAVE_PRR2_PRXA
+#define __AVR_HAVE_PRR2_PRSF
+#define __AVR_HAVE_PRR2_PRDF
+#define __AVR_HAVE_PRR2_PRIDS
+#define __AVR_HAVE_PRR2_PRRS
+#define __AVR_HAVE_PRR2_PRSSM
+
+#define RDPR    _SFR_IO8(0x04)
+#define PRPTB   0
+#define PRPTA   1
+#define PRFLT   2
+#define PRTMP   3
+#define APRPTB  4
+#define APRPTA  5
+#define ARDPRF  6
+#define RDPRF   7
+
+#define PINB    _SFR_IO8(0x05)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x06)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x07)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x08)
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x09)
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x0A)
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+/* Reserved [0x0B..0x0C] */
+
+#define RDSIFR  _SFR_IO8(0x0D)
+#define NBITA   0
+#define NBITB   1
+#define EOTA    2
+#define EOTB    3
+#define SOTA    4
+#define SOTB    5
+#define WCOA    6
+#define WCOB    7
+
+#define MCUCR   _SFR_IO8(0x0E)
+#define IVCE    0
+#define IVSEL   1
+#define SPIIO   2
+#define ENPS    3
+#define PUD     4
+#define PB4HS   5
+#define PB7LS   6
+#define PB7HS   7
+
+#define PCIFR   _SFR_IO8(0x0F)
+#define PCIF0   0
+#define PCIF1   1
+
+#define T0CR    _SFR_IO8(0x10)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+#define T1CR    _SFR_IO8(0x11)
+#define T1OTM   0
+#define T1CTM   1
+#define T1CRM   2
+#define T1TOP   4
+#define T1RES   5
+#define T1TOS   6
+#define T1ENA   7
+
+#define T2CR    _SFR_IO8(0x12)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2TOP   4
+#define T2RES   5
+#define T2TOS   6
+#define T2ENA   7
+
+#define T3CR    _SFR_IO8(0x13)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3TOS   6
+#define T3ENA   7
+
+#define T4CR    _SFR_IO8(0x14)
+#define T4OTM   0
+#define T4CTM   1
+#define T4CRM   2
+#define T4CPRM  3
+#define T4TOP   4
+#define T4RES   5
+#define T4TOS   6
+#define T4ENA   7
+
+#define T1IFR   _SFR_IO8(0x15)
+#define T1OFF   0
+#define T1COF   1
+
+#define T2IFR   _SFR_IO8(0x16)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x17)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+
+#define T4IFR   _SFR_IO8(0x18)
+#define T4OFF   0
+#define T4COF   1
+#define T4ICF   2
+
+#define T5IFR   _SFR_IO8(0x19)
+#define T5OFF   0
+#define T5COF   1
+
+#define GPIOR0  _SFR_IO8(0x1A)
+
+#define GPIOR3  _SFR_IO8(0x1B)
+
+#define GPIOR4  _SFR_IO8(0x1C)
+
+#define GPIOR5  _SFR_IO8(0x1D)
+
+#define GPIOR6  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EEPAGE  6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define GPIOR1  _SFR_IO8(0x24)
+
+#define GPIOR2  _SFR_IO8(0x25)
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+#define INT1    1
+
+#define EIFR    _SFR_IO8(0x28)
+#define INTF0   0
+#define INTF1   1
+
+#define CRCDIR  _SFR_IO8(0x29)
+
+#define VMCSR   _SFR_IO8(0x2A)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMF     5
+
+#define MCUSR   _SFR_IO8(0x2B)
+#define PORF    0
+#define EXTRF   1
+#define WDRF    3
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define RXIF    4
+#define TXIF    5
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define T0IFR   _SFR_IO8(0x2F)
+#define T0F     0
+
+/* Reserved [0x30] */
+
+#define DWDR    _SFR_IO8(0x31)
+
+/* Reserved [0x32] */
+
+#define RDCR    _SFR_IO8(0x33)
+#define RDPU    0
+#define ADIVEN  1
+#define RDEN    2
+
+#define EOTSA   _SFR_IO8(0x34)
+#define CARFA   0
+#define AMPFA   1
+#define SYTFA   2
+#define MANFA   3
+#define TMOFA   4
+#define TELRA   5
+#define RRFA    6
+#define EOTBF   7
+
+#define EOTCA   _SFR_IO8(0x35)
+#define CARFEA  0
+#define AMPFEA  1
+#define SYTFEA  2
+#define MANFEA  3
+#define TMOFEA  4
+#define TELREA  5
+#define RRFEA   6
+#define EOTBFE  7
+
+#define EOTSB   _SFR_IO8(0x36)
+#define CARFB   0
+#define AMPFB   1
+#define SYTFB   2
+#define MANFB   3
+#define TMOFB   4
+#define TELRB   5
+#define RRFB    6
+#define EOTAF   7
+
+#define EOTCB   _SFR_IO8(0x37)
+#define CARFEB  0
+#define AMPFEB  1
+#define SYTFEB  2
+#define MANFEB  3
+#define TMOFEB  4
+#define TELREB  5
+#define RRFEB   6
+#define EOTAFE  7
+
+#define SMCR    _SFR_IO8(0x38)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define CMCR    _SFR_IO8(0x39)
+#define CMM0    0
+#define CMM1    1
+#define CMM2    2
+#define CCS     3
+#define SRCD    4
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMIMR   _SFR_IO8(0x3A)
+#define ECIE    0
+
+#define CLPR    _SFR_IO8(0x3B)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLPCE   7
+
+#define SPMCSR  _SFR_IO8(0x3C)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define SPMIE   7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define FSEN    _SFR_MEM8(0x60)
+#define SDPU    0
+#define SDEN    1
+
+/* Reserved [0x61..0x63] */
+
+#define FFREQ1L _SFR_MEM8(0x64)
+
+#define FFREQ1M _SFR_MEM8(0x65)
+
+#define FFREQ1H _SFR_MEM8(0x66)
+
+#define FFREQ2L _SFR_MEM8(0x67)
+
+#define FFREQ2M _SFR_MEM8(0x68)
+
+#define FFREQ2H _SFR_MEM8(0x69)
+
+/* Reserved [0x6A] */
+
+#define EICRA   _SFR_MEM8(0x6B)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+#define PCMSK0  _SFR_MEM8(0x6C)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6D)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+
+#define WDTCR   _SFR_MEM8(0x6E)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+#define T1CNT   _SFR_MEM8(0x6F)
+
+#define T1COR   _SFR_MEM8(0x70)
+
+#define T1MR    _SFR_MEM8(0x71)
+#define T1CS0   0
+#define T1CS1   1
+#define T1PS0   2
+#define T1PS1   3
+#define T1PS2   4
+#define T1PS3   5
+#define T1DC0   6
+#define T1DC1   7
+
+#define T1IMR   _SFR_MEM8(0x72)
+#define T1OIM   0
+#define T1CIM   1
+
+#define T2CNT   _SFR_MEM8(0x73)
+
+#define T2COR   _SFR_MEM8(0x74)
+
+#define T2MR    _SFR_MEM8(0x75)
+#define T2CS0   0
+#define T2CS1   1
+#define T2PS0   2
+#define T2PS1   3
+#define T2PS2   4
+#define T2PS3   5
+#define T2DC0   6
+#define T2DC1   7
+
+#define T2IMR   _SFR_MEM8(0x76)
+#define T2OIM   0
+#define T2CIM   1
+
+/* Combine T3CNTL and T3CNTH */
+#define T3CNT   _SFR_MEM16(0x77)
+
+#define T3CNTL  _SFR_MEM8(0x77)
+#define T3CNTH  _SFR_MEM8(0x78)
+
+/* Combine T3CORL and T3CORH */
+#define T3COR   _SFR_MEM16(0x79)
+
+#define T3CORL  _SFR_MEM8(0x79)
+#define T3CORH  _SFR_MEM8(0x7A)
+
+/* Combine T3ICRL and T3ICRH */
+#define T3ICR   _SFR_MEM16(0x7B)
+
+#define T3ICRL  _SFR_MEM8(0x7B)
+#define T3ICRH  _SFR_MEM8(0x7C)
+
+#define T3MRA   _SFR_MEM8(0x7D)
+#define T3CS0   0
+#define T3CS1   1
+#define T3PS0   2
+#define T3PS1   3
+#define T3PS2   4
+
+#define T3MRB   _SFR_MEM8(0x7E)
+#define T3SCE   1
+#define T3CNC   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3ICS0  5
+#define T3ICS1  6
+#define T3ICS2  7
+
+#define T3IMR   _SFR_MEM8(0x7F)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+
+/* Combine T4CNTL and T4CNTH */
+#define T4CNT   _SFR_MEM16(0x80)
+
+#define T4CNTL  _SFR_MEM8(0x80)
+#define T4CNTH  _SFR_MEM8(0x81)
+
+/* Combine T4CORL and T4CORH */
+#define T4COR   _SFR_MEM16(0x82)
+
+#define T4CORL  _SFR_MEM8(0x82)
+#define T4CORH  _SFR_MEM8(0x83)
+
+/* Combine T4ICRL and T4ICRH */
+#define T4ICR   _SFR_MEM16(0x84)
+
+#define T4ICRL  _SFR_MEM8(0x84)
+#define T4ICRH  _SFR_MEM8(0x85)
+
+#define T4MRA   _SFR_MEM8(0x86)
+#define T4CS0   0
+#define T4CS1   1
+#define T4PS0   2
+#define T4PS1   3
+#define T4PS2   4
+
+#define T4MRB   _SFR_MEM8(0x87)
+#define T4SCE   1
+#define T4CNC   2
+#define T4CE0   3
+#define T4CE1   4
+#define T4ICS0  5
+#define T4ICS1  6
+#define T4ICS2  7
+
+#define T4IMR   _SFR_MEM8(0x88)
+#define T4OIM   0
+#define T4CIM   1
+#define T4CPIM  2
+
+/* Reserved [0x89] */
+
+/* Combine T5OCRL and T5OCRH */
+#define T5OCR   _SFR_MEM16(0x8A)
+
+#define T5OCRL  _SFR_MEM8(0x8A)
+#define T5OCRH  _SFR_MEM8(0x8B)
+
+#define T5CCR   _SFR_MEM8(0x8C)
+#define T5CS0   0
+#define T5CS1   1
+#define T5CS2   2
+#define T5CTC   3
+
+/* Combine T5CNTL and T5CNTH */
+#define T5CNT   _SFR_MEM16(0x8D)
+
+#define T5CNTL  _SFR_MEM8(0x8D)
+#define T5CNTH  _SFR_MEM8(0x8E)
+
+#define T5IMR   _SFR_MEM8(0x8F)
+#define T5OIM   0
+#define T5CIM   1
+
+#define GTCCR   _SFR_MEM8(0x90)
+#define PSR10   0
+#define TSM     7
+
+#define SOTSB   _SFR_MEM8(0x91)
+#define CAROB   0
+#define AMPOB   1
+#define SYTOB   2
+#define MANOB   3
+#define WUPOB   4
+#define SFIDOB  5
+#define RROB    6
+#define WCOAO   7
+
+#define SOTSA   _SFR_MEM8(0x92)
+#define CAROA   0
+#define AMPOA   1
+#define SYTOA   2
+#define MANOA   3
+#define WUPOA   4
+#define SFIDOA  5
+#define RROA    6
+#define WCOBO   7
+
+#define SOTCB   _SFR_MEM8(0x93)
+#define CAROEB  0
+#define AMPOEB  1
+#define SYTOEB  2
+#define MANOEB  3
+#define WUPEB   4
+#define SFIDEB  5
+#define RROEB   6
+#define WCOAOE  7
+
+#define SOTCA   _SFR_MEM8(0x94)
+#define CAROEA  0
+#define AMPOEA  1
+#define SYTOEA  2
+#define MANOEA  3
+#define WUPEA   4
+#define SFIDEA  5
+#define RROEA   6
+#define WCOBOE  7
+
+#define TESRB   _SFR_MEM8(0x95)
+#define CRCOB   0
+#define EOTLB0  1
+#define EOTLB1  2
+
+#define TESRA   _SFR_MEM8(0x96)
+#define CRCOA   0
+#define EOTLA0  1
+#define EOTLA1  2
+
+/* Reserved [0x97] */
+
+#define RDSIMR  _SFR_MEM8(0x98)
+#define NBITAM  0
+#define NBITBM  1
+#define EOTAM   2
+#define EOTBM   3
+#define SOTAM   4
+#define SOTBM   5
+#define WCOAM   6
+#define WCOBM   7
+
+#define RDOCR   _SFR_MEM8(0x99)
+#define TMDS0   1
+#define TMDS1   2
+#define ETRPA   3
+#define ETRPB   4
+#define RDSIDA  5
+#define RDSIDB  6
+
+/* Reserved [0x9A] */
+
+#define TEMPL   _SFR_MEM8(0x9B)
+
+#define TEMPH   _SFR_MEM8(0x9C)
+
+#define SYCB    _SFR_MEM8(0x9D)
+#define SYCSB0  0
+#define SYCSB1  1
+#define SYCSB2  2
+#define SYCSB3  3
+#define SYTLB0  4
+#define SYTLB1  5
+#define SYTLB2  6
+#define SYTLB3  7
+
+#define SYCA    _SFR_MEM8(0x9E)
+#define SYCSA0  0
+#define SYCSA1  1
+#define SYCSA2  2
+#define SYCSA3  3
+#define SYTLA0  4
+#define SYTLA1  5
+#define SYTLA2  6
+#define SYTLA3  7
+
+#define RXFOB   _SFR_MEM8(0x9F)
+
+#define RXFOA   _SFR_MEM8(0xA0)
+
+#define DMMB    _SFR_MEM8(0xA1)
+#define DMATB0  0
+#define DMATB1  1
+#define DMATB2  2
+#define DMATB3  3
+#define DMATB4  4
+#define DMPB    5
+#define DMHB    6
+#define DMNEB   7
+
+#define DMMA    _SFR_MEM8(0xA2)
+#define DMATA0  0
+#define DMATA1  1
+#define DMATA2  2
+#define DMATA3  3
+#define DMATA4  4
+#define DMPA    5
+#define DMHA    6
+#define DMNEA   7
+
+#define DMCDB   _SFR_MEM8(0xA3)
+#define DMCLB0  0
+#define DMCLB1  1
+#define DMCLB2  2
+#define DMCLB3  3
+#define DMCLB4  4
+#define DMCTB0  5
+#define DMCTB1  6
+#define DMCTB2  7
+
+#define DMCDA   _SFR_MEM8(0xA4)
+#define DMCLA0  0
+#define DMCLA1  1
+#define DMCLA2  2
+#define DMCLA3  3
+#define DMCLA4  4
+#define DMCTA0  5
+#define DMCTA1  6
+#define DMCTA2  7
+
+#define DMCRB   _SFR_MEM8(0xA5)
+#define DMPGB0  0
+#define DMPGB1  1
+#define DMPGB2  2
+#define DMPGB3  3
+#define DMPGB4  4
+#define SASKB   5
+#define SY1TB   6
+#define DMARB   7
+
+#define DMCRA   _SFR_MEM8(0xA6)
+#define DMPGA0  0
+#define DMPGA1  1
+#define DMPGA2  2
+#define DMPGA3  3
+#define DMPGA4  4
+#define SASKA   5
+#define SY1TA   6
+#define DMARA   7
+
+#define DMDRB   _SFR_MEM8(0xA7)
+#define DMAB0   0
+#define DMAB1   1
+#define DMAB2   2
+#define DMAB3   3
+#define DMDNB0  4
+#define DMDNB1  5
+#define DMDNB2  6
+#define DMDNB3  7
+
+#define DMDRA   _SFR_MEM8(0xA8)
+#define DMAA0   0
+#define DMAA1   1
+#define DMAA2   2
+#define DMAA3   3
+#define DMDNA0  4
+#define DMDNA1  5
+#define DMDNA2  6
+#define DMDNA3  7
+
+#define CHCR    _SFR_MEM8(0xA9)
+#define BWM0    0
+#define BWM1    1
+#define BWM2    2
+#define BWM3    3
+
+#define CHDN    _SFR_MEM8(0xAA)
+#define BBDN0   0
+#define BBDN1   1
+#define BBDN2   2
+#define BBDN3   3
+#define BBDN4   4
+#define ADCDN   5
+
+#define SFIDCB  _SFR_MEM8(0xAB)
+#define SFIDTB0 0
+#define SFIDTB1 1
+#define SFIDTB2 2
+#define SFIDTB3 3
+#define SFIDTB4 4
+#define SEMEB   7
+
+#define SFIDLB  _SFR_MEM8(0xAC)
+#define SFIDLB0 0
+#define SFIDLB1 1
+#define SFIDLB2 2
+#define SFIDLB3 3
+#define SFIDLB4 4
+#define SFIDLB5 5
+
+#define WUPTB   _SFR_MEM8(0xAD)
+#define WUPTB0  0
+#define WUPTB1  1
+#define WUPTB2  2
+#define WUPTB3  3
+#define WUPTB4  4
+
+#define WUPLB   _SFR_MEM8(0xAE)
+#define WUPLB0  0
+#define WUPLB1  1
+#define WUPLB2  2
+#define WUPLB3  3
+#define WUPLB4  4
+#define WUPLB5  5
+
+#define SFID1B  _SFR_MEM8(0xAF)
+
+#define SFID2B  _SFR_MEM8(0xB0)
+
+#define SFID3B  _SFR_MEM8(0xB1)
+
+#define SFID4B  _SFR_MEM8(0xB2)
+
+#define WUP1B   _SFR_MEM8(0xB3)
+
+#define WUP2B   _SFR_MEM8(0xB4)
+
+#define WUP3B   _SFR_MEM8(0xB5)
+
+#define WUP4B   _SFR_MEM8(0xB6)
+
+#define SFIDCA  _SFR_MEM8(0xB7)
+#define SFIDTA0 0
+#define SFIDTA1 1
+#define SFIDTA2 2
+#define SFIDTA3 3
+#define SFIDTA4 4
+#define SEMEA   7
+
+#define SFIDLA  _SFR_MEM8(0xB8)
+#define SFIDLA0 0
+#define SFIDLA1 1
+#define SFIDLA2 2
+#define SFIDLA3 3
+#define SFIDLA4 4
+#define SFIDLA5 5
+
+#define WUPTA   _SFR_MEM8(0xB9)
+#define WUPTA0  0
+#define WUPTA1  1
+#define WUPTA2  2
+#define WUPTA3  3
+#define WUPTA4  4
+
+#define WUPLA   _SFR_MEM8(0xBA)
+#define WUPLA0  0
+#define WUPLA1  1
+#define WUPLA2  2
+#define WUPLA3  3
+#define WUPLA4  4
+#define WUPLA5  5
+
+#define SFID1A  _SFR_MEM8(0xBB)
+
+#define SFID2A  _SFR_MEM8(0xBC)
+
+#define SFID3A  _SFR_MEM8(0xBD)
+
+#define SFID4A  _SFR_MEM8(0xBE)
+
+#define WUP1A   _SFR_MEM8(0xBF)
+
+#define WUP2A   _SFR_MEM8(0xC0)
+
+#define WUP3A   _SFR_MEM8(0xC1)
+
+#define WUP4A   _SFR_MEM8(0xC2)
+
+#define CLKOD   _SFR_MEM8(0xC3)
+
+#define CLKOCR  _SFR_MEM8(0xC4)
+#define CLKOS0  0
+#define CLKOS1  1
+#define CLKOEN  2
+
+#define XFUSE   _SFR_MEM8(0xC5)
+
+#define SRCCAL  _SFR_MEM8(0xC6)
+#define SRCCAL0 0
+#define SRCCAL1 1
+#define SRCCAL2 2
+#define SRCCAL3 3
+#define SRCCAL4 4
+#define SRCCAL5 5
+#define SRCTC0  6
+#define SRCTC1  7
+
+#define FRCCAL  _SFR_MEM8(0xC7)
+#define FRCCAL0 0
+#define FRCCAL1 1
+#define FRCCAL2 2
+#define FRCCAL3 3
+#define FRCCAL4 4
+#define FRCTC   5
+
+#define CMSR    _SFR_MEM8(0xC8)
+#define ECF     0
+
+#define CMOCR   _SFR_MEM8(0xC9)
+#define FRCAO   0
+#define SRCAO   1
+#define FRCACT  2
+#define SRCACT  3
+
+#define SUPFR   _SFR_MEM8(0xCA)
+#define AVCCRF  0
+#define AVCCLF  1
+
+#define SUPCR   _SFR_MEM8(0xCB)
+#define AVCCRM  0
+#define AVCCLM  1
+#define PVEN    2
+#define DVDIS   4
+#define AVEN    5
+#define AVDIC   6
+
+/* Reserved [0xCC] */
+
+#define SUPCA2  _SFR_MEM8(0xCD)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL3  3
+
+#define SUPCA3  _SFR_MEM8(0xCE)
+#define ACAL4   0
+#define ACAL5   1
+#define ACAL6   2
+#define ACAL7   3
+#define DCAL4   4
+#define DCAL5   5
+#define DCAL6   6
+
+#define SUPCA4  _SFR_MEM8(0xCF)
+#define ACAL0   0
+#define ACAL1   1
+#define ACAL2   2
+#define ACAL3   3
+#define DCAL0   4
+#define DCAL1   5
+#define DCAL2   6
+#define DCAL3   7
+
+#define CALRDY  _SFR_MEM8(0xD0)
+
+#define VMCAL   _SFR_MEM8(0xD1)
+#define VMCAL0  0
+#define VMCAL1  1
+#define VMCAL2  2
+
+#define DFS     _SFR_MEM8(0xD2)
+#define DFFLRF  0
+#define DFUFL   1
+#define DFOFL   2
+
+/* Combine DFTLL and DFTLH */
+#define DFTL    _SFR_MEM16(0xD3)
+
+#define DFTLL   _SFR_MEM8(0xD3)
+#define DFTLH   _SFR_MEM8(0xD4)
+
+#define DFL     _SFR_MEM8(0xD5)
+#define DFFLS0  0
+#define DFFLS1  1
+#define DFFLS2  2
+#define DFFLS3  3
+#define DFFLS4  4
+#define DFFLS5  5
+#define DFCLR   7
+
+#define DFWP    _SFR_MEM8(0xD6)
+#define DFWP0   0
+#define DFWP1   1
+#define DFWP2   2
+#define DFWP3   3
+#define DFWP4   4
+#define DFWP5   5
+
+#define DFRP    _SFR_MEM8(0xD7)
+#define DFRP0   0
+#define DFRP1   1
+#define DFRP2   2
+#define DFRP3   3
+#define DFRP4   4
+#define DFRP5   5
+
+#define DFD     _SFR_MEM8(0xD8)
+
+#define DFI     _SFR_MEM8(0xD9)
+#define DFFLIM  0
+#define DFERIM  1
+
+#define DFC     _SFR_MEM8(0xDA)
+#define DFFLC0  0
+#define DFFLC1  1
+#define DFFLC2  2
+#define DFFLC3  3
+#define DFFLC4  4
+#define DFFLC5  5
+#define DFDRA   7
+
+#define SFS     _SFR_MEM8(0xDB)
+#define SFFLRF  0
+#define SFUFL   1
+#define SFOFL   2
+
+#define SFL     _SFR_MEM8(0xDC)
+#define SFFLS0  0
+#define SFFLS1  1
+#define SFFLS2  2
+#define SFFLS3  3
+#define SFFLS4  4
+#define SFCLR   7
+
+#define SFWP    _SFR_MEM8(0xDD)
+#define SFWP0   0
+#define SFWP1   1
+#define SFWP2   2
+#define SFWP3   3
+#define SFWP4   4
+
+#define SFRP    _SFR_MEM8(0xDE)
+#define SFRP0   0
+#define SFRP1   1
+#define SFRP2   2
+#define SFRP3   3
+#define SFRP4   4
+
+#define SFD     _SFR_MEM8(0xDF)
+
+#define SFI     _SFR_MEM8(0xE0)
+#define SFFLIM  0
+#define SFERIM  1
+
+#define SFC     _SFR_MEM8(0xE1)
+#define SFFLC0  0
+#define SFFLC1  1
+#define SFFLC2  2
+#define SFFLC3  3
+#define SFFLC4  4
+#define SFDRA   7
+
+#define SSMCR   _SFR_MEM8(0xE2)
+#define SSMTX   0
+#define SSMTM   1
+#define SSMTGE  2
+#define SSMTPE  3
+#define SSMPVE  4
+#define SSMTAE  5
+#define SETRPA  6
+#define SETRPB  7
+
+#define SSMRCR  _SFR_MEM8(0xE3)
+#define SSMPA   0
+#define SSMPB   1
+#define SSMADA  2
+#define SSMADB  3
+#define SSMPVS  4
+#define SSMIFA  5
+#define SSMIDSE 6
+#define SSMTMOE 7
+
+#define SSMFBR  _SFR_MEM8(0xE4)
+#define SSMFID0 0
+#define SSMFID1 1
+#define SSMFID2 2
+#define SSMDFDT 3
+#define SSMHADT 4
+#define SSMPLDT 5
+
+#define SSMRR   _SFR_MEM8(0xE5)
+#define SSMR    0
+#define SSMST   1
+
+#define SSMSR   _SFR_MEM8(0xE6)
+#define SSMESM0 0
+#define SSMESM1 1
+#define SSMESM2 2
+#define SSMESM3 3
+#define SSMERR  7
+
+#define SSMIFR  _SFR_MEM8(0xE7)
+#define SSMIF   0
+
+#define SSMIMR  _SFR_MEM8(0xE8)
+#define SSMIM   0
+
+#define MSMSTR  _SFR_MEM8(0xE9)
+#define SSMMST0 0
+#define SSMMST1 1
+#define SSMMST2 2
+#define SSMMST3 3
+#define SSMMST4 4
+
+#define SSMSTR  _SFR_MEM8(0xEA)
+#define SSMSTA0 0
+#define SSMSTA1 1
+#define SSMSTA2 2
+#define SSMSTA3 3
+#define SSMSTA4 4
+#define SSMSTA5 5
+
+#define SSMXSR  _SFR_MEM8(0xEB)
+#define SSMSTB0 0
+#define SSMSTB1 1
+#define SSMSTB2 2
+#define SSMSTB3 3
+#define SSMSTB4 4
+#define SSMSTB5 5
+
+#define MSMCR1  _SFR_MEM8(0xEC)
+#define MSMSM00 0
+#define MSMSM01 1
+#define MSMSM02 2
+#define MSMSM03 3
+#define MSMSM10 4
+#define MSMSM11 5
+#define MSMSM12 6
+#define MSMSM13 7
+
+#define MSMCR2  _SFR_MEM8(0xED)
+#define MSMSM20 0
+#define MSMSM21 1
+#define MSMSM22 2
+#define MSMSM23 3
+#define MSMSM30 4
+#define MSMSM31 5
+#define MSMSM32 6
+#define MSMSM33 7
+
+#define MSMCR3  _SFR_MEM8(0xEE)
+#define MSMSM40 0
+#define MSMSM41 1
+#define MSMSM42 2
+#define MSMSM43 3
+#define MSMSM50 4
+#define MSMSM51 5
+#define MSMSM52 6
+#define MSMSM53 7
+
+#define MSMCR4  _SFR_MEM8(0xEF)
+#define MSMSM60 0
+#define MSMSM61 1
+#define MSMSM62 2
+#define MSMSM63 3
+#define MSMSM70 4
+#define MSMSM71 5
+#define MSMSM72 6
+#define MSMSM73 7
+
+#define GTCR    _SFR_MEM8(0xF0)
+#define RXTEHA  0
+#define GAPMA   1
+#define DARA    2
+#define IWUPA   3
+#define RXTEHB  4
+#define GAPMB   5
+#define DARB    6
+#define IWUPB   7
+
+#define SOTC1A  _SFR_MEM8(0xF1)
+#define CAROEA1 0
+#define AMPOEA1 1
+#define SYTOEA1 2
+#define MANOEA1 3
+#define WUPEA1  4
+#define SFIDEA1 5
+#define RROEA1  6
+#define WCOBOE1 7
+
+#define SOTC2A  _SFR_MEM8(0xF2)
+#define CAROEA2 0
+#define AMPOEA2 1
+#define SYTOEA2 2
+#define MANOEA2 3
+#define WUPEA2  4
+#define SFIDEA2 5
+#define RROEA2  6
+#define WCOBOE2 7
+
+#define SOTC1B  _SFR_MEM8(0xF3)
+#define CAROEB1 0
+#define AMPOEB1 1
+#define SYTOEB1 2
+#define MANOEB1 3
+#define WUPEB1  4
+#define SFIDEB1 5
+#define RROEB1  6
+#define WCOAOE1 7
+
+#define SOTC2B  _SFR_MEM8(0xF4)
+#define CAROEB2 0
+#define AMPOEB2 1
+#define SYTOEB2 2
+#define MANOEB2 3
+#define WUPEB2  4
+#define SFIDEB2 5
+#define RROEB2  6
+#define WCOAOE2 7
+
+#define EOTC1A  _SFR_MEM8(0xF5)
+#define CARFEA1 0
+#define AMPFEA1 1
+#define SYTFEA1 2
+#define MANFEA1 3
+#define TMOFEA1 4
+#define TELREA1 5
+#define RRFEA1  6
+#define EOTBFE1 7
+
+#define EOTC2A  _SFR_MEM8(0xF6)
+#define CARFEA2 0
+#define AMPFEA2 1
+#define SYTFEA2 2
+#define MANFEA2 3
+#define TMOFEA2 4
+#define TELREA2 5
+#define RRFEA2  6
+#define EOTBFE2 7
+
+#define EOTC3A  _SFR_MEM8(0xF7)
+#define CARFEA3 0
+#define AMPFEA3 1
+#define SYTFEA3 2
+#define MANFEA3 3
+#define TMOFEA3 4
+#define TELREA3 5
+#define RRFEA3  6
+#define EOTBFE3 7
+
+#define EOTC1B  _SFR_MEM8(0xF8)
+#define CARFEB1 0
+#define AMPFEB1 1
+#define SYTFEB1 2
+#define MANFEB1 3
+#define TMOFEB1 4
+#define TELREB1 5
+#define RRFEB1  6
+#define EOTAFE1 7
+
+#define EOTC2B  _SFR_MEM8(0xF9)
+#define CARFEB2 0
+#define AMPFEB2 1
+#define SYTFEB2 2
+#define MANFEB2 3
+#define TMOFEB2 4
+#define TELREB2 5
+#define RRFEB2  6
+#define EOTAFE2 7
+
+#define EOTC3B  _SFR_MEM8(0xFA)
+#define CARFEB3 0
+#define AMPFEB3 1
+#define SYTFEB3 2
+#define MANFEB3 3
+#define TMOFEB3 4
+#define TELREB3 5
+#define RRFEB3  6
+#define EOTAFE3 7
+
+#define WCOTOA  _SFR_MEM8(0xFB)
+
+#define WCOTOB  _SFR_MEM8(0xFC)
+
+#define SOTTOA  _SFR_MEM8(0xFD)
+
+#define SOTTOB  _SFR_MEM8(0xFE)
+
+#define SSMFCR  _SFR_MEM8(0xFF)
+#define SSMIDSO 0
+#define SSMIDSF 1
+
+#define FESR    _SFR_MEM8(0x100)
+#define LBSAT   0
+#define HBSAT   1
+#define XRDY    2
+#define PLCK    3
+
+#define FEEN1   _SFR_MEM8(0x101)
+#define PLEN    0
+#define PLCAL   1
+#define XTOEN   2
+#define LNAEN   3
+#define ADEN    4
+#define ADCLK   5
+#define PLSP1   6
+#define ATEN    7
+
+#define FEEN2   _SFR_MEM8(0x102)
+#define SDRX    0
+#define SDRX2   1
+#define PAEN    2
+#define TMPM    3
+#define PLPEN   4
+#define XTPEN   5
+
+#define FELNA   _SFR_MEM8(0x103)
+#define LBH0    0
+#define LBH1    1
+#define LBH2    2
+#define LBH3    3
+#define LBL0    4
+#define LBL1    5
+#define LBL2    6
+#define LBL3    7
+
+/* Reserved [0x104..0x105] */
+
+#define FEVCT   _SFR_MEM8(0x106)
+#define FEVCT0  0
+#define FEVCT1  1
+#define FEVCT2  2
+#define FEVCT3  3
+
+#define FEBT    _SFR_MEM8(0x107)
+#define CTN20   0
+#define CTN21   1
+#define RTN20   2
+#define RTN21   3
+
+#define FEMS    _SFR_MEM8(0x108)
+#define PLLS0   0
+#define PLLS1   1
+#define PLLS2   2
+#define PLLS3   3
+#define PLLM0   4
+#define PLLM1   5
+#define PLLM2   6
+#define PLLM3   7
+
+#define FETN4   _SFR_MEM8(0x109)
+#define CTN40   0
+#define CTN41   1
+#define CTN42   2
+#define CTN43   3
+#define RTN40   4
+#define RTN41   5
+#define RTN42   6
+#define RTN43   7
+
+#define FECR    _SFR_MEM8(0x10A)
+#define LBNHB   0
+#define S4N3    1
+#define ANDP    2
+#define ADHS    3
+#define PLCKG   4
+#define ANPS    5
+
+#define FEVCO   _SFR_MEM8(0x10B)
+#define CPCC0   0
+#define CPCC1   1
+#define CPCC2   2
+#define CPCC3   3
+#define VCOB0   4
+#define VCOB1   5
+#define VCOB2   6
+#define VCOB3   7
+
+#define FEALR   _SFR_MEM8(0x10C)
+#define RNGE0   0
+#define RNGE1   1
+
+#define FEANT   _SFR_MEM8(0x10D)
+#define LVLC0   0
+#define LVLC1   1
+#define LVLC2   2
+#define LVLC3   3
+
+#define FEBIA   _SFR_MEM8(0x10E)
+#define IFAEN   7
+
+/* Reserved [0x10F..0x12E] */
+
+#define RXBC1   _SFR_MEM8(0x12F)
+#define RXCEA   0
+#define RXCBLA0 1
+#define RXCBLA1 2
+#define RXMSBA  3
+#define RXCEB   4
+#define RXCBLB0 5
+#define RXCBLB1 6
+#define RXMSBB  7
+
+#define RXBC2   _SFR_MEM8(0x130)
+#define RXBPB   0
+#define RXBF    1
+#define RXBCLR  2
+
+#define RXTLLB  _SFR_MEM8(0x131)
+
+#define RXTLHB  _SFR_MEM8(0x132)
+#define RXTLHB0 0
+#define RXTLHB1 1
+#define RXTLHB2 2
+#define RXTLHB3 3
+
+#define RXCRLB  _SFR_MEM8(0x133)
+
+#define RXCRHB  _SFR_MEM8(0x134)
+
+#define RXCSBB  _SFR_MEM8(0x135)
+
+#define RXCILB  _SFR_MEM8(0x136)
+
+#define RXCIHB  _SFR_MEM8(0x137)
+
+#define RXCPLB  _SFR_MEM8(0x138)
+
+#define RXCPHB  _SFR_MEM8(0x139)
+
+#define RXDSB   _SFR_MEM8(0x13A)
+
+#define RXTLLA  _SFR_MEM8(0x13B)
+
+#define RXTLHA  _SFR_MEM8(0x13C)
+#define RXTLHA0 0
+#define RXTLHA1 1
+#define RXTLHA2 2
+#define RXTLHA3 3
+
+#define RXCRLA  _SFR_MEM8(0x13D)
+
+#define RXCRHA  _SFR_MEM8(0x13E)
+
+#define RXCSBA  _SFR_MEM8(0x13F)
+
+#define RXCILA  _SFR_MEM8(0x140)
+
+#define RXCIHA  _SFR_MEM8(0x141)
+
+#define RXCPLA  _SFR_MEM8(0x142)
+
+#define RXCPHA  _SFR_MEM8(0x143)
+
+#define RXDSA   _SFR_MEM8(0x144)
+
+#define CRCCR   _SFR_MEM8(0x145)
+#define CRCRS   0
+#define REFLI   1
+#define REFLO   2
+
+#define CRCDOR  _SFR_MEM8(0x146)
+
+#define IDB0    _SFR_MEM8(0x147)
+
+#define IDB1    _SFR_MEM8(0x148)
+
+#define IDB2    _SFR_MEM8(0x149)
+
+#define IDB3    _SFR_MEM8(0x14A)
+
+#define IDC     _SFR_MEM8(0x14B)
+#define IDL0    0
+#define IDL1    1
+#define IDBO0   2
+#define IDBO1   3
+#define IDFIM   5
+#define IDCLR   6
+#define IDCE    7
+
+#define IDS     _SFR_MEM8(0x14C)
+#define IDOK    0
+#define IDFULL  1
+
+#define RSSAV   _SFR_MEM8(0x14D)
+
+#define RSSPK   _SFR_MEM8(0x14E)
+
+#define RSSL    _SFR_MEM8(0x14F)
+
+#define RSSH    _SFR_MEM8(0x150)
+
+#define RSSC    _SFR_MEM8(0x151)
+#define RSUP0   0
+#define RSUP1   1
+#define RSUP2   2
+#define RSUP3   3
+#define RSWLH   4
+#define RSHRX   5
+#define RSPKF   6
+
+#define DBCR    _SFR_MEM8(0x152)
+#define DBMD    0
+#define DBCS    1
+#define DBTMS   2
+#define DBHA    3
+
+#define DBTC    _SFR_MEM8(0x153)
+
+#define DBENB   _SFR_MEM8(0x154)
+
+#define DBENC   _SFR_MEM8(0x155)
+
+#define DBGSW   _SFR_MEM8(0x156)
+#define DBGGS0  0
+#define DBGGS1  1
+#define DBGGS2  2
+#define DBGGS3  3
+#define CPBFOS0 4
+#define CPBFOS1 5
+#define CPBF    6
+#define DBGSE   7
+
+#define SFFR    _SFR_MEM8(0x157)
+#define RFL0    0
+#define RFL1    1
+#define RFL2    2
+#define RFC     3
+#define TFL0    4
+#define TFL1    5
+#define TFL2    6
+#define TFC     7
+
+#define SFIR    _SFR_MEM8(0x158)
+#define RIL0    0
+#define RIL1    1
+#define RIL2    2
+#define SRIE    3
+#define TIL0    4
+#define TIL1    5
+#define TIL2    6
+#define STIE    7
+
+#define EECR2   _SFR_MEM8(0x159)
+#define EEBRE   0
+
+#define PGMST   _SFR_MEM8(0x15A)
+#define PGMSYN0 0
+#define PGMSYN1 1
+#define PGMSYN2 2
+#define PGMSYN3 3
+#define PGMSYN4 4
+
+#define EEST    _SFR_MEM8(0x15B)
+#define EESYN0  0
+#define EESYN1  1
+#define EESYN2  2
+#define EESYN3  3
+
+#define RSIFG   _SFR_MEM8(0x15C)
+
+#define RSLDV   _SFR_MEM8(0x15D)
+
+#define RSHDV   _SFR_MEM8(0x15E)
+
+#define RSCOM   _SFR_MEM8(0x15F)
+#define RSDC    0
+#define RSIFC   1
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCI0_vect            _VECTOR(3)
+#define PCI0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCI1_vect            _VECTOR(4)
+#define PCI1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMON_vect            _VECTOR(5)
+#define VMON_vect_num        5
+
+/* AVCC Reset Interrupt */
+#define AVCCR_vect            _VECTOR(6)
+#define AVCCR_vect_num        6
+
+/* AVCC Low Interrupt */
+#define AVCCL_vect            _VECTOR(7)
+#define AVCCL_vect_num        7
+
+/* Timer 0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(8)
+#define T0INT_vect_num        8
+
+/* Timer/Counter1 Compare Match Interrupt */
+#define T1COMP_vect            _VECTOR(9)
+#define T1COMP_vect_num        9
+
+/* Timer/Counter1 Overflow Interrupt */
+#define T1OVF_vect            _VECTOR(10)
+#define T1OVF_vect_num        10
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMP_vect            _VECTOR(11)
+#define T2COMP_vect_num        11
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVF_vect            _VECTOR(12)
+#define T2OVF_vect_num        12
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAP_vect            _VECTOR(13)
+#define T3CAP_vect_num        13
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMP_vect            _VECTOR(14)
+#define T3COMP_vect_num        14
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVF_vect            _VECTOR(15)
+#define T3OVF_vect_num        15
+
+/* Timer/Counter4 Capture Event Interrupt */
+#define T4CAP_vect            _VECTOR(16)
+#define T4CAP_vect_num        16
+
+/* Timer/Counter4 Compare Match Interrupt */
+#define T4COMP_vect            _VECTOR(17)
+#define T4COMP_vect_num        17
+
+/* Timer/Counter4 Overflow Interrupt */
+#define T4OVF_vect            _VECTOR(18)
+#define T4OVF_vect_num        18
+
+/* Timer/Counter5 Compare Match Interrupt */
+#define T5COMP_vect            _VECTOR(19)
+#define T5COMP_vect_num        19
+
+/* Timer/Counter5 Overflow Interrupt */
+#define T5OVF_vect            _VECTOR(20)
+#define T5OVF_vect_num        20
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPI_vect            _VECTOR(21)
+#define SPI_vect_num        21
+
+/* SPI Rx Buffer Interrupt */
+#define SRX_FIFO_vect            _VECTOR(22)
+#define SRX_FIFO_vect_num        22
+
+/* SPI Tx Buffer Interrupt */
+#define STX_FIFO_vect            _VECTOR(23)
+#define STX_FIFO_vect_num        23
+
+/* Sequencer State Machine Interrupt */
+#define SSM_vect            _VECTOR(24)
+#define SSM_vect_num        24
+
+/* Data FIFO fill level reached Interrupt */
+#define DFFLR_vect            _VECTOR(25)
+#define DFFLR_vect_num        25
+
+/* Data FIFO overflow or underflow error Interrupt */
+#define DFOUE_vect            _VECTOR(26)
+#define DFOUE_vect_num        26
+
+/* RSSI/Preamble FIFO fill level reached Interrupt */
+#define SFFLR_vect            _VECTOR(27)
+#define SFFLR_vect_num        27
+
+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
+#define SFOUE_vect            _VECTOR(28)
+#define SFOUE_vect_num        28
+
+/* Tx Modulator Telegram Finish Interrupt */
+#define TMTCF_vect            _VECTOR(29)
+#define TMTCF_vect_num        29
+
+/* UHF receiver wake up ok on Rx path B */
+#define UHF_WCOB_vect            _VECTOR(30)
+#define UHF_WCOB_vect_num        30
+
+/* UHF receiver wake up ok on Rx path A */
+#define UHF_WCOA_vect            _VECTOR(31)
+#define UHF_WCOA_vect_num        31
+
+/* UHF receiver start of telegram ok on Rx path B */
+#define UHF_SOTB_vect            _VECTOR(32)
+#define UHF_SOTB_vect_num        32
+
+/* UHF receiver start of telegram ok on Rx path A */
+#define UHF_SOTA_vect            _VECTOR(33)
+#define UHF_SOTA_vect_num        33
+
+/* UHF receiver end of telegram on Rx path B */
+#define UHF_EOTB_vect            _VECTOR(34)
+#define UHF_EOTB_vect_num        34
+
+/* UHF receiver end of telegram on Rx path A */
+#define UHF_EOTA_vect            _VECTOR(35)
+#define UHF_EOTA_vect_num        35
+
+/* UHF receiver new bit on Rx path B */
+#define UHF_NBITB_vect            _VECTOR(36)
+#define UHF_NBITB_vect_num        36
+
+/* UHF receiver new bit on Rx path A */
+#define UHF_NBITA_vect            _VECTOR(37)
+#define UHF_NBITA_vect_num        37
+
+/* External input Clock monitoring Interrupt */
+#define EXCM_vect            _VECTOR(38)
+#define EXCM_vect_num        38
+
+/* EEPROM Ready Interrupt */
+#define ERDY_vect            _VECTOR(39)
+#define ERDY_vect_num        39
+
+/* Store Program Memory Ready */
+#define SPMR_vect            _VECTOR(40)
+#define SPMR_vect_num        40
+
+/* IDSCAN Full Interrupt */
+#define IDFULL_vect            _VECTOR(41)
+#define IDFULL_vect_num        41
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 168
+#else
+#  define _VECTORS_SIZE 168U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x8000
+#  define FLASHEND     0xCFFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x8000U
+#  define FLASHEND     0xCFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      1024
+#  define RAMEND       0x05FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x05FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  16
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  16U
+#  define E2END       0x03FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_EXTCLKEN    (unsigned char)~_BV(0)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(1)
+#define FUSE_BOOTRST     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x65
+
+
+
+
+#endif /* #ifdef _AVR_ATA8210_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioa8510.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioa8510.h
@@ -0,0 +1,1959 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA8510_H_INCLUDED
+#define _AVR_ATA8510_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa8510.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PRR0    _SFR_IO8(0x01)
+#define PRSPI   0
+#define PRRXDC  1
+#define PRTXDC  2
+#define PRCRC   3
+#define PRVM    4
+#define PRCO    5
+
+#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRRXDC)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO))
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRRXDC
+#define __AVR_HAVE_PRR0_PRTXDC
+#define __AVR_HAVE_PRR0_PRCRC
+#define __AVR_HAVE_PRR0_PRVM
+#define __AVR_HAVE_PRR0_PRCO
+
+#define PRR1    _SFR_IO8(0x02)
+#define PRT1    0
+#define PRT2    1
+#define PRT3    2
+#define PRT4    3
+#define PRT5    4
+
+#define __AVR_HAVE_PRR1	((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5))
+#define __AVR_HAVE_PRR1_PRT1
+#define __AVR_HAVE_PRR1_PRT2
+#define __AVR_HAVE_PRR1_PRT3
+#define __AVR_HAVE_PRR1_PRT4
+#define __AVR_HAVE_PRR1_PRT5
+
+#define PRR2    _SFR_IO8(0x03)
+#define PRXB    0
+#define PRXA    1
+#define PRSF    2
+#define PRDF    3
+#define PRIDS   4
+#define PRRS    5
+#define PRTM    6
+#define PRSSM   7
+
+#define __AVR_HAVE_PRR2	((1<<PRXB)|(1<<PRXA)|(1<<PRSF)|(1<<PRDF)|(1<<PRIDS)|(1<<PRRS)|(1<<PRTM)|(1<<PRSSM))
+#define __AVR_HAVE_PRR2_PRXB
+#define __AVR_HAVE_PRR2_PRXA
+#define __AVR_HAVE_PRR2_PRSF
+#define __AVR_HAVE_PRR2_PRDF
+#define __AVR_HAVE_PRR2_PRIDS
+#define __AVR_HAVE_PRR2_PRRS
+#define __AVR_HAVE_PRR2_PRTM
+#define __AVR_HAVE_PRR2_PRSSM
+
+#define RDPR    _SFR_IO8(0x04)
+#define PRPTB   0
+#define PRPTA   1
+#define PRFLT   2
+#define PRTMP   3
+#define APRPTB  4
+#define APRPTA  5
+#define ARDPRF  6
+#define RDPRF   7
+
+#define PINB    _SFR_IO8(0x05)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x06)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x07)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x08)
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x09)
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x0A)
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define FSCR    _SFR_IO8(0x0B)
+#define TXMOD   0
+#define SFM     1
+#define TXMS0   2
+#define TXMS1   3
+#define PAOER   4
+#define PAON    7
+
+/* Reserved [0x0C] */
+
+#define RDSIFR  _SFR_IO8(0x0D)
+#define NBITA   0
+#define NBITB   1
+#define EOTA    2
+#define EOTB    3
+#define SOTA    4
+#define SOTB    5
+#define WCOA    6
+#define WCOB    7
+
+#define MCUCR   _SFR_IO8(0x0E)
+#define IVCE    0
+#define IVSEL   1
+#define SPIIO   2
+#define ENPS    3
+#define PUD     4
+#define PB4HS   5
+#define PB7LS   6
+#define PB7HS   7
+
+#define PCIFR   _SFR_IO8(0x0F)
+#define PCIF0   0
+#define PCIF1   1
+
+#define T0CR    _SFR_IO8(0x10)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+#define T1CR    _SFR_IO8(0x11)
+#define T1OTM   0
+#define T1CTM   1
+#define T1CRM   2
+#define T1TOP   4
+#define T1RES   5
+#define T1TOS   6
+#define T1ENA   7
+
+#define T2CR    _SFR_IO8(0x12)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2TOP   4
+#define T2RES   5
+#define T2TOS   6
+#define T2ENA   7
+
+#define T3CR    _SFR_IO8(0x13)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3TOS   6
+#define T3ENA   7
+
+#define T4CR    _SFR_IO8(0x14)
+#define T4OTM   0
+#define T4CTM   1
+#define T4CRM   2
+#define T4CPRM  3
+#define T4TOP   4
+#define T4RES   5
+#define T4TOS   6
+#define T4ENA   7
+
+#define T1IFR   _SFR_IO8(0x15)
+#define T1OFF   0
+#define T1COF   1
+
+#define T2IFR   _SFR_IO8(0x16)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x17)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+
+#define T4IFR   _SFR_IO8(0x18)
+#define T4OFF   0
+#define T4COF   1
+#define T4ICF   2
+
+#define T5IFR   _SFR_IO8(0x19)
+#define T5OFF   0
+#define T5COF   1
+
+#define GPIOR0  _SFR_IO8(0x1A)
+
+#define GPIOR3  _SFR_IO8(0x1B)
+
+#define GPIOR4  _SFR_IO8(0x1C)
+
+#define GPIOR5  _SFR_IO8(0x1D)
+
+#define GPIOR6  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EEPAGE  6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define GPIOR1  _SFR_IO8(0x24)
+
+#define GPIOR2  _SFR_IO8(0x25)
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+#define INT1    1
+
+#define EIFR    _SFR_IO8(0x28)
+#define INTF0   0
+#define INTF1   1
+
+#define CRCDIR  _SFR_IO8(0x29)
+
+#define VMCSR   _SFR_IO8(0x2A)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMF     5
+
+#define MCUSR   _SFR_IO8(0x2B)
+#define PORF    0
+#define EXTRF   1
+#define WDRF    3
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define RXIF    4
+#define TXIF    5
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define T0IFR   _SFR_IO8(0x2F)
+#define T0F     0
+
+/* Reserved [0x30] */
+
+#define DWDR    _SFR_IO8(0x31)
+
+/* Reserved [0x32] */
+
+#define RDCR    _SFR_IO8(0x33)
+#define RDPU    0
+#define ADIVEN  1
+#define RDEN    2
+
+#define EOTSA   _SFR_IO8(0x34)
+#define CARFA   0
+#define AMPFA   1
+#define SYTFA   2
+#define MANFA   3
+#define TMOFA   4
+#define TELRA   5
+#define RRFA    6
+#define EOTBF   7
+
+#define EOTCA   _SFR_IO8(0x35)
+#define CARFEA  0
+#define AMPFEA  1
+#define SYTFEA  2
+#define MANFEA  3
+#define TMOFEA  4
+#define TELREA  5
+#define RRFEA   6
+#define EOTBFE  7
+
+#define EOTSB   _SFR_IO8(0x36)
+#define CARFB   0
+#define AMPFB   1
+#define SYTFB   2
+#define MANFB   3
+#define TMOFB   4
+#define TELRB   5
+#define RRFB    6
+#define EOTAF   7
+
+#define EOTCB   _SFR_IO8(0x37)
+#define CARFEB  0
+#define AMPFEB  1
+#define SYTFEB  2
+#define MANFEB  3
+#define TMOFEB  4
+#define TELREB  5
+#define RRFEB   6
+#define EOTAFE  7
+
+#define SMCR    _SFR_IO8(0x38)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define CMCR    _SFR_IO8(0x39)
+#define CMM0    0
+#define CMM1    1
+#define CMM2    2
+#define CCS     3
+#define SRCD    4
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMIMR   _SFR_IO8(0x3A)
+#define ECIE    0
+
+#define CLPR    _SFR_IO8(0x3B)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLPCE   7
+
+#define SPMCSR  _SFR_IO8(0x3C)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define SPMIE   7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define FSEN    _SFR_MEM8(0x60)
+#define SDPU    0
+#define SDEN    1
+#define GAEN    2
+#define PEEN    3
+#define ASEN    4
+#define ANTT    5
+
+#define FSFCR   _SFR_MEM8(0x61)
+#define BTSEL0  0
+#define BTSEL1  1
+#define ASDIV0  4
+#define ASDIV1  5
+#define ASDIV2  6
+#define ASDIV3  7
+
+/* Combine GACDIVL and GACDIVH */
+#define GACDIV  _SFR_MEM16(0x62)
+
+#define GACDIVL _SFR_MEM8(0x62)
+#define GACDIVH _SFR_MEM8(0x63)
+
+#define FFREQ1L _SFR_MEM8(0x64)
+
+#define FFREQ1M _SFR_MEM8(0x65)
+
+#define FFREQ1H _SFR_MEM8(0x66)
+
+#define FFREQ2L _SFR_MEM8(0x67)
+
+#define FFREQ2M _SFR_MEM8(0x68)
+
+#define FFREQ2H _SFR_MEM8(0x69)
+
+/* Reserved [0x6A] */
+
+#define EICRA   _SFR_MEM8(0x6B)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+#define PCMSK0  _SFR_MEM8(0x6C)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6D)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+
+#define WDTCR   _SFR_MEM8(0x6E)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+#define T1CNT   _SFR_MEM8(0x6F)
+
+#define T1COR   _SFR_MEM8(0x70)
+
+#define T1MR    _SFR_MEM8(0x71)
+#define T1CS0   0
+#define T1CS1   1
+#define T1PS0   2
+#define T1PS1   3
+#define T1PS2   4
+#define T1PS3   5
+#define T1DC0   6
+#define T1DC1   7
+
+#define T1IMR   _SFR_MEM8(0x72)
+#define T1OIM   0
+#define T1CIM   1
+
+#define T2CNT   _SFR_MEM8(0x73)
+
+#define T2COR   _SFR_MEM8(0x74)
+
+#define T2MR    _SFR_MEM8(0x75)
+#define T2CS0   0
+#define T2CS1   1
+#define T2PS0   2
+#define T2PS1   3
+#define T2PS2   4
+#define T2PS3   5
+#define T2DC0   6
+#define T2DC1   7
+
+#define T2IMR   _SFR_MEM8(0x76)
+#define T2OIM   0
+#define T2CIM   1
+
+/* Combine T3CNTL and T3CNTH */
+#define T3CNT   _SFR_MEM16(0x77)
+
+#define T3CNTL  _SFR_MEM8(0x77)
+#define T3CNTH  _SFR_MEM8(0x78)
+
+/* Combine T3CORL and T3CORH */
+#define T3COR   _SFR_MEM16(0x79)
+
+#define T3CORL  _SFR_MEM8(0x79)
+#define T3CORH  _SFR_MEM8(0x7A)
+
+/* Combine T3ICRL and T3ICRH */
+#define T3ICR   _SFR_MEM16(0x7B)
+
+#define T3ICRL  _SFR_MEM8(0x7B)
+#define T3ICRH  _SFR_MEM8(0x7C)
+
+#define T3MRA   _SFR_MEM8(0x7D)
+#define T3CS0   0
+#define T3CS1   1
+#define T3PS0   2
+#define T3PS1   3
+#define T3PS2   4
+
+#define T3MRB   _SFR_MEM8(0x7E)
+#define T3SCE   1
+#define T3CNC   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3ICS0  5
+#define T3ICS1  6
+#define T3ICS2  7
+
+#define T3IMR   _SFR_MEM8(0x7F)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+
+/* Combine T4CNTL and T4CNTH */
+#define T4CNT   _SFR_MEM16(0x80)
+
+#define T4CNTL  _SFR_MEM8(0x80)
+#define T4CNTH  _SFR_MEM8(0x81)
+
+/* Combine T4CORL and T4CORH */
+#define T4COR   _SFR_MEM16(0x82)
+
+#define T4CORL  _SFR_MEM8(0x82)
+#define T4CORH  _SFR_MEM8(0x83)
+
+/* Combine T4ICRL and T4ICRH */
+#define T4ICR   _SFR_MEM16(0x84)
+
+#define T4ICRL  _SFR_MEM8(0x84)
+#define T4ICRH  _SFR_MEM8(0x85)
+
+#define T4MRA   _SFR_MEM8(0x86)
+#define T4CS0   0
+#define T4CS1   1
+#define T4PS0   2
+#define T4PS1   3
+#define T4PS2   4
+
+#define T4MRB   _SFR_MEM8(0x87)
+#define T4SCE   1
+#define T4CNC   2
+#define T4CE0   3
+#define T4CE1   4
+#define T4ICS0  5
+#define T4ICS1  6
+#define T4ICS2  7
+
+#define T4IMR   _SFR_MEM8(0x88)
+#define T4OIM   0
+#define T4CIM   1
+#define T4CPIM  2
+
+/* Reserved [0x89] */
+
+/* Combine T5OCRL and T5OCRH */
+#define T5OCR   _SFR_MEM16(0x8A)
+
+#define T5OCRL  _SFR_MEM8(0x8A)
+#define T5OCRH  _SFR_MEM8(0x8B)
+
+#define T5CCR   _SFR_MEM8(0x8C)
+#define T5CS0   0
+#define T5CS1   1
+#define T5CS2   2
+#define T5CTC   3
+
+/* Combine T5CNTL and T5CNTH */
+#define T5CNT   _SFR_MEM16(0x8D)
+
+#define T5CNTL  _SFR_MEM8(0x8D)
+#define T5CNTH  _SFR_MEM8(0x8E)
+
+#define T5IMR   _SFR_MEM8(0x8F)
+#define T5OIM   0
+#define T5CIM   1
+
+#define GTCCR   _SFR_MEM8(0x90)
+#define PSR10   0
+#define TSM     7
+
+#define SOTSB   _SFR_MEM8(0x91)
+#define CAROB   0
+#define AMPOB   1
+#define SYTOB   2
+#define MANOB   3
+#define WUPOB   4
+#define SFIDOB  5
+#define RROB    6
+#define WCOAO   7
+
+#define SOTSA   _SFR_MEM8(0x92)
+#define CAROA   0
+#define AMPOA   1
+#define SYTOA   2
+#define MANOA   3
+#define WUPOA   4
+#define SFIDOA  5
+#define RROA    6
+#define WCOBO   7
+
+#define SOTCB   _SFR_MEM8(0x93)
+#define CAROEB  0
+#define AMPOEB  1
+#define SYTOEB  2
+#define MANOEB  3
+#define WUPEB   4
+#define SFIDEB  5
+#define RROEB   6
+#define WCOAOE  7
+
+#define SOTCA   _SFR_MEM8(0x94)
+#define CAROEA  0
+#define AMPOEA  1
+#define SYTOEA  2
+#define MANOEA  3
+#define WUPEA   4
+#define SFIDEA  5
+#define RROEA   6
+#define WCOBOE  7
+
+#define TESRB   _SFR_MEM8(0x95)
+#define CRCOB   0
+#define EOTLB0  1
+#define EOTLB1  2
+
+#define TESRA   _SFR_MEM8(0x96)
+#define CRCOA   0
+#define EOTLA0  1
+#define EOTLA1  2
+
+/* Reserved [0x97] */
+
+#define RDSIMR  _SFR_MEM8(0x98)
+#define NBITAM  0
+#define NBITBM  1
+#define EOTAM   2
+#define EOTBM   3
+#define SOTAM   4
+#define SOTBM   5
+#define WCOAM   6
+#define WCOBM   7
+
+#define RDOCR   _SFR_MEM8(0x99)
+#define TMDS0   1
+#define TMDS1   2
+#define ETRPA   3
+#define ETRPB   4
+#define RDSIDA  5
+#define RDSIDB  6
+
+/* Reserved [0x9A] */
+
+#define TEMPL   _SFR_MEM8(0x9B)
+
+#define TEMPH   _SFR_MEM8(0x9C)
+
+#define SYCB    _SFR_MEM8(0x9D)
+#define SYCSB0  0
+#define SYCSB1  1
+#define SYCSB2  2
+#define SYCSB3  3
+#define SYTLB0  4
+#define SYTLB1  5
+#define SYTLB2  6
+#define SYTLB3  7
+
+#define SYCA    _SFR_MEM8(0x9E)
+#define SYCSA0  0
+#define SYCSA1  1
+#define SYCSA2  2
+#define SYCSA3  3
+#define SYTLA0  4
+#define SYTLA1  5
+#define SYTLA2  6
+#define SYTLA3  7
+
+#define RXFOB   _SFR_MEM8(0x9F)
+
+#define RXFOA   _SFR_MEM8(0xA0)
+
+#define DMMB    _SFR_MEM8(0xA1)
+#define DMATB0  0
+#define DMATB1  1
+#define DMATB2  2
+#define DMATB3  3
+#define DMATB4  4
+#define DMPB    5
+#define DMHB    6
+#define DMNEB   7
+
+#define DMMA    _SFR_MEM8(0xA2)
+#define DMATA0  0
+#define DMATA1  1
+#define DMATA2  2
+#define DMATA3  3
+#define DMATA4  4
+#define DMPA    5
+#define DMHA    6
+#define DMNEA   7
+
+#define DMCDB   _SFR_MEM8(0xA3)
+#define DMCLB0  0
+#define DMCLB1  1
+#define DMCLB2  2
+#define DMCLB3  3
+#define DMCLB4  4
+#define DMCTB0  5
+#define DMCTB1  6
+#define DMCTB2  7
+
+#define DMCDA   _SFR_MEM8(0xA4)
+#define DMCLA0  0
+#define DMCLA1  1
+#define DMCLA2  2
+#define DMCLA3  3
+#define DMCLA4  4
+#define DMCTA0  5
+#define DMCTA1  6
+#define DMCTA2  7
+
+#define DMCRB   _SFR_MEM8(0xA5)
+#define DMPGB0  0
+#define DMPGB1  1
+#define DMPGB2  2
+#define DMPGB3  3
+#define DMPGB4  4
+#define SASKB   5
+#define SY1TB   6
+#define DMARB   7
+
+#define DMCRA   _SFR_MEM8(0xA6)
+#define DMPGA0  0
+#define DMPGA1  1
+#define DMPGA2  2
+#define DMPGA3  3
+#define DMPGA4  4
+#define SASKA   5
+#define SY1TA   6
+#define DMARA   7
+
+#define DMDRB   _SFR_MEM8(0xA7)
+#define DMAB0   0
+#define DMAB1   1
+#define DMAB2   2
+#define DMAB3   3
+#define DMDNB0  4
+#define DMDNB1  5
+#define DMDNB2  6
+#define DMDNB3  7
+
+#define DMDRA   _SFR_MEM8(0xA8)
+#define DMAA0   0
+#define DMAA1   1
+#define DMAA2   2
+#define DMAA3   3
+#define DMDNA0  4
+#define DMDNA1  5
+#define DMDNA2  6
+#define DMDNA3  7
+
+#define CHCR    _SFR_MEM8(0xA9)
+#define BWM0    0
+#define BWM1    1
+#define BWM2    2
+#define BWM3    3
+
+#define CHDN    _SFR_MEM8(0xAA)
+#define BBDN0   0
+#define BBDN1   1
+#define BBDN2   2
+#define BBDN3   3
+#define BBDN4   4
+#define ADCDN   5
+
+#define SFIDCB  _SFR_MEM8(0xAB)
+#define SFIDTB0 0
+#define SFIDTB1 1
+#define SFIDTB2 2
+#define SFIDTB3 3
+#define SFIDTB4 4
+#define SEMEB   7
+
+#define SFIDLB  _SFR_MEM8(0xAC)
+#define SFIDLB0 0
+#define SFIDLB1 1
+#define SFIDLB2 2
+#define SFIDLB3 3
+#define SFIDLB4 4
+#define SFIDLB5 5
+
+#define WUPTB   _SFR_MEM8(0xAD)
+#define WUPTB0  0
+#define WUPTB1  1
+#define WUPTB2  2
+#define WUPTB3  3
+#define WUPTB4  4
+
+#define WUPLB   _SFR_MEM8(0xAE)
+#define WUPLB0  0
+#define WUPLB1  1
+#define WUPLB2  2
+#define WUPLB3  3
+#define WUPLB4  4
+#define WUPLB5  5
+
+#define SFID1B  _SFR_MEM8(0xAF)
+
+#define SFID2B  _SFR_MEM8(0xB0)
+
+#define SFID3B  _SFR_MEM8(0xB1)
+
+#define SFID4B  _SFR_MEM8(0xB2)
+
+#define WUP1B   _SFR_MEM8(0xB3)
+
+#define WUP2B   _SFR_MEM8(0xB4)
+
+#define WUP3B   _SFR_MEM8(0xB5)
+
+#define WUP4B   _SFR_MEM8(0xB6)
+
+#define SFIDCA  _SFR_MEM8(0xB7)
+#define SFIDTA0 0
+#define SFIDTA1 1
+#define SFIDTA2 2
+#define SFIDTA3 3
+#define SFIDTA4 4
+#define SEMEA   7
+
+#define SFIDLA  _SFR_MEM8(0xB8)
+#define SFIDLA0 0
+#define SFIDLA1 1
+#define SFIDLA2 2
+#define SFIDLA3 3
+#define SFIDLA4 4
+#define SFIDLA5 5
+
+#define WUPTA   _SFR_MEM8(0xB9)
+#define WUPTA0  0
+#define WUPTA1  1
+#define WUPTA2  2
+#define WUPTA3  3
+#define WUPTA4  4
+
+#define WUPLA   _SFR_MEM8(0xBA)
+#define WUPLA0  0
+#define WUPLA1  1
+#define WUPLA2  2
+#define WUPLA3  3
+#define WUPLA4  4
+#define WUPLA5  5
+
+#define SFID1A  _SFR_MEM8(0xBB)
+
+#define SFID2A  _SFR_MEM8(0xBC)
+
+#define SFID3A  _SFR_MEM8(0xBD)
+
+#define SFID4A  _SFR_MEM8(0xBE)
+
+#define WUP1A   _SFR_MEM8(0xBF)
+
+#define WUP2A   _SFR_MEM8(0xC0)
+
+#define WUP3A   _SFR_MEM8(0xC1)
+
+#define WUP4A   _SFR_MEM8(0xC2)
+
+#define CLKOD   _SFR_MEM8(0xC3)
+
+#define CLKOCR  _SFR_MEM8(0xC4)
+#define CLKOS0  0
+#define CLKOS1  1
+#define CLKOEN  2
+
+#define XFUSE   _SFR_MEM8(0xC5)
+
+#define SRCCAL  _SFR_MEM8(0xC6)
+#define SRCCAL0 0
+#define SRCCAL1 1
+#define SRCCAL2 2
+#define SRCCAL3 3
+#define SRCCAL4 4
+#define SRCCAL5 5
+#define SRCTC0  6
+#define SRCTC1  7
+
+#define FRCCAL  _SFR_MEM8(0xC7)
+#define FRCCAL0 0
+#define FRCCAL1 1
+#define FRCCAL2 2
+#define FRCCAL3 3
+#define FRCCAL4 4
+#define FRCTC   5
+
+#define CMSR    _SFR_MEM8(0xC8)
+#define ECF     0
+
+#define CMOCR   _SFR_MEM8(0xC9)
+#define FRCAO   0
+#define SRCAO   1
+#define FRCACT  2
+#define SRCACT  3
+
+#define SUPFR   _SFR_MEM8(0xCA)
+#define AVCCRF  0
+#define AVCCLF  1
+
+#define SUPCR   _SFR_MEM8(0xCB)
+#define AVCCRM  0
+#define AVCCLM  1
+#define PVEN    2
+#define DVDIS   4
+#define AVEN    5
+#define AVDIC   6
+
+#define SUPCA1  _SFR_MEM8(0xCC)
+#define PV22    2
+#define PVDIC   3
+#define PVCAL0  4
+#define PVCAL1  5
+#define PVCAL2  6
+#define PVCAL3  7
+
+#define SUPCA2  _SFR_MEM8(0xCD)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL3  3
+
+#define SUPCA3  _SFR_MEM8(0xCE)
+#define ACAL4   0
+#define ACAL5   1
+#define ACAL6   2
+#define ACAL7   3
+#define DCAL4   4
+#define DCAL5   5
+#define DCAL6   6
+
+#define SUPCA4  _SFR_MEM8(0xCF)
+#define ACAL0   0
+#define ACAL1   1
+#define ACAL2   2
+#define ACAL3   3
+#define DCAL0   4
+#define DCAL1   5
+#define DCAL2   6
+#define DCAL3   7
+
+#define CALRDY  _SFR_MEM8(0xD0)
+
+#define VMCAL   _SFR_MEM8(0xD1)
+#define VMCAL0  0
+#define VMCAL1  1
+#define VMCAL2  2
+
+#define DFS     _SFR_MEM8(0xD2)
+#define DFFLRF  0
+#define DFUFL   1
+#define DFOFL   2
+
+/* Combine DFTLL and DFTLH */
+#define DFTL    _SFR_MEM16(0xD3)
+
+#define DFTLL   _SFR_MEM8(0xD3)
+#define DFTLH   _SFR_MEM8(0xD4)
+
+#define DFL     _SFR_MEM8(0xD5)
+#define DFFLS0  0
+#define DFFLS1  1
+#define DFFLS2  2
+#define DFFLS3  3
+#define DFFLS4  4
+#define DFFLS5  5
+#define DFCLR   7
+
+#define DFWP    _SFR_MEM8(0xD6)
+#define DFWP0   0
+#define DFWP1   1
+#define DFWP2   2
+#define DFWP3   3
+#define DFWP4   4
+#define DFWP5   5
+
+#define DFRP    _SFR_MEM8(0xD7)
+#define DFRP0   0
+#define DFRP1   1
+#define DFRP2   2
+#define DFRP3   3
+#define DFRP4   4
+#define DFRP5   5
+
+#define DFD     _SFR_MEM8(0xD8)
+
+#define DFI     _SFR_MEM8(0xD9)
+#define DFFLIM  0
+#define DFERIM  1
+
+#define DFC     _SFR_MEM8(0xDA)
+#define DFFLC0  0
+#define DFFLC1  1
+#define DFFLC2  2
+#define DFFLC3  3
+#define DFFLC4  4
+#define DFFLC5  5
+#define DFDRA   7
+
+#define SFS     _SFR_MEM8(0xDB)
+#define SFFLRF  0
+#define SFUFL   1
+#define SFOFL   2
+
+#define SFL     _SFR_MEM8(0xDC)
+#define SFFLS0  0
+#define SFFLS1  1
+#define SFFLS2  2
+#define SFFLS3  3
+#define SFFLS4  4
+#define SFCLR   7
+
+#define SFWP    _SFR_MEM8(0xDD)
+#define SFWP0   0
+#define SFWP1   1
+#define SFWP2   2
+#define SFWP3   3
+#define SFWP4   4
+
+#define SFRP    _SFR_MEM8(0xDE)
+#define SFRP0   0
+#define SFRP1   1
+#define SFRP2   2
+#define SFRP3   3
+#define SFRP4   4
+
+#define SFD     _SFR_MEM8(0xDF)
+
+#define SFI     _SFR_MEM8(0xE0)
+#define SFFLIM  0
+#define SFERIM  1
+
+#define SFC     _SFR_MEM8(0xE1)
+#define SFFLC0  0
+#define SFFLC1  1
+#define SFFLC2  2
+#define SFFLC3  3
+#define SFFLC4  4
+#define SFDRA   7
+
+#define SSMCR   _SFR_MEM8(0xE2)
+#define SSMTX   0
+#define SSMTM   1
+#define SSMTGE  2
+#define SSMTPE  3
+#define SSMPVE  4
+#define SSMTAE  5
+#define SETRPA  6
+#define SETRPB  7
+
+#define SSMRCR  _SFR_MEM8(0xE3)
+#define SSMPA   0
+#define SSMPB   1
+#define SSMADA  2
+#define SSMADB  3
+#define SSMPVS  4
+#define SSMIFA  5
+#define SSMIDSE 6
+#define SSMTMOE 7
+
+#define SSMFBR  _SFR_MEM8(0xE4)
+#define SSMFID0 0
+#define SSMFID1 1
+#define SSMFID2 2
+#define SSMDFDT 3
+#define SSMHADT 4
+#define SSMPLDT 5
+
+#define SSMRR   _SFR_MEM8(0xE5)
+#define SSMR    0
+#define SSMST   1
+
+#define SSMSR   _SFR_MEM8(0xE6)
+#define SSMESM0 0
+#define SSMESM1 1
+#define SSMESM2 2
+#define SSMESM3 3
+#define SSMERR  7
+
+#define SSMIFR  _SFR_MEM8(0xE7)
+#define SSMIF   0
+
+#define SSMIMR  _SFR_MEM8(0xE8)
+#define SSMIM   0
+
+#define MSMSTR  _SFR_MEM8(0xE9)
+#define SSMMST0 0
+#define SSMMST1 1
+#define SSMMST2 2
+#define SSMMST3 3
+#define SSMMST4 4
+
+#define SSMSTR  _SFR_MEM8(0xEA)
+#define SSMSTA0 0
+#define SSMSTA1 1
+#define SSMSTA2 2
+#define SSMSTA3 3
+#define SSMSTA4 4
+#define SSMSTA5 5
+
+#define SSMXSR  _SFR_MEM8(0xEB)
+#define SSMSTB0 0
+#define SSMSTB1 1
+#define SSMSTB2 2
+#define SSMSTB3 3
+#define SSMSTB4 4
+#define SSMSTB5 5
+
+#define MSMCR1  _SFR_MEM8(0xEC)
+#define MSMSM00 0
+#define MSMSM01 1
+#define MSMSM02 2
+#define MSMSM03 3
+#define MSMSM10 4
+#define MSMSM11 5
+#define MSMSM12 6
+#define MSMSM13 7
+
+#define MSMCR2  _SFR_MEM8(0xED)
+#define MSMSM20 0
+#define MSMSM21 1
+#define MSMSM22 2
+#define MSMSM23 3
+#define MSMSM30 4
+#define MSMSM31 5
+#define MSMSM32 6
+#define MSMSM33 7
+
+#define MSMCR3  _SFR_MEM8(0xEE)
+#define MSMSM40 0
+#define MSMSM41 1
+#define MSMSM42 2
+#define MSMSM43 3
+#define MSMSM50 4
+#define MSMSM51 5
+#define MSMSM52 6
+#define MSMSM53 7
+
+#define MSMCR4  _SFR_MEM8(0xEF)
+#define MSMSM60 0
+#define MSMSM61 1
+#define MSMSM62 2
+#define MSMSM63 3
+#define MSMSM70 4
+#define MSMSM71 5
+#define MSMSM72 6
+#define MSMSM73 7
+
+#define GTCR    _SFR_MEM8(0xF0)
+#define RXTEHA  0
+#define GAPMA   1
+#define DARA    2
+#define IWUPA   3
+#define RXTEHB  4
+#define GAPMB   5
+#define DARB    6
+#define IWUPB   7
+
+#define SOTC1A  _SFR_MEM8(0xF1)
+#define CAROEA1 0
+#define AMPOEA1 1
+#define SYTOEA1 2
+#define MANOEA1 3
+#define WUPEA1  4
+#define SFIDEA1 5
+#define RROEA1  6
+#define WCOBOE1 7
+
+#define SOTC2A  _SFR_MEM8(0xF2)
+#define CAROEA2 0
+#define AMPOEA2 1
+#define SYTOEA2 2
+#define MANOEA2 3
+#define WUPEA2  4
+#define SFIDEA2 5
+#define RROEA2  6
+#define WCOBOE2 7
+
+#define SOTC1B  _SFR_MEM8(0xF3)
+#define CAROEB1 0
+#define AMPOEB1 1
+#define SYTOEB1 2
+#define MANOEB1 3
+#define WUPEB1  4
+#define SFIDEB1 5
+#define RROEB1  6
+#define WCOAOE1 7
+
+#define SOTC2B  _SFR_MEM8(0xF4)
+#define CAROEB2 0
+#define AMPOEB2 1
+#define SYTOEB2 2
+#define MANOEB2 3
+#define WUPEB2  4
+#define SFIDEB2 5
+#define RROEB2  6
+#define WCOAOE2 7
+
+#define EOTC1A  _SFR_MEM8(0xF5)
+#define CARFEA1 0
+#define AMPFEA1 1
+#define SYTFEA1 2
+#define MANFEA1 3
+#define TMOFEA1 4
+#define TELREA1 5
+#define RRFEA1  6
+#define EOTBFE1 7
+
+#define EOTC2A  _SFR_MEM8(0xF6)
+#define CARFEA2 0
+#define AMPFEA2 1
+#define SYTFEA2 2
+#define MANFEA2 3
+#define TMOFEA2 4
+#define TELREA2 5
+#define RRFEA2  6
+#define EOTBFE2 7
+
+#define EOTC3A  _SFR_MEM8(0xF7)
+#define CARFEA3 0
+#define AMPFEA3 1
+#define SYTFEA3 2
+#define MANFEA3 3
+#define TMOFEA3 4
+#define TELREA3 5
+#define RRFEA3  6
+#define EOTBFE3 7
+
+#define EOTC1B  _SFR_MEM8(0xF8)
+#define CARFEB1 0
+#define AMPFEB1 1
+#define SYTFEB1 2
+#define MANFEB1 3
+#define TMOFEB1 4
+#define TELREB1 5
+#define RRFEB1  6
+#define EOTAFE1 7
+
+#define EOTC2B  _SFR_MEM8(0xF9)
+#define CARFEB2 0
+#define AMPFEB2 1
+#define SYTFEB2 2
+#define MANFEB2 3
+#define TMOFEB2 4
+#define TELREB2 5
+#define RRFEB2  6
+#define EOTAFE2 7
+
+#define EOTC3B  _SFR_MEM8(0xFA)
+#define CARFEB3 0
+#define AMPFEB3 1
+#define SYTFEB3 2
+#define MANFEB3 3
+#define TMOFEB3 4
+#define TELREB3 5
+#define RRFEB3  6
+#define EOTAFE3 7
+
+#define WCOTOA  _SFR_MEM8(0xFB)
+
+#define WCOTOB  _SFR_MEM8(0xFC)
+
+#define SOTTOA  _SFR_MEM8(0xFD)
+
+#define SOTTOB  _SFR_MEM8(0xFE)
+
+#define SSMFCR  _SFR_MEM8(0xFF)
+#define SSMIDSO 0
+#define SSMIDSF 1
+
+#define FESR    _SFR_MEM8(0x100)
+#define LBSAT   0
+#define HBSAT   1
+#define XRDY    2
+#define PLCK    3
+#define ANTS    4
+
+#define FEEN1   _SFR_MEM8(0x101)
+#define PLEN    0
+#define PLCAL   1
+#define XTOEN   2
+#define LNAEN   3
+#define ADEN    4
+#define ADCLK   5
+#define PLSP1   6
+#define ATEN    7
+
+#define FEEN2   _SFR_MEM8(0x102)
+#define SDRX    0
+#define SDTX    1
+#define PAEN    2
+#define TMPM    3
+#define PLPEN   4
+#define XTPEN   5
+#define CPBIA   6
+
+#define FELNA   _SFR_MEM8(0x103)
+#define LBH0    0
+#define LBH1    1
+#define LBH2    2
+#define LBH3    3
+#define LBL0    4
+#define LBL1    5
+#define LBL2    6
+#define LBL3    7
+
+#define FEAT    _SFR_MEM8(0x104)
+#define ANTN0   0
+#define ANTN1   1
+#define ANTN2   2
+#define ANTN3   3
+
+#define FEPAC   _SFR_MEM8(0x105)
+
+#define FEVCT   _SFR_MEM8(0x106)
+#define FEVCT0  0
+#define FEVCT1  1
+#define FEVCT2  2
+#define FEVCT3  3
+
+#define FEBT    _SFR_MEM8(0x107)
+#define CTN20   0
+#define CTN21   1
+#define RTN20   2
+#define RTN21   3
+
+#define FEMS    _SFR_MEM8(0x108)
+#define PLLS0   0
+#define PLLS1   1
+#define PLLS2   2
+#define PLLS3   3
+#define PLLM0   4
+#define PLLM1   5
+#define PLLM2   6
+#define PLLM3   7
+
+#define FETN4   _SFR_MEM8(0x109)
+#define CTN40   0
+#define CTN41   1
+#define CTN42   2
+#define CTN43   3
+#define RTN40   4
+#define RTN41   5
+#define RTN42   6
+#define RTN43   7
+
+#define FECR    _SFR_MEM8(0x10A)
+#define LBNHB   0
+#define S4N3    1
+#define ANDP    2
+#define ADHS    3
+#define PLCKG   4
+#define ANPS    5
+
+#define FEVCO   _SFR_MEM8(0x10B)
+#define CPCC0   0
+#define CPCC1   1
+#define CPCC2   2
+#define CPCC3   3
+#define VCOB0   4
+#define VCOB1   5
+#define VCOB2   6
+#define VCOB3   7
+
+#define FEALR   _SFR_MEM8(0x10C)
+#define RNGE0   0
+#define RNGE1   1
+
+#define FEANT   _SFR_MEM8(0x10D)
+#define LVLC0   0
+#define LVLC1   1
+#define LVLC2   2
+#define LVLC3   3
+
+#define FEBIA   _SFR_MEM8(0x10E)
+#define IFAEN   7
+
+/* Reserved [0x10F..0x11F] */
+
+#define TMFSM   _SFR_MEM8(0x120)
+#define TMSSM0  0
+#define TMSSM1  1
+#define TMSSM2  2
+#define TMSSM3  3
+#define TMMSM0  4
+#define TMMSM1  5
+#define TMMSM2  6
+
+/* Combine TMCRL and TMCRH */
+#define TMCR    _SFR_MEM16(0x121)
+
+#define TMCRL   _SFR_MEM8(0x121)
+#define TMCRH   _SFR_MEM8(0x122)
+
+#define TMCSB   _SFR_MEM8(0x123)
+
+/* Combine TMCIL and TMCIH */
+#define TMCI    _SFR_MEM16(0x124)
+
+#define TMCIL   _SFR_MEM8(0x124)
+#define TMCIH   _SFR_MEM8(0x125)
+
+/* Combine TMCPL and TMCPH */
+#define TMCP    _SFR_MEM16(0x126)
+
+#define TMCPL   _SFR_MEM8(0x126)
+#define TMCPH   _SFR_MEM8(0x127)
+
+#define TMSHR   _SFR_MEM8(0x128)
+
+/* Combine TMTLL and TMTLH */
+#define TMTL    _SFR_MEM16(0x129)
+
+#define TMTLL   _SFR_MEM8(0x129)
+#define TMTLH   _SFR_MEM8(0x12A)
+
+#define TMSSC   _SFR_MEM8(0x12B)
+#define TMSSP0  0
+#define TMSSP1  1
+#define TMSSP2  2
+#define TMSSP3  3
+#define TMSSL0  4
+#define TMSSL1  5
+#define TMSSL2  6
+#define TMSSH   7
+
+#define TMSR    _SFR_MEM8(0x12C)
+#define TMTCF   0
+
+#define TMCR2   _SFR_MEM8(0x12D)
+#define TMCRCE  0
+#define TMCRCL0 1
+#define TMCRCL1 2
+#define TMNRZE  3
+#define TMPOL   4
+#define TMSSE   5
+#define TMMSB   6
+
+#define TMCR1   _SFR_MEM8(0x12E)
+#define TMPIS0  0
+#define TMPIS1  1
+#define TMPIS2  2
+#define TMSCS   3
+#define TMCIM   4
+
+#define RXBC1   _SFR_MEM8(0x12F)
+#define RXCEA   0
+#define RXCBLA0 1
+#define RXCBLA1 2
+#define RXMSBA  3
+#define RXCEB   4
+#define RXCBLB0 5
+#define RXCBLB1 6
+#define RXMSBB  7
+
+#define RXBC2   _SFR_MEM8(0x130)
+#define RXBPB   0
+#define RXBF    1
+#define RXBCLR  2
+
+#define RXTLLB  _SFR_MEM8(0x131)
+
+#define RXTLHB  _SFR_MEM8(0x132)
+#define RXTLHB0 0
+#define RXTLHB1 1
+#define RXTLHB2 2
+#define RXTLHB3 3
+
+#define RXCRLB  _SFR_MEM8(0x133)
+
+#define RXCRHB  _SFR_MEM8(0x134)
+
+#define RXCSBB  _SFR_MEM8(0x135)
+
+#define RXCILB  _SFR_MEM8(0x136)
+
+#define RXCIHB  _SFR_MEM8(0x137)
+
+#define RXCPLB  _SFR_MEM8(0x138)
+
+#define RXCPHB  _SFR_MEM8(0x139)
+
+#define RXDSB   _SFR_MEM8(0x13A)
+
+#define RXTLLA  _SFR_MEM8(0x13B)
+
+#define RXTLHA  _SFR_MEM8(0x13C)
+#define RXTLHA0 0
+#define RXTLHA1 1
+#define RXTLHA2 2
+#define RXTLHA3 3
+
+#define RXCRLA  _SFR_MEM8(0x13D)
+
+#define RXCRHA  _SFR_MEM8(0x13E)
+
+#define RXCSBA  _SFR_MEM8(0x13F)
+
+#define RXCILA  _SFR_MEM8(0x140)
+
+#define RXCIHA  _SFR_MEM8(0x141)
+
+#define RXCPLA  _SFR_MEM8(0x142)
+
+#define RXCPHA  _SFR_MEM8(0x143)
+
+#define RXDSA   _SFR_MEM8(0x144)
+
+#define CRCCR   _SFR_MEM8(0x145)
+#define CRCRS   0
+#define REFLI   1
+#define REFLO   2
+
+#define CRCDOR  _SFR_MEM8(0x146)
+
+#define IDB0    _SFR_MEM8(0x147)
+
+#define IDB1    _SFR_MEM8(0x148)
+
+#define IDB2    _SFR_MEM8(0x149)
+
+#define IDB3    _SFR_MEM8(0x14A)
+
+#define IDC     _SFR_MEM8(0x14B)
+#define IDL0    0
+#define IDL1    1
+#define IDBO0   2
+#define IDBO1   3
+#define IDFIM   5
+#define IDCLR   6
+#define IDCE    7
+
+#define IDS     _SFR_MEM8(0x14C)
+#define IDOK    0
+#define IDFULL  1
+
+#define RSSAV   _SFR_MEM8(0x14D)
+
+#define RSSPK   _SFR_MEM8(0x14E)
+
+#define RSSL    _SFR_MEM8(0x14F)
+
+#define RSSH    _SFR_MEM8(0x150)
+
+#define RSSC    _SFR_MEM8(0x151)
+#define RSUP0   0
+#define RSUP1   1
+#define RSUP2   2
+#define RSUP3   3
+#define RSWLH   4
+#define RSHRX   5
+#define RSPKF   6
+
+#define DBCR    _SFR_MEM8(0x152)
+#define DBMD    0
+#define DBCS    1
+#define DBTMS   2
+#define DBHA    3
+
+#define DBTC    _SFR_MEM8(0x153)
+
+#define DBENB   _SFR_MEM8(0x154)
+
+#define DBENC   _SFR_MEM8(0x155)
+
+#define DBGSW   _SFR_MEM8(0x156)
+#define DBGGS0  0
+#define DBGGS1  1
+#define DBGGS2  2
+#define DBGGS3  3
+#define CPBFOS0 4
+#define CPBFOS1 5
+#define CPBF    6
+#define DBGSE   7
+
+#define SFFR    _SFR_MEM8(0x157)
+#define RFL0    0
+#define RFL1    1
+#define RFL2    2
+#define RFC     3
+#define TFL0    4
+#define TFL1    5
+#define TFL2    6
+#define TFC     7
+
+#define SFIR    _SFR_MEM8(0x158)
+#define RIL0    0
+#define RIL1    1
+#define RIL2    2
+#define SRIE    3
+#define TIL0    4
+#define TIL1    5
+#define TIL2    6
+#define STIE    7
+
+#define EECR2   _SFR_MEM8(0x159)
+#define EEBRE   0
+
+#define PGMST   _SFR_MEM8(0x15A)
+#define PGMSYN0 0
+#define PGMSYN1 1
+#define PGMSYN2 2
+#define PGMSYN3 3
+#define PGMSYN4 4
+
+#define EEST    _SFR_MEM8(0x15B)
+#define EESYN0  0
+#define EESYN1  1
+#define EESYN2  2
+#define EESYN3  3
+
+#define RSIFG   _SFR_MEM8(0x15C)
+
+#define RSLDV   _SFR_MEM8(0x15D)
+
+#define RSHDV   _SFR_MEM8(0x15E)
+
+#define RSCOM   _SFR_MEM8(0x15F)
+#define RSDC    0
+#define RSIFC   1
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCI0_vect            _VECTOR(3)
+#define PCI0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCI1_vect            _VECTOR(4)
+#define PCI1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMON_vect            _VECTOR(5)
+#define VMON_vect_num        5
+
+/* AVCC Reset Interrupt */
+#define AVCCR_vect            _VECTOR(6)
+#define AVCCR_vect_num        6
+
+/* AVCC Low Interrupt */
+#define AVCCL_vect            _VECTOR(7)
+#define AVCCL_vect_num        7
+
+/* Timer 0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(8)
+#define T0INT_vect_num        8
+
+/* Timer/Counter1 Compare Match Interrupt */
+#define T1COMP_vect            _VECTOR(9)
+#define T1COMP_vect_num        9
+
+/* Timer/Counter1 Overflow Interrupt */
+#define T1OVF_vect            _VECTOR(10)
+#define T1OVF_vect_num        10
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMP_vect            _VECTOR(11)
+#define T2COMP_vect_num        11
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVF_vect            _VECTOR(12)
+#define T2OVF_vect_num        12
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAP_vect            _VECTOR(13)
+#define T3CAP_vect_num        13
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMP_vect            _VECTOR(14)
+#define T3COMP_vect_num        14
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVF_vect            _VECTOR(15)
+#define T3OVF_vect_num        15
+
+/* Timer/Counter4 Capture Event Interrupt */
+#define T4CAP_vect            _VECTOR(16)
+#define T4CAP_vect_num        16
+
+/* Timer/Counter4 Compare Match Interrupt */
+#define T4COMP_vect            _VECTOR(17)
+#define T4COMP_vect_num        17
+
+/* Timer/Counter4 Overflow Interrupt */
+#define T4OVF_vect            _VECTOR(18)
+#define T4OVF_vect_num        18
+
+/* Timer/Counter5 Compare Match Interrupt */
+#define T5COMP_vect            _VECTOR(19)
+#define T5COMP_vect_num        19
+
+/* Timer/Counter5 Overflow Interrupt */
+#define T5OVF_vect            _VECTOR(20)
+#define T5OVF_vect_num        20
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPI_vect            _VECTOR(21)
+#define SPI_vect_num        21
+
+/* SPI Rx Buffer Interrupt */
+#define SRX_FIFO_vect            _VECTOR(22)
+#define SRX_FIFO_vect_num        22
+
+/* SPI Tx Buffer Interrupt */
+#define STX_FIFO_vect            _VECTOR(23)
+#define STX_FIFO_vect_num        23
+
+/* Sequencer State Machine Interrupt */
+#define SSM_vect            _VECTOR(24)
+#define SSM_vect_num        24
+
+/* Data FIFO fill level reached Interrupt */
+#define DFFLR_vect            _VECTOR(25)
+#define DFFLR_vect_num        25
+
+/* Data FIFO overflow or underflow error Interrupt */
+#define DFOUE_vect            _VECTOR(26)
+#define DFOUE_vect_num        26
+
+/* RSSI/Preamble FIFO fill level reached Interrupt */
+#define SFFLR_vect            _VECTOR(27)
+#define SFFLR_vect_num        27
+
+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
+#define SFOUE_vect            _VECTOR(28)
+#define SFOUE_vect_num        28
+
+/* Tx Modulator Telegram Finish Interrupt */
+#define TMTCF_vect            _VECTOR(29)
+#define TMTCF_vect_num        29
+
+/* UHF receiver wake up ok on Rx path B */
+#define UHF_WCOB_vect            _VECTOR(30)
+#define UHF_WCOB_vect_num        30
+
+/* UHF receiver wake up ok on Rx path A */
+#define UHF_WCOA_vect            _VECTOR(31)
+#define UHF_WCOA_vect_num        31
+
+/* UHF receiver start of telegram ok on Rx path B */
+#define UHF_SOTB_vect            _VECTOR(32)
+#define UHF_SOTB_vect_num        32
+
+/* UHF receiver start of telegram ok on Rx path A */
+#define UHF_SOTA_vect            _VECTOR(33)
+#define UHF_SOTA_vect_num        33
+
+/* UHF receiver end of telegram on Rx path B */
+#define UHF_EOTB_vect            _VECTOR(34)
+#define UHF_EOTB_vect_num        34
+
+/* UHF receiver end of telegram on Rx path A */
+#define UHF_EOTA_vect            _VECTOR(35)
+#define UHF_EOTA_vect_num        35
+
+/* UHF receiver new bit on Rx path B */
+#define UHF_NBITB_vect            _VECTOR(36)
+#define UHF_NBITB_vect_num        36
+
+/* UHF receiver new bit on Rx path A */
+#define UHF_NBITA_vect            _VECTOR(37)
+#define UHF_NBITA_vect_num        37
+
+/* External input Clock monitoring Interrupt */
+#define EXCM_vect            _VECTOR(38)
+#define EXCM_vect_num        38
+
+/* EEPROM Ready Interrupt */
+#define ERDY_vect            _VECTOR(39)
+#define ERDY_vect_num        39
+
+/* Store Program Memory Ready */
+#define SPMR_vect            _VECTOR(40)
+#define SPMR_vect_num        40
+
+/* IDSCAN Full Interrupt */
+#define IDFULL_vect            _VECTOR(41)
+#define IDFULL_vect_num        41
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 168
+#else
+#  define _VECTORS_SIZE 168U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x8000
+#  define FLASHEND     0xCFFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x8000U
+#  define FLASHEND     0xCFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      1024
+#  define RAMEND       0x05FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x05FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  16
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  16U
+#  define E2END       0x03FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_EXTCLKEN    (unsigned char)~_BV(0)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(1)
+#define FUSE_BOOTRST     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x61
+
+
+
+
+#endif /* #ifdef _AVR_ATA8510_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/ioat94k.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/ioat94k.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: ioat94k.h 602 2004-11-01 22:23:56Z arcanum $ */
 
 /* avr/ioat94k.h - definitions for AT94K series FPSLIC(tm) */
 
@@ -562,5 +562,4 @@
 #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
 #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
 
-
 #endif /* _AVR_IOAT94K_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iocan128.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iocan128.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2004,2005, Colin O'Flynn <coflynn@newae.com>
+/* Copyright (c) 2004,2005,2006 Colin O'Flynn <coflynn@newae.com>
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,14 +28,1975 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iocan128.h 1767 2008-10-17 23:27:53Z arcanum $ */
 
 /* iocan128.h - definitions for CAN128 */
 
 #ifndef _AVR_IOCAN128_H_
 #define _AVR_IOCAN128_H_ 1
 
-#include <avr/iocanxx.h>
+
+/* I/O registers and bit definitions. */
+
+/* RegDef:  Port A */
+#define PINA   _SFR_IO8(0x00)
+#define DDRA   _SFR_IO8(0x01)
+#define PORTA  _SFR_IO8(0x02)
+
+/* RegDef:  Port B */
+#define PINB   _SFR_IO8(0x03)
+#define DDRB   _SFR_IO8(0x04)
+#define PORTB  _SFR_IO8(0x05)
+
+/* RegDef:  Port C */
+#define PINC   _SFR_IO8(0x06)
+#define DDRC   _SFR_IO8(0x07)
+#define PORTC  _SFR_IO8(0x08)
+
+/* RegDef:  Port D */
+#define PIND   _SFR_IO8(0x09)
+#define DDRD   _SFR_IO8(0x0A)
+#define PORTD  _SFR_IO8(0x0B)
+
+/* RegDef:  Port E */
+#define PINE   _SFR_IO8(0x0C)
+#define DDRE   _SFR_IO8(0x0D)
+#define PORTE  _SFR_IO8(0x0E)
+
+/* RegDef:  Port F */
+#define PINF   _SFR_IO8(0x0F)
+#define DDRF   _SFR_IO8(0x10)
+#define PORTF  _SFR_IO8(0x11)
+
+/* RegDef:  Port G */
+#define PING   _SFR_IO8(0x12)
+#define DDRG   _SFR_IO8(0x13)
+#define PORTG  _SFR_IO8(0x14)
+
+/* RegDef:  Timer/Counter 0 interrupt Flag Register */
+#define TIFR0  _SFR_IO8(0x15)
+
+/* RegDef:  Timer/Counter 1 interrupt Flag Register */
+#define TIFR1  _SFR_IO8(0x16)
+
+/* RegDef:  Timer/Counter 2 interrupt Flag Register */
+#define TIFR2  _SFR_IO8(0x17)
+
+/* RegDef:  Timer/Counter 3 interrupt Flag Register */
+#define TIFR3  _SFR_IO8(0x18)
+
+/* RegDef:  External Interrupt Flag Register */
+#define EIFR   _SFR_IO8(0x1C)
+
+/* RegDef:  External Interrupt Mask Register */
+#define EIMSK  _SFR_IO8(0x1D)
+
+/* RegDef:  General Purpose I/O Register 0 */
+#define GPIOR0 _SFR_IO8(0x1E)
+
+/* RegDef:  EEPROM Control Register */
+#define EECR   _SFR_IO8(0x1F)
+
+/* RegDef:  EEPROM Data Register */
+#define EEDR   _SFR_IO8(0x20)
+
+/* RegDef:  EEPROM Address Register */
+#define EEAR   _SFR_IO16(0x21)
+#define EEARL  _SFR_IO8(0x21)
+#define EEARH  _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+/* RegDef:  General Timer/Counter Control Register */
+#define GTCCR  _SFR_IO8(0x23)
+
+/* RegDef:  Timer/Counter Control Register A */
+#define TCCR0A _SFR_IO8(0x24)
+
+/* RegDef:  Timer/Counter Register */
+#define TCNT0  _SFR_IO8(0x26)
+
+/* RegDef:  Output Compare Register A */
+#define OCR0A  _SFR_IO8(0x27)
+
+/* RegDef:  General Purpose I/O Register 1 */
+#define GPIOR1 _SFR_IO8(0x2A)
+
+/* RegDef:  General Purpose I/O Register 2 */
+#define GPIOR2 _SFR_IO8(0x2B)
+
+/* RegDef:  SPI Control Register */
+#define SPCR   _SFR_IO8(0x2C)
+
+/* RegDef:  SPI Status Register */
+#define SPSR   _SFR_IO8(0x2D)
+
+/* RegDef:  SPI Data Register */
+#define SPDR   _SFR_IO8(0x2E)
+
+/* RegDef:  Analog Comperator Control and Status Register */
+#define ACSR   _SFR_IO8(0x30)
+
+/* RegDef:  On-chip Debug Register */
+#define OCDR   _SFR_IO8(0x31)
+
+/* RegDef:  Sleep Mode Control Register */
+#define SMCR   _SFR_IO8(0x33)
+
+/* RegDef:  MCU Status Register */
+#define MCUSR  _SFR_IO8(0x34)
+
+/* RegDef:  MCU Control Rgeister */
+#define MCUCR  _SFR_IO8(0x35)
+
+/* RegDef:  Store Program Memory Control and Status Register */
+#define SPMCSR _SFR_IO8(0x37)
+
+/* RegDef:  RAMPZ register. */
+#define RAMPZ  _SFR_IO8(0x3B)
+
+/* RegDef:  Watchdog Timer Control Register */
+#define WDTCR  _SFR_MEM8(0x60)
+
+/* RegDef:  Clock Prescale Register */
+#define CLKPR  _SFR_MEM8(0x61)
+
+/* RegDef:  Oscillator Calibration Register */
+#define OSCCAL _SFR_MEM8(0x66)
+
+/* RegDef:  External Interrupt Control Register A */
+#define EICRA  _SFR_MEM8(0x69)
+
+/* RegDef:  External Interrupt Control Register B */
+#define EICRB  _SFR_MEM8(0x6A)
+
+/* RegDef:  Timer/Counter 0 Interrupt Mask Register */
+#define TIMSK0 _SFR_MEM8(0x6E)
+
+/* RegDef:  Timer/Counter 1 Interrupt Mask Register */
+#define TIMSK1 _SFR_MEM8(0x6F)
+
+/* RegDef:  Timer/Counter 2 Interrupt Mask Register */
+#define TIMSK2 _SFR_MEM8(0x70)
+
+/* RegDef:  Timer/Counter 3 Interrupt Mask Register */
+#define TIMSK3 _SFR_MEM8(0x71)
+
+/* RegDef:  External Memory Control Register A */
+#define XMCRA _SFR_MEM8(0x74)
+
+/* RegDef:  External Memory Control Register A */
+#define XMCRB _SFR_MEM8(0x75)
+
+/* RegDef:  ADC Data Register */
+#ifndef __ASSEMBLER__
+#define ADC    _SFR_MEM16(0x78)
+#endif
+#define ADCW   _SFR_MEM16(0x78)
+#define ADCL   _SFR_MEM8(0x78)
+#define ADCH   _SFR_MEM8(0x79)
+
+/* RegDef:  ADC Control and Status Register A */
+#define ADCSRA _SFR_MEM8(0x7A)
+
+/* RegDef:  ADC Control and Status Register B */
+#define ADCSRB _SFR_MEM8(0x7B)
+
+/* RegDef:  ADC Multiplex Selection Register */
+#define ADMUX  _SFR_MEM8(0x7C)
+
+/* RegDef:  Digital Input Disable Register 0 */
+#define DIDR0  _SFR_MEM8(0x7E)
+
+/* RegDef:  Digital Input Disable Register 1 */
+#define DIDR1  _SFR_MEM8(0x7F)
+
+/* RegDef:  Timer/Counter1 Control Register A */
+#define TCCR1A _SFR_MEM8(0x80)
+
+/* RegDef:  Timer/Counter1 Control Register B */
+#define TCCR1B _SFR_MEM8(0x81)
+
+/* RegDef:  Timer/Counter1 Control Register C */
+#define TCCR1C _SFR_MEM8(0x82)
+
+/* RegDef:  Timer/Counter1 Register */
+#define TCNT1  _SFR_MEM16(0x84)
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1H _SFR_MEM8(0x85)
+
+/* RegDef:  Timer/Counter1 Input Capture Register */
+#define ICR1   _SFR_MEM16(0x86)
+#define ICR1L  _SFR_MEM8(0x86)
+#define ICR1H  _SFR_MEM8(0x87)
+
+/* RegDef:  Timer/Counter1 Output Compare Register A */
+#define OCR1A  _SFR_MEM16(0x88)
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AH _SFR_MEM8(0x89)
+
+/* RegDef:  Timer/Counter1 Output Compare Register B */
+#define OCR1B  _SFR_MEM16(0x8A)
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BH _SFR_MEM8(0x8B)
+
+/* RegDef:  Timer/Counter1 Output Compare Register C */
+#define OCR1C  _SFR_MEM16(0x8C)
+#define OCR1CL _SFR_MEM8(0x8C)
+#define OCR1CH _SFR_MEM8(0x8D)
+
+/* RegDef:  Timer/Counter3 Control Register A */
+#define TCCR3A _SFR_MEM8(0x90)
+
+/* RegDef:  Timer/Counter3 Control Register B */
+#define TCCR3B _SFR_MEM8(0x91)
+
+/* RegDef:  Timer/Counter3 Control Register C */
+#define TCCR3C _SFR_MEM8(0x92)
+
+/* RegDef:  Timer/Counter3 Register */
+#define TCNT3  _SFR_MEM16(0x94)
+#define TCNT3L _SFR_MEM8(0x94)
+#define TCNT3H _SFR_MEM8(0x95)
+
+/* RegDef:  Timer/Counter3 Input Capture Register */
+#define ICR3   _SFR_MEM16(0x96)
+#define ICR3L  _SFR_MEM8(0x96)
+#define ICR3H  _SFR_MEM8(0x97)
+
+/* RegDef:  Timer/Counter3 Output Compare Register A */
+#define OCR3A  _SFR_MEM16(0x98)
+#define OCR3AL _SFR_MEM8(0x98)
+#define OCR3AH _SFR_MEM8(0x99)
+
+/* RegDef:  Timer/Counter3 Output Compare Register B */
+#define OCR3B  _SFR_MEM16(0x9A)
+#define OCR3BL _SFR_MEM8(0x9A)
+#define OCR3BH _SFR_MEM8(0x9B)
+
+/* RegDef:  Timer/Counter3 Output Compare Register C */
+#define OCR3C  _SFR_MEM16(0x9C)
+#define OCR3CL _SFR_MEM8(0x9C)
+#define OCR3CH _SFR_MEM8(0x9D)
+
+/* RegDef:  Timer/Counter2 Control Register A */
+#define TCCR2A _SFR_MEM8(0xB0)
+
+/* RegDef:  Timer/Counter2 Register */
+#define TCNT2  _SFR_MEM8(0xB2)
+
+/* RegDef:  Timer/Counter2 Output Compare Register */
+#define OCR2A  _SFR_MEM8(0xB3)
+
+/* RegDef:  Asynchronous Status Register */
+#define ASSR   _SFR_MEM8(0xB6)
+
+/* RegDef:  TWI Bit Rate Register */
+#define TWBR   _SFR_MEM8(0xB8)
+
+/* RegDef:  TWI Status Register */
+#define TWSR   _SFR_MEM8(0xB9)
+
+/* RegDef:  TWI (Slave) Address Register */
+#define TWAR   _SFR_MEM8(0xBA)
+
+/* RegDef:  TWI Data Register */
+#define TWDR   _SFR_MEM8(0xBB)
+
+/* RegDef:  TWI Control Register */
+#define TWCR   _SFR_MEM8(0xBC)
+
+/* RegDef:  USART0 Control and Status Register A */
+#define UCSR0A _SFR_MEM8(0xC0)
+
+/* RegDef:  USART0 Control and Status Register B */
+#define UCSR0B _SFR_MEM8(0xC1)
+
+/* RegDef:  USART0 Control and Status Register C */
+#define UCSR0C _SFR_MEM8(0xC2)
+
+/* RegDef:  USART0 Baud Rate Register */
+#define UBRR0  _SFR_MEM16(0xC4)
+#define UBRR0L _SFR_MEM8(0xC4)
+#define UBRR0H _SFR_MEM8(0xC5)
+
+/* RegDef:  USART0 I/O Data Register */
+#define UDR0   _SFR_MEM8(0xC6)
+
+/* RegDef:  USART1 Control and Status Register A */
+#define UCSR1A _SFR_MEM8(0xC8)
+
+/* RegDef:  USART1 Control and Status Register B */
+#define UCSR1B _SFR_MEM8(0xC9)
+
+/* RegDef:  USART1 Control and Status Register C */
+#define UCSR1C _SFR_MEM8(0xCA)
+
+/* RegDef:  USART1 Baud Rate Register */
+#define UBRR1  _SFR_MEM16(0xCC)
+#define UBRR1L _SFR_MEM8(0xCC)
+#define UBRR1H _SFR_MEM8(0xCD)
+
+/* RegDef:  USART1 I/O Data Register */
+#define UDR1   _SFR_MEM8(0xCE)
+
+/* RegDef:  CAN General Control Register*/
+#define CANGCON _SFR_MEM8(0xD8)
+
+/* RegDef:  CAN General Status Register*/
+#define CANGSTA _SFR_MEM8(0xD9)
+
+/* RegDef:  CAN General Interrupt Register*/
+#define CANGIT _SFR_MEM8(0xDA)
+
+/* RegDef:  CAN General Interrupt Enable Register*/
+#define CANGIE _SFR_MEM8(0xDB)
+
+/* Word Definition:  CAN Enable MOb Register*/
+#define CANEN _SFR_MEM16(0xDC) 
+
+/* RegDef:  CAN Enable MOb Register*/
+#define CANEN2 _SFR_MEM8(0xDC)
+
+/* RegDef:  CAN Enable MOb Register*/
+#define CANEN1 _SFR_MEM8(0xDD)
+
+/* Word Definition:  CAN Enable Interrupt MOb Register*/
+#define CANIE _SFR_MEM16(0xDE) 
+
+/* RegDef:  CAN Enable Interrupt MOb Register*/
+#define CANIE2 _SFR_MEM8(0xDE)
+
+/* RegDef:  CAN Enable Interrupt MOb Register*/
+#define CANIE1 _SFR_MEM8(0xDF)
+
+/* RegDef:  CAN Status Interrupt MOb Register*/
+/*
+ * WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT
+ * register.
+ */
+#define CANSIT  _SFR_MEM16(0xE0)
+#define CANSIT2 _SFR_MEM8(0xE0)
+#define CANSIT1 _SFR_MEM8(0xE1)
+
+/* RegDef:  CAN Bit Timing Register 1*/
+#define CANBT1 _SFR_MEM8(0xE2)
+
+/* RegDef:  CAN Bit Timing Register 2*/
+#define CANBT2 _SFR_MEM8(0xE3)
+
+/* RegDef:  CAN Bit Timing Register 3*/
+#define CANBT3 _SFR_MEM8(0xE4)
+
+/* RegDef:  CAN Timer Control Register*/
+#define CANTCON _SFR_MEM8(0xE5)
+
+/* RegDef:  CAN Timer Register*/
+#define CANTIM _SFR_MEM16(0xE6)
+#define CANTIML _SFR_MEM8(0xE6)
+#define CANTIMH _SFR_MEM8(0xE7)
+
+/* RegDef:  CAN TTC Timer Register*/
+#define CANTTC _SFR_MEM16(0xE8)
+#define CANTTCL _SFR_MEM8(0xE8)
+#define CANTTCH _SFR_MEM8(0xE9)
+
+/* RegDef:  CAN Transmitt Error Counter Register*/
+#define CANTEC _SFR_MEM8(0xEA)
+
+/* RegDef:  CAN Receive Error Counter Register*/
+#define CANREC _SFR_MEM8(0xEB)
+
+/* RegDef:  CAN Highest Priority MOb Register*/
+#define CANHPMOB _SFR_MEM8(0xEC)
+
+/* RegDef:  CAN Page MOb Register*/
+#define CANPAGE _SFR_MEM8(0xED)
+
+/* RegDef:  CAN MOb Status Register*/
+#define CANSTMOB _SFR_MEM8(0xEE)
+
+/* RegDef:  CAN MOb Control and DLC Register*/
+#define CANCDMOB _SFR_MEM8(0xEF)
+
+/* RegDef:  CAN Identifier Tag Registers*/
+#define CANIDT  _SFR_MEM32(0xF0)
+
+#define CANIDT4 _SFR_MEM8(0xF0)
+#define CANIDT3 _SFR_MEM8(0xF1)
+#define CANIDT2 _SFR_MEM8(0xF2)
+#define CANIDT1 _SFR_MEM8(0xF3)
+
+/* RegDef:  CAN Identifier Mask Registers */
+#define CANIDM  _SFR_MEM32(0xF4)
+
+#define CANIDM4 _SFR_MEM8(0xF4)
+#define CANIDM3 _SFR_MEM8(0xF5)
+#define CANIDM2 _SFR_MEM8(0xF6)
+#define CANIDM1 _SFR_MEM8(0xF7)
+
+/* RegDef:  CAN TTC Timer Register*/
+#define CANSTM _SFR_MEM16(0xF8)
+#define CANSTML _SFR_MEM8(0xF8)
+#define CANSTMH _SFR_MEM8(0xF9)
+
+/* RegDef:  CAN Message Register*/
+#define CANMSG _SFR_MEM8(0xFA)
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+#define SIG_INTERRUPT3			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+#define SIG_INTERRUPT4			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+#define SIG_INTERRUPT5			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num		7
+#define INT6_vect			_VECTOR(7)
+#define SIG_INTERRUPT6			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+#define SIG_INTERRUPT7			_VECTOR(8)
+
+/* Timer/Counter2 Compare Match */
+#define TIMER2_COMP_vect_num	9
+#define TIMER2_COMP_vect		_VECTOR(9)
+#define SIG_OUTPUT_COMPARE2		_VECTOR(9)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		10
+#define TIMER2_OVF_vect			_VECTOR(10)
+#define SIG_OVERFLOW2			_VECTOR(10)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	11
+#define TIMER1_CAPT_vect		_VECTOR(11)
+#define SIG_INPUT_CAPTURE1		_VECTOR(11)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	12
+#define TIMER1_COMPA_vect		_VECTOR(12)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
+
+/* Timer/Counter Compare Match B */
+#define TIMER1_COMPB_vect_num	13
+#define TIMER1_COMPB_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	14
+#define TIMER1_COMPC_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE1C		_VECTOR(14)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		15
+#define TIMER1_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW1			_VECTOR(15)
+
+/* Timer/Counter0 Compare Match */
+#define TIMER0_COMP_vect_num	16
+#define TIMER0_COMP_vect		_VECTOR(16)
+#define SIG_OUTPUT_COMPARE0		_VECTOR(16)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		17
+#define TIMER0_OVF_vect			_VECTOR(17)
+#define SIG_OVERFLOW0			_VECTOR(17)
+
+/* CAN Transfer Complete or Error */
+#define CANIT_vect_num		18
+#define CANIT_vect			_VECTOR(18)
+#define SIG_CAN_INTERRUPT1		_VECTOR(18)
+
+/* CAN Timer Overrun */
+#define OVRIT_vect_num		19
+#define OVRIT_vect			_VECTOR(19)
+#define SIG_CAN_OVERFLOW1		_VECTOR(19)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		20
+#define SPI_STC_vect			_VECTOR(20)
+#define SIG_SPI				_VECTOR(20)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		21
+#define USART0_RX_vect			_VECTOR(21)
+#define SIG_UART0_RECV			_VECTOR(21)
+#define SIG_USART0_RECV			_VECTOR(21)
+
+/* USART0 Data Register Empty */
+#define USART0_UDRE_vect_num	22
+#define USART0_UDRE_vect		_VECTOR(22)
+#define SIG_UART0_DATA			_VECTOR(22)
+#define SIG_USART0_DATA			_VECTOR(22)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		23
+#define USART0_TX_vect			_VECTOR(23)
+#define SIG_UART0_TRANS			_VECTOR(23)
+#define SIG_USART0_TRANS		_VECTOR(23)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	24
+#define ANALOG_COMP_vect		_VECTOR(24)
+#define SIG_COMPARATOR			_VECTOR(24)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		25
+#define ADC_vect			_VECTOR(25)
+#define SIG_ADC				_VECTOR(25)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		26
+#define EE_READY_vect			_VECTOR(26)
+#define SIG_EEPROM_READY		_VECTOR(26)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	27
+#define TIMER3_CAPT_vect		_VECTOR(27)
+#define SIG_INPUT_CAPTURE3		_VECTOR(27)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	28
+#define TIMER3_COMPA_vect		_VECTOR(28)
+#define SIG_OUTPUT_COMPARE3A		_VECTOR(28)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	29
+#define TIMER3_COMPB_vect		_VECTOR(29)
+#define SIG_OUTPUT_COMPARE3B		_VECTOR(29)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	30
+#define TIMER3_COMPC_vect		_VECTOR(30)
+#define SIG_OUTPUT_COMPARE3C		_VECTOR(30)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		31
+#define TIMER3_OVF_vect			_VECTOR(31)
+#define SIG_OVERFLOW3			_VECTOR(31)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		32
+#define USART1_RX_vect			_VECTOR(32)
+#define SIG_UART1_RECV			_VECTOR(32)
+#define SIG_USART1_RECV			_VECTOR(32)
+
+/* USART1, Data Register Empty */
+#define USART1_UDRE_vect_num	33
+#define USART1_UDRE_vect		_VECTOR(33)
+#define SIG_UART1_DATA			_VECTOR(33)
+#define SIG_USART1_DATA			_VECTOR(33)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		34
+#define USART1_TX_vect			_VECTOR(34)
+#define SIG_UART1_TRANS			_VECTOR(34)
+#define SIG_USART1_TRANS		_VECTOR(34)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num		35
+#define TWI_vect			_VECTOR(35)
+#define SIG_2WIRE_SERIAL		_VECTOR(35)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		36
+#define SPM_READY_vect			_VECTOR(36)
+#define SIG_SPM_READY			_VECTOR(36)
+
+#define _VECTORS_SIZE 148
+
+/* The Register Bit names are represented by their bit number (0-7). */
+
+/* Register Bits [ASSR]  */
+/* Asynchronous Status Register */
+#define    EXCLK      4
+#define    AS2        3
+#define    TCN2UB     2
+#define    OCR2UB     1
+#define    TCR2UB     0
+/* End Register Bits */
+
+/* Register Bits [TWCR] */
+/* 2-wire Control Register - TWCR */
+#define    TWINT        7
+#define    TWEA         6
+#define    TWSTA        5
+#define    TWSTO        4
+#define    TWWC         3
+#define    TWEN         2
+#define    TWIE         0
+/* End Register Bits */
+
+/* Register Bits [TWAR]  */
+/* 2-wire Address Register - TWAR */
+#define    TWA6         7
+#define    TWA5         6
+#define    TWA4         5
+#define    TWA3         4
+#define    TWA2         3
+#define    TWA1         2
+#define    TWA0         1
+#define    TWGCE        0
+/* End Register Bits */
+
+/* Register Bits [TWSR]  */
+/* 2-wire Status Register - TWSR */
+#define    TWS7         7
+#define    TWS6         6
+#define    TWS5         5
+#define    TWS4         4
+#define    TWS3         3
+#define    TWPS1        1
+#define    TWPS0        0
+/* End Register Bits */
+
+/* Register Bits [XMCRB]  */
+/* External Memory Control Register B - XMCRB */
+#define    XMBK         7
+#define    XMM2         2
+#define    XMM1         1
+#define    XMM0         0
+/* End Register Bits */
+
+/* Register Bits [XMCRA]  */
+/* External Memory Control Register A - XMCRA */
+#define    SRE         7
+#define    SRL2        6
+#define    SRL1        5
+#define    SRL0        4
+#define    SRW11       3
+#define    SRW10       2
+#define    SRW01       1
+#define    SRW00       0
+/* End Register Bits */
+
+/* Register Bits [RAMPZ]  */
+/* RAM Page Z select register - RAMPZ */
+#define     RAMPZ0      0
+/* End Register Bits */
+
+/* Register Bits [EICRA]  */
+/* External Interrupt Control Register A - EICRA */
+#define    ISC31        7
+#define    ISC30        6
+#define    ISC21        5
+#define    ISC20        4
+#define    ISC11        3
+#define    ISC10        2
+#define    ISC01        1
+#define    ISC00        0
+/* End Register Bits */
+
+/* Register Bits [EICRB]  */
+/* External Interrupt Control Register B - EICRB */
+#define    ISC71        7
+#define    ISC70        6
+#define    ISC61        5
+#define    ISC60        4
+#define    ISC51        3
+#define    ISC50        2
+#define    ISC41        1
+#define    ISC40        0
+/* End Register Bits */
+
+/* Register Bits [SPMCSR]  */
+/* Store Program Memory Control Register - SPMCSR, SPMCR */
+#define    SPMIE        7
+#define    RWWSB        6
+#define    RWWSRE       4
+#define    BLBSET       3
+#define    PGWRT        2
+#define    PGERS        1
+#define    SPMEN        0
+/* End Register Bits */
+
+/* Register Bits [EIMSK]  */
+/* External Interrupt MaSK register - EIMSK */
+#define    INT7         7
+#define    INT6         6
+#define    INT5         5
+#define    INT4         4
+#define    INT3         3
+#define    INT2         2
+#define    INT1         1
+#define    INT0         0
+/* End Register Bits */
+
+/* Register Bits [EIFR]  */
+/* External Interrupt Flag Register - EIFR */
+#define    INTF7        7
+#define    INTF6        6
+#define    INTF5        5
+#define    INTF4        4
+#define    INTF3        3
+#define    INTF2        2
+#define    INTF1        1
+#define    INTF0        0
+/* End Register Bits */
+
+/* Register Bits [TCCR2]  */
+/* Timer/Counter 2 Control Register - TCCR2 */
+#define    FOC2A        7
+#define    WGM20        6
+#define    COM2A1       5
+#define    COM2A0       4
+#define    WGM21        3
+#define    CS22         2
+#define    CS21         1
+#define    CS20         0
+/* End Register Bits */
+
+/* Register Bits [TCCR1A]  */
+/* Timer/Counter 1 Control and Status Register A - TCCR1A */
+#define    COM1A1       7
+#define    COM1A0       6
+#define    COM1B1       5
+#define    COM1B0       4
+#define    COM1C1       3
+#define    COM1C0       2
+#define    WGM11        1
+#define    WGM10        0
+/* End Register Bits */
+
+/* Register Bits [TCCR3A]  */
+/* Timer/Counter 3 Control and Status Register A - TCCR3A */
+#define    COM3A1       7
+#define    COM3A0       6
+#define    COM3B1       5
+#define    COM3B0       4
+#define    COM3C1       3
+#define    COM3C0       2
+#define    WGM31        1
+#define    WGM30        0
+/* End Register Bits */
+
+/* Register Bits [TCCR1B]  */
+/* Timer/Counter 1 Control and Status Register B - TCCR1B */
+#define    ICNC1        7
+#define    ICES1        6
+#define    WGM13        4
+#define    WGM12        3
+#define    CS12         2
+#define    CS11         1
+#define    CS10         0
+/* End Register Bits */
+
+/* Register Bits [TCCR3B]  */
+/* Timer/Counter 3 Control and Status Register B - TCCR3B */
+#define    ICNC3        7
+#define    ICES3        6
+#define    WGM33        4
+#define    WGM32        3
+#define    CS32         2
+#define    CS31         1
+#define    CS30         0
+/* End Register Bits */
+
+/* Register Bits [TCCR3C]  */
+/* Timer/Counter 3 Control Register C - TCCR3C */
+#define    FOC3A        7
+#define    FOC3B        6
+#define    FOC3C        5
+/* End Register Bits */
+
+/* Register Bits [TCCR1C]  */
+/* Timer/Counter 1 Control Register C - TCCR1C */
+#define    FOC1A        7
+#define    FOC1B        6
+#define    FOC1C        5
+/* End Register Bits */
+
+/* Register Bits [OCDR]  */
+/* On-chip Debug Register - OCDR */
+#define    IDRD         7
+#define    OCDR7        7
+#define    OCDR6        6
+#define    OCDR5        5
+#define    OCDR4        4
+#define    OCDR3        3
+#define    OCDR2        2
+#define    OCDR1        1
+#define    OCDR0        0
+/* End Register Bits */
+
+/* Register Bits [WDTCR]  */
+/* Watchdog Timer Control Register - WDTCR */
+#define    WDCE         4
+#define    WDE          3
+#define    WDP2         2
+#define    WDP1         1
+#define    WDP0         0
+/* End Register Bits */
+
+/* Register Bits [SPSR]  */
+/* SPI Status Register - SPSR */
+#define    SPIF         7
+#define    WCOL         6
+#define    SPI2X        0
+/* End Register Bits */
+
+/* Register Bits [SPCR]  */
+/* SPI Control Register - SPCR */
+#define    SPIE         7
+#define    SPE          6
+#define    DORD         5
+#define    MSTR         4
+#define    CPOL         3
+#define    CPHA         2
+#define    SPR1         1
+#define    SPR0         0
+/* End Register Bits */
+
+/* Register Bits [UCSR1C]  */
+/* USART1 Register C - UCSR1C */
+#define    UMSEL1       6
+#define    UPM11        5
+#define    UPM10        4
+#define    USBS1        3
+#define    UCSZ11       2
+#define    UCSZ10       1
+#define    UCPOL1       0
+/* End Register Bits */
+
+/* Register Bits [UCSR0C]  */
+/* USART0 Register C - UCSR0C */
+#define    UMSEL0       6
+#define    UPM01        5
+#define    UPM00        4
+#define    USBS0        3
+#define    UCSZ01       2
+#define    UCSZ00       1
+#define    UCPOL0       0
+/* End Register Bits */
+
+/* Register Bits [UCSR1A]  */
+/* USART1 Status Register A - UCSR1A */
+#define    RXC1         7
+#define    TXC1         6
+#define    UDRE1        5
+#define    FE1          4
+#define    DOR1         3
+#define    UPE1         2
+#define    U2X1         1
+#define    MPCM1        0
+/* End Register Bits */
+
+/* Register Bits [UCSR0A]  */
+/* USART0 Status Register A - UCSR0A */
+#define    RXC0         7
+#define    TXC0         6
+#define    UDRE0        5
+#define    FE0          4
+#define    DOR0         3
+#define    UPE0         2
+#define    U2X0         1
+#define    MPCM0        0
+/* End Register Bits */
+
+/* Register Bits [UCSR1B]  */
+/* USART1 Control Register B - UCSR1B */
+#define    RXCIE1       7
+#define    TXCIE1       6
+#define    UDRIE1       5
+#define    RXEN1        4
+#define    TXEN1        3
+#define    UCSZ12       2
+#define    RXB81        1
+#define    TXB81        0
+/* End Register Bits */
+
+/* Register Bits [UCSR0B]  */
+/* USART0 Control Register B - UCSR0B */
+#define    RXCIE0       7
+#define    TXCIE0       6
+#define    UDRIE0       5
+#define    RXEN0        4
+#define    TXEN0        3
+#define    UCSZ02       2
+#define    RXB80        1
+#define    TXB80        0
+/* End Register Bits */
+
+/* Register Bits [ACSR]  */
+/* Analog Comparator Control and Status Register - ACSR */
+#define    ACD          7
+#define    ACBG         6
+#define    ACO          5
+#define    ACI          4
+#define    ACIE         3
+#define    ACIC         2
+#define    ACIS1        1
+#define    ACIS0        0
+/* End Register Bits */
+
+/* Register Bits [ADCSRA]  */
+/* ADC Control and status register - ADCSRA */
+#define    ADEN         7
+#define    ADSC         6
+#define    ADATE        5
+#define    ADIF         4
+#define    ADIE         3
+#define    ADPS2        2
+#define    ADPS1        1
+#define    ADPS0        0
+/* End Register Bits */
+
+/* 
+   The ADHSM bit has been removed from all documentation, 
+   as being not needed at all since the comparator has proven 
+   to be fast enough even without feeding it more power.
+*/
+
+/* Register Bits [ADCSRB]  */
+/* ADC Control and status register - ADCSRB */
+#define    ACME         6
+#define    ADTS2        2
+#define    ADTS1        1
+#define    ADTS0        0
+/* End Register Bits */
+
+/* Register Bits [ADMUX]  */
+/* ADC Multiplexer select - ADMUX */
+#define    REFS1        7
+#define    REFS0        6
+#define    ADLAR        5
+#define    MUX4         4
+#define    MUX3         3
+#define    MUX2         2
+#define    MUX1         1
+#define    MUX0         0
+/* End Register Bits */
+
+/* Register Bits [DIDR0]  */
+/* Digital Input Disable Register 0 */
+#define    ADC7D        7
+#define    ADC6D        6
+#define    ADC5D        5
+#define    ADC4D        4
+#define    ADC3D        3
+#define    ADC2D        2
+#define    ADC1D        1
+#define    ADC0D        0
+/* End Register Bits */
+
+/* Register Bits [DIDR1]  */
+/* Digital Input Disable Register 1 */
+#define    AIN1D        1
+#define    AIN0D        0
+/* End Register Bits */
+
+/* Register Bits [PORTA]  */
+/* Port A Data Register - PORTA */
+#define    PA7          7
+#define    PA6          6
+#define    PA5          5
+#define    PA4          4
+#define    PA3          3
+#define    PA2          2
+#define    PA1          1
+#define    PA0          0
+/* End Register Bits */
+
+/* Register Bits [DDRA]  */
+/* Port A Data Direction Register - DDRA */
+#define    DDA7         7
+#define    DDA6         6
+#define    DDA5         5
+#define    DDA4         4
+#define    DDA3         3
+#define    DDA2         2
+#define    DDA1         1
+#define    DDA0         0
+/* End Register Bits */
+
+/* Register Bits [PINA]  */
+/* Port A Input Pins - PINA */
+#define    PINA7        7
+#define    PINA6        6
+#define    PINA5        5
+#define    PINA4        4
+#define    PINA3        3
+#define    PINA2        2
+#define    PINA1        1
+#define    PINA0        0
+/* End Register Bits */
+
+/* Register Bits [PORTB]  */
+/* Port B Data Register - PORTB */
+#define    PB7          7
+#define    PB6          6
+#define    PB5          5
+#define    PB4          4
+#define    PB3          3
+#define    PB2          2
+#define    PB1          1
+#define    PB0          0
+/* End Register Bits */
+
+/* Register Bits [DDRB]  */
+/* Port B Data Direction Register - DDRB */
+#define    DDB7         7
+#define    DDB6         6
+#define    DDB5         5
+#define    DDB4         4
+#define    DDB3         3
+#define    DDB2         2
+#define    DDB1         1
+#define    DDB0         0
+/* End Register Bits */
+
+/* Register Bits [PINB]  */
+/* Port B Input Pins - PINB */
+#define    PINB7        7
+#define    PINB6        6
+#define    PINB5        5
+#define    PINB4        4
+#define    PINB3        3
+#define    PINB2        2
+#define    PINB1        1
+#define    PINB0        0
+/* End Register Bits */
+
+/* Register Bits [PORTC]  */
+/* Port C Data Register - PORTC */
+#define    PC7          7
+#define    PC6          6
+#define    PC5          5
+#define    PC4          4
+#define    PC3          3
+#define    PC2          2
+#define    PC1          1
+#define    PC0          0
+/* End Register Bits */
+
+/* Register Bits [DDRC]  */
+/* Port C Data Direction Register - DDRC */
+#define    DDC7         7
+#define    DDC6         6
+#define    DDC5         5
+#define    DDC4         4
+#define    DDC3         3
+#define    DDC2         2
+#define    DDC1         1
+#define    DDC0         0
+/* End Register Bits */
+
+/* Register Bits [PINC]  */
+/* Port C Input Pins - PINC */
+#define    PINC7        7
+#define    PINC6        6
+#define    PINC5        5
+#define    PINC4        4
+#define    PINC3        3
+#define    PINC2        2
+#define    PINC1        1
+#define    PINC0        0
+/* End Register Bits */
+
+/* Register Bits [PORTD]  */
+/* Port D Data Register - PORTD */
+#define    PD7          7
+#define    PD6          6
+#define    PD5          5
+#define    PD4          4
+#define    PD3          3
+#define    PD2          2
+#define    PD1          1
+#define    PD0          0
+/* End Register Bits */
+
+/* Register Bits [DDRD]  */
+/* Port D Data Direction Register - DDRD */
+#define    DDD7         7
+#define    DDD6         6
+#define    DDD5         5
+#define    DDD4         4
+#define    DDD3         3
+#define    DDD2         2
+#define    DDD1         1
+#define    DDD0         0
+/* End Register Bits */
+
+/* Register Bits [PIND]  */
+/* Port D Input Pins - PIND */
+#define    PIND7        7
+#define    PIND6        6
+#define    PIND5        5
+#define    PIND4        4
+#define    PIND3        3
+#define    PIND2        2
+#define    PIND1        1
+#define    PIND0        0
+/* End Register Bits */
+
+/* Register Bits [PORTE]  */
+/* Port E Data Register - PORTE */
+#define    PE7          7
+#define    PE6          6
+#define    PE5          5
+#define    PE4          4
+#define    PE3          3
+#define    PE2          2
+#define    PE1          1
+#define    PE0          0
+/* End Register Bits */
+
+/* Register Bits [DDRE]  */
+/* Port E Data Direction Register - DDRE */
+#define    DDE7         7
+#define    DDE6         6
+#define    DDE5         5
+#define    DDE4         4
+#define    DDE3         3
+#define    DDE2         2
+#define    DDE1         1
+#define    DDE0         0
+/* End Register Bits */
+
+/* Register Bits [PINE]  */
+/* Port E Input Pins - PINE */
+#define    PINE7        7
+#define    PINE6        6
+#define    PINE5        5
+#define    PINE4        4
+#define    PINE3        3
+#define    PINE2        2
+#define    PINE1        1
+#define    PINE0        0
+/* End Register Bits */
+
+/* Register Bits [PORTF]  */
+/* Port F Data Register - PORTF */
+#define    PF7          7
+#define    PF6          6
+#define    PF5          5
+#define    PF4          4
+#define    PF3          3
+#define    PF2          2
+#define    PF1          1
+#define    PF0          0
+/* End Register Bits */
+
+/* Register Bits [DDRF]  */
+/* Port F Data Direction Register - DDRF */
+#define    DDF7         7
+#define    DDF6         6
+#define    DDF5         5
+#define    DDF4         4
+#define    DDF3         3
+#define    DDF2         2
+#define    DDF1         1
+#define    DDF0         0
+/* End Register Bits */
+
+/* Register Bits [PINF]  */
+/* Port F Input Pins - PINF */
+#define    PINF7        7
+#define    PINF6        6
+#define    PINF5        5
+#define    PINF4        4
+#define    PINF3        3
+#define    PINF2        2
+#define    PINF1        1
+#define    PINF0        0
+/* End Register Bits */
+
+/* Register Bits [PORTG]  */
+/* Port G Data Register - PORTG */
+#define    PG4          4
+#define    PG3          3
+#define    PG2          2
+#define    PG1          1
+#define    PG0          0
+/* End Register Bits */
+
+/* Register Bits [DDRG]  */
+/* Port G Data Direction Register - DDRG */
+#define    DDG4         4
+#define    DDG3         3
+#define    DDG2         2
+#define    DDG1         1
+#define    DDG0         0
+/* End Register Bits */
+
+/* Register Bits [PING]  */
+/* Port G Input Pins - PING */
+#define    PING4        4
+#define    PING3        3
+#define    PING2        2
+#define    PING1        1
+#define    PING0        0
+/* End Register Bits */
+
+
+/* Register Bits [TIFR0]  */
+/* Timer/Counter 0 interrupt Flag Register */
+#define    OCF0A        1
+#define    TOV0         0
+/* End Register Bits */
+
+/* Register Bits [TIFR1]  */
+/* Timer/Counter 1 interrupt Flag Register */
+#define    ICF1       5
+#define    OCF1C      3
+#define    OCF1B      2
+#define    OCF1A      1
+#define    TOV1       0
+/* End Register Bits */
+
+/* Register Bits [TIFR2]  */
+/* Timer/Counter 2 interrupt Flag Register */
+#define    OCF2A      1
+#define    TOV2       0
+/* End Register Bits */
+
+/* Register Bits [TIFR3]  */
+/* Timer/Counter 3 interrupt Flag Register */
+#define    ICF3       5
+#define    OCF3C      3
+#define    OCF3B      2
+#define    OCF3A      1
+#define    TOV3       0
+/* End Register Bits */
+
+/* Register Bits [GPIOR0]  */
+/* General Purpose I/O Register 0 */
+#define    GPIOR07     7
+#define    GPIOR06     6
+#define    GPIOR05     5
+#define    GPIOR04     4
+#define    GPIOR03     3
+#define    GPIOR02     2
+#define    GPIOR01     1
+#define    GPIOR00     0
+/* End Register Bits */
+
+/* Register Bits [GPIOR1]  */
+/* General Purpose I/O Register 1 */
+#define    GPIOR17     7
+#define    GPIOR16     6
+#define    GPIOR15     5
+#define    GPIOR14     4
+#define    GPIOR13     3
+#define    GPIOR12     2
+#define    GPIOR11     1
+#define    GPIOR10     0
+/* End Register Bits */
+
+/* Register Bits [GPIOR2]  */
+/* General Purpose I/O Register 2 */
+#define    GPIOR27     7
+#define    GPIOR26     6
+#define    GPIOR25     5
+#define    GPIOR24     4
+#define    GPIOR23     3
+#define    GPIOR22     2
+#define    GPIOR21     1
+#define    GPIOR20     0
+/* End Register Bits */
+
+/* Register Bits [EECR]  */
+/* EEPROM Control Register */
+#define    EERIE       3
+#define    EEMWE       2
+#define    EEWE        1
+#define    EERE        0
+/* End Register Bits */
+
+/* Register Bits [EEDR]  */
+/* EEPROM Data Register */
+#define    EEDR7     7
+#define    EEDR6     6
+#define    EEDR5     5
+#define    EEDR4     4
+#define    EEDR3     3
+#define    EEDR2     2
+#define    EEDR1     1
+#define    EEDR0     0
+/* End Register Bits */
+
+/* Register Bits [EEARL]  */
+/* EEPROM Address Register */
+#define    EEAR7     7
+#define    EEAR6     6
+#define    EEAR5     5
+#define    EEAR4     4
+#define    EEAR3     3
+#define    EEAR2     2
+#define    EEAR1     1
+#define    EEAR0     0
+/* End Register Bits */
+
+/* Register Bits [EEARH]  */
+/* EEPROM Address Register */
+#define    EEAR11    3
+#define    EEAR10    2
+#define    EEAR9     1
+#define    EEAR8     0
+/* End Register Bits */
+
+/* Register Bits [GTCCR]  */
+/* General Timer/Counter Control Register  */
+#define    TSM      7
+#define    PSR2     1
+#define    PSR310   0
+/* End Register Bits */
+
+/* Register Bits [TCCR0A]  */
+/* Timer/Counter Control Register A */
+/* ALSO COVERED IN GENERIC SECTION */
+#define    FOC0A    7
+#define    WGM00    6
+#define    COM0A1   5
+#define    COM0A0   4
+#define    WGM01    3
+#define    CS02     2
+#define    CS01     1
+#define    CS00     0
+/* End Register Bits */
+
+/* Register Bits [OCR0A]  */
+/* Output Compare Register A */
+#define    OCR0A7     7
+#define    OCR0A6     6
+#define    OCR0A5     5
+#define    OCR0A4     4
+#define    OCR0A3     3
+#define    OCR0A2     2
+#define    OCR0A1     1
+#define    OCR0A0     0
+/* End Register Bits */
+
+
+/* Register Bits [SPIDR]  */
+/* SPI Data Register */
+#define    SPD7     7
+#define    SPD6     6
+#define    SPD5     5
+#define    SPD4     4
+#define    SPD3     3
+#define    SPD2     2
+#define    SPD1     1
+#define    SPD0     0
+/* End Register Bits */
+
+/* Register Bits [SMCR]  */
+/* Sleep Mode Control Register */
+#define    SM2     3
+#define    SM1     2
+#define    SM0     1
+#define    SE      0
+/* End Register Bits */
+
+/* Register Bits [MCUSR]  */
+/* MCU Status Register */
+#define    JTRF    4
+#define    WDRF    3
+#define    BORF    2
+#define    EXTRF   1
+#define    PORF    0
+/* End Register Bits */
+
+/* Register Bits [MCUCR]  */
+/* MCU Control Register */
+#define    JTD     7
+#define    PUD     4
+#define    IVSEL   1
+#define    IVCE    0
+/* End Register Bits */
+
+/* Register Bits [CLKPR]  */
+/* Clock Prescale Register */
+#define    CLKPCE     7
+#define    CLKPS3     3
+#define    CLKPS2     2
+#define    CLKPS1     1
+#define    CLKPS0     0
+/* End Register Bits */
+
+/* Register Bits [OSCCAL]  */
+/* Oscillator Calibration Register */
+#define    CAL6     6
+#define    CAL5     5
+#define    CAL4     4
+#define    CAL3     3
+#define    CAL2     2
+#define    CAL1     1
+#define    CAL0     0
+/* End Register Bits */
+
+/* Register Bits [TIMSK0]  */
+/* Timer/Counter 0 interrupt mask Register */
+#define    OCIE0A      1
+#define    TOIE0       0
+/* End Register Bits */
+
+/* Register Bits [TIMSK1]  */
+/* Timer/Counter 1 interrupt mask Register */
+#define    ICIE1       5
+#define    OCIE1C      3
+#define    OCIE1B      2
+#define    OCIE1A      1
+#define    TOIE1       0
+/* End Register Bits */
+
+/* Register Bits [TIMSK2]  */
+/* Timer/Counter 2 interrupt mask Register */
+#define    OCIE2A      1
+#define    TOIE2       0
+/* End Register Bits */
+
+/* Register Bits [TIMSK3]  */
+/* Timer/Counter 3 interrupt mask Register */
+#define    ICIE3       5
+#define    OCIE3C      3
+#define    OCIE3B      2
+#define    OCIE3A      1
+#define    TOIE3       0
+/* End Register Bits */
+
+//Begin CAN specific parts
+
+/* Register Bits [CANGCON]  */
+/* CAN General Control Register */
+#define    ABRQ       7
+#define    OVRQ       6
+#define    TTC        5
+#define    SYNTTC     4
+#define    LISTEN     3
+#define    TEST       2
+#define    ENASTB     1
+#define    SWRES      0
+/* End Register Bits */
+
+/* Register Bits [CANGSTA]  */
+/* CAN General Status Register */
+#define    OVFG       6
+#define    OVRG       6
+#define    TXBSY      4
+#define    RXBSY      3
+#define    ENFG       2
+#define    BOFF       1
+#define    ERRP       0
+/* End Register Bits */
+
+/* Register Bits [CANGIT]  */
+/* CAN General Interrupt Register */
+#define    CANIT      7
+#define    BOFFIT     6
+#define    OVRTIM     5
+#define    BXOK       4
+#define    SERG       3
+#define    CERG       2
+#define    FERG       1
+#define    AERG       0
+/* End Register Bits */
+
+/* Register Bits [CANGIE]  */
+/* CAN General Interrupt Enable */
+#define    ENIT        7
+#define    ENBOFF      6
+#define    ENRX        5
+#define    ENTX        4
+#define    ENERR       3
+#define    ENBX        2
+#define    ENERG       1
+#define    ENOVRT      0
+/* End Register Bits */
+
+/* Register Bits [CANEN2]  */
+/* CAN Enable MOb Register */
+#define    ENMOB7      7
+#define    ENMOB6      6
+#define    ENMOB5      5
+#define    ENMOB4      4
+#define    ENMOB3      3
+#define    ENMOB2      2
+#define    ENMOB1      1
+#define    ENMOB0      0
+/* End Register Bits */
+
+/* Register Bits [CANEN1]  */
+/* CAN Enable MOb Register */
+#define    ENMOB14      6
+#define    ENMOB13      5
+#define    ENMOB12      4
+#define    ENMOB11      3
+#define    ENMOB10      2
+#define    ENMOB9       1
+#define    ENMOB8       0
+/* End Register Bits */
+
+/* Register Bits [CANIE2]  */
+/* CAN Interrupt Enable MOb Register */
+#define    IEMOB7      7
+#define    IEMOB6      6
+#define    IEMOB5      5
+#define    IEMOB4      4
+#define    IEMOB3      3
+#define    IEMOB2      2
+#define    IEMOB1      1
+#define    IEMOB0      0
+/* End Register Bits */
+
+/* Register Bits [CANIE1]  */
+/* CAN Interrupt Enable MOb Register */
+#define    IEMOB14      6
+#define    IEMOB13      5
+#define    IEMOB12      4
+#define    IEMOB11      3
+#define    IEMOB10      2
+#define    IEMOB9       1
+#define    IEMOB8       0
+/* End Register Bits */
+
+/* Register Bits [CANSIT2]  */
+/* CAN Status Interrupt MOb Register */
+#define    SIT7      7
+#define    SIT6      6
+#define    SIT5      5
+#define    SIT4      4
+#define    SIT3      3
+#define    SIT2      2
+#define    SIT1      1
+#define    SIT0      0
+/* End Register Bits */
+
+/* Register Bits [CANSIT1]  */
+/* CAN Status Interrupt MOb Register */
+#define    SIT14      6
+#define    SIT13      5
+#define    SIT12      4
+#define    SIT11      3
+#define    SIT10      2
+#define    SIT9       1
+#define    SIT8       0
+/* End Register Bits */
+
+/* Register Bits [CANBT1]  */
+/* Bit Timing Register 1 */
+#define    BRP5       6
+#define    BRP4       5
+#define    BRP3       4
+#define    BRP2       3
+#define    BRP1       2
+#define    BRP0       1
+/* End Register Bits */
+
+/* Register Bits [CANBT2]  */
+/* Bit Timing Register 2 */
+#define    SJW1       6
+#define    SJW0       5
+#define    PRS2       3
+#define    PRS1       2
+#define    PRS0       1
+/* End Register Bits */
+
+/* Register Bits [CANBT3]  */
+/* Bit Timing Register 3 */
+#define    PHS22      6
+#define    PHS21      5
+#define    PHS20      4
+#define    PHS12      3
+#define    PHS11      2
+#define    PHS10      1
+#define    SMP        0
+/* End Register Bits */
+
+/* Register Bits [CANTCON]  */
+/* CAN Timer Control Register */
+#define    TPRSC7      7
+#define    TPRSC6      6
+#define    TPRSC5      5
+#define    TPRSC4      4
+#define    TPRSC3      3
+#define    TPRSC2      2
+#define    TPRSC1      1
+#define    TPRSC0      0
+/* End Register Bits */
+
+/* Register Bits [CANTIML]  */
+/* CAN Timer Register Low */
+#define    CANTIM7      7
+#define    CANTIM6      6
+#define    CANTIM5      5
+#define    CANTIM4      4
+#define    CANTIM3      3
+#define    CANTIM2      2
+#define    CANTIM1      1
+#define    CANTIM0      0
+/* End Register Bits */
+
+/* Register Bits [CANTIMH]  */
+/* CAN Timer Register High */
+#define    CANTIM15     7
+#define    CANTIM14     6
+#define    CANTIM13     5
+#define    CANTIM12     4
+#define    CANTIM11     3
+#define    CANTIM10     2
+#define    CANTIM9      1
+#define    CANTIM8      0
+/* End Register Bits */
+
+/* Register Bits [CANTTCL]  */
+/* CAN TTC Timer Register Low */
+#define    TIMTTC7      7
+#define    TIMTTC6      6
+#define    TIMTTC5      5
+#define    TIMTTC4      4
+#define    TIMTTC3      3
+#define    TIMTTC2      2
+#define    TIMTTC1      1
+#define    TIMTTC0      0
+/* End Register Bits */
+
+/* Register Bits [CANTTCH]  */
+/* CAN TTC Timer Register High */
+#define    TIMTTC15     7
+#define    TIMTTC14     6
+#define    TIMTTC13     5
+#define    TIMTTC12     4
+#define    TIMTTC11     3
+#define    TIMTTC10     2
+#define    TIMTTC9      1
+#define    TIMTTC8      0
+/* End Register Bits */
+
+/* Register Bits [CANTEC]  */
+/* CAN Transmitt Error Counter */
+#define    TEC7      7
+#define    TEC6      6
+#define    TEC5      5
+#define    TEC4      4
+#define    TEC3      3
+#define    TEC2      2
+#define    TEC1      1
+#define    TEC0      0
+/* End Register Bits */
+
+/* Register Bits [CANREC]  */
+/* CAN Receive Error Counter */
+#define    REC7      7
+#define    REC6      6
+#define    REC5      5
+#define    REC4      4
+#define    REC3      3
+#define    REC2      2
+#define    REC1      1
+#define    REC0      0
+/* End Register Bits */
+
+/* Register Bits [CANHPMOB]  */
+/* Highest Priority MOb */
+#define    HPMOB3     7
+#define    HPMOB2     6
+#define    HPMOB1     5
+#define    HPMOB0     4
+#define    CGP3       3
+#define    CGP2       2
+#define    CGP1       1
+#define    CGP0       0
+/* End Register Bits */
+
+/* Register Bits [CANPAGE]  */
+/* CAN Page MOb Register */
+#define    MOBNB3     7
+#define    MOBNB2     6
+#define    MOBNB1     5
+#define    MOBNB0     4
+#define    AINC       3
+#define    INDX2      2
+#define    INDX1      1
+#define    INDX0      0
+/* End Register Bits */
+
+/* Register Bits [CANSTMOB]  */
+/* CAN MOb Status Register */
+#define    DLCW       7
+#define    TXOK       6
+#define    RXOK       5
+#define    BERR       4
+#define    SERR       3
+#define    CERR       2
+#define    FERR       1
+#define    AERR       0
+/* End Register Bits */
+
+/* Register Bits [CANCDMOB]  */
+/* CAN MOb Control and DLC Register */
+#define    CONMOB1    7
+#define    CONMOB0    6
+#define    RPLV       5
+#define    IDE        4
+#define    DLC3       3
+#define    DLC2       2
+#define    DLC1       1
+#define    DLC0       0
+/* End Register Bits */
+
+/* Register Bits [CANIDT4]  */
+/* CAN Identifier Tag Register 4 */
+#define    IDT4       7
+#define    IDT3       6
+#define    IDT2       5
+#define    IDT1       4
+#define    IDT0       3
+#define    RTRTAG     2
+#define    RB1TAG     1
+#define    RB0TAG     0
+/* End Register Bits */
+
+/* Register Bits [CANIDT3]  */
+/* CAN Identifier Tag Register 3 */
+#define    IDT12      7
+#define    IDT11      6
+#define    IDT10      5
+#define    IDT9       4
+#define    IDT8       3
+#define    IDT7       2
+#define    IDT6       1
+#define    IDT5       0
+/* End Register Bits */
+
+/* Register Bits [CANIDT2]  */
+/* CAN Identifier Tag Register 2 */
+#define    IDT20      7
+#define    IDT19      6
+#define    IDT18      5
+#define    IDT17      4
+#define    IDT16      3
+#define    IDT15      2
+#define    IDT14      1
+#define    IDT13      0
+/* End Register Bits */
+
+/* Register Bits [CANIDT1]  */
+/* CAN Identifier Tag Register 1 */
+#define    IDT28      7
+#define    IDT27      6
+#define    IDT26      5
+#define    IDT25      4
+#define    IDT24      3
+#define    IDT23      2
+#define    IDT22      1
+#define    IDT21      0
+/* End Register Bits */
+
+/* Register Bits [CANIDM4]  */
+/* CAN Identifier Mask Register 4 */
+#define    IDMSK4       7
+#define    IDMSK3       6
+#define    IDMSK2       5
+#define    IDMSK1       4
+#define    IDMSK0       3
+#define    RTRMSK       2
+#define    IDEMSK       0
+/* End Register Bits */
+
+/* Register Bits [CANIDM3]  */
+/* CAN Identifier Mask Register 3 */
+#define    IDMSK12      7
+#define    IDMSK11      6
+#define    IDMSK10      5
+#define    IDMSK9       4
+#define    IDMSK8       3
+#define    IDMSK7       2
+#define    IDMSK6       1
+#define    IDMSK5       0
+/* End Register Bits */
+
+/* Register Bits [CANIDM2]  */
+/* CAN Identifier Mask Register 2 */
+#define    IDMSK20      7
+#define    IDMSK19      6
+#define    IDMSK18      5
+#define    IDMSK17      4
+#define    IDMSK16      3
+#define    IDMSK15      2
+#define    IDMSK14      1
+#define    IDMSK13      0
+/* End Register Bits */
+
+/* Register Bits [CANIDM1]  */
+/* CAN Identifier Mask Register 1 */
+#define    IDMSK28      7
+#define    IDMSK27      6
+#define    IDMSK26      5
+#define    IDMSK25      4
+#define    IDMSK24      3
+#define    IDMSK23      2
+#define    IDMSK22      1
+#define    IDMSK21      0
+/* End Register Bits */
+
+/* Register Bits [CANSTML]  */
+/* CAN Timer Register of some sort, low*/
+#define    TIMSTM7       7
+#define    TIMSTM6       6
+#define    TIMSTM5       5
+#define    TIMSTM4       4
+#define    TIMSTM3       3
+#define    TIMSTM2       2
+#define    TIMSTM1       1
+#define    TIMSTM0       0
+/* End Register Bits */
+
+/* Register Bits [CANSTMH]  */
+/* CAN Timer Register of some sort, high */
+#define    TIMSTM15       7
+#define    TIMSTM14       6
+#define    TIMSTM13       5
+#define    TIMSTM12       4
+#define    TIMSTM11       3
+#define    TIMSTM10       2
+#define    TIMSTM9        1
+#define    TIMSTM8        0
+/* End Register Bits */
+
+/* Register Bits [CANMSG]  */
+/* CAN Message Register */
+#define    MSG7           7
+#define    MSG6           6
+#define    MSG5           5
+#define    MSG4           4
+#define    MSG3           3
+#define    MSG2           2
+#define    MSG1           1
+#define    MSG0           0
+/* End Register Bits */
+
+/* Begin Verbatim */
+
+/* Timer/Counter Control Register (generic) */
+#define    FOC          7
+#define    WGM0         6
+#define    COM1         5
+#define    COM0         4
+#define    WGM1         3
+#define    CS2          2
+#define    CS1          1
+#define    CS0          0
+
+/* Timer/Counter Control Register A (generic) */
+#define    COMA1        7
+#define    COMA0        6
+#define    COMB1        5
+#define    COMB0        4
+#define    COMC1        3
+#define    COMC0        2
+#define    WGMA1        1
+#define    WGMA0        0
+
+/* Timer/Counter Control and Status Register B (generic) */
+#define    ICNC         7
+#define    ICES         6
+#define    WGMB3        4
+#define    WGMB2        3
+#define    CSB2         2
+#define    CSB1         1
+#define    CSB0         0
+
+/* Timer/Counter Control Register C (generic) */
+#define    FOCA         7
+#define    FOCB         6
+#define    FOCC         5
+
+/* Port Data Register (generic) */
+#define    PORT7        7
+#define    PORT6        6
+#define    PORT5        5
+#define    PORT4        4
+#define    PORT3        3
+#define    PORT2        2
+#define    PORT1        1
+#define    PORT0        0
+
+/* Port Data Direction Register (generic) */
+#define    DD7          7
+#define    DD6          6
+#define    DD5          5
+#define    DD4          4
+#define    DD3          3
+#define    DD2          2
+#define    DD1          1
+#define    DD0          0
+
+/* Port Input Pins (generic) */
+#define    PIN7         7
+#define    PIN6         6
+#define    PIN5         5
+#define    PIN4         4
+#define    PIN3         3
+#define    PIN2         2
+#define    PIN1         1
+#define    PIN0         0
+
+/* USART Status Register A (generic) */
+#define    RXC          7
+#define    TXC          6
+#define    UDRE         5
+#define    FE           4
+#define    DOR          3
+#define    UPE          2
+#define    U2X          1
+#define    MPCM         0
+
+/* USART Control Register B (generic) */
+#define    RXCIE        7
+#define    TXCIE        6
+#define    UDRIE        5
+#define    RXEN         4
+#define    TXEN         3
+#define    UCSZ         2
+#define    UCSZ2        2       /* new name in datasheet (2467E-AVR-05/02) */
+#define    RXB8         1
+#define    TXB8         0
+
+/* USART Register C (generic) */
+#define    UMSEL        6
+#define    UPM1         5
+#define    UPM0         4
+#define    USBS         3
+#define    UCSZ1        2
+#define    UCSZ0        1
+#define    UCPOL        0
+
+/* End Verbatim */
 
 /* Constants */
 #define SPM_PAGESIZE 256
@@ -91,12 +2052,10 @@
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x81
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif  /* _AVR_IOCAN128_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iocan32.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iocan32.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
+/* Copyright (c) 2004,2005,2006 Colin O'Flynn <coflynn@newae.com>, 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,14 +28,1975 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iocan32.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* iocan32.h - definitions for CAN32 */
 
 #ifndef _AVR_IOCAN32_H_
 #define _AVR_IOCAN32_H_ 1
 
-#include <avr/iocanxx.h>
+
+/* I/O registers and bit definitions. */
+
+/* RegDef:  Port A */
+#define PINA   _SFR_IO8(0x00)
+#define DDRA   _SFR_IO8(0x01)
+#define PORTA  _SFR_IO8(0x02)
+
+/* RegDef:  Port B */
+#define PINB   _SFR_IO8(0x03)
+#define DDRB   _SFR_IO8(0x04)
+#define PORTB  _SFR_IO8(0x05)
+
+/* RegDef:  Port C */
+#define PINC   _SFR_IO8(0x06)
+#define DDRC   _SFR_IO8(0x07)
+#define PORTC  _SFR_IO8(0x08)
+
+/* RegDef:  Port D */
+#define PIND   _SFR_IO8(0x09)
+#define DDRD   _SFR_IO8(0x0A)
+#define PORTD  _SFR_IO8(0x0B)
+
+/* RegDef:  Port E */
+#define PINE   _SFR_IO8(0x0C)
+#define DDRE   _SFR_IO8(0x0D)
+#define PORTE  _SFR_IO8(0x0E)
+
+/* RegDef:  Port F */
+#define PINF   _SFR_IO8(0x0F)
+#define DDRF   _SFR_IO8(0x10)
+#define PORTF  _SFR_IO8(0x11)
+
+/* RegDef:  Port G */
+#define PING   _SFR_IO8(0x12)
+#define DDRG   _SFR_IO8(0x13)
+#define PORTG  _SFR_IO8(0x14)
+
+/* RegDef:  Timer/Counter 0 interrupt Flag Register */
+#define TIFR0  _SFR_IO8(0x15)
+
+/* RegDef:  Timer/Counter 1 interrupt Flag Register */
+#define TIFR1  _SFR_IO8(0x16)
+
+/* RegDef:  Timer/Counter 2 interrupt Flag Register */
+#define TIFR2  _SFR_IO8(0x17)
+
+/* RegDef:  Timer/Counter 3 interrupt Flag Register */
+#define TIFR3  _SFR_IO8(0x18)
+
+/* RegDef:  External Interrupt Flag Register */
+#define EIFR   _SFR_IO8(0x1C)
+
+/* RegDef:  External Interrupt Mask Register */
+#define EIMSK  _SFR_IO8(0x1D)
+
+/* RegDef:  General Purpose I/O Register 0 */
+#define GPIOR0 _SFR_IO8(0x1E)
+
+/* RegDef:  EEPROM Control Register */
+#define EECR   _SFR_IO8(0x1F)
+
+/* RegDef:  EEPROM Data Register */
+#define EEDR   _SFR_IO8(0x20)
+
+/* RegDef:  EEPROM Address Register */
+#define EEAR   _SFR_IO16(0x21)
+#define EEARL  _SFR_IO8(0x21)
+#define EEARH  _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+/* RegDef:  General Timer/Counter Control Register */
+#define GTCCR  _SFR_IO8(0x23)
+
+/* RegDef:  Timer/Counter Control Register A */
+#define TCCR0A _SFR_IO8(0x24)
+
+/* RegDef:  Timer/Counter Register */
+#define TCNT0  _SFR_IO8(0x26)
+
+/* RegDef:  Output Compare Register A */
+#define OCR0A  _SFR_IO8(0x27)
+
+/* RegDef:  General Purpose I/O Register 1 */
+#define GPIOR1 _SFR_IO8(0x2A)
+
+/* RegDef:  General Purpose I/O Register 2 */
+#define GPIOR2 _SFR_IO8(0x2B)
+
+/* RegDef:  SPI Control Register */
+#define SPCR   _SFR_IO8(0x2C)
+
+/* RegDef:  SPI Status Register */
+#define SPSR   _SFR_IO8(0x2D)
+
+/* RegDef:  SPI Data Register */
+#define SPDR   _SFR_IO8(0x2E)
+
+/* RegDef:  Analog Comperator Control and Status Register */
+#define ACSR   _SFR_IO8(0x30)
+
+/* RegDef:  On-chip Debug Register */
+#define OCDR   _SFR_IO8(0x31)
+
+/* RegDef:  Sleep Mode Control Register */
+#define SMCR   _SFR_IO8(0x33)
+
+/* RegDef:  MCU Status Register */
+#define MCUSR  _SFR_IO8(0x34)
+
+/* RegDef:  MCU Control Rgeister */
+#define MCUCR  _SFR_IO8(0x35)
+
+/* RegDef:  Store Program Memory Control and Status Register */
+#define SPMCSR _SFR_IO8(0x37)
+
+/* RegDef:  RAMPZ register. */
+#define RAMPZ  _SFR_IO8(0x3B)
+
+/* RegDef:  Watchdog Timer Control Register */
+#define WDTCR  _SFR_MEM8(0x60)
+
+/* RegDef:  Clock Prescale Register */
+#define CLKPR  _SFR_MEM8(0x61)
+
+/* RegDef:  Oscillator Calibration Register */
+#define OSCCAL _SFR_MEM8(0x66)
+
+/* RegDef:  External Interrupt Control Register A */
+#define EICRA  _SFR_MEM8(0x69)
+
+/* RegDef:  External Interrupt Control Register B */
+#define EICRB  _SFR_MEM8(0x6A)
+
+/* RegDef:  Timer/Counter 0 Interrupt Mask Register */
+#define TIMSK0 _SFR_MEM8(0x6E)
+
+/* RegDef:  Timer/Counter 1 Interrupt Mask Register */
+#define TIMSK1 _SFR_MEM8(0x6F)
+
+/* RegDef:  Timer/Counter 2 Interrupt Mask Register */
+#define TIMSK2 _SFR_MEM8(0x70)
+
+/* RegDef:  Timer/Counter 3 Interrupt Mask Register */
+#define TIMSK3 _SFR_MEM8(0x71)
+
+/* RegDef:  External Memory Control Register A */
+#define XMCRA _SFR_MEM8(0x74)
+
+/* RegDef:  External Memory Control Register A */
+#define XMCRB _SFR_MEM8(0x75)
+
+/* RegDef:  ADC Data Register */
+#ifndef __ASSEMBLER__
+#define ADC    _SFR_MEM16(0x78)
+#endif
+#define ADCW   _SFR_MEM16(0x78)
+#define ADCL   _SFR_MEM8(0x78)
+#define ADCH   _SFR_MEM8(0x79)
+
+/* RegDef:  ADC Control and Status Register A */
+#define ADCSRA _SFR_MEM8(0x7A)
+
+/* RegDef:  ADC Control and Status Register B */
+#define ADCSRB _SFR_MEM8(0x7B)
+
+/* RegDef:  ADC Multiplex Selection Register */
+#define ADMUX  _SFR_MEM8(0x7C)
+
+/* RegDef:  Digital Input Disable Register 0 */
+#define DIDR0  _SFR_MEM8(0x7E)
+
+/* RegDef:  Digital Input Disable Register 1 */
+#define DIDR1  _SFR_MEM8(0x7F)
+
+/* RegDef:  Timer/Counter1 Control Register A */
+#define TCCR1A _SFR_MEM8(0x80)
+
+/* RegDef:  Timer/Counter1 Control Register B */
+#define TCCR1B _SFR_MEM8(0x81)
+
+/* RegDef:  Timer/Counter1 Control Register C */
+#define TCCR1C _SFR_MEM8(0x82)
+
+/* RegDef:  Timer/Counter1 Register */
+#define TCNT1  _SFR_MEM16(0x84)
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1H _SFR_MEM8(0x85)
+
+/* RegDef:  Timer/Counter1 Input Capture Register */
+#define ICR1   _SFR_MEM16(0x86)
+#define ICR1L  _SFR_MEM8(0x86)
+#define ICR1H  _SFR_MEM8(0x87)
+
+/* RegDef:  Timer/Counter1 Output Compare Register A */
+#define OCR1A  _SFR_MEM16(0x88)
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AH _SFR_MEM8(0x89)
+
+/* RegDef:  Timer/Counter1 Output Compare Register B */
+#define OCR1B  _SFR_MEM16(0x8A)
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BH _SFR_MEM8(0x8B)
+
+/* RegDef:  Timer/Counter1 Output Compare Register C */
+#define OCR1C  _SFR_MEM16(0x8C)
+#define OCR1CL _SFR_MEM8(0x8C)
+#define OCR1CH _SFR_MEM8(0x8D)
+
+/* RegDef:  Timer/Counter3 Control Register A */
+#define TCCR3A _SFR_MEM8(0x90)
+
+/* RegDef:  Timer/Counter3 Control Register B */
+#define TCCR3B _SFR_MEM8(0x91)
+
+/* RegDef:  Timer/Counter3 Control Register C */
+#define TCCR3C _SFR_MEM8(0x92)
+
+/* RegDef:  Timer/Counter3 Register */
+#define TCNT3  _SFR_MEM16(0x94)
+#define TCNT3L _SFR_MEM8(0x94)
+#define TCNT3H _SFR_MEM8(0x95)
+
+/* RegDef:  Timer/Counter3 Input Capture Register */
+#define ICR3   _SFR_MEM16(0x96)
+#define ICR3L  _SFR_MEM8(0x96)
+#define ICR3H  _SFR_MEM8(0x97)
+
+/* RegDef:  Timer/Counter3 Output Compare Register A */
+#define OCR3A  _SFR_MEM16(0x98)
+#define OCR3AL _SFR_MEM8(0x98)
+#define OCR3AH _SFR_MEM8(0x99)
+
+/* RegDef:  Timer/Counter3 Output Compare Register B */
+#define OCR3B  _SFR_MEM16(0x9A)
+#define OCR3BL _SFR_MEM8(0x9A)
+#define OCR3BH _SFR_MEM8(0x9B)
+
+/* RegDef:  Timer/Counter3 Output Compare Register C */
+#define OCR3C  _SFR_MEM16(0x9C)
+#define OCR3CL _SFR_MEM8(0x9C)
+#define OCR3CH _SFR_MEM8(0x9D)
+
+/* RegDef:  Timer/Counter2 Control Register A */
+#define TCCR2A _SFR_MEM8(0xB0)
+
+/* RegDef:  Timer/Counter2 Register */
+#define TCNT2  _SFR_MEM8(0xB2)
+
+/* RegDef:  Timer/Counter2 Output Compare Register */
+#define OCR2A  _SFR_MEM8(0xB3)
+
+/* RegDef:  Asynchronous Status Register */
+#define ASSR   _SFR_MEM8(0xB6)
+
+/* RegDef:  TWI Bit Rate Register */
+#define TWBR   _SFR_MEM8(0xB8)
+
+/* RegDef:  TWI Status Register */
+#define TWSR   _SFR_MEM8(0xB9)
+
+/* RegDef:  TWI (Slave) Address Register */
+#define TWAR   _SFR_MEM8(0xBA)
+
+/* RegDef:  TWI Data Register */
+#define TWDR   _SFR_MEM8(0xBB)
+
+/* RegDef:  TWI Control Register */
+#define TWCR   _SFR_MEM8(0xBC)
+
+/* RegDef:  USART0 Control and Status Register A */
+#define UCSR0A _SFR_MEM8(0xC0)
+
+/* RegDef:  USART0 Control and Status Register B */
+#define UCSR0B _SFR_MEM8(0xC1)
+
+/* RegDef:  USART0 Control and Status Register C */
+#define UCSR0C _SFR_MEM8(0xC2)
+
+/* RegDef:  USART0 Baud Rate Register */
+#define UBRR0  _SFR_MEM16(0xC4)
+#define UBRR0L _SFR_MEM8(0xC4)
+#define UBRR0H _SFR_MEM8(0xC5)
+
+/* RegDef:  USART0 I/O Data Register */
+#define UDR0   _SFR_MEM8(0xC6)
+
+/* RegDef:  USART1 Control and Status Register A */
+#define UCSR1A _SFR_MEM8(0xC8)
+
+/* RegDef:  USART1 Control and Status Register B */
+#define UCSR1B _SFR_MEM8(0xC9)
+
+/* RegDef:  USART1 Control and Status Register C */
+#define UCSR1C _SFR_MEM8(0xCA)
+
+/* RegDef:  USART1 Baud Rate Register */
+#define UBRR1  _SFR_MEM16(0xCC)
+#define UBRR1L _SFR_MEM8(0xCC)
+#define UBRR1H _SFR_MEM8(0xCD)
+
+/* RegDef:  USART1 I/O Data Register */
+#define UDR1   _SFR_MEM8(0xCE)
+
+/* RegDef:  CAN General Control Register*/
+#define CANGCON _SFR_MEM8(0xD8)
+
+/* RegDef:  CAN General Status Register*/
+#define CANGSTA _SFR_MEM8(0xD9)
+
+/* RegDef:  CAN General Interrupt Register*/
+#define CANGIT _SFR_MEM8(0xDA)
+
+/* RegDef:  CAN General Interrupt Enable Register*/
+#define CANGIE _SFR_MEM8(0xDB)
+
+/* Word Definition:  CAN Enable MOb Register*/
+#define CANEN _SFR_MEM16(0xDC) 
+
+/* RegDef:  CAN Enable MOb Register*/
+#define CANEN2 _SFR_MEM8(0xDC)
+
+/* RegDef:  CAN Enable MOb Register*/
+#define CANEN1 _SFR_MEM8(0xDD)
+
+/* Word Definition:  CAN Enable Interrupt MOb Register*/
+#define CANIE _SFR_MEM16(0xDE) 
+
+/* RegDef:  CAN Enable Interrupt MOb Register*/
+#define CANIE2 _SFR_MEM8(0xDE)
+
+/* RegDef:  CAN Enable Interrupt MOb Register*/
+#define CANIE1 _SFR_MEM8(0xDF)
+
+/* RegDef:  CAN Status Interrupt MOb Register*/
+/*
+ * WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT
+ * register.
+ */
+#define CANSIT  _SFR_MEM16(0xE0)
+#define CANSIT2 _SFR_MEM8(0xE0)
+#define CANSIT1 _SFR_MEM8(0xE1)
+
+/* RegDef:  CAN Bit Timing Register 1*/
+#define CANBT1 _SFR_MEM8(0xE2)
+
+/* RegDef:  CAN Bit Timing Register 2*/
+#define CANBT2 _SFR_MEM8(0xE3)
+
+/* RegDef:  CAN Bit Timing Register 3*/
+#define CANBT3 _SFR_MEM8(0xE4)
+
+/* RegDef:  CAN Timer Control Register*/
+#define CANTCON _SFR_MEM8(0xE5)
+
+/* RegDef:  CAN Timer Register*/
+#define CANTIM _SFR_MEM16(0xE6)
+#define CANTIML _SFR_MEM8(0xE6)
+#define CANTIMH _SFR_MEM8(0xE7)
+
+/* RegDef:  CAN TTC Timer Register*/
+#define CANTTC _SFR_MEM16(0xE8)
+#define CANTTCL _SFR_MEM8(0xE8)
+#define CANTTCH _SFR_MEM8(0xE9)
+
+/* RegDef:  CAN Transmitt Error Counter Register*/
+#define CANTEC _SFR_MEM8(0xEA)
+
+/* RegDef:  CAN Receive Error Counter Register*/
+#define CANREC _SFR_MEM8(0xEB)
+
+/* RegDef:  CAN Highest Priority MOb Register*/
+#define CANHPMOB _SFR_MEM8(0xEC)
+
+/* RegDef:  CAN Page MOb Register*/
+#define CANPAGE _SFR_MEM8(0xED)
+
+/* RegDef:  CAN MOb Status Register*/
+#define CANSTMOB _SFR_MEM8(0xEE)
+
+/* RegDef:  CAN MOb Control and DLC Register*/
+#define CANCDMOB _SFR_MEM8(0xEF)
+
+/* RegDef:  CAN Identifier Tag Registers*/
+#define CANIDT  _SFR_MEM32(0xF0)
+
+#define CANIDT4 _SFR_MEM8(0xF0)
+#define CANIDT3 _SFR_MEM8(0xF1)
+#define CANIDT2 _SFR_MEM8(0xF2)
+#define CANIDT1 _SFR_MEM8(0xF3)
+
+/* RegDef:  CAN Identifier Mask Registers */
+#define CANIDM  _SFR_MEM32(0xF4)
+
+#define CANIDM4 _SFR_MEM8(0xF4)
+#define CANIDM3 _SFR_MEM8(0xF5)
+#define CANIDM2 _SFR_MEM8(0xF6)
+#define CANIDM1 _SFR_MEM8(0xF7)
+
+/* RegDef:  CAN TTC Timer Register*/
+#define CANSTM _SFR_MEM16(0xF8)
+#define CANSTML _SFR_MEM8(0xF8)
+#define CANSTMH _SFR_MEM8(0xF9)
+
+/* RegDef:  CAN Message Register*/
+#define CANMSG _SFR_MEM8(0xFA)
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+#define SIG_INTERRUPT3			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+#define SIG_INTERRUPT4			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+#define SIG_INTERRUPT5			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num		7
+#define INT6_vect			_VECTOR(7)
+#define SIG_INTERRUPT6			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+#define SIG_INTERRUPT7			_VECTOR(8)
+
+/* Timer/Counter2 Compare Match */
+#define TIMER2_COMP_vect_num	9
+#define TIMER2_COMP_vect		_VECTOR(9)
+#define SIG_OUTPUT_COMPARE2		_VECTOR(9)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		10
+#define TIMER2_OVF_vect			_VECTOR(10)
+#define SIG_OVERFLOW2			_VECTOR(10)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	11
+#define TIMER1_CAPT_vect		_VECTOR(11)
+#define SIG_INPUT_CAPTURE1		_VECTOR(11)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	12
+#define TIMER1_COMPA_vect		_VECTOR(12)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
+
+/* Timer/Counter Compare Match B */
+#define TIMER1_COMPB_vect_num	13
+#define TIMER1_COMPB_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	14
+#define TIMER1_COMPC_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE1C		_VECTOR(14)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		15
+#define TIMER1_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW1			_VECTOR(15)
+
+/* Timer/Counter0 Compare Match */
+#define TIMER0_COMP_vect_num	16
+#define TIMER0_COMP_vect		_VECTOR(16)
+#define SIG_OUTPUT_COMPARE0		_VECTOR(16)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		17
+#define TIMER0_OVF_vect			_VECTOR(17)
+#define SIG_OVERFLOW0			_VECTOR(17)
+
+/* CAN Transfer Complete or Error */
+#define CANIT_vect_num		18
+#define CANIT_vect			_VECTOR(18)
+#define SIG_CAN_INTERRUPT1		_VECTOR(18)
+
+/* CAN Timer Overrun */
+#define OVRIT_vect_num		19
+#define OVRIT_vect			_VECTOR(19)
+#define SIG_CAN_OVERFLOW1		_VECTOR(19)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		20
+#define SPI_STC_vect			_VECTOR(20)
+#define SIG_SPI				_VECTOR(20)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		21
+#define USART0_RX_vect			_VECTOR(21)
+#define SIG_UART0_RECV			_VECTOR(21)
+#define SIG_USART0_RECV			_VECTOR(21)
+
+/* USART0 Data Register Empty */
+#define USART0_UDRE_vect_num	22
+#define USART0_UDRE_vect		_VECTOR(22)
+#define SIG_UART0_DATA			_VECTOR(22)
+#define SIG_USART0_DATA			_VECTOR(22)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		23
+#define USART0_TX_vect			_VECTOR(23)
+#define SIG_UART0_TRANS			_VECTOR(23)
+#define SIG_USART0_TRANS		_VECTOR(23)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	24
+#define ANALOG_COMP_vect		_VECTOR(24)
+#define SIG_COMPARATOR			_VECTOR(24)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		25
+#define ADC_vect			_VECTOR(25)
+#define SIG_ADC				_VECTOR(25)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		26
+#define EE_READY_vect			_VECTOR(26)
+#define SIG_EEPROM_READY		_VECTOR(26)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	27
+#define TIMER3_CAPT_vect		_VECTOR(27)
+#define SIG_INPUT_CAPTURE3		_VECTOR(27)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	28
+#define TIMER3_COMPA_vect		_VECTOR(28)
+#define SIG_OUTPUT_COMPARE3A		_VECTOR(28)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	29
+#define TIMER3_COMPB_vect		_VECTOR(29)
+#define SIG_OUTPUT_COMPARE3B		_VECTOR(29)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	30
+#define TIMER3_COMPC_vect		_VECTOR(30)
+#define SIG_OUTPUT_COMPARE3C		_VECTOR(30)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		31
+#define TIMER3_OVF_vect			_VECTOR(31)
+#define SIG_OVERFLOW3			_VECTOR(31)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		32
+#define USART1_RX_vect			_VECTOR(32)
+#define SIG_UART1_RECV			_VECTOR(32)
+#define SIG_USART1_RECV			_VECTOR(32)
+
+/* USART1, Data Register Empty */
+#define USART1_UDRE_vect_num	33
+#define USART1_UDRE_vect		_VECTOR(33)
+#define SIG_UART1_DATA			_VECTOR(33)
+#define SIG_USART1_DATA			_VECTOR(33)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		34
+#define USART1_TX_vect			_VECTOR(34)
+#define SIG_UART1_TRANS			_VECTOR(34)
+#define SIG_USART1_TRANS		_VECTOR(34)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num		35
+#define TWI_vect			_VECTOR(35)
+#define SIG_2WIRE_SERIAL		_VECTOR(35)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		36
+#define SPM_READY_vect			_VECTOR(36)
+#define SIG_SPM_READY			_VECTOR(36)
+
+#define _VECTORS_SIZE 148
+
+/* The Register Bit names are represented by their bit number (0-7). */
+
+/* Register Bits [ASSR]  */
+/* Asynchronous Status Register */
+#define    EXCLK      4
+#define    AS2        3
+#define    TCN2UB     2
+#define    OCR2UB     1
+#define    TCR2UB     0
+/* End Register Bits */
+
+/* Register Bits [TWCR] */
+/* 2-wire Control Register - TWCR */
+#define    TWINT        7
+#define    TWEA         6
+#define    TWSTA        5
+#define    TWSTO        4
+#define    TWWC         3
+#define    TWEN         2
+#define    TWIE         0
+/* End Register Bits */
+
+/* Register Bits [TWAR]  */
+/* 2-wire Address Register - TWAR */
+#define    TWA6         7
+#define    TWA5         6
+#define    TWA4         5
+#define    TWA3         4
+#define    TWA2         3
+#define    TWA1         2
+#define    TWA0         1
+#define    TWGCE        0
+/* End Register Bits */
+
+/* Register Bits [TWSR]  */
+/* 2-wire Status Register - TWSR */
+#define    TWS7         7
+#define    TWS6         6
+#define    TWS5         5
+#define    TWS4         4
+#define    TWS3         3
+#define    TWPS1        1
+#define    TWPS0        0
+/* End Register Bits */
+
+/* Register Bits [XMCRB]  */
+/* External Memory Control Register B - XMCRB */
+#define    XMBK         7
+#define    XMM2         2
+#define    XMM1         1
+#define    XMM0         0
+/* End Register Bits */
+
+/* Register Bits [XMCRA]  */
+/* External Memory Control Register A - XMCRA */
+#define    SRE         7
+#define    SRL2        6
+#define    SRL1        5
+#define    SRL0        4
+#define    SRW11       3
+#define    SRW10       2
+#define    SRW01       1
+#define    SRW00       0
+/* End Register Bits */
+
+/* Register Bits [RAMPZ]  */
+/* RAM Page Z select register - RAMPZ */
+#define     RAMPZ0      0
+/* End Register Bits */
+
+/* Register Bits [EICRA]  */
+/* External Interrupt Control Register A - EICRA */
+#define    ISC31        7
+#define    ISC30        6
+#define    ISC21        5
+#define    ISC20        4
+#define    ISC11        3
+#define    ISC10        2
+#define    ISC01        1
+#define    ISC00        0
+/* End Register Bits */
+
+/* Register Bits [EICRB]  */
+/* External Interrupt Control Register B - EICRB */
+#define    ISC71        7
+#define    ISC70        6
+#define    ISC61        5
+#define    ISC60        4
+#define    ISC51        3
+#define    ISC50        2
+#define    ISC41        1
+#define    ISC40        0
+/* End Register Bits */
+
+/* Register Bits [SPMCSR]  */
+/* Store Program Memory Control Register - SPMCSR, SPMCR */
+#define    SPMIE        7
+#define    RWWSB        6
+#define    RWWSRE       4
+#define    BLBSET       3
+#define    PGWRT        2
+#define    PGERS        1
+#define    SPMEN        0
+/* End Register Bits */
+
+/* Register Bits [EIMSK]  */
+/* External Interrupt MaSK register - EIMSK */
+#define    INT7         7
+#define    INT6         6
+#define    INT5         5
+#define    INT4         4
+#define    INT3         3
+#define    INT2         2
+#define    INT1         1
+#define    INT0         0
+/* End Register Bits */
+
+/* Register Bits [EIFR]  */
+/* External Interrupt Flag Register - EIFR */
+#define    INTF7        7
+#define    INTF6        6
+#define    INTF5        5
+#define    INTF4        4
+#define    INTF3        3
+#define    INTF2        2
+#define    INTF1        1
+#define    INTF0        0
+/* End Register Bits */
+
+/* Register Bits [TCCR2]  */
+/* Timer/Counter 2 Control Register - TCCR2 */
+#define    FOC2A        7
+#define    WGM20        6
+#define    COM2A1       5
+#define    COM2A0       4
+#define    WGM21        3
+#define    CS22         2
+#define    CS21         1
+#define    CS20         0
+/* End Register Bits */
+
+/* Register Bits [TCCR1A]  */
+/* Timer/Counter 1 Control and Status Register A - TCCR1A */
+#define    COM1A1       7
+#define    COM1A0       6
+#define    COM1B1       5
+#define    COM1B0       4
+#define    COM1C1       3
+#define    COM1C0       2
+#define    WGM11        1
+#define    WGM10        0
+/* End Register Bits */
+
+/* Register Bits [TCCR3A]  */
+/* Timer/Counter 3 Control and Status Register A - TCCR3A */
+#define    COM3A1       7
+#define    COM3A0       6
+#define    COM3B1       5
+#define    COM3B0       4
+#define    COM3C1       3
+#define    COM3C0       2
+#define    WGM31        1
+#define    WGM30        0
+/* End Register Bits */
+
+/* Register Bits [TCCR1B]  */
+/* Timer/Counter 1 Control and Status Register B - TCCR1B */
+#define    ICNC1        7
+#define    ICES1        6
+#define    WGM13        4
+#define    WGM12        3
+#define    CS12         2
+#define    CS11         1
+#define    CS10         0
+/* End Register Bits */
+
+/* Register Bits [TCCR3B]  */
+/* Timer/Counter 3 Control and Status Register B - TCCR3B */
+#define    ICNC3        7
+#define    ICES3        6
+#define    WGM33        4
+#define    WGM32        3
+#define    CS32         2
+#define    CS31         1
+#define    CS30         0
+/* End Register Bits */
+
+/* Register Bits [TCCR3C]  */
+/* Timer/Counter 3 Control Register C - TCCR3C */
+#define    FOC3A        7
+#define    FOC3B        6
+#define    FOC3C        5
+/* End Register Bits */
+
+/* Register Bits [TCCR1C]  */
+/* Timer/Counter 1 Control Register C - TCCR1C */
+#define    FOC1A        7
+#define    FOC1B        6
+#define    FOC1C        5
+/* End Register Bits */
+
+/* Register Bits [OCDR]  */
+/* On-chip Debug Register - OCDR */
+#define    IDRD         7
+#define    OCDR7        7
+#define    OCDR6        6
+#define    OCDR5        5
+#define    OCDR4        4
+#define    OCDR3        3
+#define    OCDR2        2
+#define    OCDR1        1
+#define    OCDR0        0
+/* End Register Bits */
+
+/* Register Bits [WDTCR]  */
+/* Watchdog Timer Control Register - WDTCR */
+#define    WDCE         4
+#define    WDE          3
+#define    WDP2         2
+#define    WDP1         1
+#define    WDP0         0
+/* End Register Bits */
+
+/* Register Bits [SPSR]  */
+/* SPI Status Register - SPSR */
+#define    SPIF         7
+#define    WCOL         6
+#define    SPI2X        0
+/* End Register Bits */
+
+/* Register Bits [SPCR]  */
+/* SPI Control Register - SPCR */
+#define    SPIE         7
+#define    SPE          6
+#define    DORD         5
+#define    MSTR         4
+#define    CPOL         3
+#define    CPHA         2
+#define    SPR1         1
+#define    SPR0         0
+/* End Register Bits */
+
+/* Register Bits [UCSR1C]  */
+/* USART1 Register C - UCSR1C */
+#define    UMSEL1       6
+#define    UPM11        5
+#define    UPM10        4
+#define    USBS1        3
+#define    UCSZ11       2
+#define    UCSZ10       1
+#define    UCPOL1       0
+/* End Register Bits */
+
+/* Register Bits [UCSR0C]  */
+/* USART0 Register C - UCSR0C */
+#define    UMSEL0       6
+#define    UPM01        5
+#define    UPM00        4
+#define    USBS0        3
+#define    UCSZ01       2
+#define    UCSZ00       1
+#define    UCPOL0       0
+/* End Register Bits */
+
+/* Register Bits [UCSR1A]  */
+/* USART1 Status Register A - UCSR1A */
+#define    RXC1         7
+#define    TXC1         6
+#define    UDRE1        5
+#define    FE1          4
+#define    DOR1         3
+#define    UPE1         2
+#define    U2X1         1
+#define    MPCM1        0
+/* End Register Bits */
+
+/* Register Bits [UCSR0A]  */
+/* USART0 Status Register A - UCSR0A */
+#define    RXC0         7
+#define    TXC0         6
+#define    UDRE0        5
+#define    FE0          4
+#define    DOR0         3
+#define    UPE0         2
+#define    U2X0         1
+#define    MPCM0        0
+/* End Register Bits */
+
+/* Register Bits [UCSR1B]  */
+/* USART1 Control Register B - UCSR1B */
+#define    RXCIE1       7
+#define    TXCIE1       6
+#define    UDRIE1       5
+#define    RXEN1        4
+#define    TXEN1        3
+#define    UCSZ12       2
+#define    RXB81        1
+#define    TXB81        0
+/* End Register Bits */
+
+/* Register Bits [UCSR0B]  */
+/* USART0 Control Register B - UCSR0B */
+#define    RXCIE0       7
+#define    TXCIE0       6
+#define    UDRIE0       5
+#define    RXEN0        4
+#define    TXEN0        3
+#define    UCSZ02       2
+#define    RXB80        1
+#define    TXB80        0
+/* End Register Bits */
+
+/* Register Bits [ACSR]  */
+/* Analog Comparator Control and Status Register - ACSR */
+#define    ACD          7
+#define    ACBG         6
+#define    ACO          5
+#define    ACI          4
+#define    ACIE         3
+#define    ACIC         2
+#define    ACIS1        1
+#define    ACIS0        0
+/* End Register Bits */
+
+/* Register Bits [ADCSRA]  */
+/* ADC Control and status register - ADCSRA */
+#define    ADEN         7
+#define    ADSC         6
+#define    ADATE        5
+#define    ADIF         4
+#define    ADIE         3
+#define    ADPS2        2
+#define    ADPS1        1
+#define    ADPS0        0
+/* End Register Bits */
+
+/* 
+   The ADHSM bit has been removed from all documentation, 
+   as being not needed at all since the comparator has proven 
+   to be fast enough even without feeding it more power.
+*/
+
+/* Register Bits [ADCSRB]  */
+/* ADC Control and status register - ADCSRB */
+#define    ACME         6
+#define    ADTS2        2
+#define    ADTS1        1
+#define    ADTS0        0
+/* End Register Bits */
+
+/* Register Bits [ADMUX]  */
+/* ADC Multiplexer select - ADMUX */
+#define    REFS1        7
+#define    REFS0        6
+#define    ADLAR        5
+#define    MUX4         4
+#define    MUX3         3
+#define    MUX2         2
+#define    MUX1         1
+#define    MUX0         0
+/* End Register Bits */
+
+/* Register Bits [DIDR0]  */
+/* Digital Input Disable Register 0 */
+#define    ADC7D        7
+#define    ADC6D        6
+#define    ADC5D        5
+#define    ADC4D        4
+#define    ADC3D        3
+#define    ADC2D        2
+#define    ADC1D        1
+#define    ADC0D        0
+/* End Register Bits */
+
+/* Register Bits [DIDR1]  */
+/* Digital Input Disable Register 1 */
+#define    AIN1D        1
+#define    AIN0D        0
+/* End Register Bits */
+
+/* Register Bits [PORTA]  */
+/* Port A Data Register - PORTA */
+#define    PA7          7
+#define    PA6          6
+#define    PA5          5
+#define    PA4          4
+#define    PA3          3
+#define    PA2          2
+#define    PA1          1
+#define    PA0          0
+/* End Register Bits */
+
+/* Register Bits [DDRA]  */
+/* Port A Data Direction Register - DDRA */
+#define    DDA7         7
+#define    DDA6         6
+#define    DDA5         5
+#define    DDA4         4
+#define    DDA3         3
+#define    DDA2         2
+#define    DDA1         1
+#define    DDA0         0
+/* End Register Bits */
+
+/* Register Bits [PINA]  */
+/* Port A Input Pins - PINA */
+#define    PINA7        7
+#define    PINA6        6
+#define    PINA5        5
+#define    PINA4        4
+#define    PINA3        3
+#define    PINA2        2
+#define    PINA1        1
+#define    PINA0        0
+/* End Register Bits */
+
+/* Register Bits [PORTB]  */
+/* Port B Data Register - PORTB */
+#define    PB7          7
+#define    PB6          6
+#define    PB5          5
+#define    PB4          4
+#define    PB3          3
+#define    PB2          2
+#define    PB1          1
+#define    PB0          0
+/* End Register Bits */
+
+/* Register Bits [DDRB]  */
+/* Port B Data Direction Register - DDRB */
+#define    DDB7         7
+#define    DDB6         6
+#define    DDB5         5
+#define    DDB4         4
+#define    DDB3         3
+#define    DDB2         2
+#define    DDB1         1
+#define    DDB0         0
+/* End Register Bits */
+
+/* Register Bits [PINB]  */
+/* Port B Input Pins - PINB */
+#define    PINB7        7
+#define    PINB6        6
+#define    PINB5        5
+#define    PINB4        4
+#define    PINB3        3
+#define    PINB2        2
+#define    PINB1        1
+#define    PINB0        0
+/* End Register Bits */
+
+/* Register Bits [PORTC]  */
+/* Port C Data Register - PORTC */
+#define    PC7          7
+#define    PC6          6
+#define    PC5          5
+#define    PC4          4
+#define    PC3          3
+#define    PC2          2
+#define    PC1          1
+#define    PC0          0
+/* End Register Bits */
+
+/* Register Bits [DDRC]  */
+/* Port C Data Direction Register - DDRC */
+#define    DDC7         7
+#define    DDC6         6
+#define    DDC5         5
+#define    DDC4         4
+#define    DDC3         3
+#define    DDC2         2
+#define    DDC1         1
+#define    DDC0         0
+/* End Register Bits */
+
+/* Register Bits [PINC]  */
+/* Port C Input Pins - PINC */
+#define    PINC7        7
+#define    PINC6        6
+#define    PINC5        5
+#define    PINC4        4
+#define    PINC3        3
+#define    PINC2        2
+#define    PINC1        1
+#define    PINC0        0
+/* End Register Bits */
+
+/* Register Bits [PORTD]  */
+/* Port D Data Register - PORTD */
+#define    PD7          7
+#define    PD6          6
+#define    PD5          5
+#define    PD4          4
+#define    PD3          3
+#define    PD2          2
+#define    PD1          1
+#define    PD0          0
+/* End Register Bits */
+
+/* Register Bits [DDRD]  */
+/* Port D Data Direction Register - DDRD */
+#define    DDD7         7
+#define    DDD6         6
+#define    DDD5         5
+#define    DDD4         4
+#define    DDD3         3
+#define    DDD2         2
+#define    DDD1         1
+#define    DDD0         0
+/* End Register Bits */
+
+/* Register Bits [PIND]  */
+/* Port D Input Pins - PIND */
+#define    PIND7        7
+#define    PIND6        6
+#define    PIND5        5
+#define    PIND4        4
+#define    PIND3        3
+#define    PIND2        2
+#define    PIND1        1
+#define    PIND0        0
+/* End Register Bits */
+
+/* Register Bits [PORTE]  */
+/* Port E Data Register - PORTE */
+#define    PE7          7
+#define    PE6          6
+#define    PE5          5
+#define    PE4          4
+#define    PE3          3
+#define    PE2          2
+#define    PE1          1
+#define    PE0          0
+/* End Register Bits */
+
+/* Register Bits [DDRE]  */
+/* Port E Data Direction Register - DDRE */
+#define    DDE7         7
+#define    DDE6         6
+#define    DDE5         5
+#define    DDE4         4
+#define    DDE3         3
+#define    DDE2         2
+#define    DDE1         1
+#define    DDE0         0
+/* End Register Bits */
+
+/* Register Bits [PINE]  */
+/* Port E Input Pins - PINE */
+#define    PINE7        7
+#define    PINE6        6
+#define    PINE5        5
+#define    PINE4        4
+#define    PINE3        3
+#define    PINE2        2
+#define    PINE1        1
+#define    PINE0        0
+/* End Register Bits */
+
+/* Register Bits [PORTF]  */
+/* Port F Data Register - PORTF */
+#define    PF7          7
+#define    PF6          6
+#define    PF5          5
+#define    PF4          4
+#define    PF3          3
+#define    PF2          2
+#define    PF1          1
+#define    PF0          0
+/* End Register Bits */
+
+/* Register Bits [DDRF]  */
+/* Port F Data Direction Register - DDRF */
+#define    DDF7         7
+#define    DDF6         6
+#define    DDF5         5
+#define    DDF4         4
+#define    DDF3         3
+#define    DDF2         2
+#define    DDF1         1
+#define    DDF0         0
+/* End Register Bits */
+
+/* Register Bits [PINF]  */
+/* Port F Input Pins - PINF */
+#define    PINF7        7
+#define    PINF6        6
+#define    PINF5        5
+#define    PINF4        4
+#define    PINF3        3
+#define    PINF2        2
+#define    PINF1        1
+#define    PINF0        0
+/* End Register Bits */
+
+/* Register Bits [PORTG]  */
+/* Port G Data Register - PORTG */
+#define    PG4          4
+#define    PG3          3
+#define    PG2          2
+#define    PG1          1
+#define    PG0          0
+/* End Register Bits */
+
+/* Register Bits [DDRG]  */
+/* Port G Data Direction Register - DDRG */
+#define    DDG4         4
+#define    DDG3         3
+#define    DDG2         2
+#define    DDG1         1
+#define    DDG0         0
+/* End Register Bits */
+
+/* Register Bits [PING]  */
+/* Port G Input Pins - PING */
+#define    PING4        4
+#define    PING3        3
+#define    PING2        2
+#define    PING1        1
+#define    PING0        0
+/* End Register Bits */
+
+
+/* Register Bits [TIFR0]  */
+/* Timer/Counter 0 interrupt Flag Register */
+#define    OCF0A        1
+#define    TOV0         0
+/* End Register Bits */
+
+/* Register Bits [TIFR1]  */
+/* Timer/Counter 1 interrupt Flag Register */
+#define    ICF1       5
+#define    OCF1C      3
+#define    OCF1B      2
+#define    OCF1A      1
+#define    TOV1       0
+/* End Register Bits */
+
+/* Register Bits [TIFR2]  */
+/* Timer/Counter 2 interrupt Flag Register */
+#define    OCF2A      1
+#define    TOV2       0
+/* End Register Bits */
+
+/* Register Bits [TIFR3]  */
+/* Timer/Counter 3 interrupt Flag Register */
+#define    ICF3       5
+#define    OCF3C      3
+#define    OCF3B      2
+#define    OCF3A      1
+#define    TOV3       0
+/* End Register Bits */
+
+/* Register Bits [GPIOR0]  */
+/* General Purpose I/O Register 0 */
+#define    GPIOR07     7
+#define    GPIOR06     6
+#define    GPIOR05     5
+#define    GPIOR04     4
+#define    GPIOR03     3
+#define    GPIOR02     2
+#define    GPIOR01     1
+#define    GPIOR00     0
+/* End Register Bits */
+
+/* Register Bits [GPIOR1]  */
+/* General Purpose I/O Register 1 */
+#define    GPIOR17     7
+#define    GPIOR16     6
+#define    GPIOR15     5
+#define    GPIOR14     4
+#define    GPIOR13     3
+#define    GPIOR12     2
+#define    GPIOR11     1
+#define    GPIOR10     0
+/* End Register Bits */
+
+/* Register Bits [GPIOR2]  */
+/* General Purpose I/O Register 2 */
+#define    GPIOR27     7
+#define    GPIOR26     6
+#define    GPIOR25     5
+#define    GPIOR24     4
+#define    GPIOR23     3
+#define    GPIOR22     2
+#define    GPIOR21     1
+#define    GPIOR20     0
+/* End Register Bits */
+
+/* Register Bits [EECR]  */
+/* EEPROM Control Register */
+#define    EERIE       3
+#define    EEMWE       2
+#define    EEWE        1
+#define    EERE        0
+/* End Register Bits */
+
+/* Register Bits [EEDR]  */
+/* EEPROM Data Register */
+#define    EEDR7     7
+#define    EEDR6     6
+#define    EEDR5     5
+#define    EEDR4     4
+#define    EEDR3     3
+#define    EEDR2     2
+#define    EEDR1     1
+#define    EEDR0     0
+/* End Register Bits */
+
+/* Register Bits [EEARL]  */
+/* EEPROM Address Register */
+#define    EEAR7     7
+#define    EEAR6     6
+#define    EEAR5     5
+#define    EEAR4     4
+#define    EEAR3     3
+#define    EEAR2     2
+#define    EEAR1     1
+#define    EEAR0     0
+/* End Register Bits */
+
+/* Register Bits [EEARH]  */
+/* EEPROM Address Register */
+#define    EEAR11    3
+#define    EEAR10    2
+#define    EEAR9     1
+#define    EEAR8     0
+/* End Register Bits */
+
+/* Register Bits [GTCCR]  */
+/* General Timer/Counter Control Register  */
+#define    TSM      7
+#define    PSR2     1
+#define    PSR310   0
+/* End Register Bits */
+
+/* Register Bits [TCCR0A]  */
+/* Timer/Counter Control Register A */
+/* ALSO COVERED IN GENERIC SECTION */
+#define    FOC0A    7
+#define    WGM00    6
+#define    COM0A1   5
+#define    COM0A0   4
+#define    WGM01    3
+#define    CS02     2
+#define    CS01     1
+#define    CS00     0
+/* End Register Bits */
+
+/* Register Bits [OCR0A]  */
+/* Output Compare Register A */
+#define    OCR0A7     7
+#define    OCR0A6     6
+#define    OCR0A5     5
+#define    OCR0A4     4
+#define    OCR0A3     3
+#define    OCR0A2     2
+#define    OCR0A1     1
+#define    OCR0A0     0
+/* End Register Bits */
+
+
+/* Register Bits [SPIDR]  */
+/* SPI Data Register */
+#define    SPD7     7
+#define    SPD6     6
+#define    SPD5     5
+#define    SPD4     4
+#define    SPD3     3
+#define    SPD2     2
+#define    SPD1     1
+#define    SPD0     0
+/* End Register Bits */
+
+/* Register Bits [SMCR]  */
+/* Sleep Mode Control Register */
+#define    SM2     3
+#define    SM1     2
+#define    SM0     1
+#define    SE      0
+/* End Register Bits */
+
+/* Register Bits [MCUSR]  */
+/* MCU Status Register */
+#define    JTRF    4
+#define    WDRF    3
+#define    BORF    2
+#define    EXTRF   1
+#define    PORF    0
+/* End Register Bits */
+
+/* Register Bits [MCUCR]  */
+/* MCU Control Register */
+#define    JTD     7
+#define    PUD     4
+#define    IVSEL   1
+#define    IVCE    0
+/* End Register Bits */
+
+/* Register Bits [CLKPR]  */
+/* Clock Prescale Register */
+#define    CLKPCE     7
+#define    CLKPS3     3
+#define    CLKPS2     2
+#define    CLKPS1     1
+#define    CLKPS0     0
+/* End Register Bits */
+
+/* Register Bits [OSCCAL]  */
+/* Oscillator Calibration Register */
+#define    CAL6     6
+#define    CAL5     5
+#define    CAL4     4
+#define    CAL3     3
+#define    CAL2     2
+#define    CAL1     1
+#define    CAL0     0
+/* End Register Bits */
+
+/* Register Bits [TIMSK0]  */
+/* Timer/Counter 0 interrupt mask Register */
+#define    OCIE0A      1
+#define    TOIE0       0
+/* End Register Bits */
+
+/* Register Bits [TIMSK1]  */
+/* Timer/Counter 1 interrupt mask Register */
+#define    ICIE1       5
+#define    OCIE1C      3
+#define    OCIE1B      2
+#define    OCIE1A      1
+#define    TOIE1       0
+/* End Register Bits */
+
+/* Register Bits [TIMSK2]  */
+/* Timer/Counter 2 interrupt mask Register */
+#define    OCIE2A      1
+#define    TOIE2       0
+/* End Register Bits */
+
+/* Register Bits [TIMSK3]  */
+/* Timer/Counter 3 interrupt mask Register */
+#define    ICIE3       5
+#define    OCIE3C      3
+#define    OCIE3B      2
+#define    OCIE3A      1
+#define    TOIE3       0
+/* End Register Bits */
+
+//Begin CAN specific parts
+
+/* Register Bits [CANGCON]  */
+/* CAN General Control Register */
+#define    ABRQ       7
+#define    OVRQ       6
+#define    TTC        5
+#define    SYNTTC     4
+#define    LISTEN     3
+#define    TEST       2
+#define    ENASTB     1
+#define    SWRES      0
+/* End Register Bits */
+
+/* Register Bits [CANGSTA]  */
+/* CAN General Status Register */
+#define    OVFG       6
+#define    OVRG       6
+#define    TXBSY      4
+#define    RXBSY      3
+#define    ENFG       2
+#define    BOFF       1
+#define    ERRP       0
+/* End Register Bits */
+
+/* Register Bits [CANGIT]  */
+/* CAN General Interrupt Register */
+#define    CANIT      7
+#define    BOFFIT     6
+#define    OVRTIM     5
+#define    BXOK       4
+#define    SERG       3
+#define    CERG       2
+#define    FERG       1
+#define    AERG       0
+/* End Register Bits */
+
+/* Register Bits [CANGIE]  */
+/* CAN General Interrupt Enable */
+#define    ENIT        7
+#define    ENBOFF      6
+#define    ENRX        5
+#define    ENTX        4
+#define    ENERR       3
+#define    ENBX        2
+#define    ENERG       1
+#define    ENOVRT      0
+/* End Register Bits */
+
+/* Register Bits [CANEN2]  */
+/* CAN Enable MOb Register */
+#define    ENMOB7      7
+#define    ENMOB6      6
+#define    ENMOB5      5
+#define    ENMOB4      4
+#define    ENMOB3      3
+#define    ENMOB2      2
+#define    ENMOB1      1
+#define    ENMOB0      0
+/* End Register Bits */
+
+/* Register Bits [CANEN1]  */
+/* CAN Enable MOb Register */
+#define    ENMOB14      6
+#define    ENMOB13      5
+#define    ENMOB12      4
+#define    ENMOB11      3
+#define    ENMOB10      2
+#define    ENMOB9       1
+#define    ENMOB8       0
+/* End Register Bits */
+
+/* Register Bits [CANIE2]  */
+/* CAN Interrupt Enable MOb Register */
+#define    IEMOB7      7
+#define    IEMOB6      6
+#define    IEMOB5      5
+#define    IEMOB4      4
+#define    IEMOB3      3
+#define    IEMOB2      2
+#define    IEMOB1      1
+#define    IEMOB0      0
+/* End Register Bits */
+
+/* Register Bits [CANIE1]  */
+/* CAN Interrupt Enable MOb Register */
+#define    IEMOB14      6
+#define    IEMOB13      5
+#define    IEMOB12      4
+#define    IEMOB11      3
+#define    IEMOB10      2
+#define    IEMOB9       1
+#define    IEMOB8       0
+/* End Register Bits */
+
+/* Register Bits [CANSIT2]  */
+/* CAN Status Interrupt MOb Register */
+#define    SIT7      7
+#define    SIT6      6
+#define    SIT5      5
+#define    SIT4      4
+#define    SIT3      3
+#define    SIT2      2
+#define    SIT1      1
+#define    SIT0      0
+/* End Register Bits */
+
+/* Register Bits [CANSIT1]  */
+/* CAN Status Interrupt MOb Register */
+#define    SIT14      6
+#define    SIT13      5
+#define    SIT12      4
+#define    SIT11      3
+#define    SIT10      2
+#define    SIT9       1
+#define    SIT8       0
+/* End Register Bits */
+
+/* Register Bits [CANBT1]  */
+/* Bit Timing Register 1 */
+#define    BRP5       6
+#define    BRP4       5
+#define    BRP3       4
+#define    BRP2       3
+#define    BRP1       2
+#define    BRP0       1
+/* End Register Bits */
+
+/* Register Bits [CANBT2]  */
+/* Bit Timing Register 2 */
+#define    SJW1       6
+#define    SJW0       5
+#define    PRS2       3
+#define    PRS1       2
+#define    PRS0       1
+/* End Register Bits */
+
+/* Register Bits [CANBT3]  */
+/* Bit Timing Register 3 */
+#define    PHS22      6
+#define    PHS21      5
+#define    PHS20      4
+#define    PHS12      3
+#define    PHS11      2
+#define    PHS10      1
+#define    SMP        0
+/* End Register Bits */
+
+/* Register Bits [CANTCON]  */
+/* CAN Timer Control Register */
+#define    TPRSC7      7
+#define    TPRSC6      6
+#define    TPRSC5      5
+#define    TPRSC4      4
+#define    TPRSC3      3
+#define    TPRSC2      2
+#define    TPRSC1      1
+#define    TPRSC0      0
+/* End Register Bits */
+
+/* Register Bits [CANTIML]  */
+/* CAN Timer Register Low */
+#define    CANTIM7      7
+#define    CANTIM6      6
+#define    CANTIM5      5
+#define    CANTIM4      4
+#define    CANTIM3      3
+#define    CANTIM2      2
+#define    CANTIM1      1
+#define    CANTIM0      0
+/* End Register Bits */
+
+/* Register Bits [CANTIMH]  */
+/* CAN Timer Register High */
+#define    CANTIM15     7
+#define    CANTIM14     6
+#define    CANTIM13     5
+#define    CANTIM12     4
+#define    CANTIM11     3
+#define    CANTIM10     2
+#define    CANTIM9      1
+#define    CANTIM8      0
+/* End Register Bits */
+
+/* Register Bits [CANTTCL]  */
+/* CAN TTC Timer Register Low */
+#define    TIMTTC7      7
+#define    TIMTTC6      6
+#define    TIMTTC5      5
+#define    TIMTTC4      4
+#define    TIMTTC3      3
+#define    TIMTTC2      2
+#define    TIMTTC1      1
+#define    TIMTTC0      0
+/* End Register Bits */
+
+/* Register Bits [CANTTCH]  */
+/* CAN TTC Timer Register High */
+#define    TIMTTC15     7
+#define    TIMTTC14     6
+#define    TIMTTC13     5
+#define    TIMTTC12     4
+#define    TIMTTC11     3
+#define    TIMTTC10     2
+#define    TIMTTC9      1
+#define    TIMTTC8      0
+/* End Register Bits */
+
+/* Register Bits [CANTEC]  */
+/* CAN Transmitt Error Counter */
+#define    TEC7      7
+#define    TEC6      6
+#define    TEC5      5
+#define    TEC4      4
+#define    TEC3      3
+#define    TEC2      2
+#define    TEC1      1
+#define    TEC0      0
+/* End Register Bits */
+
+/* Register Bits [CANREC]  */
+/* CAN Receive Error Counter */
+#define    REC7      7
+#define    REC6      6
+#define    REC5      5
+#define    REC4      4
+#define    REC3      3
+#define    REC2      2
+#define    REC1      1
+#define    REC0      0
+/* End Register Bits */
+
+/* Register Bits [CANHPMOB]  */
+/* Highest Priority MOb */
+#define    HPMOB3     7
+#define    HPMOB2     6
+#define    HPMOB1     5
+#define    HPMOB0     4
+#define    CGP3       3
+#define    CGP2       2
+#define    CGP1       1
+#define    CGP0       0
+/* End Register Bits */
+
+/* Register Bits [CANPAGE]  */
+/* CAN Page MOb Register */
+#define    MOBNB3     7
+#define    MOBNB2     6
+#define    MOBNB1     5
+#define    MOBNB0     4
+#define    AINC       3
+#define    INDX2      2
+#define    INDX1      1
+#define    INDX0      0
+/* End Register Bits */
+
+/* Register Bits [CANSTMOB]  */
+/* CAN MOb Status Register */
+#define    DLCW       7
+#define    TXOK       6
+#define    RXOK       5
+#define    BERR       4
+#define    SERR       3
+#define    CERR       2
+#define    FERR       1
+#define    AERR       0
+/* End Register Bits */
+
+/* Register Bits [CANCDMOB]  */
+/* CAN MOb Control and DLC Register */
+#define    CONMOB1    7
+#define    CONMOB0    6
+#define    RPLV       5
+#define    IDE        4
+#define    DLC3       3
+#define    DLC2       2
+#define    DLC1       1
+#define    DLC0       0
+/* End Register Bits */
+
+/* Register Bits [CANIDT4]  */
+/* CAN Identifier Tag Register 4 */
+#define    IDT4       7
+#define    IDT3       6
+#define    IDT2       5
+#define    IDT1       4
+#define    IDT0       3
+#define    RTRTAG     2
+#define    RB1TAG     1
+#define    RB0TAG     0
+/* End Register Bits */
+
+/* Register Bits [CANIDT3]  */
+/* CAN Identifier Tag Register 3 */
+#define    IDT12      7
+#define    IDT11      6
+#define    IDT10      5
+#define    IDT9       4
+#define    IDT8       3
+#define    IDT7       2
+#define    IDT6       1
+#define    IDT5       0
+/* End Register Bits */
+
+/* Register Bits [CANIDT2]  */
+/* CAN Identifier Tag Register 2 */
+#define    IDT20      7
+#define    IDT19      6
+#define    IDT18      5
+#define    IDT17      4
+#define    IDT16      3
+#define    IDT15      2
+#define    IDT14      1
+#define    IDT13      0
+/* End Register Bits */
+
+/* Register Bits [CANIDT1]  */
+/* CAN Identifier Tag Register 1 */
+#define    IDT28      7
+#define    IDT27      6
+#define    IDT26      5
+#define    IDT25      4
+#define    IDT24      3
+#define    IDT23      2
+#define    IDT22      1
+#define    IDT21      0
+/* End Register Bits */
+
+/* Register Bits [CANIDM4]  */
+/* CAN Identifier Mask Register 4 */
+#define    IDMSK4       7
+#define    IDMSK3       6
+#define    IDMSK2       5
+#define    IDMSK1       4
+#define    IDMSK0       3
+#define    RTRMSK       2
+#define    IDEMSK       0
+/* End Register Bits */
+
+/* Register Bits [CANIDM3]  */
+/* CAN Identifier Mask Register 3 */
+#define    IDMSK12      7
+#define    IDMSK11      6
+#define    IDMSK10      5
+#define    IDMSK9       4
+#define    IDMSK8       3
+#define    IDMSK7       2
+#define    IDMSK6       1
+#define    IDMSK5       0
+/* End Register Bits */
+
+/* Register Bits [CANIDM2]  */
+/* CAN Identifier Mask Register 2 */
+#define    IDMSK20      7
+#define    IDMSK19      6
+#define    IDMSK18      5
+#define    IDMSK17      4
+#define    IDMSK16      3
+#define    IDMSK15      2
+#define    IDMSK14      1
+#define    IDMSK13      0
+/* End Register Bits */
+
+/* Register Bits [CANIDM1]  */
+/* CAN Identifier Mask Register 1 */
+#define    IDMSK28      7
+#define    IDMSK27      6
+#define    IDMSK26      5
+#define    IDMSK25      4
+#define    IDMSK24      3
+#define    IDMSK23      2
+#define    IDMSK22      1
+#define    IDMSK21      0
+/* End Register Bits */
+
+/* Register Bits [CANSTML]  */
+/* CAN Timer Register of some sort, low*/
+#define    TIMSTM7       7
+#define    TIMSTM6       6
+#define    TIMSTM5       5
+#define    TIMSTM4       4
+#define    TIMSTM3       3
+#define    TIMSTM2       2
+#define    TIMSTM1       1
+#define    TIMSTM0       0
+/* End Register Bits */
+
+/* Register Bits [CANSTMH]  */
+/* CAN Timer Register of some sort, high */
+#define    TIMSTM15       7
+#define    TIMSTM14       6
+#define    TIMSTM13       5
+#define    TIMSTM12       4
+#define    TIMSTM11       3
+#define    TIMSTM10       2
+#define    TIMSTM9        1
+#define    TIMSTM8        0
+/* End Register Bits */
+
+/* Register Bits [CANMSG]  */
+/* CAN Message Register */
+#define    MSG7           7
+#define    MSG6           6
+#define    MSG5           5
+#define    MSG4           4
+#define    MSG3           3
+#define    MSG2           2
+#define    MSG1           1
+#define    MSG0           0
+/* End Register Bits */
+
+/* Begin Verbatim */
+
+/* Timer/Counter Control Register (generic) */
+#define    FOC          7
+#define    WGM0         6
+#define    COM1         5
+#define    COM0         4
+#define    WGM1         3
+#define    CS2          2
+#define    CS1          1
+#define    CS0          0
+
+/* Timer/Counter Control Register A (generic) */
+#define    COMA1        7
+#define    COMA0        6
+#define    COMB1        5
+#define    COMB0        4
+#define    COMC1        3
+#define    COMC0        2
+#define    WGMA1        1
+#define    WGMA0        0
+
+/* Timer/Counter Control and Status Register B (generic) */
+#define    ICNC         7
+#define    ICES         6
+#define    WGMB3        4
+#define    WGMB2        3
+#define    CSB2         2
+#define    CSB1         1
+#define    CSB0         0
+
+/* Timer/Counter Control Register C (generic) */
+#define    FOCA         7
+#define    FOCB         6
+#define    FOCC         5
+
+/* Port Data Register (generic) */
+#define    PORT7        7
+#define    PORT6        6
+#define    PORT5        5
+#define    PORT4        4
+#define    PORT3        3
+#define    PORT2        2
+#define    PORT1        1
+#define    PORT0        0
+
+/* Port Data Direction Register (generic) */
+#define    DD7          7
+#define    DD6          6
+#define    DD5          5
+#define    DD4          4
+#define    DD3          3
+#define    DD2          2
+#define    DD1          1
+#define    DD0          0
+
+/* Port Input Pins (generic) */
+#define    PIN7         7
+#define    PIN6         6
+#define    PIN5         5
+#define    PIN4         4
+#define    PIN3         3
+#define    PIN2         2
+#define    PIN1         1
+#define    PIN0         0
+
+/* USART Status Register A (generic) */
+#define    RXC          7
+#define    TXC          6
+#define    UDRE         5
+#define    FE           4
+#define    DOR          3
+#define    UPE          2
+#define    U2X          1
+#define    MPCM         0
+
+/* USART Control Register B (generic) */
+#define    RXCIE        7
+#define    TXCIE        6
+#define    UDRIE        5
+#define    RXEN         4
+#define    TXEN         3
+#define    UCSZ         2
+#define    UCSZ2        2       /* new name in datasheet (2467E-AVR-05/02) */
+#define    RXB8         1
+#define    TXB8         0
+
+/* USART Register C (generic) */
+#define    UMSEL        6
+#define    UPM1         5
+#define    UPM0         4
+#define    USBS         3
+#define    UCSZ1        2
+#define    UCSZ0        1
+#define    UCPOL        0
+
+/* End Verbatim */
 
 /* Constants */
 #define SPM_PAGESIZE 256
@@ -91,12 +2052,10 @@
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x81
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif  /* _AVR_IOCAN32_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iocan64.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iocan64.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
+/* Copyright (c) 2004,2005,2006 Colin O'Flynn <coflynn@newae.com>, 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,14 +28,1975 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iocan64.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* iocan64.h - definitions for CAN64 */
 
 #ifndef _AVR_IOCAN64_H_
 #define _AVR_IOCAN64_H_ 1
 
-#include <avr/iocanxx.h>
+
+/* I/O registers and bit definitions. */
+
+/* RegDef:  Port A */
+#define PINA   _SFR_IO8(0x00)
+#define DDRA   _SFR_IO8(0x01)
+#define PORTA  _SFR_IO8(0x02)
+
+/* RegDef:  Port B */
+#define PINB   _SFR_IO8(0x03)
+#define DDRB   _SFR_IO8(0x04)
+#define PORTB  _SFR_IO8(0x05)
+
+/* RegDef:  Port C */
+#define PINC   _SFR_IO8(0x06)
+#define DDRC   _SFR_IO8(0x07)
+#define PORTC  _SFR_IO8(0x08)
+
+/* RegDef:  Port D */
+#define PIND   _SFR_IO8(0x09)
+#define DDRD   _SFR_IO8(0x0A)
+#define PORTD  _SFR_IO8(0x0B)
+
+/* RegDef:  Port E */
+#define PINE   _SFR_IO8(0x0C)
+#define DDRE   _SFR_IO8(0x0D)
+#define PORTE  _SFR_IO8(0x0E)
+
+/* RegDef:  Port F */
+#define PINF   _SFR_IO8(0x0F)
+#define DDRF   _SFR_IO8(0x10)
+#define PORTF  _SFR_IO8(0x11)
+
+/* RegDef:  Port G */
+#define PING   _SFR_IO8(0x12)
+#define DDRG   _SFR_IO8(0x13)
+#define PORTG  _SFR_IO8(0x14)
+
+/* RegDef:  Timer/Counter 0 interrupt Flag Register */
+#define TIFR0  _SFR_IO8(0x15)
+
+/* RegDef:  Timer/Counter 1 interrupt Flag Register */
+#define TIFR1  _SFR_IO8(0x16)
+
+/* RegDef:  Timer/Counter 2 interrupt Flag Register */
+#define TIFR2  _SFR_IO8(0x17)
+
+/* RegDef:  Timer/Counter 3 interrupt Flag Register */
+#define TIFR3  _SFR_IO8(0x18)
+
+/* RegDef:  External Interrupt Flag Register */
+#define EIFR   _SFR_IO8(0x1C)
+
+/* RegDef:  External Interrupt Mask Register */
+#define EIMSK  _SFR_IO8(0x1D)
+
+/* RegDef:  General Purpose I/O Register 0 */
+#define GPIOR0 _SFR_IO8(0x1E)
+
+/* RegDef:  EEPROM Control Register */
+#define EECR   _SFR_IO8(0x1F)
+
+/* RegDef:  EEPROM Data Register */
+#define EEDR   _SFR_IO8(0x20)
+
+/* RegDef:  EEPROM Address Register */
+#define EEAR   _SFR_IO16(0x21)
+#define EEARL  _SFR_IO8(0x21)
+#define EEARH  _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+/* RegDef:  General Timer/Counter Control Register */
+#define GTCCR  _SFR_IO8(0x23)
+
+/* RegDef:  Timer/Counter Control Register A */
+#define TCCR0A _SFR_IO8(0x24)
+
+/* RegDef:  Timer/Counter Register */
+#define TCNT0  _SFR_IO8(0x26)
+
+/* RegDef:  Output Compare Register A */
+#define OCR0A  _SFR_IO8(0x27)
+
+/* RegDef:  General Purpose I/O Register 1 */
+#define GPIOR1 _SFR_IO8(0x2A)
+
+/* RegDef:  General Purpose I/O Register 2 */
+#define GPIOR2 _SFR_IO8(0x2B)
+
+/* RegDef:  SPI Control Register */
+#define SPCR   _SFR_IO8(0x2C)
+
+/* RegDef:  SPI Status Register */
+#define SPSR   _SFR_IO8(0x2D)
+
+/* RegDef:  SPI Data Register */
+#define SPDR   _SFR_IO8(0x2E)
+
+/* RegDef:  Analog Comperator Control and Status Register */
+#define ACSR   _SFR_IO8(0x30)
+
+/* RegDef:  On-chip Debug Register */
+#define OCDR   _SFR_IO8(0x31)
+
+/* RegDef:  Sleep Mode Control Register */
+#define SMCR   _SFR_IO8(0x33)
+
+/* RegDef:  MCU Status Register */
+#define MCUSR  _SFR_IO8(0x34)
+
+/* RegDef:  MCU Control Rgeister */
+#define MCUCR  _SFR_IO8(0x35)
+
+/* RegDef:  Store Program Memory Control and Status Register */
+#define SPMCSR _SFR_IO8(0x37)
+
+/* RegDef:  RAMPZ register. */
+#define RAMPZ  _SFR_IO8(0x3B)
+
+/* RegDef:  Watchdog Timer Control Register */
+#define WDTCR  _SFR_MEM8(0x60)
+
+/* RegDef:  Clock Prescale Register */
+#define CLKPR  _SFR_MEM8(0x61)
+
+/* RegDef:  Oscillator Calibration Register */
+#define OSCCAL _SFR_MEM8(0x66)
+
+/* RegDef:  External Interrupt Control Register A */
+#define EICRA  _SFR_MEM8(0x69)
+
+/* RegDef:  External Interrupt Control Register B */
+#define EICRB  _SFR_MEM8(0x6A)
+
+/* RegDef:  Timer/Counter 0 Interrupt Mask Register */
+#define TIMSK0 _SFR_MEM8(0x6E)
+
+/* RegDef:  Timer/Counter 1 Interrupt Mask Register */
+#define TIMSK1 _SFR_MEM8(0x6F)
+
+/* RegDef:  Timer/Counter 2 Interrupt Mask Register */
+#define TIMSK2 _SFR_MEM8(0x70)
+
+/* RegDef:  Timer/Counter 3 Interrupt Mask Register */
+#define TIMSK3 _SFR_MEM8(0x71)
+
+/* RegDef:  External Memory Control Register A */
+#define XMCRA _SFR_MEM8(0x74)
+
+/* RegDef:  External Memory Control Register A */
+#define XMCRB _SFR_MEM8(0x75)
+
+/* RegDef:  ADC Data Register */
+#ifndef __ASSEMBLER__
+#define ADC    _SFR_MEM16(0x78)
+#endif
+#define ADCW   _SFR_MEM16(0x78)
+#define ADCL   _SFR_MEM8(0x78)
+#define ADCH   _SFR_MEM8(0x79)
+
+/* RegDef:  ADC Control and Status Register A */
+#define ADCSRA _SFR_MEM8(0x7A)
+
+/* RegDef:  ADC Control and Status Register B */
+#define ADCSRB _SFR_MEM8(0x7B)
+
+/* RegDef:  ADC Multiplex Selection Register */
+#define ADMUX  _SFR_MEM8(0x7C)
+
+/* RegDef:  Digital Input Disable Register 0 */
+#define DIDR0  _SFR_MEM8(0x7E)
+
+/* RegDef:  Digital Input Disable Register 1 */
+#define DIDR1  _SFR_MEM8(0x7F)
+
+/* RegDef:  Timer/Counter1 Control Register A */
+#define TCCR1A _SFR_MEM8(0x80)
+
+/* RegDef:  Timer/Counter1 Control Register B */
+#define TCCR1B _SFR_MEM8(0x81)
+
+/* RegDef:  Timer/Counter1 Control Register C */
+#define TCCR1C _SFR_MEM8(0x82)
+
+/* RegDef:  Timer/Counter1 Register */
+#define TCNT1  _SFR_MEM16(0x84)
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1H _SFR_MEM8(0x85)
+
+/* RegDef:  Timer/Counter1 Input Capture Register */
+#define ICR1   _SFR_MEM16(0x86)
+#define ICR1L  _SFR_MEM8(0x86)
+#define ICR1H  _SFR_MEM8(0x87)
+
+/* RegDef:  Timer/Counter1 Output Compare Register A */
+#define OCR1A  _SFR_MEM16(0x88)
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AH _SFR_MEM8(0x89)
+
+/* RegDef:  Timer/Counter1 Output Compare Register B */
+#define OCR1B  _SFR_MEM16(0x8A)
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BH _SFR_MEM8(0x8B)
+
+/* RegDef:  Timer/Counter1 Output Compare Register C */
+#define OCR1C  _SFR_MEM16(0x8C)
+#define OCR1CL _SFR_MEM8(0x8C)
+#define OCR1CH _SFR_MEM8(0x8D)
+
+/* RegDef:  Timer/Counter3 Control Register A */
+#define TCCR3A _SFR_MEM8(0x90)
+
+/* RegDef:  Timer/Counter3 Control Register B */
+#define TCCR3B _SFR_MEM8(0x91)
+
+/* RegDef:  Timer/Counter3 Control Register C */
+#define TCCR3C _SFR_MEM8(0x92)
+
+/* RegDef:  Timer/Counter3 Register */
+#define TCNT3  _SFR_MEM16(0x94)
+#define TCNT3L _SFR_MEM8(0x94)
+#define TCNT3H _SFR_MEM8(0x95)
+
+/* RegDef:  Timer/Counter3 Input Capture Register */
+#define ICR3   _SFR_MEM16(0x96)
+#define ICR3L  _SFR_MEM8(0x96)
+#define ICR3H  _SFR_MEM8(0x97)
+
+/* RegDef:  Timer/Counter3 Output Compare Register A */
+#define OCR3A  _SFR_MEM16(0x98)
+#define OCR3AL _SFR_MEM8(0x98)
+#define OCR3AH _SFR_MEM8(0x99)
+
+/* RegDef:  Timer/Counter3 Output Compare Register B */
+#define OCR3B  _SFR_MEM16(0x9A)
+#define OCR3BL _SFR_MEM8(0x9A)
+#define OCR3BH _SFR_MEM8(0x9B)
+
+/* RegDef:  Timer/Counter3 Output Compare Register C */
+#define OCR3C  _SFR_MEM16(0x9C)
+#define OCR3CL _SFR_MEM8(0x9C)
+#define OCR3CH _SFR_MEM8(0x9D)
+
+/* RegDef:  Timer/Counter2 Control Register A */
+#define TCCR2A _SFR_MEM8(0xB0)
+
+/* RegDef:  Timer/Counter2 Register */
+#define TCNT2  _SFR_MEM8(0xB2)
+
+/* RegDef:  Timer/Counter2 Output Compare Register */
+#define OCR2A  _SFR_MEM8(0xB3)
+
+/* RegDef:  Asynchronous Status Register */
+#define ASSR   _SFR_MEM8(0xB6)
+
+/* RegDef:  TWI Bit Rate Register */
+#define TWBR   _SFR_MEM8(0xB8)
+
+/* RegDef:  TWI Status Register */
+#define TWSR   _SFR_MEM8(0xB9)
+
+/* RegDef:  TWI (Slave) Address Register */
+#define TWAR   _SFR_MEM8(0xBA)
+
+/* RegDef:  TWI Data Register */
+#define TWDR   _SFR_MEM8(0xBB)
+
+/* RegDef:  TWI Control Register */
+#define TWCR   _SFR_MEM8(0xBC)
+
+/* RegDef:  USART0 Control and Status Register A */
+#define UCSR0A _SFR_MEM8(0xC0)
+
+/* RegDef:  USART0 Control and Status Register B */
+#define UCSR0B _SFR_MEM8(0xC1)
+
+/* RegDef:  USART0 Control and Status Register C */
+#define UCSR0C _SFR_MEM8(0xC2)
+
+/* RegDef:  USART0 Baud Rate Register */
+#define UBRR0  _SFR_MEM16(0xC4)
+#define UBRR0L _SFR_MEM8(0xC4)
+#define UBRR0H _SFR_MEM8(0xC5)
+
+/* RegDef:  USART0 I/O Data Register */
+#define UDR0   _SFR_MEM8(0xC6)
+
+/* RegDef:  USART1 Control and Status Register A */
+#define UCSR1A _SFR_MEM8(0xC8)
+
+/* RegDef:  USART1 Control and Status Register B */
+#define UCSR1B _SFR_MEM8(0xC9)
+
+/* RegDef:  USART1 Control and Status Register C */
+#define UCSR1C _SFR_MEM8(0xCA)
+
+/* RegDef:  USART1 Baud Rate Register */
+#define UBRR1  _SFR_MEM16(0xCC)
+#define UBRR1L _SFR_MEM8(0xCC)
+#define UBRR1H _SFR_MEM8(0xCD)
+
+/* RegDef:  USART1 I/O Data Register */
+#define UDR1   _SFR_MEM8(0xCE)
+
+/* RegDef:  CAN General Control Register*/
+#define CANGCON _SFR_MEM8(0xD8)
+
+/* RegDef:  CAN General Status Register*/
+#define CANGSTA _SFR_MEM8(0xD9)
+
+/* RegDef:  CAN General Interrupt Register*/
+#define CANGIT _SFR_MEM8(0xDA)
+
+/* RegDef:  CAN General Interrupt Enable Register*/
+#define CANGIE _SFR_MEM8(0xDB)
+
+/* Word Definition:  CAN Enable MOb Register*/
+#define CANEN _SFR_MEM16(0xDC) 
+
+/* RegDef:  CAN Enable MOb Register*/
+#define CANEN2 _SFR_MEM8(0xDC)
+
+/* RegDef:  CAN Enable MOb Register*/
+#define CANEN1 _SFR_MEM8(0xDD)
+
+/* Word Definition:  CAN Enable Interrupt MOb Register*/
+#define CANIE _SFR_MEM16(0xDE) 
+
+/* RegDef:  CAN Enable Interrupt MOb Register*/
+#define CANIE2 _SFR_MEM8(0xDE)
+
+/* RegDef:  CAN Enable Interrupt MOb Register*/
+#define CANIE1 _SFR_MEM8(0xDF)
+
+/* RegDef:  CAN Status Interrupt MOb Register*/
+/*
+ * WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT
+ * register.
+ */
+#define CANSIT  _SFR_MEM16(0xE0)
+#define CANSIT2 _SFR_MEM8(0xE0)
+#define CANSIT1 _SFR_MEM8(0xE1)
+
+/* RegDef:  CAN Bit Timing Register 1*/
+#define CANBT1 _SFR_MEM8(0xE2)
+
+/* RegDef:  CAN Bit Timing Register 2*/
+#define CANBT2 _SFR_MEM8(0xE3)
+
+/* RegDef:  CAN Bit Timing Register 3*/
+#define CANBT3 _SFR_MEM8(0xE4)
+
+/* RegDef:  CAN Timer Control Register*/
+#define CANTCON _SFR_MEM8(0xE5)
+
+/* RegDef:  CAN Timer Register*/
+#define CANTIM _SFR_MEM16(0xE6)
+#define CANTIML _SFR_MEM8(0xE6)
+#define CANTIMH _SFR_MEM8(0xE7)
+
+/* RegDef:  CAN TTC Timer Register*/
+#define CANTTC _SFR_MEM16(0xE8)
+#define CANTTCL _SFR_MEM8(0xE8)
+#define CANTTCH _SFR_MEM8(0xE9)
+
+/* RegDef:  CAN Transmitt Error Counter Register*/
+#define CANTEC _SFR_MEM8(0xEA)
+
+/* RegDef:  CAN Receive Error Counter Register*/
+#define CANREC _SFR_MEM8(0xEB)
+
+/* RegDef:  CAN Highest Priority MOb Register*/
+#define CANHPMOB _SFR_MEM8(0xEC)
+
+/* RegDef:  CAN Page MOb Register*/
+#define CANPAGE _SFR_MEM8(0xED)
+
+/* RegDef:  CAN MOb Status Register*/
+#define CANSTMOB _SFR_MEM8(0xEE)
+
+/* RegDef:  CAN MOb Control and DLC Register*/
+#define CANCDMOB _SFR_MEM8(0xEF)
+
+/* RegDef:  CAN Identifier Tag Registers*/
+#define CANIDT  _SFR_MEM32(0xF0)
+
+#define CANIDT4 _SFR_MEM8(0xF0)
+#define CANIDT3 _SFR_MEM8(0xF1)
+#define CANIDT2 _SFR_MEM8(0xF2)
+#define CANIDT1 _SFR_MEM8(0xF3)
+
+/* RegDef:  CAN Identifier Mask Registers */
+#define CANIDM  _SFR_MEM32(0xF4)
+
+#define CANIDM4 _SFR_MEM8(0xF4)
+#define CANIDM3 _SFR_MEM8(0xF5)
+#define CANIDM2 _SFR_MEM8(0xF6)
+#define CANIDM1 _SFR_MEM8(0xF7)
+
+/* RegDef:  CAN TTC Timer Register*/
+#define CANSTM _SFR_MEM16(0xF8)
+#define CANSTML _SFR_MEM8(0xF8)
+#define CANSTMH _SFR_MEM8(0xF9)
+
+/* RegDef:  CAN Message Register*/
+#define CANMSG _SFR_MEM8(0xFA)
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+#define SIG_INTERRUPT3			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+#define SIG_INTERRUPT4			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+#define SIG_INTERRUPT5			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num		7
+#define INT6_vect			_VECTOR(7)
+#define SIG_INTERRUPT6			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+#define SIG_INTERRUPT7			_VECTOR(8)
+
+/* Timer/Counter2 Compare Match */
+#define TIMER2_COMP_vect_num	9
+#define TIMER2_COMP_vect		_VECTOR(9)
+#define SIG_OUTPUT_COMPARE2		_VECTOR(9)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		10
+#define TIMER2_OVF_vect			_VECTOR(10)
+#define SIG_OVERFLOW2			_VECTOR(10)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	11
+#define TIMER1_CAPT_vect		_VECTOR(11)
+#define SIG_INPUT_CAPTURE1		_VECTOR(11)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	12
+#define TIMER1_COMPA_vect		_VECTOR(12)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
+
+/* Timer/Counter Compare Match B */
+#define TIMER1_COMPB_vect_num	13
+#define TIMER1_COMPB_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	14
+#define TIMER1_COMPC_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE1C		_VECTOR(14)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		15
+#define TIMER1_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW1			_VECTOR(15)
+
+/* Timer/Counter0 Compare Match */
+#define TIMER0_COMP_vect_num	16
+#define TIMER0_COMP_vect		_VECTOR(16)
+#define SIG_OUTPUT_COMPARE0		_VECTOR(16)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		17
+#define TIMER0_OVF_vect			_VECTOR(17)
+#define SIG_OVERFLOW0			_VECTOR(17)
+
+/* CAN Transfer Complete or Error */
+#define CANIT_vect_num		18
+#define CANIT_vect			_VECTOR(18)
+#define SIG_CAN_INTERRUPT1		_VECTOR(18)
+
+/* CAN Timer Overrun */
+#define OVRIT_vect_num		19
+#define OVRIT_vect			_VECTOR(19)
+#define SIG_CAN_OVERFLOW1		_VECTOR(19)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		20
+#define SPI_STC_vect			_VECTOR(20)
+#define SIG_SPI				_VECTOR(20)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		21
+#define USART0_RX_vect			_VECTOR(21)
+#define SIG_UART0_RECV			_VECTOR(21)
+#define SIG_USART0_RECV			_VECTOR(21)
+
+/* USART0 Data Register Empty */
+#define USART0_UDRE_vect_num	22
+#define USART0_UDRE_vect		_VECTOR(22)
+#define SIG_UART0_DATA			_VECTOR(22)
+#define SIG_USART0_DATA			_VECTOR(22)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		23
+#define USART0_TX_vect			_VECTOR(23)
+#define SIG_UART0_TRANS			_VECTOR(23)
+#define SIG_USART0_TRANS		_VECTOR(23)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	24
+#define ANALOG_COMP_vect		_VECTOR(24)
+#define SIG_COMPARATOR			_VECTOR(24)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		25
+#define ADC_vect			_VECTOR(25)
+#define SIG_ADC				_VECTOR(25)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		26
+#define EE_READY_vect			_VECTOR(26)
+#define SIG_EEPROM_READY		_VECTOR(26)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	27
+#define TIMER3_CAPT_vect		_VECTOR(27)
+#define SIG_INPUT_CAPTURE3		_VECTOR(27)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	28
+#define TIMER3_COMPA_vect		_VECTOR(28)
+#define SIG_OUTPUT_COMPARE3A		_VECTOR(28)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	29
+#define TIMER3_COMPB_vect		_VECTOR(29)
+#define SIG_OUTPUT_COMPARE3B		_VECTOR(29)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	30
+#define TIMER3_COMPC_vect		_VECTOR(30)
+#define SIG_OUTPUT_COMPARE3C		_VECTOR(30)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		31
+#define TIMER3_OVF_vect			_VECTOR(31)
+#define SIG_OVERFLOW3			_VECTOR(31)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		32
+#define USART1_RX_vect			_VECTOR(32)
+#define SIG_UART1_RECV			_VECTOR(32)
+#define SIG_USART1_RECV			_VECTOR(32)
+
+/* USART1, Data Register Empty */
+#define USART1_UDRE_vect_num	33
+#define USART1_UDRE_vect		_VECTOR(33)
+#define SIG_UART1_DATA			_VECTOR(33)
+#define SIG_USART1_DATA			_VECTOR(33)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		34
+#define USART1_TX_vect			_VECTOR(34)
+#define SIG_UART1_TRANS			_VECTOR(34)
+#define SIG_USART1_TRANS		_VECTOR(34)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num		35
+#define TWI_vect			_VECTOR(35)
+#define SIG_2WIRE_SERIAL		_VECTOR(35)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		36
+#define SPM_READY_vect			_VECTOR(36)
+#define SIG_SPM_READY			_VECTOR(36)
+
+#define _VECTORS_SIZE 148
+
+/* The Register Bit names are represented by their bit number (0-7). */
+
+/* Register Bits [ASSR]  */
+/* Asynchronous Status Register */
+#define    EXCLK      4
+#define    AS2        3
+#define    TCN2UB     2
+#define    OCR2UB     1
+#define    TCR2UB     0
+/* End Register Bits */
+
+/* Register Bits [TWCR] */
+/* 2-wire Control Register - TWCR */
+#define    TWINT        7
+#define    TWEA         6
+#define    TWSTA        5
+#define    TWSTO        4
+#define    TWWC         3
+#define    TWEN         2
+#define    TWIE         0
+/* End Register Bits */
+
+/* Register Bits [TWAR]  */
+/* 2-wire Address Register - TWAR */
+#define    TWA6         7
+#define    TWA5         6
+#define    TWA4         5
+#define    TWA3         4
+#define    TWA2         3
+#define    TWA1         2
+#define    TWA0         1
+#define    TWGCE        0
+/* End Register Bits */
+
+/* Register Bits [TWSR]  */
+/* 2-wire Status Register - TWSR */
+#define    TWS7         7
+#define    TWS6         6
+#define    TWS5         5
+#define    TWS4         4
+#define    TWS3         3
+#define    TWPS1        1
+#define    TWPS0        0
+/* End Register Bits */
+
+/* Register Bits [XMCRB]  */
+/* External Memory Control Register B - XMCRB */
+#define    XMBK         7
+#define    XMM2         2
+#define    XMM1         1
+#define    XMM0         0
+/* End Register Bits */
+
+/* Register Bits [XMCRA]  */
+/* External Memory Control Register A - XMCRA */
+#define    SRE         7
+#define    SRL2        6
+#define    SRL1        5
+#define    SRL0        4
+#define    SRW11       3
+#define    SRW10       2
+#define    SRW01       1
+#define    SRW00       0
+/* End Register Bits */
+
+/* Register Bits [RAMPZ]  */
+/* RAM Page Z select register - RAMPZ */
+#define     RAMPZ0      0
+/* End Register Bits */
+
+/* Register Bits [EICRA]  */
+/* External Interrupt Control Register A - EICRA */
+#define    ISC31        7
+#define    ISC30        6
+#define    ISC21        5
+#define    ISC20        4
+#define    ISC11        3
+#define    ISC10        2
+#define    ISC01        1
+#define    ISC00        0
+/* End Register Bits */
+
+/* Register Bits [EICRB]  */
+/* External Interrupt Control Register B - EICRB */
+#define    ISC71        7
+#define    ISC70        6
+#define    ISC61        5
+#define    ISC60        4
+#define    ISC51        3
+#define    ISC50        2
+#define    ISC41        1
+#define    ISC40        0
+/* End Register Bits */
+
+/* Register Bits [SPMCSR]  */
+/* Store Program Memory Control Register - SPMCSR, SPMCR */
+#define    SPMIE        7
+#define    RWWSB        6
+#define    RWWSRE       4
+#define    BLBSET       3
+#define    PGWRT        2
+#define    PGERS        1
+#define    SPMEN        0
+/* End Register Bits */
+
+/* Register Bits [EIMSK]  */
+/* External Interrupt MaSK register - EIMSK */
+#define    INT7         7
+#define    INT6         6
+#define    INT5         5
+#define    INT4         4
+#define    INT3         3
+#define    INT2         2
+#define    INT1         1
+#define    INT0         0
+/* End Register Bits */
+
+/* Register Bits [EIFR]  */
+/* External Interrupt Flag Register - EIFR */
+#define    INTF7        7
+#define    INTF6        6
+#define    INTF5        5
+#define    INTF4        4
+#define    INTF3        3
+#define    INTF2        2
+#define    INTF1        1
+#define    INTF0        0
+/* End Register Bits */
+
+/* Register Bits [TCCR2]  */
+/* Timer/Counter 2 Control Register - TCCR2 */
+#define    FOC2A        7
+#define    WGM20        6
+#define    COM2A1       5
+#define    COM2A0       4
+#define    WGM21        3
+#define    CS22         2
+#define    CS21         1
+#define    CS20         0
+/* End Register Bits */
+
+/* Register Bits [TCCR1A]  */
+/* Timer/Counter 1 Control and Status Register A - TCCR1A */
+#define    COM1A1       7
+#define    COM1A0       6
+#define    COM1B1       5
+#define    COM1B0       4
+#define    COM1C1       3
+#define    COM1C0       2
+#define    WGM11        1
+#define    WGM10        0
+/* End Register Bits */
+
+/* Register Bits [TCCR3A]  */
+/* Timer/Counter 3 Control and Status Register A - TCCR3A */
+#define    COM3A1       7
+#define    COM3A0       6
+#define    COM3B1       5
+#define    COM3B0       4
+#define    COM3C1       3
+#define    COM3C0       2
+#define    WGM31        1
+#define    WGM30        0
+/* End Register Bits */
+
+/* Register Bits [TCCR1B]  */
+/* Timer/Counter 1 Control and Status Register B - TCCR1B */
+#define    ICNC1        7
+#define    ICES1        6
+#define    WGM13        4
+#define    WGM12        3
+#define    CS12         2
+#define    CS11         1
+#define    CS10         0
+/* End Register Bits */
+
+/* Register Bits [TCCR3B]  */
+/* Timer/Counter 3 Control and Status Register B - TCCR3B */
+#define    ICNC3        7
+#define    ICES3        6
+#define    WGM33        4
+#define    WGM32        3
+#define    CS32         2
+#define    CS31         1
+#define    CS30         0
+/* End Register Bits */
+
+/* Register Bits [TCCR3C]  */
+/* Timer/Counter 3 Control Register C - TCCR3C */
+#define    FOC3A        7
+#define    FOC3B        6
+#define    FOC3C        5
+/* End Register Bits */
+
+/* Register Bits [TCCR1C]  */
+/* Timer/Counter 1 Control Register C - TCCR1C */
+#define    FOC1A        7
+#define    FOC1B        6
+#define    FOC1C        5
+/* End Register Bits */
+
+/* Register Bits [OCDR]  */
+/* On-chip Debug Register - OCDR */
+#define    IDRD         7
+#define    OCDR7        7
+#define    OCDR6        6
+#define    OCDR5        5
+#define    OCDR4        4
+#define    OCDR3        3
+#define    OCDR2        2
+#define    OCDR1        1
+#define    OCDR0        0
+/* End Register Bits */
+
+/* Register Bits [WDTCR]  */
+/* Watchdog Timer Control Register - WDTCR */
+#define    WDCE         4
+#define    WDE          3
+#define    WDP2         2
+#define    WDP1         1
+#define    WDP0         0
+/* End Register Bits */
+
+/* Register Bits [SPSR]  */
+/* SPI Status Register - SPSR */
+#define    SPIF         7
+#define    WCOL         6
+#define    SPI2X        0
+/* End Register Bits */
+
+/* Register Bits [SPCR]  */
+/* SPI Control Register - SPCR */
+#define    SPIE         7
+#define    SPE          6
+#define    DORD         5
+#define    MSTR         4
+#define    CPOL         3
+#define    CPHA         2
+#define    SPR1         1
+#define    SPR0         0
+/* End Register Bits */
+
+/* Register Bits [UCSR1C]  */
+/* USART1 Register C - UCSR1C */
+#define    UMSEL1       6
+#define    UPM11        5
+#define    UPM10        4
+#define    USBS1        3
+#define    UCSZ11       2
+#define    UCSZ10       1
+#define    UCPOL1       0
+/* End Register Bits */
+
+/* Register Bits [UCSR0C]  */
+/* USART0 Register C - UCSR0C */
+#define    UMSEL0       6
+#define    UPM01        5
+#define    UPM00        4
+#define    USBS0        3
+#define    UCSZ01       2
+#define    UCSZ00       1
+#define    UCPOL0       0
+/* End Register Bits */
+
+/* Register Bits [UCSR1A]  */
+/* USART1 Status Register A - UCSR1A */
+#define    RXC1         7
+#define    TXC1         6
+#define    UDRE1        5
+#define    FE1          4
+#define    DOR1         3
+#define    UPE1         2
+#define    U2X1         1
+#define    MPCM1        0
+/* End Register Bits */
+
+/* Register Bits [UCSR0A]  */
+/* USART0 Status Register A - UCSR0A */
+#define    RXC0         7
+#define    TXC0         6
+#define    UDRE0        5
+#define    FE0          4
+#define    DOR0         3
+#define    UPE0         2
+#define    U2X0         1
+#define    MPCM0        0
+/* End Register Bits */
+
+/* Register Bits [UCSR1B]  */
+/* USART1 Control Register B - UCSR1B */
+#define    RXCIE1       7
+#define    TXCIE1       6
+#define    UDRIE1       5
+#define    RXEN1        4
+#define    TXEN1        3
+#define    UCSZ12       2
+#define    RXB81        1
+#define    TXB81        0
+/* End Register Bits */
+
+/* Register Bits [UCSR0B]  */
+/* USART0 Control Register B - UCSR0B */
+#define    RXCIE0       7
+#define    TXCIE0       6
+#define    UDRIE0       5
+#define    RXEN0        4
+#define    TXEN0        3
+#define    UCSZ02       2
+#define    RXB80        1
+#define    TXB80        0
+/* End Register Bits */
+
+/* Register Bits [ACSR]  */
+/* Analog Comparator Control and Status Register - ACSR */
+#define    ACD          7
+#define    ACBG         6
+#define    ACO          5
+#define    ACI          4
+#define    ACIE         3
+#define    ACIC         2
+#define    ACIS1        1
+#define    ACIS0        0
+/* End Register Bits */
+
+/* Register Bits [ADCSRA]  */
+/* ADC Control and status register - ADCSRA */
+#define    ADEN         7
+#define    ADSC         6
+#define    ADATE        5
+#define    ADIF         4
+#define    ADIE         3
+#define    ADPS2        2
+#define    ADPS1        1
+#define    ADPS0        0
+/* End Register Bits */
+
+/* 
+   The ADHSM bit has been removed from all documentation, 
+   as being not needed at all since the comparator has proven 
+   to be fast enough even without feeding it more power.
+*/
+
+/* Register Bits [ADCSRB]  */
+/* ADC Control and status register - ADCSRB */
+#define    ACME         6
+#define    ADTS2        2
+#define    ADTS1        1
+#define    ADTS0        0
+/* End Register Bits */
+
+/* Register Bits [ADMUX]  */
+/* ADC Multiplexer select - ADMUX */
+#define    REFS1        7
+#define    REFS0        6
+#define    ADLAR        5
+#define    MUX4         4
+#define    MUX3         3
+#define    MUX2         2
+#define    MUX1         1
+#define    MUX0         0
+/* End Register Bits */
+
+/* Register Bits [DIDR0]  */
+/* Digital Input Disable Register 0 */
+#define    ADC7D        7
+#define    ADC6D        6
+#define    ADC5D        5
+#define    ADC4D        4
+#define    ADC3D        3
+#define    ADC2D        2
+#define    ADC1D        1
+#define    ADC0D        0
+/* End Register Bits */
+
+/* Register Bits [DIDR1]  */
+/* Digital Input Disable Register 1 */
+#define    AIN1D        1
+#define    AIN0D        0
+/* End Register Bits */
+
+/* Register Bits [PORTA]  */
+/* Port A Data Register - PORTA */
+#define    PA7          7
+#define    PA6          6
+#define    PA5          5
+#define    PA4          4
+#define    PA3          3
+#define    PA2          2
+#define    PA1          1
+#define    PA0          0
+/* End Register Bits */
+
+/* Register Bits [DDRA]  */
+/* Port A Data Direction Register - DDRA */
+#define    DDA7         7
+#define    DDA6         6
+#define    DDA5         5
+#define    DDA4         4
+#define    DDA3         3
+#define    DDA2         2
+#define    DDA1         1
+#define    DDA0         0
+/* End Register Bits */
+
+/* Register Bits [PINA]  */
+/* Port A Input Pins - PINA */
+#define    PINA7        7
+#define    PINA6        6
+#define    PINA5        5
+#define    PINA4        4
+#define    PINA3        3
+#define    PINA2        2
+#define    PINA1        1
+#define    PINA0        0
+/* End Register Bits */
+
+/* Register Bits [PORTB]  */
+/* Port B Data Register - PORTB */
+#define    PB7          7
+#define    PB6          6
+#define    PB5          5
+#define    PB4          4
+#define    PB3          3
+#define    PB2          2
+#define    PB1          1
+#define    PB0          0
+/* End Register Bits */
+
+/* Register Bits [DDRB]  */
+/* Port B Data Direction Register - DDRB */
+#define    DDB7         7
+#define    DDB6         6
+#define    DDB5         5
+#define    DDB4         4
+#define    DDB3         3
+#define    DDB2         2
+#define    DDB1         1
+#define    DDB0         0
+/* End Register Bits */
+
+/* Register Bits [PINB]  */
+/* Port B Input Pins - PINB */
+#define    PINB7        7
+#define    PINB6        6
+#define    PINB5        5
+#define    PINB4        4
+#define    PINB3        3
+#define    PINB2        2
+#define    PINB1        1
+#define    PINB0        0
+/* End Register Bits */
+
+/* Register Bits [PORTC]  */
+/* Port C Data Register - PORTC */
+#define    PC7          7
+#define    PC6          6
+#define    PC5          5
+#define    PC4          4
+#define    PC3          3
+#define    PC2          2
+#define    PC1          1
+#define    PC0          0
+/* End Register Bits */
+
+/* Register Bits [DDRC]  */
+/* Port C Data Direction Register - DDRC */
+#define    DDC7         7
+#define    DDC6         6
+#define    DDC5         5
+#define    DDC4         4
+#define    DDC3         3
+#define    DDC2         2
+#define    DDC1         1
+#define    DDC0         0
+/* End Register Bits */
+
+/* Register Bits [PINC]  */
+/* Port C Input Pins - PINC */
+#define    PINC7        7
+#define    PINC6        6
+#define    PINC5        5
+#define    PINC4        4
+#define    PINC3        3
+#define    PINC2        2
+#define    PINC1        1
+#define    PINC0        0
+/* End Register Bits */
+
+/* Register Bits [PORTD]  */
+/* Port D Data Register - PORTD */
+#define    PD7          7
+#define    PD6          6
+#define    PD5          5
+#define    PD4          4
+#define    PD3          3
+#define    PD2          2
+#define    PD1          1
+#define    PD0          0
+/* End Register Bits */
+
+/* Register Bits [DDRD]  */
+/* Port D Data Direction Register - DDRD */
+#define    DDD7         7
+#define    DDD6         6
+#define    DDD5         5
+#define    DDD4         4
+#define    DDD3         3
+#define    DDD2         2
+#define    DDD1         1
+#define    DDD0         0
+/* End Register Bits */
+
+/* Register Bits [PIND]  */
+/* Port D Input Pins - PIND */
+#define    PIND7        7
+#define    PIND6        6
+#define    PIND5        5
+#define    PIND4        4
+#define    PIND3        3
+#define    PIND2        2
+#define    PIND1        1
+#define    PIND0        0
+/* End Register Bits */
+
+/* Register Bits [PORTE]  */
+/* Port E Data Register - PORTE */
+#define    PE7          7
+#define    PE6          6
+#define    PE5          5
+#define    PE4          4
+#define    PE3          3
+#define    PE2          2
+#define    PE1          1
+#define    PE0          0
+/* End Register Bits */
+
+/* Register Bits [DDRE]  */
+/* Port E Data Direction Register - DDRE */
+#define    DDE7         7
+#define    DDE6         6
+#define    DDE5         5
+#define    DDE4         4
+#define    DDE3         3
+#define    DDE2         2
+#define    DDE1         1
+#define    DDE0         0
+/* End Register Bits */
+
+/* Register Bits [PINE]  */
+/* Port E Input Pins - PINE */
+#define    PINE7        7
+#define    PINE6        6
+#define    PINE5        5
+#define    PINE4        4
+#define    PINE3        3
+#define    PINE2        2
+#define    PINE1        1
+#define    PINE0        0
+/* End Register Bits */
+
+/* Register Bits [PORTF]  */
+/* Port F Data Register - PORTF */
+#define    PF7          7
+#define    PF6          6
+#define    PF5          5
+#define    PF4          4
+#define    PF3          3
+#define    PF2          2
+#define    PF1          1
+#define    PF0          0
+/* End Register Bits */
+
+/* Register Bits [DDRF]  */
+/* Port F Data Direction Register - DDRF */
+#define    DDF7         7
+#define    DDF6         6
+#define    DDF5         5
+#define    DDF4         4
+#define    DDF3         3
+#define    DDF2         2
+#define    DDF1         1
+#define    DDF0         0
+/* End Register Bits */
+
+/* Register Bits [PINF]  */
+/* Port F Input Pins - PINF */
+#define    PINF7        7
+#define    PINF6        6
+#define    PINF5        5
+#define    PINF4        4
+#define    PINF3        3
+#define    PINF2        2
+#define    PINF1        1
+#define    PINF0        0
+/* End Register Bits */
+
+/* Register Bits [PORTG]  */
+/* Port G Data Register - PORTG */
+#define    PG4          4
+#define    PG3          3
+#define    PG2          2
+#define    PG1          1
+#define    PG0          0
+/* End Register Bits */
+
+/* Register Bits [DDRG]  */
+/* Port G Data Direction Register - DDRG */
+#define    DDG4         4
+#define    DDG3         3
+#define    DDG2         2
+#define    DDG1         1
+#define    DDG0         0
+/* End Register Bits */
+
+/* Register Bits [PING]  */
+/* Port G Input Pins - PING */
+#define    PING4        4
+#define    PING3        3
+#define    PING2        2
+#define    PING1        1
+#define    PING0        0
+/* End Register Bits */
+
+
+/* Register Bits [TIFR0]  */
+/* Timer/Counter 0 interrupt Flag Register */
+#define    OCF0A        1
+#define    TOV0         0
+/* End Register Bits */
+
+/* Register Bits [TIFR1]  */
+/* Timer/Counter 1 interrupt Flag Register */
+#define    ICF1       5
+#define    OCF1C      3
+#define    OCF1B      2
+#define    OCF1A      1
+#define    TOV1       0
+/* End Register Bits */
+
+/* Register Bits [TIFR2]  */
+/* Timer/Counter 2 interrupt Flag Register */
+#define    OCF2A      1
+#define    TOV2       0
+/* End Register Bits */
+
+/* Register Bits [TIFR3]  */
+/* Timer/Counter 3 interrupt Flag Register */
+#define    ICF3       5
+#define    OCF3C      3
+#define    OCF3B      2
+#define    OCF3A      1
+#define    TOV3       0
+/* End Register Bits */
+
+/* Register Bits [GPIOR0]  */
+/* General Purpose I/O Register 0 */
+#define    GPIOR07     7
+#define    GPIOR06     6
+#define    GPIOR05     5
+#define    GPIOR04     4
+#define    GPIOR03     3
+#define    GPIOR02     2
+#define    GPIOR01     1
+#define    GPIOR00     0
+/* End Register Bits */
+
+/* Register Bits [GPIOR1]  */
+/* General Purpose I/O Register 1 */
+#define    GPIOR17     7
+#define    GPIOR16     6
+#define    GPIOR15     5
+#define    GPIOR14     4
+#define    GPIOR13     3
+#define    GPIOR12     2
+#define    GPIOR11     1
+#define    GPIOR10     0
+/* End Register Bits */
+
+/* Register Bits [GPIOR2]  */
+/* General Purpose I/O Register 2 */
+#define    GPIOR27     7
+#define    GPIOR26     6
+#define    GPIOR25     5
+#define    GPIOR24     4
+#define    GPIOR23     3
+#define    GPIOR22     2
+#define    GPIOR21     1
+#define    GPIOR20     0
+/* End Register Bits */
+
+/* Register Bits [EECR]  */
+/* EEPROM Control Register */
+#define    EERIE       3
+#define    EEMWE       2
+#define    EEWE        1
+#define    EERE        0
+/* End Register Bits */
+
+/* Register Bits [EEDR]  */
+/* EEPROM Data Register */
+#define    EEDR7     7
+#define    EEDR6     6
+#define    EEDR5     5
+#define    EEDR4     4
+#define    EEDR3     3
+#define    EEDR2     2
+#define    EEDR1     1
+#define    EEDR0     0
+/* End Register Bits */
+
+/* Register Bits [EEARL]  */
+/* EEPROM Address Register */
+#define    EEAR7     7
+#define    EEAR6     6
+#define    EEAR5     5
+#define    EEAR4     4
+#define    EEAR3     3
+#define    EEAR2     2
+#define    EEAR1     1
+#define    EEAR0     0
+/* End Register Bits */
+
+/* Register Bits [EEARH]  */
+/* EEPROM Address Register */
+#define    EEAR11    3
+#define    EEAR10    2
+#define    EEAR9     1
+#define    EEAR8     0
+/* End Register Bits */
+
+/* Register Bits [GTCCR]  */
+/* General Timer/Counter Control Register  */
+#define    TSM      7
+#define    PSR2     1
+#define    PSR310   0
+/* End Register Bits */
+
+/* Register Bits [TCCR0A]  */
+/* Timer/Counter Control Register A */
+/* ALSO COVERED IN GENERIC SECTION */
+#define    FOC0A    7
+#define    WGM00    6
+#define    COM0A1   5
+#define    COM0A0   4
+#define    WGM01    3
+#define    CS02     2
+#define    CS01     1
+#define    CS00     0
+/* End Register Bits */
+
+/* Register Bits [OCR0A]  */
+/* Output Compare Register A */
+#define    OCR0A7     7
+#define    OCR0A6     6
+#define    OCR0A5     5
+#define    OCR0A4     4
+#define    OCR0A3     3
+#define    OCR0A2     2
+#define    OCR0A1     1
+#define    OCR0A0     0
+/* End Register Bits */
+
+
+/* Register Bits [SPIDR]  */
+/* SPI Data Register */
+#define    SPD7     7
+#define    SPD6     6
+#define    SPD5     5
+#define    SPD4     4
+#define    SPD3     3
+#define    SPD2     2
+#define    SPD1     1
+#define    SPD0     0
+/* End Register Bits */
+
+/* Register Bits [SMCR]  */
+/* Sleep Mode Control Register */
+#define    SM2     3
+#define    SM1     2
+#define    SM0     1
+#define    SE      0
+/* End Register Bits */
+
+/* Register Bits [MCUSR]  */
+/* MCU Status Register */
+#define    JTRF    4
+#define    WDRF    3
+#define    BORF    2
+#define    EXTRF   1
+#define    PORF    0
+/* End Register Bits */
+
+/* Register Bits [MCUCR]  */
+/* MCU Control Register */
+#define    JTD     7
+#define    PUD     4
+#define    IVSEL   1
+#define    IVCE    0
+/* End Register Bits */
+
+/* Register Bits [CLKPR]  */
+/* Clock Prescale Register */
+#define    CLKPCE     7
+#define    CLKPS3     3
+#define    CLKPS2     2
+#define    CLKPS1     1
+#define    CLKPS0     0
+/* End Register Bits */
+
+/* Register Bits [OSCCAL]  */
+/* Oscillator Calibration Register */
+#define    CAL6     6
+#define    CAL5     5
+#define    CAL4     4
+#define    CAL3     3
+#define    CAL2     2
+#define    CAL1     1
+#define    CAL0     0
+/* End Register Bits */
+
+/* Register Bits [TIMSK0]  */
+/* Timer/Counter 0 interrupt mask Register */
+#define    OCIE0A      1
+#define    TOIE0       0
+/* End Register Bits */
+
+/* Register Bits [TIMSK1]  */
+/* Timer/Counter 1 interrupt mask Register */
+#define    ICIE1       5
+#define    OCIE1C      3
+#define    OCIE1B      2
+#define    OCIE1A      1
+#define    TOIE1       0
+/* End Register Bits */
+
+/* Register Bits [TIMSK2]  */
+/* Timer/Counter 2 interrupt mask Register */
+#define    OCIE2A      1
+#define    TOIE2       0
+/* End Register Bits */
+
+/* Register Bits [TIMSK3]  */
+/* Timer/Counter 3 interrupt mask Register */
+#define    ICIE3       5
+#define    OCIE3C      3
+#define    OCIE3B      2
+#define    OCIE3A      1
+#define    TOIE3       0
+/* End Register Bits */
+
+//Begin CAN specific parts
+
+/* Register Bits [CANGCON]  */
+/* CAN General Control Register */
+#define    ABRQ       7
+#define    OVRQ       6
+#define    TTC        5
+#define    SYNTTC     4
+#define    LISTEN     3
+#define    TEST       2
+#define    ENASTB     1
+#define    SWRES      0
+/* End Register Bits */
+
+/* Register Bits [CANGSTA]  */
+/* CAN General Status Register */
+#define    OVFG       6
+#define    OVRG       6
+#define    TXBSY      4
+#define    RXBSY      3
+#define    ENFG       2
+#define    BOFF       1
+#define    ERRP       0
+/* End Register Bits */
+
+/* Register Bits [CANGIT]  */
+/* CAN General Interrupt Register */
+#define    CANIT      7
+#define    BOFFIT     6
+#define    OVRTIM     5
+#define    BXOK       4
+#define    SERG       3
+#define    CERG       2
+#define    FERG       1
+#define    AERG       0
+/* End Register Bits */
+
+/* Register Bits [CANGIE]  */
+/* CAN General Interrupt Enable */
+#define    ENIT        7
+#define    ENBOFF      6
+#define    ENRX        5
+#define    ENTX        4
+#define    ENERR       3
+#define    ENBX        2
+#define    ENERG       1
+#define    ENOVRT      0
+/* End Register Bits */
+
+/* Register Bits [CANEN2]  */
+/* CAN Enable MOb Register */
+#define    ENMOB7      7
+#define    ENMOB6      6
+#define    ENMOB5      5
+#define    ENMOB4      4
+#define    ENMOB3      3
+#define    ENMOB2      2
+#define    ENMOB1      1
+#define    ENMOB0      0
+/* End Register Bits */
+
+/* Register Bits [CANEN1]  */
+/* CAN Enable MOb Register */
+#define    ENMOB14      6
+#define    ENMOB13      5
+#define    ENMOB12      4
+#define    ENMOB11      3
+#define    ENMOB10      2
+#define    ENMOB9       1
+#define    ENMOB8       0
+/* End Register Bits */
+
+/* Register Bits [CANIE2]  */
+/* CAN Interrupt Enable MOb Register */
+#define    IEMOB7      7
+#define    IEMOB6      6
+#define    IEMOB5      5
+#define    IEMOB4      4
+#define    IEMOB3      3
+#define    IEMOB2      2
+#define    IEMOB1      1
+#define    IEMOB0      0
+/* End Register Bits */
+
+/* Register Bits [CANIE1]  */
+/* CAN Interrupt Enable MOb Register */
+#define    IEMOB14      6
+#define    IEMOB13      5
+#define    IEMOB12      4
+#define    IEMOB11      3
+#define    IEMOB10      2
+#define    IEMOB9       1
+#define    IEMOB8       0
+/* End Register Bits */
+
+/* Register Bits [CANSIT2]  */
+/* CAN Status Interrupt MOb Register */
+#define    SIT7      7
+#define    SIT6      6
+#define    SIT5      5
+#define    SIT4      4
+#define    SIT3      3
+#define    SIT2      2
+#define    SIT1      1
+#define    SIT0      0
+/* End Register Bits */
+
+/* Register Bits [CANSIT1]  */
+/* CAN Status Interrupt MOb Register */
+#define    SIT14      6
+#define    SIT13      5
+#define    SIT12      4
+#define    SIT11      3
+#define    SIT10      2
+#define    SIT9       1
+#define    SIT8       0
+/* End Register Bits */
+
+/* Register Bits [CANBT1]  */
+/* Bit Timing Register 1 */
+#define    BRP5       6
+#define    BRP4       5
+#define    BRP3       4
+#define    BRP2       3
+#define    BRP1       2
+#define    BRP0       1
+/* End Register Bits */
+
+/* Register Bits [CANBT2]  */
+/* Bit Timing Register 2 */
+#define    SJW1       6
+#define    SJW0       5
+#define    PRS2       3
+#define    PRS1       2
+#define    PRS0       1
+/* End Register Bits */
+
+/* Register Bits [CANBT3]  */
+/* Bit Timing Register 3 */
+#define    PHS22      6
+#define    PHS21      5
+#define    PHS20      4
+#define    PHS12      3
+#define    PHS11      2
+#define    PHS10      1
+#define    SMP        0
+/* End Register Bits */
+
+/* Register Bits [CANTCON]  */
+/* CAN Timer Control Register */
+#define    TPRSC7      7
+#define    TPRSC6      6
+#define    TPRSC5      5
+#define    TPRSC4      4
+#define    TPRSC3      3
+#define    TPRSC2      2
+#define    TPRSC1      1
+#define    TPRSC0      0
+/* End Register Bits */
+
+/* Register Bits [CANTIML]  */
+/* CAN Timer Register Low */
+#define    CANTIM7      7
+#define    CANTIM6      6
+#define    CANTIM5      5
+#define    CANTIM4      4
+#define    CANTIM3      3
+#define    CANTIM2      2
+#define    CANTIM1      1
+#define    CANTIM0      0
+/* End Register Bits */
+
+/* Register Bits [CANTIMH]  */
+/* CAN Timer Register High */
+#define    CANTIM15     7
+#define    CANTIM14     6
+#define    CANTIM13     5
+#define    CANTIM12     4
+#define    CANTIM11     3
+#define    CANTIM10     2
+#define    CANTIM9      1
+#define    CANTIM8      0
+/* End Register Bits */
+
+/* Register Bits [CANTTCL]  */
+/* CAN TTC Timer Register Low */
+#define    TIMTTC7      7
+#define    TIMTTC6      6
+#define    TIMTTC5      5
+#define    TIMTTC4      4
+#define    TIMTTC3      3
+#define    TIMTTC2      2
+#define    TIMTTC1      1
+#define    TIMTTC0      0
+/* End Register Bits */
+
+/* Register Bits [CANTTCH]  */
+/* CAN TTC Timer Register High */
+#define    TIMTTC15     7
+#define    TIMTTC14     6
+#define    TIMTTC13     5
+#define    TIMTTC12     4
+#define    TIMTTC11     3
+#define    TIMTTC10     2
+#define    TIMTTC9      1
+#define    TIMTTC8      0
+/* End Register Bits */
+
+/* Register Bits [CANTEC]  */
+/* CAN Transmitt Error Counter */
+#define    TEC7      7
+#define    TEC6      6
+#define    TEC5      5
+#define    TEC4      4
+#define    TEC3      3
+#define    TEC2      2
+#define    TEC1      1
+#define    TEC0      0
+/* End Register Bits */
+
+/* Register Bits [CANREC]  */
+/* CAN Receive Error Counter */
+#define    REC7      7
+#define    REC6      6
+#define    REC5      5
+#define    REC4      4
+#define    REC3      3
+#define    REC2      2
+#define    REC1      1
+#define    REC0      0
+/* End Register Bits */
+
+/* Register Bits [CANHPMOB]  */
+/* Highest Priority MOb */
+#define    HPMOB3     7
+#define    HPMOB2     6
+#define    HPMOB1     5
+#define    HPMOB0     4
+#define    CGP3       3
+#define    CGP2       2
+#define    CGP1       1
+#define    CGP0       0
+/* End Register Bits */
+
+/* Register Bits [CANPAGE]  */
+/* CAN Page MOb Register */
+#define    MOBNB3     7
+#define    MOBNB2     6
+#define    MOBNB1     5
+#define    MOBNB0     4
+#define    AINC       3
+#define    INDX2      2
+#define    INDX1      1
+#define    INDX0      0
+/* End Register Bits */
+
+/* Register Bits [CANSTMOB]  */
+/* CAN MOb Status Register */
+#define    DLCW       7
+#define    TXOK       6
+#define    RXOK       5
+#define    BERR       4
+#define    SERR       3
+#define    CERR       2
+#define    FERR       1
+#define    AERR       0
+/* End Register Bits */
+
+/* Register Bits [CANCDMOB]  */
+/* CAN MOb Control and DLC Register */
+#define    CONMOB1    7
+#define    CONMOB0    6
+#define    RPLV       5
+#define    IDE        4
+#define    DLC3       3
+#define    DLC2       2
+#define    DLC1       1
+#define    DLC0       0
+/* End Register Bits */
+
+/* Register Bits [CANIDT4]  */
+/* CAN Identifier Tag Register 4 */
+#define    IDT4       7
+#define    IDT3       6
+#define    IDT2       5
+#define    IDT1       4
+#define    IDT0       3
+#define    RTRTAG     2
+#define    RB1TAG     1
+#define    RB0TAG     0
+/* End Register Bits */
+
+/* Register Bits [CANIDT3]  */
+/* CAN Identifier Tag Register 3 */
+#define    IDT12      7
+#define    IDT11      6
+#define    IDT10      5
+#define    IDT9       4
+#define    IDT8       3
+#define    IDT7       2
+#define    IDT6       1
+#define    IDT5       0
+/* End Register Bits */
+
+/* Register Bits [CANIDT2]  */
+/* CAN Identifier Tag Register 2 */
+#define    IDT20      7
+#define    IDT19      6
+#define    IDT18      5
+#define    IDT17      4
+#define    IDT16      3
+#define    IDT15      2
+#define    IDT14      1
+#define    IDT13      0
+/* End Register Bits */
+
+/* Register Bits [CANIDT1]  */
+/* CAN Identifier Tag Register 1 */
+#define    IDT28      7
+#define    IDT27      6
+#define    IDT26      5
+#define    IDT25      4
+#define    IDT24      3
+#define    IDT23      2
+#define    IDT22      1
+#define    IDT21      0
+/* End Register Bits */
+
+/* Register Bits [CANIDM4]  */
+/* CAN Identifier Mask Register 4 */
+#define    IDMSK4       7
+#define    IDMSK3       6
+#define    IDMSK2       5
+#define    IDMSK1       4
+#define    IDMSK0       3
+#define    RTRMSK       2
+#define    IDEMSK       0
+/* End Register Bits */
+
+/* Register Bits [CANIDM3]  */
+/* CAN Identifier Mask Register 3 */
+#define    IDMSK12      7
+#define    IDMSK11      6
+#define    IDMSK10      5
+#define    IDMSK9       4
+#define    IDMSK8       3
+#define    IDMSK7       2
+#define    IDMSK6       1
+#define    IDMSK5       0
+/* End Register Bits */
+
+/* Register Bits [CANIDM2]  */
+/* CAN Identifier Mask Register 2 */
+#define    IDMSK20      7
+#define    IDMSK19      6
+#define    IDMSK18      5
+#define    IDMSK17      4
+#define    IDMSK16      3
+#define    IDMSK15      2
+#define    IDMSK14      1
+#define    IDMSK13      0
+/* End Register Bits */
+
+/* Register Bits [CANIDM1]  */
+/* CAN Identifier Mask Register 1 */
+#define    IDMSK28      7
+#define    IDMSK27      6
+#define    IDMSK26      5
+#define    IDMSK25      4
+#define    IDMSK24      3
+#define    IDMSK23      2
+#define    IDMSK22      1
+#define    IDMSK21      0
+/* End Register Bits */
+
+/* Register Bits [CANSTML]  */
+/* CAN Timer Register of some sort, low*/
+#define    TIMSTM7       7
+#define    TIMSTM6       6
+#define    TIMSTM5       5
+#define    TIMSTM4       4
+#define    TIMSTM3       3
+#define    TIMSTM2       2
+#define    TIMSTM1       1
+#define    TIMSTM0       0
+/* End Register Bits */
+
+/* Register Bits [CANSTMH]  */
+/* CAN Timer Register of some sort, high */
+#define    TIMSTM15       7
+#define    TIMSTM14       6
+#define    TIMSTM13       5
+#define    TIMSTM12       4
+#define    TIMSTM11       3
+#define    TIMSTM10       2
+#define    TIMSTM9        1
+#define    TIMSTM8        0
+/* End Register Bits */
+
+/* Register Bits [CANMSG]  */
+/* CAN Message Register */
+#define    MSG7           7
+#define    MSG6           6
+#define    MSG5           5
+#define    MSG4           4
+#define    MSG3           3
+#define    MSG2           2
+#define    MSG1           1
+#define    MSG0           0
+/* End Register Bits */
+
+/* Begin Verbatim */
+
+/* Timer/Counter Control Register (generic) */
+#define    FOC          7
+#define    WGM0         6
+#define    COM1         5
+#define    COM0         4
+#define    WGM1         3
+#define    CS2          2
+#define    CS1          1
+#define    CS0          0
+
+/* Timer/Counter Control Register A (generic) */
+#define    COMA1        7
+#define    COMA0        6
+#define    COMB1        5
+#define    COMB0        4
+#define    COMC1        3
+#define    COMC0        2
+#define    WGMA1        1
+#define    WGMA0        0
+
+/* Timer/Counter Control and Status Register B (generic) */
+#define    ICNC         7
+#define    ICES         6
+#define    WGMB3        4
+#define    WGMB2        3
+#define    CSB2         2
+#define    CSB1         1
+#define    CSB0         0
+
+/* Timer/Counter Control Register C (generic) */
+#define    FOCA         7
+#define    FOCB         6
+#define    FOCC         5
+
+/* Port Data Register (generic) */
+#define    PORT7        7
+#define    PORT6        6
+#define    PORT5        5
+#define    PORT4        4
+#define    PORT3        3
+#define    PORT2        2
+#define    PORT1        1
+#define    PORT0        0
+
+/* Port Data Direction Register (generic) */
+#define    DD7          7
+#define    DD6          6
+#define    DD5          5
+#define    DD4          4
+#define    DD3          3
+#define    DD2          2
+#define    DD1          1
+#define    DD0          0
+
+/* Port Input Pins (generic) */
+#define    PIN7         7
+#define    PIN6         6
+#define    PIN5         5
+#define    PIN4         4
+#define    PIN3         3
+#define    PIN2         2
+#define    PIN1         1
+#define    PIN0         0
+
+/* USART Status Register A (generic) */
+#define    RXC          7
+#define    TXC          6
+#define    UDRE         5
+#define    FE           4
+#define    DOR          3
+#define    UPE          2
+#define    U2X          1
+#define    MPCM         0
+
+/* USART Control Register B (generic) */
+#define    RXCIE        7
+#define    TXCIE        6
+#define    UDRIE        5
+#define    RXEN         4
+#define    TXEN         3
+#define    UCSZ         2
+#define    UCSZ2        2       /* new name in datasheet (2467E-AVR-05/02) */
+#define    RXB8         1
+#define    TXB8         0
+
+/* USART Register C (generic) */
+#define    UMSEL        6
+#define    UPM1         5
+#define    UPM0         4
+#define    USBS         3
+#define    UCSZ1        2
+#define    UCSZ0        1
+#define    UCPOL        0
+
+/* End Verbatim */
 
 /* Constants */
 #define SPM_PAGESIZE 256
@@ -91,12 +2052,10 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x81
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif  /* _AVR_IOCAN64_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom103.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom103.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom103.h 2227 2011-03-04 19:35:10Z arcanum $ */
 
 /* avr/iom103.h - definitions for ATmega103 */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom128.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom128.h
@@ -29,7 +29,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom128.h 2226 2011-03-04 17:47:16Z arcanum $ */
 
 /* avr/iom128.h - defines for ATmega128 
 
@@ -1289,8 +1289,6 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
-
 #define SLEEP_MODE_IDLE (0x00<<2)
 #define SLEEP_MODE_ADC (0x02<<2)
 #define SLEEP_MODE_PWR_DOWN (0x04<<2)
@@ -1298,5 +1296,4 @@
 #define SLEEP_MODE_STANDBY (0x05<<2)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<2)
 
-
 #endif /* _AVR_IOM128_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom1280.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom1280.h
@@ -28,14 +28,1615 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom1280.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* avr/iom1280.h - definitions for ATmega1280 */
 
 #ifndef _AVR_IOM1280_H_
 #define _AVR_IOM1280_H_ 1
 
-#include <avr/iomxx0_1.h>
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iomxx0_1.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0X01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0X02)
+#define PA7     7
+#define PA6     6
+#define PA5     5
+#define PA4     4
+#define PA3     3
+#define PA2     2
+#define PA1     1
+#define PA0     0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7     7
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC3     3
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7     7
+#define PE6     6
+#define PE5     5
+#define PE4     4
+#define PE3     3
+#define PE2     2
+#define PE1     1
+#define PE0     0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7     7
+#define PF6     6
+#define PF5     5
+#define PF4     4
+#define PF3     3
+#define PF2     2
+#define PF1     1
+#define PF0     0
+
+#define PING    _SFR_IO8(0x12)
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDG5    5
+#define DDG4    4
+#define DDG3    3
+#define DDG2    2
+#define DDG1    1
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PG5     5
+#define PG4     4
+#define PG3     3
+#define PG2     2
+#define PG1     1
+#define PG0     0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8(0x17)
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define TIFR3   _SFR_IO8(0x18)
+#define ICF3    5
+#define OCF3C   3
+#define OCF3B   2
+#define OCF3A   1
+#define TOV3    0
+
+#define TIFR4   _SFR_IO8(0x19)
+#define ICF4    5
+#define OCF4C   3
+#define OCF4B   2
+#define OCF4A   1
+#define TOV4    0
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define ICF5    5
+#define OCF5C   3
+#define OCF5B   2
+#define OCF5A   1
+#define TOV5    0
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF2  2
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR   _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0X27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0X2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8(0x31)
+#define OCDR    _SFR_IO8(0x31)
+#define IDRD    7
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0X35)
+#define JTD     7
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0X3B)
+#define RAMPZ0  0
+
+#define EIND    _SFR_IO8(0X3C)
+#define EIND0   0
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTWI       7
+#define PRTIM2      6
+#define PRTIM0      5
+#define PRTIM1      3
+#define PRSPI       2
+#define PRUSART0    1
+#define PRADC       0
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRUSART0
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRTIM5      5
+#define PRTIM4      4
+#define PRTIM3      3
+#define PRUSART3    2
+#define PRUSART2    1
+#define PRUSART1    0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRUSART2)|(1<<PRUSART3)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRUSART2
+#define __AVR_HAVE_PRR1_PRUSART3
+#define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRTIM4
+#define __AVR_HAVE_PRR1_PRTIM5
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE2  2
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+#define PCMSK2 _SFR_MEM8(0x6D)
+#define PCINT23 7
+#define PCINT22 6
+#define PCINT21 5
+#define PCINT20 4
+#define PCINT19 3
+#define PCINT18 2
+#define PCINT17 1
+#define PCINT16 0
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define ICIE3   5
+#define OCIE3C  3
+#define OCIE3B  2
+#define OCIE3A  1
+#define TOIE3   0
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define ICIE4   5
+#define OCIE4C  3
+#define OCIE4B  2
+#define OCIE4A  1
+#define TOIE4   0
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define ICIE5   5
+#define OCIE5C  3
+#define OCIE5B  2
+#define OCIE5A  1
+#define TOIE5   0
+
+#define XMCRA   _SFR_MEM8(0x74)
+#define SRE     7
+#define SRL2    6
+#define SRL1    5
+#define SRL0    4
+#define SRW11   3
+#define SRW10   2
+#define SRW01   1
+#define SRW00   0
+
+#define XMCRB   _SFR_MEM8(0x75)
+#define XMBK    7
+#define XMM2    2
+#define XMM1    1
+#define XMM0    0
+
+/* Reserved [0x76..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define MUX5    3
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC15D  7
+#define ADC14D  6
+#define ADC13D  5
+#define ADC12D  4
+#define ADC11D  3
+#define ADC10D  2
+#define ADC9D   1
+#define ADC8D   0
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define COM3A1  7
+#define COM3A0  6
+#define COM3B1  5
+#define COM3B0  4
+#define COM3C1  3
+#define COM3C0  2
+#define WGM31   1
+#define WGM30   0
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define ICNC3   7
+#define ICES3   6
+#define WGM33   4
+#define WGM32   3
+#define CS32    2
+#define CS31    1
+#define CS30    0
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3A   7
+#define FOC3B   6
+#define FOC3C   5
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define COM4A1  7
+#define COM4A0  6
+#define COM4B1  5
+#define COM4B0  4
+#define COM4C1  3
+#define COM4C0  2
+#define WGM41   1
+#define WGM40   0
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define ICNC4   7
+#define ICES4   6
+#define WGM43   4
+#define WGM42   3
+#define CS42    2
+#define CS41    1
+#define CS40    0
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4A   7
+#define FOC4B   6
+#define FOC4C   5
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define EXCLK   6
+#define AS2     5
+#define TCN2UB  4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define RXC0    7
+#define TXC0    6
+#define UDRE0   5
+#define FE0     4
+#define DOR0    3
+#define UPE0    2
+#define U2X0    1
+#define MPCM0   0
+
+#define UCSR0B  _SFR_MEM8(0XC1)
+#define RXCIE0  7
+#define TXCIE0  6
+#define UDRIE0  5
+#define RXEN0   4
+#define TXEN0   3
+#define UCSZ02  2
+#define RXB80   1
+#define TXB80   0
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UMSEL01 7
+#define UMSEL00 6
+#define UPM01   5
+#define UPM00   4
+#define USBS0   3
+#define UCSZ01  2
+#define UCSZ00  1
+#define UCPOL0  0
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0XC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF] */
+
+#define UCSR2A _SFR_MEM8(0xD0)
+#define RXC2   7
+#define TXC2   6
+#define UDRE2  5
+#define FE2    4
+#define DOR2   3
+#define UPE2   2
+#define U2X2   1
+#define MPCM2  0
+
+#define UCSR2B _SFR_MEM8(0XD1)
+#define RXCIE2 7
+#define TXCIE2 6
+#define UDRIE2 5
+#define RXEN2  4
+#define TXEN2  3
+#define UCSZ22 2
+#define RXB82  1
+#define TXB82  0
+
+#define UCSR2C _SFR_MEM8(0xD2)
+#define UMSEL21 7
+#define UMSEL20 6
+#define UPM21  5
+#define UPM20  4
+#define USBS2  3
+#define UCSZ21 2
+#define UCSZ20 1
+#define UCPOL2 0
+
+/* Reserved [0xD3] */
+
+/* Combine UBRR2L and UBRR2H */
+#define UBRR2  _SFR_MEM16(0xD4)
+
+#define UBRR2L _SFR_MEM8(0xD4)
+#define UBRR2H _SFR_MEM8(0xD5)
+
+#define UDR2   _SFR_MEM8(0XD6)
+
+/* Reserved [0xD7..0xFF] */
+
+#define PINH   _SFR_MEM8(0x100)
+#define PINH7  7
+#define PINH6  6
+#define PINH5  5
+#define PINH4  4
+#define PINH3  3
+#define PINH2  2
+#define PINH1  1
+#define PINH0  0
+
+#define DDRH   _SFR_MEM8(0x101)
+#define DDH7   7
+#define DDH6   6
+#define DDH5   5
+#define DDH4   4
+#define DDH3   3
+#define DDH2   2
+#define DDH1   1
+#define DDH0   0
+
+#define PORTH  _SFR_MEM8(0x102)
+#define PH7    7
+#define PH6    6
+#define PH5    5
+#define PH4    4
+#define PH3    3
+#define PH2    2
+#define PH1    1
+#define PH0    0
+
+#define PINJ   _SFR_MEM8(0x103)
+#define PINJ7  7
+#define PINJ6  6
+#define PINJ5  5
+#define PINJ4  4
+#define PINJ3  3
+#define PINJ2  2
+#define PINJ1  1
+#define PINJ0  0
+
+#define DDRJ   _SFR_MEM8(0x104)
+#define DDJ7   7
+#define DDJ6   6
+#define DDJ5   5
+#define DDJ4   4
+#define DDJ3   3
+#define DDJ2   2
+#define DDJ1   1
+#define DDJ0   0
+
+#define PORTJ  _SFR_MEM8(0x105)
+#define PJ7 7
+#define PJ6 6
+#define PJ5 5
+#define PJ4 4
+#define PJ3 3
+#define PJ2 2
+#define PJ1 1
+#define PJ0 0
+
+#define PINK   _SFR_MEM8(0x106)
+#define PINK7  7
+#define PINK6  6
+#define PINK5  5
+#define PINK4  4
+#define PINK3  3
+#define PINK2  2
+#define PINK1  1
+#define PINK0  0
+
+#define DDRK   _SFR_MEM8(0x107)
+#define DDK7   7
+#define DDK6   6
+#define DDK5   5
+#define DDK4   4
+#define DDK3   3
+#define DDK2   2
+#define DDK1   1
+#define DDK0   0
+
+#define PORTK  _SFR_MEM8(0x108)
+#define PK7 7
+#define PK6 6
+#define PK5 5
+#define PK4 4
+#define PK3 3
+#define PK2 2
+#define PK1 1
+#define PK0 0
+
+#define PINL   _SFR_MEM8(0x109)
+#define PINL7  7
+#define PINL6  6
+#define PINL5  5
+#define PINL4  4
+#define PINL3  3
+#define PINL2  2
+#define PINL1  1
+#define PINL0  0
+
+#define DDRL   _SFR_MEM8(0x10A)
+#define DDL7   7
+#define DDL6   6
+#define DDL5   5
+#define DDL4   4
+#define DDL3   3
+#define DDL2   2
+#define DDL1   1
+#define DDL0   0
+
+#define PORTL  _SFR_MEM8(0x10B)
+#define PL7 7
+#define PL6 6
+#define PL5 5
+#define PL4 4
+#define PL3 3
+#define PL2 2
+#define PL1 1
+#define PL0 0
+
+/* Reserved [0x10C..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define COM5A1  7
+#define COM5A0  6
+#define COM5B1  5
+#define COM5B0  4
+#define COM5C1  3
+#define COM5C0  2
+#define WGM51   1
+#define WGM50   0
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define ICNC5   7
+#define ICES5   6
+#define WGM53   4
+#define WGM52   3
+#define CS52    2
+#define CS51    1
+#define CS50    0
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5A   7
+#define FOC5B   6
+#define FOC5C   5
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E..0x12F] */
+
+#define UCSR3A _SFR_MEM8(0x130)
+#define RXC3   7
+#define TXC3   6
+#define UDRE3  5
+#define FE3    4
+#define DOR3   3
+#define UPE3   2
+#define U2X3   1
+#define MPCM3  0
+
+#define UCSR3B _SFR_MEM8(0X131)
+#define RXCIE3 7
+#define TXCIE3 6
+#define UDRIE3 5
+#define RXEN3  4
+#define TXEN3  3
+#define UCSZ32 2
+#define RXB83  1
+#define TXB83  0
+
+#define UCSR3C _SFR_MEM8(0x132)
+#define UMSEL31 7
+#define UMSEL30 6
+#define UPM31  5
+#define UPM30  4
+#define USBS3  3
+#define UCSZ31 2
+#define UCSZ30 1
+#define UCPOL3 0
+
+/* Reserved [0x133] */
+
+/* Combine UBRR3L and UBRR3H */
+#define UBRR3  _SFR_MEM16(0x134)
+
+#define UBRR3L _SFR_MEM8(0x134)
+#define UBRR3H _SFR_MEM8(0x135)
+
+#define UDR3   _SFR_MEM8(0X136)
+
+/* Reserved [0x137..1FF] */
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+#define SIG_INTERRUPT3			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+#define SIG_INTERRUPT4			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+#define SIG_INTERRUPT5			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num		7
+#define INT6_vect			_VECTOR(7)
+#define SIG_INTERRUPT6			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+#define SIG_INTERRUPT7			_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		9
+#define PCINT0_vect			_VECTOR(9)
+#define SIG_PIN_CHANGE0			_VECTOR(9)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		10
+#define PCINT1_vect			_VECTOR(10)
+#define SIG_PIN_CHANGE1			_VECTOR(10)
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect_num		11
+#define PCINT2_vect			_VECTOR(11)
+#define SIG_PIN_CHANGE2			_VECTOR(11)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		12
+#define WDT_vect			_VECTOR(12)
+#define SIG_WATCHDOG_TIMEOUT		_VECTOR(12)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	13
+#define TIMER2_COMPA_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE2A		_VECTOR(13)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	14
+#define TIMER2_COMPB_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE2B		_VECTOR(14)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		15
+#define TIMER2_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW2			_VECTOR(15)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	16
+#define TIMER1_CAPT_vect		_VECTOR(16)
+#define SIG_INPUT_CAPTURE1		_VECTOR(16)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	17
+#define TIMER1_COMPA_vect		_VECTOR(17)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(17)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	18
+#define TIMER1_COMPB_vect		_VECTOR(18)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(18)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	19
+#define TIMER1_COMPC_vect		_VECTOR(19)
+#define SIG_OUTPUT_COMPARE1C		_VECTOR(19)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		20
+#define TIMER1_OVF_vect			_VECTOR(20)
+#define SIG_OVERFLOW1			_VECTOR(20)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	21
+#define TIMER0_COMPA_vect		_VECTOR(21)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(21)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	22
+#define TIMER0_COMPB_vect		_VECTOR(22)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(22)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		23
+#define TIMER0_OVF_vect			_VECTOR(23)
+#define SIG_OVERFLOW0			_VECTOR(23)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		24
+#define SPI_STC_vect			_VECTOR(24)
+#define SIG_SPI				_VECTOR(24)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		25
+#define USART0_RX_vect			_VECTOR(25)
+#define SIG_USART0_RECV			_VECTOR(25)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	26
+#define USART0_UDRE_vect		_VECTOR(26)
+#define SIG_USART0_DATA			_VECTOR(26)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		27
+#define USART0_TX_vect			_VECTOR(27)
+#define SIG_USART0_TRANS		_VECTOR(27)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	28
+#define ANALOG_COMP_vect		_VECTOR(28)
+#define SIG_COMPARATOR			_VECTOR(28)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		29
+#define ADC_vect			_VECTOR(29)
+#define SIG_ADC				_VECTOR(29)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		30
+#define EE_READY_vect			_VECTOR(30)
+#define SIG_EEPROM_READY		_VECTOR(30)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	31
+#define TIMER3_CAPT_vect		_VECTOR(31)
+#define SIG_INPUT_CAPTURE3		_VECTOR(31)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	32
+#define TIMER3_COMPA_vect		_VECTOR(32)
+#define SIG_OUTPUT_COMPARE3A		_VECTOR(32)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	33
+#define TIMER3_COMPB_vect		_VECTOR(33)
+#define SIG_OUTPUT_COMPARE3B		_VECTOR(33)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	34
+#define TIMER3_COMPC_vect		_VECTOR(34)
+#define SIG_OUTPUT_COMPARE3C		_VECTOR(34)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		35
+#define TIMER3_OVF_vect			_VECTOR(35)
+#define SIG_OVERFLOW3			_VECTOR(35)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		36
+#define USART1_RX_vect			_VECTOR(36)
+#define SIG_USART1_RECV			_VECTOR(36)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num	37
+#define USART1_UDRE_vect		_VECTOR(37)
+#define SIG_USART1_DATA			_VECTOR(37)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		38
+#define USART1_TX_vect			_VECTOR(38)
+#define SIG_USART1_TRANS		_VECTOR(38)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num		39
+#define TWI_vect			_VECTOR(39)
+#define SIG_2WIRE_SERIAL		_VECTOR(39)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		40
+#define SPM_READY_vect			_VECTOR(40)
+#define SIG_SPM_READY			_VECTOR(40)
+
+/* Timer/Counter4 Capture Event */
+#define TIMER4_CAPT_vect_num	41
+#define TIMER4_CAPT_vect		_VECTOR(41)
+#define SIG_INPUT_CAPTURE4		_VECTOR(41)
+
+/* Timer/Counter4 Compare Match A */
+#define TIMER4_COMPA_vect_num	42
+#define TIMER4_COMPA_vect		_VECTOR(42)
+#define SIG_OUTPUT_COMPARE4A		_VECTOR(42)
+
+/* Timer/Counter4 Compare Match B */
+#define TIMER4_COMPB_vect_num	43
+#define TIMER4_COMPB_vect		_VECTOR(43)
+#define SIG_OUTPUT_COMPARE4B		_VECTOR(43)
+
+/* Timer/Counter4 Compare Match C */
+#define TIMER4_COMPC_vect_num	44
+#define TIMER4_COMPC_vect		_VECTOR(44)
+#define SIG_OUTPUT_COMPARE4C		_VECTOR(44)
+
+/* Timer/Counter4 Overflow */
+#define TIMER4_OVF_vect_num		45
+#define TIMER4_OVF_vect			_VECTOR(45)
+#define SIG_OVERFLOW4			_VECTOR(45)
+
+/* Timer/Counter5 Capture Event */
+#define TIMER5_CAPT_vect_num	46
+#define TIMER5_CAPT_vect		_VECTOR(46)
+#define SIG_INPUT_CAPTURE5		_VECTOR(46)
+
+/* Timer/Counter5 Compare Match A */
+#define TIMER5_COMPA_vect_num	47
+#define TIMER5_COMPA_vect		_VECTOR(47)
+#define SIG_OUTPUT_COMPARE5A		_VECTOR(47)
+
+/* Timer/Counter5 Compare Match B */
+#define TIMER5_COMPB_vect_num	48
+#define TIMER5_COMPB_vect		_VECTOR(48)
+#define SIG_OUTPUT_COMPARE5B		_VECTOR(48)
+
+/* Timer/Counter5 Compare Match C */
+#define TIMER5_COMPC_vect_num	49
+#define TIMER5_COMPC_vect		_VECTOR(49)
+#define SIG_OUTPUT_COMPARE5C		_VECTOR(49)
+
+/* Timer/Counter5 Overflow */
+#define TIMER5_OVF_vect_num		50
+#define TIMER5_OVF_vect			_VECTOR(50)
+#define SIG_OVERFLOW5			_VECTOR(50)
+
+/* USART2, Rx Complete */
+#define USART2_RX_vect_num		51
+#define USART2_RX_vect			_VECTOR(51)
+#define SIG_USART2_RECV			_VECTOR(51)
+
+/* USART2 Data register Empty */
+#define USART2_UDRE_vect_num		52
+#define USART2_UDRE_vect		_VECTOR(52)
+#define SIG_USART2_DATA			_VECTOR(52)
+
+/* USART2, Tx Complete */
+#define USART2_TX_vect_num		53
+#define USART2_TX_vect			_VECTOR(53)
+#define SIG_USART2_TRANS		_VECTOR(53)
+
+/* USART3, Rx Complete */
+#define USART3_RX_vect_num		54
+#define USART3_RX_vect			_VECTOR(54)
+#define SIG_USART3_RECV			_VECTOR(54)
+
+/* USART3 Data register Empty */
+#define USART3_UDRE_vect_num		55
+#define USART3_UDRE_vect		_VECTOR(55)
+#define SIG_USART3_DATA			_VECTOR(55)
+
+/* USART3, Tx Complete */
+#define USART3_TX_vect_num		56
+#define USART3_TX_vect			_VECTOR(56)
+#define SIG_USART3_TRANS		_VECTOR(56)
+
+# define _VECTORS_SIZE 228
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_INTERRUPT2
+#pragma GCC poison SIG_INTERRUPT3
+#pragma GCC poison SIG_INTERRUPT4
+#pragma GCC poison SIG_INTERRUPT5
+#pragma GCC poison SIG_INTERRUPT6
+#pragma GCC poison SIG_INTERRUPT7
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OUTPUT_COMPARE1C
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART0_RECV
+#pragma GCC poison SIG_USART0_DATA
+#pragma GCC poison SIG_USART0_TRANS
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_INPUT_CAPTURE3
+#pragma GCC poison SIG_OUTPUT_COMPARE3A
+#pragma GCC poison SIG_OUTPUT_COMPARE3B
+#pragma GCC poison SIG_OUTPUT_COMPARE3C
+#pragma GCC poison SIG_OVERFLOW3
+#pragma GCC poison SIG_USART1_RECV
+#pragma GCC poison SIG_USART1_DATA
+#pragma GCC poison SIG_USART1_TRANS
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+#pragma GCC poison SIG_INPUT_CAPTURE4
+#pragma GCC poison SIG_OUTPUT_COMPARE4A
+#pragma GCC poison SIG_OUTPUT_COMPARE4B
+#pragma GCC poison SIG_OUTPUT_COMPARE4C
+#pragma GCC poison SIG_OVERFLOW4
+#pragma GCC poison SIG_INPUT_CAPTURE5
+#pragma GCC poison SIG_OUTPUT_COMPARE5A
+#pragma GCC poison SIG_OUTPUT_COMPARE5B
+#pragma GCC poison SIG_OUTPUT_COMPARE5C
+#pragma GCC poison SIG_OVERFLOW5
+#pragma GCC poison SIG_USART2_RECV
+#pragma GCC poison SIG_USART2_DATA
+#pragma GCC poison SIG_USART2_TRANS
+#pragma GCC poison SIG_USART3_RECV
+#pragma GCC poison SIG_USART3_DATA
+#pragma GCC poison SIG_USART3_TRANS
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
 
 /* Constants */
 #define SPM_PAGESIZE    256
@@ -91,7 +1692,6 @@
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x03
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -99,5 +1699,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_IOM1280_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom1281.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom1281.h
@@ -28,14 +28,1356 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom1281.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 /* avr/iom1281.h - definitions for ATmega1281 */
 
 #ifndef _AVR_IOM1281_H_
 #define _AVR_IOM1281_H_ 1
 
-#include <avr/iomxx0_1.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iomxx0_1.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0X01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0X02)
+#define PA7     7
+#define PA6     6
+#define PA5     5
+#define PA4     4
+#define PA3     3
+#define PA2     2
+#define PA1     1
+#define PA0     0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7     7
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC3     3
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7     7
+#define PE6     6
+#define PE5     5
+#define PE4     4
+#define PE3     3
+#define PE2     2
+#define PE1     1
+#define PE0     0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7     7
+#define PF6     6
+#define PF5     5
+#define PF4     4
+#define PF3     3
+#define PF2     2
+#define PF1     1
+#define PF0     0
+
+#define PING    _SFR_IO8(0x12)
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDG5    5
+#define DDG4    4
+#define DDG3    3
+#define DDG2    2
+#define DDG1    1
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PG5     5
+#define PG4     4
+#define PG3     3
+#define PG2     2
+#define PG1     1
+#define PG0     0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8(0x17)
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define TIFR3   _SFR_IO8(0x18)
+#define ICF3    5
+#define OCF3C   3
+#define OCF3B   2
+#define OCF3A   1
+#define TOV3    0
+
+#define TIFR4   _SFR_IO8(0x19)
+#define ICF4    5
+#define OCF4C   3
+#define OCF4B   2
+#define OCF4A   1
+#define TOV4    0
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define ICF5    5
+#define OCF5C   3
+#define OCF5B   2
+#define OCF5A   1
+#define TOV5    0
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR   _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0X27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0X2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8(0x31)
+#define OCDR    _SFR_IO8(0x31)
+#define IDRD    7
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0X35)
+#define JTD     7
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0X3B)
+#define RAMPZ0  0
+
+#define EIND    _SFR_IO8(0X3C)
+#define EIND0   0
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTWI       7
+#define PRTIM2      6
+#define PRTIM0      5
+#define PRTIM1      3
+#define PRSPI       2
+#define PRUSART0    1
+#define PRADC       0
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRUSART0
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRTIM5      5
+#define PRTIM4      4
+#define PRTIM3      3
+#define PRUSART3    2
+#define PRUSART2    1
+#define PRUSART1    0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRUSART2)|(1<<PRUSART3)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRUSART2
+#define __AVR_HAVE_PRR1_PRUSART3
+#define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRTIM4
+#define __AVR_HAVE_PRR1_PRTIM5
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define ICIE3   5
+#define OCIE3C  3
+#define OCIE3B  2
+#define OCIE3A  1
+#define TOIE3   0
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define ICIE4   5
+#define OCIE4C  3
+#define OCIE4B  2
+#define OCIE4A  1
+#define TOIE4   0
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define ICIE5   5
+#define OCIE5C  3
+#define OCIE5B  2
+#define OCIE5A  1
+#define TOIE5   0
+
+#define XMCRA   _SFR_MEM8(0x74)
+#define SRE     7
+#define SRL2    6
+#define SRL1    5
+#define SRL0    4
+#define SRW11   3
+#define SRW10   2
+#define SRW01   1
+#define SRW00   0
+
+#define XMCRB   _SFR_MEM8(0x75)
+#define XMBK    7
+#define XMM2    2
+#define XMM1    1
+#define XMM0    0
+
+/* Reserved [0x76..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC15D  7
+#define ADC14D  6
+#define ADC13D  5
+#define ADC12D  4
+#define ADC11D  3
+#define ADC10D  2
+#define ADC9D   1
+#define ADC8D   0
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define COM3A1  7
+#define COM3A0  6
+#define COM3B1  5
+#define COM3B0  4
+#define COM3C1  3
+#define COM3C0  2
+#define WGM31   1
+#define WGM30   0
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define ICNC3   7
+#define ICES3   6
+#define WGM33   4
+#define WGM32   3
+#define CS32    2
+#define CS31    1
+#define CS30    0
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3A   7
+#define FOC3B   6
+#define FOC3C   5
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define COM4A1  7
+#define COM4A0  6
+#define COM4B1  5
+#define COM4B0  4
+#define COM4C1  3
+#define COM4C0  2
+#define WGM41   1
+#define WGM40   0
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define ICNC4   7
+#define ICES4   6
+#define WGM43   4
+#define WGM42   3
+#define CS42    2
+#define CS41    1
+#define CS40    0
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4A   7
+#define FOC4B   6
+#define FOC4C   5
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define EXCLK   6
+#define AS2     5
+#define TCN2UB  4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define RXC0    7
+#define TXC0    6
+#define UDRE0   5
+#define FE0     4
+#define DOR0    3
+#define UPE0    2
+#define U2X0    1
+#define MPCM0   0
+
+#define UCSR0B  _SFR_MEM8(0XC1)
+#define RXCIE0  7
+#define TXCIE0  6
+#define UDRIE0  5
+#define RXEN0   4
+#define TXEN0   3
+#define UCSZ02  2
+#define RXB80   1
+#define TXB80   0
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UMSEL01 7
+#define UMSEL00 6
+#define UPM01   5
+#define UPM00   4
+#define USBS0   3
+#define UCSZ01  2
+#define UCSZ00  1
+#define UCPOL0  0
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0XC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF] */
+
+/* Reserved [0xD7..0xFF] */
+
+/* Reserved [0x10C..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define COM5A1  7
+#define COM5A0  6
+#define COM5B1  5
+#define COM5B0  4
+#define COM5C1  3
+#define COM5C0  2
+#define WGM51   1
+#define WGM50   0
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define ICNC5   7
+#define ICES5   6
+#define WGM53   4
+#define WGM52   3
+#define CS52    2
+#define CS51    1
+#define CS50    0
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5A   7
+#define FOC5B   6
+#define FOC5C   5
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E..0x12F] */
+
+/* Reserved [0x137..1FF] */
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+#define SIG_INTERRUPT3			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+#define SIG_INTERRUPT4			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+#define SIG_INTERRUPT5			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num		7
+#define INT6_vect			_VECTOR(7)
+#define SIG_INTERRUPT6			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+#define SIG_INTERRUPT7			_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		9
+#define PCINT0_vect			_VECTOR(9)
+#define SIG_PIN_CHANGE0			_VECTOR(9)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		10
+#define PCINT1_vect			_VECTOR(10)
+#define SIG_PIN_CHANGE1			_VECTOR(10)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		12
+#define WDT_vect			_VECTOR(12)
+#define SIG_WATCHDOG_TIMEOUT		_VECTOR(12)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	13
+#define TIMER2_COMPA_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE2A		_VECTOR(13)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	14
+#define TIMER2_COMPB_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE2B		_VECTOR(14)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		15
+#define TIMER2_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW2			_VECTOR(15)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	16
+#define TIMER1_CAPT_vect		_VECTOR(16)
+#define SIG_INPUT_CAPTURE1		_VECTOR(16)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	17
+#define TIMER1_COMPA_vect		_VECTOR(17)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(17)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	18
+#define TIMER1_COMPB_vect		_VECTOR(18)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(18)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	19
+#define TIMER1_COMPC_vect		_VECTOR(19)
+#define SIG_OUTPUT_COMPARE1C		_VECTOR(19)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		20
+#define TIMER1_OVF_vect			_VECTOR(20)
+#define SIG_OVERFLOW1			_VECTOR(20)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	21
+#define TIMER0_COMPA_vect		_VECTOR(21)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(21)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	22
+#define TIMER0_COMPB_vect		_VECTOR(22)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(22)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		23
+#define TIMER0_OVF_vect			_VECTOR(23)
+#define SIG_OVERFLOW0			_VECTOR(23)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		24
+#define SPI_STC_vect			_VECTOR(24)
+#define SIG_SPI				_VECTOR(24)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		25
+#define USART0_RX_vect			_VECTOR(25)
+#define SIG_USART0_RECV			_VECTOR(25)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	26
+#define USART0_UDRE_vect		_VECTOR(26)
+#define SIG_USART0_DATA			_VECTOR(26)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		27
+#define USART0_TX_vect			_VECTOR(27)
+#define SIG_USART0_TRANS		_VECTOR(27)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	28
+#define ANALOG_COMP_vect		_VECTOR(28)
+#define SIG_COMPARATOR			_VECTOR(28)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		29
+#define ADC_vect			_VECTOR(29)
+#define SIG_ADC				_VECTOR(29)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		30
+#define EE_READY_vect			_VECTOR(30)
+#define SIG_EEPROM_READY		_VECTOR(30)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	31
+#define TIMER3_CAPT_vect		_VECTOR(31)
+#define SIG_INPUT_CAPTURE3		_VECTOR(31)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	32
+#define TIMER3_COMPA_vect		_VECTOR(32)
+#define SIG_OUTPUT_COMPARE3A		_VECTOR(32)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	33
+#define TIMER3_COMPB_vect		_VECTOR(33)
+#define SIG_OUTPUT_COMPARE3B		_VECTOR(33)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	34
+#define TIMER3_COMPC_vect		_VECTOR(34)
+#define SIG_OUTPUT_COMPARE3C		_VECTOR(34)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		35
+#define TIMER3_OVF_vect			_VECTOR(35)
+#define SIG_OVERFLOW3			_VECTOR(35)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		36
+#define USART1_RX_vect			_VECTOR(36)
+#define SIG_USART1_RECV			_VECTOR(36)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num	37
+#define USART1_UDRE_vect		_VECTOR(37)
+#define SIG_USART1_DATA			_VECTOR(37)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		38
+#define USART1_TX_vect			_VECTOR(38)
+#define SIG_USART1_TRANS		_VECTOR(38)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num		39
+#define TWI_vect			_VECTOR(39)
+#define SIG_2WIRE_SERIAL		_VECTOR(39)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		40
+#define SPM_READY_vect			_VECTOR(40)
+#define SIG_SPM_READY			_VECTOR(40)
+
+/* Timer/Counter4 Compare Match A */
+#define TIMER4_COMPA_vect_num	42
+#define TIMER4_COMPA_vect		_VECTOR(42)
+#define SIG_OUTPUT_COMPARE4A		_VECTOR(42)
+
+/* Timer/Counter4 Compare Match B */
+#define TIMER4_COMPB_vect_num	43
+#define TIMER4_COMPB_vect		_VECTOR(43)
+#define SIG_OUTPUT_COMPARE4B		_VECTOR(43)
+
+/* Timer/Counter4 Compare Match C */
+#define TIMER4_COMPC_vect_num	44
+#define TIMER4_COMPC_vect		_VECTOR(44)
+#define SIG_OUTPUT_COMPARE4C		_VECTOR(44)
+
+/* Timer/Counter4 Overflow */
+#define TIMER4_OVF_vect_num		45
+#define TIMER4_OVF_vect			_VECTOR(45)
+#define SIG_OVERFLOW4			_VECTOR(45)
+
+/* Timer/Counter5 Compare Match A */
+#define TIMER5_COMPA_vect_num	47
+#define TIMER5_COMPA_vect		_VECTOR(47)
+#define SIG_OUTPUT_COMPARE5A		_VECTOR(47)
+
+/* Timer/Counter5 Compare Match B */
+#define TIMER5_COMPB_vect_num	48
+#define TIMER5_COMPB_vect		_VECTOR(48)
+#define SIG_OUTPUT_COMPARE5B		_VECTOR(48)
+
+/* Timer/Counter5 Compare Match C */
+#define TIMER5_COMPC_vect_num	49
+#define TIMER5_COMPC_vect		_VECTOR(49)
+#define SIG_OUTPUT_COMPARE5C		_VECTOR(49)
+
+/* Timer/Counter5 Overflow */
+#define TIMER5_OVF_vect_num		50
+#define TIMER5_OVF_vect			_VECTOR(50)
+#define SIG_OVERFLOW5			_VECTOR(50)
+
+#define _VECTORS_SIZE 204
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_INTERRUPT2
+#pragma GCC poison SIG_INTERRUPT3
+#pragma GCC poison SIG_INTERRUPT4
+#pragma GCC poison SIG_INTERRUPT5
+#pragma GCC poison SIG_INTERRUPT6
+#pragma GCC poison SIG_INTERRUPT7
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OUTPUT_COMPARE1C
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART0_RECV
+#pragma GCC poison SIG_USART0_DATA
+#pragma GCC poison SIG_USART0_TRANS
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_INPUT_CAPTURE3
+#pragma GCC poison SIG_OUTPUT_COMPARE3A
+#pragma GCC poison SIG_OUTPUT_COMPARE3B
+#pragma GCC poison SIG_OUTPUT_COMPARE3C
+#pragma GCC poison SIG_OVERFLOW3
+#pragma GCC poison SIG_USART1_RECV
+#pragma GCC poison SIG_USART1_DATA
+#pragma GCC poison SIG_USART1_TRANS
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+#pragma GCC poison SIG_INPUT_CAPTURE4
+#pragma GCC poison SIG_OUTPUT_COMPARE4A
+#pragma GCC poison SIG_OUTPUT_COMPARE4B
+#pragma GCC poison SIG_OUTPUT_COMPARE4C
+#pragma GCC poison SIG_OVERFLOW4
+#pragma GCC poison SIG_INPUT_CAPTURE5
+#pragma GCC poison SIG_OUTPUT_COMPARE5A
+#pragma GCC poison SIG_OUTPUT_COMPARE5B
+#pragma GCC poison SIG_OUTPUT_COMPARE5C
+#pragma GCC poison SIG_OVERFLOW5
+#pragma GCC poison SIG_USART2_RECV
+#pragma GCC poison SIG_USART2_DATA
+#pragma GCC poison SIG_USART2_TRANS
+#pragma GCC poison SIG_USART3_RECV
+#pragma GCC poison SIG_USART3_DATA
+#pragma GCC poison SIG_USART3_TRANS
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
+
 
 /* Constants */
 #define SPM_PAGESIZE    256
@@ -91,7 +1433,6 @@
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x04
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -99,5 +1440,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_IOM1281_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom1284.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom1284.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA1284_H_INCLUDED
 #define _AVR_ATMEGA1284_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRA    _SFR_IO8(0x01)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x02)
 #define PORTA7  7
@@ -92,13 +91,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -122,13 +137,29 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC7  7
@@ -152,13 +183,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -390,19 +437,19 @@
 
 #define PRR0    _SFR_MEM8(0x64)
 #define PRADC   0
+#define PRUSART0 1
 #define PRSPI   2
 #define PRTIM1  3
-#define PRUSART0 1
 #define PRUSART1 4
 #define PRTIM0  5
 #define PRTIM2  6
 #define PRTWI   7
 
-#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
 #define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRUSART0
 #define __AVR_HAVE_PRR0_PRSPI
 #define __AVR_HAVE_PRR0_PRTIM1
-#define __AVR_HAVE_PRR0_PRUSART0
 #define __AVR_HAVE_PRR0_PRUSART1
 #define __AVR_HAVE_PRR0_PRTIM0
 #define __AVR_HAVE_PRR0_PRTIM2
@@ -819,6 +866,16 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -957,21 +1014,44 @@
 #define TIMER3_OVF_vect            _VECTOR(34)
 #define TIMER3_OVF_vect_num        34
 
-#define _VECTORS_SIZE 140
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 140
+#else
+#  define _VECTORS_SIZE 140U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 256
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFFF
-#define RAMSTART     0x0100
-#define RAMSIZE      16384
-#define RAMEND       0x40FF
-#define E2START     0
-#define E2SIZE      4096
-#define E2PAGESIZE  8
-#define E2END       0x0FFF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 256
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFFF
+#else
+#  define SPM_PAGESIZE 256U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      16384
+#  define RAMEND       0x40FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      16384U
+#  define RAMEND       0x40FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      4096
+#  define E2PAGESIZE  8
+#  define E2END       0x0FFF
+#else
+#  define E2START     0U
+#  define E2SIZE      4096U
+#  define E2PAGESIZE  8U
+#  define E2END       0x0FFFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -988,6 +1068,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -998,11 +1080,15 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_JTAGEN      (unsigned char)~_BV(6)
 #define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
 #define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
 #define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -1018,12 +1104,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 #endif /* #ifdef _AVR_ATMEGA1284_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom1284p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom1284p.h
@@ -29,7 +29,7 @@
   POSSIBILITY OF SUCH DAMAGE. 
 */
 
-/* $Id$ */
+/* $Id: iom1284p.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/iom1284p.h - definitions for ATmega1284P. */
 
@@ -1209,7 +1209,6 @@
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x05
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -1217,5 +1216,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif  /* _AVR_IOM1284P_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom1284rfr2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom1284rfr2.h
@@ -1,41 +1,25 @@
-/* Copyright (c) 2013 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* $Id$ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
 
-/* avr/iom1284rfr2.h - definitions for ATmega1284RFR2 */
 
-#ifndef _AVR_IOM1284RFR2_H_
-#define _AVR_IOM1284RFR2_H_ 1
+#ifndef _AVR_ATMEGA1284RFR2_H_INCLUDED
+#define _AVR_ATMEGA1284RFR2_H_INCLUDED
 
-/* This file should only be included from <avr/io.h>, never directly. */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -47,1189 +31,582 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif
 
-#include <avr/sfr_defs.h>
+/* Registers and associated bit numbers */
 
-#ifndef __ASSEMBLER__
-#  define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr))
-#  define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type)
-#  define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type)
-#endif /* __ASSEMBLER__ */
-
-/*
- * USAGE:
- *
- * simple register assignment:
- * TIFR1 = 0x17
- * subregister assignment:
- * TIFR1_struct.ocf1a = 1
- * (subregister names are converted to small letters)
- */
-
-
-/* Port A Input Pins Address */
-#define PINA                            _SFR_IO8(0x00)
-
-  /* PINA */
-
-#define PINA0                           0
-#define PINA1                           1
-#define PINA2                           2
-#define PINA3                           3
-#define PINA4                           4
-#define PINA5                           5
-#define PINA6                           6
-#define PINA7                           7
-
-/* Port A Data Direction Register */
-#define DDRA                            _SFR_IO8(0x01)
-
-  /* DDRA */
-
-#define DDA0                            0
-#define DDA1                            1
-#define DDA2                            2
-#define DDA3                            3
-#define DDA4                            4
-#define DDA5                            5
-#define DDA6                            6
-#define DDA7                            7
-
-/* Port A Data Register */
-#define PORTA                           _SFR_IO8(0x02)
-
-  /* PORTA */
-
-#define PORTA0                          0
-#define PA0                             0
-#define PORTA1                          1
-#define PA1                             1
-#define PORTA2                          2
-#define PA2                             2
-#define PORTA3                          3
-#define PA3                             3
-#define PORTA4                          4
-#define PA4                             4
-#define PORTA5                          5
-#define PA5                             5
-#define PORTA6                          6
-#define PA6                             6
-#define PORTA7                          7
-#define PA7                             7
-
-/* Port B Input Pins Address */
-#define PINB                            _SFR_IO8(0x03)
-
-  /* PINB */
-
-#define PINB0                           0
-#define PINB1                           1
-#define PINB2                           2
-#define PINB3                           3
-#define PINB4                           4
-#define PINB5                           5
-#define PINB6                           6
-#define PINB7                           7
-
-/* Port B Data Direction Register */
-#define DDRB                            _SFR_IO8(0x04)
-
-  /* DDRB */
-
-#define DDB0                            0
-#define DDB1                            1
-#define DDB2                            2
-#define DDB3                            3
-#define DDB4                            4
-#define DDB5                            5
-#define DDB6                            6
-#define DDB7                            7
-
-/* Port B Data Register */
-#define PORTB                           _SFR_IO8(0x05)
-
-  /* PORTB */
-
-#define PORTB0                          0
-#define PB0                             0
-#define PORTB1                          1
-#define PB1                             1
-#define PORTB2                          2
-#define PB2                             2
-#define PORTB3                          3
-#define PB3                             3
-#define PORTB4                          4
-#define PB4                             4
-#define PORTB5                          5
-#define PB5                             5
-#define PORTB6                          6
-#define PB6                             6
-#define PORTB7                          7
-#define PB7                             7
-
-/* Port C Input Pins Address */
-#define PINC                            _SFR_IO8(0x06)
-
-  /* PINC */
-
-#define PINC0                           0
-#define PINC1                           1
-#define PINC2                           2
-#define PINC3                           3
-#define PINC4                           4
-#define PINC5                           5
-#define PINC6                           6
-#define PINC7                           7
-
-/* Port C Data Direction Register */
-#define DDRC                            _SFR_IO8(0x07)
-
-  /* DDRC */
-
-#define DDC0                            0
-#define DDC1                            1
-#define DDC2                            2
-#define DDC3                            3
-#define DDC4                            4
-#define DDC5                            5
-#define DDC6                            6
-#define DDC7                            7
-
-/* Port C Data Register */
-#define PORTC                           _SFR_IO8(0x08)
-
-  /* PORTC */
-
-#define PORTC0                          0
-#define PC0                             0
-#define PORTC1                          1
-#define PC1                             1
-#define PORTC2                          2
-#define PC2                             2
-#define PORTC3                          3
-#define PC3                             3
-#define PORTC4                          4
-#define PC4                             4
-#define PORTC5                          5
-#define PC5                             5
-#define PORTC6                          6
-#define PC6                             6
-#define PORTC7                          7
-#define PC7                             7
-
-/* Port D Input Pins Address */
-#define PIND                            _SFR_IO8(0x09)
-
-  /* PIND */
-
-#define PIND0                           0
-#define PIND1                           1
-#define PIND2                           2
-#define PIND3                           3
-#define PIND4                           4
-#define PIND5                           5
-#define PIND6                           6
-#define PIND7                           7
-
-/* Port D Data Direction Register */
-#define DDRD                            _SFR_IO8(0x0A)
-
-  /* DDRD */
-
-#define DDD0                            0
-#define DDD1                            1
-#define DDD2                            2
-#define DDD3                            3
-#define DDD4                            4
-#define DDD5                            5
-#define DDD6                            6
-#define DDD7                            7
-
-/* Port D Data Register */
-#define PORTD                           _SFR_IO8(0x0B)
-
-  /* PORTD */
-
-#define PORTD0                          0
-#define PD0                             0
-#define PORTD1                          1
-#define PD1                             1
-#define PORTD2                          2
-#define PD2                             2
-#define PORTD3                          3
-#define PD3                             3
-#define PORTD4                          4
-#define PD4                             4
-#define PORTD5                          5
-#define PD5                             5
-#define PORTD6                          6
-#define PD6                             6
-#define PORTD7                          7
-#define PD7                             7
-
-/* Port E Input Pins Address */
-#define PINE                            _SFR_IO8(0x0C)
-
-  /* PINE */
-
-#define PINE0                           0
-#define PINE1                           1
-#define PINE2                           2
-#define PINE3                           3
-#define PINE4                           4
-#define PINE5                           5
-#define PINE6                           6
-#define PINE7                           7
-
-/* Port E Data Direction Register */
-#define DDRE                            _SFR_IO8(0x0D)
-
-  /* DDRE */
-
-#define DDE0                            0
-#define DDE1                            1
-#define DDE2                            2
-#define DDE3                            3
-#define DDE4                            4
-#define DDE5                            5
-#define DDE6                            6
-#define DDE7                            7
-
-/* Port E Data Register */
-#define PORTE                           _SFR_IO8(0x0E)
-
-  /* PORTE */
-
-#define PORTE0                          0
-#define PE0                             0
-#define PORTE1                          1
-#define PE1                             1
-#define PORTE2                          2
-#define PE2                             2
-#define PORTE3                          3
-#define PE3                             3
-#define PORTE4                          4
-#define PE4                             4
-#define PORTE5                          5
-#define PE5                             5
-#define PORTE6                          6
-#define PE6                             6
-#define PORTE7                          7
-#define PE7                             7
-
-/* Port F Input Pins Address */
-#define PINF                            _SFR_IO8(0x0F)
-
-  /* PINF */
-
-#define PINF0                           0
-#define PINF1                           1
-#define PINF2                           2
-#define PINF3                           3
-#define PINF4                           4
-#define PINF5                           5
-#define PINF6                           6
-#define PINF7                           7
-
-/* Port F Data Direction Register */
-#define DDRF                            _SFR_IO8(0x10)
-
-  /* DDRF */
-
-#define DDF0                            0
-#define DDF1                            1
-#define DDF2                            2
-#define DDF3                            3
-#define DDF4                            4
-#define DDF5                            5
-#define DDF6                            6
-#define DDF7                            7
-
-/* Port F Data Register */
-#define PORTF                           _SFR_IO8(0x11)
-
-  /* PORTF */
-
-#define PORTF0                          0
-#define PF0                             0
-#define PORTF1                          1
-#define PF1                             1
-#define PORTF2                          2
-#define PF2                             2
-#define PORTF3                          3
-#define PF3                             3
-#define PORTF4                          4
-#define PF4                             4
-#define PORTF5                          5
-#define PF5                             5
-#define PORTF6                          6
-#define PF6                             6
-#define PORTF7                          7
-#define PF7                             7
-
-/* Port G Input Pins Address */
-#define PING                            _SFR_IO8(0x12)
-
-  /* PING */
-
-#define PING0                           0
-#define PING1                           1
-#define PING2                           2
-#define PING3                           3
-#define PING4                           4
-#define PING5                           5
-
-/* Port G Data Direction Register */
-#define DDRG                            _SFR_IO8(0x13)
-
-  /* DDRG */
-
-#define DDG0                            0
-#define DDG1                            1
-#define DDG2                            2
-#define DDG3                            3
-#define DDG4                            4
-#define DDG5                            5
-
-/* Port G Data Register */
-#define PORTG                           _SFR_IO8(0x14)
-
-  /* PORTG */
-
-#define PORTG0                          0
-#define PG0                             0
-#define PORTG1                          1
-#define PG1                             1
-#define PORTG2                          2
-#define PG2                             2
-#define PORTG3                          3
-#define PG3                             3
-#define PORTG4                          4
-#define PG4                             4
-#define PORTG5                          5
-#define PG5                             5
-
-/* Timer/Counter0 Interrupt Flag Register */
-#define TIFR0                           _SFR_IO8(0x15)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR0 {
-        unsigned int tov0 : 1;	/* Timer/Counter0 Overflow Flag */
-        unsigned int ocf0a : 1;	/* Timer/Counter0 Output Compare A Match Flag */
-        unsigned int ocf0b : 1;	/* Timer/Counter0 Output Compare B Match Flag */
-        unsigned int : 5;
-};
-
-#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR0 */
-
-#define TOV0                            0
-#define OCF0A                           1
-#define OCF0B                           2
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1                           _SFR_IO8(0x16)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR1 {
-        unsigned int tov1 : 1;	/* Timer/Counter1 Overflow Flag */
-        unsigned int ocf1a : 1;	/* Timer/Counter1 Output Compare A Match Flag */
-        unsigned int ocf1b : 1;	/* Timer/Counter1 Output Compare B Match Flag */
-        unsigned int ocf1c : 1;	/* Timer/Counter1 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf1 : 1;	/* Timer/Counter1 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR1 */
-
-#define TOV1                            0
-#define OCF1A                           1
-#define OCF1B                           2
-#define OCF1C                           3
-#define ICF1                            5
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR2                           _SFR_IO8(0x17)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR2 {
-        unsigned int tov2 : 1;	/* Timer/Counter2 Overflow Flag */
-        unsigned int ocf2a : 1;	/* Output Compare Flag 2 A */
-        unsigned int ocf2b : 1;	/* Output Compare Flag 2 B */
-        unsigned int : 5;
-};
-
-#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR2 */
-
-#define TOV2                            0
-#define OCF2A                           1
-#define OCF2B                           2
-
-/* Timer/Counter3 Interrupt Flag Register */
-#define TIFR3                           _SFR_IO8(0x18)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR3 {
-        unsigned int tov3 : 1;	/* Timer/Counter3 Overflow Flag */
-        unsigned int ocf3a : 1;	/* Timer/Counter3 Output Compare A Match Flag */
-        unsigned int ocf3b : 1;	/* Timer/Counter3 Output Compare B Match Flag */
-        unsigned int ocf3c : 1;	/* Timer/Counter3 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf3 : 1;	/* Timer/Counter3 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR3 */
-
-#define TOV3                            0
-#define OCF3A                           1
-#define OCF3B                           2
-#define OCF3C                           3
-#define ICF3                            5
-
-/* Timer/Counter4 Interrupt Flag Register */
-#define TIFR4                           _SFR_IO8(0x19)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR4 {
-        unsigned int tov4 : 1;	/* Timer/Counter4 Overflow Flag */
-        unsigned int ocf4a : 1;	/* Timer/Counter4 Output Compare A Match Flag */
-        unsigned int ocf4b : 1;	/* Timer/Counter4 Output Compare B Match Flag */
-        unsigned int ocf4c : 1;	/* Timer/Counter4 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf4 : 1;	/* Timer/Counter4 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR4 */
-
-#define TOV4                            0
-#define OCF4A                           1
-#define OCF4B                           2
-#define OCF4C                           3
-#define ICF4                            5
-
-/* Timer/Counter5 Interrupt Flag Register */
-#define TIFR5                           _SFR_IO8(0x1A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR5 {
-        unsigned int tov5 : 1;	/* Timer/Counter5 Overflow Flag */
-        unsigned int ocf5a : 1;	/* Timer/Counter5 Output Compare A Match Flag */
-        unsigned int ocf5b : 1;	/* Timer/Counter5 Output Compare B Match Flag */
-        unsigned int ocf5c : 1;	/* Timer/Counter5 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf5 : 1;	/* Timer/Counter5 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR5 */
-
-#define TOV5                            0
-#define OCF5A                           1
-#define OCF5B                           2
-#define OCF5C                           3
-#define ICF5                            5
-
-/* Pin Change Interrupt Flag Register */
-#define PCIFR                           _SFR_IO8(0x1B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCIFR {
-        unsigned int pcif : 3;	/* Pin Change Interrupt Flags */
-        unsigned int : 5;
-};
-
-#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCIFR */
-
-#define PCIF0                           0
-#define PCIF1                           1
-#define PCIF2                           2
-
-/* External Interrupt Flag Register */
-#define EIFR                            _SFR_IO8(0x1C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIFR {
-        unsigned int intf : 8;	/* External Interrupt Flag */
-};
-
-#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIFR */
-
-#define INTF0                           0
-#define INTF1                           1
-#define INTF2                           2
-#define INTF3                           3
-#define INTF4                           4
-#define INTF5                           5
-#define INTF6                           6
-#define INTF7                           7
-
-/* External Interrupt Mask Register */
-#define EIMSK                           _SFR_IO8(0x1D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIMSK {
-        unsigned int intm : 8;	/* External Interrupt Request Enable */
-};
-
-#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIMSK */
-
-#define INT0                            0
-#define INT1                            1
-#define INT2                            2
-#define INT3                            3
-#define INT4                            4
-#define INT5                            5
-#define INT6                            6
-#define INT7                            7
-
-/* General Purpose IO Register 0 */
-#define GPIOR0                          _SFR_IO8(0x1E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR0 {
-        unsigned int gpior00 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior01 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior02 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior03 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior04 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior05 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior06 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior07 : 1;	/* General Purpose I/O Register 0 Value */
-};
-
-#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR0 */
-
-#define GPIOR00                         0
-#define GPIOR01                         1
-#define GPIOR02                         2
-#define GPIOR03                         3
-#define GPIOR04                         4
-#define GPIOR05                         5
-#define GPIOR06                         6
-#define GPIOR07                         7
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* EEPROM Control Register */
-#define EECR                            _SFR_IO8(0x1F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EECR {
-        unsigned int eere : 1;	/* EEPROM Read Enable */
-        unsigned int eepe : 1;	/* EEPROM Programming Enable */
-        unsigned int eempe : 1;	/* EEPROM Master Write Enable */
-        unsigned int eerie : 1;	/* EEPROM Ready Interrupt Enable */
-        unsigned int eepm : 2;	/* EEPROM Programming Mode */
-        unsigned int : 2;
-};
-
-#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EECR */
-
-#define EERE                            0
-#define EEPE                            1
-#define EEMPE                           2
-#define EERIE                           3
-#define EEPM0                           4
-#define EEPM1                           5
-
-/* EEPROM Data Register */
-#define EEDR                            _SFR_IO8(0x20)
-
-  /* EEDR */
-
-#define EEDR0                           0
-#define EEDR1                           1
-#define EEDR2                           2
-#define EEDR3                           3
-#define EEDR4                           4
-#define EEDR5                           5
-#define EEDR6                           6
-#define EEDR7                           7
-
-/* EEPROM Address Register  Bytes */
-#define EEAR                            _SFR_IO16(0x21)
-#define EEARL                           _SFR_IO8(0x21)
-#define EEARH                           _SFR_IO8(0x22)
-
-/* General Timer/Counter Control Register */
-#define GTCCR                           _SFR_IO8(0x23)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GTCCR {
-        unsigned int psrsync : 1;	/* Prescaler Reset for Synchronous Timer/Counters */
-        unsigned int psrasy : 1;	/* Prescaler Reset Timer/Counter2 */
-        unsigned int : 5;
-        unsigned int tsm : 1;	/* Timer/Counter Synchronization Mode */
-};
-
-#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GTCCR */
-
-#define PSRSYNC                         0
-#define PSR10                           0
-#define PSRASY                          1
-#define PSR2                            1
-#define TSM                             7
-
-/* Timer/Counter0 Control Register A */
-#define TCCR0A                          _SFR_IO8(0x24)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0A {
-        unsigned int wgm0 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com0b : 2;	/* Compare Match Output B Mode */
-        unsigned int com0a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0A */
-
-#define WGM00                           0
-#define WGM01                           1
-#define COM0B0                          4
-#define COM0B1                          5
-#define COM0A0                          6
-#define COM0A1                          7
-
-/* Timer/Counter0 Control Register B */
-#define TCCR0B                          _SFR_IO8(0x25)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0B {
-        unsigned int cs0 : 3;	/* Clock Select */
-        unsigned int wgm02 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc0b : 1;	/* Force Output Compare B */
-        unsigned int foc0a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0B */
-
-#define CS00                            0
-#define CS01                            1
-#define CS02                            2
-#define WGM02                           3
-#define FOC0B                           6
-#define FOC0A                           7
-
-/* Timer/Counter0 Register */
-#define TCNT0                           _SFR_IO8(0x26)
-
-  /* TCNT0 */
-
-#define TCNT0_0                         0
-#define TCNT0_1                         1
-#define TCNT0_2                         2
-#define TCNT0_3                         3
-#define TCNT0_4                         4
-#define TCNT0_5                         5
-#define TCNT0_6                         6
-#define TCNT0_7                         7
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0A                           _SFR_IO8(0x27)
-
-  /* OCR0A */
-
-#define OCR0A_0                         0
-#define OCR0A_1                         1
-#define OCR0A_2                         2
-#define OCR0A_3                         3
-#define OCR0A_4                         4
-#define OCR0A_5                         5
-#define OCR0A_6                         6
-#define OCR0A_7                         7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B                           _SFR_IO8(0x28)
-
-  /* OCR0B */
-
-#define OCR0B_0                         0
-#define OCR0B_1                         1
-#define OCR0B_2                         2
-#define OCR0B_3                         3
-#define OCR0B_4                         4
-#define OCR0B_5                         5
-#define OCR0B_6                         6
-#define OCR0B_7                         7
-
-/* General Purpose IO Register 1 */
-#define GPIOR1                          _SFR_IO8(0x2A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR1 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 1 Value */
-};
-
-#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR1 */
-
-#define GPIOR10                         0
-#define GPIOR11                         1
-#define GPIOR12                         2
-#define GPIOR13                         3
-#define GPIOR14                         4
-#define GPIOR15                         5
-#define GPIOR16                         6
-#define GPIOR17                         7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2                          _SFR_IO8(0x2B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR2 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 2 Value */
-};
-
-#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR2 */
-
-#define GPIOR20                         0
-#define GPIOR21                         1
-#define GPIOR22                         2
-#define GPIOR23                         3
-#define GPIOR24                         4
-#define GPIOR25                         5
-#define GPIOR26                         6
-#define GPIOR27                         7
-
-/* SPI Control Register */
-#define SPCR                            _SFR_IO8(0x2C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPCR {
-        unsigned int spr : 2;	/* SPI Clock Rate Select 1 and 0 */
-        unsigned int cpha : 1;	/* Clock Phase */
-        unsigned int cpol : 1;	/* Clock polarity */
-        unsigned int mstr : 1;	/* Master/Slave Select */
-        unsigned int dord : 1;	/* Data Order */
-        unsigned int spe : 1;	/* SPI Enable */
-        unsigned int spie : 1;	/* SPI Interrupt Enable */
-};
-
-#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPCR */
-
-#define SPR0                            0
-#define SPR1                            1
-#define CPHA                            2
-#define CPOL                            3
-#define MSTR                            4
-#define DORD                            5
-#define SPE                             6
-#define SPIE                            7
-
-/* SPI Status Register */
-#define SPSR                            _SFR_IO8(0x2D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPSR {
-        unsigned int spi2x : 1;	/* Double SPI Speed Bit */
-        unsigned int : 5;
-        unsigned int wcol : 1;	/* Write Collision Flag */
-        unsigned int spif : 1;	/* SPI Interrupt Flag */
-};
-
-#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPSR */
-
-#define SPI2X                           0
-#define WCOL                            6
-#define SPIF                            7
-
-/* SPI Data Register */
-#define SPDR                            _SFR_IO8(0x2E)
-
-  /* SPDR */
-
-#define SPDR0                           0
-#define SPDR1                           1
-#define SPDR2                           2
-#define SPDR3                           3
-#define SPDR4                           4
-#define SPDR5                           5
-#define SPDR6                           6
-#define SPDR7                           7
-
-/* Analog Comparator Control And Status Register */
-#define ACSR                            _SFR_IO8(0x30)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ACSR {
-        unsigned int acis : 2;	/* Analog Comparator Interrupt Mode Select */
-        unsigned int acic : 1;	/* Analog Comparator Input Capture Enable */
-        unsigned int acie : 1;	/* Analog Comparator Interrupt Enable */
-        unsigned int aci : 1;	/* Analog Comparator Interrupt Flag */
-        unsigned int aco : 1;	/* Analog Compare Output */
-        unsigned int acbg : 1;	/* Analog Comparator Bandgap Select */
-        unsigned int acd : 1;	/* Analog Comparator Disable */
-};
-
-#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ACSR */
-
-#define ACIS0                           0
-#define ACIS1                           1
-#define ACIC                            2
-#define ACIE                            3
-#define ACI                             4
-#define ACO                             5
-#define ACBG                            6
-#define ACD                             7
-
-/* On-Chip Debug Register */
-#define OCDR                            _SFR_IO8(0x31)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OCDR {
-        unsigned int ocdr : 8;	/* On-Chip Debug Register Data */
-};
-
-#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OCDR */
-
-#define OCDR0                           0
-#define OCDR1                           1
-#define OCDR2                           2
-#define OCDR3                           3
-#define OCDR4                           4
-#define OCDR5                           5
-#define OCDR6                           6
-#define OCDR7                           7
-#define IDRD                            7
-
-/* Sleep Mode Control Register */
-#define SMCR                            _SFR_IO8(0x33)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SMCR {
-        unsigned int se : 1;	/* Sleep Enable */
-        unsigned int sm : 3;	/* Sleep Mode Select bits */
-        unsigned int : 4;
-};
-
-#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SMCR */
-
-#define SE                              0
-#define SM0                             1
-#define SM1                             2
-#define SM2                             3
-
-/* MCU Status Register */
-#define MCUSR                           _SFR_IO8(0x34)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUSR {
-        unsigned int porf : 1;	/* Power-on Reset Flag */
-        unsigned int extrf : 1;	/* External Reset Flag */
-        unsigned int borf : 1;	/* Brown-out Reset Flag */
-        unsigned int wdrf : 1;	/* Watchdog Reset Flag */
-        unsigned int jtrf : 1;	/* JTAG Reset Flag */
-        unsigned int : 3;
-};
-
-#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUSR */
-
-#define PORF                            0
-#define EXTRF                           1
-#define BORF                            2
-#define WDRF                            3
-#define JTRF                            4
-
-/* MCU Control Register */
-#define MCUCR                           _SFR_IO8(0x35)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUCR {
-        unsigned int ivce : 1;	/* Interrupt Vector Change Enable */
-        unsigned int ivsel : 1;	/* Interrupt Vector Select */
-        unsigned int : 2;
-        unsigned int pud : 1;	/* Pull-up Disable */
-        unsigned int : 2;
-        unsigned int jtd : 1;	/* JTAG Interface Disable */
-};
-
-#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUCR */
-
-#define IVCE                            0
-#define IVSEL                           1
-#define PUD                             4
-#define JTD                             7
-
-/* Store Program Memory Control Register */
-#define SPMCSR                          _SFR_IO8(0x37)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPMCSR {
-        unsigned int spmen : 1;	/* Store Program Memory Enable */
-        unsigned int pgers : 1;	/* Page Erase */
-        unsigned int pgwrt : 1;	/* Page Write */
-        unsigned int blbset : 1;	/* Boot Lock Bit Set */
-        unsigned int rwwsre : 1;	/* Read While Write Section Read Enable */
-        unsigned int sigrd : 1;	/* Signature Row Read */
-        unsigned int rwwsb : 1;	/* Read While Write Section Busy */
-        unsigned int spmie : 1;	/* SPM Interrupt Enable */
-};
-
-#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPMCSR */
-
-#define SPMEN                           0
-#define PGERS                           1
-#define PGWRT                           2
-#define BLBSET                          3
-#define RWWSRE                          4
-#define SIGRD                           5
-#define RWWSB                           6
-#define SPMIE                           7
-
-/* Extended Z-pointer Register for ELPM/SPM */
-#define RAMPZ                           _SFR_IO8(0x3B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RAMPZ {
-        unsigned int rampz0 : 1;	/* Extended Z-Pointer Value */
-        unsigned int : 7;
-};
-
-#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ)
-
-#endif /* __ASSEMBLER__ */
-
-  /* RAMPZ */
-
-#define RAMPZ0                          0
-
-/* Stack Pointer */
-#define SP                              _SFR_IO16(0x3D)
-#define SPL                             _SFR_IO8(0x3D)
-#define SPH                             _SFR_IO8(0x3E)
-
-/* Status Register */
-#define SREG                            _SFR_IO8(0x3F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SREG {
-        unsigned int c : 1;	/* Carry Flag */
-        unsigned int z : 1;	/* Zero Flag */
-        unsigned int n : 1;	/* Negative Flag */
-        unsigned int v : 1;	/* Two's Complement Overflow Flag */
-        unsigned int s : 1;	/* Sign Bit */
-        unsigned int h : 1;	/* Half Carry Flag */
-        unsigned int t : 1;	/* Bit Copy Storage */
-        unsigned int i : 1;	/* Global Interrupt Enable */
-};
-
-#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SREG */
-
-#define SREG_C                          0
-#define SREG_Z                          1
-#define SREG_N                          2
-#define SREG_V                          3
-#define SREG_S                          4
-#define SREG_H                          5
-#define SREG_T                          6
-#define SREG_I                          7
-
-/* Watchdog Timer Control Register */
-#define WDTCSR                          _SFR_MEM8(0x60)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_WDTCSR {
-        unsigned int wdp : 3;	/* Watchdog Timer Prescaler Bits */
-        unsigned int wde : 1;	/* Watch Dog Enable */
-        unsigned int wdce : 1;	/* Watchdog Change Enable */
-        unsigned int : 1;
-        unsigned int wdie : 1;	/* Watchdog Timeout Interrupt Enable */
-        unsigned int wdif : 1;	/* Watchdog Timeout Interrupt Flag */
-};
-
-#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* WDTCSR */
-
-#define WDP0                            0
-#define WDP1                            1
-#define WDP2                            2
-#define WDE                             3
-#define WDCE                            4
-#define WDP3                            5
-#define WDIE                            6
-#define WDIF                            7
-
-/* Clock Prescale Register */
-#define CLKPR                           _SFR_MEM8(0x61)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CLKPR {
-        unsigned int clkps : 4;	/* Clock Prescaler Select Bits */
-        unsigned int : 3;
-        unsigned int clkpce : 1;	/* Clock Prescaler Change Enable */
-};
-
-#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CLKPR */
-
-#define CLKPS0                          0
-#define CLKPS1                          1
-#define CLKPS2                          2
-#define CLKPS3                          3
-#define CLKPCE                          7
-
-/* Power Reduction Register 2 */
-#define PRR2                            _SFR_MEM8(0x63)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR2 {
-        unsigned int prram : 4;	/* Power Reduction SRAMs */
-        unsigned int : 4;
-};
-
-#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR2 */
-
-#define PRRAM0                          0
-#define PRRAM1                          1
-#define PRRAM2                          2
-#define PRRAM3                          3
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
+#define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
+#define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
+#define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
+#define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
+#define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
+#define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
+#define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE7  7
+#define PORTE6  6
+#define PORTE5  5
+#define PORTE4  4
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
+#define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
+#define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
+#define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
+#define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
+#define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
+#define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
+#define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PORTF7  7
+#define PORTF6  6
+#define PORTF5  5
+#define PORTF4  4
+#define PORTF3  3
+#define PORTF2  2
+#define PORTF1  1
+#define PORTF0  0
+
+#define PING    _SFR_IO8(0x12)
+#define PING7   7
+#define PING6   6
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDRG7   7
+// Inserted "DDG7" from "DDRG7" due to compatibility
+#define DDG7    7
+#define DDRG6   6
+// Inserted "DDG6" from "DDRG6" due to compatibility
+#define DDG6    6
+#define DDRG5   5
+// Inserted "DDG5" from "DDRG5" due to compatibility
+#define DDG5    5
+#define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
+#define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
+#define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
+#define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
+#define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PORTG7  7
+#define PORTG6  6
+#define PORTG5  5
+#define PORTG4  4
+#define PORTG3  3
+#define PORTG2  2
+#define PORTG1  1
+#define PORTG0  0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+#define Res0    3
+#define Res1    4
+#define Res2    5
+#define Res3    6
+#define Res4    7
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define OCF1C   3
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+
+#define TIFR3   _SFR_IO8(0x18)
+#define TOV3    0
+#define OCF3A   1
+#define OCF3B   2
+#define OCF3C   3
+#define ICF3    5
+
+#define TIFR4   _SFR_IO8(0x19)
+#define TOV4    0
+#define OCF4A   1
+#define OCF4B   2
+#define OCF4C   3
+#define ICF4    5
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define TOV5    0
+#define OCF5A   1
+#define OCF5B   2
+#define OCF5C   3
+#define ICF5    5
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+#define INTF2   2
+#define INTF3   3
+#define INTF4   4
+#define INTF5   5
+#define INTF6   6
+#define INTF7   7
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+#define INT2    2
+#define INT3    3
+#define INT4    4
+#define INT5    5
+#define INT6    6
+#define INT7    7
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define PSRASY  1
+#define TSM     7
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define OCDR    _SFR_IO8(0x31)
+#define OCDR0   0
+#define OCDR1   1
+#define OCDR2   2
+#define OCDR3   3
+#define OCDR4   4
+#define OCDR5   5
+#define OCDR6   6
+#define OCDR7   7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0x3B)
+#define RAMPZ0  0
+#define Res5    6
+#define Res6    7
+
+/* Reserved [0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62] */
+
+#define PRR2    _SFR_MEM8(0x63)
+#define PRRAM0  0
+#define PRRAM1  1
+#define PRRAM2  2
+#define PRRAM3  3
 
 #define __AVR_HAVE_PRR2	((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3))
 #define __AVR_HAVE_PRR2_PRRAM0
@@ -1237,36 +614,15 @@
 #define __AVR_HAVE_PRR2_PRRAM2
 #define __AVR_HAVE_PRR2_PRRAM3
 
-/* Power Reduction Register0 */
-#define PRR0                            _SFR_MEM8(0x64)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR0 {
-        unsigned int pradc : 1;	/* Power Reduction ADC */
-        unsigned int prusart0 : 1;	/* Power Reduction USART */
-        unsigned int prspi : 1;	/* Power Reduction Serial Peripheral Interface */
-        unsigned int prtim1 : 1;	/* Power Reduction Timer/Counter1 */
-        unsigned int prpga : 1;	/* Power Reduction PGA */
-        unsigned int prtim0 : 1;	/* Power Reduction Timer/Counter0 */
-        unsigned int prtim2 : 1;	/* Power Reduction Timer/Counter2 */
-        unsigned int prtwi : 1;	/* Power Reduction TWI */
-};
-
-#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR0 */
-
-#define PRADC                           0
-#define PRUSART0                        1
-#define PRSPI                           2
-#define PRTIM1                          3
-#define PRPGA                           4
-#define PRTIM0                          5
-#define PRTIM2                          6
-#define PRTWI                           7
+#define PRR0    _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRPGA   4
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
 
 #define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
 #define __AVR_HAVE_PRR0_PRADC
@@ -1278,32 +634,13 @@
 #define __AVR_HAVE_PRR0_PRTIM2
 #define __AVR_HAVE_PRR0_PRTWI
 
-/* Power Reduction Register 1 */
-#define PRR1                            _SFR_MEM8(0x65)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR1 {
-        unsigned int prusart1 : 1;	/* Power Reduction USART1 */
-        unsigned int : 2;
-        unsigned int prtim3 : 1;	/* Power Reduction Timer/Counter3 */
-        unsigned int prtim4 : 1;	/* Power Reduction Timer/Counter4 */
-        unsigned int prtim5 : 1;	/* Power Reduction Timer/Counter5 */
-        unsigned int prtrx24 : 1;	/* Power Reduction Transceiver */
-        unsigned int : 1;
-};
-
-#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR1 */
-
-#define PRUSART1                        0
-#define PRTIM3                          3
-#define PRTIM4                          4
-#define PRTIM5                          5
-#define PRTRX24                         6
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSART1 0
+#define PRTIM3  3
+#define PRTIM4  4
+#define PRTIM5  5
+#define PRTRX24 6
+#define Res     7
 
 #define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24))
 #define __AVR_HAVE_PRR1_PRUSART1
@@ -1312,4975 +649,2060 @@
 #define __AVR_HAVE_PRR1_PRTIM5
 #define __AVR_HAVE_PRR1_PRTRX24
 
-/* Oscillator Calibration Value */
-#define OSCCAL                          _SFR_MEM8(0x66)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OSCCAL {
-        unsigned int cal : 8;	/* Oscillator Calibration Tuning Value */
-};
-
-#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OSCCAL */
-
-#define CAL0                            0
-#define CAL1                            1
-#define CAL2                            2
-#define CAL3                            3
-#define CAL4                            4
-#define CAL5                            5
-#define CAL6                            6
-#define CAL7                            7
-
-/* Reference Voltage Calibration Register */
-#define BGCR                            _SFR_MEM8(0x67)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BGCR {
-        unsigned int bgcal : 3;	/* Coarse Calibration Bits */
-        unsigned int bgcal_fine : 4;	/* Fine Calibration Bits */
-        unsigned int : 1;
-};
-
-#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* BGCR */
-
-#define BGCAL0                          0
-#define BGCAL1                          1
-#define BGCAL2                          2
-#define BGCAL_FINE0                     3
-#define BGCAL_FINE1                     4
-#define BGCAL_FINE2                     5
-#define BGCAL_FINE3                     6
-
-/* Pin Change Interrupt Control Register */
-#define PCICR                           _SFR_MEM8(0x68)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCICR {
-        unsigned int pcie : 3;	/* Pin Change Interrupt Enables */
-        unsigned int : 5;
-};
-
-#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCICR */
-
-#define PCIE0                           0
-#define PCIE1                           1
-#define PCIE2                           2
-
-/* External Interrupt Control Register A */
-#define EICRA                           _SFR_MEM8(0x69)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRA {
-        unsigned int isc0 : 2;	/* External Interrupt 0 Sense Control Bit */
-        unsigned int isc1 : 2;	/* External Interrupt 1 Sense Control Bit */
-        unsigned int isc2 : 2;	/* External Interrupt 2 Sense Control Bit */
-        unsigned int isc3 : 2;	/* External Interrupt 3 Sense Control Bit */
-};
-
-#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRA */
-
-#define ISC00                           0
-#define ISC01                           1
-#define ISC10                           2
-#define ISC11                           3
-#define ISC20                           4
-#define ISC21                           5
-#define ISC30                           6
-#define ISC31                           7
-
-/* External Interrupt Control Register B */
-#define EICRB                           _SFR_MEM8(0x6A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRB {
-        unsigned int isc4 : 2;	/* External Interrupt 4 Sense Control Bit */
-        unsigned int isc5 : 2;	/* External Interrupt 5 Sense Control Bit */
-        unsigned int isc6 : 2;	/* External Interrupt 6 Sense Control Bit */
-        unsigned int isc7 : 2;	/* External Interrupt 7 Sense Control Bit */
-};
-
-#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRB */
-
-#define ISC40                           0
-#define ISC41                           1
-#define ISC50                           2
-#define ISC51                           3
-#define ISC60                           4
-#define ISC61                           5
-#define ISC70                           6
-#define ISC71                           7
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0                          _SFR_MEM8(0x6B)
-
-  /* PCMSK0 */
-
-#define PCINT0                          0
-#define PCINT1                          1
-#define PCINT2                          2
-#define PCINT3                          3
-#define PCINT4                          4
-#define PCINT5                          5
-#define PCINT6                          6
-#define PCINT7                          7
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1                          _SFR_MEM8(0x6C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK1 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK1 */
-
-#define PCINT8                          0
-#define PCINT9                          1
-#define PCINT10                         2
-#define PCINT11                         3
-#define PCINT12                         4
-#define PCINT13                         5
-#define PCINT14                         6
-#define PCINT15                         7
-
-/* Pin Change Mask Register 2 */
-#define PCMSK2                          _SFR_MEM8(0x6D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK2 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK2 */
-
-#define PCINT16                         0
-#define PCINT17                         1
-#define PCINT18                         2
-#define PCINT19                         3
-#define PCINT20                         4
-#define PCINT21                         5
-#define PCINT22                         6
-#define PCINT23                         7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0                          _SFR_MEM8(0x6E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK0 {
-        unsigned int toie0 : 1;	/* Timer/Counter0 Overflow Interrupt Enable */
-        unsigned int ocie0a : 1;	/* Timer/Counter0 Output Compare Match A Interrupt Enable */
-        unsigned int ocie0b : 1;	/* Timer/Counter0 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK0 */
-
-#define TOIE0                           0
-#define OCIE0A                          1
-#define OCIE0B                          2
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1                          _SFR_MEM8(0x6F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK1 {
-        unsigned int toie1 : 1;	/* Timer/Counter1 Overflow Interrupt Enable */
-        unsigned int ocie1a : 1;	/* Timer/Counter1 Output Compare A Match Interrupt Enable */
-        unsigned int ocie1b : 1;	/* Timer/Counter1 Output Compare B Match Interrupt Enable */
-        unsigned int ocie1c : 1;	/* Timer/Counter1 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie1 : 1;	/* Timer/Counter1 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK1 */
-
-#define TOIE1                           0
-#define OCIE1A                          1
-#define OCIE1B                          2
-#define OCIE1C                          3
-#define ICIE1                           5
-
-/* Timer/Counter Interrupt Mask register */
-#define TIMSK2                          _SFR_MEM8(0x70)
+#define OSCCAL  _SFR_MEM8(0x66)
+#define CAL0    0
+#define CAL1    1
+#define CAL2    2
+#define CAL3    3
+#define CAL4    4
+#define CAL5    5
+#define CAL6    6
+#define CAL7    7
+
+#define BGCR    _SFR_MEM8(0x67)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL_FINE0 3
+#define BGCAL_FINE1 4
+#define BGCAL_FINE2 5
+#define BGCAL_FINE3 6
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+#define ISC20   4
+#define ISC21   5
+#define ISC30   6
+#define ISC31   7
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC40   0
+#define ISC41   1
+#define ISC50   2
+#define ISC51   3
+#define ISC60   4
+#define ISC61   5
+#define ISC70   6
+#define ISC71   7
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define OCIE1C  3
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define TOIE3   0
+#define OCIE3A  1
+#define OCIE3B  2
+#define OCIE3C  3
+#define ICIE3   5
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define TOIE4   0
+#define OCIE4A  1
+#define OCIE4B  2
+#define OCIE4C  3
+#define ICIE4   5
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define TOIE5   0
+#define OCIE5A  1
+#define OCIE5B  2
+#define OCIE5C  3
+#define ICIE5   5
+
+/* Reserved [0x74] */
+
+#define NEMCR   _SFR_MEM8(0x75)
+#define AEAM0   4
+#define AEAM1   5
+#define ENEAM   6
+
+/* Reserved [0x76] */
+
+#define ADCSRC  _SFR_MEM8(0x77)
+#define ADSUT0  0
+#define ADSUT1  1
+#define ADSUT2  2
+#define ADSUT3  3
+#define ADSUT4  4
+#define ADTHT0  6
+#define ADTHT1  7
 
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK2 {
-        unsigned int toie2 : 1;	/* Timer/Counter2 Overflow Interrupt Enable */
-        unsigned int ocie2a : 1;	/* Timer/Counter2 Output Compare Match A Interrupt Enable */
-        unsigned int ocie2b : 1;	/* Timer/Counter2 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK2 */
-
-#define TOIE2                           0
-#define TOIE2A                          0
-#define OCIE2A                          1
-#define OCIE2B                          2
-
-/* Timer/Counter3 Interrupt Mask Register */
-#define TIMSK3                          _SFR_MEM8(0x71)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK3 {
-        unsigned int toie3 : 1;	/* Timer/Counter3 Overflow Interrupt Enable */
-        unsigned int ocie3a : 1;	/* Timer/Counter3 Output Compare A Match Interrupt Enable */
-        unsigned int ocie3b : 1;	/* Timer/Counter3 Output Compare B Match Interrupt Enable */
-        unsigned int ocie3c : 1;	/* Timer/Counter3 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie3 : 1;	/* Timer/Counter3 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK3 */
-
-#define TOIE3                           0
-#define OCIE3A                          1
-#define OCIE3B                          2
-#define OCIE3C                          3
-#define ICIE3                           5
-
-/* Timer/Counter4 Interrupt Mask Register */
-#define TIMSK4                          _SFR_MEM8(0x72)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK4 {
-        unsigned int toie4 : 1;	/* Timer/Counter4 Overflow Interrupt Enable */
-        unsigned int ocie4a : 1;	/* Timer/Counter4 Output Compare A Match Interrupt Enable */
-        unsigned int ocie4b : 1;	/* Timer/Counter4 Output Compare B Match Interrupt Enable */
-        unsigned int ocie4c : 1;	/* Timer/Counter4 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie4 : 1;	/* Timer/Counter4 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK4 */
-
-#define TOIE4                           0
-#define OCIE4A                          1
-#define OCIE4B                          2
-#define OCIE4C                          3
-#define ICIE4                           5
-
-/* Timer/Counter5 Interrupt Mask Register */
-#define TIMSK5                          _SFR_MEM8(0x73)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK5 {
-        unsigned int toie5 : 1;	/* Timer/Counter5 Overflow Interrupt Enable */
-        unsigned int ocie5a : 1;	/* Timer/Counter5 Output Compare A Match Interrupt Enable */
-        unsigned int ocie5b : 1;	/* Timer/Counter5 Output Compare B Match Interrupt Enable */
-        unsigned int ocie5c : 1;	/* Timer/Counter5 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie5 : 1;	/* Timer/Counter5 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK5 */
-
-#define TOIE5                           0
-#define OCIE5A                          1
-#define OCIE5B                          2
-#define OCIE5C                          3
-#define ICIE5                           5
-
-/* Flash Extended-Mode Control-Register */
-#define NEMCR                           _SFR_MEM8(0x75)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_NEMCR {
-        unsigned int : 4;
-        unsigned int aeam : 2;	/* Address for Extended Address Mode of Extra Rows */
-        unsigned int eneam : 1;	/* Enable Extended Address Mode for Extra Rows */
-        unsigned int : 1;
-};
-
-#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* NEMCR */
-
-#define AEAM0                           4
-#define AEAM1                           5
-#define ENEAM                           6
-
-/* The ADC Control and Status Register C */
-#define ADCSRC                          _SFR_MEM8(0x77)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRC {
-        unsigned int adsut : 5;	/* ADC Start-up Time */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int adtht : 2;	/* ADC Track-and-Hold Time */
-};
-
-#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRC */
-
-#define ADSUT0                          0
-#define ADSUT1                          1
-#define ADSUT2                          2
-#define ADSUT3                          3
-#define ADSUT4                          4
-#define ADTHT0                          6
-#define ADTHT1                          7
-
-/* ADC Data Register  Bytes */
+/* Combine ADCL and ADCH */
 #ifndef __ASSEMBLER__
-#define ADC                             _SFR_MEM16(0x78)
-#define ADCL                            _SFR_MEM8(0x78)
-#define ADCH                            _SFR_MEM8(0x79)
-#endif /* __ASSEMBLER__ */
-#define ADCW                            _SFR_MEM16(0x78)
-#define ADCWL                           _SFR_MEM8(0x78)
-#define ADCWH                           _SFR_MEM8(0x79)
-
-/* The ADC Control and Status Register A */
-#define ADCSRA                          _SFR_MEM8(0x7A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRA {
-        unsigned int adps : 3;	/* ADC  Prescaler Select Bits */
-        unsigned int adie : 1;	/* ADC Interrupt Enable */
-        unsigned int adif : 1;	/* ADC Interrupt Flag */
-        unsigned int adate : 1;	/* ADC Auto Trigger Enable */
-        unsigned int adsc : 1;	/* ADC Start Conversion */
-        unsigned int aden : 1;	/* ADC Enable */
-};
-
-#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRA */
-
-#define ADPS0                           0
-#define ADPS1                           1
-#define ADPS2                           2
-#define ADIE                            3
-#define ADIF                            4
-#define ADATE                           5
-#define ADSC                            6
-#define ADEN                            7
-
-/* ADC Control and Status Register B */
-#define ADCSRB                          _SFR_MEM8(0x7B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRB {
-        unsigned int adts : 3;	/* ADC Auto Trigger Source */
-        unsigned int mux5 : 1;	/* Analog Channel and Gain Selection Bits */
-        unsigned int acch : 1;	/* Analog Channel Change */
-        unsigned int refok : 1;	/* Reference Voltage OK */
-        unsigned int acme : 1;	/* Analog Comparator Multiplexer Enable */
-        unsigned int avddok : 1;	/* AVDD Supply Voltage OK */
-};
-
-#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRB */
-
-#define ADTS0                           0
-#define ADTS1                           1
-#define ADTS2                           2
-#define MUX5                            3
-#define ACCH                            4
-#define REFOK                           5
-#define ACME                            6
-#define AVDDOK                          7
-
-/* The ADC Multiplexer Selection Register */
-#define ADMUX                           _SFR_MEM8(0x7C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADMUX {
-        unsigned int mux : 5;	/* Analog Channel and Gain Selection Bits */
-        unsigned int adlar : 1;	/* ADC Left Adjust Result */
-        unsigned int refs : 2;	/* Reference Selection Bits */
-};
-
-#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADMUX */
-
-#define MUX0                            0
-#define MUX1                            1
-#define MUX2                            2
-#define MUX3                            3
-#define MUX4                            4
-#define ADLAR                           5
-#define REFS0                           6
-#define REFS1                           7
-
-/* Digital Input Disable Register 2 */
-#define DIDR2                           _SFR_MEM8(0x7D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR2 {
-        unsigned int adc8d : 1;	/* Reserved Bits */
-        unsigned int adc9d : 1;	/* Reserved Bits */
-        unsigned int adc10d : 1;	/* Reserved Bits */
-        unsigned int adc11d : 1;	/* Reserved Bits */
-        unsigned int adc12d : 1;	/* Reserved Bits */
-        unsigned int adc13d : 1;	/* Reserved Bits */
-        unsigned int adc14d : 1;	/* Reserved Bits */
-        unsigned int adc15d : 1;	/* Reserved Bits */
-};
-
-#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR2 */
-
-#define ADC8D                           0
-#define ADC9D                           1
-#define ADC10D                          2
-#define ADC11D                          3
-#define ADC12D                          4
-#define ADC13D                          5
-#define ADC14D                          6
-#define ADC15D                          7
-
-/* Digital Input Disable Register 0 */
-#define DIDR0                           _SFR_MEM8(0x7E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR0 {
-        unsigned int adc0d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc1d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc2d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc3d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc4d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc5d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc6d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc7d : 1;	/* Disable ADC7:0 Digital Input */
-};
-
-#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR0 */
-
-#define ADC0D                           0
-#define ADC1D                           1
-#define ADC2D                           2
-#define ADC3D                           3
-#define ADC4D                           4
-#define ADC5D                           5
-#define ADC6D                           6
-#define ADC7D                           7
-
-/* Digital Input Disable Register 1 */
-#define DIDR1                           _SFR_MEM8(0x7F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR1 {
-        unsigned int ain0d : 1;	/* AIN0 Digital Input Disable */
-        unsigned int ain1d : 1;	/* AIN1 Digital Input Disable */
-        unsigned int : 6;
-};
-
-#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR1 */
-
-#define AIN0D                           0
-#define AIN1D                           1
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A                          _SFR_MEM8(0x80)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1A {
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int com1c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com1b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com1a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1A */
-
-#define WGM10                           0
-#define WGM11                           1
-#define COM1C0                          2
-#define COM1C1                          3
-#define COM1B0                          4
-#define COM1B1                          5
-#define COM1A0                          6
-#define COM1A1                          7
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B                          _SFR_MEM8(0x81)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1B {
-        unsigned int cs1 : 3;	/* Clock Select */
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices1 : 1;	/* Input Capture 1 Edge Select */
-        unsigned int icnc1 : 1;	/* Input Capture 1 Noise Canceller */
-};
-
-#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1B */
-
-#define CS10                            0
-#define CS11                            1
-#define CS12                            2
-#define WGM12                           3
-#define WGM13                           4
-#define ICES1                           6
-#define ICNC1                           7
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C                          _SFR_MEM8(0x82)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1C {
-        unsigned int : 5;
-        unsigned int foc1c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc1b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc1a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1C */
-
-#define FOC1C                           5
-#define FOC1B                           6
-#define FOC1A                           7
-
-/* Timer/Counter1  Bytes */
-#define TCNT1                           _SFR_MEM16(0x84)
-#define TCNT1L                          _SFR_MEM8(0x84)
-#define TCNT1H                          _SFR_MEM8(0x85)
-
-/* Timer/Counter1 Input Capture Register  Bytes */
-#define ICR1                            _SFR_MEM16(0x86)
-#define ICR1L                           _SFR_MEM8(0x86)
-#define ICR1H                           _SFR_MEM8(0x87)
-
-/* Timer/Counter1 Output Compare Register A  Bytes */
-#define OCR1A                           _SFR_MEM16(0x88)
-#define OCR1AL                          _SFR_MEM8(0x88)
-#define OCR1AH                          _SFR_MEM8(0x89)
-
-/* Timer/Counter1 Output Compare Register B  Bytes */
-#define OCR1B                           _SFR_MEM16(0x8A)
-#define OCR1BL                          _SFR_MEM8(0x8A)
-#define OCR1BH                          _SFR_MEM8(0x8B)
-
-/* Timer/Counter1 Output Compare Register C  Bytes */
-#define OCR1C                           _SFR_MEM16(0x8C)
-#define OCR1CL                          _SFR_MEM8(0x8C)
-#define OCR1CH                          _SFR_MEM8(0x8D)
-
-/* Timer/Counter3 Control Register A */
-#define TCCR3A                          _SFR_MEM8(0x90)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3A {
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int com3c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com3b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com3a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3A */
-
-#define WGM30                           0
-#define WGM31                           1
-#define COM3C0                          2
-#define COM3C1                          3
-#define COM3B0                          4
-#define COM3B1                          5
-#define COM3A0                          6
-#define COM3A1                          7
-
-/* Timer/Counter3 Control Register B */
-#define TCCR3B                          _SFR_MEM8(0x91)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3B {
-        unsigned int cs3 : 3;	/* Clock Select */
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices3 : 1;	/* Input Capture 3 Edge Select */
-        unsigned int icnc3 : 1;	/* Input Capture 3 Noise Canceller */
-};
-
-#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3B */
-
-#define CS30                            0
-#define CS31                            1
-#define CS32                            2
-#define WGM32                           3
-#define WGM33                           4
-#define ICES3                           6
-#define ICNC3                           7
-
-/* Timer/Counter3 Control Register C */
-#define TCCR3C                          _SFR_MEM8(0x92)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3C {
-        unsigned int : 5;
-        unsigned int foc3c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc3b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc3a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3C */
-
-#define FOC3C                           5
-#define FOC3B                           6
-#define FOC3A                           7
-
-/* Timer/Counter3  Bytes */
-#define TCNT3                           _SFR_MEM16(0x94)
-#define TCNT3L                          _SFR_MEM8(0x94)
-#define TCNT3H                          _SFR_MEM8(0x95)
-
-/* Timer/Counter3 Input Capture Register  Bytes */
-#define ICR3                            _SFR_MEM16(0x96)
-#define ICR3L                           _SFR_MEM8(0x96)
-#define ICR3H                           _SFR_MEM8(0x97)
-
-/* Timer/Counter3 Output Compare Register A  Bytes */
-#define OCR3A                           _SFR_MEM16(0x98)
-#define OCR3AL                          _SFR_MEM8(0x98)
-#define OCR3AH                          _SFR_MEM8(0x99)
-
-/* Timer/Counter3 Output Compare Register B  Bytes */
-#define OCR3B                           _SFR_MEM16(0x9A)
-#define OCR3BL                          _SFR_MEM8(0x9A)
-#define OCR3BH                          _SFR_MEM8(0x9B)
-
-/* Timer/Counter3 Output Compare Register C  Bytes */
-#define OCR3C                           _SFR_MEM16(0x9C)
-#define OCR3CL                          _SFR_MEM8(0x9C)
-#define OCR3CH                          _SFR_MEM8(0x9D)
-
-/* Timer/Counter4 Control Register A */
-#define TCCR4A                          _SFR_MEM8(0xA0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4A {
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int com4c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com4b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com4a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4A */
-
-#define WGM40                           0
-#define WGM41                           1
-#define COM4C0                          2
-#define COM4C1                          3
-#define COM4B0                          4
-#define COM4B1                          5
-#define COM4A0                          6
-#define COM4A1                          7
-
-/* Timer/Counter4 Control Register B */
-#define TCCR4B                          _SFR_MEM8(0xA1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4B {
-        unsigned int cs4 : 3;	/* Clock Select */
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices4 : 1;	/* Input Capture 4 Edge Select */
-        unsigned int icnc4 : 1;	/* Input Capture 4 Noise Canceller */
-};
-
-#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4B */
-
-#define CS40                            0
-#define CS41                            1
-#define CS42                            2
-#define WGM42                           3
-#define WGM43                           4
-#define ICES4                           6
-#define ICNC4                           7
-
-/* Timer/Counter4 Control Register C */
-#define TCCR4C                          _SFR_MEM8(0xA2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4C {
-        unsigned int : 5;
-        unsigned int foc4c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc4b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc4a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4C */
-
-#define FOC4C                           5
-#define FOC4B                           6
-#define FOC4A                           7
-
-/* Timer/Counter4  Bytes */
-#define TCNT4                           _SFR_MEM16(0xA4)
-#define TCNT4L                          _SFR_MEM8(0xA4)
-#define TCNT4H                          _SFR_MEM8(0xA5)
-
-/* Timer/Counter4 Input Capture Register  Bytes */
-#define ICR4                            _SFR_MEM16(0xA6)
-#define ICR4L                           _SFR_MEM8(0xA6)
-#define ICR4H                           _SFR_MEM8(0xA7)
-
-/* Timer/Counter4 Output Compare Register A  Bytes */
-#define OCR4A                           _SFR_MEM16(0xA8)
-#define OCR4AL                          _SFR_MEM8(0xA8)
-#define OCR4AH                          _SFR_MEM8(0xA9)
-
-/* Timer/Counter4 Output Compare Register B  Bytes */
-#define OCR4B                           _SFR_MEM16(0xAA)
-#define OCR4BL                          _SFR_MEM8(0xAA)
-#define OCR4BH                          _SFR_MEM8(0xAB)
-
-/* Timer/Counter4 Output Compare Register C  Bytes */
-#define OCR4C                           _SFR_MEM16(0xAC)
-#define OCR4CL                          _SFR_MEM8(0xAC)
-#define OCR4CH                          _SFR_MEM8(0xAD)
-
-/* Timer/Counter2 Control Register A */
-#define TCCR2A                          _SFR_MEM8(0xB0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2A {
-        unsigned int wgm2 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com2b : 2;	/* Compare Match Output B Mode */
-        unsigned int com2a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2A */
-
-#define WGM20                           0
-#define WGM21                           1
-#define COM2B0                          4
-#define COM2B1                          5
-#define COM2A0                          6
-#define COM2A1                          7
-
-/* Timer/Counter2 Control Register B */
-#define TCCR2B                          _SFR_MEM8(0xB1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2B {
-        unsigned int cs2 : 3;	/* Clock Select */
-        unsigned int wgm22 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc2b : 1;	/* Force Output Compare B */
-        unsigned int foc2a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2B */
-
-#define CS20                            0
-#define CS21                            1
-#define CS22                            2
-#define WGM22                           3
-#define FOC2B                           6
-#define FOC2A                           7
-
-/* Timer/Counter2 */
-#define TCNT2                           _SFR_MEM8(0xB2)
-
-  /* TCNT2 */
-
-#define TCNT20                          0
-#define TCNT21                          1
-#define TCNT22                          2
-#define TCNT23                          3
-#define TCNT24                          4
-#define TCNT25                          5
-#define TCNT26                          6
-#define TCNT27                          7
-
-/* Timer/Counter2 Output Compare Register A */
-#define OCR2A                           _SFR_MEM8(0xB3)
-
-  /* OCR2A */
-
-#define OCR2A0                          0
-#define OCR2A1                          1
-#define OCR2A2                          2
-#define OCR2A3                          3
-#define OCR2A4                          4
-#define OCR2A5                          5
-#define OCR2A6                          6
-#define OCR2A7                          7
-
-/* Timer/Counter2 Output Compare Register B */
-#define OCR2B                           _SFR_MEM8(0xB4)
-
-  /* OCR2B */
-
-#define OCR2B0                          0
-#define OCR2B1                          1
-#define OCR2B2                          2
-#define OCR2B3                          3
-#define OCR2B4                          4
-#define OCR2B5                          5
-#define OCR2B6                          6
-#define OCR2B7                          7
-
-/* Asynchronous Status Register */
-#define ASSR                            _SFR_MEM8(0xB6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ASSR {
-        unsigned int tcr2bub : 1;	/* Timer/Counter2 Control Register B Update Busy */
-        unsigned int tcr2aub : 1;	/* Timer/Counter2 Control Register A Update Busy */
-        unsigned int ocr2bub : 1;	/* Timer/Counter2 Output Compare Register B Update Busy */
-        unsigned int ocr2aub : 1;	/* Timer/Counter2 Output Compare Register A Update Busy */
-        unsigned int tcn2ub : 1;	/* Timer/Counter2 Update Busy */
-        unsigned int as2 : 1;	/* Timer/Counter2 Asynchronous Mode */
-        unsigned int exclk : 1;	/* Enable External Clock Input */
-        unsigned int exclkamr : 1;	/* Enable External Clock Input for AMR */
-};
-
-#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ASSR */
-
-#define TCR2BUB                         0
-#define TCR2AUB                         1
-#define OCR2BUB                         2
-#define OCR2AUB                         3
-#define TCN2UB                          4
-#define AS2                             5
-#define EXCLK                           6
-#define EXCLKAMR                        7
-
-/* TWI Bit Rate Register */
-#define TWBR                            _SFR_MEM8(0xB8)
-
-  /* TWBR */
-
-#define TWBR0                           0
-#define TWBR1                           1
-#define TWBR2                           2
-#define TWBR3                           3
-#define TWBR4                           4
-#define TWBR5                           5
-#define TWBR6                           6
-#define TWBR7                           7
-
-/* TWI Status Register */
-#define TWSR                            _SFR_MEM8(0xB9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWSR {
-        unsigned int twps : 2;	/* TWI Prescaler Bits */
-        unsigned int : 1;
-        unsigned int tws : 5;	/* TWI Status */
-};
-
-#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWSR */
-
-#define TWPS0                           0
-#define TWPS1                           1
-#define TWS3                            3
-#define TWS4                            4
-#define TWS5                            5
-#define TWS6                            6
-#define TWS7                            7
-
-/* TWI (Slave) Address Register */
-#define TWAR                            _SFR_MEM8(0xBA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAR {
-        unsigned int twgce : 1;	/* TWI General Call Recognition Enable Bit */
-        unsigned int twa : 7;	/* TWI (Slave) Address */
-};
-
-#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAR */
-
-#define TWGCE                           0
-#define TWA0                            1
-#define TWA1                            2
-#define TWA2                            3
-#define TWA3                            4
-#define TWA4                            5
-#define TWA5                            6
-#define TWA6                            7
-
-/* TWI Data Register */
-#define TWDR                            _SFR_MEM8(0xBB)
-
-  /* TWDR */
-
-#define TWD0                            0
-#define TWD1                            1
-#define TWD2                            2
-#define TWD3                            3
-#define TWD4                            4
-#define TWD5                            5
-#define TWD6                            6
-#define TWD7                            7
-
-/* TWI Control Register */
-#define TWCR                            _SFR_MEM8(0xBC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWCR {
-        unsigned int twie : 1;	/* TWI Interrupt Enable */
-        unsigned int : 1;
-        unsigned int twen : 1;	/* TWI Enable Bit */
-        unsigned int twwc : 1;	/* TWI Write Collision Flag */
-        unsigned int twsto : 1;	/* TWI STOP Condition Bit */
-        unsigned int twsta : 1;	/* TWI START Condition Bit */
-        unsigned int twea : 1;	/* TWI Enable Acknowledge Bit */
-        unsigned int twint : 1;	/* TWI Interrupt Flag */
-};
-
-#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWCR */
-
-#define TWIE                            0
-#define TWEN                            2
-#define TWWC                            3
-#define TWSTO                           4
-#define TWSTA                           5
-#define TWEA                            6
-#define TWINT                           7
-
-/* TWI (Slave) Address Mask Register */
-#define TWAMR                           _SFR_MEM8(0xBD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAMR {
-        unsigned int : 1;
-        unsigned int twam : 7;	/* TWI Address Mask */
-};
-
-#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAMR */
-
-#define TWAM0                           1
-#define TWAMR0                          1
-#define TWAM1                           2
-#define TWAMR1                          2
-#define TWAM2                           3
-#define TWAMR2                          3
-#define TWAM3                           4
-#define TWAMR3                          4
-#define TWAM4                           5
-#define TWAMR4                          5
-#define TWAM5                           6
-#define TWAMR5                          6
-#define TWAM6                           7
-#define TWAMR6                          7
-
-/* Transceiver Interrupt Enable Register 1 */
-#define IRQ_MASK1                       _SFR_MEM8(0xBE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK1 {
-        unsigned int tx_start_en : 1;	/* Transmit Start Interrupt enable */
-        unsigned int maf_0_ami_en : 1;	/* Address Match Interrupt enable Address filter 0 */
-        unsigned int maf_1_ami_en : 1;	/* Address Match Interrupt enable Address filter 1 */
-        unsigned int maf_2_ami_en : 1;	/* Address Match Interrupt enable Address filter 2 */
-        unsigned int maf_3_ami_en : 1;	/* Address Match Interrupt enable Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_MASK1_struct _SFR_MEM8_STRUCT(0xbe, struct __reg_IRQ_MASK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK1 */
-
-#define TX_START_EN                     0
-#define MAF_0_AMI_EN                    1
-#define MAF_1_AMI_EN                    2
-#define MAF_2_AMI_EN                    3
-#define MAF_3_AMI_EN                    4
-
-/* Transceiver Interrupt Status Register 1 */
-#define IRQ_STATUS1                     _SFR_MEM8(0xBF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS1 {
-        unsigned int tx_start : 1;	/* Transmit Start Interrupt Status */
-        unsigned int maf_0_ami : 1;	/* Address Match Interrupt Status Address filter 0 */
-        unsigned int maf_1_ami : 1;	/* Address Match Interrupt Status Address filter 1 */
-        unsigned int maf_2_ami : 1;	/* Address Match Interrupt Status Address filter 2 */
-        unsigned int maf_3_ami : 1;	/* Address Match Interrupt Status Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_STATUS1_struct _SFR_MEM8_STRUCT(0xbf, struct __reg_IRQ_STATUS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS1 */
-
-#define TX_START                        0
-#define MAF_0_AMI                       1
-#define MAF_1_AMI                       2
-#define MAF_2_AMI                       3
-#define MAF_3_AMI                       4
-
-/* USART0 Control and Status Register A */
-#define UCSR0A                          _SFR_MEM8(0xC0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0A {
-        unsigned int mpcm0 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x0 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe0 : 1;	/* USART Parity Error */
-        unsigned int dor0 : 1;	/* Data OverRun */
-        unsigned int fe0 : 1;	/* Frame Error */
-        unsigned int udre0 : 1;	/* USART Data Register Empty */
-        unsigned int txc0 : 1;	/* USART Transmit Complete */
-        unsigned int rxc0 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0A */
-
-#define MPCM0                           0
-#define U2X0                            1
-#define UPE0                            2
-#define DOR0                            3
-#define FE0                             4
-#define UDRE0                           5
-#define TXC0                            6
-#define RXC0                            7
-
-/* USART0 Control and Status Register B */
-#define UCSR0B                          _SFR_MEM8(0xC1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0B {
-        unsigned int txb80 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb80 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz02 : 1;	/* Character Size */
-        unsigned int txen0 : 1;	/* Transmitter Enable */
-        unsigned int rxen0 : 1;	/* Receiver Enable */
-        unsigned int udrie0 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie0 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie0 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0B */
-
-#define TXB80                           0
-#define RXB80                           1
-#define UCSZ02                          2
-#define TXEN0                           3
-#define RXEN0                           4
-#define UDRIE0                          5
-#define TXCIE0                          6
-#define RXCIE0                          7
-
-/* USART0 Control and Status Register C */
-#define UCSR0C                          _SFR_MEM8(0xC2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0C {
-        unsigned int ucpol0 : 1;	/* Clock Polarity */
-        unsigned int ucsz0 : 2;	/* Character Size */
-        unsigned int ucpha0 : 1;	/* Clock Phase */
-        unsigned int udord0 : 1;	/* Data Order */
-        unsigned int usbs0 : 1;	/* Stop Bit Select */
-        unsigned int upm0 : 2;	/* Parity Mode */
-        unsigned int umsel0 : 2;	/* USART Mode Select */
-};
-
-#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0C */
-
-#define UCPOL0                          0
-#define UCPHA0                          1
-#define UCPHA0                          1
-#define UCSZ00                          1
-#define UDORD0                          2
-#define UDORD0                          2
-#define UCSZ01                          2
-#define USBS0                           3
-#define UPM00                           4
-#define UPM01                           5
-#define UMSEL00                         6
-#define UMSEL0                          6
-#define UMSEL01                         7
-#define UMSEL1                          7
-
-/* USART0 Baud Rate Register  Bytes */
-#define UBRR0                           _SFR_MEM16(0xC4)
-#define UBRR0L                          _SFR_MEM8(0xC4)
-#define UBRR0H                          _SFR_MEM8(0xC5)
-
-/* USART0 I/O Data Register */
-#define UDR0                            _SFR_MEM8(0xC6)
-
-  /* UDR0 */
-
-#define UDR00                           0
-#define UDR01                           1
-#define UDR02                           2
-#define UDR03                           3
-#define UDR04                           4
-#define UDR05                           5
-#define UDR06                           6
-#define UDR07                           7
-
-/* USART1 Control and Status Register A */
-#define UCSR1A                          _SFR_MEM8(0xC8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1A {
-        unsigned int mpcm1 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x1 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe1 : 1;	/* USART Parity Error */
-        unsigned int dor1 : 1;	/* Data OverRun */
-        unsigned int fe1 : 1;	/* Frame Error */
-        unsigned int udre1 : 1;	/* USART Data Register Empty */
-        unsigned int txc1 : 1;	/* USART Transmit Complete */
-        unsigned int rxc1 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1A */
-
-#define MPCM1                           0
-#define U2X1                            1
-#define UPE1                            2
-#define DOR1                            3
-#define FE1                             4
-#define UDRE1                           5
-#define TXC1                            6
-#define RXC1                            7
-
-/* USART1 Control and Status Register B */
-#define UCSR1B                          _SFR_MEM8(0xC9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1B {
-        unsigned int txb81 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb81 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz12 : 1;	/* Character Size */
-        unsigned int txen1 : 1;	/* Transmitter Enable */
-        unsigned int rxen1 : 1;	/* Receiver Enable */
-        unsigned int udrie1 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie1 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie1 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1B */
-
-#define TXB81                           0
-#define RXB81                           1
-#define UCSZ12                          2
-#define TXEN1                           3
-#define RXEN1                           4
-#define UDRIE1                          5
-#define TXCIE1                          6
-#define RXCIE1                          7
-
-/* USART1 Control and Status Register C */
-#define UCSR1C                          _SFR_MEM8(0xCA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1C {
-        unsigned int ucpol1 : 1;	/* Clock Polarity */
-        unsigned int ucsz1 : 2;	/* Character Size */
-        unsigned int ucpha1 : 1;	/* Clock Phase */
-        unsigned int udord1 : 1;	/* Data Order */
-        unsigned int usbs1 : 1;	/* Stop Bit Select */
-        unsigned int upm1 : 2;	/* Parity Mode */
-        unsigned int umsel1 : 2;	/* USART Mode Select */
-};
-
-#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1C */
-
-#define UCPOL1                          0
-#define UCPHA1                          1
-#define UCPHA1                          1
-#define UCSZ10                          1
-#define UDORD1                          2
-#define UDORD1                          2
-#define UCSZ11                          2
-#define USBS1                           3
-#define UPM10                           4
-#define UPM11                           5
-#define UMSEL10                         6
-#define UMSEL11                         7
-
-/* USART1 Baud Rate Register  Bytes */
-#define UBRR1                           _SFR_MEM16(0xCC)
-#define UBRR1L                          _SFR_MEM8(0xCC)
-#define UBRR1H                          _SFR_MEM8(0xCD)
-
-/* USART1 I/O Data Register */
-#define UDR1                            _SFR_MEM8(0xCE)
-
-  /* UDR1 */
-
-#define UDR10                           0
-#define UDR11                           1
-#define UDR12                           2
-#define UDR13                           3
-#define UDR14                           4
-#define UDR15                           5
-#define UDR16                           6
-#define UDR17                           7
-
-/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-#define SCRSTRLL                        _SFR_MEM8(0xD7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLL {
-        unsigned int scrstrll : 8;	/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-};
-
-#define SCRSTRLL_struct _SFR_MEM8_STRUCT(0xd7, struct __reg_SCRSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLL */
-
-#define SCRSTRLL0                       0
-#define SCRSTRLL1                       1
-#define SCRSTRLL2                       2
-#define SCRSTRLL3                       3
-#define SCRSTRLL4                       4
-#define SCRSTRLL5                       5
-#define SCRSTRLL6                       6
-#define SCRSTRLL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-#define SCRSTRLH                        _SFR_MEM8(0xD8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLH {
-        unsigned int scrstrlh : 8;	/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-};
-
-#define SCRSTRLH_struct _SFR_MEM8_STRUCT(0xd8, struct __reg_SCRSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLH */
-
-#define SCRSTRLH0                       0
-#define SCRSTRLH1                       1
-#define SCRSTRLH2                       2
-#define SCRSTRLH3                       3
-#define SCRSTRLH4                       4
-#define SCRSTRLH5                       5
-#define SCRSTRLH6                       6
-#define SCRSTRLH7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-#define SCRSTRHL                        _SFR_MEM8(0xD9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHL {
-        unsigned int scrstrhl : 8;	/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-};
-
-#define SCRSTRHL_struct _SFR_MEM8_STRUCT(0xd9, struct __reg_SCRSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHL */
-
-#define SCRSTRHL0                       0
-#define SCRSTRHL1                       1
-#define SCRSTRHL2                       2
-#define SCRSTRHL3                       3
-#define SCRSTRHL4                       4
-#define SCRSTRHL5                       5
-#define SCRSTRHL6                       6
-#define SCRSTRHL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-#define SCRSTRHH                        _SFR_MEM8(0xDA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHH {
-        unsigned int scrstrhh : 8;	/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-};
-
-#define SCRSTRHH_struct _SFR_MEM8_STRUCT(0xda, struct __reg_SCRSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHH */
-
-#define SCRSTRHH0                       0
-#define SCRSTRHH1                       1
-#define SCRSTRHH2                       2
-#define SCRSTRHH3                       3
-#define SCRSTRHH4                       4
-#define SCRSTRHH5                       5
-#define SCRSTRHH6                       6
-#define SCRSTRHH7                       7
-
-/* Symbol Counter Compare Source Register */
-#define SCCSR                           _SFR_MEM8(0xDB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCSR {
-        unsigned int sccs1 : 2;	/* Symbol Counter Compare Source select register for Compare Units */
-        unsigned int sccs2 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 2 */
-        unsigned int sccs3 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 3 */
-        unsigned int : 2;
-};
-
-#define SCCSR_struct _SFR_MEM8_STRUCT(0xdb, struct __reg_SCCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCSR */
-
-#define SCCS10                          0
-#define SCCS11                          1
-#define SCCS20                          2
-#define SCCS21                          3
-#define SCCS30                          4
-#define SCCS31                          5
-
-/* Symbol Counter Control Register 0 */
-#define SCCR0                           _SFR_MEM8(0xDC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR0 {
-        unsigned int sccmp : 3;	/* Symbol Counter Compare Unit 3 Mode select */
-        unsigned int sctse : 1;	/* Symbol Counter Automatic Timestamping enable */
-        unsigned int sccksel : 1;	/* Symbol Counter Clock Source select */
-        unsigned int scen : 1;	/* Symbol Counter enable */
-        unsigned int scmbts : 1;	/* Manual Beacon Timestamp */
-        unsigned int scres : 1;	/* Symbol Counter Synchronization */
-};
-
-#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR0 */
-
-#define SCCMP1                          0
-#define SCCMP2                          1
-#define SCCMP3                          2
-#define SCTSE                           3
-#define SCCKSEL                         4
-#define SCEN                            5
-#define SCMBTS                          6
-#define SCRES                           7
-
-/* Symbol Counter Control Register 1 */
-#define SCCR1                           _SFR_MEM8(0xDD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR1 {
-        unsigned int scenbo : 1;	/* Backoff Slot Counter enable */
-        unsigned int sceeclk : 1;	/* Enable External Clock Source on PG2 */
-        unsigned int scckdiv : 3;	/* Clock divider for synchronous clock source (16MHz Transceiver Clock) */
-        unsigned int scbtsm : 1;	/* Symbol Counter Beacon Timestamp Mask Register */
-        unsigned int : 2;
-};
-
-#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR1 */
-
-#define SCENBO                          0
-#define SCEECLK                         1
-#define SCCKDIV0                        2
-#define SCCKDIV1                        3
-#define SCCKDIV2                        4
-#define SCBTSM                          5
-
-/* Symbol Counter Status Register */
-#define SCSR                            _SFR_MEM8(0xDE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCSR {
-        unsigned int scbsy : 1;	/* Symbol Counter busy */
-        unsigned int : 7;
-};
-
-#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCSR */
-
-#define SCBSY                           0
-
-/* Symbol Counter Interrupt Mask Register */
-#define SCIRQM                          _SFR_MEM8(0xDF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQM {
-        unsigned int irqmcp : 3;	/* Symbol Counter Compare Match 3 IRQ enable */
-        unsigned int irqmof : 1;	/* Symbol Counter Overflow IRQ enable */
-        unsigned int irqmbo : 1;	/* Backoff Slot Counter IRQ enable */
-        unsigned int : 3;
-};
-
-#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQM */
-
-#define IRQMCP1                         0
-#define IRQMCP2                         1
-#define IRQMCP3                         2
-#define IRQMOF                          3
-#define IRQMBO                          4
-
-/* Symbol Counter Interrupt Status Register */
-#define SCIRQS                          _SFR_MEM8(0xE0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQS {
-        unsigned int irqscp : 3;	/* Compare Unit 3 Compare Match IRQ */
-        unsigned int irqsof : 1;	/* Symbol Counter Overflow IRQ */
-        unsigned int irqsbo : 1;	/* Backoff Slot Counter IRQ */
-        unsigned int : 3;
-};
-
-#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQS */
-
-#define IRQSCP1                         0
-#define IRQSCP2                         1
-#define IRQSCP3                         2
-#define IRQSOF                          3
-#define IRQSBO                          4
-
-/* Symbol Counter Register LL-Byte */
-#define SCCNTLL                         _SFR_MEM8(0xE1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLL {
-        unsigned int sccntll : 8;	/* Symbol Counter Register LL-Byte */
-};
-
-#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLL */
-
-#define SCCNTLL0                        0
-#define SCCNTLL1                        1
-#define SCCNTLL2                        2
-#define SCCNTLL3                        3
-#define SCCNTLL4                        4
-#define SCCNTLL5                        5
-#define SCCNTLL6                        6
-#define SCCNTLL7                        7
-
-/* Symbol Counter Register LH-Byte */
-#define SCCNTLH                         _SFR_MEM8(0xE2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLH {
-        unsigned int sccntlh : 8;	/* Symbol Counter Register LH-Byte */
-};
-
-#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLH */
-
-#define SCCNTLH0                        0
-#define SCCNTLH1                        1
-#define SCCNTLH2                        2
-#define SCCNTLH3                        3
-#define SCCNTLH4                        4
-#define SCCNTLH5                        5
-#define SCCNTLH6                        6
-#define SCCNTLH7                        7
-
-/* Symbol Counter Register HL-Byte */
-#define SCCNTHL                         _SFR_MEM8(0xE3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHL {
-        unsigned int sccnthl : 8;	/* Symbol Counter Register HL-Byte */
-};
-
-#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHL */
-
-#define SCCNTHL0                        0
-#define SCCNTHL1                        1
-#define SCCNTHL2                        2
-#define SCCNTHL3                        3
-#define SCCNTHL4                        4
-#define SCCNTHL5                        5
-#define SCCNTHL6                        6
-#define SCCNTHL7                        7
-
-/* Symbol Counter Register HH-Byte */
-#define SCCNTHH                         _SFR_MEM8(0xE4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHH {
-        unsigned int sccnthh : 8;	/* Symbol Counter Register HH-Byte */
-};
-
-#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHH */
-
-#define SCCNTHH0                        0
-#define SCCNTHH1                        1
-#define SCCNTHH2                        2
-#define SCCNTHH3                        3
-#define SCCNTHH4                        4
-#define SCCNTHH5                        5
-#define SCCNTHH6                        6
-#define SCCNTHH7                        7
-
-/* Symbol Counter Beacon Timestamp Register LL-Byte */
-#define SCBTSRLL                        _SFR_MEM8(0xE5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLL {
-        unsigned int scbtsrll : 8;	/* Symbol Counter Beacon Timestamp Register LL-Byte */
-};
-
-#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLL */
-
-#define SCBTSRLL0                       0
-#define SCBTSRLL1                       1
-#define SCBTSRLL2                       2
-#define SCBTSRLL3                       3
-#define SCBTSRLL4                       4
-#define SCBTSRLL5                       5
-#define SCBTSRLL6                       6
-#define SCBTSRLL7                       7
-
-/* Symbol Counter Beacon Timestamp Register LH-Byte */
-#define SCBTSRLH                        _SFR_MEM8(0xE6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLH {
-        unsigned int scbtsrlh : 8;	/* Symbol Counter Beacon Timestamp Register LH-Byte */
-};
-
-#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLH */
-
-#define SCBTSRLH0                       0
-#define SCBTSRLH1                       1
-#define SCBTSRLH2                       2
-#define SCBTSRLH3                       3
-#define SCBTSRLH4                       4
-#define SCBTSRLH5                       5
-#define SCBTSRLH6                       6
-#define SCBTSRLH7                       7
-
-/* Symbol Counter Beacon Timestamp Register HL-Byte */
-#define SCBTSRHL                        _SFR_MEM8(0xE7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHL {
-        unsigned int scbtsrhl : 8;	/* Symbol Counter Beacon Timestamp Register HL-Byte */
-};
-
-#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHL */
-
-#define SCBTSRHL0                       0
-#define SCBTSRHL1                       1
-#define SCBTSRHL2                       2
-#define SCBTSRHL3                       3
-#define SCBTSRHL4                       4
-#define SCBTSRHL5                       5
-#define SCBTSRHL6                       6
-#define SCBTSRHL7                       7
-
-/* Symbol Counter Beacon Timestamp Register HH-Byte */
-#define SCBTSRHH                        _SFR_MEM8(0xE8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHH {
-        unsigned int scbtsrhh : 8;	/* Symbol Counter Beacon Timestamp Register HH-Byte */
-};
-
-#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHH */
-
-#define SCBTSRHH0                       0
-#define SCBTSRHH1                       1
-#define SCBTSRHH2                       2
-#define SCBTSRHH3                       3
-#define SCBTSRHH4                       4
-#define SCBTSRHH5                       5
-#define SCBTSRHH6                       6
-#define SCBTSRHH7                       7
-
-/* Symbol Counter Frame Timestamp Register LL-Byte */
-#define SCTSRLL                         _SFR_MEM8(0xE9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLL {
-        unsigned int sctsrll : 8;	/* Symbol Counter Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLL */
-
-#define SCTSRLL0                        0
-#define SCTSRLL1                        1
-#define SCTSRLL2                        2
-#define SCTSRLL3                        3
-#define SCTSRLL4                        4
-#define SCTSRLL5                        5
-#define SCTSRLL6                        6
-#define SCTSRLL7                        7
-
-/* Symbol Counter Frame Timestamp Register LH-Byte */
-#define SCTSRLH                         _SFR_MEM8(0xEA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLH {
-        unsigned int sctsrlh : 8;	/* Symbol Counter Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLH */
-
-#define SCTSRLH0                        0
-#define SCTSRLH1                        1
-#define SCTSRLH2                        2
-#define SCTSRLH3                        3
-#define SCTSRLH4                        4
-#define SCTSRLH5                        5
-#define SCTSRLH6                        6
-#define SCTSRLH7                        7
-
-/* Symbol Counter Frame Timestamp Register HL-Byte */
-#define SCTSRHL                         _SFR_MEM8(0xEB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHL {
-        unsigned int sctsrhl : 8;	/* Symbol Counter Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHL */
-
-#define SCTSRHL0                        0
-#define SCTSRHL1                        1
-#define SCTSRHL2                        2
-#define SCTSRHL3                        3
-#define SCTSRHL4                        4
-#define SCTSRHL5                        5
-#define SCTSRHL6                        6
-#define SCTSRHL7                        7
-
-/* Symbol Counter Frame Timestamp Register HH-Byte */
-#define SCTSRHH                         _SFR_MEM8(0xEC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHH {
-        unsigned int sctsrhh : 8;	/* Symbol Counter Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHH */
-
-#define SCTSRHH0                        0
-#define SCTSRHH1                        1
-#define SCTSRHH2                        2
-#define SCTSRHH3                        3
-#define SCTSRHH4                        4
-#define SCTSRHH5                        5
-#define SCTSRHH6                        6
-#define SCTSRHH7                        7
-
-/* Symbol Counter Output Compare Register 3 LL-Byte */
-#define SCOCR3LL                        _SFR_MEM8(0xED)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LL {
-        unsigned int scocr3ll : 8;	/* Symbol Counter Output Compare Register 3 LL-Byte */
-};
-
-#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LL */
-
-#define SCOCR3LL0                       0
-#define SCOCR3LL1                       1
-#define SCOCR3LL2                       2
-#define SCOCR3LL3                       3
-#define SCOCR3LL4                       4
-#define SCOCR3LL5                       5
-#define SCOCR3LL6                       6
-#define SCOCR3LL7                       7
-
-/* Symbol Counter Output Compare Register 3 LH-Byte */
-#define SCOCR3LH                        _SFR_MEM8(0xEE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LH {
-        unsigned int scocr3lh : 8;	/* Symbol Counter Output Compare Register 3 LH-Byte */
-};
-
-#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LH */
-
-#define SCOCR3LH0                       0
-#define SCOCR3LH1                       1
-#define SCOCR3LH2                       2
-#define SCOCR3LH3                       3
-#define SCOCR3LH4                       4
-#define SCOCR3LH5                       5
-#define SCOCR3LH6                       6
-#define SCOCR3LH7                       7
-
-/* Symbol Counter Output Compare Register 3 HL-Byte */
-#define SCOCR3HL                        _SFR_MEM8(0xEF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HL {
-        unsigned int scocr3hl : 8;	/* Symbol Counter Output Compare Register 3 HL-Byte */
-};
-
-#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HL */
-
-#define SCOCR3HL0                       0
-#define SCOCR3HL1                       1
-#define SCOCR3HL2                       2
-#define SCOCR3HL3                       3
-#define SCOCR3HL4                       4
-#define SCOCR3HL5                       5
-#define SCOCR3HL6                       6
-#define SCOCR3HL7                       7
-
-/* Symbol Counter Output Compare Register 3 HH-Byte */
-#define SCOCR3HH                        _SFR_MEM8(0xF0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HH {
-        unsigned int scocr3hh : 8;	/* Symbol Counter Output Compare Register 3 HH-Byte */
-};
-
-#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HH */
-
-#define SCOCR3HH0                       0
-#define SCOCR3HH1                       1
-#define SCOCR3HH2                       2
-#define SCOCR3HH3                       3
-#define SCOCR3HH4                       4
-#define SCOCR3HH5                       5
-#define SCOCR3HH6                       6
-#define SCOCR3HH7                       7
-
-/* Symbol Counter Output Compare Register 2 LL-Byte */
-#define SCOCR2LL                        _SFR_MEM8(0xF1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LL {
-        unsigned int scocr2ll : 8;	/* Symbol Counter Output Compare Register 2 LL-Byte */
-};
-
-#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LL */
-
-#define SCOCR2LL0                       0
-#define SCOCR2LL1                       1
-#define SCOCR2LL2                       2
-#define SCOCR2LL3                       3
-#define SCOCR2LL4                       4
-#define SCOCR2LL5                       5
-#define SCOCR2LL6                       6
-#define SCOCR2LL7                       7
-
-/* Symbol Counter Output Compare Register 2 LH-Byte */
-#define SCOCR2LH                        _SFR_MEM8(0xF2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LH {
-        unsigned int scocr2lh : 8;	/* Symbol Counter Output Compare Register 2 LH-Byte */
-};
-
-#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LH */
-
-#define SCOCR2LH0                       0
-#define SCOCR2LH1                       1
-#define SCOCR2LH2                       2
-#define SCOCR2LH3                       3
-#define SCOCR2LH4                       4
-#define SCOCR2LH5                       5
-#define SCOCR2LH6                       6
-#define SCOCR2LH7                       7
-
-/* Symbol Counter Output Compare Register 2 HL-Byte */
-#define SCOCR2HL                        _SFR_MEM8(0xF3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HL {
-        unsigned int scocr2hl : 8;	/* Symbol Counter Output Compare Register 2 HL-Byte */
-};
-
-#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HL */
-
-#define SCOCR2HL0                       0
-#define SCOCR2HL1                       1
-#define SCOCR2HL2                       2
-#define SCOCR2HL3                       3
-#define SCOCR2HL4                       4
-#define SCOCR2HL5                       5
-#define SCOCR2HL6                       6
-#define SCOCR2HL7                       7
-
-/* Symbol Counter Output Compare Register 2 HH-Byte */
-#define SCOCR2HH                        _SFR_MEM8(0xF4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HH {
-        unsigned int scocr2hh : 8;	/* Symbol Counter Output Compare Register 2 HH-Byte */
-};
-
-#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HH */
-
-#define SCOCR2HH0                       0
-#define SCOCR2HH1                       1
-#define SCOCR2HH2                       2
-#define SCOCR2HH3                       3
-#define SCOCR2HH4                       4
-#define SCOCR2HH5                       5
-#define SCOCR2HH6                       6
-#define SCOCR2HH7                       7
-
-/* Symbol Counter Output Compare Register 1 LL-Byte */
-#define SCOCR1LL                        _SFR_MEM8(0xF5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LL {
-        unsigned int scocr1ll : 8;	/* Symbol Counter Output Compare Register 1 LL-Byte */
-};
-
-#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LL */
-
-#define SCOCR1LL0                       0
-#define SCOCR1LL1                       1
-#define SCOCR1LL2                       2
-#define SCOCR1LL3                       3
-#define SCOCR1LL4                       4
-#define SCOCR1LL5                       5
-#define SCOCR1LL6                       6
-#define SCOCR1LL7                       7
-
-/* Symbol Counter Output Compare Register 1 LH-Byte */
-#define SCOCR1LH                        _SFR_MEM8(0xF6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LH {
-        unsigned int scocr1lh : 8;	/* Symbol Counter Output Compare Register 1 LH-Byte */
-};
-
-#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LH */
-
-#define SCOCR1LH0                       0
-#define SCOCR1LH1                       1
-#define SCOCR1LH2                       2
-#define SCOCR1LH3                       3
-#define SCOCR1LH4                       4
-#define SCOCR1LH5                       5
-#define SCOCR1LH6                       6
-#define SCOCR1LH7                       7
-
-/* Symbol Counter Output Compare Register 1 HL-Byte */
-#define SCOCR1HL                        _SFR_MEM8(0xF7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HL {
-        unsigned int scocr1hl : 8;	/* Symbol Counter Output Compare Register 1 HL-Byte */
-};
-
-#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HL */
-
-#define SCOCR1HL0                       0
-#define SCOCR1HL1                       1
-#define SCOCR1HL2                       2
-#define SCOCR1HL3                       3
-#define SCOCR1HL4                       4
-#define SCOCR1HL5                       5
-#define SCOCR1HL6                       6
-#define SCOCR1HL7                       7
-
-/* Symbol Counter Output Compare Register 1 HH-Byte */
-#define SCOCR1HH                        _SFR_MEM8(0xF8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HH {
-        unsigned int scocr1hh : 8;	/* Symbol Counter Output Compare Register 1 HH-Byte */
-};
-
-#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HH */
-
-#define SCOCR1HH0                       0
-#define SCOCR1HH1                       1
-#define SCOCR1HH2                       2
-#define SCOCR1HH3                       3
-#define SCOCR1HH4                       4
-#define SCOCR1HH5                       5
-#define SCOCR1HH6                       6
-#define SCOCR1HH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-#define SCTSTRLL                        _SFR_MEM8(0xF9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLL {
-        unsigned int sctstrll : 8;	/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSTRLL_struct _SFR_MEM8_STRUCT(0xf9, struct __reg_SCTSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLL */
-
-#define SCTSTRLL0                       0
-#define SCTSTRLL1                       1
-#define SCTSTRLL2                       2
-#define SCTSTRLL3                       3
-#define SCTSTRLL4                       4
-#define SCTSTRLL5                       5
-#define SCTSTRLL6                       6
-#define SCTSTRLL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-#define SCTSTRLH                        _SFR_MEM8(0xFA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLH {
-        unsigned int sctstrlh : 8;	/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSTRLH_struct _SFR_MEM8_STRUCT(0xfa, struct __reg_SCTSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLH */
-
-#define SCTSTRLH0                       0
-#define SCTSTRLH1                       1
-#define SCTSTRLH2                       2
-#define SCTSTRLH3                       3
-#define SCTSTRLH4                       4
-#define SCTSTRLH5                       5
-#define SCTSTRLH6                       6
-#define SCTSTRLH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-#define SCTSTRHL                        _SFR_MEM8(0xFB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHL {
-        unsigned int sctstrhl : 8;	/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSTRHL_struct _SFR_MEM8_STRUCT(0xfb, struct __reg_SCTSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHL */
-
-#define SCTSTRHL0                       0
-#define SCTSTRHL1                       1
-#define SCTSTRHL2                       2
-#define SCTSTRHL3                       3
-#define SCTSTRHL4                       4
-#define SCTSTRHL5                       5
-#define SCTSTRHL6                       6
-#define SCTSTRHL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-#define SCTSTRHH                        _SFR_MEM8(0xFC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHH {
-        unsigned int sctstrhh : 8;	/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSTRHH_struct _SFR_MEM8_STRUCT(0xfc, struct __reg_SCTSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHH */
-
-#define SCTSTRHH0                       0
-#define SCTSTRHH1                       1
-#define SCTSTRHH2                       2
-#define SCTSTRHH3                       3
-#define SCTSTRHH4                       4
-#define SCTSTRHH5                       5
-#define SCTSTRHH6                       6
-#define SCTSTRHH7                       7
-
-/* Multiple Address Filter Configuration Register 0 */
-#define MAFCR0                          _SFR_MEM8(0x10C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR0 {
-        unsigned int maf0en : 1;	/* Multiple Address Filter 0 Enable */
-        unsigned int maf1en : 1;	/* Multiple Address Filter 1 Enable */
-        unsigned int maf2en : 1;	/* Multiple Address Filter 2 Enable */
-        unsigned int maf3en : 1;	/* Multiple Address Filter 3 Enable */
-        unsigned int : 4;
-};
-
-#define MAFCR0_struct _SFR_MEM8_STRUCT(0x10c, struct __reg_MAFCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR0 */
-
-#define MAF0EN                          0
-#define MAF1EN                          1
-#define MAF2EN                          2
-#define MAF3EN                          3
-
-/* Multiple Address Filter Configuration Register 1 */
-#define MAFCR1                          _SFR_MEM8(0x10D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR1 {
-        unsigned int aack_0_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 0. */
-        unsigned int aack_0_set_pd : 1;	/* Set Data Pending bit for address filter 0. */
-        unsigned int aack_1_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 1. */
-        unsigned int aack_1_set_pd : 1;	/* Set Data Pending bit for address filter 1. */
-        unsigned int aack_2_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 2. */
-        unsigned int aack_2_set_pd : 1;	/* Set Data Pending bit for address filter 2. */
-        unsigned int aack_3_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 3. */
-        unsigned int aack_3_set_pd : 1;	/* Set Data Pending bit for address filter 3. */
-};
-
-#define MAFCR1_struct _SFR_MEM8_STRUCT(0x10d, struct __reg_MAFCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR1 */
-
-#define AACK_0_I_AM_COORD               0
-#define AACK_0_SET_PD                   1
-#define AACK_1_I_AM_COORD               2
-#define AACK_1_SET_PD                   3
-#define AACK_2_I_AM_COORD               4
-#define AACK_2_SET_PD                   5
-#define AACK_3_I_AM_COORD               6
-#define AACK_3_SET_PD                   7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) */
-#define MAFSA0L                         _SFR_MEM8(0x10E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0L {
-        unsigned int mafsa0l : 8;	/* MAC Short Address low Byte for Frame Filter 0 */
-};
-
-#define MAFSA0L_struct _SFR_MEM8_STRUCT(0x10e, struct __reg_MAFSA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0L */
-
-#define MAFSA0L0                        0
-#define MAFSA0L1                        1
-#define MAFSA0L2                        2
-#define MAFSA0L3                        3
-#define MAFSA0L4                        4
-#define MAFSA0L5                        5
-#define MAFSA0L6                        6
-#define MAFSA0L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) */
-#define MAFSA0H                         _SFR_MEM8(0x10F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0H {
-        unsigned int mafsa0h : 8;	/* MAC Short Address high Byte for Frame Filter 0 */
-};
-
-#define MAFSA0H_struct _SFR_MEM8_STRUCT(0x10f, struct __reg_MAFSA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0H */
-
-#define MAFSA0H0                        0
-#define MAFSA0H1                        1
-#define MAFSA0H2                        2
-#define MAFSA0H3                        3
-#define MAFSA0H4                        4
-#define MAFSA0H5                        5
-#define MAFSA0H6                        6
-#define MAFSA0H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) */
-#define MAFPA0L                         _SFR_MEM8(0x110)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0L {
-        unsigned int mafpa0l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 0 */
-};
-
-#define MAFPA0L_struct _SFR_MEM8_STRUCT(0x110, struct __reg_MAFPA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0L */
-
-#define MAFPA0L0                        0
-#define MAFPA0L1                        1
-#define MAFPA0L2                        2
-#define MAFPA0L3                        3
-#define MAFPA0L4                        4
-#define MAFPA0L5                        5
-#define MAFPA0L6                        6
-#define MAFPA0L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) */
-#define MAFPA0H                         _SFR_MEM8(0x111)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0H {
-        unsigned int mafpa0h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 0 */
-};
-
-#define MAFPA0H_struct _SFR_MEM8_STRUCT(0x111, struct __reg_MAFPA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0H */
-
-#define MAFPA0H0                        0
-#define MAFPA0H1                        1
-#define MAFPA0H2                        2
-#define MAFPA0H3                        3
-#define MAFPA0H4                        4
-#define MAFPA0H5                        5
-#define MAFPA0H6                        6
-#define MAFPA0H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) */
-#define MAFSA1L                         _SFR_MEM8(0x112)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1L {
-        unsigned int mafsa1l : 8;	/* MAC Short Address low Byte for Frame Filter 1 */
-};
-
-#define MAFSA1L_struct _SFR_MEM8_STRUCT(0x112, struct __reg_MAFSA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1L */
-
-#define MAFSA1L0                        0
-#define MAFSA1L1                        1
-#define MAFSA1L2                        2
-#define MAFSA1L3                        3
-#define MAFSA1L4                        4
-#define MAFSA1L5                        5
-#define MAFSA1L6                        6
-#define MAFSA1L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) */
-#define MAFSA1H                         _SFR_MEM8(0x113)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1H {
-        unsigned int mafsa1h : 8;	/* MAC Short Address high Byte for Frame Filter 1 */
-};
-
-#define MAFSA1H_struct _SFR_MEM8_STRUCT(0x113, struct __reg_MAFSA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1H */
-
-#define MAFSA1H0                        0
-#define MAFSA1H1                        1
-#define MAFSA1H2                        2
-#define MAFSA1H3                        3
-#define MAFSA1H4                        4
-#define MAFSA1H5                        5
-#define MAFSA1H6                        6
-#define MAFSA1H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) */
-#define MAFPA1L                         _SFR_MEM8(0x114)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1L {
-        unsigned int mafpa1l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 1 */
-};
-
-#define MAFPA1L_struct _SFR_MEM8_STRUCT(0x114, struct __reg_MAFPA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1L */
-
-#define MAFPA1L0                        0
-#define MAFPA1L1                        1
-#define MAFPA1L2                        2
-#define MAFPA1L3                        3
-#define MAFPA1L4                        4
-#define MAFPA1L5                        5
-#define MAFPA1L6                        6
-#define MAFPA1L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) */
-#define MAFPA1H                         _SFR_MEM8(0x115)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1H {
-        unsigned int mafpa1h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 1 */
-};
-
-#define MAFPA1H_struct _SFR_MEM8_STRUCT(0x115, struct __reg_MAFPA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1H */
-
-#define MAFPA1H0                        0
-#define MAFPA1H1                        1
-#define MAFPA1H2                        2
-#define MAFPA1H3                        3
-#define MAFPA1H4                        4
-#define MAFPA1H5                        5
-#define MAFPA1H6                        6
-#define MAFPA1H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) */
-#define MAFSA2L                         _SFR_MEM8(0x116)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2L {
-        unsigned int mafsa2l : 8;	/* MAC Short Address low Byte for Frame Filter 2 */
-};
-
-#define MAFSA2L_struct _SFR_MEM8_STRUCT(0x116, struct __reg_MAFSA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2L */
-
-#define MAFSA2L0                        0
-#define MAFSA2L1                        1
-#define MAFSA2L2                        2
-#define MAFSA2L3                        3
-#define MAFSA2L4                        4
-#define MAFSA2L5                        5
-#define MAFSA2L6                        6
-#define MAFSA2L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) */
-#define MAFSA2H                         _SFR_MEM8(0x117)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2H {
-        unsigned int mafsa2h : 8;	/* MAC Short Address high Byte for Frame Filter 2 */
-};
-
-#define MAFSA2H_struct _SFR_MEM8_STRUCT(0x117, struct __reg_MAFSA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2H */
-
-#define MAFSA2H0                        0
-#define MAFSA2H1                        1
-#define MAFSA2H2                        2
-#define MAFSA2H3                        3
-#define MAFSA2H4                        4
-#define MAFSA2H5                        5
-#define MAFSA2H6                        6
-#define MAFSA2H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) */
-#define MAFPA2L                         _SFR_MEM8(0x118)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2L {
-        unsigned int mafpa2l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 2 */
-};
-
-#define MAFPA2L_struct _SFR_MEM8_STRUCT(0x118, struct __reg_MAFPA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2L */
-
-#define MAFPA2L0                        0
-#define MAFPA2L1                        1
-#define MAFPA2L2                        2
-#define MAFPA2L3                        3
-#define MAFPA2L4                        4
-#define MAFPA2L5                        5
-#define MAFPA2L6                        6
-#define MAFPA2L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) */
-#define MAFPA2H                         _SFR_MEM8(0x119)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2H {
-        unsigned int mafpa2h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 2 */
-};
-
-#define MAFPA2H_struct _SFR_MEM8_STRUCT(0x119, struct __reg_MAFPA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2H */
-
-#define MAFPA2H0                        0
-#define MAFPA2H1                        1
-#define MAFPA2H2                        2
-#define MAFPA2H3                        3
-#define MAFPA2H4                        4
-#define MAFPA2H5                        5
-#define MAFPA2H6                        6
-#define MAFPA2H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) */
-#define MAFSA3L                         _SFR_MEM8(0x11A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3L {
-        unsigned int mafsa3l : 8;	/* MAC Short Address low Byte for Frame Filter 3 */
-};
-
-#define MAFSA3L_struct _SFR_MEM8_STRUCT(0x11a, struct __reg_MAFSA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3L */
-
-#define MAFSA3L0                        0
-#define MAFSA3L1                        1
-#define MAFSA3L2                        2
-#define MAFSA3L3                        3
-#define MAFSA3L4                        4
-#define MAFSA3L5                        5
-#define MAFSA3L6                        6
-#define MAFSA3L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) */
-#define MAFSA3H                         _SFR_MEM8(0x11B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3H {
-        unsigned int mafsa3h : 8;	/* MAC Short Address high Byte for Frame Filter 3 */
-};
-
-#define MAFSA3H_struct _SFR_MEM8_STRUCT(0x11b, struct __reg_MAFSA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3H */
-
-#define MAFSA3H0                        0
-#define MAFSA3H1                        1
-#define MAFSA3H2                        2
-#define MAFSA3H3                        3
-#define MAFSA3H4                        4
-#define MAFSA3H5                        5
-#define MAFSA3H6                        6
-#define MAFSA3H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) */
-#define MAFPA3L                         _SFR_MEM8(0x11C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3L {
-        unsigned int mafpa3l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 3 */
-};
-
-#define MAFPA3L_struct _SFR_MEM8_STRUCT(0x11c, struct __reg_MAFPA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3L */
-
-#define MAFPA3L0                        0
-#define MAFPA3L1                        1
-#define MAFPA3L2                        2
-#define MAFPA3L3                        3
-#define MAFPA3L4                        4
-#define MAFPA3L5                        5
-#define MAFPA3L6                        6
-#define MAFPA3L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) */
-#define MAFPA3H                         _SFR_MEM8(0x11D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3H {
-        unsigned int mafpa3h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 3 */
-};
-
-#define MAFPA3H_struct _SFR_MEM8_STRUCT(0x11d, struct __reg_MAFPA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3H */
-
-#define MAFPA3H0                        0
-#define MAFPA3H1                        1
-#define MAFPA3H2                        2
-#define MAFPA3H3                        3
-#define MAFPA3H4                        4
-#define MAFPA3H5                        5
-#define MAFPA3H6                        6
-#define MAFPA3H7                        7
-
-/* Timer/Counter5 Control Register A */
-#define TCCR5A                          _SFR_MEM8(0x120)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5A {
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int com5c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com5b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com5a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5A */
-
-#define WGM50                           0
-#define WGM51                           1
-#define COM5C0                          2
-#define COM5C1                          3
-#define COM5B0                          4
-#define COM5B1                          5
-#define COM5A0                          6
-#define COM5A1                          7
-
-/* Timer/Counter5 Control Register B */
-#define TCCR5B                          _SFR_MEM8(0x121)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5B {
-        unsigned int cs5 : 3;	/* Clock Select */
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices5 : 1;	/* Input Capture 5 Edge Select */
-        unsigned int icnc5 : 1;	/* Input Capture 5 Noise Canceller */
-};
-
-#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5B */
-
-#define CS50                            0
-#define CS51                            1
-#define CS52                            2
-#define WGM52                           3
-#define WGM53                           4
-#define ICES5                           6
-#define ICNC5                           7
-
-/* Timer/Counter5 Control Register C */
-#define TCCR5C                          _SFR_MEM8(0x122)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5C {
-        unsigned int : 5;
-        unsigned int foc5c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc5b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc5a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5C */
-
-#define FOC5C                           5
-#define FOC5B                           6
-#define FOC5A                           7
-
-/* Timer/Counter5  Bytes */
-#define TCNT5                           _SFR_MEM16(0x124)
-#define TCNT5L                          _SFR_MEM8(0x124)
-#define TCNT5H                          _SFR_MEM8(0x125)
-
-/* Timer/Counter5 Input Capture Register  Bytes */
-#define ICR5                            _SFR_MEM16(0x126)
-#define ICR5L                           _SFR_MEM8(0x126)
-#define ICR5H                           _SFR_MEM8(0x127)
-
-/* Timer/Counter5 Output Compare Register A  Bytes */
-#define OCR5A                           _SFR_MEM16(0x128)
-#define OCR5AL                          _SFR_MEM8(0x128)
-#define OCR5AH                          _SFR_MEM8(0x129)
-
-/* Timer/Counter5 Output Compare Register B  Bytes */
-#define OCR5B                           _SFR_MEM16(0x12A)
-#define OCR5BL                          _SFR_MEM8(0x12A)
-#define OCR5BH                          _SFR_MEM8(0x12B)
-
-/* Timer/Counter5 Output Compare Register C  Bytes */
-#define OCR5C                           _SFR_MEM16(0x12C)
-#define OCR5CL                          _SFR_MEM8(0x12C)
-#define OCR5CH                          _SFR_MEM8(0x12D)
-
-/* Low Leakage Voltage Regulator Control Register */
-#define LLCR                            _SFR_MEM8(0x12F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLCR {
-        unsigned int llencal : 1;	/* Enable Automatic Calibration */
-        unsigned int llshort : 1;	/* Short Lower Calibration Circuit */
-        unsigned int lltco : 1;	/* Temperature Coefficient of Current Source */
-        unsigned int llcal : 1;	/* Calibration Active */
-        unsigned int llcomp : 1;	/* Comparator Output */
-        unsigned int lldone : 1;	/* Calibration Done */
-        unsigned int : 2;
-};
-
-#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLCR */
-
-#define LLENCAL                         0
-#define LLSHORT                         1
-#define LLTCO                           2
-#define LLCAL                           3
-#define LLCOMP                          4
-#define LLDONE                          5
-
-/* Low Leakage Voltage Regulator Data Register (Low-Byte) */
-#define LLDRL                           _SFR_MEM8(0x130)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRL {
-        unsigned int lldrl : 4;	/* Low-Byte Data Register Bits */
-        unsigned int : 4;
-};
-
-#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRL */
-
-#define LLDRL0                          0
-#define LLDRL1                          1
-#define LLDRL2                          2
-#define LLDRL3                          3
-
-/* Low Leakage Voltage Regulator Data Register (High-Byte) */
-#define LLDRH                           _SFR_MEM8(0x131)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRH {
-        unsigned int lldrh : 5;	/* High-Byte Data Register Bits */
-        unsigned int : 3;
-};
-
-#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRH */
-
-#define LLDRH0                          0
-#define LLDRH1                          1
-#define LLDRH2                          2
-#define LLDRH3                          3
-#define LLDRH4                          4
-
-/* Data Retention Configuration Register #3 */
-#define DRTRAM3                         _SFR_MEM8(0x132)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM3 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM3 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #2 */
-#define DRTRAM2                         _SFR_MEM8(0x133)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM2 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM2 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #1 */
-#define DRTRAM1                         _SFR_MEM8(0x134)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM1 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM1 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #0 */
-#define DRTRAM0                         _SFR_MEM8(0x135)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM0 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM0 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Port Driver Strength Register 0 */
-#define DPDS0                           _SFR_MEM8(0x136)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS0 {
-        unsigned int pbdrv : 2;	/* Driver Strength Port B */
-        unsigned int pddrv : 2;	/* Driver Strength Port D */
-        unsigned int pedrv : 2;	/* Driver Strength Port E */
-        unsigned int pfdrv : 2;	/* Driver Strength Port F */
-};
-
-#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS0 */
-
-#define PBDRV0                          0
-#define PBDRV1                          1
-#define PDDRV0                          2
-#define PDDRV1                          3
-#define PEDRV0                          4
-#define PEDRV1                          5
-#define PFDRV0                          6
-#define PFDRV1                          7
-
-/* Port Driver Strength Register 1 */
-#define DPDS1                           _SFR_MEM8(0x137)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS1 {
-        unsigned int pgdrv : 2;	/* Driver Strength Port G */
-        unsigned int : 6;
-};
-
-#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS1 */
-
-#define PGDRV0                          0
-#define PGDRV1                          1
-
-/* Power Amplifier Ramp up/down Control Register */
-#define PARCR                           _SFR_MEM8(0x138)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PARCR {
-        unsigned int parufi : 1;	/* Power Amplifier Ramp Up Frequency Inversion */
-        unsigned int pardfi : 1;	/* Power Amplifier Ramp Down Frequency Inversion */
-        unsigned int paltu : 3;	/* ext. PA Ramp Up Lead Time */
-        unsigned int paltd : 3;	/* ext. PA Ramp Down Lead Time */
-};
-
-#define PARCR_struct _SFR_MEM8_STRUCT(0x138, struct __reg_PARCR)
-
-/* symbolic names */
-
-#define PALTU_MINUS_3US                 0
-#define PALTU_MINUS_2US                 1
-#define PALTU_MINUS_1US                 2
-#define PALTU_0US                       3
-#define PALTU_1US                       4
-#define PALTU_2US                       5
-#define PALTU_3US                       6
-#define PALTU_4US                       7
-#define PALTD_MINUS_3US                 0
-#define PALTD_MINUS_2US                 1
-#define PALTD_MINUS_1US                 2
-#define PALTD_0US                       3
-#define PALTD_1US                       4
-#define PALTD_2US                       5
-#define PALTD_3US                       6
-#define PALTD_4US                       7
-
-#endif /* __ASSEMBLER__ */
-
-  /* PARCR */
-
-#define PARUFI                          0
-#define PARDFI                          1
-#define PALTU0                          2
-#define PALTU1                          3
-#define PALTU2                          4
-#define PALTD0                          5
-#define PALTD1                          6
-#define PALTD2                          7
-
-/* Transceiver Pin Register */
-#define TRXPR                           _SFR_MEM8(0x139)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRXPR {
-        unsigned int trxrst : 1;	/* Force Transceiver Reset */
-        unsigned int slptr : 1;	/* Multi-purpose Transceiver Control Bit */
-        unsigned int : 6;
-};
-
-#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRXPR */
-
-#define TRXRST                          0
-#define SLPTR                           1
-
-/* AES Control Register */
-#define AES_CTRL                        _SFR_MEM8(0x13C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_CTRL {
-        unsigned int : 2;
-        unsigned int aes_im : 1;	/* AES Interrupt Enable */
-        unsigned int aes_dir : 1;	/* Set AES Operation Direction */
-        unsigned int : 1;
-        unsigned int aes_mode : 1;	/* Set AES Operation Mode */
-        unsigned int : 1;
-        unsigned int aes_request : 1;	/* Request AES Operation. */
-};
-
-#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL)
-
-/* symbolic names */
-
-#define AES_DIR_ENC                     0
-#define AES_DIR_DEC                     1
-#define AES_MODE_ECB                    0
-#define AES_MODE_CBC                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_CTRL */
-
-#define AES_IM                          2
-#define AES_DIR                         3
-#define AES_MODE                        5
-#define AES_REQUEST                     7
-
-/* AES Status Register */
-#define AES_STATUS                      _SFR_MEM8(0x13D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATUS {
-        unsigned int aes_done : 1;	/* AES Operation Finished with Success */
-        unsigned int : 6;
-        unsigned int aes_er : 1;	/* AES Operation Finished with Error */
-};
-
-#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATUS */
-
-#define AES_DONE                        0
-#define AES_ER                          7
-
-/* AES Plain and Cipher Text Buffer Register */
-#define AES_STATE                       _SFR_MEM8(0x13E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATE {
-        unsigned int aes_state : 8;	/* AES Plain and Cipher Text Buffer */
-};
-
-#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATE */
-
-#define AES_STATE0                      0
-#define AES_STATE1                      1
-#define AES_STATE2                      2
-#define AES_STATE3                      3
-#define AES_STATE4                      4
-#define AES_STATE5                      5
-#define AES_STATE6                      6
-#define AES_STATE7                      7
-
-/* AES Encryption and Decryption Key Buffer Register */
-#define AES_KEY                         _SFR_MEM8(0x13F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_KEY {
-        unsigned int aes_key : 8;	/* AES Encryption/Decryption Key Buffer */
-};
-
-#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_KEY */
-
-#define AES_KEY0                        0
-#define AES_KEY1                        1
-#define AES_KEY2                        2
-#define AES_KEY3                        3
-#define AES_KEY4                        4
-#define AES_KEY5                        5
-#define AES_KEY6                        6
-#define AES_KEY7                        7
-
-/* Transceiver Status Register */
-#define TRX_STATUS                      _SFR_MEM8(0x141)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATUS {
-        unsigned int trx_status : 5;	/* Transceiver Main Status */
-        unsigned int tst_status : 1;	/* Test mode status */
-        unsigned int cca_status : 1;	/* CCA Status Result */
-        unsigned int cca_done : 1;	/* CCA Algorithm Status */
-};
-
-#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS)
-
-/* symbolic names */
-
-#define BUSY_RX                         1
-#define BUSY_TX                         2
-#define RX_ON                           6
-#define TRX_OFF                         8
-#define PLL_ON                          9
-#define SLEEP                           15
-#define BUSY_RX_AACK                    17
-#define BUSY_TX_ARET                    18
-#define RX_AACK_ON                      22
-#define TX_ARET_ON                      25
-#define STATE_TRANSITION_IN_PROGRESS    31
-#define TST_DISABLED                    0
-#define TST_ENABLED                     1
-#define CCA_BUSY                        0
-#define CCA_IDLE                        1
-#define CCA_NOT_FIN                     0
-#define CCA_FIN                         1
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATUS */
-
-#define TRX_STATUS0                     0
-#define TRX_STATUS1                     1
-#define TRX_STATUS2                     2
-#define TRX_STATUS3                     3
-#define TRX_STATUS4                     4
-#define TST_STATUS                      5
-#define CCA_STATUS                      6
-#define CCA_DONE                        7
-
-/* Transceiver State Control Register */
-#define TRX_STATE                       _SFR_MEM8(0x142)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATE {
-        unsigned int trx_cmd : 5;	/* State Control Command */
-        unsigned int trac_status : 3;	/* Transaction Status */
-};
-
-#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE)
-
-/* symbolic names */
-
-#define CMD_NOP                         0
-#define CMD_TX_START                    2
-#define CMD_FORCE_TRX_OFF               3
-#define CMD_FORCE_PLL_ON                4
-#define CMD_RX_ON                       6
-#define CMD_TRX_OFF                     8
-#define CMD_PLL_ON                      9
-#define CMD_RX_AACK_ON                  22
-#define CMD_TX_ARET_ON                  25
-#define TRAC_SUCCESS                    0
-#define TRAC_SUCCESS_DATA_PENDING       1
-#define TRAC_SUCCESS_WAIT_FOR_ACK       2
-#define TRAC_CHANNEL_ACCESS_FAILURE     3
-#define TRAC_NO_ACK                     5
-#define TRAC_INVALID                    7
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATE */
-
-#define TRX_CMD0                        0
-#define TRX_CMD1                        1
-#define TRX_CMD2                        2
-#define TRX_CMD3                        3
-#define TRX_CMD4                        4
-#define TRAC_STATUS0                    5
-#define TRAC_STATUS1                    6
-#define TRAC_STATUS2                    7
-
-/* Reserved */
-#define TRX_CTRL_0                      _SFR_MEM8(0x143)
-
-/* Transceiver Control Register 1 */
-#define TRX_CTRL_1                      _SFR_MEM8(0x144)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_1 {
-        unsigned int : 4;
-        unsigned int pll_tx_flt : 1;	/* Enable PLL TX Filter */
-        unsigned int tx_auto_crc_on : 1;	/* Enable Automatic CRC Calculation */
-        unsigned int irq_2_ext_en : 1;	/* Connect Frame Start IRQ to TC1 */
-        unsigned int pa_ext_en : 1;	/* External PA support enable */
-};
-
-#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_1 */
-
-#define PLL_TX_FLT                      4
-#define TX_AUTO_CRC_ON                  5
-#define IRQ_2_EXT_EN                    6
-#define PA_EXT_EN                       7
-
-/* Transceiver Transmit Power Control Register */
-#define PHY_TX_PWR                      _SFR_MEM8(0x145)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_TX_PWR {
-        unsigned int tx_pwr : 4;	/* Transmit Power Setting */
-        unsigned int : 4;
-};
-
-#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_TX_PWR */
-
-#define TX_PWR0                         0
-#define TX_PWR1                         1
-#define TX_PWR2                         2
-#define TX_PWR3                         3
-
-/* Receiver Signal Strength Indicator Register */
-#define PHY_RSSI                        _SFR_MEM8(0x146)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_RSSI {
-        unsigned int rssi : 5;	/* Receiver Signal Strength Indicator */
-        unsigned int rnd_value : 2;	/* Random Value */
-        unsigned int rx_crc_valid : 1;	/* Received Frame CRC Status */
-};
-
-#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI)
-
-/* symbolic names */
-
-#define RSSI_MIN                        0
-#define RSSI_MIN_PLUS_3dB               1
-#define RSSI_MAX                        28
-#define CRC_INVALID                     0
-#define CRC_VALID                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_RSSI */
-
-#define RSSI0                           0
-#define RSSI1                           1
-#define RSSI2                           2
-#define RSSI3                           3
-#define RSSI4                           4
-#define RND_VALUE0                      5
-#define RND_VALUE1                      6
-#define RX_CRC_VALID                    7
-
-/* Transceiver Energy Detection Level Register */
-#define PHY_ED_LEVEL                    _SFR_MEM8(0x147)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_ED_LEVEL {
-        unsigned int ed_level : 8;	/* Energy Detection Level */
-};
-
-#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL)
-
-/* symbolic names */
-
-#define ED_MIN                          0
-#define ED_MIN_PLUS_1dB                 1
-#define ED_MAX                          83
-#define ED_RESET                        255
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_ED_LEVEL */
-
-#define ED_LEVEL0                       0
-#define ED_LEVEL1                       1
-#define ED_LEVEL2                       2
-#define ED_LEVEL3                       3
-#define ED_LEVEL4                       4
-#define ED_LEVEL5                       5
-#define ED_LEVEL6                       6
-#define ED_LEVEL7                       7
-
-/* Transceiver Clear Channel Assessment (CCA) Control Register */
-#define PHY_CC_CCA                      _SFR_MEM8(0x148)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_CC_CCA {
-        unsigned int channel : 5;	/* RX/TX Channel Selection */
-        unsigned int cca_mode : 2;	/* Select CCA Measurement Mode */
-        unsigned int cca_request : 1;	/* Manual CCA Measurement Request */
-};
-
-#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA)
-
-/* symbolic names */
-
-#define F_2405MHZ                       11
-#define F_2410MHZ                       12
-#define F_2415MHZ                       13
-#define F_2420MHZ                       14
-#define F_2425MHZ                       15
-#define F_2430MHZ                       16
-#define F_2435MHZ                       17
-#define F_2440MHZ                       18
-#define F_2445MHZ                       19
-#define F_2450MHZ                       20
-#define F_2455MHZ                       21
-#define F_2460MHZ                       22
-#define F_2465MHZ                       23
-#define F_2470MHZ                       24
-#define F_2475MHZ                       25
-#define F_2480MHZ                       26
-#define CCA_CS_OR_ED                    0
-#define CCA_ED                          1
-#define CCA_CS                          2
-#define CCA_CS_AND_ED                   3
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_CC_CCA */
-
-#define CHANNEL0                        0
-#define CHANNEL1                        1
-#define CHANNEL2                        2
-#define CHANNEL3                        3
-#define CHANNEL4                        4
-#define CCA_MODE0                       5
-#define CCA_MODE1                       6
-#define CCA_REQUEST                     7
-
-/* Transceiver CCA Threshold Setting Register */
-#define CCA_THRES                       _SFR_MEM8(0x149)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CCA_THRES {
-        unsigned int cca_ed_thres : 4;	/* ED Threshold Level for CCA Measurement */
-        unsigned int cca_cs_thres : 4;	/* CS Threshold Level for CCA Measurement */
-};
-
-#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CCA_THRES */
-
-#define CCA_ED_THRES0                   0
-#define CCA_ED_THRES1                   1
-#define CCA_ED_THRES2                   2
-#define CCA_ED_THRES3                   3
-#define CCA_CS_THRES0                   4
-#define CCA_CS_THRES1                   5
-#define CCA_CS_THRES2                   6
-#define CCA_CS_THRES3                   7
-
-/* Transceiver Receive Control Register */
-#define RX_CTRL                         _SFR_MEM8(0x14A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_CTRL {
-        unsigned int pdt_thres : 4;	/* Receiver Sensitivity Control */
-        unsigned int : 4;
-};
-
-#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL)
-
-/* symbolic names */
-
-#define PDT_THRES_ANT_DIV_OFF           7
-#define PDT_THRES_ANT_DIV_ON            3
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_CTRL */
-
-#define PDT_THRES0                      0
-#define PDT_THRES1                      1
-#define PDT_THRES2                      2
-#define PDT_THRES3                      3
-
-/* Start of Frame Delimiter Value Register */
-#define SFD_VALUE                       _SFR_MEM8(0x14B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SFD_VALUE {
-        unsigned int sfd_value : 8;	/* Start of Frame Delimiter Value */
-};
-
-#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE)
-
-/* symbolic names */
-
-#define IEEE_SFD                        167
-
-#endif /* __ASSEMBLER__ */
-
-  /* SFD_VALUE */
-
-#define SFD_VALUE0                      0
-#define SFD_VALUE1                      1
-#define SFD_VALUE2                      2
-#define SFD_VALUE3                      3
-#define SFD_VALUE4                      4
-#define SFD_VALUE5                      5
-#define SFD_VALUE6                      6
-#define SFD_VALUE7                      7
-
-/* Transceiver Control Register 2 */
-#define TRX_CTRL_2                      _SFR_MEM8(0x14C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_2 {
-        unsigned int oqpsk_data_rate : 2;	/* Data Rate Selection */
-        unsigned int : 5;
-        unsigned int rx_safe_mode : 1;	/* RX Safe Mode */
-};
-
-#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2)
-
-/* symbolic names */
-
-#define RATE_250KB                      0
-#define RATE_500KB                      1
-#define RATE_1000KB                     2
-#define RATE_2000KB                     3
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_2 */
-
-#define OQPSK_DATA_RATE0                0
-#define OQPSK_DATA_RATE1                1
-#define RX_SAFE_MODE                    7
-
-/* Antenna Diversity Control Register */
-#define ANT_DIV                         _SFR_MEM8(0x14D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ANT_DIV {
-        unsigned int ant_ctrl : 2;	/* Static Antenna Diversity Switch Control */
-        unsigned int ant_ext_sw_en : 1;	/* Enable External Antenna Switch Control */
-        unsigned int ant_div_en : 1;	/* Enable Antenna Diversity */
-        unsigned int : 3;
-        unsigned int ant_sel : 1;	/* Antenna Diversity Antenna Status */
-};
-
-#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV)
-
-/* symbolic names */
-
-#define ANT_1                           1
-#define ANT_0                           2
-#define ANT_RESET                       3
-#define ANT_DIV_EXT_SW_DIS              0
-#define ANT_DIV_EXT_SW_EN               1
-#define ANTENNA_0                       0
-#define ANTENNA_1                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* ANT_DIV */
-
-#define ANT_CTRL0                       0
-#define ANT_CTRL1                       1
-#define ANT_EXT_SW_EN                   2
-#define ANT_DIV_EN                      3
-#define ANT_SEL                         7
-
-/* Transceiver Interrupt Enable Register */
-#define IRQ_MASK                        _SFR_MEM8(0x14E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK {
-        unsigned int pll_lock_en : 1;	/* PLL Lock Interrupt Enable */
-        unsigned int pll_unlock_en : 1;	/* PLL Unlock Interrupt Enable */
-        unsigned int rx_start_en : 1;	/* RX_START Interrupt Enable */
-        unsigned int rx_end_en : 1;	/* RX_END Interrupt Enable */
-        unsigned int cca_ed_done_en : 1;	/* End of ED Measurement Interrupt Enable */
-        unsigned int ami_en : 1;	/* Address Match Interrupt Enable */
-        unsigned int tx_end_en : 1;	/* TX_END Interrupt Enable */
-        unsigned int awake_en : 1;	/* Awake Interrupt Enable */
-};
-
-#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK */
-
-#define PLL_LOCK_EN                     0
-#define PLL_UNLOCK_EN                   1
-#define RX_START_EN                     2
-#define RX_END_EN                       3
-#define CCA_ED_DONE_EN                  4
-#define AMI_EN                          5
-#define TX_END_EN                       6
-#define AWAKE_EN                        7
-
-/* Transceiver Interrupt Status Register */
-#define IRQ_STATUS                      _SFR_MEM8(0x14F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS {
-        unsigned int pll_lock : 1;	/* PLL Lock Interrupt Status */
-        unsigned int pll_unlock : 1;	/* PLL Unlock Interrupt Status */
-        unsigned int rx_start : 1;	/* RX_START Interrupt Status */
-        unsigned int rx_end : 1;	/* RX_END Interrupt Status */
-        unsigned int cca_ed_done : 1;	/* End of ED Measurement Interrupt Status */
-        unsigned int ami : 1;	/* Address Match Interrupt Status */
-        unsigned int tx_end : 1;	/* TX_END Interrupt Status */
-        unsigned int awake : 1;	/* Awake Interrupt Status */
-};
-
-#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS */
-
-#define PLL_LOCK                        0
-#define PLL_UNLOCK                      1
-#define RX_START                        2
-#define RX_END                          3
-#define CCA_ED_DONE                     4
-#define AMI                             5
-#define TX_END                          6
-#define AWAKE                           7
-
-/* Voltage Regulator Control and Status Register */
-#define VREG_CTRL                       _SFR_MEM8(0x150)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VREG_CTRL {
-        unsigned int : 2;
-        unsigned int dvdd_ok : 1;	/* DVDD Supply Voltage Valid */
-        unsigned int dvreg_ext : 1;	/* Use External DVDD Regulator */
-        unsigned int : 2;
-        unsigned int avdd_ok : 1;	/* AVDD Supply Voltage Valid */
-        unsigned int avreg_ext : 1;	/* Use External AVDD Regulator */
-};
-
-#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL)
-
-/* symbolic names */
-
-#define DVDD_INT                        0
-#define DVDD_EXT                        1
-#define AVDD_INT                        0
-#define AVDD_EXT                        1
-
-#endif /* __ASSEMBLER__ */
-
-  /* VREG_CTRL */
-
-#define DVDD_OK                         2
-#define DVREG_EXT                       3
-#define AVDD_OK                         6
-#define AVREG_EXT                       7
-
-/* Battery Monitor Control and Status Register */
-#define BATMON                          _SFR_MEM8(0x151)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BATMON {
-        unsigned int batmon_vth : 4;	/* Battery Monitor Threshold Voltage */
-        unsigned int batmon_hr : 1;	/* Battery Monitor Voltage Range */
-        unsigned int batmon_ok : 1;	/* Battery Monitor Status */
-        unsigned int bat_low_en : 1;	/* Battery Monitor Interrupt Enable */
-        unsigned int bat_low : 1;	/* Battery Monitor Interrupt Status */
-};
-
-#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON)
-
-/* symbolic names */
-
-#define BATMON_HR_DIS                   0
-#define BATMON_HR_EN                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* BATMON */
-
-#define BATMON_VTH0                     0
-#define BATMON_VTH1                     1
-#define BATMON_VTH2                     2
-#define BATMON_VTH3                     3
-#define BATMON_HR                       4
-#define BATMON_OK                       5
-#define BAT_LOW_EN                      6
-#define BAT_LOW                         7
-
-/* Crystal Oscillator Control Register */
-#define XOSC_CTRL                       _SFR_MEM8(0x152)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XOSC_CTRL {
-        unsigned int xtal_trim : 4;	/* Crystal Oscillator Load Capacitance Trimming */
-        unsigned int xtal_mode : 4;	/* Crystal Oscillator Operating Mode */
-};
-
-#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL)
-
-/* symbolic names */
-
-#define XTAL_TRIM_MIN                   0
-#define XTAL_TRIM_MAX                   15
-
-#endif /* __ASSEMBLER__ */
-
-  /* XOSC_CTRL */
-
-#define XTAL_TRIM0                      0
-#define XTAL_TRIM1                      1
-#define XTAL_TRIM2                      2
-#define XTAL_TRIM3                      3
-#define XTAL_MODE0                      4
-#define XTAL_MODE1                      5
-#define XTAL_MODE2                      6
-#define XTAL_MODE3                      7
-
-/* Channel Control Register 0 */
-#define CC_CTRL_0                       _SFR_MEM8(0x153)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_0 {
-        unsigned int cc_number : 8;	/* Channel Number */
-};
-
-#define CC_CTRL_0_struct _SFR_MEM8_STRUCT(0x153, struct __reg_CC_CTRL_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_0 */
-
-#define CC_NUMBER0                      0
-#define CC_NUMBER1                      1
-#define CC_NUMBER2                      2
-#define CC_NUMBER3                      3
-#define CC_NUMBER4                      4
-#define CC_NUMBER5                      5
-#define CC_NUMBER6                      6
-#define CC_NUMBER7                      7
-
-/* Channel Control Register 1 */
-#define CC_CTRL_1                       _SFR_MEM8(0x154)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_1 {
-        unsigned int cc_band : 4;	/* Channel Band */
-        unsigned int : 4;
-};
-
-#define CC_CTRL_1_struct _SFR_MEM8_STRUCT(0x154, struct __reg_CC_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_1 */
-
-#define CC_BAND0                        0
-#define CC_BAND1                        1
-#define CC_BAND2                        2
-#define CC_BAND3                        3
-
-/* Transceiver Receiver Sensitivity Control Register */
-#define RX_SYN                          _SFR_MEM8(0x155)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_SYN {
-        unsigned int rx_pdt_level : 4;	/* Reduce Receiver Sensitivity */
-        unsigned int : 2;
-        unsigned int rx_override : 1;	/* Receiver Override Function */
-        unsigned int rx_pdt_dis : 1;	/* Prevent Frame Reception */
-};
-
-#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN)
-
-/* symbolic names */
-
-#define RX_PDT_LEVEL_MIN                0
-#define RX_PDT_LEVEL_MAX                15
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_SYN */
-
-#define RX_PDT_LEVEL0                   0
-#define RX_PDT_LEVEL1                   1
-#define RX_PDT_LEVEL2                   2
-#define RX_PDT_LEVEL3                   3
-#define RX_OVERRIDE                     6
-#define RX_PDT_DIS                      7
-
-/* Transceiver Reduced Power Consumption Control */
-#define TRX_RPC                         _SFR_MEM8(0x156)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_RPC {
-        unsigned int : 1;
-        unsigned int ipan_rpc_en : 1;	/* Smart Receiving Mode IPAN Handling Enable */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int pll_rpc_en : 1;	/* PLL Smart Receiving Mode Enable */
-        unsigned int pdt_rpc_en : 1;	/* Smart Receiving Mode Reduced Sensitivity Enable */
-        unsigned int rx_rpc_en : 1;	/* Receiver Smart Receiving Mode Enable */
-        unsigned int rx_rpc_ctrl : 2;	/* Smart Receiving Mode Timing */
-};
-
-#define TRX_RPC_struct _SFR_MEM8_STRUCT(0x156, struct __reg_TRX_RPC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_RPC */
-
-#define IPAN_RPC_EN                     1
-#define PLL_RPC_EN                      3
-#define PDT_RPC_EN                      4
-#define RX_RPC_EN                       5
-#define RX_RPC_CTRL0                    6
-#define RX_RPC_CTRL1                    7
-
-/* Transceiver Acknowledgment Frame Control Register 1 */
-#define XAH_CTRL_1                      _SFR_MEM8(0x157)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_1 {
-        unsigned int : 1;
-        unsigned int aack_prom_mode : 1;	/* Enable Promiscuous Mode */
-        unsigned int aack_ack_time : 1;	/* Reduce Acknowledgment Time */
-        unsigned int : 1;
-        unsigned int aack_upld_res_ft : 1;	/* Process Reserved Frames */
-        unsigned int aack_fltr_res_ft : 1;	/* Filter Reserved Frames */
-        unsigned int : 2;
-};
-
-#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1)
-
-/* symbolic names */
-
-#define AACK_ACK_TIME_12_SYM            0
-#define AACK_ACK_TIME_2_SYM             1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_1 */
-
-#define AACK_PROM_MODE                  1
-#define AACK_ACK_TIME                   2
-#define AACK_UPLD_RES_FT                4
-#define AACK_FLTR_RES_FT                5
-
-/* Transceiver Filter Tuning Control Register */
-#define FTN_CTRL                        _SFR_MEM8(0x158)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_FTN_CTRL {
-        unsigned int : 7;
-        unsigned int ftn_start : 1;	/* Start Calibration Loop of Filter Tuning Network */
-};
-
-#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* FTN_CTRL */
-
-#define FTN_START                       7
-
-/* Transceiver Center Frequency Calibration Control Register */
-#define PLL_CF                          _SFR_MEM8(0x15A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_CF {
-        unsigned int : 7;
-        unsigned int pll_cf_start : 1;	/* Start Center Frequency Calibration */
-};
-
-#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_CF */
-
-#define PLL_CF_START                    7
-
-/* Transceiver Delay Cell Calibration Control Register */
-#define PLL_DCU                         _SFR_MEM8(0x15B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_DCU {
-        unsigned int : 7;
-        unsigned int pll_dcu_start : 1;	/* Start Delay Cell Calibration */
-};
-
-#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_DCU */
-
-#define PLL_DCU_START                   7
-
-/* Device Identification Register (Part Number) */
-#define PART_NUM                        _SFR_MEM8(0x15C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PART_NUM {
-        unsigned int part_num : 8;	/* Part Number */
-};
-
-#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM)
-
-/* symbolic names */
-
-#define P_RFR2                          148
-
-#endif /* __ASSEMBLER__ */
-
-  /* PART_NUM */
-
-#define PART_NUM0                       0
-#define PART_NUM1                       1
-#define PART_NUM2                       2
-#define PART_NUM3                       3
-#define PART_NUM4                       4
-#define PART_NUM5                       5
-#define PART_NUM6                       6
-#define PART_NUM7                       7
-
-/* Device Identification Register (Version Number) */
-#define VERSION_NUM                     _SFR_MEM8(0x15D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VERSION_NUM {
-        unsigned int version_num : 8;	/* Version Number */
-};
-
-#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM)
-
-/* symbolic names */
-
-#define REV_A                           12
-#define REV_B                           1
-#define REV_C                           3
-#define REV_D                           4
-
-#endif /* __ASSEMBLER__ */
-
-  /* VERSION_NUM */
-
-#define VERSION_NUM0                    0
-#define VERSION_NUM1                    1
-#define VERSION_NUM2                    2
-#define VERSION_NUM3                    3
-#define VERSION_NUM4                    4
-#define VERSION_NUM5                    5
-#define VERSION_NUM6                    6
-#define VERSION_NUM7                    7
-
-/* Device Identification Register (Manufacture ID Low Byte) */
-#define MAN_ID_0                        _SFR_MEM8(0x15E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_0 {
-        unsigned int man_id_00 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_01 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_02 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_03 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_04 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_05 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_06 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_07 : 1;	/* Manufacturer ID (Low Byte) */
-};
-
-#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_0                    31
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_0 */
-
-#define MAN_ID_00                       0
-#define MAN_ID_01                       1
-#define MAN_ID_02                       2
-#define MAN_ID_03                       3
-#define MAN_ID_04                       4
-#define MAN_ID_05                       5
-#define MAN_ID_06                       6
-#define MAN_ID_07                       7
-
-/* Device Identification Register (Manufacture ID High Byte) */
-#define MAN_ID_1                        _SFR_MEM8(0x15F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_1 {
-        unsigned int man_id_ : 8;	/* Manufacturer ID (High Byte) */
-};
-
-#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_1                    0
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_1 */
-
-#define MAN_ID_10                       0
-#define MAN_ID_11                       1
-#define MAN_ID_12                       2
-#define MAN_ID_13                       3
-#define MAN_ID_14                       4
-#define MAN_ID_15                       5
-#define MAN_ID_16                       6
-#define MAN_ID_17                       7
-
-/* Transceiver MAC Short Address Register (Low Byte) */
-#define SHORT_ADDR_0                    _SFR_MEM8(0x160)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_0 {
-        unsigned int short_addr_00 : 1;	/* MAC Short Address */
-        unsigned int short_addr_01 : 1;	/* MAC Short Address */
-        unsigned int short_addr_02 : 1;	/* MAC Short Address */
-        unsigned int short_addr_03 : 1;	/* MAC Short Address */
-        unsigned int short_addr_04 : 1;	/* MAC Short Address */
-        unsigned int short_addr_05 : 1;	/* MAC Short Address */
-        unsigned int short_addr_06 : 1;	/* MAC Short Address */
-        unsigned int short_addr_07 : 1;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_0 */
-
-#define SHORT_ADDR_00                   0
-#define SHORT_ADDR_01                   1
-#define SHORT_ADDR_02                   2
-#define SHORT_ADDR_03                   3
-#define SHORT_ADDR_04                   4
-#define SHORT_ADDR_05                   5
-#define SHORT_ADDR_06                   6
-#define SHORT_ADDR_07                   7
-
-/* Transceiver MAC Short Address Register (High Byte) */
-#define SHORT_ADDR_1                    _SFR_MEM8(0x161)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_1 {
-        unsigned int short_addr_ : 8;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_1 */
-
-#define SHORT_ADDR_10                   0
-#define SHORT_ADDR_11                   1
-#define SHORT_ADDR_12                   2
-#define SHORT_ADDR_13                   3
-#define SHORT_ADDR_14                   4
-#define SHORT_ADDR_15                   5
-#define SHORT_ADDR_16                   6
-#define SHORT_ADDR_17                   7
-
-/* Transceiver Personal Area Network ID Register (Low Byte) */
-#define PAN_ID_0                        _SFR_MEM8(0x162)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_0 {
-        unsigned int pan_id_00 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_01 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_02 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_03 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_04 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_05 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_06 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_07 : 1;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_0 */
-
-#define PAN_ID_00                       0
-#define PAN_ID_01                       1
-#define PAN_ID_02                       2
-#define PAN_ID_03                       3
-#define PAN_ID_04                       4
-#define PAN_ID_05                       5
-#define PAN_ID_06                       6
-#define PAN_ID_07                       7
-
-/* Transceiver Personal Area Network ID Register (High Byte) */
-#define PAN_ID_1                        _SFR_MEM8(0x163)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_1 {
-        unsigned int pan_id_ : 8;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_1 */
-
-#define PAN_ID_10                       0
-#define PAN_ID_11                       1
-#define PAN_ID_12                       2
-#define PAN_ID_13                       3
-#define PAN_ID_14                       4
-#define PAN_ID_15                       5
-#define PAN_ID_16                       6
-#define PAN_ID_17                       7
-
-/* Transceiver MAC IEEE Address Register 0 */
-#define IEEE_ADDR_0                     _SFR_MEM8(0x164)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_0 {
-        unsigned int ieee_addr_00 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_01 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_02 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_03 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_04 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_05 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_06 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_07 : 1;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_0 */
-
-#define IEEE_ADDR_00                    0
-#define IEEE_ADDR_01                    1
-#define IEEE_ADDR_02                    2
-#define IEEE_ADDR_03                    3
-#define IEEE_ADDR_04                    4
-#define IEEE_ADDR_05                    5
-#define IEEE_ADDR_06                    6
-#define IEEE_ADDR_07                    7
-
-/* Transceiver MAC IEEE Address Register 1 */
-#define IEEE_ADDR_1                     _SFR_MEM8(0x165)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_1 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_1 */
-
-#define IEEE_ADDR_10                    0
-#define IEEE_ADDR_11                    1
-#define IEEE_ADDR_12                    2
-#define IEEE_ADDR_13                    3
-#define IEEE_ADDR_14                    4
-#define IEEE_ADDR_15                    5
-#define IEEE_ADDR_16                    6
-#define IEEE_ADDR_17                    7
-
-/* Transceiver MAC IEEE Address Register 2 */
-#define IEEE_ADDR_2                     _SFR_MEM8(0x166)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_2 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_2 */
-
-#define IEEE_ADDR_20                    0
-#define IEEE_ADDR_21                    1
-#define IEEE_ADDR_22                    2
-#define IEEE_ADDR_23                    3
-#define IEEE_ADDR_24                    4
-#define IEEE_ADDR_25                    5
-#define IEEE_ADDR_26                    6
-#define IEEE_ADDR_27                    7
-
-/* Transceiver MAC IEEE Address Register 3 */
-#define IEEE_ADDR_3                     _SFR_MEM8(0x167)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_3 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_3 */
-
-#define IEEE_ADDR_30                    0
-#define IEEE_ADDR_31                    1
-#define IEEE_ADDR_32                    2
-#define IEEE_ADDR_33                    3
-#define IEEE_ADDR_34                    4
-#define IEEE_ADDR_35                    5
-#define IEEE_ADDR_36                    6
-#define IEEE_ADDR_37                    7
-
-/* Transceiver MAC IEEE Address Register 4 */
-#define IEEE_ADDR_4                     _SFR_MEM8(0x168)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_4 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_4 */
-
-#define IEEE_ADDR_40                    0
-#define IEEE_ADDR_41                    1
-#define IEEE_ADDR_42                    2
-#define IEEE_ADDR_43                    3
-#define IEEE_ADDR_44                    4
-#define IEEE_ADDR_45                    5
-#define IEEE_ADDR_46                    6
-#define IEEE_ADDR_47                    7
-
-/* Transceiver MAC IEEE Address Register 5 */
-#define IEEE_ADDR_5                     _SFR_MEM8(0x169)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_5 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_5 */
-
-#define IEEE_ADDR_50                    0
-#define IEEE_ADDR_51                    1
-#define IEEE_ADDR_52                    2
-#define IEEE_ADDR_53                    3
-#define IEEE_ADDR_54                    4
-#define IEEE_ADDR_55                    5
-#define IEEE_ADDR_56                    6
-#define IEEE_ADDR_57                    7
-
-/* Transceiver MAC IEEE Address Register 6 */
-#define IEEE_ADDR_6                     _SFR_MEM8(0x16A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_6 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_6 */
-
-#define IEEE_ADDR_60                    0
-#define IEEE_ADDR_61                    1
-#define IEEE_ADDR_62                    2
-#define IEEE_ADDR_63                    3
-#define IEEE_ADDR_64                    4
-#define IEEE_ADDR_65                    5
-#define IEEE_ADDR_66                    6
-#define IEEE_ADDR_67                    7
-
-/* Transceiver MAC IEEE Address Register 7 */
-#define IEEE_ADDR_7                     _SFR_MEM8(0x16B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_7 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_7 */
-
-#define IEEE_ADDR_70                    0
-#define IEEE_ADDR_71                    1
-#define IEEE_ADDR_72                    2
-#define IEEE_ADDR_73                    3
-#define IEEE_ADDR_74                    4
-#define IEEE_ADDR_75                    5
-#define IEEE_ADDR_76                    6
-#define IEEE_ADDR_77                    7
-
-/* Transceiver Extended Operating Mode Control Register */
-#define XAH_CTRL_0                      _SFR_MEM8(0x16C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_0 {
-        unsigned int slotted_operation : 1;	/* Set Slotted Acknowledgment */
-        unsigned int max_csma_retries : 3;	/* Maximum Number of CSMA-CA Procedure Repetition Attempts */
-        unsigned int max_frame_retries : 4;	/* Maximum Number of Frame Re-transmission Attempts */
-};
-
-#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0)
-
-/* symbolic names */
-
-#define SLOTTED_OP_DIS                  0
-#define SLOTTED_OP_EN                   1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_0 */
-
-#define SLOTTED_OPERATION               0
-#define MAX_CSMA_RETRIES0               1
-#define MAX_CSMA_RETRIES1               2
-#define MAX_CSMA_RETRIES2               3
-#define MAX_FRAME_RETRIES0              4
-#define MAX_FRAME_RETRIES1              5
-#define MAX_FRAME_RETRIES2              6
-#define MAX_FRAME_RETRIES3              7
-
-/* Transceiver CSMA-CA Random Number Generator Seed Register */
-#define CSMA_SEED_0                     _SFR_MEM8(0x16D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_0 {
-        unsigned int csma_seed_00 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_01 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_02 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_03 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_04 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_05 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_06 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_07 : 1;	/* Seed Value for CSMA Random Number Generator */
-};
-
-#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_0 */
-
-#define CSMA_SEED_00                    0
-#define CSMA_SEED_01                    1
-#define CSMA_SEED_02                    2
-#define CSMA_SEED_03                    3
-#define CSMA_SEED_04                    4
-#define CSMA_SEED_05                    5
-#define CSMA_SEED_06                    6
-#define CSMA_SEED_07                    7
-
-/* Transceiver Acknowledgment Frame Control Register 2 */
-#define CSMA_SEED_1                     _SFR_MEM8(0x16E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_1 {
-        unsigned int csma_seed_1 : 3;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int aack_i_am_coord : 1;	/* Set Personal Area Network Coordinator */
-        unsigned int aack_dis_ack : 1;	/* Disable Acknowledgment Frame Transmission */
-        unsigned int aack_set_pd : 1;	/* Set Frame Pending Sub-field */
-        unsigned int aack_fvn_mode : 2;	/* Acknowledgment Frame Filter Mode */
-};
-
-#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_1 */
-
-#define CSMA_SEED_10                    0
-#define CSMA_SEED_11                    1
-#define CSMA_SEED_12                    2
-#define AACK_I_AM_COORD                 3
-#define AACK_DIS_ACK                    4
-#define AACK_SET_PD                     5
-#define AACK_FVN_MODE0                  6
-#define AACK_FVN_MODE1                  7
-
-/* Transceiver CSMA-CA Back-off Exponent Control Register */
-#define CSMA_BE                         _SFR_MEM8(0x16F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_BE {
-        unsigned int min_be : 4;	/* Minimum Back-off Exponent */
-        unsigned int max_be : 4;	/* Maximum Back-off Exponent */
-};
-
-#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_BE */
-
-#define MIN_BE0                         0
-#define MIN_BE1                         1
-#define MIN_BE2                         2
-#define MIN_BE3                         3
-#define MAX_BE0                         4
-#define MAX_BE1                         5
-#define MAX_BE2                         6
-#define MAX_BE3                         7
-
-/* Transceiver Digital Test Control Register */
-#define TST_CTRL_DIGI                   _SFR_MEM8(0x176)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_CTRL_DIGI {
-        unsigned int tst_ctrl_dig : 4;	/* Digital Test Controller Register */
-        unsigned int : 4;
-};
-
-#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_CTRL_DIGI */
-
-#define TST_CTRL_DIG0                   0
-#define TST_CTRL_DIG1                   1
-#define TST_CTRL_DIG2                   2
-#define TST_CTRL_DIG3                   3
-
-/* Transceiver Received Frame Length Register */
-#define TST_RX_LENGTH                   _SFR_MEM8(0x17B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_RX_LENGTH {
-        unsigned int rx_length : 8;	/* Received Frame Length */
-};
-
-#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH)
-
-#endif /* __ASSEMBLER__ */
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
 
-  /* TST_RX_LENGTH */
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
 
-#define RX_LENGTH0                      0
-#define RX_LENGTH1                      1
-#define RX_LENGTH2                      2
-#define RX_LENGTH3                      3
-#define RX_LENGTH4                      4
-#define RX_LENGTH5                      5
-#define RX_LENGTH6                      6
-#define RX_LENGTH7                      7
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define MUX5    3
+#define ACCH    4
+#define REFOK   5
+#define AVDDOK  7
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC8D   0
+#define ADC9D   1
+#define ADC10D  2
+#define ADC11D  3
+#define ADC12D  4
+#define ADC13D  5
+#define ADC14D  6
+#define ADC15D  7
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1C0  2
+#define COM1C1  3
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1C   5
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define WGM30   0
+#define WGM31   1
+#define COM3C0  2
+#define COM3C1  3
+#define COM3B0  4
+#define COM3B1  5
+#define COM3A0  6
+#define COM3A1  7
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define CS30    0
+#define CS31    1
+#define CS32    2
+#define WGM32   3
+#define WGM33   4
+#define ICES3   6
+#define ICNC3   7
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3C   5
+#define FOC3B   6
+#define FOC3A   7
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define WGM40   0
+#define WGM41   1
+#define COM4C0  2
+#define COM4C1  3
+#define COM4B0  4
+#define COM4B1  5
+#define COM4A0  6
+#define COM4A1  7
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define CS40    0
+#define CS41    1
+#define CS42    2
+#define WGM42   3
+#define WGM43   4
+#define ICES4   6
+#define ICNC4   7
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4C   5
+#define FOC4B   6
+#define FOC4A   7
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+#define EXCLKAMR 7
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+#define IRQ_MASK1 _SFR_MEM8(0xBE)
+#define TX_START_EN 0
+#define MAF_0_AMI_EN 1
+#define MAF_1_AMI_EN 2
+#define MAF_2_AMI_EN 3
+#define MAF_3_AMI_EN 4
+
+#define IRQ_STATUS1 _SFR_MEM8(0xBF)
+#define TX_START 0
+#define MAF_0_AMI 1
+#define MAF_1_AMI 2
+#define MAF_2_AMI 3
+#define MAF_3_AMI 4
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+#define UCPHA0  1
+#define UDORD0  2
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+#define UCSR1B  _SFR_MEM8(0xC9)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+#define UCPHA1  1
+#define UDORD1  2
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0xCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define SCRSTRLL _SFR_MEM8(0xD7)
+#define SCRSTRLL0 0
+#define SCRSTRLL1 1
+#define SCRSTRLL2 2
+#define SCRSTRLL3 3
+#define SCRSTRLL4 4
+#define SCRSTRLL5 5
+#define SCRSTRLL6 6
+#define SCRSTRLL7 7
+
+#define SCRSTRLH _SFR_MEM8(0xD8)
+#define SCRSTRLH0 0
+#define SCRSTRLH1 1
+#define SCRSTRLH2 2
+#define SCRSTRLH3 3
+#define SCRSTRLH4 4
+#define SCRSTRLH5 5
+#define SCRSTRLH6 6
+#define SCRSTRLH7 7
+
+#define SCRSTRHL _SFR_MEM8(0xD9)
+#define SCRSTRHL0 0
+#define SCRSTRHL1 1
+#define SCRSTRHL2 2
+#define SCRSTRHL3 3
+#define SCRSTRHL4 4
+#define SCRSTRHL5 5
+#define SCRSTRHL6 6
+#define SCRSTRHL7 7
+
+#define SCRSTRHH _SFR_MEM8(0xDA)
+#define SCRSTRHH0 0
+#define SCRSTRHH1 1
+#define SCRSTRHH2 2
+#define SCRSTRHH3 3
+#define SCRSTRHH4 4
+#define SCRSTRHH5 5
+#define SCRSTRHH6 6
+#define SCRSTRHH7 7
+
+#define SCCSR   _SFR_MEM8(0xDB)
+#define SCCS10  0
+#define SCCS11  1
+#define SCCS20  2
+#define SCCS21  3
+#define SCCS30  4
+#define SCCS31  5
+
+#define SCCR0   _SFR_MEM8(0xDC)
+#define SCCMP1  0
+#define SCCMP2  1
+#define SCCMP3  2
+#define SCTSE   3
+#define SCCKSEL 4
+#define SCEN    5
+#define SCMBTS  6
+#define SCRES   7
+
+#define SCCR1   _SFR_MEM8(0xDD)
+#define SCENBO  0
+#define SCEECLK 1
+#define SCCKDIV0 2
+#define SCCKDIV1 3
+#define SCCKDIV2 4
+#define SCBTSM  5
+
+#define SCSR    _SFR_MEM8(0xDE)
+#define SCBSY   0
+
+#define SCIRQM  _SFR_MEM8(0xDF)
+#define IRQMCP1 0
+#define IRQMCP2 1
+#define IRQMCP3 2
+#define IRQMOF  3
+#define IRQMBO  4
+
+#define SCIRQS  _SFR_MEM8(0xE0)
+#define IRQSCP1 0
+#define IRQSCP2 1
+#define IRQSCP3 2
+#define IRQSOF  3
+#define IRQSBO  4
+
+#define SCCNTLL _SFR_MEM8(0xE1)
+#define SCCNTLL0 0
+#define SCCNTLL1 1
+#define SCCNTLL2 2
+#define SCCNTLL3 3
+#define SCCNTLL4 4
+#define SCCNTLL5 5
+#define SCCNTLL6 6
+#define SCCNTLL7 7
+
+#define SCCNTLH _SFR_MEM8(0xE2)
+#define SCCNTLH0 0
+#define SCCNTLH1 1
+#define SCCNTLH2 2
+#define SCCNTLH3 3
+#define SCCNTLH4 4
+#define SCCNTLH5 5
+#define SCCNTLH6 6
+#define SCCNTLH7 7
+
+#define SCCNTHL _SFR_MEM8(0xE3)
+#define SCCNTHL0 0
+#define SCCNTHL1 1
+#define SCCNTHL2 2
+#define SCCNTHL3 3
+#define SCCNTHL4 4
+#define SCCNTHL5 5
+#define SCCNTHL6 6
+#define SCCNTHL7 7
+
+#define SCCNTHH _SFR_MEM8(0xE4)
+#define SCCNTHH0 0
+#define SCCNTHH1 1
+#define SCCNTHH2 2
+#define SCCNTHH3 3
+#define SCCNTHH4 4
+#define SCCNTHH5 5
+#define SCCNTHH6 6
+#define SCCNTHH7 7
+
+#define SCBTSRLL _SFR_MEM8(0xE5)
+#define SCBTSRLL0 0
+#define SCBTSRLL1 1
+#define SCBTSRLL2 2
+#define SCBTSRLL3 3
+#define SCBTSRLL4 4
+#define SCBTSRLL5 5
+#define SCBTSRLL6 6
+#define SCBTSRLL7 7
+
+#define SCBTSRLH _SFR_MEM8(0xE6)
+#define SCBTSRLH0 0
+#define SCBTSRLH1 1
+#define SCBTSRLH2 2
+#define SCBTSRLH3 3
+#define SCBTSRLH4 4
+#define SCBTSRLH5 5
+#define SCBTSRLH6 6
+#define SCBTSRLH7 7
+
+#define SCBTSRHL _SFR_MEM8(0xE7)
+#define SCBTSRHL0 0
+#define SCBTSRHL1 1
+#define SCBTSRHL2 2
+#define SCBTSRHL3 3
+#define SCBTSRHL4 4
+#define SCBTSRHL5 5
+#define SCBTSRHL6 6
+#define SCBTSRHL7 7
+
+#define SCBTSRHH _SFR_MEM8(0xE8)
+#define SCBTSRHH0 0
+#define SCBTSRHH1 1
+#define SCBTSRHH2 2
+#define SCBTSRHH3 3
+#define SCBTSRHH4 4
+#define SCBTSRHH5 5
+#define SCBTSRHH6 6
+#define SCBTSRHH7 7
+
+#define SCTSRLL _SFR_MEM8(0xE9)
+#define SCTSRLL0 0
+#define SCTSRLL1 1
+#define SCTSRLL2 2
+#define SCTSRLL3 3
+#define SCTSRLL4 4
+#define SCTSRLL5 5
+#define SCTSRLL6 6
+#define SCTSRLL7 7
+
+#define SCTSRLH _SFR_MEM8(0xEA)
+#define SCTSRLH0 0
+#define SCTSRLH1 1
+#define SCTSRLH2 2
+#define SCTSRLH3 3
+#define SCTSRLH4 4
+#define SCTSRLH5 5
+#define SCTSRLH6 6
+#define SCTSRLH7 7
+
+#define SCTSRHL _SFR_MEM8(0xEB)
+#define SCTSRHL0 0
+#define SCTSRHL1 1
+#define SCTSRHL2 2
+#define SCTSRHL3 3
+#define SCTSRHL4 4
+#define SCTSRHL5 5
+#define SCTSRHL6 6
+#define SCTSRHL7 7
+
+#define SCTSRHH _SFR_MEM8(0xEC)
+#define SCTSRHH0 0
+#define SCTSRHH1 1
+#define SCTSRHH2 2
+#define SCTSRHH3 3
+#define SCTSRHH4 4
+#define SCTSRHH5 5
+#define SCTSRHH6 6
+#define SCTSRHH7 7
+
+#define SCOCR3LL _SFR_MEM8(0xED)
+#define SCOCR3LL0 0
+#define SCOCR3LL1 1
+#define SCOCR3LL2 2
+#define SCOCR3LL3 3
+#define SCOCR3LL4 4
+#define SCOCR3LL5 5
+#define SCOCR3LL6 6
+#define SCOCR3LL7 7
+
+#define SCOCR3LH _SFR_MEM8(0xEE)
+#define SCOCR3LH0 0
+#define SCOCR3LH1 1
+#define SCOCR3LH2 2
+#define SCOCR3LH3 3
+#define SCOCR3LH4 4
+#define SCOCR3LH5 5
+#define SCOCR3LH6 6
+#define SCOCR3LH7 7
+
+#define SCOCR3HL _SFR_MEM8(0xEF)
+#define SCOCR3HL0 0
+#define SCOCR3HL1 1
+#define SCOCR3HL2 2
+#define SCOCR3HL3 3
+#define SCOCR3HL4 4
+#define SCOCR3HL5 5
+#define SCOCR3HL6 6
+#define SCOCR3HL7 7
+
+#define SCOCR3HH _SFR_MEM8(0xF0)
+#define SCOCR3HH0 0
+#define SCOCR3HH1 1
+#define SCOCR3HH2 2
+#define SCOCR3HH3 3
+#define SCOCR3HH4 4
+#define SCOCR3HH5 5
+#define SCOCR3HH6 6
+#define SCOCR3HH7 7
+
+#define SCOCR2LL _SFR_MEM8(0xF1)
+#define SCOCR2LL0 0
+#define SCOCR2LL1 1
+#define SCOCR2LL2 2
+#define SCOCR2LL3 3
+#define SCOCR2LL4 4
+#define SCOCR2LL5 5
+#define SCOCR2LL6 6
+#define SCOCR2LL7 7
+
+#define SCOCR2LH _SFR_MEM8(0xF2)
+#define SCOCR2LH0 0
+#define SCOCR2LH1 1
+#define SCOCR2LH2 2
+#define SCOCR2LH3 3
+#define SCOCR2LH4 4
+#define SCOCR2LH5 5
+#define SCOCR2LH6 6
+#define SCOCR2LH7 7
+
+#define SCOCR2HL _SFR_MEM8(0xF3)
+#define SCOCR2HL0 0
+#define SCOCR2HL1 1
+#define SCOCR2HL2 2
+#define SCOCR2HL3 3
+#define SCOCR2HL4 4
+#define SCOCR2HL5 5
+#define SCOCR2HL6 6
+#define SCOCR2HL7 7
+
+#define SCOCR2HH _SFR_MEM8(0xF4)
+#define SCOCR2HH0 0
+#define SCOCR2HH1 1
+#define SCOCR2HH2 2
+#define SCOCR2HH3 3
+#define SCOCR2HH4 4
+#define SCOCR2HH5 5
+#define SCOCR2HH6 6
+#define SCOCR2HH7 7
+
+#define SCOCR1LL _SFR_MEM8(0xF5)
+#define SCOCR1LL0 0
+#define SCOCR1LL1 1
+#define SCOCR1LL2 2
+#define SCOCR1LL3 3
+#define SCOCR1LL4 4
+#define SCOCR1LL5 5
+#define SCOCR1LL6 6
+#define SCOCR1LL7 7
+
+#define SCOCR1LH _SFR_MEM8(0xF6)
+#define SCOCR1LH0 0
+#define SCOCR1LH1 1
+#define SCOCR1LH2 2
+#define SCOCR1LH3 3
+#define SCOCR1LH4 4
+#define SCOCR1LH5 5
+#define SCOCR1LH6 6
+#define SCOCR1LH7 7
+
+#define SCOCR1HL _SFR_MEM8(0xF7)
+#define SCOCR1HL0 0
+#define SCOCR1HL1 1
+#define SCOCR1HL2 2
+#define SCOCR1HL3 3
+#define SCOCR1HL4 4
+#define SCOCR1HL5 5
+#define SCOCR1HL6 6
+#define SCOCR1HL7 7
+
+#define SCOCR1HH _SFR_MEM8(0xF8)
+#define SCOCR1HH0 0
+#define SCOCR1HH1 1
+#define SCOCR1HH2 2
+#define SCOCR1HH3 3
+#define SCOCR1HH4 4
+#define SCOCR1HH5 5
+#define SCOCR1HH6 6
+#define SCOCR1HH7 7
+
+#define SCTSTRLL _SFR_MEM8(0xF9)
+#define SCTSTRLL0 0
+#define SCTSTRLL1 1
+#define SCTSTRLL2 2
+#define SCTSTRLL3 3
+#define SCTSTRLL4 4
+#define SCTSTRLL5 5
+#define SCTSTRLL6 6
+#define SCTSTRLL7 7
+
+#define SCTSTRLH _SFR_MEM8(0xFA)
+#define SCTSTRLH0 0
+#define SCTSTRLH1 1
+#define SCTSTRLH2 2
+#define SCTSTRLH3 3
+#define SCTSTRLH4 4
+#define SCTSTRLH5 5
+#define SCTSTRLH6 6
+#define SCTSTRLH7 7
+
+#define SCTSTRHL _SFR_MEM8(0xFB)
+#define SCTSTRHL0 0
+#define SCTSTRHL1 1
+#define SCTSTRHL2 2
+#define SCTSTRHL3 3
+#define SCTSTRHL4 4
+#define SCTSTRHL5 5
+#define SCTSTRHL6 6
+#define SCTSTRHL7 7
+
+#define SCTSTRHH _SFR_MEM8(0xFC)
+#define SCTSTRHH0 0
+#define SCTSTRHH1 1
+#define SCTSTRHH2 2
+#define SCTSTRHH3 3
+#define SCTSTRHH4 4
+#define SCTSTRHH5 5
+#define SCTSTRHH6 6
+#define SCTSTRHH7 7
+
+/* Reserved [0xFD..0x10B] */
+
+#define MAFCR0  _SFR_MEM8(0x10C)
+#define MAF0EN  0
+#define MAF1EN  1
+#define MAF2EN  2
+#define MAF3EN  3
+
+#define MAFCR1  _SFR_MEM8(0x10D)
+#define AACK_0_I_AM_COORD 0
+#define AACK_0_SET_PD 1
+#define AACK_1_I_AM_COORD 2
+#define AACK_1_SET_PD 3
+#define AACK_2_I_AM_COORD 4
+#define AACK_2_SET_PD 5
+#define AACK_3_I_AM_COORD 6
+#define AACK_3_SET_PD 7
+
+#define MAFSA0L _SFR_MEM8(0x10E)
+#define MAFSA0L0 0
+#define MAFSA0L1 1
+#define MAFSA0L2 2
+#define MAFSA0L3 3
+#define MAFSA0L4 4
+#define MAFSA0L5 5
+#define MAFSA0L6 6
+#define MAFSA0L7 7
+
+#define MAFSA0H _SFR_MEM8(0x10F)
+#define MAFSA0H0 0
+#define MAFSA0H1 1
+#define MAFSA0H2 2
+#define MAFSA0H3 3
+#define MAFSA0H4 4
+#define MAFSA0H5 5
+#define MAFSA0H6 6
+#define MAFSA0H7 7
+
+#define MAFPA0L _SFR_MEM8(0x110)
+#define MAFPA0L0 0
+#define MAFPA0L1 1
+#define MAFPA0L2 2
+#define MAFPA0L3 3
+#define MAFPA0L4 4
+#define MAFPA0L5 5
+#define MAFPA0L6 6
+#define MAFPA0L7 7
+
+#define MAFPA0H _SFR_MEM8(0x111)
+#define MAFPA0H0 0
+#define MAFPA0H1 1
+#define MAFPA0H2 2
+#define MAFPA0H3 3
+#define MAFPA0H4 4
+#define MAFPA0H5 5
+#define MAFPA0H6 6
+#define MAFPA0H7 7
+
+#define MAFSA1L _SFR_MEM8(0x112)
+#define MAFSA1L0 0
+#define MAFSA1L1 1
+#define MAFSA1L2 2
+#define MAFSA1L3 3
+#define MAFSA1L4 4
+#define MAFSA1L5 5
+#define MAFSA1L6 6
+#define MAFSA1L7 7
+
+#define MAFSA1H _SFR_MEM8(0x113)
+#define MAFSA1H0 0
+#define MAFSA1H1 1
+#define MAFSA1H2 2
+#define MAFSA1H3 3
+#define MAFSA1H4 4
+#define MAFSA1H5 5
+#define MAFSA1H6 6
+#define MAFSA1H7 7
+
+#define MAFPA1L _SFR_MEM8(0x114)
+#define MAFPA1L0 0
+#define MAFPA1L1 1
+#define MAFPA1L2 2
+#define MAFPA1L3 3
+#define MAFPA1L4 4
+#define MAFPA1L5 5
+#define MAFPA1L6 6
+#define MAFPA1L7 7
+
+#define MAFPA1H _SFR_MEM8(0x115)
+#define MAFPA1H0 0
+#define MAFPA1H1 1
+#define MAFPA1H2 2
+#define MAFPA1H3 3
+#define MAFPA1H4 4
+#define MAFPA1H5 5
+#define MAFPA1H6 6
+#define MAFPA1H7 7
+
+#define MAFSA2L _SFR_MEM8(0x116)
+#define MAFSA2L0 0
+#define MAFSA2L1 1
+#define MAFSA2L2 2
+#define MAFSA2L3 3
+#define MAFSA2L4 4
+#define MAFSA2L5 5
+#define MAFSA2L6 6
+#define MAFSA2L7 7
+
+#define MAFSA2H _SFR_MEM8(0x117)
+#define MAFSA2H0 0
+#define MAFSA2H1 1
+#define MAFSA2H2 2
+#define MAFSA2H3 3
+#define MAFSA2H4 4
+#define MAFSA2H5 5
+#define MAFSA2H6 6
+#define MAFSA2H7 7
+
+#define MAFPA2L _SFR_MEM8(0x118)
+#define MAFPA2L0 0
+#define MAFPA2L1 1
+#define MAFPA2L2 2
+#define MAFPA2L3 3
+#define MAFPA2L4 4
+#define MAFPA2L5 5
+#define MAFPA2L6 6
+#define MAFPA2L7 7
+
+#define MAFPA2H _SFR_MEM8(0x119)
+#define MAFPA2H0 0
+#define MAFPA2H1 1
+#define MAFPA2H2 2
+#define MAFPA2H3 3
+#define MAFPA2H4 4
+#define MAFPA2H5 5
+#define MAFPA2H6 6
+#define MAFPA2H7 7
+
+#define MAFSA3L _SFR_MEM8(0x11A)
+#define MAFSA3L0 0
+#define MAFSA3L1 1
+#define MAFSA3L2 2
+#define MAFSA3L3 3
+#define MAFSA3L4 4
+#define MAFSA3L5 5
+#define MAFSA3L6 6
+#define MAFSA3L7 7
+
+#define MAFSA3H _SFR_MEM8(0x11B)
+#define MAFSA3H0 0
+#define MAFSA3H1 1
+#define MAFSA3H2 2
+#define MAFSA3H3 3
+#define MAFSA3H4 4
+#define MAFSA3H5 5
+#define MAFSA3H6 6
+#define MAFSA3H7 7
+
+#define MAFPA3L _SFR_MEM8(0x11C)
+#define MAFPA3L0 0
+#define MAFPA3L1 1
+#define MAFPA3L2 2
+#define MAFPA3L3 3
+#define MAFPA3L4 4
+#define MAFPA3L5 5
+#define MAFPA3L6 6
+#define MAFPA3L7 7
+
+#define MAFPA3H _SFR_MEM8(0x11D)
+#define MAFPA3H0 0
+#define MAFPA3H1 1
+#define MAFPA3H2 2
+#define MAFPA3H3 3
+#define MAFPA3H4 4
+#define MAFPA3H5 5
+#define MAFPA3H6 6
+#define MAFPA3H7 7
+
+/* Reserved [0x11E..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define WGM50   0
+#define WGM51   1
+#define COM5C0  2
+#define COM5C1  3
+#define COM5B0  4
+#define COM5B1  5
+#define COM5A0  6
+#define COM5A1  7
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define CS50    0
+#define CS51    1
+#define CS52    2
+#define WGM52   3
+#define WGM53   4
+#define ICES5   6
+#define ICNC5   7
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5C   5
+#define FOC5B   6
+#define FOC5A   7
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E] */
+
+#define LLCR    _SFR_MEM8(0x12F)
+#define LLENCAL 0
+#define LLSHORT 1
+#define LLTCO   2
+#define LLCAL   3
+#define LLCOMP  4
+#define LLDONE  5
+
+#define LLDRL   _SFR_MEM8(0x130)
+#define LLDRL0  0
+#define LLDRL1  1
+#define LLDRL2  2
+#define LLDRL3  3
+
+#define LLDRH   _SFR_MEM8(0x131)
+#define LLDRH0  0
+#define LLDRH1  1
+#define LLDRH2  2
+#define LLDRH3  3
+#define LLDRH4  4
+
+#define DRTRAM3 _SFR_MEM8(0x132)
+#define ENDRT   4
+#define DRTSWOK 5
+
+#define DRTRAM2 _SFR_MEM8(0x133)
+
+#define DRTRAM1 _SFR_MEM8(0x134)
+
+#define DRTRAM0 _SFR_MEM8(0x135)
+
+#define DPDS0   _SFR_MEM8(0x136)
+#define PBDRV0  0
+#define PBDRV1  1
+#define PDDRV0  2
+#define PDDRV1  3
+#define PEDRV0  4
+#define PEDRV1  5
+#define PFDRV0  6
+#define PFDRV1  7
+
+#define DPDS1   _SFR_MEM8(0x137)
+#define PGDRV0  0
+#define PGDRV1  1
+
+#define PARCR   _SFR_MEM8(0x138)
+#define PARUFI  0
+#define PARDFI  1
+#define PALTU0  2
+#define PALTU1  3
+#define PALTU2  4
+#define PALTD0  5
+#define PALTD1  6
+#define PALTD2  7
+
+#define TRXPR   _SFR_MEM8(0x139)
+#define TRXRST  0
+#define SLPTR   1
+
+/* Reserved [0x13A..0x13B] */
+
+#define AES_CTRL _SFR_MEM8(0x13C)
+#define AES_IM  2
+#define AES_DIR 3
+#define AES_MODE 5
+#define AES_REQUEST 7
+
+#define AES_STATUS _SFR_MEM8(0x13D)
+#define AES_DONE 0
+#define AES_ER  7
+
+#define AES_STATE _SFR_MEM8(0x13E)
+#define AES_STATE0 0
+#define AES_STATE1 1
+#define AES_STATE2 2
+#define AES_STATE3 3
+#define AES_STATE4 4
+#define AES_STATE5 5
+#define AES_STATE6 6
+#define AES_STATE7 7
+
+#define AES_KEY _SFR_MEM8(0x13F)
+#define AES_KEY0 0
+#define AES_KEY1 1
+#define AES_KEY2 2
+#define AES_KEY3 3
+#define AES_KEY4 4
+#define AES_KEY5 5
+#define AES_KEY6 6
+#define AES_KEY7 7
+
+/* Reserved [0x140] */
+
+#define TRX_STATUS _SFR_MEM8(0x141)
+#define TRX_STATUS0 0
+#define TRX_STATUS1 1
+#define TRX_STATUS2 2
+#define TRX_STATUS3 3
+#define TRX_STATUS4 4
+#define TST_STATUS 5
+#define CCA_STATUS 6
+#define CCA_DONE 7
+
+#define TRX_STATE _SFR_MEM8(0x142)
+#define TRX_CMD0 0
+#define TRX_CMD1 1
+#define TRX_CMD2 2
+#define TRX_CMD3 3
+#define TRX_CMD4 4
+#define TRAC_STATUS0 5
+#define TRAC_STATUS1 6
+#define TRAC_STATUS2 7
+
+#define TRX_CTRL_0 _SFR_MEM8(0x143)
+#define PMU_IF_INV 4
+#define PMU_START 5
+#define PMU_EN  6
+#define Res7    7
+
+#define TRX_CTRL_1 _SFR_MEM8(0x144)
+#define PLL_TX_FLT 4
+#define TX_AUTO_CRC_ON 5
+#define IRQ_2_EXT_EN 6
+#define PA_EXT_EN 7
+
+#define PHY_TX_PWR _SFR_MEM8(0x145)
+#define TX_PWR0 0
+#define TX_PWR1 1
+#define TX_PWR2 2
+#define TX_PWR3 3
+
+#define PHY_RSSI _SFR_MEM8(0x146)
+#define RSSI0   0
+#define RSSI1   1
+#define RSSI2   2
+#define RSSI3   3
+#define RSSI4   4
+#define RND_VALUE0 5
+#define RND_VALUE1 6
+#define RX_CRC_VALID 7
+
+#define PHY_ED_LEVEL _SFR_MEM8(0x147)
+#define ED_LEVEL0 0
+#define ED_LEVEL1 1
+#define ED_LEVEL2 2
+#define ED_LEVEL3 3
+#define ED_LEVEL4 4
+#define ED_LEVEL5 5
+#define ED_LEVEL6 6
+#define ED_LEVEL7 7
+
+#define PHY_CC_CCA _SFR_MEM8(0x148)
+#define CHANNEL0 0
+#define CHANNEL1 1
+#define CHANNEL2 2
+#define CHANNEL3 3
+#define CHANNEL4 4
+#define CCA_MODE0 5
+#define CCA_MODE1 6
+#define CCA_REQUEST 7
+
+#define CCA_THRES _SFR_MEM8(0x149)
+#define CCA_ED_THRES0 0
+#define CCA_ED_THRES1 1
+#define CCA_ED_THRES2 2
+#define CCA_ED_THRES3 3
+#define CCA_CS_THRES0 4
+#define CCA_CS_THRES1 5
+#define CCA_CS_THRES2 6
+#define CCA_CS_THRES3 7
+
+#define RX_CTRL _SFR_MEM8(0x14A)
+#define PDT_THRES0 0
+#define PDT_THRES1 1
+#define PDT_THRES2 2
+#define PDT_THRES3 3
+
+#define SFD_VALUE _SFR_MEM8(0x14B)
+#define SFD_VALUE0 0
+#define SFD_VALUE1 1
+#define SFD_VALUE2 2
+#define SFD_VALUE3 3
+#define SFD_VALUE4 4
+#define SFD_VALUE5 5
+#define SFD_VALUE6 6
+#define SFD_VALUE7 7
+
+#define TRX_CTRL_2 _SFR_MEM8(0x14C)
+#define OQPSK_DATA_RATE0 0
+#define OQPSK_DATA_RATE1 1
+#define RX_SAFE_MODE 7
+
+#define ANT_DIV _SFR_MEM8(0x14D)
+#define ANT_CTRL0 0
+#define ANT_CTRL1 1
+#define ANT_EXT_SW_EN 2
+#define ANT_DIV_EN 3
+#define ANT_SEL 7
+
+#define IRQ_MASK _SFR_MEM8(0x14E)
+#define PLL_LOCK_EN 0
+#define PLL_UNLOCK_EN 1
+#define RX_START_EN 2
+#define RX_END_EN 3
+#define CCA_ED_DONE_EN 4
+#define AMI_EN  5
+#define TX_END_EN 6
+#define AWAKE_EN 7
+
+#define IRQ_STATUS _SFR_MEM8(0x14F)
+#define PLL_LOCK 0
+#define PLL_UNLOCK 1
+#define RX_START 2
+#define RX_END  3
+#define CCA_ED_DONE 4
+#define AMI     5
+#define TX_END  6
+#define AWAKE   7
+
+#define VREG_CTRL _SFR_MEM8(0x150)
+#define DVDD_OK 2
+#define DVREG_EXT 3
+#define AVDD_OK 6
+#define AVREG_EXT 7
+
+#define BATMON  _SFR_MEM8(0x151)
+#define BATMON_VTH0 0
+#define BATMON_VTH1 1
+#define BATMON_VTH2 2
+#define BATMON_VTH3 3
+#define BATMON_HR 4
+#define BATMON_OK 5
+#define BAT_LOW_EN 6
+#define BAT_LOW 7
+
+#define XOSC_CTRL _SFR_MEM8(0x152)
+#define XTAL_TRIM0 0
+#define XTAL_TRIM1 1
+#define XTAL_TRIM2 2
+#define XTAL_TRIM3 3
+#define XTAL_MODE0 4
+#define XTAL_MODE1 5
+#define XTAL_MODE2 6
+#define XTAL_MODE3 7
+
+#define CC_CTRL_0 _SFR_MEM8(0x153)
+#define CC_NUMBER0 0
+#define CC_NUMBER1 1
+#define CC_NUMBER2 2
+#define CC_NUMBER3 3
+#define CC_NUMBER4 4
+#define CC_NUMBER5 5
+#define CC_NUMBER6 6
+#define CC_NUMBER7 7
+
+#define CC_CTRL_1 _SFR_MEM8(0x154)
+#define CC_BAND0 0
+#define CC_BAND1 1
+#define CC_BAND2 2
+#define CC_BAND3 3
+
+#define RX_SYN  _SFR_MEM8(0x155)
+#define RX_PDT_LEVEL0 0
+#define RX_PDT_LEVEL1 1
+#define RX_PDT_LEVEL2 2
+#define RX_PDT_LEVEL3 3
+#define RX_OVERRIDE 6
+#define RX_PDT_DIS 7
+
+#define TRX_RPC _SFR_MEM8(0x156)
+#define XAH_RPC_EN 0
+#define IPAN_RPC_EN 1
+#define PLL_RPC_EN 3
+#define PDT_RPC_EN 4
+#define RX_RPC_EN 5
+#define RX_RPC_CTRL0 6
+#define RX_RPC_CTRL1 7
+
+#define XAH_CTRL_1 _SFR_MEM8(0x157)
+#define AACK_PROM_MODE 1
+#define AACK_ACK_TIME 2
+#define AACK_UPLD_RES_FT 4
+#define AACK_FLTR_RES_FT 5
+
+#define FTN_CTRL _SFR_MEM8(0x158)
+#define FTN_START 7
+
+/* Reserved [0x159] */
+
+#define PLL_CF  _SFR_MEM8(0x15A)
+#define PLL_CF_START 7
+
+#define PLL_DCU _SFR_MEM8(0x15B)
+#define PLL_DCU_START 7
+
+#define PART_NUM _SFR_MEM8(0x15C)
+#define PART_NUM0 0
+#define PART_NUM1 1
+#define PART_NUM2 2
+#define PART_NUM3 3
+#define PART_NUM4 4
+#define PART_NUM5 5
+#define PART_NUM6 6
+#define PART_NUM7 7
+
+#define VERSION_NUM _SFR_MEM8(0x15D)
+#define VERSION_NUM0 0
+#define VERSION_NUM1 1
+#define VERSION_NUM2 2
+#define VERSION_NUM3 3
+#define VERSION_NUM4 4
+#define VERSION_NUM5 5
+#define VERSION_NUM6 6
+#define VERSION_NUM7 7
+
+#define MAN_ID_0 _SFR_MEM8(0x15E)
+#define MAN_ID_00 0
+#define MAN_ID_01 1
+#define MAN_ID_02 2
+#define MAN_ID_03 3
+#define MAN_ID_04 4
+#define MAN_ID_05 5
+#define MAN_ID_06 6
+#define MAN_ID_07 7
+
+#define MAN_ID_1 _SFR_MEM8(0x15F)
+#define MAN_ID_10 0
+#define MAN_ID_11 1
+#define MAN_ID_12 2
+#define MAN_ID_13 3
+#define MAN_ID_14 4
+#define MAN_ID_15 5
+#define MAN_ID_16 6
+#define MAN_ID_17 7
+
+#define SHORT_ADDR_0 _SFR_MEM8(0x160)
+#define SHORT_ADDR_00 0
+#define SHORT_ADDR_01 1
+#define SHORT_ADDR_02 2
+#define SHORT_ADDR_03 3
+#define SHORT_ADDR_04 4
+#define SHORT_ADDR_05 5
+#define SHORT_ADDR_06 6
+#define SHORT_ADDR_07 7
+
+#define SHORT_ADDR_1 _SFR_MEM8(0x161)
+#define SHORT_ADDR_10 0
+#define SHORT_ADDR_11 1
+#define SHORT_ADDR_12 2
+#define SHORT_ADDR_13 3
+#define SHORT_ADDR_14 4
+#define SHORT_ADDR_15 5
+#define SHORT_ADDR_16 6
+#define SHORT_ADDR_17 7
+
+#define PAN_ID_0 _SFR_MEM8(0x162)
+#define PAN_ID_00 0
+#define PAN_ID_01 1
+#define PAN_ID_02 2
+#define PAN_ID_03 3
+#define PAN_ID_04 4
+#define PAN_ID_05 5
+#define PAN_ID_06 6
+#define PAN_ID_07 7
+
+#define PAN_ID_1 _SFR_MEM8(0x163)
+#define PAN_ID_10 0
+#define PAN_ID_11 1
+#define PAN_ID_12 2
+#define PAN_ID_13 3
+#define PAN_ID_14 4
+#define PAN_ID_15 5
+#define PAN_ID_16 6
+#define PAN_ID_17 7
+
+#define IEEE_ADDR_0 _SFR_MEM8(0x164)
+#define IEEE_ADDR_00 0
+#define IEEE_ADDR_01 1
+#define IEEE_ADDR_02 2
+#define IEEE_ADDR_03 3
+#define IEEE_ADDR_04 4
+#define IEEE_ADDR_05 5
+#define IEEE_ADDR_06 6
+#define IEEE_ADDR_07 7
+
+#define IEEE_ADDR_1 _SFR_MEM8(0x165)
+#define IEEE_ADDR_10 0
+#define IEEE_ADDR_11 1
+#define IEEE_ADDR_12 2
+#define IEEE_ADDR_13 3
+#define IEEE_ADDR_14 4
+#define IEEE_ADDR_15 5
+#define IEEE_ADDR_16 6
+#define IEEE_ADDR_17 7
+
+#define IEEE_ADDR_2 _SFR_MEM8(0x166)
+#define IEEE_ADDR_20 0
+#define IEEE_ADDR_21 1
+#define IEEE_ADDR_22 2
+#define IEEE_ADDR_23 3
+#define IEEE_ADDR_24 4
+#define IEEE_ADDR_25 5
+#define IEEE_ADDR_26 6
+#define IEEE_ADDR_27 7
+
+#define IEEE_ADDR_3 _SFR_MEM8(0x167)
+#define IEEE_ADDR_30 0
+#define IEEE_ADDR_31 1
+#define IEEE_ADDR_32 2
+#define IEEE_ADDR_33 3
+#define IEEE_ADDR_34 4
+#define IEEE_ADDR_35 5
+#define IEEE_ADDR_36 6
+#define IEEE_ADDR_37 7
+
+#define IEEE_ADDR_4 _SFR_MEM8(0x168)
+#define IEEE_ADDR_40 0
+#define IEEE_ADDR_41 1
+#define IEEE_ADDR_42 2
+#define IEEE_ADDR_43 3
+#define IEEE_ADDR_44 4
+#define IEEE_ADDR_45 5
+#define IEEE_ADDR_46 6
+#define IEEE_ADDR_47 7
+
+#define IEEE_ADDR_5 _SFR_MEM8(0x169)
+#define IEEE_ADDR_50 0
+#define IEEE_ADDR_51 1
+#define IEEE_ADDR_52 2
+#define IEEE_ADDR_53 3
+#define IEEE_ADDR_54 4
+#define IEEE_ADDR_55 5
+#define IEEE_ADDR_56 6
+#define IEEE_ADDR_57 7
+
+#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
+#define IEEE_ADDR_60 0
+#define IEEE_ADDR_61 1
+#define IEEE_ADDR_62 2
+#define IEEE_ADDR_63 3
+#define IEEE_ADDR_64 4
+#define IEEE_ADDR_65 5
+#define IEEE_ADDR_66 6
+#define IEEE_ADDR_67 7
+
+#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
+#define IEEE_ADDR_70 0
+#define IEEE_ADDR_71 1
+#define IEEE_ADDR_72 2
+#define IEEE_ADDR_73 3
+#define IEEE_ADDR_74 4
+#define IEEE_ADDR_75 5
+#define IEEE_ADDR_76 6
+#define IEEE_ADDR_77 7
+
+#define XAH_CTRL_0 _SFR_MEM8(0x16C)
+#define SLOTTED_OPERATION 0
+#define MAX_CSMA_RETRIES0 1
+#define MAX_CSMA_RETRIES1 2
+#define MAX_CSMA_RETRIES2 3
+#define MAX_FRAME_RETRIES0 4
+#define MAX_FRAME_RETRIES1 5
+#define MAX_FRAME_RETRIES2 6
+#define MAX_FRAME_RETRIES3 7
+
+#define CSMA_SEED_0 _SFR_MEM8(0x16D)
+#define CSMA_SEED_00 0
+#define CSMA_SEED_01 1
+#define CSMA_SEED_02 2
+#define CSMA_SEED_03 3
+#define CSMA_SEED_04 4
+#define CSMA_SEED_05 5
+#define CSMA_SEED_06 6
+#define CSMA_SEED_07 7
+
+#define CSMA_SEED_1 _SFR_MEM8(0x16E)
+#define CSMA_SEED_10 0
+#define CSMA_SEED_11 1
+#define CSMA_SEED_12 2
+#define AACK_I_AM_COORD 3
+#define AACK_DIS_ACK 4
+#define AACK_SET_PD 5
+#define AACK_FVN_MODE0 6
+#define AACK_FVN_MODE1 7
+
+#define CSMA_BE _SFR_MEM8(0x16F)
+#define MIN_BE0 0
+#define MIN_BE1 1
+#define MIN_BE2 2
+#define MIN_BE3 3
+#define MAX_BE0 4
+#define MAX_BE1 5
+#define MAX_BE2 6
+#define MAX_BE3 7
+
+/* Reserved [0x170..0x175] */
+
+#define TST_CTRL_DIGI _SFR_MEM8(0x176)
+#define TST_CTRL_DIG0 0
+#define TST_CTRL_DIG1 1
+#define TST_CTRL_DIG2 2
+#define TST_CTRL_DIG3 3
+
+/* Reserved [0x177..0x17A] */
+
+#define TST_RX_LENGTH _SFR_MEM8(0x17B)
+#define RX_LENGTH0 0
+#define RX_LENGTH1 1
+#define RX_LENGTH2 2
+#define RX_LENGTH3 3
+#define RX_LENGTH4 4
+#define RX_LENGTH5 5
+#define RX_LENGTH6 6
+#define RX_LENGTH7 7
+
+/* Reserved [0x17C..0x17F] */
+
+#define TRXFBST _SFR_MEM8(0x180)
 
-/* Start of frame buffer */
-#define TRXFBST                         _SFR_MEM8(0x180)
+/* Reserved [0x181..0x1FE] */
 
-  /* TRXFBST */
+#define TRXFBEND _SFR_MEM8(0x1FF)
 
-#define TRXFBST0                        0
-#define TRXFBST1                        1
-#define TRXFBST2                        2
-#define TRXFBST3                        3
-#define TRXFBST4                        4
-#define TRXFBST5                        5
-#define TRXFBST6                        6
-#define TRXFBST7                        7
 
-/* End of frame buffer */
-#define TRXFBEND                        _SFR_MEM8(0x1FF)
 
-  /* TRXFBEND */
+/* Values and associated defines */
 
-#define TRXFBEND0                       0
-#define TRXFBEND1                       1
-#define TRXFBEND2                       2
-#define TRXFBEND3                       3
-#define TRXFBEND4                       4
-#define TRXFBEND5                       5
-#define TRXFBEND6                       6
-#define TRXFBEND7                       7
 
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
-
-#define _VECTORS_SIZE                  308
-
 /* External Interrupt Request 0 */
-#define INT0_vect                       _VECTOR(1)
-#define INT0_vect_num                   1
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
 
 /* External Interrupt Request 1 */
-#define INT1_vect                       _VECTOR(2)
-#define INT1_vect_num                   2
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
 
 /* External Interrupt Request 2 */
-#define INT2_vect                       _VECTOR(3)
-#define INT2_vect_num                   3
+#define INT2_vect            _VECTOR(3)
+#define INT2_vect_num        3
 
 /* External Interrupt Request 3 */
-#define INT3_vect                       _VECTOR(4)
-#define INT3_vect_num                   4
+#define INT3_vect            _VECTOR(4)
+#define INT3_vect_num        4
 
 /* External Interrupt Request 4 */
-#define INT4_vect                       _VECTOR(5)
-#define INT4_vect_num                   5
+#define INT4_vect            _VECTOR(5)
+#define INT4_vect_num        5
 
 /* External Interrupt Request 5 */
-#define INT5_vect                       _VECTOR(6)
-#define INT5_vect_num                   6
+#define INT5_vect            _VECTOR(6)
+#define INT5_vect_num        6
 
 /* External Interrupt Request 6 */
-#define INT6_vect                       _VECTOR(7)
-#define INT6_vect_num                   7
+#define INT6_vect            _VECTOR(7)
+#define INT6_vect_num        7
 
 /* External Interrupt Request 7 */
-#define INT7_vect                       _VECTOR(8)
-#define INT7_vect_num                   8
+#define INT7_vect            _VECTOR(8)
+#define INT7_vect_num        8
 
 /* Pin Change Interrupt Request 0 */
-#define PCINT0_vect                     _VECTOR(9)
-#define PCINT0_vect_num                 9
+#define PCINT0_vect            _VECTOR(9)
+#define PCINT0_vect_num        9
 
 /* Pin Change Interrupt Request 1 */
-#define PCINT1_vect                     _VECTOR(10)
-#define PCINT1_vect_num                 10
+#define PCINT1_vect            _VECTOR(10)
+#define PCINT1_vect_num        10
 
 /* Pin Change Interrupt Request 2 */
-#define PCINT2_vect                     _VECTOR(11)
-#define PCINT2_vect_num                 11
+#define PCINT2_vect            _VECTOR(11)
+#define PCINT2_vect_num        11
 
 /* Watchdog Time-out Interrupt */
-#define WDT_vect                        _VECTOR(12)
-#define WDT_vect_num                    12
+#define WDT_vect            _VECTOR(12)
+#define WDT_vect_num        12
 
 /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect               _VECTOR(13)
-#define TIMER2_COMPA_vect_num           13
+#define TIMER2_COMPA_vect            _VECTOR(13)
+#define TIMER2_COMPA_vect_num        13
 
 /* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect               _VECTOR(14)
-#define TIMER2_COMPB_vect_num           14
+#define TIMER2_COMPB_vect            _VECTOR(14)
+#define TIMER2_COMPB_vect_num        14
 
 /* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect                 _VECTOR(15)
-#define TIMER2_OVF_vect_num             15
+#define TIMER2_OVF_vect            _VECTOR(15)
+#define TIMER2_OVF_vect_num        15
 
 /* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect                _VECTOR(16)
-#define TIMER1_CAPT_vect_num            16
+#define TIMER1_CAPT_vect            _VECTOR(16)
+#define TIMER1_CAPT_vect_num        16
 
 /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect               _VECTOR(17)
-#define TIMER1_COMPA_vect_num           17
+#define TIMER1_COMPA_vect            _VECTOR(17)
+#define TIMER1_COMPA_vect_num        17
 
 /* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect               _VECTOR(18)
-#define TIMER1_COMPB_vect_num           18
+#define TIMER1_COMPB_vect            _VECTOR(18)
+#define TIMER1_COMPB_vect_num        18
 
 /* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect               _VECTOR(19)
-#define TIMER1_COMPC_vect_num           19
+#define TIMER1_COMPC_vect            _VECTOR(19)
+#define TIMER1_COMPC_vect_num        19
 
 /* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect                 _VECTOR(20)
-#define TIMER1_OVF_vect_num             20
+#define TIMER1_OVF_vect            _VECTOR(20)
+#define TIMER1_OVF_vect_num        20
 
 /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect               _VECTOR(21)
-#define TIMER0_COMPA_vect_num           21
+#define TIMER0_COMPA_vect            _VECTOR(21)
+#define TIMER0_COMPA_vect_num        21
 
 /* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect               _VECTOR(22)
-#define TIMER0_COMPB_vect_num           22
+#define TIMER0_COMPB_vect            _VECTOR(22)
+#define TIMER0_COMPB_vect_num        22
 
 /* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect                 _VECTOR(23)
-#define TIMER0_OVF_vect_num             23
+#define TIMER0_OVF_vect            _VECTOR(23)
+#define TIMER0_OVF_vect_num        23
 
 /* SPI Serial Transfer Complete */
-#define SPI_STC_vect                    _VECTOR(24)
-#define SPI_STC_vect_num                24
+#define SPI_STC_vect            _VECTOR(24)
+#define SPI_STC_vect_num        24
 
 /* USART0, Rx Complete */
-#define USART0_RX_vect                  _VECTOR(25)
-#define USART0_RX_vect_num              25
+#define USART0_RX_vect            _VECTOR(25)
+#define USART0_RX_vect_num        25
 
 /* USART0 Data register Empty */
-#define USART0_UDRE_vect                _VECTOR(26)
-#define USART0_UDRE_vect_num            26
+#define USART0_UDRE_vect            _VECTOR(26)
+#define USART0_UDRE_vect_num        26
 
 /* USART0, Tx Complete */
-#define USART0_TX_vect                  _VECTOR(27)
-#define USART0_TX_vect_num              27
+#define USART0_TX_vect            _VECTOR(27)
+#define USART0_TX_vect_num        27
 
 /* Analog Comparator */
-#define ANALOG_COMP_vect                _VECTOR(28)
-#define ANALOG_COMP_vect_num            28
+#define ANALOG_COMP_vect            _VECTOR(28)
+#define ANALOG_COMP_vect_num        28
 
 /* ADC Conversion Complete */
-#define ADC_vect                        _VECTOR(29)
-#define ADC_vect_num                    29
+#define ADC_vect            _VECTOR(29)
+#define ADC_vect_num        29
 
 /* EEPROM Ready */
-#define EE_READY_vect                   _VECTOR(30)
-#define EE_READY_vect_num               30
+#define EE_READY_vect            _VECTOR(30)
+#define EE_READY_vect_num        30
 
 /* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect                _VECTOR(31)
-#define TIMER3_CAPT_vect_num            31
+#define TIMER3_CAPT_vect            _VECTOR(31)
+#define TIMER3_CAPT_vect_num        31
 
 /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect               _VECTOR(32)
-#define TIMER3_COMPA_vect_num           32
+#define TIMER3_COMPA_vect            _VECTOR(32)
+#define TIMER3_COMPA_vect_num        32
 
 /* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect               _VECTOR(33)
-#define TIMER3_COMPB_vect_num           33
+#define TIMER3_COMPB_vect            _VECTOR(33)
+#define TIMER3_COMPB_vect_num        33
 
 /* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect               _VECTOR(34)
-#define TIMER3_COMPC_vect_num           34
+#define TIMER3_COMPC_vect            _VECTOR(34)
+#define TIMER3_COMPC_vect_num        34
 
 /* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect                 _VECTOR(35)
-#define TIMER3_OVF_vect_num             35
+#define TIMER3_OVF_vect            _VECTOR(35)
+#define TIMER3_OVF_vect_num        35
 
 /* USART1, Rx Complete */
-#define USART1_RX_vect                  _VECTOR(36)
-#define USART1_RX_vect_num              36
+#define USART1_RX_vect            _VECTOR(36)
+#define USART1_RX_vect_num        36
 
 /* USART1 Data register Empty */
-#define USART1_UDRE_vect                _VECTOR(37)
-#define USART1_UDRE_vect_num            37
+#define USART1_UDRE_vect            _VECTOR(37)
+#define USART1_UDRE_vect_num        37
 
 /* USART1, Tx Complete */
-#define USART1_TX_vect                  _VECTOR(38)
-#define USART1_TX_vect_num              38
+#define USART1_TX_vect            _VECTOR(38)
+#define USART1_TX_vect_num        38
 
 /* 2-wire Serial Interface */
-#define TWI_vect                        _VECTOR(39)
-#define TWI_vect_num                    39
+#define TWI_vect            _VECTOR(39)
+#define TWI_vect_num        39
 
 /* Store Program Memory Read */
-#define SPM_READY_vect                  _VECTOR(40)
-#define SPM_READY_vect_num              40
+#define SPM_READY_vect            _VECTOR(40)
+#define SPM_READY_vect_num        40
 
 /* Timer/Counter4 Capture Event */
-#define TIMER4_CAPT_vect                _VECTOR(41)
-#define TIMER4_CAPT_vect_num            41
+#define TIMER4_CAPT_vect            _VECTOR(41)
+#define TIMER4_CAPT_vect_num        41
 
 /* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPA_vect               _VECTOR(42)
-#define TIMER4_COMPA_vect_num           42
+#define TIMER4_COMPA_vect            _VECTOR(42)
+#define TIMER4_COMPA_vect_num        42
 
 /* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPB_vect               _VECTOR(43)
-#define TIMER4_COMPB_vect_num           43
+#define TIMER4_COMPB_vect            _VECTOR(43)
+#define TIMER4_COMPB_vect_num        43
 
 /* Timer/Counter4 Compare Match C */
-#define TIMER4_COMPC_vect               _VECTOR(44)
-#define TIMER4_COMPC_vect_num           44
+#define TIMER4_COMPC_vect            _VECTOR(44)
+#define TIMER4_COMPC_vect_num        44
 
 /* Timer/Counter4 Overflow */
-#define TIMER4_OVF_vect                 _VECTOR(45)
-#define TIMER4_OVF_vect_num             45
+#define TIMER4_OVF_vect            _VECTOR(45)
+#define TIMER4_OVF_vect_num        45
 
 /* Timer/Counter5 Capture Event */
-#define TIMER5_CAPT_vect                _VECTOR(46)
-#define TIMER5_CAPT_vect_num            46
+#define TIMER5_CAPT_vect            _VECTOR(46)
+#define TIMER5_CAPT_vect_num        46
 
 /* Timer/Counter5 Compare Match A */
-#define TIMER5_COMPA_vect               _VECTOR(47)
-#define TIMER5_COMPA_vect_num           47
+#define TIMER5_COMPA_vect            _VECTOR(47)
+#define TIMER5_COMPA_vect_num        47
 
 /* Timer/Counter5 Compare Match B */
-#define TIMER5_COMPB_vect               _VECTOR(48)
-#define TIMER5_COMPB_vect_num           48
+#define TIMER5_COMPB_vect            _VECTOR(48)
+#define TIMER5_COMPB_vect_num        48
 
 /* Timer/Counter5 Compare Match C */
-#define TIMER5_COMPC_vect               _VECTOR(49)
-#define TIMER5_COMPC_vect_num           49
+#define TIMER5_COMPC_vect            _VECTOR(49)
+#define TIMER5_COMPC_vect_num        49
 
 /* Timer/Counter5 Overflow */
-#define TIMER5_OVF_vect                 _VECTOR(50)
-#define TIMER5_OVF_vect_num             50
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_51_vect                _VECTOR(51)
-#define RESERVED_51_vect_num            51
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_52_vect                _VECTOR(52)
-#define RESERVED_52_vect_num            52
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_53_vect                _VECTOR(53)
-#define RESERVED_53_vect_num            53
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_54_vect                _VECTOR(54)
-#define RESERVED_54_vect_num            54
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_55_vect                _VECTOR(55)
-#define RESERVED_55_vect_num            55
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_56_vect                _VECTOR(56)
-#define RESERVED_56_vect_num            56
+#define TIMER5_OVF_vect            _VECTOR(50)
+#define TIMER5_OVF_vect_num        50
 
 /* TRX24 - PLL lock interrupt */
-#define TRX24_PLL_LOCK_vect             _VECTOR(57)
-#define TRX24_PLL_LOCK_vect_num         57
+#define TRX24_PLL_LOCK_vect            _VECTOR(57)
+#define TRX24_PLL_LOCK_vect_num        57
 
 /* TRX24 - PLL unlock interrupt */
-#define TRX24_PLL_UNLOCK_vect           _VECTOR(58)
-#define TRX24_PLL_UNLOCK_vect_num       58
+#define TRX24_PLL_UNLOCK_vect            _VECTOR(58)
+#define TRX24_PLL_UNLOCK_vect_num        58
 
 /* TRX24 - Receive start interrupt */
-#define TRX24_RX_START_vect             _VECTOR(59)
-#define TRX24_RX_START_vect_num         59
+#define TRX24_RX_START_vect            _VECTOR(59)
+#define TRX24_RX_START_vect_num        59
 
 /* TRX24 - RX_END interrupt */
-#define TRX24_RX_END_vect               _VECTOR(60)
-#define TRX24_RX_END_vect_num           60
+#define TRX24_RX_END_vect            _VECTOR(60)
+#define TRX24_RX_END_vect_num        60
 
 /* TRX24 - CCA/ED done interrupt */
-#define TRX24_CCA_ED_DONE_vect          _VECTOR(61)
-#define TRX24_CCA_ED_DONE_vect_num      61
+#define TRX24_CCA_ED_DONE_vect            _VECTOR(61)
+#define TRX24_CCA_ED_DONE_vect_num        61
 
 /* TRX24 - XAH - AMI */
-#define TRX24_XAH_AMI_vect              _VECTOR(62)
-#define TRX24_XAH_AMI_vect_num          62
+#define TRX24_XAH_AMI_vect            _VECTOR(62)
+#define TRX24_XAH_AMI_vect_num        62
 
 /* TRX24 - TX_END interrupt */
-#define TRX24_TX_END_vect               _VECTOR(63)
-#define TRX24_TX_END_vect_num           63
+#define TRX24_TX_END_vect            _VECTOR(63)
+#define TRX24_TX_END_vect_num        63
 
 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
-#define TRX24_AWAKE_vect                _VECTOR(64)
-#define TRX24_AWAKE_vect_num            64
+#define TRX24_AWAKE_vect            _VECTOR(64)
+#define TRX24_AWAKE_vect_num        64
 
 /* Symbol counter - compare match 1 interrupt */
-#define SCNT_CMP1_vect                  _VECTOR(65)
-#define SCNT_CMP1_vect_num              65
+#define SCNT_CMP1_vect            _VECTOR(65)
+#define SCNT_CMP1_vect_num        65
 
 /* Symbol counter - compare match 2 interrupt */
-#define SCNT_CMP2_vect                  _VECTOR(66)
-#define SCNT_CMP2_vect_num              66
+#define SCNT_CMP2_vect            _VECTOR(66)
+#define SCNT_CMP2_vect_num        66
 
 /* Symbol counter - compare match 3 interrupt */
-#define SCNT_CMP3_vect                  _VECTOR(67)
-#define SCNT_CMP3_vect_num              67
+#define SCNT_CMP3_vect            _VECTOR(67)
+#define SCNT_CMP3_vect_num        67
 
 /* Symbol counter - overflow interrupt */
-#define SCNT_OVFL_vect                  _VECTOR(68)
-#define SCNT_OVFL_vect_num              68
+#define SCNT_OVFL_vect            _VECTOR(68)
+#define SCNT_OVFL_vect_num        68
 
 /* Symbol counter - backoff interrupt */
-#define SCNT_BACKOFF_vect               _VECTOR(69)
-#define SCNT_BACKOFF_vect_num           69
+#define SCNT_BACKOFF_vect            _VECTOR(69)
+#define SCNT_BACKOFF_vect_num        69
 
 /* AES engine ready interrupt */
-#define AES_READY_vect                  _VECTOR(70)
-#define AES_READY_vect_num              70
+#define AES_READY_vect            _VECTOR(70)
+#define AES_READY_vect_num        70
 
 /* Battery monitor indicates supply voltage below threshold */
-#define BAT_LOW_vect                    _VECTOR(71)
-#define BAT_LOW_vect_num                71
+#define BAT_LOW_vect            _VECTOR(71)
+#define BAT_LOW_vect_num        71
 
 /* TRX24 TX start interrupt */
-#define TRX24_TX_START_vect             _VECTOR(72)
-#define TRX24_TX_START_vect_num         72
+#define TRX24_TX_START_vect            _VECTOR(72)
+#define TRX24_TX_START_vect_num        72
 
 /* Address match interrupt of address filter 0 */
-#define TRX24_AMI0_vect                 _VECTOR(73)
-#define TRX24_AMI0_vect_num             73
+#define TRX24_AMI0_vect            _VECTOR(73)
+#define TRX24_AMI0_vect_num        73
 
 /* Address match interrupt of address filter 1 */
-#define TRX24_AMI1_vect                 _VECTOR(74)
-#define TRX24_AMI1_vect_num             74
+#define TRX24_AMI1_vect            _VECTOR(74)
+#define TRX24_AMI1_vect_num        74
 
 /* Address match interrupt of address filter 2 */
-#define TRX24_AMI2_vect                 _VECTOR(75)
-#define TRX24_AMI2_vect_num             75
+#define TRX24_AMI2_vect            _VECTOR(75)
+#define TRX24_AMI2_vect_num        75
 
 /* Address match interrupt of address filter 3 */
-#define TRX24_AMI3_vect                 _VECTOR(76)
-#define TRX24_AMI3_vect_num             76
+#define TRX24_AMI3_vect            _VECTOR(76)
+#define TRX24_AMI3_vect_num        76
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 308
+#else
+#  define _VECTORS_SIZE 308U
+#endif
 
 
-/* memory parameters */
+/* Constants */
 
-#define SPM_PAGESIZE                    (256)
-#define RAMSTART                        (0x200)
-#define RAMSIZE                         (0x4000)
-#define RAMEND                          (0x41FF)
-#define XRAMSTART                       (0x0000)
-#define XRAMSIZE                        (0x0000)
-#define XRAMEND                         RAMEND
-#define E2END                           (0xFFF)
-#define E2PAGESIZE                      (0x08)
-#define FLASHEND                        (0x1ffff)
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 256
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFFF
+#else
+#  define SPM_PAGESIZE 256U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      16384
+#  define RAMEND       0x41FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      16384U
+#  define RAMEND       0x41FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      4096
+#  define E2PAGESIZE  8
+#  define E2END       0x0FFF
+#else
+#  define E2START     0U
+#  define E2SIZE      4096U
+#  define E2PAGESIZE  8U
+#  define E2END       0x0FFFU
+#endif
+#define XRAMEND      RAMEND
 
 
 /* Fuses */
 
 #define FUSE_MEMORY_SIZE 3
 
-/* LFUSE Byte */
-#define FUSE_CKSEL0     ~_BV(0) /* Select Clock Source */
-#define FUSE_CKSEL1     ~_BV(1) /* Select Clock Source */
-#define FUSE_CKSEL2     ~_BV(2) /* Select Clock Source */
-#define FUSE_CKSEL3     ~_BV(3) /* Select Clock Source */
-#define FUSE_SUT0       ~_BV(4) /* Select start-up time */
-#define FUSE_SUT1       ~_BV(5) /* Select start-up time */
-#define FUSE_CKOUT      ~_BV(6) /* Clock output */
-#define FUSE_CKDIV8     ~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* HFUSE Byte */
-#define FUSE_BOOTRST    ~_BV(0) /* Select Reset Vector */
-#define FUSE_BOOTSZ0    ~_BV(1) /* Select Boot Size */
-#define FUSE_BOOTSZ1    ~_BV(2) /* Select Boot Size */
-#define FUSE_EESAVE     ~_BV(3) /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      ~_BV(4) /* Watchdog timer always on */
-#define FUSE_SPIEN      ~_BV(5) /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN     ~_BV(6) /* Enable JTAG */
-#define FUSE_OCDEN      ~_BV(7) /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* EFUSE Byte */
-#define FUSE_BODLEVEL0  ~_BV(0) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  ~_BV(1) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  ~_BV(2) /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
+/* Low Fuse Byte */
+#define FUSE_CKSEL_SUT0  (unsigned char)~_BV(0)
+#define FUSE_CKSEL_SUT1  (unsigned char)~_BV(1)
+#define FUSE_CKSEL_SUT2  (unsigned char)~_BV(2)
+#define FUSE_CKSEL_SUT3  (unsigned char)~_BV(3)
+#define FUSE_CKSEL_SUT4  (unsigned char)~_BV(4)
+#define FUSE_CKSEL_SUT5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_CKSEL_SUT0 & FUSE_CKSEL_SUT2 & FUSE_CKSEL_SUT3 & FUSE_CKSEL_SUT4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BODLEVEL0)
 
 
 
 /* Lock Bits */
-
+#define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST
-#define __LOCK_BITS_EXIST
 
 
 /* Signature */
-
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0xA7
 #define SIGNATURE_2 0x03
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 
-#endif /* _AVR_IOM1284RFR2_H_ */
+
+#endif /* #ifdef _AVR_ATMEGA1284RFR2_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom128a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom128a.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA128A_H_INCLUDED
 #define _AVR_ATMEGA128A_H_INCLUDED
 
@@ -72,13 +55,29 @@
 
 #define DDRE    _SFR_IO8(0x02)
 #define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
 #define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
 #define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
 #define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
 #define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
 #define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
 #define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
 #define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
 
 #define PORTE   _SFR_IO8(0x03)
 #define PORTE7  7
@@ -182,13 +181,29 @@
 
 #define DDRD    _SFR_IO8(0x11)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x12)
 #define PORTD7  7
@@ -212,13 +227,29 @@
 
 #define DDRC    _SFR_IO8(0x14)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x15)
 #define PORTC7  7
@@ -242,13 +273,29 @@
 
 #define DDRB    _SFR_IO8(0x17)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x18)
 #define PORTB7  7
@@ -272,13 +319,29 @@
 
 #define DDRA    _SFR_IO8(0x1A)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x1B)
 #define PORTA7  7
@@ -486,13 +549,29 @@
 
 #define DDRF    _SFR_MEM8(0x61)
 #define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
 #define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
 #define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
 #define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
 #define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
 #define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
 #define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
 #define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
 
 #define PORTF   _SFR_MEM8(0x62)
 #define PORTF7  7
@@ -513,10 +592,20 @@
 
 #define DDRG    _SFR_MEM8(0x64)
 #define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
 #define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
 #define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
 #define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
 #define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
 
 #define PORTG   _SFR_MEM8(0x65)
 #define PORTG4  4
@@ -749,6 +838,16 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<2)
+#define SLEEP_MODE_ADC (0x02<<2)
+#define SLEEP_MODE_PWR_DOWN (0x04<<2)
+#define SLEEP_MODE_PWR_SAVE (0x06<<2)
+#define SLEEP_MODE_STANDBY (0x05<<2)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<2)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -887,21 +986,44 @@
 #define SPM_READY_vect            _VECTOR(34)
 #define SPM_READY_vect_num        34
 
-#define _VECTORS_SIZE 140
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 140
+#else
+#  define _VECTORS_SIZE 140U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 256
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFFF
-#define RAMSTART     0x0100
-#define RAMSIZE      4096
-#define RAMEND       0x10FF
-#define E2START     0
-#define E2SIZE      4096
-#define E2PAGESIZE  8
-#define E2END       0x0FFF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 256
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFFF
+#else
+#  define SPM_PAGESIZE 256U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      4096
+#  define RAMEND       0x10FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      4096U
+#  define RAMEND       0x10FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      4096
+#  define E2PAGESIZE  8
+#  define E2END       0x0FFF
+#else
+#  define E2START     0U
+#  define E2SIZE      4096U
+#  define E2PAGESIZE  8U
+#  define E2END       0x0FFFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -918,6 +1040,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_BODEN       (unsigned char)~_BV(6)
 #define FUSE_BODLEVEL    (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -928,10 +1052,14 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_JTAGEN      (unsigned char)~_BV(6)
 #define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_WDTON       (unsigned char)~_BV(0)
 #define FUSE_M103C       (unsigned char)~_BV(1)
+#define EFUSE_DEFAULT    (FUSE_M103C)
+
 
 
 /* Lock Bits */
@@ -947,12 +1075,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<2)
-#define SLEEP_MODE_ADC (0x02<<2)
-#define SLEEP_MODE_PWR_DOWN (0x04<<2)
-#define SLEEP_MODE_PWR_SAVE (0x06<<2)
-#define SLEEP_MODE_STANDBY (0x05<<2)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<2)
 
 #endif /* #ifdef _AVR_ATMEGA128A_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom128rfa1.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom128rfa1.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom128rfa1.h 2009 2009-07-01 14:57:41Z joerg_wunsch $ */
 
 /* avr/iom128rfa1.h - definitions for ATmega128RFA1 */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom128rfr2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom128rfr2.h
@@ -1,41 +1,25 @@
-/* Copyright (c) 2013 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* $Id$ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
 
-/* avr/iom128rfr2.h - definitions for ATmega128RFR2 */
 
-#ifndef _AVR_IOM128RFR2_H_
-#define _AVR_IOM128RFR2_H_ 1
+#ifndef _AVR_ATMEGA128RFR2_H_INCLUDED
+#define _AVR_ATMEGA128RFR2_H_INCLUDED
 
-/* This file should only be included from <avr/io.h>, never directly. */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -47,1189 +31,580 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif
 
-#include <avr/sfr_defs.h>
+/* Registers and associated bit numbers */
 
-#ifndef __ASSEMBLER__
-#  define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr))
-#  define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type)
-#  define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type)
-#endif /* __ASSEMBLER__ */
-
-/*
- * USAGE:
- *
- * simple register assignment:
- * TIFR1 = 0x17
- * subregister assignment:
- * TIFR1_struct.ocf1a = 1
- * (subregister names are converted to small letters)
- */
-
-
-/* Port A Input Pins Address */
-#define PINA                            _SFR_IO8(0x00)
-
-  /* PINA */
-
-#define PINA0                           0
-#define PINA1                           1
-#define PINA2                           2
-#define PINA3                           3
-#define PINA4                           4
-#define PINA5                           5
-#define PINA6                           6
-#define PINA7                           7
-
-/* Port A Data Direction Register */
-#define DDRA                            _SFR_IO8(0x01)
-
-  /* DDRA */
-
-#define DDA0                            0
-#define DDA1                            1
-#define DDA2                            2
-#define DDA3                            3
-#define DDA4                            4
-#define DDA5                            5
-#define DDA6                            6
-#define DDA7                            7
-
-/* Port A Data Register */
-#define PORTA                           _SFR_IO8(0x02)
-
-  /* PORTA */
-
-#define PORTA0                          0
-#define PA0                             0
-#define PORTA1                          1
-#define PA1                             1
-#define PORTA2                          2
-#define PA2                             2
-#define PORTA3                          3
-#define PA3                             3
-#define PORTA4                          4
-#define PA4                             4
-#define PORTA5                          5
-#define PA5                             5
-#define PORTA6                          6
-#define PA6                             6
-#define PORTA7                          7
-#define PA7                             7
-
-/* Port B Input Pins Address */
-#define PINB                            _SFR_IO8(0x03)
-
-  /* PINB */
-
-#define PINB0                           0
-#define PINB1                           1
-#define PINB2                           2
-#define PINB3                           3
-#define PINB4                           4
-#define PINB5                           5
-#define PINB6                           6
-#define PINB7                           7
-
-/* Port B Data Direction Register */
-#define DDRB                            _SFR_IO8(0x04)
-
-  /* DDRB */
-
-#define DDB0                            0
-#define DDB1                            1
-#define DDB2                            2
-#define DDB3                            3
-#define DDB4                            4
-#define DDB5                            5
-#define DDB6                            6
-#define DDB7                            7
-
-/* Port B Data Register */
-#define PORTB                           _SFR_IO8(0x05)
-
-  /* PORTB */
-
-#define PORTB0                          0
-#define PB0                             0
-#define PORTB1                          1
-#define PB1                             1
-#define PORTB2                          2
-#define PB2                             2
-#define PORTB3                          3
-#define PB3                             3
-#define PORTB4                          4
-#define PB4                             4
-#define PORTB5                          5
-#define PB5                             5
-#define PORTB6                          6
-#define PB6                             6
-#define PORTB7                          7
-#define PB7                             7
-
-/* Port C Input Pins Address */
-#define PINC                            _SFR_IO8(0x06)
-
-  /* PINC */
-
-#define PINC0                           0
-#define PINC1                           1
-#define PINC2                           2
-#define PINC3                           3
-#define PINC4                           4
-#define PINC5                           5
-#define PINC6                           6
-#define PINC7                           7
-
-/* Port C Data Direction Register */
-#define DDRC                            _SFR_IO8(0x07)
-
-  /* DDRC */
-
-#define DDC0                            0
-#define DDC1                            1
-#define DDC2                            2
-#define DDC3                            3
-#define DDC4                            4
-#define DDC5                            5
-#define DDC6                            6
-#define DDC7                            7
-
-/* Port C Data Register */
-#define PORTC                           _SFR_IO8(0x08)
-
-  /* PORTC */
-
-#define PORTC0                          0
-#define PC0                             0
-#define PORTC1                          1
-#define PC1                             1
-#define PORTC2                          2
-#define PC2                             2
-#define PORTC3                          3
-#define PC3                             3
-#define PORTC4                          4
-#define PC4                             4
-#define PORTC5                          5
-#define PC5                             5
-#define PORTC6                          6
-#define PC6                             6
-#define PORTC7                          7
-#define PC7                             7
-
-/* Port D Input Pins Address */
-#define PIND                            _SFR_IO8(0x09)
-
-  /* PIND */
-
-#define PIND0                           0
-#define PIND1                           1
-#define PIND2                           2
-#define PIND3                           3
-#define PIND4                           4
-#define PIND5                           5
-#define PIND6                           6
-#define PIND7                           7
-
-/* Port D Data Direction Register */
-#define DDRD                            _SFR_IO8(0x0A)
-
-  /* DDRD */
-
-#define DDD0                            0
-#define DDD1                            1
-#define DDD2                            2
-#define DDD3                            3
-#define DDD4                            4
-#define DDD5                            5
-#define DDD6                            6
-#define DDD7                            7
-
-/* Port D Data Register */
-#define PORTD                           _SFR_IO8(0x0B)
-
-  /* PORTD */
-
-#define PORTD0                          0
-#define PD0                             0
-#define PORTD1                          1
-#define PD1                             1
-#define PORTD2                          2
-#define PD2                             2
-#define PORTD3                          3
-#define PD3                             3
-#define PORTD4                          4
-#define PD4                             4
-#define PORTD5                          5
-#define PD5                             5
-#define PORTD6                          6
-#define PD6                             6
-#define PORTD7                          7
-#define PD7                             7
-
-/* Port E Input Pins Address */
-#define PINE                            _SFR_IO8(0x0C)
-
-  /* PINE */
-
-#define PINE0                           0
-#define PINE1                           1
-#define PINE2                           2
-#define PINE3                           3
-#define PINE4                           4
-#define PINE5                           5
-#define PINE6                           6
-#define PINE7                           7
-
-/* Port E Data Direction Register */
-#define DDRE                            _SFR_IO8(0x0D)
-
-  /* DDRE */
-
-#define DDE0                            0
-#define DDE1                            1
-#define DDE2                            2
-#define DDE3                            3
-#define DDE4                            4
-#define DDE5                            5
-#define DDE6                            6
-#define DDE7                            7
-
-/* Port E Data Register */
-#define PORTE                           _SFR_IO8(0x0E)
-
-  /* PORTE */
-
-#define PORTE0                          0
-#define PE0                             0
-#define PORTE1                          1
-#define PE1                             1
-#define PORTE2                          2
-#define PE2                             2
-#define PORTE3                          3
-#define PE3                             3
-#define PORTE4                          4
-#define PE4                             4
-#define PORTE5                          5
-#define PE5                             5
-#define PORTE6                          6
-#define PE6                             6
-#define PORTE7                          7
-#define PE7                             7
-
-/* Port F Input Pins Address */
-#define PINF                            _SFR_IO8(0x0F)
-
-  /* PINF */
-
-#define PINF0                           0
-#define PINF1                           1
-#define PINF2                           2
-#define PINF3                           3
-#define PINF4                           4
-#define PINF5                           5
-#define PINF6                           6
-#define PINF7                           7
-
-/* Port F Data Direction Register */
-#define DDRF                            _SFR_IO8(0x10)
-
-  /* DDRF */
-
-#define DDF0                            0
-#define DDF1                            1
-#define DDF2                            2
-#define DDF3                            3
-#define DDF4                            4
-#define DDF5                            5
-#define DDF6                            6
-#define DDF7                            7
-
-/* Port F Data Register */
-#define PORTF                           _SFR_IO8(0x11)
-
-  /* PORTF */
-
-#define PORTF0                          0
-#define PF0                             0
-#define PORTF1                          1
-#define PF1                             1
-#define PORTF2                          2
-#define PF2                             2
-#define PORTF3                          3
-#define PF3                             3
-#define PORTF4                          4
-#define PF4                             4
-#define PORTF5                          5
-#define PF5                             5
-#define PORTF6                          6
-#define PF6                             6
-#define PORTF7                          7
-#define PF7                             7
-
-/* Port G Input Pins Address */
-#define PING                            _SFR_IO8(0x12)
-
-  /* PING */
-
-#define PING0                           0
-#define PING1                           1
-#define PING2                           2
-#define PING3                           3
-#define PING4                           4
-#define PING5                           5
-
-/* Port G Data Direction Register */
-#define DDRG                            _SFR_IO8(0x13)
-
-  /* DDRG */
-
-#define DDG0                            0
-#define DDG1                            1
-#define DDG2                            2
-#define DDG3                            3
-#define DDG4                            4
-#define DDG5                            5
-
-/* Port G Data Register */
-#define PORTG                           _SFR_IO8(0x14)
-
-  /* PORTG */
-
-#define PORTG0                          0
-#define PG0                             0
-#define PORTG1                          1
-#define PG1                             1
-#define PORTG2                          2
-#define PG2                             2
-#define PORTG3                          3
-#define PG3                             3
-#define PORTG4                          4
-#define PG4                             4
-#define PORTG5                          5
-#define PG5                             5
-
-/* Timer/Counter0 Interrupt Flag Register */
-#define TIFR0                           _SFR_IO8(0x15)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR0 {
-        unsigned int tov0 : 1;	/* Timer/Counter0 Overflow Flag */
-        unsigned int ocf0a : 1;	/* Timer/Counter0 Output Compare A Match Flag */
-        unsigned int ocf0b : 1;	/* Timer/Counter0 Output Compare B Match Flag */
-        unsigned int : 5;
-};
-
-#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR0 */
-
-#define TOV0                            0
-#define OCF0A                           1
-#define OCF0B                           2
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1                           _SFR_IO8(0x16)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR1 {
-        unsigned int tov1 : 1;	/* Timer/Counter1 Overflow Flag */
-        unsigned int ocf1a : 1;	/* Timer/Counter1 Output Compare A Match Flag */
-        unsigned int ocf1b : 1;	/* Timer/Counter1 Output Compare B Match Flag */
-        unsigned int ocf1c : 1;	/* Timer/Counter1 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf1 : 1;	/* Timer/Counter1 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR1 */
-
-#define TOV1                            0
-#define OCF1A                           1
-#define OCF1B                           2
-#define OCF1C                           3
-#define ICF1                            5
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR2                           _SFR_IO8(0x17)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR2 {
-        unsigned int tov2 : 1;	/* Timer/Counter2 Overflow Flag */
-        unsigned int ocf2a : 1;	/* Output Compare Flag 2 A */
-        unsigned int ocf2b : 1;	/* Output Compare Flag 2 B */
-        unsigned int : 5;
-};
-
-#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR2 */
-
-#define TOV2                            0
-#define OCF2A                           1
-#define OCF2B                           2
-
-/* Timer/Counter3 Interrupt Flag Register */
-#define TIFR3                           _SFR_IO8(0x18)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR3 {
-        unsigned int tov3 : 1;	/* Timer/Counter3 Overflow Flag */
-        unsigned int ocf3a : 1;	/* Timer/Counter3 Output Compare A Match Flag */
-        unsigned int ocf3b : 1;	/* Timer/Counter3 Output Compare B Match Flag */
-        unsigned int ocf3c : 1;	/* Timer/Counter3 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf3 : 1;	/* Timer/Counter3 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR3 */
-
-#define TOV3                            0
-#define OCF3A                           1
-#define OCF3B                           2
-#define OCF3C                           3
-#define ICF3                            5
-
-/* Timer/Counter4 Interrupt Flag Register */
-#define TIFR4                           _SFR_IO8(0x19)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR4 {
-        unsigned int tov4 : 1;	/* Timer/Counter4 Overflow Flag */
-        unsigned int ocf4a : 1;	/* Timer/Counter4 Output Compare A Match Flag */
-        unsigned int ocf4b : 1;	/* Timer/Counter4 Output Compare B Match Flag */
-        unsigned int ocf4c : 1;	/* Timer/Counter4 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf4 : 1;	/* Timer/Counter4 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR4 */
-
-#define TOV4                            0
-#define OCF4A                           1
-#define OCF4B                           2
-#define OCF4C                           3
-#define ICF4                            5
-
-/* Timer/Counter5 Interrupt Flag Register */
-#define TIFR5                           _SFR_IO8(0x1A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR5 {
-        unsigned int tov5 : 1;	/* Timer/Counter5 Overflow Flag */
-        unsigned int ocf5a : 1;	/* Timer/Counter5 Output Compare A Match Flag */
-        unsigned int ocf5b : 1;	/* Timer/Counter5 Output Compare B Match Flag */
-        unsigned int ocf5c : 1;	/* Timer/Counter5 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf5 : 1;	/* Timer/Counter5 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR5 */
-
-#define TOV5                            0
-#define OCF5A                           1
-#define OCF5B                           2
-#define OCF5C                           3
-#define ICF5                            5
-
-/* Pin Change Interrupt Flag Register */
-#define PCIFR                           _SFR_IO8(0x1B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCIFR {
-        unsigned int pcif : 3;	/* Pin Change Interrupt Flags */
-        unsigned int : 5;
-};
-
-#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCIFR */
-
-#define PCIF0                           0
-#define PCIF1                           1
-#define PCIF2                           2
-
-/* External Interrupt Flag Register */
-#define EIFR                            _SFR_IO8(0x1C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIFR {
-        unsigned int intf : 8;	/* External Interrupt Flag */
-};
-
-#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIFR */
-
-#define INTF0                           0
-#define INTF1                           1
-#define INTF2                           2
-#define INTF3                           3
-#define INTF4                           4
-#define INTF5                           5
-#define INTF6                           6
-#define INTF7                           7
-
-/* External Interrupt Mask Register */
-#define EIMSK                           _SFR_IO8(0x1D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIMSK {
-        unsigned int intm : 8;	/* External Interrupt Request Enable */
-};
-
-#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIMSK */
-
-#define INT0                            0
-#define INT1                            1
-#define INT2                            2
-#define INT3                            3
-#define INT4                            4
-#define INT5                            5
-#define INT6                            6
-#define INT7                            7
-
-/* General Purpose IO Register 0 */
-#define GPIOR0                          _SFR_IO8(0x1E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR0 {
-        unsigned int gpior00 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior01 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior02 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior03 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior04 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior05 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior06 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior07 : 1;	/* General Purpose I/O Register 0 Value */
-};
-
-#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR0 */
-
-#define GPIOR00                         0
-#define GPIOR01                         1
-#define GPIOR02                         2
-#define GPIOR03                         3
-#define GPIOR04                         4
-#define GPIOR05                         5
-#define GPIOR06                         6
-#define GPIOR07                         7
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* EEPROM Control Register */
-#define EECR                            _SFR_IO8(0x1F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EECR {
-        unsigned int eere : 1;	/* EEPROM Read Enable */
-        unsigned int eepe : 1;	/* EEPROM Programming Enable */
-        unsigned int eempe : 1;	/* EEPROM Master Write Enable */
-        unsigned int eerie : 1;	/* EEPROM Ready Interrupt Enable */
-        unsigned int eepm : 2;	/* EEPROM Programming Mode */
-        unsigned int : 2;
-};
-
-#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EECR */
-
-#define EERE                            0
-#define EEPE                            1
-#define EEMPE                           2
-#define EERIE                           3
-#define EEPM0                           4
-#define EEPM1                           5
-
-/* EEPROM Data Register */
-#define EEDR                            _SFR_IO8(0x20)
-
-  /* EEDR */
-
-#define EEDR0                           0
-#define EEDR1                           1
-#define EEDR2                           2
-#define EEDR3                           3
-#define EEDR4                           4
-#define EEDR5                           5
-#define EEDR6                           6
-#define EEDR7                           7
-
-/* EEPROM Address Register  Bytes */
-#define EEAR                            _SFR_IO16(0x21)
-#define EEARL                           _SFR_IO8(0x21)
-#define EEARH                           _SFR_IO8(0x22)
-
-/* General Timer/Counter Control Register */
-#define GTCCR                           _SFR_IO8(0x23)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GTCCR {
-        unsigned int psrsync : 1;	/* Prescaler Reset for Synchronous Timer/Counters */
-        unsigned int psrasy : 1;	/* Prescaler Reset Timer/Counter2 */
-        unsigned int : 5;
-        unsigned int tsm : 1;	/* Timer/Counter Synchronization Mode */
-};
-
-#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GTCCR */
-
-#define PSRSYNC                         0
-#define PSR10                           0
-#define PSRASY                          1
-#define PSR2                            1
-#define TSM                             7
-
-/* Timer/Counter0 Control Register A */
-#define TCCR0A                          _SFR_IO8(0x24)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0A {
-        unsigned int wgm0 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com0b : 2;	/* Compare Match Output B Mode */
-        unsigned int com0a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0A */
-
-#define WGM00                           0
-#define WGM01                           1
-#define COM0B0                          4
-#define COM0B1                          5
-#define COM0A0                          6
-#define COM0A1                          7
-
-/* Timer/Counter0 Control Register B */
-#define TCCR0B                          _SFR_IO8(0x25)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0B {
-        unsigned int cs0 : 3;	/* Clock Select */
-        unsigned int wgm02 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc0b : 1;	/* Force Output Compare B */
-        unsigned int foc0a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0B */
-
-#define CS00                            0
-#define CS01                            1
-#define CS02                            2
-#define WGM02                           3
-#define FOC0B                           6
-#define FOC0A                           7
-
-/* Timer/Counter0 Register */
-#define TCNT0                           _SFR_IO8(0x26)
-
-  /* TCNT0 */
-
-#define TCNT0_0                         0
-#define TCNT0_1                         1
-#define TCNT0_2                         2
-#define TCNT0_3                         3
-#define TCNT0_4                         4
-#define TCNT0_5                         5
-#define TCNT0_6                         6
-#define TCNT0_7                         7
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0A                           _SFR_IO8(0x27)
-
-  /* OCR0A */
-
-#define OCR0A_0                         0
-#define OCR0A_1                         1
-#define OCR0A_2                         2
-#define OCR0A_3                         3
-#define OCR0A_4                         4
-#define OCR0A_5                         5
-#define OCR0A_6                         6
-#define OCR0A_7                         7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B                           _SFR_IO8(0x28)
-
-  /* OCR0B */
-
-#define OCR0B_0                         0
-#define OCR0B_1                         1
-#define OCR0B_2                         2
-#define OCR0B_3                         3
-#define OCR0B_4                         4
-#define OCR0B_5                         5
-#define OCR0B_6                         6
-#define OCR0B_7                         7
-
-/* General Purpose IO Register 1 */
-#define GPIOR1                          _SFR_IO8(0x2A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR1 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 1 Value */
-};
-
-#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR1 */
-
-#define GPIOR10                         0
-#define GPIOR11                         1
-#define GPIOR12                         2
-#define GPIOR13                         3
-#define GPIOR14                         4
-#define GPIOR15                         5
-#define GPIOR16                         6
-#define GPIOR17                         7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2                          _SFR_IO8(0x2B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR2 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 2 Value */
-};
-
-#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR2 */
-
-#define GPIOR20                         0
-#define GPIOR21                         1
-#define GPIOR22                         2
-#define GPIOR23                         3
-#define GPIOR24                         4
-#define GPIOR25                         5
-#define GPIOR26                         6
-#define GPIOR27                         7
-
-/* SPI Control Register */
-#define SPCR                            _SFR_IO8(0x2C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPCR {
-        unsigned int spr : 2;	/* SPI Clock Rate Select 1 and 0 */
-        unsigned int cpha : 1;	/* Clock Phase */
-        unsigned int cpol : 1;	/* Clock polarity */
-        unsigned int mstr : 1;	/* Master/Slave Select */
-        unsigned int dord : 1;	/* Data Order */
-        unsigned int spe : 1;	/* SPI Enable */
-        unsigned int spie : 1;	/* SPI Interrupt Enable */
-};
-
-#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPCR */
-
-#define SPR0                            0
-#define SPR1                            1
-#define CPHA                            2
-#define CPOL                            3
-#define MSTR                            4
-#define DORD                            5
-#define SPE                             6
-#define SPIE                            7
-
-/* SPI Status Register */
-#define SPSR                            _SFR_IO8(0x2D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPSR {
-        unsigned int spi2x : 1;	/* Double SPI Speed Bit */
-        unsigned int : 5;
-        unsigned int wcol : 1;	/* Write Collision Flag */
-        unsigned int spif : 1;	/* SPI Interrupt Flag */
-};
-
-#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPSR */
-
-#define SPI2X                           0
-#define WCOL                            6
-#define SPIF                            7
-
-/* SPI Data Register */
-#define SPDR                            _SFR_IO8(0x2E)
-
-  /* SPDR */
-
-#define SPDR0                           0
-#define SPDR1                           1
-#define SPDR2                           2
-#define SPDR3                           3
-#define SPDR4                           4
-#define SPDR5                           5
-#define SPDR6                           6
-#define SPDR7                           7
-
-/* Analog Comparator Control And Status Register */
-#define ACSR                            _SFR_IO8(0x30)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ACSR {
-        unsigned int acis : 2;	/* Analog Comparator Interrupt Mode Select */
-        unsigned int acic : 1;	/* Analog Comparator Input Capture Enable */
-        unsigned int acie : 1;	/* Analog Comparator Interrupt Enable */
-        unsigned int aci : 1;	/* Analog Comparator Interrupt Flag */
-        unsigned int aco : 1;	/* Analog Compare Output */
-        unsigned int acbg : 1;	/* Analog Comparator Bandgap Select */
-        unsigned int acd : 1;	/* Analog Comparator Disable */
-};
-
-#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ACSR */
-
-#define ACIS0                           0
-#define ACIS1                           1
-#define ACIC                            2
-#define ACIE                            3
-#define ACI                             4
-#define ACO                             5
-#define ACBG                            6
-#define ACD                             7
-
-/* On-Chip Debug Register */
-#define OCDR                            _SFR_IO8(0x31)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OCDR {
-        unsigned int ocdr : 8;	/* On-Chip Debug Register Data */
-};
-
-#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OCDR */
-
-#define OCDR0                           0
-#define OCDR1                           1
-#define OCDR2                           2
-#define OCDR3                           3
-#define OCDR4                           4
-#define OCDR5                           5
-#define OCDR6                           6
-#define OCDR7                           7
-#define IDRD                            7
-
-/* Sleep Mode Control Register */
-#define SMCR                            _SFR_IO8(0x33)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SMCR {
-        unsigned int se : 1;	/* Sleep Enable */
-        unsigned int sm : 3;	/* Sleep Mode Select bits */
-        unsigned int : 4;
-};
-
-#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SMCR */
-
-#define SE                              0
-#define SM0                             1
-#define SM1                             2
-#define SM2                             3
-
-/* MCU Status Register */
-#define MCUSR                           _SFR_IO8(0x34)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUSR {
-        unsigned int porf : 1;	/* Power-on Reset Flag */
-        unsigned int extrf : 1;	/* External Reset Flag */
-        unsigned int borf : 1;	/* Brown-out Reset Flag */
-        unsigned int wdrf : 1;	/* Watchdog Reset Flag */
-        unsigned int jtrf : 1;	/* JTAG Reset Flag */
-        unsigned int : 3;
-};
-
-#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUSR */
-
-#define PORF                            0
-#define EXTRF                           1
-#define BORF                            2
-#define WDRF                            3
-#define JTRF                            4
-
-/* MCU Control Register */
-#define MCUCR                           _SFR_IO8(0x35)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUCR {
-        unsigned int ivce : 1;	/* Interrupt Vector Change Enable */
-        unsigned int ivsel : 1;	/* Interrupt Vector Select */
-        unsigned int : 2;
-        unsigned int pud : 1;	/* Pull-up Disable */
-        unsigned int : 2;
-        unsigned int jtd : 1;	/* JTAG Interface Disable */
-};
-
-#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUCR */
-
-#define IVCE                            0
-#define IVSEL                           1
-#define PUD                             4
-#define JTD                             7
-
-/* Store Program Memory Control Register */
-#define SPMCSR                          _SFR_IO8(0x37)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPMCSR {
-        unsigned int spmen : 1;	/* Store Program Memory Enable */
-        unsigned int pgers : 1;	/* Page Erase */
-        unsigned int pgwrt : 1;	/* Page Write */
-        unsigned int blbset : 1;	/* Boot Lock Bit Set */
-        unsigned int rwwsre : 1;	/* Read While Write Section Read Enable */
-        unsigned int sigrd : 1;	/* Signature Row Read */
-        unsigned int rwwsb : 1;	/* Read While Write Section Busy */
-        unsigned int spmie : 1;	/* SPM Interrupt Enable */
-};
-
-#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPMCSR */
-
-#define SPMEN                           0
-#define PGERS                           1
-#define PGWRT                           2
-#define BLBSET                          3
-#define RWWSRE                          4
-#define SIGRD                           5
-#define RWWSB                           6
-#define SPMIE                           7
-
-/* Extended Z-pointer Register for ELPM/SPM */
-#define RAMPZ                           _SFR_IO8(0x3B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RAMPZ {
-        unsigned int rampz0 : 1;	/* Extended Z-Pointer Value */
-        unsigned int : 7;
-};
-
-#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ)
-
-#endif /* __ASSEMBLER__ */
-
-  /* RAMPZ */
-
-#define RAMPZ0                          0
-
-/* Stack Pointer */
-#define SP                              _SFR_IO16(0x3D)
-#define SPL                             _SFR_IO8(0x3D)
-#define SPH                             _SFR_IO8(0x3E)
-
-/* Status Register */
-#define SREG                            _SFR_IO8(0x3F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SREG {
-        unsigned int c : 1;	/* Carry Flag */
-        unsigned int z : 1;	/* Zero Flag */
-        unsigned int n : 1;	/* Negative Flag */
-        unsigned int v : 1;	/* Two's Complement Overflow Flag */
-        unsigned int s : 1;	/* Sign Bit */
-        unsigned int h : 1;	/* Half Carry Flag */
-        unsigned int t : 1;	/* Bit Copy Storage */
-        unsigned int i : 1;	/* Global Interrupt Enable */
-};
-
-#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SREG */
-
-#define SREG_C                          0
-#define SREG_Z                          1
-#define SREG_N                          2
-#define SREG_V                          3
-#define SREG_S                          4
-#define SREG_H                          5
-#define SREG_T                          6
-#define SREG_I                          7
-
-/* Watchdog Timer Control Register */
-#define WDTCSR                          _SFR_MEM8(0x60)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_WDTCSR {
-        unsigned int wdp : 3;	/* Watchdog Timer Prescaler Bits */
-        unsigned int wde : 1;	/* Watch Dog Enable */
-        unsigned int wdce : 1;	/* Watchdog Change Enable */
-        unsigned int : 1;
-        unsigned int wdie : 1;	/* Watchdog Timeout Interrupt Enable */
-        unsigned int wdif : 1;	/* Watchdog Timeout Interrupt Flag */
-};
-
-#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* WDTCSR */
-
-#define WDP0                            0
-#define WDP1                            1
-#define WDP2                            2
-#define WDE                             3
-#define WDCE                            4
-#define WDP3                            5
-#define WDIE                            6
-#define WDIF                            7
-
-/* Clock Prescale Register */
-#define CLKPR                           _SFR_MEM8(0x61)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CLKPR {
-        unsigned int clkps : 4;	/* Clock Prescaler Select Bits */
-        unsigned int : 3;
-        unsigned int clkpce : 1;	/* Clock Prescaler Change Enable */
-};
-
-#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CLKPR */
-
-#define CLKPS0                          0
-#define CLKPS1                          1
-#define CLKPS2                          2
-#define CLKPS3                          3
-#define CLKPCE                          7
-
-/* Power Reduction Register 2 */
-#define PRR2                            _SFR_MEM8(0x63)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR2 {
-        unsigned int prram : 4;	/* Power Reduction SRAMs */
-        unsigned int : 4;
-};
-
-#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR2 */
-
-#define PRRAM0                          0
-#define PRRAM1                          1
-#define PRRAM2                          2
-#define PRRAM3                          3
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
+#define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
+#define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
+#define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
+#define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
+#define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
+#define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
+#define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE7  7
+#define PORTE6  6
+#define PORTE5  5
+#define PORTE4  4
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
+#define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
+#define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
+#define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
+#define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
+#define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
+#define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
+#define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PORTF7  7
+#define PORTF6  6
+#define PORTF5  5
+#define PORTF4  4
+#define PORTF3  3
+#define PORTF2  2
+#define PORTF1  1
+#define PORTF0  0
+
+#define PING    _SFR_IO8(0x12)
+#define PING7   7
+#define PING6   6
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDRG7   7
+// Inserted "DDG7" from "DDRG7" due to compatibility
+#define DDG7    7
+#define DDRG6   6
+// Inserted "DDG6" from "DDRG6" due to compatibility
+#define DDG6    6
+#define DDRG5   5
+// Inserted "DDG5" from "DDRG5" due to compatibility
+#define DDG5    5
+#define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
+#define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
+#define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
+#define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
+#define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PORTG7  7
+#define PORTG6  6
+#define PORTG5  5
+#define PORTG4  4
+#define PORTG3  3
+#define PORTG2  2
+#define PORTG1  1
+#define PORTG0  0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define OCF1C   3
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+#define Res0    3
+#define Res1    4
+#define Res2    5
+#define Res3    6
+#define Res4    7
+
+#define TIFR3   _SFR_IO8(0x18)
+#define TOV3    0
+#define OCF3A   1
+#define OCF3B   2
+#define OCF3C   3
+#define ICF3    5
+
+#define TIFR4   _SFR_IO8(0x19)
+#define TOV4    0
+#define OCF4A   1
+#define OCF4B   2
+#define OCF4C   3
+#define ICF4    5
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define TOV5    0
+#define OCF5A   1
+#define OCF5B   2
+#define OCF5C   3
+#define ICF5    5
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+#define INTF2   2
+#define INTF3   3
+#define INTF4   4
+#define INTF5   5
+#define INTF6   6
+#define INTF7   7
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+#define INT2    2
+#define INT3    3
+#define INT4    4
+#define INT5    5
+#define INT6    6
+#define INT7    7
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define PSRASY  1
+#define TSM     7
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define OCDR    _SFR_IO8(0x31)
+#define OCDR0   0
+#define OCDR1   1
+#define OCDR2   2
+#define OCDR3   3
+#define OCDR4   4
+#define OCDR5   5
+#define OCDR6   6
+#define OCDR7   7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0x3B)
+#define RAMPZ0  0
+
+/* Reserved [0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62] */
+
+#define PRR2    _SFR_MEM8(0x63)
+#define PRRAM0  0
+#define PRRAM1  1
+#define PRRAM2  2
+#define PRRAM3  3
 
 #define __AVR_HAVE_PRR2	((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3))
 #define __AVR_HAVE_PRR2_PRRAM0
@@ -1237,36 +612,15 @@
 #define __AVR_HAVE_PRR2_PRRAM2
 #define __AVR_HAVE_PRR2_PRRAM3
 
-/* Power Reduction Register0 */
-#define PRR0                            _SFR_MEM8(0x64)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR0 {
-        unsigned int pradc : 1;	/* Power Reduction ADC */
-        unsigned int prusart0 : 1;	/* Power Reduction USART */
-        unsigned int prspi : 1;	/* Power Reduction Serial Peripheral Interface */
-        unsigned int prtim1 : 1;	/* Power Reduction Timer/Counter1 */
-        unsigned int prpga : 1;	/* Power Reduction PGA */
-        unsigned int prtim0 : 1;	/* Power Reduction Timer/Counter0 */
-        unsigned int prtim2 : 1;	/* Power Reduction Timer/Counter2 */
-        unsigned int prtwi : 1;	/* Power Reduction TWI */
-};
-
-#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR0 */
-
-#define PRADC                           0
-#define PRUSART0                        1
-#define PRSPI                           2
-#define PRTIM1                          3
-#define PRPGA                           4
-#define PRTIM0                          5
-#define PRTIM2                          6
-#define PRTWI                           7
+#define PRR0    _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRPGA   4
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
 
 #define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
 #define __AVR_HAVE_PRR0_PRADC
@@ -1278,32 +632,13 @@
 #define __AVR_HAVE_PRR0_PRTIM2
 #define __AVR_HAVE_PRR0_PRTWI
 
-/* Power Reduction Register 1 */
-#define PRR1                            _SFR_MEM8(0x65)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR1 {
-        unsigned int prusart1 : 1;	/* Power Reduction USART1 */
-        unsigned int : 2;
-        unsigned int prtim3 : 1;	/* Power Reduction Timer/Counter3 */
-        unsigned int prtim4 : 1;	/* Power Reduction Timer/Counter4 */
-        unsigned int prtim5 : 1;	/* Power Reduction Timer/Counter5 */
-        unsigned int prtrx24 : 1;	/* Power Reduction Transceiver */
-        unsigned int : 1;
-};
-
-#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR1 */
-
-#define PRUSART1                        0
-#define PRTIM3                          3
-#define PRTIM4                          4
-#define PRTIM5                          5
-#define PRTRX24                         6
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSART1 0
+#define PRTIM3  3
+#define PRTIM4  4
+#define PRTIM5  5
+#define PRTRX24 6
+#define Res     7
 
 #define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24))
 #define __AVR_HAVE_PRR1_PRUSART1
@@ -1312,5056 +647,2070 @@
 #define __AVR_HAVE_PRR1_PRTIM5
 #define __AVR_HAVE_PRR1_PRTRX24
 
-/* Oscillator Calibration Value */
-#define OSCCAL                          _SFR_MEM8(0x66)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OSCCAL {
-        unsigned int cal : 8;	/* Oscillator Calibration Tuning Value */
-};
-
-#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OSCCAL */
-
-#define CAL0                            0
-#define CAL1                            1
-#define CAL2                            2
-#define CAL3                            3
-#define CAL4                            4
-#define CAL5                            5
-#define CAL6                            6
-#define CAL7                            7
-
-/* Reference Voltage Calibration Register */
-#define BGCR                            _SFR_MEM8(0x67)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BGCR {
-        unsigned int bgcal : 3;	/* Coarse Calibration Bits */
-        unsigned int bgcal_fine : 4;	/* Fine Calibration Bits */
-        unsigned int : 1;
-};
-
-#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* BGCR */
-
-#define BGCAL0                          0
-#define BGCAL1                          1
-#define BGCAL2                          2
-#define BGCAL_FINE0                     3
-#define BGCAL_FINE1                     4
-#define BGCAL_FINE2                     5
-#define BGCAL_FINE3                     6
-
-/* Pin Change Interrupt Control Register */
-#define PCICR                           _SFR_MEM8(0x68)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCICR {
-        unsigned int pcie : 3;	/* Pin Change Interrupt Enables */
-        unsigned int : 5;
-};
-
-#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCICR */
-
-#define PCIE0                           0
-#define PCIE1                           1
-#define PCIE2                           2
-
-/* External Interrupt Control Register A */
-#define EICRA                           _SFR_MEM8(0x69)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRA {
-        unsigned int isc0 : 2;	/* External Interrupt 0 Sense Control Bit */
-        unsigned int isc1 : 2;	/* External Interrupt 1 Sense Control Bit */
-        unsigned int isc2 : 2;	/* External Interrupt 2 Sense Control Bit */
-        unsigned int isc3 : 2;	/* External Interrupt 3 Sense Control Bit */
-};
-
-#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRA */
-
-#define ISC00                           0
-#define ISC01                           1
-#define ISC10                           2
-#define ISC11                           3
-#define ISC20                           4
-#define ISC21                           5
-#define ISC30                           6
-#define ISC31                           7
-
-/* External Interrupt Control Register B */
-#define EICRB                           _SFR_MEM8(0x6A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRB {
-        unsigned int isc4 : 2;	/* External Interrupt 4 Sense Control Bit */
-        unsigned int isc5 : 2;	/* External Interrupt 5 Sense Control Bit */
-        unsigned int isc6 : 2;	/* External Interrupt 6 Sense Control Bit */
-        unsigned int isc7 : 2;	/* External Interrupt 7 Sense Control Bit */
-};
-
-#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRB */
-
-#define ISC40                           0
-#define ISC41                           1
-#define ISC50                           2
-#define ISC51                           3
-#define ISC60                           4
-#define ISC61                           5
-#define ISC70                           6
-#define ISC71                           7
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0                          _SFR_MEM8(0x6B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK0 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK0_struct _SFR_MEM8_STRUCT(0x6b, struct __reg_PCMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK0 */
-
-#define PCINT0                          0
-#define PCINT1                          1
-#define PCINT2                          2
-#define PCINT3                          3
-#define PCINT4                          4
-#define PCINT5                          5
-#define PCINT6                          6
-#define PCINT7                          7
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1                          _SFR_MEM8(0x6C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK1 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK1 */
-
-#define PCINT8                          0
-#define PCINT9                          1
-#define PCINT10                         2
-#define PCINT11                         3
-#define PCINT12                         4
-#define PCINT13                         5
-#define PCINT14                         6
-#define PCINT15                         7
-
-/* Pin Change Mask Register 2 */
-#define PCMSK2                          _SFR_MEM8(0x6D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK2 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK2 */
-
-#define PCINT16                         0
-#define PCINT17                         1
-#define PCINT18                         2
-#define PCINT19                         3
-#define PCINT20                         4
-#define PCINT21                         5
-#define PCINT22                         6
-#define PCINT23                         7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0                          _SFR_MEM8(0x6E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK0 {
-        unsigned int toie0 : 1;	/* Timer/Counter0 Overflow Interrupt Enable */
-        unsigned int ocie0a : 1;	/* Timer/Counter0 Output Compare Match A Interrupt Enable */
-        unsigned int ocie0b : 1;	/* Timer/Counter0 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK0 */
-
-#define TOIE0                           0
-#define OCIE0A                          1
-#define OCIE0B                          2
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1                          _SFR_MEM8(0x6F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK1 {
-        unsigned int toie1 : 1;	/* Timer/Counter1 Overflow Interrupt Enable */
-        unsigned int ocie1a : 1;	/* Timer/Counter1 Output Compare A Match Interrupt Enable */
-        unsigned int ocie1b : 1;	/* Timer/Counter1 Output Compare B Match Interrupt Enable */
-        unsigned int ocie1c : 1;	/* Timer/Counter1 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie1 : 1;	/* Timer/Counter1 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK1 */
+#define OSCCAL  _SFR_MEM8(0x66)
+#define CAL0    0
+#define CAL1    1
+#define CAL2    2
+#define CAL3    3
+#define CAL4    4
+#define CAL5    5
+#define CAL6    6
+#define CAL7    7
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+#define BGCR    _SFR_MEM8(0x67)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL_FINE0 3
+#define BGCAL_FINE1 4
+#define BGCAL_FINE2 5
+#define BGCAL_FINE3 6
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+#define ISC20   4
+#define ISC21   5
+#define ISC30   6
+#define ISC31   7
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC40   0
+#define ISC41   1
+#define ISC50   2
+#define ISC51   3
+#define ISC60   4
+#define ISC61   5
+#define ISC70   6
+#define ISC71   7
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define OCIE1C  3
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define TOIE3   0
+#define OCIE3A  1
+#define OCIE3B  2
+#define OCIE3C  3
+#define ICIE3   5
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define TOIE4   0
+#define OCIE4A  1
+#define OCIE4B  2
+#define OCIE4C  3
+#define ICIE4   5
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define TOIE5   0
+#define OCIE5A  1
+#define OCIE5B  2
+#define OCIE5C  3
+#define ICIE5   5
+
+/* Reserved [0x74] */
+
+#define NEMCR   _SFR_MEM8(0x75)
+#define AEAM0   4
+#define AEAM1   5
+#define ENEAM   6
+
+/* Reserved [0x76] */
+
+#define ADCSRC  _SFR_MEM8(0x77)
+#define ADSUT0  0
+#define ADSUT1  1
+#define ADSUT2  2
+#define ADSUT3  3
+#define ADSUT4  4
+#define ADTHT0  6
+#define ADTHT1  7
 
-#define TOIE1                           0
-#define OCIE1A                          1
-#define OCIE1B                          2
-#define OCIE1C                          3
-#define ICIE1                           5
-
-/* Timer/Counter Interrupt Mask register */
-#define TIMSK2                          _SFR_MEM8(0x70)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK2 {
-        unsigned int toie2 : 1;	/* Timer/Counter2 Overflow Interrupt Enable */
-        unsigned int ocie2a : 1;	/* Timer/Counter2 Output Compare Match A Interrupt Enable */
-        unsigned int ocie2b : 1;	/* Timer/Counter2 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK2 */
-
-#define TOIE2                           0
-#define TOIE2A                          0
-#define OCIE2A                          1
-#define OCIE2B                          2
-
-/* Timer/Counter3 Interrupt Mask Register */
-#define TIMSK3                          _SFR_MEM8(0x71)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK3 {
-        unsigned int toie3 : 1;	/* Timer/Counter3 Overflow Interrupt Enable */
-        unsigned int ocie3a : 1;	/* Timer/Counter3 Output Compare A Match Interrupt Enable */
-        unsigned int ocie3b : 1;	/* Timer/Counter3 Output Compare B Match Interrupt Enable */
-        unsigned int ocie3c : 1;	/* Timer/Counter3 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie3 : 1;	/* Timer/Counter3 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK3 */
-
-#define TOIE3                           0
-#define OCIE3A                          1
-#define OCIE3B                          2
-#define OCIE3C                          3
-#define ICIE3                           5
-
-/* Timer/Counter4 Interrupt Mask Register */
-#define TIMSK4                          _SFR_MEM8(0x72)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK4 {
-        unsigned int toie4 : 1;	/* Timer/Counter4 Overflow Interrupt Enable */
-        unsigned int ocie4a : 1;	/* Timer/Counter4 Output Compare A Match Interrupt Enable */
-        unsigned int ocie4b : 1;	/* Timer/Counter4 Output Compare B Match Interrupt Enable */
-        unsigned int ocie4c : 1;	/* Timer/Counter4 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie4 : 1;	/* Timer/Counter4 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK4 */
-
-#define TOIE4                           0
-#define OCIE4A                          1
-#define OCIE4B                          2
-#define OCIE4C                          3
-#define ICIE4                           5
-
-/* Timer/Counter5 Interrupt Mask Register */
-#define TIMSK5                          _SFR_MEM8(0x73)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK5 {
-        unsigned int toie5 : 1;	/* Timer/Counter5 Overflow Interrupt Enable */
-        unsigned int ocie5a : 1;	/* Timer/Counter5 Output Compare A Match Interrupt Enable */
-        unsigned int ocie5b : 1;	/* Timer/Counter5 Output Compare B Match Interrupt Enable */
-        unsigned int ocie5c : 1;	/* Timer/Counter5 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie5 : 1;	/* Timer/Counter5 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK5 */
-
-#define TOIE5                           0
-#define OCIE5A                          1
-#define OCIE5B                          2
-#define OCIE5C                          3
-#define ICIE5                           5
-
-/* Flash Extended-Mode Control-Register */
-#define NEMCR                           _SFR_MEM8(0x75)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_NEMCR {
-        unsigned int : 4;
-        unsigned int aeam : 2;	/* Address for Extended Address Mode of Extra Rows */
-        unsigned int eneam : 1;	/* Enable Extended Address Mode for Extra Rows */
-        unsigned int : 1;
-};
-
-#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* NEMCR */
-
-#define AEAM0                           4
-#define AEAM1                           5
-#define ENEAM                           6
-
-/* The ADC Control and Status Register C */
-#define ADCSRC                          _SFR_MEM8(0x77)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRC {
-        unsigned int adsut : 5;	/* ADC Start-up Time */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int adtht : 2;	/* ADC Track-and-Hold Time */
-};
-
-#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRC */
-
-#define ADSUT0                          0
-#define ADSUT1                          1
-#define ADSUT2                          2
-#define ADSUT3                          3
-#define ADSUT4                          4
-#define ADTHT0                          6
-#define ADTHT1                          7
-
-/* ADC Data Register  Bytes */
+/* Combine ADCL and ADCH */
 #ifndef __ASSEMBLER__
-#define ADC                             _SFR_MEM16(0x78)
-#define ADCL                            _SFR_MEM8(0x78)
-#define ADCH                            _SFR_MEM8(0x79)
-#endif /* __ASSEMBLER__ */
-#define ADCW                            _SFR_MEM16(0x78)
-#define ADCWL                           _SFR_MEM8(0x78)
-#define ADCWH                           _SFR_MEM8(0x79)
-
-/* The ADC Control and Status Register A */
-#define ADCSRA                          _SFR_MEM8(0x7A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRA {
-        unsigned int adps : 3;	/* ADC  Prescaler Select Bits */
-        unsigned int adie : 1;	/* ADC Interrupt Enable */
-        unsigned int adif : 1;	/* ADC Interrupt Flag */
-        unsigned int adate : 1;	/* ADC Auto Trigger Enable */
-        unsigned int adsc : 1;	/* ADC Start Conversion */
-        unsigned int aden : 1;	/* ADC Enable */
-};
-
-#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRA */
-
-#define ADPS0                           0
-#define ADPS1                           1
-#define ADPS2                           2
-#define ADIE                            3
-#define ADIF                            4
-#define ADATE                           5
-#define ADSC                            6
-#define ADEN                            7
-
-/* ADC Control and Status Register B */
-#define ADCSRB                          _SFR_MEM8(0x7B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRB {
-        unsigned int adts : 3;	/* ADC Auto Trigger Source */
-        unsigned int mux5 : 1;	/* Analog Channel and Gain Selection Bits */
-        unsigned int acch : 1;	/* Analog Channel Change */
-        unsigned int refok : 1;	/* Reference Voltage OK */
-        unsigned int acme : 1;	/* Analog Comparator Multiplexer Enable */
-        unsigned int avddok : 1;	/* AVDD Supply Voltage OK */
-};
-
-#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRB */
-
-#define ADTS0                           0
-#define ADTS1                           1
-#define ADTS2                           2
-#define MUX5                            3
-#define ACCH                            4
-#define REFOK                           5
-#define ACME                            6
-#define AVDDOK                          7
-
-/* The ADC Multiplexer Selection Register */
-#define ADMUX                           _SFR_MEM8(0x7C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADMUX {
-        unsigned int mux : 5;	/* Analog Channel and Gain Selection Bits */
-        unsigned int adlar : 1;	/* ADC Left Adjust Result */
-        unsigned int refs : 2;	/* Reference Selection Bits */
-};
-
-#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADMUX */
-
-#define MUX0                            0
-#define MUX1                            1
-#define MUX2                            2
-#define MUX3                            3
-#define MUX4                            4
-#define ADLAR                           5
-#define REFS0                           6
-#define REFS1                           7
-
-/* Digital Input Disable Register 2 */
-#define DIDR2                           _SFR_MEM8(0x7D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR2 {
-        unsigned int adc8d : 1;	/* Reserved Bits */
-        unsigned int adc9d : 1;	/* Reserved Bits */
-        unsigned int adc10d : 1;	/* Reserved Bits */
-        unsigned int adc11d : 1;	/* Reserved Bits */
-        unsigned int adc12d : 1;	/* Reserved Bits */
-        unsigned int adc13d : 1;	/* Reserved Bits */
-        unsigned int adc14d : 1;	/* Reserved Bits */
-        unsigned int adc15d : 1;	/* Reserved Bits */
-};
-
-#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR2 */
-
-#define ADC8D                           0
-#define ADC9D                           1
-#define ADC10D                          2
-#define ADC11D                          3
-#define ADC12D                          4
-#define ADC13D                          5
-#define ADC14D                          6
-#define ADC15D                          7
-
-/* Digital Input Disable Register 0 */
-#define DIDR0                           _SFR_MEM8(0x7E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR0 {
-        unsigned int adc0d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc1d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc2d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc3d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc4d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc5d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc6d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc7d : 1;	/* Disable ADC7:0 Digital Input */
-};
-
-#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR0 */
-
-#define ADC0D                           0
-#define ADC1D                           1
-#define ADC2D                           2
-#define ADC3D                           3
-#define ADC4D                           4
-#define ADC5D                           5
-#define ADC6D                           6
-#define ADC7D                           7
-
-/* Digital Input Disable Register 1 */
-#define DIDR1                           _SFR_MEM8(0x7F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR1 {
-        unsigned int ain0d : 1;	/* AIN0 Digital Input Disable */
-        unsigned int ain1d : 1;	/* AIN1 Digital Input Disable */
-        unsigned int : 6;
-};
-
-#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR1 */
-
-#define AIN0D                           0
-#define AIN1D                           1
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A                          _SFR_MEM8(0x80)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1A {
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int com1c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com1b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com1a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1A */
-
-#define WGM10                           0
-#define WGM11                           1
-#define COM1C0                          2
-#define COM1C1                          3
-#define COM1B0                          4
-#define COM1B1                          5
-#define COM1A0                          6
-#define COM1A1                          7
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B                          _SFR_MEM8(0x81)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1B {
-        unsigned int cs1 : 3;	/* Clock Select */
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices1 : 1;	/* Input Capture 1 Edge Select */
-        unsigned int icnc1 : 1;	/* Input Capture 1 Noise Canceller */
-};
-
-#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1B */
-
-#define CS10                            0
-#define CS11                            1
-#define CS12                            2
-#define WGM12                           3
-#define WGM13                           4
-#define ICES1                           6
-#define ICNC1                           7
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C                          _SFR_MEM8(0x82)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1C {
-        unsigned int : 5;
-        unsigned int foc1c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc1b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc1a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1C */
-
-#define FOC1C                           5
-#define FOC1B                           6
-#define FOC1A                           7
-
-/* Timer/Counter1  Bytes */
-#define TCNT1                           _SFR_MEM16(0x84)
-#define TCNT1L                          _SFR_MEM8(0x84)
-#define TCNT1H                          _SFR_MEM8(0x85)
-
-/* Timer/Counter1 Input Capture Register  Bytes */
-#define ICR1                            _SFR_MEM16(0x86)
-#define ICR1L                           _SFR_MEM8(0x86)
-#define ICR1H                           _SFR_MEM8(0x87)
-
-/* Timer/Counter1 Output Compare Register A  Bytes */
-#define OCR1A                           _SFR_MEM16(0x88)
-#define OCR1AL                          _SFR_MEM8(0x88)
-#define OCR1AH                          _SFR_MEM8(0x89)
-
-/* Timer/Counter1 Output Compare Register B  Bytes */
-#define OCR1B                           _SFR_MEM16(0x8A)
-#define OCR1BL                          _SFR_MEM8(0x8A)
-#define OCR1BH                          _SFR_MEM8(0x8B)
-
-/* Timer/Counter1 Output Compare Register C  Bytes */
-#define OCR1C                           _SFR_MEM16(0x8C)
-#define OCR1CL                          _SFR_MEM8(0x8C)
-#define OCR1CH                          _SFR_MEM8(0x8D)
-
-/* Timer/Counter3 Control Register A */
-#define TCCR3A                          _SFR_MEM8(0x90)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3A {
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int com3c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com3b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com3a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3A */
-
-#define WGM30                           0
-#define WGM31                           1
-#define COM3C0                          2
-#define COM3C1                          3
-#define COM3B0                          4
-#define COM3B1                          5
-#define COM3A0                          6
-#define COM3A1                          7
-
-/* Timer/Counter3 Control Register B */
-#define TCCR3B                          _SFR_MEM8(0x91)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3B {
-        unsigned int cs3 : 3;	/* Clock Select */
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices3 : 1;	/* Input Capture 3 Edge Select */
-        unsigned int icnc3 : 1;	/* Input Capture 3 Noise Canceller */
-};
-
-#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3B */
-
-#define CS30                            0
-#define CS31                            1
-#define CS32                            2
-#define WGM32                           3
-#define WGM33                           4
-#define ICES3                           6
-#define ICNC3                           7
-
-/* Timer/Counter3 Control Register C */
-#define TCCR3C                          _SFR_MEM8(0x92)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3C {
-        unsigned int : 5;
-        unsigned int foc3c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc3b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc3a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3C */
-
-#define FOC3C                           5
-#define FOC3B                           6
-#define FOC3A                           7
-
-/* Timer/Counter3  Bytes */
-#define TCNT3                           _SFR_MEM16(0x94)
-#define TCNT3L                          _SFR_MEM8(0x94)
-#define TCNT3H                          _SFR_MEM8(0x95)
-
-/* Timer/Counter3 Input Capture Register  Bytes */
-#define ICR3                            _SFR_MEM16(0x96)
-#define ICR3L                           _SFR_MEM8(0x96)
-#define ICR3H                           _SFR_MEM8(0x97)
-
-/* Timer/Counter3 Output Compare Register A  Bytes */
-#define OCR3A                           _SFR_MEM16(0x98)
-#define OCR3AL                          _SFR_MEM8(0x98)
-#define OCR3AH                          _SFR_MEM8(0x99)
-
-/* Timer/Counter3 Output Compare Register B  Bytes */
-#define OCR3B                           _SFR_MEM16(0x9A)
-#define OCR3BL                          _SFR_MEM8(0x9A)
-#define OCR3BH                          _SFR_MEM8(0x9B)
-
-/* Timer/Counter3 Output Compare Register C  Bytes */
-#define OCR3C                           _SFR_MEM16(0x9C)
-#define OCR3CL                          _SFR_MEM8(0x9C)
-#define OCR3CH                          _SFR_MEM8(0x9D)
-
-/* Timer/Counter4 Control Register A */
-#define TCCR4A                          _SFR_MEM8(0xA0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4A {
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int com4c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com4b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com4a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4A */
-
-#define WGM40                           0
-#define WGM41                           1
-#define COM4C0                          2
-#define COM4C1                          3
-#define COM4B0                          4
-#define COM4B1                          5
-#define COM4A0                          6
-#define COM4A1                          7
-
-/* Timer/Counter4 Control Register B */
-#define TCCR4B                          _SFR_MEM8(0xA1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4B {
-        unsigned int cs4 : 3;	/* Clock Select */
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices4 : 1;	/* Input Capture 4 Edge Select */
-        unsigned int icnc4 : 1;	/* Input Capture 4 Noise Canceller */
-};
-
-#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4B */
-
-#define CS40                            0
-#define CS41                            1
-#define CS42                            2
-#define WGM42                           3
-#define WGM43                           4
-#define ICES4                           6
-#define ICNC4                           7
-
-/* Timer/Counter4 Control Register C */
-#define TCCR4C                          _SFR_MEM8(0xA2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4C {
-        unsigned int : 5;
-        unsigned int foc4c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc4b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc4a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4C */
-
-#define FOC4C                           5
-#define FOC4B                           6
-#define FOC4A                           7
-
-/* Timer/Counter4  Bytes */
-#define TCNT4                           _SFR_MEM16(0xA4)
-#define TCNT4L                          _SFR_MEM8(0xA4)
-#define TCNT4H                          _SFR_MEM8(0xA5)
-
-/* Timer/Counter4 Input Capture Register  Bytes */
-#define ICR4                            _SFR_MEM16(0xA6)
-#define ICR4L                           _SFR_MEM8(0xA6)
-#define ICR4H                           _SFR_MEM8(0xA7)
-
-/* Timer/Counter4 Output Compare Register A  Bytes */
-#define OCR4A                           _SFR_MEM16(0xA8)
-#define OCR4AL                          _SFR_MEM8(0xA8)
-#define OCR4AH                          _SFR_MEM8(0xA9)
-
-/* Timer/Counter4 Output Compare Register B  Bytes */
-#define OCR4B                           _SFR_MEM16(0xAA)
-#define OCR4BL                          _SFR_MEM8(0xAA)
-#define OCR4BH                          _SFR_MEM8(0xAB)
-
-/* Timer/Counter4 Output Compare Register C  Bytes */
-#define OCR4C                           _SFR_MEM16(0xAC)
-#define OCR4CL                          _SFR_MEM8(0xAC)
-#define OCR4CH                          _SFR_MEM8(0xAD)
-
-/* Timer/Counter2 Control Register A */
-#define TCCR2A                          _SFR_MEM8(0xB0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2A {
-        unsigned int wgm2 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com2b : 2;	/* Compare Match Output B Mode */
-        unsigned int com2a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2A */
-
-#define WGM20                           0
-#define WGM21                           1
-#define COM2B0                          4
-#define COM2B1                          5
-#define COM2A0                          6
-#define COM2A1                          7
-
-/* Timer/Counter2 Control Register B */
-#define TCCR2B                          _SFR_MEM8(0xB1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2B {
-        unsigned int cs2 : 3;	/* Clock Select */
-        unsigned int wgm22 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc2b : 1;	/* Force Output Compare B */
-        unsigned int foc2a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2B */
-
-#define CS20                            0
-#define CS21                            1
-#define CS22                            2
-#define WGM22                           3
-#define FOC2B                           6
-#define FOC2A                           7
-
-/* Timer/Counter2 */
-#define TCNT2                           _SFR_MEM8(0xB2)
-
-  /* TCNT2 */
-
-#define TCNT20                          0
-#define TCNT21                          1
-#define TCNT22                          2
-#define TCNT23                          3
-#define TCNT24                          4
-#define TCNT25                          5
-#define TCNT26                          6
-#define TCNT27                          7
-
-/* Timer/Counter2 Output Compare Register A */
-#define OCR2A                           _SFR_MEM8(0xB3)
-
-  /* OCR2A */
-
-#define OCR2A0                          0
-#define OCR2A1                          1
-#define OCR2A2                          2
-#define OCR2A3                          3
-#define OCR2A4                          4
-#define OCR2A5                          5
-#define OCR2A6                          6
-#define OCR2A7                          7
-
-/* Timer/Counter2 Output Compare Register B */
-#define OCR2B                           _SFR_MEM8(0xB4)
-
-  /* OCR2B */
-
-#define OCR2B0                          0
-#define OCR2B1                          1
-#define OCR2B2                          2
-#define OCR2B3                          3
-#define OCR2B4                          4
-#define OCR2B5                          5
-#define OCR2B6                          6
-#define OCR2B7                          7
-
-/* Asynchronous Status Register */
-#define ASSR                            _SFR_MEM8(0xB6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ASSR {
-        unsigned int tcr2bub : 1;	/* Timer/Counter2 Control Register B Update Busy */
-        unsigned int tcr2aub : 1;	/* Timer/Counter2 Control Register A Update Busy */
-        unsigned int ocr2bub : 1;	/* Timer/Counter2 Output Compare Register B Update Busy */
-        unsigned int ocr2aub : 1;	/* Timer/Counter2 Output Compare Register A Update Busy */
-        unsigned int tcn2ub : 1;	/* Timer/Counter2 Update Busy */
-        unsigned int as2 : 1;	/* Timer/Counter2 Asynchronous Mode */
-        unsigned int exclk : 1;	/* Enable External Clock Input */
-        unsigned int exclkamr : 1;	/* Enable External Clock Input for AMR */
-};
-
-#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ASSR */
-
-#define TCR2BUB                         0
-#define TCR2AUB                         1
-#define OCR2BUB                         2
-#define OCR2AUB                         3
-#define TCN2UB                          4
-#define AS2                             5
-#define EXCLK                           6
-#define EXCLKAMR                        7
-
-/* TWI Bit Rate Register */
-#define TWBR                            _SFR_MEM8(0xB8)
-
-  /* TWBR */
-
-#define TWBR0                           0
-#define TWBR1                           1
-#define TWBR2                           2
-#define TWBR3                           3
-#define TWBR4                           4
-#define TWBR5                           5
-#define TWBR6                           6
-#define TWBR7                           7
-
-/* TWI Status Register */
-#define TWSR                            _SFR_MEM8(0xB9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWSR {
-        unsigned int twps : 2;	/* TWI Prescaler Bits */
-        unsigned int : 1;
-        unsigned int tws : 5;	/* TWI Status */
-};
-
-#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWSR */
-
-#define TWPS0                           0
-#define TWPS1                           1
-#define TWS3                            3
-#define TWS4                            4
-#define TWS5                            5
-#define TWS6                            6
-#define TWS7                            7
-
-/* TWI (Slave) Address Register */
-#define TWAR                            _SFR_MEM8(0xBA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAR {
-        unsigned int twgce : 1;	/* TWI General Call Recognition Enable Bit */
-        unsigned int twa : 7;	/* TWI (Slave) Address */
-};
-
-#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAR */
-
-#define TWGCE                           0
-#define TWA0                            1
-#define TWA1                            2
-#define TWA2                            3
-#define TWA3                            4
-#define TWA4                            5
-#define TWA5                            6
-#define TWA6                            7
-
-/* TWI Data Register */
-#define TWDR                            _SFR_MEM8(0xBB)
-
-  /* TWDR */
-
-#define TWD0                            0
-#define TWD1                            1
-#define TWD2                            2
-#define TWD3                            3
-#define TWD4                            4
-#define TWD5                            5
-#define TWD6                            6
-#define TWD7                            7
-
-/* TWI Control Register */
-#define TWCR                            _SFR_MEM8(0xBC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWCR {
-        unsigned int twie : 1;	/* TWI Interrupt Enable */
-        unsigned int : 1;
-        unsigned int twen : 1;	/* TWI Enable Bit */
-        unsigned int twwc : 1;	/* TWI Write Collision Flag */
-        unsigned int twsto : 1;	/* TWI STOP Condition Bit */
-        unsigned int twsta : 1;	/* TWI START Condition Bit */
-        unsigned int twea : 1;	/* TWI Enable Acknowledge Bit */
-        unsigned int twint : 1;	/* TWI Interrupt Flag */
-};
-
-#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWCR */
-
-#define TWIE                            0
-#define TWEN                            2
-#define TWWC                            3
-#define TWSTO                           4
-#define TWSTA                           5
-#define TWEA                            6
-#define TWINT                           7
-
-/* TWI (Slave) Address Mask Register */
-#define TWAMR                           _SFR_MEM8(0xBD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAMR {
-        unsigned int : 1;
-        unsigned int twam : 7;	/* TWI Address Mask */
-};
-
-#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAMR */
-
-#define TWAM0                           1
-#define TWAMR0                          1
-#define TWAM1                           2
-#define TWAMR1                          2
-#define TWAM2                           3
-#define TWAMR2                          3
-#define TWAM3                           4
-#define TWAMR3                          4
-#define TWAM4                           5
-#define TWAMR4                          5
-#define TWAM5                           6
-#define TWAMR5                          6
-#define TWAM6                           7
-#define TWAMR6                          7
-
-/* Transceiver Interrupt Enable Register 1 */
-#define IRQ_MASK1                       _SFR_MEM8(0xBE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK1 {
-        unsigned int tx_start_en : 1;	/* Transmit Start Interrupt enable */
-        unsigned int maf_0_ami_en : 1;	/* Address Match Interrupt enable Address filter 0 */
-        unsigned int maf_1_ami_en : 1;	/* Address Match Interrupt enable Address filter 1 */
-        unsigned int maf_2_ami_en : 1;	/* Address Match Interrupt enable Address filter 2 */
-        unsigned int maf_3_ami_en : 1;	/* Address Match Interrupt enable Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_MASK1_struct _SFR_MEM8_STRUCT(0xbe, struct __reg_IRQ_MASK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK1 */
-
-#define TX_START_EN                     0
-#define MAF_0_AMI_EN                    1
-#define MAF_1_AMI_EN                    2
-#define MAF_2_AMI_EN                    3
-#define MAF_3_AMI_EN                    4
-
-/* Transceiver Interrupt Status Register 1 */
-#define IRQ_STATUS1                     _SFR_MEM8(0xBF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS1 {
-        unsigned int tx_start : 1;	/* Transmit Start Interrupt Status */
-        unsigned int maf_0_ami : 1;	/* Address Match Interrupt Status Address filter 0 */
-        unsigned int maf_1_ami : 1;	/* Address Match Interrupt Status Address filter 1 */
-        unsigned int maf_2_ami : 1;	/* Address Match Interrupt Status Address filter 2 */
-        unsigned int maf_3_ami : 1;	/* Address Match Interrupt Status Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_STATUS1_struct _SFR_MEM8_STRUCT(0xbf, struct __reg_IRQ_STATUS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS1 */
-
-#define TX_START                        0
-#define MAF_0_AMI                       1
-#define MAF_1_AMI                       2
-#define MAF_2_AMI                       3
-#define MAF_3_AMI                       4
-
-/* USART0 Control and Status Register A */
-#define UCSR0A                          _SFR_MEM8(0xC0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0A {
-        unsigned int mpcm0 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x0 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe0 : 1;	/* USART Parity Error */
-        unsigned int dor0 : 1;	/* Data OverRun */
-        unsigned int fe0 : 1;	/* Frame Error */
-        unsigned int udre0 : 1;	/* USART Data Register Empty */
-        unsigned int txc0 : 1;	/* USART Transmit Complete */
-        unsigned int rxc0 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0A */
-
-#define MPCM0                           0
-#define U2X0                            1
-#define UPE0                            2
-#define DOR0                            3
-#define FE0                             4
-#define UDRE0                           5
-#define TXC0                            6
-#define RXC0                            7
-
-/* USART0 Control and Status Register B */
-#define UCSR0B                          _SFR_MEM8(0xC1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0B {
-        unsigned int txb80 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb80 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz02 : 1;	/* Character Size */
-        unsigned int txen0 : 1;	/* Transmitter Enable */
-        unsigned int rxen0 : 1;	/* Receiver Enable */
-        unsigned int udrie0 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie0 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie0 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0B */
-
-#define TXB80                           0
-#define RXB80                           1
-#define UCSZ02                          2
-#define TXEN0                           3
-#define RXEN0                           4
-#define UDRIE0                          5
-#define TXCIE0                          6
-#define RXCIE0                          7
-
-/* USART0 Control and Status Register C */
-#define UCSR0C                          _SFR_MEM8(0xC2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0C {
-        unsigned int ucpol0 : 1;	/* Clock Polarity */
-        unsigned int ucsz0 : 2;	/* Character Size */
-        unsigned int ucpha0 : 1;	/* Clock Phase */
-        unsigned int udord0 : 1;	/* Data Order */
-        unsigned int usbs0 : 1;	/* Stop Bit Select */
-        unsigned int upm0 : 2;	/* Parity Mode */
-        unsigned int umsel0 : 2;	/* USART Mode Select */
-};
-
-#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0C */
-
-#define UCPOL0                          0
-#define UCPHA0                          1
-#define UCPHA0                          1
-#define UCSZ00                          1
-#define UDORD0                          2
-#define UDORD0                          2
-#define UCSZ01                          2
-#define USBS0                           3
-#define UPM00                           4
-#define UPM01                           5
-#define UMSEL00                         6
-#define UMSEL0                          6
-#define UMSEL01                         7
-#define UMSEL1                          7
-
-/* USART0 Baud Rate Register  Bytes */
-#define UBRR0                           _SFR_MEM16(0xC4)
-#define UBRR0L                          _SFR_MEM8(0xC4)
-#define UBRR0H                          _SFR_MEM8(0xC5)
-
-/* USART0 I/O Data Register */
-#define UDR0                            _SFR_MEM8(0xC6)
-
-  /* UDR0 */
-
-#define UDR00                           0
-#define UDR01                           1
-#define UDR02                           2
-#define UDR03                           3
-#define UDR04                           4
-#define UDR05                           5
-#define UDR06                           6
-#define UDR07                           7
-
-/* USART1 Control and Status Register A */
-#define UCSR1A                          _SFR_MEM8(0xC8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1A {
-        unsigned int mpcm1 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x1 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe1 : 1;	/* USART Parity Error */
-        unsigned int dor1 : 1;	/* Data OverRun */
-        unsigned int fe1 : 1;	/* Frame Error */
-        unsigned int udre1 : 1;	/* USART Data Register Empty */
-        unsigned int txc1 : 1;	/* USART Transmit Complete */
-        unsigned int rxc1 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1A */
-
-#define MPCM1                           0
-#define U2X1                            1
-#define UPE1                            2
-#define DOR1                            3
-#define FE1                             4
-#define UDRE1                           5
-#define TXC1                            6
-#define RXC1                            7
-
-/* USART1 Control and Status Register B */
-#define UCSR1B                          _SFR_MEM8(0xC9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1B {
-        unsigned int txb81 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb81 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz12 : 1;	/* Character Size */
-        unsigned int txen1 : 1;	/* Transmitter Enable */
-        unsigned int rxen1 : 1;	/* Receiver Enable */
-        unsigned int udrie1 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie1 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie1 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1B */
-
-#define TXB81                           0
-#define RXB81                           1
-#define UCSZ12                          2
-#define TXEN1                           3
-#define RXEN1                           4
-#define UDRIE1                          5
-#define TXCIE1                          6
-#define RXCIE1                          7
-
-/* USART1 Control and Status Register C */
-#define UCSR1C                          _SFR_MEM8(0xCA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1C {
-        unsigned int ucpol1 : 1;	/* Clock Polarity */
-        unsigned int ucsz1 : 2;	/* Character Size */
-        unsigned int ucpha1 : 1;	/* Clock Phase */
-        unsigned int udord1 : 1;	/* Data Order */
-        unsigned int usbs1 : 1;	/* Stop Bit Select */
-        unsigned int upm1 : 2;	/* Parity Mode */
-        unsigned int umsel1 : 2;	/* USART Mode Select */
-};
-
-#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1C */
-
-#define UCPOL1                          0
-#define UCPHA1                          1
-#define UCPHA1                          1
-#define UCSZ10                          1
-#define UDORD1                          2
-#define UDORD1                          2
-#define UCSZ11                          2
-#define USBS1                           3
-#define UPM10                           4
-#define UPM11                           5
-#define UMSEL10                         6
-#define UMSEL11                         7
-
-/* USART1 Baud Rate Register  Bytes */
-#define UBRR1                           _SFR_MEM16(0xCC)
-#define UBRR1L                          _SFR_MEM8(0xCC)
-#define UBRR1H                          _SFR_MEM8(0xCD)
-
-/* USART1 I/O Data Register */
-#define UDR1                            _SFR_MEM8(0xCE)
-
-  /* UDR1 */
-
-#define UDR10                           0
-#define UDR11                           1
-#define UDR12                           2
-#define UDR13                           3
-#define UDR14                           4
-#define UDR15                           5
-#define UDR16                           6
-#define UDR17                           7
-
-/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-#define SCRSTRLL                        _SFR_MEM8(0xD7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLL {
-        unsigned int scrstrll : 8;	/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-};
-
-#define SCRSTRLL_struct _SFR_MEM8_STRUCT(0xd7, struct __reg_SCRSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLL */
-
-#define SCRSTRLL0                       0
-#define SCRSTRLL1                       1
-#define SCRSTRLL2                       2
-#define SCRSTRLL3                       3
-#define SCRSTRLL4                       4
-#define SCRSTRLL5                       5
-#define SCRSTRLL6                       6
-#define SCRSTRLL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-#define SCRSTRLH                        _SFR_MEM8(0xD8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLH {
-        unsigned int scrstrlh : 8;	/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-};
-
-#define SCRSTRLH_struct _SFR_MEM8_STRUCT(0xd8, struct __reg_SCRSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLH */
-
-#define SCRSTRLH0                       0
-#define SCRSTRLH1                       1
-#define SCRSTRLH2                       2
-#define SCRSTRLH3                       3
-#define SCRSTRLH4                       4
-#define SCRSTRLH5                       5
-#define SCRSTRLH6                       6
-#define SCRSTRLH7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-#define SCRSTRHL                        _SFR_MEM8(0xD9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHL {
-        unsigned int scrstrhl : 8;	/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-};
-
-#define SCRSTRHL_struct _SFR_MEM8_STRUCT(0xd9, struct __reg_SCRSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHL */
-
-#define SCRSTRHL0                       0
-#define SCRSTRHL1                       1
-#define SCRSTRHL2                       2
-#define SCRSTRHL3                       3
-#define SCRSTRHL4                       4
-#define SCRSTRHL5                       5
-#define SCRSTRHL6                       6
-#define SCRSTRHL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-#define SCRSTRHH                        _SFR_MEM8(0xDA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHH {
-        unsigned int scrstrhh : 8;	/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-};
-
-#define SCRSTRHH_struct _SFR_MEM8_STRUCT(0xda, struct __reg_SCRSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHH */
-
-#define SCRSTRHH0                       0
-#define SCRSTRHH1                       1
-#define SCRSTRHH2                       2
-#define SCRSTRHH3                       3
-#define SCRSTRHH4                       4
-#define SCRSTRHH5                       5
-#define SCRSTRHH6                       6
-#define SCRSTRHH7                       7
-
-/* Symbol Counter Compare Source Register */
-#define SCCSR                           _SFR_MEM8(0xDB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCSR {
-        unsigned int sccs1 : 2;	/* Symbol Counter Compare Source select register for Compare Units */
-        unsigned int sccs2 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 2 */
-        unsigned int sccs3 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 3 */
-        unsigned int : 2;
-};
-
-#define SCCSR_struct _SFR_MEM8_STRUCT(0xdb, struct __reg_SCCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCSR */
-
-#define SCCS10                          0
-#define SCCS11                          1
-#define SCCS20                          2
-#define SCCS21                          3
-#define SCCS30                          4
-#define SCCS31                          5
-
-/* Symbol Counter Control Register 0 */
-#define SCCR0                           _SFR_MEM8(0xDC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR0 {
-        unsigned int sccmp : 3;	/* Symbol Counter Compare Unit 3 Mode select */
-        unsigned int sctse : 1;	/* Symbol Counter Automatic Timestamping enable */
-        unsigned int sccksel : 1;	/* Symbol Counter Clock Source select */
-        unsigned int scen : 1;	/* Symbol Counter enable */
-        unsigned int scmbts : 1;	/* Manual Beacon Timestamp */
-        unsigned int scres : 1;	/* Symbol Counter Synchronization */
-};
-
-#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR0 */
-
-#define SCCMP1                          0
-#define SCCMP2                          1
-#define SCCMP3                          2
-#define SCTSE                           3
-#define SCCKSEL                         4
-#define SCEN                            5
-#define SCMBTS                          6
-#define SCRES                           7
-
-/* Symbol Counter Control Register 1 */
-#define SCCR1                           _SFR_MEM8(0xDD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR1 {
-        unsigned int scenbo : 1;	/* Backoff Slot Counter enable */
-        unsigned int sceeclk : 1;	/* Enable External Clock Source on PG2 */
-        unsigned int scckdiv : 3;	/* Clock divider for synchronous clock source (16MHz Transceiver Clock) */
-        unsigned int scbtsm : 1;	/* Symbol Counter Beacon Timestamp Mask Register */
-        unsigned int : 2;
-};
-
-#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR1 */
-
-#define SCENBO                          0
-#define SCEECLK                         1
-#define SCCKDIV0                        2
-#define SCCKDIV1                        3
-#define SCCKDIV2                        4
-#define SCBTSM                          5
-
-/* Symbol Counter Status Register */
-#define SCSR                            _SFR_MEM8(0xDE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCSR {
-        unsigned int scbsy : 1;	/* Symbol Counter busy */
-        unsigned int : 7;
-};
-
-#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCSR */
-
-#define SCBSY                           0
-
-/* Symbol Counter Interrupt Mask Register */
-#define SCIRQM                          _SFR_MEM8(0xDF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQM {
-        unsigned int irqmcp : 3;	/* Symbol Counter Compare Match 3 IRQ enable */
-        unsigned int irqmof : 1;	/* Symbol Counter Overflow IRQ enable */
-        unsigned int irqmbo : 1;	/* Backoff Slot Counter IRQ enable */
-        unsigned int : 3;
-};
-
-#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQM */
-
-#define IRQMCP1                         0
-#define IRQMCP2                         1
-#define IRQMCP3                         2
-#define IRQMOF                          3
-#define IRQMBO                          4
-
-/* Symbol Counter Interrupt Status Register */
-#define SCIRQS                          _SFR_MEM8(0xE0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQS {
-        unsigned int irqscp : 3;	/* Compare Unit 3 Compare Match IRQ */
-        unsigned int irqsof : 1;	/* Symbol Counter Overflow IRQ */
-        unsigned int irqsbo : 1;	/* Backoff Slot Counter IRQ */
-        unsigned int : 3;
-};
-
-#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQS */
-
-#define IRQSCP1                         0
-#define IRQSCP2                         1
-#define IRQSCP3                         2
-#define IRQSOF                          3
-#define IRQSBO                          4
-
-/* Symbol Counter Register LL-Byte */
-#define SCCNTLL                         _SFR_MEM8(0xE1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLL {
-        unsigned int sccntll : 8;	/* Symbol Counter Register LL-Byte */
-};
-
-#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLL */
-
-#define SCCNTLL0                        0
-#define SCCNTLL1                        1
-#define SCCNTLL2                        2
-#define SCCNTLL3                        3
-#define SCCNTLL4                        4
-#define SCCNTLL5                        5
-#define SCCNTLL6                        6
-#define SCCNTLL7                        7
-
-/* Symbol Counter Register LH-Byte */
-#define SCCNTLH                         _SFR_MEM8(0xE2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLH {
-        unsigned int sccntlh : 8;	/* Symbol Counter Register LH-Byte */
-};
-
-#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLH */
-
-#define SCCNTLH0                        0
-#define SCCNTLH1                        1
-#define SCCNTLH2                        2
-#define SCCNTLH3                        3
-#define SCCNTLH4                        4
-#define SCCNTLH5                        5
-#define SCCNTLH6                        6
-#define SCCNTLH7                        7
-
-/* Symbol Counter Register HL-Byte */
-#define SCCNTHL                         _SFR_MEM8(0xE3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHL {
-        unsigned int sccnthl : 8;	/* Symbol Counter Register HL-Byte */
-};
-
-#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHL */
-
-#define SCCNTHL0                        0
-#define SCCNTHL1                        1
-#define SCCNTHL2                        2
-#define SCCNTHL3                        3
-#define SCCNTHL4                        4
-#define SCCNTHL5                        5
-#define SCCNTHL6                        6
-#define SCCNTHL7                        7
-
-/* Symbol Counter Register HH-Byte */
-#define SCCNTHH                         _SFR_MEM8(0xE4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHH {
-        unsigned int sccnthh : 8;	/* Symbol Counter Register HH-Byte */
-};
-
-#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHH */
-
-#define SCCNTHH0                        0
-#define SCCNTHH1                        1
-#define SCCNTHH2                        2
-#define SCCNTHH3                        3
-#define SCCNTHH4                        4
-#define SCCNTHH5                        5
-#define SCCNTHH6                        6
-#define SCCNTHH7                        7
-
-/* Symbol Counter Beacon Timestamp Register LL-Byte */
-#define SCBTSRLL                        _SFR_MEM8(0xE5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLL {
-        unsigned int scbtsrll : 8;	/* Symbol Counter Beacon Timestamp Register LL-Byte */
-};
-
-#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLL */
-
-#define SCBTSRLL0                       0
-#define SCBTSRLL1                       1
-#define SCBTSRLL2                       2
-#define SCBTSRLL3                       3
-#define SCBTSRLL4                       4
-#define SCBTSRLL5                       5
-#define SCBTSRLL6                       6
-#define SCBTSRLL7                       7
-
-/* Symbol Counter Beacon Timestamp Register LH-Byte */
-#define SCBTSRLH                        _SFR_MEM8(0xE6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLH {
-        unsigned int scbtsrlh : 8;	/* Symbol Counter Beacon Timestamp Register LH-Byte */
-};
-
-#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLH */
-
-#define SCBTSRLH0                       0
-#define SCBTSRLH1                       1
-#define SCBTSRLH2                       2
-#define SCBTSRLH3                       3
-#define SCBTSRLH4                       4
-#define SCBTSRLH5                       5
-#define SCBTSRLH6                       6
-#define SCBTSRLH7                       7
-
-/* Symbol Counter Beacon Timestamp Register HL-Byte */
-#define SCBTSRHL                        _SFR_MEM8(0xE7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHL {
-        unsigned int scbtsrhl : 8;	/* Symbol Counter Beacon Timestamp Register HL-Byte */
-};
-
-#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHL */
-
-#define SCBTSRHL0                       0
-#define SCBTSRHL1                       1
-#define SCBTSRHL2                       2
-#define SCBTSRHL3                       3
-#define SCBTSRHL4                       4
-#define SCBTSRHL5                       5
-#define SCBTSRHL6                       6
-#define SCBTSRHL7                       7
-
-/* Symbol Counter Beacon Timestamp Register HH-Byte */
-#define SCBTSRHH                        _SFR_MEM8(0xE8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHH {
-        unsigned int scbtsrhh : 8;	/* Symbol Counter Beacon Timestamp Register HH-Byte */
-};
-
-#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHH */
-
-#define SCBTSRHH0                       0
-#define SCBTSRHH1                       1
-#define SCBTSRHH2                       2
-#define SCBTSRHH3                       3
-#define SCBTSRHH4                       4
-#define SCBTSRHH5                       5
-#define SCBTSRHH6                       6
-#define SCBTSRHH7                       7
-
-/* Symbol Counter Frame Timestamp Register LL-Byte */
-#define SCTSRLL                         _SFR_MEM8(0xE9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLL {
-        unsigned int sctsrll : 8;	/* Symbol Counter Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLL */
-
-#define SCTSRLL0                        0
-#define SCTSRLL1                        1
-#define SCTSRLL2                        2
-#define SCTSRLL3                        3
-#define SCTSRLL4                        4
-#define SCTSRLL5                        5
-#define SCTSRLL6                        6
-#define SCTSRLL7                        7
-
-/* Symbol Counter Frame Timestamp Register LH-Byte */
-#define SCTSRLH                         _SFR_MEM8(0xEA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLH {
-        unsigned int sctsrlh : 8;	/* Symbol Counter Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLH */
-
-#define SCTSRLH0                        0
-#define SCTSRLH1                        1
-#define SCTSRLH2                        2
-#define SCTSRLH3                        3
-#define SCTSRLH4                        4
-#define SCTSRLH5                        5
-#define SCTSRLH6                        6
-#define SCTSRLH7                        7
-
-/* Symbol Counter Frame Timestamp Register HL-Byte */
-#define SCTSRHL                         _SFR_MEM8(0xEB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHL {
-        unsigned int sctsrhl : 8;	/* Symbol Counter Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHL */
-
-#define SCTSRHL0                        0
-#define SCTSRHL1                        1
-#define SCTSRHL2                        2
-#define SCTSRHL3                        3
-#define SCTSRHL4                        4
-#define SCTSRHL5                        5
-#define SCTSRHL6                        6
-#define SCTSRHL7                        7
-
-/* Symbol Counter Frame Timestamp Register HH-Byte */
-#define SCTSRHH                         _SFR_MEM8(0xEC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHH {
-        unsigned int sctsrhh : 8;	/* Symbol Counter Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHH */
-
-#define SCTSRHH0                        0
-#define SCTSRHH1                        1
-#define SCTSRHH2                        2
-#define SCTSRHH3                        3
-#define SCTSRHH4                        4
-#define SCTSRHH5                        5
-#define SCTSRHH6                        6
-#define SCTSRHH7                        7
-
-/* Symbol Counter Output Compare Register 3 LL-Byte */
-#define SCOCR3LL                        _SFR_MEM8(0xED)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LL {
-        unsigned int scocr3ll : 8;	/* Symbol Counter Output Compare Register 3 LL-Byte */
-};
-
-#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LL */
-
-#define SCOCR3LL0                       0
-#define SCOCR3LL1                       1
-#define SCOCR3LL2                       2
-#define SCOCR3LL3                       3
-#define SCOCR3LL4                       4
-#define SCOCR3LL5                       5
-#define SCOCR3LL6                       6
-#define SCOCR3LL7                       7
-
-/* Symbol Counter Output Compare Register 3 LH-Byte */
-#define SCOCR3LH                        _SFR_MEM8(0xEE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LH {
-        unsigned int scocr3lh : 8;	/* Symbol Counter Output Compare Register 3 LH-Byte */
-};
-
-#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LH */
-
-#define SCOCR3LH0                       0
-#define SCOCR3LH1                       1
-#define SCOCR3LH2                       2
-#define SCOCR3LH3                       3
-#define SCOCR3LH4                       4
-#define SCOCR3LH5                       5
-#define SCOCR3LH6                       6
-#define SCOCR3LH7                       7
-
-/* Symbol Counter Output Compare Register 3 HL-Byte */
-#define SCOCR3HL                        _SFR_MEM8(0xEF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HL {
-        unsigned int scocr3hl : 8;	/* Symbol Counter Output Compare Register 3 HL-Byte */
-};
-
-#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HL */
-
-#define SCOCR3HL0                       0
-#define SCOCR3HL1                       1
-#define SCOCR3HL2                       2
-#define SCOCR3HL3                       3
-#define SCOCR3HL4                       4
-#define SCOCR3HL5                       5
-#define SCOCR3HL6                       6
-#define SCOCR3HL7                       7
-
-/* Symbol Counter Output Compare Register 3 HH-Byte */
-#define SCOCR3HH                        _SFR_MEM8(0xF0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HH {
-        unsigned int scocr3hh : 8;	/* Symbol Counter Output Compare Register 3 HH-Byte */
-};
-
-#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HH */
-
-#define SCOCR3HH0                       0
-#define SCOCR3HH1                       1
-#define SCOCR3HH2                       2
-#define SCOCR3HH3                       3
-#define SCOCR3HH4                       4
-#define SCOCR3HH5                       5
-#define SCOCR3HH6                       6
-#define SCOCR3HH7                       7
-
-/* Symbol Counter Output Compare Register 2 LL-Byte */
-#define SCOCR2LL                        _SFR_MEM8(0xF1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LL {
-        unsigned int scocr2ll : 8;	/* Symbol Counter Output Compare Register 2 LL-Byte */
-};
-
-#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LL */
-
-#define SCOCR2LL0                       0
-#define SCOCR2LL1                       1
-#define SCOCR2LL2                       2
-#define SCOCR2LL3                       3
-#define SCOCR2LL4                       4
-#define SCOCR2LL5                       5
-#define SCOCR2LL6                       6
-#define SCOCR2LL7                       7
-
-/* Symbol Counter Output Compare Register 2 LH-Byte */
-#define SCOCR2LH                        _SFR_MEM8(0xF2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LH {
-        unsigned int scocr2lh : 8;	/* Symbol Counter Output Compare Register 2 LH-Byte */
-};
-
-#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LH */
-
-#define SCOCR2LH0                       0
-#define SCOCR2LH1                       1
-#define SCOCR2LH2                       2
-#define SCOCR2LH3                       3
-#define SCOCR2LH4                       4
-#define SCOCR2LH5                       5
-#define SCOCR2LH6                       6
-#define SCOCR2LH7                       7
-
-/* Symbol Counter Output Compare Register 2 HL-Byte */
-#define SCOCR2HL                        _SFR_MEM8(0xF3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HL {
-        unsigned int scocr2hl : 8;	/* Symbol Counter Output Compare Register 2 HL-Byte */
-};
-
-#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HL */
-
-#define SCOCR2HL0                       0
-#define SCOCR2HL1                       1
-#define SCOCR2HL2                       2
-#define SCOCR2HL3                       3
-#define SCOCR2HL4                       4
-#define SCOCR2HL5                       5
-#define SCOCR2HL6                       6
-#define SCOCR2HL7                       7
-
-/* Symbol Counter Output Compare Register 2 HH-Byte */
-#define SCOCR2HH                        _SFR_MEM8(0xF4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HH {
-        unsigned int scocr2hh : 8;	/* Symbol Counter Output Compare Register 2 HH-Byte */
-};
-
-#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HH */
-
-#define SCOCR2HH0                       0
-#define SCOCR2HH1                       1
-#define SCOCR2HH2                       2
-#define SCOCR2HH3                       3
-#define SCOCR2HH4                       4
-#define SCOCR2HH5                       5
-#define SCOCR2HH6                       6
-#define SCOCR2HH7                       7
-
-/* Symbol Counter Output Compare Register 1 LL-Byte */
-#define SCOCR1LL                        _SFR_MEM8(0xF5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LL {
-        unsigned int scocr1ll : 8;	/* Symbol Counter Output Compare Register 1 LL-Byte */
-};
-
-#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LL */
-
-#define SCOCR1LL0                       0
-#define SCOCR1LL1                       1
-#define SCOCR1LL2                       2
-#define SCOCR1LL3                       3
-#define SCOCR1LL4                       4
-#define SCOCR1LL5                       5
-#define SCOCR1LL6                       6
-#define SCOCR1LL7                       7
-
-/* Symbol Counter Output Compare Register 1 LH-Byte */
-#define SCOCR1LH                        _SFR_MEM8(0xF6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LH {
-        unsigned int scocr1lh : 8;	/* Symbol Counter Output Compare Register 1 LH-Byte */
-};
-
-#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LH */
-
-#define SCOCR1LH0                       0
-#define SCOCR1LH1                       1
-#define SCOCR1LH2                       2
-#define SCOCR1LH3                       3
-#define SCOCR1LH4                       4
-#define SCOCR1LH5                       5
-#define SCOCR1LH6                       6
-#define SCOCR1LH7                       7
-
-/* Symbol Counter Output Compare Register 1 HL-Byte */
-#define SCOCR1HL                        _SFR_MEM8(0xF7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HL {
-        unsigned int scocr1hl : 8;	/* Symbol Counter Output Compare Register 1 HL-Byte */
-};
-
-#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HL */
-
-#define SCOCR1HL0                       0
-#define SCOCR1HL1                       1
-#define SCOCR1HL2                       2
-#define SCOCR1HL3                       3
-#define SCOCR1HL4                       4
-#define SCOCR1HL5                       5
-#define SCOCR1HL6                       6
-#define SCOCR1HL7                       7
-
-/* Symbol Counter Output Compare Register 1 HH-Byte */
-#define SCOCR1HH                        _SFR_MEM8(0xF8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HH {
-        unsigned int scocr1hh : 8;	/* Symbol Counter Output Compare Register 1 HH-Byte */
-};
-
-#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HH */
-
-#define SCOCR1HH0                       0
-#define SCOCR1HH1                       1
-#define SCOCR1HH2                       2
-#define SCOCR1HH3                       3
-#define SCOCR1HH4                       4
-#define SCOCR1HH5                       5
-#define SCOCR1HH6                       6
-#define SCOCR1HH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-#define SCTSTRLL                        _SFR_MEM8(0xF9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLL {
-        unsigned int sctstrll : 8;	/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSTRLL_struct _SFR_MEM8_STRUCT(0xf9, struct __reg_SCTSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLL */
-
-#define SCTSTRLL0                       0
-#define SCTSTRLL1                       1
-#define SCTSTRLL2                       2
-#define SCTSTRLL3                       3
-#define SCTSTRLL4                       4
-#define SCTSTRLL5                       5
-#define SCTSTRLL6                       6
-#define SCTSTRLL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-#define SCTSTRLH                        _SFR_MEM8(0xFA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLH {
-        unsigned int sctstrlh : 8;	/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSTRLH_struct _SFR_MEM8_STRUCT(0xfa, struct __reg_SCTSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLH */
-
-#define SCTSTRLH0                       0
-#define SCTSTRLH1                       1
-#define SCTSTRLH2                       2
-#define SCTSTRLH3                       3
-#define SCTSTRLH4                       4
-#define SCTSTRLH5                       5
-#define SCTSTRLH6                       6
-#define SCTSTRLH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-#define SCTSTRHL                        _SFR_MEM8(0xFB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHL {
-        unsigned int sctstrhl : 8;	/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSTRHL_struct _SFR_MEM8_STRUCT(0xfb, struct __reg_SCTSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHL */
-
-#define SCTSTRHL0                       0
-#define SCTSTRHL1                       1
-#define SCTSTRHL2                       2
-#define SCTSTRHL3                       3
-#define SCTSTRHL4                       4
-#define SCTSTRHL5                       5
-#define SCTSTRHL6                       6
-#define SCTSTRHL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-#define SCTSTRHH                        _SFR_MEM8(0xFC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHH {
-        unsigned int sctstrhh : 8;	/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSTRHH_struct _SFR_MEM8_STRUCT(0xfc, struct __reg_SCTSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHH */
-
-#define SCTSTRHH0                       0
-#define SCTSTRHH1                       1
-#define SCTSTRHH2                       2
-#define SCTSTRHH3                       3
-#define SCTSTRHH4                       4
-#define SCTSTRHH5                       5
-#define SCTSTRHH6                       6
-#define SCTSTRHH7                       7
-
-/* Multiple Address Filter Configuration Register 0 */
-#define MAFCR0                          _SFR_MEM8(0x10C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR0 {
-        unsigned int maf0en : 1;	/* Multiple Address Filter 0 Enable */
-        unsigned int maf1en : 1;	/* Multiple Address Filter 1 Enable */
-        unsigned int maf2en : 1;	/* Multiple Address Filter 2 Enable */
-        unsigned int maf3en : 1;	/* Multiple Address Filter 3 Enable */
-        unsigned int : 4;
-};
-
-#define MAFCR0_struct _SFR_MEM8_STRUCT(0x10c, struct __reg_MAFCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR0 */
-
-#define MAF0EN                          0
-#define MAF1EN                          1
-#define MAF2EN                          2
-#define MAF3EN                          3
-
-/* Multiple Address Filter Configuration Register 1 */
-#define MAFCR1                          _SFR_MEM8(0x10D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR1 {
-        unsigned int aack_0_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 0. */
-        unsigned int aack_0_set_pd : 1;	/* Set Data Pending bit for address filter 0. */
-        unsigned int aack_1_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 1. */
-        unsigned int aack_1_set_pd : 1;	/* Set Data Pending bit for address filter 1. */
-        unsigned int aack_2_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 2. */
-        unsigned int aack_2_set_pd : 1;	/* Set Data Pending bit for address filter 2. */
-        unsigned int aack_3_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 3. */
-        unsigned int aack_3_set_pd : 1;	/* Set Data Pending bit for address filter 3. */
-};
-
-#define MAFCR1_struct _SFR_MEM8_STRUCT(0x10d, struct __reg_MAFCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR1 */
-
-#define AACK_0_I_AM_COORD               0
-#define AACK_0_SET_PD                   1
-#define AACK_1_I_AM_COORD               2
-#define AACK_1_SET_PD                   3
-#define AACK_2_I_AM_COORD               4
-#define AACK_2_SET_PD                   5
-#define AACK_3_I_AM_COORD               6
-#define AACK_3_SET_PD                   7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) */
-#define MAFSA0L                         _SFR_MEM8(0x10E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0L {
-        unsigned int mafsa0l : 8;	/* MAC Short Address low Byte for Frame Filter 0 */
-};
-
-#define MAFSA0L_struct _SFR_MEM8_STRUCT(0x10e, struct __reg_MAFSA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0L */
-
-#define MAFSA0L0                        0
-#define MAFSA0L1                        1
-#define MAFSA0L2                        2
-#define MAFSA0L3                        3
-#define MAFSA0L4                        4
-#define MAFSA0L5                        5
-#define MAFSA0L6                        6
-#define MAFSA0L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) */
-#define MAFSA0H                         _SFR_MEM8(0x10F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0H {
-        unsigned int mafsa0h : 8;	/* MAC Short Address high Byte for Frame Filter 0 */
-};
-
-#define MAFSA0H_struct _SFR_MEM8_STRUCT(0x10f, struct __reg_MAFSA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0H */
-
-#define MAFSA0H0                        0
-#define MAFSA0H1                        1
-#define MAFSA0H2                        2
-#define MAFSA0H3                        3
-#define MAFSA0H4                        4
-#define MAFSA0H5                        5
-#define MAFSA0H6                        6
-#define MAFSA0H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) */
-#define MAFPA0L                         _SFR_MEM8(0x110)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0L {
-        unsigned int mafpa0l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 0 */
-};
-
-#define MAFPA0L_struct _SFR_MEM8_STRUCT(0x110, struct __reg_MAFPA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0L */
-
-#define MAFPA0L0                        0
-#define MAFPA0L1                        1
-#define MAFPA0L2                        2
-#define MAFPA0L3                        3
-#define MAFPA0L4                        4
-#define MAFPA0L5                        5
-#define MAFPA0L6                        6
-#define MAFPA0L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) */
-#define MAFPA0H                         _SFR_MEM8(0x111)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0H {
-        unsigned int mafpa0h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 0 */
-};
-
-#define MAFPA0H_struct _SFR_MEM8_STRUCT(0x111, struct __reg_MAFPA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0H */
-
-#define MAFPA0H0                        0
-#define MAFPA0H1                        1
-#define MAFPA0H2                        2
-#define MAFPA0H3                        3
-#define MAFPA0H4                        4
-#define MAFPA0H5                        5
-#define MAFPA0H6                        6
-#define MAFPA0H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) */
-#define MAFSA1L                         _SFR_MEM8(0x112)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1L {
-        unsigned int mafsa1l : 8;	/* MAC Short Address low Byte for Frame Filter 1 */
-};
-
-#define MAFSA1L_struct _SFR_MEM8_STRUCT(0x112, struct __reg_MAFSA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1L */
-
-#define MAFSA1L0                        0
-#define MAFSA1L1                        1
-#define MAFSA1L2                        2
-#define MAFSA1L3                        3
-#define MAFSA1L4                        4
-#define MAFSA1L5                        5
-#define MAFSA1L6                        6
-#define MAFSA1L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) */
-#define MAFSA1H                         _SFR_MEM8(0x113)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1H {
-        unsigned int mafsa1h : 8;	/* MAC Short Address high Byte for Frame Filter 1 */
-};
-
-#define MAFSA1H_struct _SFR_MEM8_STRUCT(0x113, struct __reg_MAFSA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1H */
-
-#define MAFSA1H0                        0
-#define MAFSA1H1                        1
-#define MAFSA1H2                        2
-#define MAFSA1H3                        3
-#define MAFSA1H4                        4
-#define MAFSA1H5                        5
-#define MAFSA1H6                        6
-#define MAFSA1H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) */
-#define MAFPA1L                         _SFR_MEM8(0x114)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1L {
-        unsigned int mafpa1l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 1 */
-};
-
-#define MAFPA1L_struct _SFR_MEM8_STRUCT(0x114, struct __reg_MAFPA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1L */
-
-#define MAFPA1L0                        0
-#define MAFPA1L1                        1
-#define MAFPA1L2                        2
-#define MAFPA1L3                        3
-#define MAFPA1L4                        4
-#define MAFPA1L5                        5
-#define MAFPA1L6                        6
-#define MAFPA1L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) */
-#define MAFPA1H                         _SFR_MEM8(0x115)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1H {
-        unsigned int mafpa1h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 1 */
-};
-
-#define MAFPA1H_struct _SFR_MEM8_STRUCT(0x115, struct __reg_MAFPA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1H */
-
-#define MAFPA1H0                        0
-#define MAFPA1H1                        1
-#define MAFPA1H2                        2
-#define MAFPA1H3                        3
-#define MAFPA1H4                        4
-#define MAFPA1H5                        5
-#define MAFPA1H6                        6
-#define MAFPA1H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) */
-#define MAFSA2L                         _SFR_MEM8(0x116)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2L {
-        unsigned int mafsa2l : 8;	/* MAC Short Address low Byte for Frame Filter 2 */
-};
-
-#define MAFSA2L_struct _SFR_MEM8_STRUCT(0x116, struct __reg_MAFSA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2L */
-
-#define MAFSA2L0                        0
-#define MAFSA2L1                        1
-#define MAFSA2L2                        2
-#define MAFSA2L3                        3
-#define MAFSA2L4                        4
-#define MAFSA2L5                        5
-#define MAFSA2L6                        6
-#define MAFSA2L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) */
-#define MAFSA2H                         _SFR_MEM8(0x117)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2H {
-        unsigned int mafsa2h : 8;	/* MAC Short Address high Byte for Frame Filter 2 */
-};
-
-#define MAFSA2H_struct _SFR_MEM8_STRUCT(0x117, struct __reg_MAFSA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2H */
-
-#define MAFSA2H0                        0
-#define MAFSA2H1                        1
-#define MAFSA2H2                        2
-#define MAFSA2H3                        3
-#define MAFSA2H4                        4
-#define MAFSA2H5                        5
-#define MAFSA2H6                        6
-#define MAFSA2H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) */
-#define MAFPA2L                         _SFR_MEM8(0x118)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2L {
-        unsigned int mafpa2l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 2 */
-};
-
-#define MAFPA2L_struct _SFR_MEM8_STRUCT(0x118, struct __reg_MAFPA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2L */
-
-#define MAFPA2L0                        0
-#define MAFPA2L1                        1
-#define MAFPA2L2                        2
-#define MAFPA2L3                        3
-#define MAFPA2L4                        4
-#define MAFPA2L5                        5
-#define MAFPA2L6                        6
-#define MAFPA2L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) */
-#define MAFPA2H                         _SFR_MEM8(0x119)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2H {
-        unsigned int mafpa2h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 2 */
-};
-
-#define MAFPA2H_struct _SFR_MEM8_STRUCT(0x119, struct __reg_MAFPA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2H */
-
-#define MAFPA2H0                        0
-#define MAFPA2H1                        1
-#define MAFPA2H2                        2
-#define MAFPA2H3                        3
-#define MAFPA2H4                        4
-#define MAFPA2H5                        5
-#define MAFPA2H6                        6
-#define MAFPA2H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) */
-#define MAFSA3L                         _SFR_MEM8(0x11A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3L {
-        unsigned int mafsa3l : 8;	/* MAC Short Address low Byte for Frame Filter 3 */
-};
-
-#define MAFSA3L_struct _SFR_MEM8_STRUCT(0x11a, struct __reg_MAFSA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3L */
-
-#define MAFSA3L0                        0
-#define MAFSA3L1                        1
-#define MAFSA3L2                        2
-#define MAFSA3L3                        3
-#define MAFSA3L4                        4
-#define MAFSA3L5                        5
-#define MAFSA3L6                        6
-#define MAFSA3L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) */
-#define MAFSA3H                         _SFR_MEM8(0x11B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3H {
-        unsigned int mafsa3h : 8;	/* MAC Short Address high Byte for Frame Filter 3 */
-};
-
-#define MAFSA3H_struct _SFR_MEM8_STRUCT(0x11b, struct __reg_MAFSA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3H */
-
-#define MAFSA3H0                        0
-#define MAFSA3H1                        1
-#define MAFSA3H2                        2
-#define MAFSA3H3                        3
-#define MAFSA3H4                        4
-#define MAFSA3H5                        5
-#define MAFSA3H6                        6
-#define MAFSA3H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) */
-#define MAFPA3L                         _SFR_MEM8(0x11C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3L {
-        unsigned int mafpa3l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 3 */
-};
-
-#define MAFPA3L_struct _SFR_MEM8_STRUCT(0x11c, struct __reg_MAFPA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3L */
-
-#define MAFPA3L0                        0
-#define MAFPA3L1                        1
-#define MAFPA3L2                        2
-#define MAFPA3L3                        3
-#define MAFPA3L4                        4
-#define MAFPA3L5                        5
-#define MAFPA3L6                        6
-#define MAFPA3L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) */
-#define MAFPA3H                         _SFR_MEM8(0x11D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3H {
-        unsigned int mafpa3h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 3 */
-};
-
-#define MAFPA3H_struct _SFR_MEM8_STRUCT(0x11d, struct __reg_MAFPA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3H */
-
-#define MAFPA3H0                        0
-#define MAFPA3H1                        1
-#define MAFPA3H2                        2
-#define MAFPA3H3                        3
-#define MAFPA3H4                        4
-#define MAFPA3H5                        5
-#define MAFPA3H6                        6
-#define MAFPA3H7                        7
-
-/* Timer/Counter5 Control Register A */
-#define TCCR5A                          _SFR_MEM8(0x120)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5A {
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int com5c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com5b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com5a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5A */
-
-#define WGM50                           0
-#define WGM51                           1
-#define COM5C0                          2
-#define COM5C1                          3
-#define COM5B0                          4
-#define COM5B1                          5
-#define COM5A0                          6
-#define COM5A1                          7
-
-/* Timer/Counter5 Control Register B */
-#define TCCR5B                          _SFR_MEM8(0x121)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5B {
-        unsigned int cs5 : 3;	/* Clock Select */
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices5 : 1;	/* Input Capture 5 Edge Select */
-        unsigned int icnc5 : 1;	/* Input Capture 5 Noise Canceller */
-};
-
-#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5B */
-
-#define CS50                            0
-#define CS51                            1
-#define CS52                            2
-#define WGM52                           3
-#define WGM53                           4
-#define ICES5                           6
-#define ICNC5                           7
-
-/* Timer/Counter5 Control Register C */
-#define TCCR5C                          _SFR_MEM8(0x122)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5C {
-        unsigned int : 5;
-        unsigned int foc5c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc5b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc5a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5C */
-
-#define FOC5C                           5
-#define FOC5B                           6
-#define FOC5A                           7
-
-/* Timer/Counter5  Bytes */
-#define TCNT5                           _SFR_MEM16(0x124)
-#define TCNT5L                          _SFR_MEM8(0x124)
-#define TCNT5H                          _SFR_MEM8(0x125)
-
-/* Timer/Counter5 Input Capture Register  Bytes */
-#define ICR5                            _SFR_MEM16(0x126)
-#define ICR5L                           _SFR_MEM8(0x126)
-#define ICR5H                           _SFR_MEM8(0x127)
-
-/* Timer/Counter5 Output Compare Register A  Bytes */
-#define OCR5A                           _SFR_MEM16(0x128)
-#define OCR5AL                          _SFR_MEM8(0x128)
-#define OCR5AH                          _SFR_MEM8(0x129)
-
-/* Timer/Counter5 Output Compare Register B  Bytes */
-#define OCR5B                           _SFR_MEM16(0x12A)
-#define OCR5BL                          _SFR_MEM8(0x12A)
-#define OCR5BH                          _SFR_MEM8(0x12B)
-
-/* Timer/Counter5 Output Compare Register C  Bytes */
-#define OCR5C                           _SFR_MEM16(0x12C)
-#define OCR5CL                          _SFR_MEM8(0x12C)
-#define OCR5CH                          _SFR_MEM8(0x12D)
-
-/* Low Leakage Voltage Regulator Control Register */
-#define LLCR                            _SFR_MEM8(0x12F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLCR {
-        unsigned int llencal : 1;	/* Enable Automatic Calibration */
-        unsigned int llshort : 1;	/* Short Lower Calibration Circuit */
-        unsigned int lltco : 1;	/* Temperature Coefficient of Current Source */
-        unsigned int llcal : 1;	/* Calibration Active */
-        unsigned int llcomp : 1;	/* Comparator Output */
-        unsigned int lldone : 1;	/* Calibration Done */
-        unsigned int : 2;
-};
-
-#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLCR */
-
-#define LLENCAL                         0
-#define LLSHORT                         1
-#define LLTCO                           2
-#define LLCAL                           3
-#define LLCOMP                          4
-#define LLDONE                          5
-
-/* Low Leakage Voltage Regulator Data Register (Low-Byte) */
-#define LLDRL                           _SFR_MEM8(0x130)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRL {
-        unsigned int lldrl : 4;	/* Low-Byte Data Register Bits */
-        unsigned int : 4;
-};
-
-#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRL */
-
-#define LLDRL0                          0
-#define LLDRL1                          1
-#define LLDRL2                          2
-#define LLDRL3                          3
-
-/* Low Leakage Voltage Regulator Data Register (High-Byte) */
-#define LLDRH                           _SFR_MEM8(0x131)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRH {
-        unsigned int lldrh : 5;	/* High-Byte Data Register Bits */
-        unsigned int : 3;
-};
-
-#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRH */
-
-#define LLDRH0                          0
-#define LLDRH1                          1
-#define LLDRH2                          2
-#define LLDRH3                          3
-#define LLDRH4                          4
-
-/* Data Retention Configuration Register #3 */
-#define DRTRAM3                         _SFR_MEM8(0x132)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM3 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM3 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #2 */
-#define DRTRAM2                         _SFR_MEM8(0x133)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM2 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM2 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #1 */
-#define DRTRAM1                         _SFR_MEM8(0x134)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM1 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM1 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #0 */
-#define DRTRAM0                         _SFR_MEM8(0x135)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM0 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM0 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Port Driver Strength Register 0 */
-#define DPDS0                           _SFR_MEM8(0x136)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS0 {
-        unsigned int pbdrv : 2;	/* Driver Strength Port B */
-        unsigned int pddrv : 2;	/* Driver Strength Port D */
-        unsigned int pedrv : 2;	/* Driver Strength Port E */
-        unsigned int pfdrv : 2;	/* Driver Strength Port F */
-};
-
-#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS0 */
-
-#define PBDRV0                          0
-#define PBDRV1                          1
-#define PDDRV0                          2
-#define PDDRV1                          3
-#define PEDRV0                          4
-#define PEDRV1                          5
-#define PFDRV0                          6
-#define PFDRV1                          7
-
-/* Port Driver Strength Register 1 */
-#define DPDS1                           _SFR_MEM8(0x137)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS1 {
-        unsigned int pgdrv : 2;	/* Driver Strength Port G */
-        unsigned int : 6;
-};
-
-#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS1 */
-
-#define PGDRV0                          0
-#define PGDRV1                          1
-
-/* Power Amplifier Ramp up/down Control Register */
-#define PARCR                           _SFR_MEM8(0x138)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PARCR {
-        unsigned int parufi : 1;	/* Power Amplifier Ramp Up Frequency Inversion */
-        unsigned int pardfi : 1;	/* Power Amplifier Ramp Down Frequency Inversion */
-        unsigned int paltu : 3;	/* ext. PA Ramp Up Lead Time */
-        unsigned int paltd : 3;	/* ext. PA Ramp Down Lead Time */
-};
-
-#define PARCR_struct _SFR_MEM8_STRUCT(0x138, struct __reg_PARCR)
-
-/* symbolic names */
-
-#define PALTU_MINUS_3US                 0
-#define PALTU_MINUS_2US                 1
-#define PALTU_MINUS_1US                 2
-#define PALTU_0US                       3
-#define PALTU_1US                       4
-#define PALTU_2US                       5
-#define PALTU_3US                       6
-#define PALTU_4US                       7
-#define PALTD_MINUS_3US                 0
-#define PALTD_MINUS_2US                 1
-#define PALTD_MINUS_1US                 2
-#define PALTD_0US                       3
-#define PALTD_1US                       4
-#define PALTD_2US                       5
-#define PALTD_3US                       6
-#define PALTD_4US                       7
-
-#endif /* __ASSEMBLER__ */
-
-  /* PARCR */
-
-#define PARUFI                          0
-#define PARDFI                          1
-#define PALTU0                          2
-#define PALTU1                          3
-#define PALTU2                          4
-#define PALTD0                          5
-#define PALTD1                          6
-#define PALTD2                          7
-
-/* Transceiver Pin Register */
-#define TRXPR                           _SFR_MEM8(0x139)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRXPR {
-        unsigned int trxrst : 1;	/* Force Transceiver Reset */
-        unsigned int slptr : 1;	/* Multi-purpose Transceiver Control Bit */
-        unsigned int : 6;
-};
-
-#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRXPR */
-
-#define TRXRST                          0
-#define SLPTR                           1
-
-/* AES Control Register */
-#define AES_CTRL                        _SFR_MEM8(0x13C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_CTRL {
-        unsigned int : 2;
-        unsigned int aes_im : 1;	/* AES Interrupt Enable */
-        unsigned int aes_dir : 1;	/* Set AES Operation Direction */
-        unsigned int : 1;
-        unsigned int aes_mode : 1;	/* Set AES Operation Mode */
-        unsigned int : 1;
-        unsigned int aes_request : 1;	/* Request AES Operation. */
-};
-
-#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL)
-
-/* symbolic names */
-
-#define AES_DIR_ENC                     0
-#define AES_DIR_DEC                     1
-#define AES_MODE_ECB                    0
-#define AES_MODE_CBC                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_CTRL */
-
-#define AES_IM                          2
-#define AES_DIR                         3
-#define AES_MODE                        5
-#define AES_REQUEST                     7
-
-/* AES Status Register */
-#define AES_STATUS                      _SFR_MEM8(0x13D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATUS {
-        unsigned int aes_done : 1;	/* AES Operation Finished with Success */
-        unsigned int : 6;
-        unsigned int aes_er : 1;	/* AES Operation Finished with Error */
-};
-
-#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATUS */
-
-#define AES_DONE                        0
-#define AES_ER                          7
-
-/* AES Plain and Cipher Text Buffer Register */
-#define AES_STATE                       _SFR_MEM8(0x13E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATE {
-        unsigned int aes_state : 8;	/* AES Plain and Cipher Text Buffer */
-};
-
-#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATE */
-
-#define AES_STATE0                      0
-#define AES_STATE1                      1
-#define AES_STATE2                      2
-#define AES_STATE3                      3
-#define AES_STATE4                      4
-#define AES_STATE5                      5
-#define AES_STATE6                      6
-#define AES_STATE7                      7
-
-/* AES Encryption and Decryption Key Buffer Register */
-#define AES_KEY                         _SFR_MEM8(0x13F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_KEY {
-        unsigned int aes_key : 8;	/* AES Encryption/Decryption Key Buffer */
-};
-
-#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_KEY */
-
-#define AES_KEY0                        0
-#define AES_KEY1                        1
-#define AES_KEY2                        2
-#define AES_KEY3                        3
-#define AES_KEY4                        4
-#define AES_KEY5                        5
-#define AES_KEY6                        6
-#define AES_KEY7                        7
-
-/* Transceiver Status Register */
-#define TRX_STATUS                      _SFR_MEM8(0x141)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATUS {
-        unsigned int trx_status : 5;	/* Transceiver Main Status */
-        unsigned int tst_status : 1;	/* Test mode status */
-        unsigned int cca_status : 1;	/* CCA Status Result */
-        unsigned int cca_done : 1;	/* CCA Algorithm Status */
-};
-
-#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS)
-
-/* symbolic names */
-
-#define BUSY_RX                         1
-#define BUSY_TX                         2
-#define RX_ON                           6
-#define TRX_OFF                         8
-#define PLL_ON                          9
-#define SLEEP                           15
-#define BUSY_RX_AACK                    17
-#define BUSY_TX_ARET                    18
-#define RX_AACK_ON                      22
-#define TX_ARET_ON                      25
-#define STATE_TRANSITION_IN_PROGRESS    31
-#define TST_DISABLED                    0
-#define TST_ENABLED                     1
-#define CCA_BUSY                        0
-#define CCA_IDLE                        1
-#define CCA_NOT_FIN                     0
-#define CCA_FIN                         1
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATUS */
-
-#define TRX_STATUS0                     0
-#define TRX_STATUS1                     1
-#define TRX_STATUS2                     2
-#define TRX_STATUS3                     3
-#define TRX_STATUS4                     4
-#define TST_STATUS                      5
-#define CCA_STATUS                      6
-#define CCA_DONE                        7
-
-/* Transceiver State Control Register */
-#define TRX_STATE                       _SFR_MEM8(0x142)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATE {
-        unsigned int trx_cmd : 5;	/* State Control Command */
-        unsigned int trac_status : 3;	/* Transaction Status */
-};
-
-#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE)
-
-/* symbolic names */
-
-#define CMD_NOP                         0
-#define CMD_TX_START                    2
-#define CMD_FORCE_TRX_OFF               3
-#define CMD_FORCE_PLL_ON                4
-#define CMD_RX_ON                       6
-#define CMD_TRX_OFF                     8
-#define CMD_PLL_ON                      9
-#define CMD_RX_AACK_ON                  22
-#define CMD_TX_ARET_ON                  25
-#define TRAC_SUCCESS                    0
-#define TRAC_SUCCESS_DATA_PENDING       1
-#define TRAC_SUCCESS_WAIT_FOR_ACK       2
-#define TRAC_CHANNEL_ACCESS_FAILURE     3
-#define TRAC_NO_ACK                     5
-#define TRAC_INVALID                    7
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATE */
-
-#define TRX_CMD0                        0
-#define TRX_CMD1                        1
-#define TRX_CMD2                        2
-#define TRX_CMD3                        3
-#define TRX_CMD4                        4
-#define TRAC_STATUS0                    5
-#define TRAC_STATUS1                    6
-#define TRAC_STATUS2                    7
-
-/* Tranceiver Control Register 0 */
-#define TRX_CTRL_0                      _SFR_MEM8(0x143)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_0 {
-        unsigned int : 4;
-        unsigned int pmu_if_inv : 1;	/* PMU IF Inverse */
-        unsigned int pmu_start : 1;	/* Start of Phase Measurement Unit */
-        unsigned int pmu_en : 1;	/* Enable Phase Measurement Unit */
-        unsigned int res7 : 1;	/* Reserved */
-};
-
-#define TRX_CTRL_0_struct _SFR_MEM8_STRUCT(0x143, struct __reg_TRX_CTRL_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_0 */
-
-#define PMU_IF_INV                      4
-#define PMU_START                       5
-#define PMU_EN                          6
-
-/* Transceiver Control Register 1 */
-#define TRX_CTRL_1                      _SFR_MEM8(0x144)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_1 {
-        unsigned int : 4;
-        unsigned int pll_tx_flt : 1;	/* Enable PLL TX Filter */
-        unsigned int tx_auto_crc_on : 1;	/* Enable Automatic CRC Calculation */
-        unsigned int irq_2_ext_en : 1;	/* Connect Frame Start IRQ to TC1 */
-        unsigned int pa_ext_en : 1;	/* External PA support enable */
-};
-
-#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_1 */
-
-#define PLL_TX_FLT                      4
-#define TX_AUTO_CRC_ON                  5
-#define IRQ_2_EXT_EN                    6
-#define PA_EXT_EN                       7
-
-/* Transceiver Transmit Power Control Register */
-#define PHY_TX_PWR                      _SFR_MEM8(0x145)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_TX_PWR {
-        unsigned int tx_pwr : 4;	/* Transmit Power Setting */
-        unsigned int : 4;
-};
-
-#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_TX_PWR */
-
-#define TX_PWR0                         0
-#define TX_PWR1                         1
-#define TX_PWR2                         2
-#define TX_PWR3                         3
-
-/* Receiver Signal Strength Indicator Register */
-#define PHY_RSSI                        _SFR_MEM8(0x146)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_RSSI {
-        unsigned int rssi : 5;	/* Receiver Signal Strength Indicator */
-        unsigned int rnd_value : 2;	/* Random Value */
-        unsigned int rx_crc_valid : 1;	/* Received Frame CRC Status */
-};
-
-#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI)
-
-/* symbolic names */
-
-#define RSSI_MIN                        0
-#define RSSI_MIN_PLUS_3dB               1
-#define RSSI_MAX                        28
-#define CRC_INVALID                     0
-#define CRC_VALID                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_RSSI */
-
-#define RSSI0                           0
-#define RSSI1                           1
-#define RSSI2                           2
-#define RSSI3                           3
-#define RSSI4                           4
-#define RND_VALUE0                      5
-#define RND_VALUE1                      6
-#define RX_CRC_VALID                    7
-
-/* Transceiver Energy Detection Level Register */
-#define PHY_ED_LEVEL                    _SFR_MEM8(0x147)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_ED_LEVEL {
-        unsigned int ed_level : 8;	/* Energy Detection Level */
-};
-
-#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL)
-
-/* symbolic names */
-
-#define ED_MIN                          0
-#define ED_MIN_PLUS_1dB                 1
-#define ED_MAX                          83
-#define ED_RESET                        255
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_ED_LEVEL */
-
-#define ED_LEVEL0                       0
-#define ED_LEVEL1                       1
-#define ED_LEVEL2                       2
-#define ED_LEVEL3                       3
-#define ED_LEVEL4                       4
-#define ED_LEVEL5                       5
-#define ED_LEVEL6                       6
-#define ED_LEVEL7                       7
-
-/* Transceiver Clear Channel Assessment (CCA) Control Register */
-#define PHY_CC_CCA                      _SFR_MEM8(0x148)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_CC_CCA {
-        unsigned int channel : 5;	/* RX/TX Channel Selection */
-        unsigned int cca_mode : 2;	/* Select CCA Measurement Mode */
-        unsigned int cca_request : 1;	/* Manual CCA Measurement Request */
-};
-
-#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA)
-
-/* symbolic names */
-
-#define F_2405MHZ                       11
-#define F_2410MHZ                       12
-#define F_2415MHZ                       13
-#define F_2420MHZ                       14
-#define F_2425MHZ                       15
-#define F_2430MHZ                       16
-#define F_2435MHZ                       17
-#define F_2440MHZ                       18
-#define F_2445MHZ                       19
-#define F_2450MHZ                       20
-#define F_2455MHZ                       21
-#define F_2460MHZ                       22
-#define F_2465MHZ                       23
-#define F_2470MHZ                       24
-#define F_2475MHZ                       25
-#define F_2480MHZ                       26
-#define CCA_CS_OR_ED                    0
-#define CCA_ED                          1
-#define CCA_CS                          2
-#define CCA_CS_AND_ED                   3
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_CC_CCA */
-
-#define CHANNEL0                        0
-#define CHANNEL1                        1
-#define CHANNEL2                        2
-#define CHANNEL3                        3
-#define CHANNEL4                        4
-#define CCA_MODE0                       5
-#define CCA_MODE1                       6
-#define CCA_REQUEST                     7
-
-/* Transceiver CCA Threshold Setting Register */
-#define CCA_THRES                       _SFR_MEM8(0x149)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CCA_THRES {
-        unsigned int cca_ed_thres : 4;	/* ED Threshold Level for CCA Measurement */
-        unsigned int cca_cs_thres : 4;	/* CS Threshold Level for CCA Measurement */
-};
-
-#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CCA_THRES */
-
-#define CCA_ED_THRES0                   0
-#define CCA_ED_THRES1                   1
-#define CCA_ED_THRES2                   2
-#define CCA_ED_THRES3                   3
-#define CCA_CS_THRES0                   4
-#define CCA_CS_THRES1                   5
-#define CCA_CS_THRES2                   6
-#define CCA_CS_THRES3                   7
-
-/* Transceiver Receive Control Register */
-#define RX_CTRL                         _SFR_MEM8(0x14A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_CTRL {
-        unsigned int pdt_thres : 4;	/* Receiver Sensitivity Control */
-        unsigned int : 4;
-};
-
-#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL)
-
-/* symbolic names */
-
-#define PDT_THRES_ANT_DIV_OFF           7
-#define PDT_THRES_ANT_DIV_ON            3
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_CTRL */
-
-#define PDT_THRES0                      0
-#define PDT_THRES1                      1
-#define PDT_THRES2                      2
-#define PDT_THRES3                      3
-
-/* Start of Frame Delimiter Value Register */
-#define SFD_VALUE                       _SFR_MEM8(0x14B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SFD_VALUE {
-        unsigned int sfd_value : 8;	/* Start of Frame Delimiter Value */
-};
-
-#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE)
-
-/* symbolic names */
-
-#define IEEE_SFD                        167
-
-#endif /* __ASSEMBLER__ */
-
-  /* SFD_VALUE */
-
-#define SFD_VALUE0                      0
-#define SFD_VALUE1                      1
-#define SFD_VALUE2                      2
-#define SFD_VALUE3                      3
-#define SFD_VALUE4                      4
-#define SFD_VALUE5                      5
-#define SFD_VALUE6                      6
-#define SFD_VALUE7                      7
-
-/* Transceiver Control Register 2 */
-#define TRX_CTRL_2                      _SFR_MEM8(0x14C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_2 {
-        unsigned int oqpsk_data_rate : 2;	/* Data Rate Selection */
-        unsigned int : 5;
-        unsigned int rx_safe_mode : 1;	/* RX Safe Mode */
-};
-
-#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2)
-
-/* symbolic names */
-
-#define RATE_250KB                      0
-#define RATE_500KB                      1
-#define RATE_1000KB                     2
-#define RATE_2000KB                     3
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_2 */
-
-#define OQPSK_DATA_RATE0                0
-#define OQPSK_DATA_RATE1                1
-#define RX_SAFE_MODE                    7
-
-/* Antenna Diversity Control Register */
-#define ANT_DIV                         _SFR_MEM8(0x14D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ANT_DIV {
-        unsigned int ant_ctrl : 2;	/* Static Antenna Diversity Switch Control */
-        unsigned int ant_ext_sw_en : 1;	/* Enable External Antenna Switch Control */
-        unsigned int ant_div_en : 1;	/* Enable Antenna Diversity */
-        unsigned int : 3;
-        unsigned int ant_sel : 1;	/* Antenna Diversity Antenna Status */
-};
-
-#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV)
-
-/* symbolic names */
-
-#define ANT_1                           1
-#define ANT_0                           2
-#define ANT_RESET                       3
-#define ANT_DIV_EXT_SW_DIS              0
-#define ANT_DIV_EXT_SW_EN               1
-#define ANTENNA_0                       0
-#define ANTENNA_1                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* ANT_DIV */
-
-#define ANT_CTRL0                       0
-#define ANT_CTRL1                       1
-#define ANT_EXT_SW_EN                   2
-#define ANT_DIV_EN                      3
-#define ANT_SEL                         7
-
-/* Transceiver Interrupt Enable Register */
-#define IRQ_MASK                        _SFR_MEM8(0x14E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK {
-        unsigned int pll_lock_en : 1;	/* PLL Lock Interrupt Enable */
-        unsigned int pll_unlock_en : 1;	/* PLL Unlock Interrupt Enable */
-        unsigned int rx_start_en : 1;	/* RX_START Interrupt Enable */
-        unsigned int rx_end_en : 1;	/* RX_END Interrupt Enable */
-        unsigned int cca_ed_done_en : 1;	/* End of ED Measurement Interrupt Enable */
-        unsigned int ami_en : 1;	/* Address Match Interrupt Enable */
-        unsigned int tx_end_en : 1;	/* TX_END Interrupt Enable */
-        unsigned int awake_en : 1;	/* Awake Interrupt Enable */
-};
-
-#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK */
-
-#define PLL_LOCK_EN                     0
-#define PLL_UNLOCK_EN                   1
-#define RX_START_EN                     2
-#define RX_END_EN                       3
-#define CCA_ED_DONE_EN                  4
-#define AMI_EN                          5
-#define TX_END_EN                       6
-#define AWAKE_EN                        7
-
-/* Transceiver Interrupt Status Register */
-#define IRQ_STATUS                      _SFR_MEM8(0x14F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS {
-        unsigned int pll_lock : 1;	/* PLL Lock Interrupt Status */
-        unsigned int pll_unlock : 1;	/* PLL Unlock Interrupt Status */
-        unsigned int rx_start : 1;	/* RX_START Interrupt Status */
-        unsigned int rx_end : 1;	/* RX_END Interrupt Status */
-        unsigned int cca_ed_done : 1;	/* End of ED Measurement Interrupt Status */
-        unsigned int ami : 1;	/* Address Match Interrupt Status */
-        unsigned int tx_end : 1;	/* TX_END Interrupt Status */
-        unsigned int awake : 1;	/* Awake Interrupt Status */
-};
-
-#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS */
-
-#define PLL_LOCK                        0
-#define PLL_UNLOCK                      1
-#define RX_START                        2
-#define RX_END                          3
-#define CCA_ED_DONE                     4
-#define AMI                             5
-#define TX_END                          6
-#define AWAKE                           7
-
-/* Voltage Regulator Control and Status Register */
-#define VREG_CTRL                       _SFR_MEM8(0x150)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VREG_CTRL {
-        unsigned int : 2;
-        unsigned int dvdd_ok : 1;	/* DVDD Supply Voltage Valid */
-        unsigned int dvreg_ext : 1;	/* Use External DVDD Regulator */
-        unsigned int : 2;
-        unsigned int avdd_ok : 1;	/* AVDD Supply Voltage Valid */
-        unsigned int avreg_ext : 1;	/* Use External AVDD Regulator */
-};
-
-#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL)
-
-/* symbolic names */
-
-#define DVDD_INT                        0
-#define DVDD_EXT                        1
-#define AVDD_INT                        0
-#define AVDD_EXT                        1
-
-#endif /* __ASSEMBLER__ */
-
-  /* VREG_CTRL */
-
-#define DVDD_OK                         2
-#define DVREG_EXT                       3
-#define AVDD_OK                         6
-#define AVREG_EXT                       7
-
-/* Battery Monitor Control and Status Register */
-#define BATMON                          _SFR_MEM8(0x151)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BATMON {
-        unsigned int batmon_vth : 4;	/* Battery Monitor Threshold Voltage */
-        unsigned int batmon_hr : 1;	/* Battery Monitor Voltage Range */
-        unsigned int batmon_ok : 1;	/* Battery Monitor Status */
-        unsigned int bat_low_en : 1;	/* Battery Monitor Interrupt Enable */
-        unsigned int bat_low : 1;	/* Battery Monitor Interrupt Status */
-};
-
-#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON)
-
-/* symbolic names */
-
-#define BATMON_HR_DIS                   0
-#define BATMON_HR_EN                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* BATMON */
-
-#define BATMON_VTH0                     0
-#define BATMON_VTH1                     1
-#define BATMON_VTH2                     2
-#define BATMON_VTH3                     3
-#define BATMON_HR                       4
-#define BATMON_OK                       5
-#define BAT_LOW_EN                      6
-#define BAT_LOW                         7
-
-/* Crystal Oscillator Control Register */
-#define XOSC_CTRL                       _SFR_MEM8(0x152)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XOSC_CTRL {
-        unsigned int xtal_trim : 4;	/* Crystal Oscillator Load Capacitance Trimming */
-        unsigned int xtal_mode : 4;	/* Crystal Oscillator Operating Mode */
-};
-
-#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL)
-
-/* symbolic names */
-
-#define XTAL_TRIM_MIN                   0
-#define XTAL_TRIM_MAX                   15
-
-#endif /* __ASSEMBLER__ */
-
-  /* XOSC_CTRL */
-
-#define XTAL_TRIM0                      0
-#define XTAL_TRIM1                      1
-#define XTAL_TRIM2                      2
-#define XTAL_TRIM3                      3
-#define XTAL_MODE0                      4
-#define XTAL_MODE1                      5
-#define XTAL_MODE2                      6
-#define XTAL_MODE3                      7
-
-/* Channel Control Register 0 */
-#define CC_CTRL_0                       _SFR_MEM8(0x153)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_0 {
-        unsigned int cc_number : 8;	/* Channel Number */
-};
-
-#define CC_CTRL_0_struct _SFR_MEM8_STRUCT(0x153, struct __reg_CC_CTRL_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_0 */
-
-#define CC_NUMBER0                      0
-#define CC_NUMBER1                      1
-#define CC_NUMBER2                      2
-#define CC_NUMBER3                      3
-#define CC_NUMBER4                      4
-#define CC_NUMBER5                      5
-#define CC_NUMBER6                      6
-#define CC_NUMBER7                      7
-
-/* Channel Control Register 1 */
-#define CC_CTRL_1                       _SFR_MEM8(0x154)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_1 {
-        unsigned int cc_band : 4;	/* Channel Band */
-        unsigned int : 4;
-};
-
-#define CC_CTRL_1_struct _SFR_MEM8_STRUCT(0x154, struct __reg_CC_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_1 */
-
-#define CC_BAND0                        0
-#define CC_BAND1                        1
-#define CC_BAND2                        2
-#define CC_BAND3                        3
-
-/* Transceiver Receiver Sensitivity Control Register */
-#define RX_SYN                          _SFR_MEM8(0x155)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_SYN {
-        unsigned int rx_pdt_level : 4;	/* Reduce Receiver Sensitivity */
-        unsigned int : 2;
-        unsigned int rx_override : 1;	/* Receiver Override Function */
-        unsigned int rx_pdt_dis : 1;	/* Prevent Frame Reception */
-};
-
-#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN)
-
-/* symbolic names */
-
-#define RX_PDT_LEVEL_MIN                0
-#define RX_PDT_LEVEL_MAX                15
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_SYN */
-
-#define RX_PDT_LEVEL0                   0
-#define RX_PDT_LEVEL1                   1
-#define RX_PDT_LEVEL2                   2
-#define RX_PDT_LEVEL3                   3
-#define RX_OVERRIDE                     6
-#define RX_PDT_DIS                      7
-
-/* Transceiver Reduced Power Consumption Control */
-#define TRX_RPC                         _SFR_MEM8(0x156)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_RPC {
-        unsigned int : 1;
-        unsigned int ipan_rpc_en : 1;	/* Smart Receiving Mode IPAN Handling Enable */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int pll_rpc_en : 1;	/* PLL Smart Receiving Mode Enable */
-        unsigned int pdt_rpc_en : 1;	/* Smart Receiving Mode Reduced Sensitivity Enable */
-        unsigned int rx_rpc_en : 1;	/* Receiver Smart Receiving Mode Enable */
-        unsigned int rx_rpc_ctrl : 2;	/* Smart Receiving Mode Timing */
-};
-
-#define TRX_RPC_struct _SFR_MEM8_STRUCT(0x156, struct __reg_TRX_RPC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_RPC */
-
-#define IPAN_RPC_EN                     1
-#define PLL_RPC_EN                      3
-#define PDT_RPC_EN                      4
-#define RX_RPC_EN                       5
-#define RX_RPC_CTRL0                    6
-#define RX_RPC_CTRL1                    7
-
-/* Transceiver Acknowledgment Frame Control Register 1 */
-#define XAH_CTRL_1                      _SFR_MEM8(0x157)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_1 {
-        unsigned int : 1;
-        unsigned int aack_prom_mode : 1;	/* Enable Promiscuous Mode */
-        unsigned int aack_ack_time : 1;	/* Reduce Acknowledgment Time */
-        unsigned int : 1;
-        unsigned int aack_upld_res_ft : 1;	/* Process Reserved Frames */
-        unsigned int aack_fltr_res_ft : 1;	/* Filter Reserved Frames */
-        unsigned int : 2;
-};
-
-#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1)
-
-/* symbolic names */
-
-#define AACK_ACK_TIME_12_SYM            0
-#define AACK_ACK_TIME_2_SYM             1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_1 */
-
-#define AACK_PROM_MODE                  1
-#define AACK_ACK_TIME                   2
-#define AACK_UPLD_RES_FT                4
-#define AACK_FLTR_RES_FT                5
-
-/* Transceiver Filter Tuning Control Register */
-#define FTN_CTRL                        _SFR_MEM8(0x158)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_FTN_CTRL {
-        unsigned int : 7;
-        unsigned int ftn_start : 1;	/* Start Calibration Loop of Filter Tuning Network */
-};
-
-#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* FTN_CTRL */
-
-#define FTN_START                       7
-
-/* Transceiver Center Frequency Calibration Control Register */
-#define PLL_CF                          _SFR_MEM8(0x15A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_CF {
-        unsigned int : 7;
-        unsigned int pll_cf_start : 1;	/* Start Center Frequency Calibration */
-};
-
-#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_CF */
-
-#define PLL_CF_START                    7
-
-/* Transceiver Delay Cell Calibration Control Register */
-#define PLL_DCU                         _SFR_MEM8(0x15B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_DCU {
-        unsigned int : 7;
-        unsigned int pll_dcu_start : 1;	/* Start Delay Cell Calibration */
-};
-
-#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_DCU */
-
-#define PLL_DCU_START                   7
-
-/* Device Identification Register (Part Number) */
-#define PART_NUM                        _SFR_MEM8(0x15C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PART_NUM {
-        unsigned int part_num : 8;	/* Part Number */
-};
-
-#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM)
-
-/* symbolic names */
-
-#define P_RFR2                          148
-
-#endif /* __ASSEMBLER__ */
-
-  /* PART_NUM */
-
-#define PART_NUM0                       0
-#define PART_NUM1                       1
-#define PART_NUM2                       2
-#define PART_NUM3                       3
-#define PART_NUM4                       4
-#define PART_NUM5                       5
-#define PART_NUM6                       6
-#define PART_NUM7                       7
-
-/* Device Identification Register (Version Number) */
-#define VERSION_NUM                     _SFR_MEM8(0x15D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VERSION_NUM {
-        unsigned int version_num : 8;	/* Version Number */
-};
-
-#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM)
-
-/* symbolic names */
-
-#define REV_A                           12
-#define REV_B                           1
-#define REV_C                           3
-#define REV_D                           4
-
-#endif /* __ASSEMBLER__ */
-
-  /* VERSION_NUM */
-
-#define VERSION_NUM0                    0
-#define VERSION_NUM1                    1
-#define VERSION_NUM2                    2
-#define VERSION_NUM3                    3
-#define VERSION_NUM4                    4
-#define VERSION_NUM5                    5
-#define VERSION_NUM6                    6
-#define VERSION_NUM7                    7
-
-/* Device Identification Register (Manufacture ID Low Byte) */
-#define MAN_ID_0                        _SFR_MEM8(0x15E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_0 {
-        unsigned int man_id_00 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_01 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_02 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_03 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_04 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_05 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_06 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_07 : 1;	/* Manufacturer ID (Low Byte) */
-};
-
-#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_0                    31
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_0 */
-
-#define MAN_ID_00                       0
-#define MAN_ID_01                       1
-#define MAN_ID_02                       2
-#define MAN_ID_03                       3
-#define MAN_ID_04                       4
-#define MAN_ID_05                       5
-#define MAN_ID_06                       6
-#define MAN_ID_07                       7
-
-/* Device Identification Register (Manufacture ID High Byte) */
-#define MAN_ID_1                        _SFR_MEM8(0x15F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_1 {
-        unsigned int man_id_ : 8;	/* Manufacturer ID (High Byte) */
-};
-
-#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_1                    0
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_1 */
-
-#define MAN_ID_10                       0
-#define MAN_ID_11                       1
-#define MAN_ID_12                       2
-#define MAN_ID_13                       3
-#define MAN_ID_14                       4
-#define MAN_ID_15                       5
-#define MAN_ID_16                       6
-#define MAN_ID_17                       7
-
-/* Transceiver MAC Short Address Register (Low Byte) */
-#define SHORT_ADDR_0                    _SFR_MEM8(0x160)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_0 {
-        unsigned int short_addr_00 : 1;	/* MAC Short Address */
-        unsigned int short_addr_01 : 1;	/* MAC Short Address */
-        unsigned int short_addr_02 : 1;	/* MAC Short Address */
-        unsigned int short_addr_03 : 1;	/* MAC Short Address */
-        unsigned int short_addr_04 : 1;	/* MAC Short Address */
-        unsigned int short_addr_05 : 1;	/* MAC Short Address */
-        unsigned int short_addr_06 : 1;	/* MAC Short Address */
-        unsigned int short_addr_07 : 1;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_0 */
-
-#define SHORT_ADDR_00                   0
-#define SHORT_ADDR_01                   1
-#define SHORT_ADDR_02                   2
-#define SHORT_ADDR_03                   3
-#define SHORT_ADDR_04                   4
-#define SHORT_ADDR_05                   5
-#define SHORT_ADDR_06                   6
-#define SHORT_ADDR_07                   7
-
-/* Transceiver MAC Short Address Register (High Byte) */
-#define SHORT_ADDR_1                    _SFR_MEM8(0x161)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_1 {
-        unsigned int short_addr_ : 8;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_1 */
-
-#define SHORT_ADDR_10                   0
-#define SHORT_ADDR_11                   1
-#define SHORT_ADDR_12                   2
-#define SHORT_ADDR_13                   3
-#define SHORT_ADDR_14                   4
-#define SHORT_ADDR_15                   5
-#define SHORT_ADDR_16                   6
-#define SHORT_ADDR_17                   7
-
-/* Transceiver Personal Area Network ID Register (Low Byte) */
-#define PAN_ID_0                        _SFR_MEM8(0x162)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_0 {
-        unsigned int pan_id_00 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_01 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_02 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_03 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_04 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_05 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_06 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_07 : 1;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_0 */
-
-#define PAN_ID_00                       0
-#define PAN_ID_01                       1
-#define PAN_ID_02                       2
-#define PAN_ID_03                       3
-#define PAN_ID_04                       4
-#define PAN_ID_05                       5
-#define PAN_ID_06                       6
-#define PAN_ID_07                       7
-
-/* Transceiver Personal Area Network ID Register (High Byte) */
-#define PAN_ID_1                        _SFR_MEM8(0x163)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_1 {
-        unsigned int pan_id_ : 8;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_1 */
-
-#define PAN_ID_10                       0
-#define PAN_ID_11                       1
-#define PAN_ID_12                       2
-#define PAN_ID_13                       3
-#define PAN_ID_14                       4
-#define PAN_ID_15                       5
-#define PAN_ID_16                       6
-#define PAN_ID_17                       7
-
-/* Transceiver MAC IEEE Address Register 0 */
-#define IEEE_ADDR_0                     _SFR_MEM8(0x164)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_0 {
-        unsigned int ieee_addr_00 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_01 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_02 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_03 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_04 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_05 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_06 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_07 : 1;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_0 */
-
-#define IEEE_ADDR_00                    0
-#define IEEE_ADDR_01                    1
-#define IEEE_ADDR_02                    2
-#define IEEE_ADDR_03                    3
-#define IEEE_ADDR_04                    4
-#define IEEE_ADDR_05                    5
-#define IEEE_ADDR_06                    6
-#define IEEE_ADDR_07                    7
-
-/* Transceiver MAC IEEE Address Register 1 */
-#define IEEE_ADDR_1                     _SFR_MEM8(0x165)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_1 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_1 */
-
-#define IEEE_ADDR_10                    0
-#define IEEE_ADDR_11                    1
-#define IEEE_ADDR_12                    2
-#define IEEE_ADDR_13                    3
-#define IEEE_ADDR_14                    4
-#define IEEE_ADDR_15                    5
-#define IEEE_ADDR_16                    6
-#define IEEE_ADDR_17                    7
-
-/* Transceiver MAC IEEE Address Register 2 */
-#define IEEE_ADDR_2                     _SFR_MEM8(0x166)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_2 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_2 */
-
-#define IEEE_ADDR_20                    0
-#define IEEE_ADDR_21                    1
-#define IEEE_ADDR_22                    2
-#define IEEE_ADDR_23                    3
-#define IEEE_ADDR_24                    4
-#define IEEE_ADDR_25                    5
-#define IEEE_ADDR_26                    6
-#define IEEE_ADDR_27                    7
-
-/* Transceiver MAC IEEE Address Register 3 */
-#define IEEE_ADDR_3                     _SFR_MEM8(0x167)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_3 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_3 */
-
-#define IEEE_ADDR_30                    0
-#define IEEE_ADDR_31                    1
-#define IEEE_ADDR_32                    2
-#define IEEE_ADDR_33                    3
-#define IEEE_ADDR_34                    4
-#define IEEE_ADDR_35                    5
-#define IEEE_ADDR_36                    6
-#define IEEE_ADDR_37                    7
-
-/* Transceiver MAC IEEE Address Register 4 */
-#define IEEE_ADDR_4                     _SFR_MEM8(0x168)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_4 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_4 */
-
-#define IEEE_ADDR_40                    0
-#define IEEE_ADDR_41                    1
-#define IEEE_ADDR_42                    2
-#define IEEE_ADDR_43                    3
-#define IEEE_ADDR_44                    4
-#define IEEE_ADDR_45                    5
-#define IEEE_ADDR_46                    6
-#define IEEE_ADDR_47                    7
-
-/* Transceiver MAC IEEE Address Register 5 */
-#define IEEE_ADDR_5                     _SFR_MEM8(0x169)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_5 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_5 */
-
-#define IEEE_ADDR_50                    0
-#define IEEE_ADDR_51                    1
-#define IEEE_ADDR_52                    2
-#define IEEE_ADDR_53                    3
-#define IEEE_ADDR_54                    4
-#define IEEE_ADDR_55                    5
-#define IEEE_ADDR_56                    6
-#define IEEE_ADDR_57                    7
-
-/* Transceiver MAC IEEE Address Register 6 */
-#define IEEE_ADDR_6                     _SFR_MEM8(0x16A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_6 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_6 */
-
-#define IEEE_ADDR_60                    0
-#define IEEE_ADDR_61                    1
-#define IEEE_ADDR_62                    2
-#define IEEE_ADDR_63                    3
-#define IEEE_ADDR_64                    4
-#define IEEE_ADDR_65                    5
-#define IEEE_ADDR_66                    6
-#define IEEE_ADDR_67                    7
-
-/* Transceiver MAC IEEE Address Register 7 */
-#define IEEE_ADDR_7                     _SFR_MEM8(0x16B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_7 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_7 */
-
-#define IEEE_ADDR_70                    0
-#define IEEE_ADDR_71                    1
-#define IEEE_ADDR_72                    2
-#define IEEE_ADDR_73                    3
-#define IEEE_ADDR_74                    4
-#define IEEE_ADDR_75                    5
-#define IEEE_ADDR_76                    6
-#define IEEE_ADDR_77                    7
-
-/* Transceiver Extended Operating Mode Control Register */
-#define XAH_CTRL_0                      _SFR_MEM8(0x16C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_0 {
-        unsigned int slotted_operation : 1;	/* Set Slotted Acknowledgment */
-        unsigned int max_csma_retries : 3;	/* Maximum Number of CSMA-CA Procedure Repetition Attempts */
-        unsigned int max_frame_retries : 4;	/* Maximum Number of Frame Re-transmission Attempts */
-};
-
-#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0)
-
-/* symbolic names */
-
-#define SLOTTED_OP_DIS                  0
-#define SLOTTED_OP_EN                   1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_0 */
-
-#define SLOTTED_OPERATION               0
-#define MAX_CSMA_RETRIES0               1
-#define MAX_CSMA_RETRIES1               2
-#define MAX_CSMA_RETRIES2               3
-#define MAX_FRAME_RETRIES0              4
-#define MAX_FRAME_RETRIES1              5
-#define MAX_FRAME_RETRIES2              6
-#define MAX_FRAME_RETRIES3              7
-
-/* Transceiver CSMA-CA Random Number Generator Seed Register */
-#define CSMA_SEED_0                     _SFR_MEM8(0x16D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_0 {
-        unsigned int csma_seed_00 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_01 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_02 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_03 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_04 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_05 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_06 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_07 : 1;	/* Seed Value for CSMA Random Number Generator */
-};
-
-#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_0 */
-
-#define CSMA_SEED_00                    0
-#define CSMA_SEED_01                    1
-#define CSMA_SEED_02                    2
-#define CSMA_SEED_03                    3
-#define CSMA_SEED_04                    4
-#define CSMA_SEED_05                    5
-#define CSMA_SEED_06                    6
-#define CSMA_SEED_07                    7
-
-/* Transceiver Acknowledgment Frame Control Register 2 */
-#define CSMA_SEED_1                     _SFR_MEM8(0x16E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_1 {
-        unsigned int csma_seed_1 : 3;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int aack_i_am_coord : 1;	/* Set Personal Area Network Coordinator */
-        unsigned int aack_dis_ack : 1;	/* Disable Acknowledgment Frame Transmission */
-        unsigned int aack_set_pd : 1;	/* Set Frame Pending Sub-field */
-        unsigned int aack_fvn_mode : 2;	/* Acknowledgment Frame Filter Mode */
-};
-
-#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_1 */
-
-#define CSMA_SEED_10                    0
-#define CSMA_SEED_11                    1
-#define CSMA_SEED_12                    2
-#define AACK_I_AM_COORD                 3
-#define AACK_DIS_ACK                    4
-#define AACK_SET_PD                     5
-#define AACK_FVN_MODE0                  6
-#define AACK_FVN_MODE1                  7
-
-/* Transceiver CSMA-CA Back-off Exponent Control Register */
-#define CSMA_BE                         _SFR_MEM8(0x16F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_BE {
-        unsigned int min_be : 4;	/* Minimum Back-off Exponent */
-        unsigned int max_be : 4;	/* Maximum Back-off Exponent */
-};
-
-#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_BE */
-
-#define MIN_BE0                         0
-#define MIN_BE1                         1
-#define MIN_BE2                         2
-#define MIN_BE3                         3
-#define MAX_BE0                         4
-#define MAX_BE1                         5
-#define MAX_BE2                         6
-#define MAX_BE3                         7
-
-/* Transceiver Digital Test Control Register */
-#define TST_CTRL_DIGI                   _SFR_MEM8(0x176)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_CTRL_DIGI {
-        unsigned int tst_ctrl_dig : 4;	/* Digital Test Controller Register */
-        unsigned int : 4;
-};
-
-#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_CTRL_DIGI */
-
-#define TST_CTRL_DIG0                   0
-#define TST_CTRL_DIG1                   1
-#define TST_CTRL_DIG2                   2
-#define TST_CTRL_DIG3                   3
-
-/* Transceiver Received Frame Length Register */
-#define TST_RX_LENGTH                   _SFR_MEM8(0x17B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_RX_LENGTH {
-        unsigned int rx_length : 8;	/* Received Frame Length */
-};
-
-#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_RX_LENGTH */
-
-#define RX_LENGTH0                      0
-#define RX_LENGTH1                      1
-#define RX_LENGTH2                      2
-#define RX_LENGTH3                      3
-#define RX_LENGTH4                      4
-#define RX_LENGTH5                      5
-#define RX_LENGTH6                      6
-#define RX_LENGTH7                      7
-
-/* Transceiver Automatic Gain Control and Test Register */
-#define TST_AGC                         _SFR_MEM8(0x17C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_AGC {
-        unsigned int gc : 2;	/* Receiver Gain Control Word */
-        unsigned int agc_hold : 1;	/* Select AGC Hold Function */
-        unsigned int agc_off : 1;	/* Disable AGC Regulation */
-        unsigned int agc_rst : 1;	/* Reset AGC Gain */
-        unsigned int agc_hold_sel : 1;	/* Enable AGC Hold Function */
-        unsigned int : 2;
-};
-
-#define TST_AGC_struct _SFR_MEM8_STRUCT(0x17c, struct __reg_TST_AGC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_AGC */
-
-#define GC0                             0
-#define GC1                             1
-#define AGC_HOLD                        2
-#define AGC_OFF                         3
-#define AGC_RST                         4
-#define AGC_HOLD_SEL                    5
-
-/* Transceiver Sigma-Delta Modulator Control and Test Register */
-#define TST_SDM                         _SFR_MEM8(0x17D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_SDM {
-        unsigned int : 4;
-        unsigned int tx_rx_sel : 1;	/* Select Transmit/Receive Control Signal */
-        unsigned int tx_rx : 1;	/* Switch between Transmit and Receive */
-        unsigned int mod : 1;	/* Select Modulation Signal Type */
-        unsigned int mod_sel : 1;	/* Select Modulation Data Source */
-};
-
-#define TST_SDM_struct _SFR_MEM8_STRUCT(0x17d, struct __reg_TST_SDM)
-
-#endif /* __ASSEMBLER__ */
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
 
-  /* TST_SDM */
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
 
-#define TX_RX_SEL                       4
-#define TX_RX                           5
-#define MOD                             6
-#define MOD_SEL                         7
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define MUX5    3
+#define ACCH    4
+#define REFOK   5
+#define AVDDOK  7
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC8D   0
+#define ADC9D   1
+#define ADC10D  2
+#define ADC11D  3
+#define ADC12D  4
+#define ADC13D  5
+#define ADC14D  6
+#define ADC15D  7
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1C0  2
+#define COM1C1  3
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1C   5
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define WGM30   0
+#define WGM31   1
+#define COM3C0  2
+#define COM3C1  3
+#define COM3B0  4
+#define COM3B1  5
+#define COM3A0  6
+#define COM3A1  7
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define CS30    0
+#define CS31    1
+#define CS32    2
+#define WGM32   3
+#define WGM33   4
+#define ICES3   6
+#define ICNC3   7
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3C   5
+#define FOC3B   6
+#define FOC3A   7
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define WGM40   0
+#define WGM41   1
+#define COM4C0  2
+#define COM4C1  3
+#define COM4B0  4
+#define COM4B1  5
+#define COM4A0  6
+#define COM4A1  7
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define CS40    0
+#define CS41    1
+#define CS42    2
+#define WGM42   3
+#define WGM43   4
+#define ICES4   6
+#define ICNC4   7
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4C   5
+#define FOC4B   6
+#define FOC4A   7
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+#define EXCLKAMR 7
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+#define IRQ_MASK1 _SFR_MEM8(0xBE)
+#define TX_START_EN 0
+#define MAF_0_AMI_EN 1
+#define MAF_1_AMI_EN 2
+#define MAF_2_AMI_EN 3
+#define MAF_3_AMI_EN 4
+
+#define IRQ_STATUS1 _SFR_MEM8(0xBF)
+#define TX_START 0
+#define MAF_0_AMI 1
+#define MAF_1_AMI 2
+#define MAF_2_AMI 3
+#define MAF_3_AMI 4
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+#define UCPHA0  1
+#define UDORD0  2
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+#define UCSR1B  _SFR_MEM8(0xC9)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+#define UCPHA1  1
+#define UDORD1  2
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0xCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define SCRSTRLL _SFR_MEM8(0xD7)
+#define SCRSTRLL0 0
+#define SCRSTRLL1 1
+#define SCRSTRLL2 2
+#define SCRSTRLL3 3
+#define SCRSTRLL4 4
+#define SCRSTRLL5 5
+#define SCRSTRLL6 6
+#define SCRSTRLL7 7
+
+#define SCRSTRLH _SFR_MEM8(0xD8)
+#define SCRSTRLH0 0
+#define SCRSTRLH1 1
+#define SCRSTRLH2 2
+#define SCRSTRLH3 3
+#define SCRSTRLH4 4
+#define SCRSTRLH5 5
+#define SCRSTRLH6 6
+#define SCRSTRLH7 7
+
+#define SCRSTRHL _SFR_MEM8(0xD9)
+#define SCRSTRHL0 0
+#define SCRSTRHL1 1
+#define SCRSTRHL2 2
+#define SCRSTRHL3 3
+#define SCRSTRHL4 4
+#define SCRSTRHL5 5
+#define SCRSTRHL6 6
+#define SCRSTRHL7 7
+
+#define SCRSTRHH _SFR_MEM8(0xDA)
+#define SCRSTRHH0 0
+#define SCRSTRHH1 1
+#define SCRSTRHH2 2
+#define SCRSTRHH3 3
+#define SCRSTRHH4 4
+#define SCRSTRHH5 5
+#define SCRSTRHH6 6
+#define SCRSTRHH7 7
+
+#define SCCSR   _SFR_MEM8(0xDB)
+#define SCCS10  0
+#define SCCS11  1
+#define SCCS20  2
+#define SCCS21  3
+#define SCCS30  4
+#define SCCS31  5
+
+#define SCCR0   _SFR_MEM8(0xDC)
+#define SCCMP1  0
+#define SCCMP2  1
+#define SCCMP3  2
+#define SCTSE   3
+#define SCCKSEL 4
+#define SCEN    5
+#define SCMBTS  6
+#define SCRES   7
+
+#define SCCR1   _SFR_MEM8(0xDD)
+#define SCENBO  0
+#define SCEECLK 1
+#define SCCKDIV0 2
+#define SCCKDIV1 3
+#define SCCKDIV2 4
+#define SCBTSM  5
+#define Res5    6
+#define Res6    7
+
+#define SCSR    _SFR_MEM8(0xDE)
+#define SCBSY   0
+
+#define SCIRQM  _SFR_MEM8(0xDF)
+#define IRQMCP1 0
+#define IRQMCP2 1
+#define IRQMCP3 2
+#define IRQMOF  3
+#define IRQMBO  4
+
+#define SCIRQS  _SFR_MEM8(0xE0)
+#define IRQSCP1 0
+#define IRQSCP2 1
+#define IRQSCP3 2
+#define IRQSOF  3
+#define IRQSBO  4
+
+#define SCCNTLL _SFR_MEM8(0xE1)
+#define SCCNTLL0 0
+#define SCCNTLL1 1
+#define SCCNTLL2 2
+#define SCCNTLL3 3
+#define SCCNTLL4 4
+#define SCCNTLL5 5
+#define SCCNTLL6 6
+#define SCCNTLL7 7
+
+#define SCCNTLH _SFR_MEM8(0xE2)
+#define SCCNTLH0 0
+#define SCCNTLH1 1
+#define SCCNTLH2 2
+#define SCCNTLH3 3
+#define SCCNTLH4 4
+#define SCCNTLH5 5
+#define SCCNTLH6 6
+#define SCCNTLH7 7
+
+#define SCCNTHL _SFR_MEM8(0xE3)
+#define SCCNTHL0 0
+#define SCCNTHL1 1
+#define SCCNTHL2 2
+#define SCCNTHL3 3
+#define SCCNTHL4 4
+#define SCCNTHL5 5
+#define SCCNTHL6 6
+#define SCCNTHL7 7
+
+#define SCCNTHH _SFR_MEM8(0xE4)
+#define SCCNTHH0 0
+#define SCCNTHH1 1
+#define SCCNTHH2 2
+#define SCCNTHH3 3
+#define SCCNTHH4 4
+#define SCCNTHH5 5
+#define SCCNTHH6 6
+#define SCCNTHH7 7
+
+#define SCBTSRLL _SFR_MEM8(0xE5)
+#define SCBTSRLL0 0
+#define SCBTSRLL1 1
+#define SCBTSRLL2 2
+#define SCBTSRLL3 3
+#define SCBTSRLL4 4
+#define SCBTSRLL5 5
+#define SCBTSRLL6 6
+#define SCBTSRLL7 7
+
+#define SCBTSRLH _SFR_MEM8(0xE6)
+#define SCBTSRLH0 0
+#define SCBTSRLH1 1
+#define SCBTSRLH2 2
+#define SCBTSRLH3 3
+#define SCBTSRLH4 4
+#define SCBTSRLH5 5
+#define SCBTSRLH6 6
+#define SCBTSRLH7 7
+
+#define SCBTSRHL _SFR_MEM8(0xE7)
+#define SCBTSRHL0 0
+#define SCBTSRHL1 1
+#define SCBTSRHL2 2
+#define SCBTSRHL3 3
+#define SCBTSRHL4 4
+#define SCBTSRHL5 5
+#define SCBTSRHL6 6
+#define SCBTSRHL7 7
+
+#define SCBTSRHH _SFR_MEM8(0xE8)
+#define SCBTSRHH0 0
+#define SCBTSRHH1 1
+#define SCBTSRHH2 2
+#define SCBTSRHH3 3
+#define SCBTSRHH4 4
+#define SCBTSRHH5 5
+#define SCBTSRHH6 6
+#define SCBTSRHH7 7
+
+#define SCTSRLL _SFR_MEM8(0xE9)
+#define SCTSRLL0 0
+#define SCTSRLL1 1
+#define SCTSRLL2 2
+#define SCTSRLL3 3
+#define SCTSRLL4 4
+#define SCTSRLL5 5
+#define SCTSRLL6 6
+#define SCTSRLL7 7
+
+#define SCTSRLH _SFR_MEM8(0xEA)
+#define SCTSRLH0 0
+#define SCTSRLH1 1
+#define SCTSRLH2 2
+#define SCTSRLH3 3
+#define SCTSRLH4 4
+#define SCTSRLH5 5
+#define SCTSRLH6 6
+#define SCTSRLH7 7
+
+#define SCTSRHL _SFR_MEM8(0xEB)
+#define SCTSRHL0 0
+#define SCTSRHL1 1
+#define SCTSRHL2 2
+#define SCTSRHL3 3
+#define SCTSRHL4 4
+#define SCTSRHL5 5
+#define SCTSRHL6 6
+#define SCTSRHL7 7
+
+#define SCTSRHH _SFR_MEM8(0xEC)
+#define SCTSRHH0 0
+#define SCTSRHH1 1
+#define SCTSRHH2 2
+#define SCTSRHH3 3
+#define SCTSRHH4 4
+#define SCTSRHH5 5
+#define SCTSRHH6 6
+#define SCTSRHH7 7
+
+#define SCOCR3LL _SFR_MEM8(0xED)
+#define SCOCR3LL0 0
+#define SCOCR3LL1 1
+#define SCOCR3LL2 2
+#define SCOCR3LL3 3
+#define SCOCR3LL4 4
+#define SCOCR3LL5 5
+#define SCOCR3LL6 6
+#define SCOCR3LL7 7
+
+#define SCOCR3LH _SFR_MEM8(0xEE)
+#define SCOCR3LH0 0
+#define SCOCR3LH1 1
+#define SCOCR3LH2 2
+#define SCOCR3LH3 3
+#define SCOCR3LH4 4
+#define SCOCR3LH5 5
+#define SCOCR3LH6 6
+#define SCOCR3LH7 7
+
+#define SCOCR3HL _SFR_MEM8(0xEF)
+#define SCOCR3HL0 0
+#define SCOCR3HL1 1
+#define SCOCR3HL2 2
+#define SCOCR3HL3 3
+#define SCOCR3HL4 4
+#define SCOCR3HL5 5
+#define SCOCR3HL6 6
+#define SCOCR3HL7 7
+
+#define SCOCR3HH _SFR_MEM8(0xF0)
+#define SCOCR3HH0 0
+#define SCOCR3HH1 1
+#define SCOCR3HH2 2
+#define SCOCR3HH3 3
+#define SCOCR3HH4 4
+#define SCOCR3HH5 5
+#define SCOCR3HH6 6
+#define SCOCR3HH7 7
+
+#define SCOCR2LL _SFR_MEM8(0xF1)
+#define SCOCR2LL0 0
+#define SCOCR2LL1 1
+#define SCOCR2LL2 2
+#define SCOCR2LL3 3
+#define SCOCR2LL4 4
+#define SCOCR2LL5 5
+#define SCOCR2LL6 6
+#define SCOCR2LL7 7
+
+#define SCOCR2LH _SFR_MEM8(0xF2)
+#define SCOCR2LH0 0
+#define SCOCR2LH1 1
+#define SCOCR2LH2 2
+#define SCOCR2LH3 3
+#define SCOCR2LH4 4
+#define SCOCR2LH5 5
+#define SCOCR2LH6 6
+#define SCOCR2LH7 7
+
+#define SCOCR2HL _SFR_MEM8(0xF3)
+#define SCOCR2HL0 0
+#define SCOCR2HL1 1
+#define SCOCR2HL2 2
+#define SCOCR2HL3 3
+#define SCOCR2HL4 4
+#define SCOCR2HL5 5
+#define SCOCR2HL6 6
+#define SCOCR2HL7 7
+
+#define SCOCR2HH _SFR_MEM8(0xF4)
+#define SCOCR2HH0 0
+#define SCOCR2HH1 1
+#define SCOCR2HH2 2
+#define SCOCR2HH3 3
+#define SCOCR2HH4 4
+#define SCOCR2HH5 5
+#define SCOCR2HH6 6
+#define SCOCR2HH7 7
+
+#define SCOCR1LL _SFR_MEM8(0xF5)
+#define SCOCR1LL0 0
+#define SCOCR1LL1 1
+#define SCOCR1LL2 2
+#define SCOCR1LL3 3
+#define SCOCR1LL4 4
+#define SCOCR1LL5 5
+#define SCOCR1LL6 6
+#define SCOCR1LL7 7
+
+#define SCOCR1LH _SFR_MEM8(0xF6)
+#define SCOCR1LH0 0
+#define SCOCR1LH1 1
+#define SCOCR1LH2 2
+#define SCOCR1LH3 3
+#define SCOCR1LH4 4
+#define SCOCR1LH5 5
+#define SCOCR1LH6 6
+#define SCOCR1LH7 7
+
+#define SCOCR1HL _SFR_MEM8(0xF7)
+#define SCOCR1HL0 0
+#define SCOCR1HL1 1
+#define SCOCR1HL2 2
+#define SCOCR1HL3 3
+#define SCOCR1HL4 4
+#define SCOCR1HL5 5
+#define SCOCR1HL6 6
+#define SCOCR1HL7 7
+
+#define SCOCR1HH _SFR_MEM8(0xF8)
+#define SCOCR1HH0 0
+#define SCOCR1HH1 1
+#define SCOCR1HH2 2
+#define SCOCR1HH3 3
+#define SCOCR1HH4 4
+#define SCOCR1HH5 5
+#define SCOCR1HH6 6
+#define SCOCR1HH7 7
+
+#define SCTSTRLL _SFR_MEM8(0xF9)
+#define SCTSTRLL0 0
+#define SCTSTRLL1 1
+#define SCTSTRLL2 2
+#define SCTSTRLL3 3
+#define SCTSTRLL4 4
+#define SCTSTRLL5 5
+#define SCTSTRLL6 6
+#define SCTSTRLL7 7
+
+#define SCTSTRLH _SFR_MEM8(0xFA)
+#define SCTSTRLH0 0
+#define SCTSTRLH1 1
+#define SCTSTRLH2 2
+#define SCTSTRLH3 3
+#define SCTSTRLH4 4
+#define SCTSTRLH5 5
+#define SCTSTRLH6 6
+#define SCTSTRLH7 7
+
+#define SCTSTRHL _SFR_MEM8(0xFB)
+#define SCTSTRHL0 0
+#define SCTSTRHL1 1
+#define SCTSTRHL2 2
+#define SCTSTRHL3 3
+#define SCTSTRHL4 4
+#define SCTSTRHL5 5
+#define SCTSTRHL6 6
+#define SCTSTRHL7 7
+
+#define SCTSTRHH _SFR_MEM8(0xFC)
+#define SCTSTRHH0 0
+#define SCTSTRHH1 1
+#define SCTSTRHH2 2
+#define SCTSTRHH3 3
+#define SCTSTRHH4 4
+#define SCTSTRHH5 5
+#define SCTSTRHH6 6
+#define SCTSTRHH7 7
+
+/* Reserved [0xFD..0x10B] */
+
+#define MAFCR0  _SFR_MEM8(0x10C)
+#define MAF0EN  0
+#define MAF1EN  1
+#define MAF2EN  2
+#define MAF3EN  3
+
+#define MAFCR1  _SFR_MEM8(0x10D)
+#define AACK_0_I_AM_COORD 0
+#define AACK_0_SET_PD 1
+#define AACK_1_I_AM_COORD 2
+#define AACK_1_SET_PD 3
+#define AACK_2_I_AM_COORD 4
+#define AACK_2_SET_PD 5
+#define AACK_3_I_AM_COORD 6
+#define AACK_3_SET_PD 7
+
+#define MAFSA0L _SFR_MEM8(0x10E)
+#define MAFSA0L0 0
+#define MAFSA0L1 1
+#define MAFSA0L2 2
+#define MAFSA0L3 3
+#define MAFSA0L4 4
+#define MAFSA0L5 5
+#define MAFSA0L6 6
+#define MAFSA0L7 7
+
+#define MAFSA0H _SFR_MEM8(0x10F)
+#define MAFSA0H0 0
+#define MAFSA0H1 1
+#define MAFSA0H2 2
+#define MAFSA0H3 3
+#define MAFSA0H4 4
+#define MAFSA0H5 5
+#define MAFSA0H6 6
+#define MAFSA0H7 7
+
+#define MAFPA0L _SFR_MEM8(0x110)
+#define MAFPA0L0 0
+#define MAFPA0L1 1
+#define MAFPA0L2 2
+#define MAFPA0L3 3
+#define MAFPA0L4 4
+#define MAFPA0L5 5
+#define MAFPA0L6 6
+#define MAFPA0L7 7
+
+#define MAFPA0H _SFR_MEM8(0x111)
+#define MAFPA0H0 0
+#define MAFPA0H1 1
+#define MAFPA0H2 2
+#define MAFPA0H3 3
+#define MAFPA0H4 4
+#define MAFPA0H5 5
+#define MAFPA0H6 6
+#define MAFPA0H7 7
+
+#define MAFSA1L _SFR_MEM8(0x112)
+#define MAFSA1L0 0
+#define MAFSA1L1 1
+#define MAFSA1L2 2
+#define MAFSA1L3 3
+#define MAFSA1L4 4
+#define MAFSA1L5 5
+#define MAFSA1L6 6
+#define MAFSA1L7 7
+
+#define MAFSA1H _SFR_MEM8(0x113)
+#define MAFSA1H0 0
+#define MAFSA1H1 1
+#define MAFSA1H2 2
+#define MAFSA1H3 3
+#define MAFSA1H4 4
+#define MAFSA1H5 5
+#define MAFSA1H6 6
+#define MAFSA1H7 7
+
+#define MAFPA1L _SFR_MEM8(0x114)
+#define MAFPA1L0 0
+#define MAFPA1L1 1
+#define MAFPA1L2 2
+#define MAFPA1L3 3
+#define MAFPA1L4 4
+#define MAFPA1L5 5
+#define MAFPA1L6 6
+#define MAFPA1L7 7
+
+#define MAFPA1H _SFR_MEM8(0x115)
+#define MAFPA1H0 0
+#define MAFPA1H1 1
+#define MAFPA1H2 2
+#define MAFPA1H3 3
+#define MAFPA1H4 4
+#define MAFPA1H5 5
+#define MAFPA1H6 6
+#define MAFPA1H7 7
+
+#define MAFSA2L _SFR_MEM8(0x116)
+#define MAFSA2L0 0
+#define MAFSA2L1 1
+#define MAFSA2L2 2
+#define MAFSA2L3 3
+#define MAFSA2L4 4
+#define MAFSA2L5 5
+#define MAFSA2L6 6
+#define MAFSA2L7 7
+
+#define MAFSA2H _SFR_MEM8(0x117)
+#define MAFSA2H0 0
+#define MAFSA2H1 1
+#define MAFSA2H2 2
+#define MAFSA2H3 3
+#define MAFSA2H4 4
+#define MAFSA2H5 5
+#define MAFSA2H6 6
+#define MAFSA2H7 7
+
+#define MAFPA2L _SFR_MEM8(0x118)
+#define MAFPA2L0 0
+#define MAFPA2L1 1
+#define MAFPA2L2 2
+#define MAFPA2L3 3
+#define MAFPA2L4 4
+#define MAFPA2L5 5
+#define MAFPA2L6 6
+#define MAFPA2L7 7
+
+#define MAFPA2H _SFR_MEM8(0x119)
+#define MAFPA2H0 0
+#define MAFPA2H1 1
+#define MAFPA2H2 2
+#define MAFPA2H3 3
+#define MAFPA2H4 4
+#define MAFPA2H5 5
+#define MAFPA2H6 6
+#define MAFPA2H7 7
+
+#define MAFSA3L _SFR_MEM8(0x11A)
+#define MAFSA3L0 0
+#define MAFSA3L1 1
+#define MAFSA3L2 2
+#define MAFSA3L3 3
+#define MAFSA3L4 4
+#define MAFSA3L5 5
+#define MAFSA3L6 6
+#define MAFSA3L7 7
+
+#define MAFSA3H _SFR_MEM8(0x11B)
+#define MAFSA3H0 0
+#define MAFSA3H1 1
+#define MAFSA3H2 2
+#define MAFSA3H3 3
+#define MAFSA3H4 4
+#define MAFSA3H5 5
+#define MAFSA3H6 6
+#define MAFSA3H7 7
+
+#define MAFPA3L _SFR_MEM8(0x11C)
+#define MAFPA3L0 0
+#define MAFPA3L1 1
+#define MAFPA3L2 2
+#define MAFPA3L3 3
+#define MAFPA3L4 4
+#define MAFPA3L5 5
+#define MAFPA3L6 6
+#define MAFPA3L7 7
+
+#define MAFPA3H _SFR_MEM8(0x11D)
+#define MAFPA3H0 0
+#define MAFPA3H1 1
+#define MAFPA3H2 2
+#define MAFPA3H3 3
+#define MAFPA3H4 4
+#define MAFPA3H5 5
+#define MAFPA3H6 6
+#define MAFPA3H7 7
+
+/* Reserved [0x11E..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define WGM50   0
+#define WGM51   1
+#define COM5C0  2
+#define COM5C1  3
+#define COM5B0  4
+#define COM5B1  5
+#define COM5A0  6
+#define COM5A1  7
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define CS50    0
+#define CS51    1
+#define CS52    2
+#define WGM52   3
+#define WGM53   4
+#define ICES5   6
+#define ICNC5   7
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5C   5
+#define FOC5B   6
+#define FOC5A   7
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E] */
+
+#define LLCR    _SFR_MEM8(0x12F)
+#define LLENCAL 0
+#define LLSHORT 1
+#define LLTCO   2
+#define LLCAL   3
+#define LLCOMP  4
+#define LLDONE  5
+
+#define LLDRL   _SFR_MEM8(0x130)
+#define LLDRL0  0
+#define LLDRL1  1
+#define LLDRL2  2
+#define LLDRL3  3
+
+#define LLDRH   _SFR_MEM8(0x131)
+#define LLDRH0  0
+#define LLDRH1  1
+#define LLDRH2  2
+#define LLDRH3  3
+#define LLDRH4  4
+
+#define DRTRAM3 _SFR_MEM8(0x132)
+#define ENDRT   4
+#define DRTSWOK 5
+
+#define DRTRAM2 _SFR_MEM8(0x133)
+
+#define DRTRAM1 _SFR_MEM8(0x134)
+
+#define DRTRAM0 _SFR_MEM8(0x135)
+
+#define DPDS0   _SFR_MEM8(0x136)
+#define PBDRV0  0
+#define PBDRV1  1
+#define PDDRV0  2
+#define PDDRV1  3
+#define PEDRV0  4
+#define PEDRV1  5
+#define PFDRV0  6
+#define PFDRV1  7
+
+#define DPDS1   _SFR_MEM8(0x137)
+#define PGDRV0  0
+#define PGDRV1  1
+
+#define PARCR   _SFR_MEM8(0x138)
+#define PARUFI  0
+#define PARDFI  1
+#define PALTU0  2
+#define PALTU1  3
+#define PALTU2  4
+#define PALTD0  5
+#define PALTD1  6
+#define PALTD2  7
+
+#define TRXPR   _SFR_MEM8(0x139)
+#define TRXRST  0
+#define SLPTR   1
+
+/* Reserved [0x13A..0x13B] */
+
+#define AES_CTRL _SFR_MEM8(0x13C)
+#define AES_IM  2
+#define AES_DIR 3
+#define AES_MODE 5
+#define AES_REQUEST 7
+
+#define AES_STATUS _SFR_MEM8(0x13D)
+#define AES_DONE 0
+#define AES_ER  7
+
+#define AES_STATE _SFR_MEM8(0x13E)
+#define AES_STATE0 0
+#define AES_STATE1 1
+#define AES_STATE2 2
+#define AES_STATE3 3
+#define AES_STATE4 4
+#define AES_STATE5 5
+#define AES_STATE6 6
+#define AES_STATE7 7
+
+#define AES_KEY _SFR_MEM8(0x13F)
+#define AES_KEY0 0
+#define AES_KEY1 1
+#define AES_KEY2 2
+#define AES_KEY3 3
+#define AES_KEY4 4
+#define AES_KEY5 5
+#define AES_KEY6 6
+#define AES_KEY7 7
+
+/* Reserved [0x140] */
+
+#define TRX_STATUS _SFR_MEM8(0x141)
+#define TRX_STATUS0 0
+#define TRX_STATUS1 1
+#define TRX_STATUS2 2
+#define TRX_STATUS3 3
+#define TRX_STATUS4 4
+#define TST_STATUS 5
+#define CCA_STATUS 6
+#define CCA_DONE 7
+
+#define TRX_STATE _SFR_MEM8(0x142)
+#define TRX_CMD0 0
+#define TRX_CMD1 1
+#define TRX_CMD2 2
+#define TRX_CMD3 3
+#define TRX_CMD4 4
+#define TRAC_STATUS0 5
+#define TRAC_STATUS1 6
+#define TRAC_STATUS2 7
+
+#define TRX_CTRL_0 _SFR_MEM8(0x143)
+#define PMU_IF_INV 4
+#define PMU_START 5
+#define PMU_EN  6
+#define Res7    7
+
+#define TRX_CTRL_1 _SFR_MEM8(0x144)
+#define PLL_TX_FLT 4
+#define TX_AUTO_CRC_ON 5
+#define IRQ_2_EXT_EN 6
+#define PA_EXT_EN 7
+
+#define PHY_TX_PWR _SFR_MEM8(0x145)
+#define TX_PWR0 0
+#define TX_PWR1 1
+#define TX_PWR2 2
+#define TX_PWR3 3
+
+#define PHY_RSSI _SFR_MEM8(0x146)
+#define RSSI0   0
+#define RSSI1   1
+#define RSSI2   2
+#define RSSI3   3
+#define RSSI4   4
+#define RND_VALUE0 5
+#define RND_VALUE1 6
+#define RX_CRC_VALID 7
+
+#define PHY_ED_LEVEL _SFR_MEM8(0x147)
+#define ED_LEVEL0 0
+#define ED_LEVEL1 1
+#define ED_LEVEL2 2
+#define ED_LEVEL3 3
+#define ED_LEVEL4 4
+#define ED_LEVEL5 5
+#define ED_LEVEL6 6
+#define ED_LEVEL7 7
+
+#define PHY_CC_CCA _SFR_MEM8(0x148)
+#define CHANNEL0 0
+#define CHANNEL1 1
+#define CHANNEL2 2
+#define CHANNEL3 3
+#define CHANNEL4 4
+#define CCA_MODE0 5
+#define CCA_MODE1 6
+#define CCA_REQUEST 7
+
+#define CCA_THRES _SFR_MEM8(0x149)
+#define CCA_ED_THRES0 0
+#define CCA_ED_THRES1 1
+#define CCA_ED_THRES2 2
+#define CCA_ED_THRES3 3
+#define CCA_CS_THRES0 4
+#define CCA_CS_THRES1 5
+#define CCA_CS_THRES2 6
+#define CCA_CS_THRES3 7
+
+#define RX_CTRL _SFR_MEM8(0x14A)
+#define PDT_THRES0 0
+#define PDT_THRES1 1
+#define PDT_THRES2 2
+#define PDT_THRES3 3
+
+#define SFD_VALUE _SFR_MEM8(0x14B)
+#define SFD_VALUE0 0
+#define SFD_VALUE1 1
+#define SFD_VALUE2 2
+#define SFD_VALUE3 3
+#define SFD_VALUE4 4
+#define SFD_VALUE5 5
+#define SFD_VALUE6 6
+#define SFD_VALUE7 7
+
+#define TRX_CTRL_2 _SFR_MEM8(0x14C)
+#define OQPSK_DATA_RATE0 0
+#define OQPSK_DATA_RATE1 1
+#define RX_SAFE_MODE 7
+
+#define ANT_DIV _SFR_MEM8(0x14D)
+#define ANT_CTRL0 0
+#define ANT_CTRL1 1
+#define ANT_EXT_SW_EN 2
+#define ANT_DIV_EN 3
+#define ANT_SEL 7
+
+#define IRQ_MASK _SFR_MEM8(0x14E)
+#define PLL_LOCK_EN 0
+#define PLL_UNLOCK_EN 1
+#define RX_START_EN 2
+#define RX_END_EN 3
+#define CCA_ED_DONE_EN 4
+#define AMI_EN  5
+#define TX_END_EN 6
+#define AWAKE_EN 7
+
+#define IRQ_STATUS _SFR_MEM8(0x14F)
+#define PLL_LOCK 0
+#define PLL_UNLOCK 1
+#define RX_START 2
+#define RX_END  3
+#define CCA_ED_DONE 4
+#define AMI     5
+#define TX_END  6
+#define AWAKE   7
+
+#define VREG_CTRL _SFR_MEM8(0x150)
+#define DVDD_OK 2
+#define DVREG_EXT 3
+#define AVDD_OK 6
+#define AVREG_EXT 7
+
+#define BATMON  _SFR_MEM8(0x151)
+#define BATMON_VTH0 0
+#define BATMON_VTH1 1
+#define BATMON_VTH2 2
+#define BATMON_VTH3 3
+#define BATMON_HR 4
+#define BATMON_OK 5
+#define BAT_LOW_EN 6
+#define BAT_LOW 7
+
+#define XOSC_CTRL _SFR_MEM8(0x152)
+#define XTAL_TRIM0 0
+#define XTAL_TRIM1 1
+#define XTAL_TRIM2 2
+#define XTAL_TRIM3 3
+#define XTAL_MODE0 4
+#define XTAL_MODE1 5
+#define XTAL_MODE2 6
+#define XTAL_MODE3 7
+
+#define CC_CTRL_0 _SFR_MEM8(0x153)
+#define CC_NUMBER0 0
+#define CC_NUMBER1 1
+#define CC_NUMBER2 2
+#define CC_NUMBER3 3
+#define CC_NUMBER4 4
+#define CC_NUMBER5 5
+#define CC_NUMBER6 6
+#define CC_NUMBER7 7
+
+#define CC_CTRL_1 _SFR_MEM8(0x154)
+#define CC_BAND0 0
+#define CC_BAND1 1
+#define CC_BAND2 2
+#define CC_BAND3 3
+
+#define RX_SYN  _SFR_MEM8(0x155)
+#define RX_PDT_LEVEL0 0
+#define RX_PDT_LEVEL1 1
+#define RX_PDT_LEVEL2 2
+#define RX_PDT_LEVEL3 3
+#define RX_OVERRIDE 6
+#define RX_PDT_DIS 7
+
+#define TRX_RPC _SFR_MEM8(0x156)
+#define XAH_RPC_EN 0
+#define IPAN_RPC_EN 1
+#define PLL_RPC_EN 3
+#define PDT_RPC_EN 4
+#define RX_RPC_EN 5
+#define RX_RPC_CTRL0 6
+#define RX_RPC_CTRL1 7
+
+#define XAH_CTRL_1 _SFR_MEM8(0x157)
+#define AACK_PROM_MODE 1
+#define AACK_ACK_TIME 2
+#define AACK_UPLD_RES_FT 4
+#define AACK_FLTR_RES_FT 5
+
+#define FTN_CTRL _SFR_MEM8(0x158)
+#define FTN_START 7
+
+/* Reserved [0x159] */
+
+#define PLL_CF  _SFR_MEM8(0x15A)
+#define PLL_CF_START 7
+
+#define PLL_DCU _SFR_MEM8(0x15B)
+#define PLL_DCU_START 7
+
+#define PART_NUM _SFR_MEM8(0x15C)
+#define PART_NUM0 0
+#define PART_NUM1 1
+#define PART_NUM2 2
+#define PART_NUM3 3
+#define PART_NUM4 4
+#define PART_NUM5 5
+#define PART_NUM6 6
+#define PART_NUM7 7
+
+#define VERSION_NUM _SFR_MEM8(0x15D)
+#define VERSION_NUM0 0
+#define VERSION_NUM1 1
+#define VERSION_NUM2 2
+#define VERSION_NUM3 3
+#define VERSION_NUM4 4
+#define VERSION_NUM5 5
+#define VERSION_NUM6 6
+#define VERSION_NUM7 7
+
+#define MAN_ID_0 _SFR_MEM8(0x15E)
+#define MAN_ID_00 0
+#define MAN_ID_01 1
+#define MAN_ID_02 2
+#define MAN_ID_03 3
+#define MAN_ID_04 4
+#define MAN_ID_05 5
+#define MAN_ID_06 6
+#define MAN_ID_07 7
+
+#define MAN_ID_1 _SFR_MEM8(0x15F)
+#define MAN_ID_10 0
+#define MAN_ID_11 1
+#define MAN_ID_12 2
+#define MAN_ID_13 3
+#define MAN_ID_14 4
+#define MAN_ID_15 5
+#define MAN_ID_16 6
+#define MAN_ID_17 7
+
+#define SHORT_ADDR_0 _SFR_MEM8(0x160)
+#define SHORT_ADDR_00 0
+#define SHORT_ADDR_01 1
+#define SHORT_ADDR_02 2
+#define SHORT_ADDR_03 3
+#define SHORT_ADDR_04 4
+#define SHORT_ADDR_05 5
+#define SHORT_ADDR_06 6
+#define SHORT_ADDR_07 7
+
+#define SHORT_ADDR_1 _SFR_MEM8(0x161)
+#define SHORT_ADDR_10 0
+#define SHORT_ADDR_11 1
+#define SHORT_ADDR_12 2
+#define SHORT_ADDR_13 3
+#define SHORT_ADDR_14 4
+#define SHORT_ADDR_15 5
+#define SHORT_ADDR_16 6
+#define SHORT_ADDR_17 7
+
+#define PAN_ID_0 _SFR_MEM8(0x162)
+#define PAN_ID_00 0
+#define PAN_ID_01 1
+#define PAN_ID_02 2
+#define PAN_ID_03 3
+#define PAN_ID_04 4
+#define PAN_ID_05 5
+#define PAN_ID_06 6
+#define PAN_ID_07 7
+
+#define PAN_ID_1 _SFR_MEM8(0x163)
+#define PAN_ID_10 0
+#define PAN_ID_11 1
+#define PAN_ID_12 2
+#define PAN_ID_13 3
+#define PAN_ID_14 4
+#define PAN_ID_15 5
+#define PAN_ID_16 6
+#define PAN_ID_17 7
+
+#define IEEE_ADDR_0 _SFR_MEM8(0x164)
+#define IEEE_ADDR_00 0
+#define IEEE_ADDR_01 1
+#define IEEE_ADDR_02 2
+#define IEEE_ADDR_03 3
+#define IEEE_ADDR_04 4
+#define IEEE_ADDR_05 5
+#define IEEE_ADDR_06 6
+#define IEEE_ADDR_07 7
+
+#define IEEE_ADDR_1 _SFR_MEM8(0x165)
+#define IEEE_ADDR_10 0
+#define IEEE_ADDR_11 1
+#define IEEE_ADDR_12 2
+#define IEEE_ADDR_13 3
+#define IEEE_ADDR_14 4
+#define IEEE_ADDR_15 5
+#define IEEE_ADDR_16 6
+#define IEEE_ADDR_17 7
+
+#define IEEE_ADDR_2 _SFR_MEM8(0x166)
+#define IEEE_ADDR_20 0
+#define IEEE_ADDR_21 1
+#define IEEE_ADDR_22 2
+#define IEEE_ADDR_23 3
+#define IEEE_ADDR_24 4
+#define IEEE_ADDR_25 5
+#define IEEE_ADDR_26 6
+#define IEEE_ADDR_27 7
+
+#define IEEE_ADDR_3 _SFR_MEM8(0x167)
+#define IEEE_ADDR_30 0
+#define IEEE_ADDR_31 1
+#define IEEE_ADDR_32 2
+#define IEEE_ADDR_33 3
+#define IEEE_ADDR_34 4
+#define IEEE_ADDR_35 5
+#define IEEE_ADDR_36 6
+#define IEEE_ADDR_37 7
+
+#define IEEE_ADDR_4 _SFR_MEM8(0x168)
+#define IEEE_ADDR_40 0
+#define IEEE_ADDR_41 1
+#define IEEE_ADDR_42 2
+#define IEEE_ADDR_43 3
+#define IEEE_ADDR_44 4
+#define IEEE_ADDR_45 5
+#define IEEE_ADDR_46 6
+#define IEEE_ADDR_47 7
+
+#define IEEE_ADDR_5 _SFR_MEM8(0x169)
+#define IEEE_ADDR_50 0
+#define IEEE_ADDR_51 1
+#define IEEE_ADDR_52 2
+#define IEEE_ADDR_53 3
+#define IEEE_ADDR_54 4
+#define IEEE_ADDR_55 5
+#define IEEE_ADDR_56 6
+#define IEEE_ADDR_57 7
+
+#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
+#define IEEE_ADDR_60 0
+#define IEEE_ADDR_61 1
+#define IEEE_ADDR_62 2
+#define IEEE_ADDR_63 3
+#define IEEE_ADDR_64 4
+#define IEEE_ADDR_65 5
+#define IEEE_ADDR_66 6
+#define IEEE_ADDR_67 7
+
+#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
+#define IEEE_ADDR_70 0
+#define IEEE_ADDR_71 1
+#define IEEE_ADDR_72 2
+#define IEEE_ADDR_73 3
+#define IEEE_ADDR_74 4
+#define IEEE_ADDR_75 5
+#define IEEE_ADDR_76 6
+#define IEEE_ADDR_77 7
+
+#define XAH_CTRL_0 _SFR_MEM8(0x16C)
+#define SLOTTED_OPERATION 0
+#define MAX_CSMA_RETRIES0 1
+#define MAX_CSMA_RETRIES1 2
+#define MAX_CSMA_RETRIES2 3
+#define MAX_FRAME_RETRIES0 4
+#define MAX_FRAME_RETRIES1 5
+#define MAX_FRAME_RETRIES2 6
+#define MAX_FRAME_RETRIES3 7
+
+#define CSMA_SEED_0 _SFR_MEM8(0x16D)
+#define CSMA_SEED_00 0
+#define CSMA_SEED_01 1
+#define CSMA_SEED_02 2
+#define CSMA_SEED_03 3
+#define CSMA_SEED_04 4
+#define CSMA_SEED_05 5
+#define CSMA_SEED_06 6
+#define CSMA_SEED_07 7
+
+#define CSMA_SEED_1 _SFR_MEM8(0x16E)
+#define CSMA_SEED_10 0
+#define CSMA_SEED_11 1
+#define CSMA_SEED_12 2
+#define AACK_I_AM_COORD 3
+#define AACK_DIS_ACK 4
+#define AACK_SET_PD 5
+#define AACK_FVN_MODE0 6
+#define AACK_FVN_MODE1 7
+
+#define CSMA_BE _SFR_MEM8(0x16F)
+#define MIN_BE0 0
+#define MIN_BE1 1
+#define MIN_BE2 2
+#define MIN_BE3 3
+#define MAX_BE0 4
+#define MAX_BE1 5
+#define MAX_BE2 6
+#define MAX_BE3 7
+
+/* Reserved [0x170..0x175] */
+
+#define TST_CTRL_DIGI _SFR_MEM8(0x176)
+#define TST_CTRL_DIG0 0
+#define TST_CTRL_DIG1 1
+#define TST_CTRL_DIG2 2
+#define TST_CTRL_DIG3 3
+
+/* Reserved [0x177..0x17A] */
+
+#define TST_RX_LENGTH _SFR_MEM8(0x17B)
+#define RX_LENGTH0 0
+#define RX_LENGTH1 1
+#define RX_LENGTH2 2
+#define RX_LENGTH3 3
+#define RX_LENGTH4 4
+#define RX_LENGTH5 5
+#define RX_LENGTH6 6
+#define RX_LENGTH7 7
+
+/* Reserved [0x17C..0x17F] */
+
+#define TRXFBST _SFR_MEM8(0x180)
 
-/* Start of frame buffer */
-#define TRXFBST                         _SFR_MEM8(0x180)
+/* Reserved [0x181..0x1FE] */
 
-  /* TRXFBST */
+#define TRXFBEND _SFR_MEM8(0x1FF)
 
-#define TRXFBST0                        0
-#define TRXFBST1                        1
-#define TRXFBST2                        2
-#define TRXFBST3                        3
-#define TRXFBST4                        4
-#define TRXFBST5                        5
-#define TRXFBST6                        6
-#define TRXFBST7                        7
 
-/* End of frame buffer */
-#define TRXFBEND                        _SFR_MEM8(0x1FF)
 
-  /* TRXFBEND */
+/* Values and associated defines */
 
-#define TRXFBEND0                       0
-#define TRXFBEND1                       1
-#define TRXFBEND2                       2
-#define TRXFBEND3                       3
-#define TRXFBEND4                       4
-#define TRXFBEND5                       5
-#define TRXFBEND6                       6
-#define TRXFBEND7                       7
 
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
-
-#define _VECTORS_SIZE                  308
-
 /* External Interrupt Request 0 */
-#define INT0_vect                       _VECTOR(1)
-#define INT0_vect_num                   1
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
 
 /* External Interrupt Request 1 */
-#define INT1_vect                       _VECTOR(2)
-#define INT1_vect_num                   2
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
 
 /* External Interrupt Request 2 */
-#define INT2_vect                       _VECTOR(3)
-#define INT2_vect_num                   3
+#define INT2_vect            _VECTOR(3)
+#define INT2_vect_num        3
 
 /* External Interrupt Request 3 */
-#define INT3_vect                       _VECTOR(4)
-#define INT3_vect_num                   4
+#define INT3_vect            _VECTOR(4)
+#define INT3_vect_num        4
 
 /* External Interrupt Request 4 */
-#define INT4_vect                       _VECTOR(5)
-#define INT4_vect_num                   5
+#define INT4_vect            _VECTOR(5)
+#define INT4_vect_num        5
 
 /* External Interrupt Request 5 */
-#define INT5_vect                       _VECTOR(6)
-#define INT5_vect_num                   6
+#define INT5_vect            _VECTOR(6)
+#define INT5_vect_num        6
 
 /* External Interrupt Request 6 */
-#define INT6_vect                       _VECTOR(7)
-#define INT6_vect_num                   7
+#define INT6_vect            _VECTOR(7)
+#define INT6_vect_num        7
 
 /* External Interrupt Request 7 */
-#define INT7_vect                       _VECTOR(8)
-#define INT7_vect_num                   8
+#define INT7_vect            _VECTOR(8)
+#define INT7_vect_num        8
 
 /* Pin Change Interrupt Request 0 */
-#define PCINT0_vect                     _VECTOR(9)
-#define PCINT0_vect_num                 9
+#define PCINT0_vect            _VECTOR(9)
+#define PCINT0_vect_num        9
 
 /* Pin Change Interrupt Request 1 */
-#define PCINT1_vect                     _VECTOR(10)
-#define PCINT1_vect_num                 10
+#define PCINT1_vect            _VECTOR(10)
+#define PCINT1_vect_num        10
 
 /* Pin Change Interrupt Request 2 */
-#define PCINT2_vect                     _VECTOR(11)
-#define PCINT2_vect_num                 11
+#define PCINT2_vect            _VECTOR(11)
+#define PCINT2_vect_num        11
 
 /* Watchdog Time-out Interrupt */
-#define WDT_vect                        _VECTOR(12)
-#define WDT_vect_num                    12
+#define WDT_vect            _VECTOR(12)
+#define WDT_vect_num        12
 
 /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect               _VECTOR(13)
-#define TIMER2_COMPA_vect_num           13
+#define TIMER2_COMPA_vect            _VECTOR(13)
+#define TIMER2_COMPA_vect_num        13
 
 /* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect               _VECTOR(14)
-#define TIMER2_COMPB_vect_num           14
+#define TIMER2_COMPB_vect            _VECTOR(14)
+#define TIMER2_COMPB_vect_num        14
 
 /* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect                 _VECTOR(15)
-#define TIMER2_OVF_vect_num             15
+#define TIMER2_OVF_vect            _VECTOR(15)
+#define TIMER2_OVF_vect_num        15
 
 /* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect                _VECTOR(16)
-#define TIMER1_CAPT_vect_num            16
+#define TIMER1_CAPT_vect            _VECTOR(16)
+#define TIMER1_CAPT_vect_num        16
 
 /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect               _VECTOR(17)
-#define TIMER1_COMPA_vect_num           17
+#define TIMER1_COMPA_vect            _VECTOR(17)
+#define TIMER1_COMPA_vect_num        17
 
 /* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect               _VECTOR(18)
-#define TIMER1_COMPB_vect_num           18
+#define TIMER1_COMPB_vect            _VECTOR(18)
+#define TIMER1_COMPB_vect_num        18
 
 /* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect               _VECTOR(19)
-#define TIMER1_COMPC_vect_num           19
+#define TIMER1_COMPC_vect            _VECTOR(19)
+#define TIMER1_COMPC_vect_num        19
 
 /* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect                 _VECTOR(20)
-#define TIMER1_OVF_vect_num             20
+#define TIMER1_OVF_vect            _VECTOR(20)
+#define TIMER1_OVF_vect_num        20
 
 /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect               _VECTOR(21)
-#define TIMER0_COMPA_vect_num           21
+#define TIMER0_COMPA_vect            _VECTOR(21)
+#define TIMER0_COMPA_vect_num        21
 
 /* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect               _VECTOR(22)
-#define TIMER0_COMPB_vect_num           22
+#define TIMER0_COMPB_vect            _VECTOR(22)
+#define TIMER0_COMPB_vect_num        22
 
 /* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect                 _VECTOR(23)
-#define TIMER0_OVF_vect_num             23
+#define TIMER0_OVF_vect            _VECTOR(23)
+#define TIMER0_OVF_vect_num        23
 
 /* SPI Serial Transfer Complete */
-#define SPI_STC_vect                    _VECTOR(24)
-#define SPI_STC_vect_num                24
+#define SPI_STC_vect            _VECTOR(24)
+#define SPI_STC_vect_num        24
 
 /* USART0, Rx Complete */
-#define USART0_RX_vect                  _VECTOR(25)
-#define USART0_RX_vect_num              25
+#define USART0_RX_vect            _VECTOR(25)
+#define USART0_RX_vect_num        25
 
 /* USART0 Data register Empty */
-#define USART0_UDRE_vect                _VECTOR(26)
-#define USART0_UDRE_vect_num            26
+#define USART0_UDRE_vect            _VECTOR(26)
+#define USART0_UDRE_vect_num        26
 
 /* USART0, Tx Complete */
-#define USART0_TX_vect                  _VECTOR(27)
-#define USART0_TX_vect_num              27
+#define USART0_TX_vect            _VECTOR(27)
+#define USART0_TX_vect_num        27
 
 /* Analog Comparator */
-#define ANALOG_COMP_vect                _VECTOR(28)
-#define ANALOG_COMP_vect_num            28
+#define ANALOG_COMP_vect            _VECTOR(28)
+#define ANALOG_COMP_vect_num        28
 
 /* ADC Conversion Complete */
-#define ADC_vect                        _VECTOR(29)
-#define ADC_vect_num                    29
+#define ADC_vect            _VECTOR(29)
+#define ADC_vect_num        29
 
 /* EEPROM Ready */
-#define EE_READY_vect                   _VECTOR(30)
-#define EE_READY_vect_num               30
+#define EE_READY_vect            _VECTOR(30)
+#define EE_READY_vect_num        30
 
 /* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect                _VECTOR(31)
-#define TIMER3_CAPT_vect_num            31
+#define TIMER3_CAPT_vect            _VECTOR(31)
+#define TIMER3_CAPT_vect_num        31
 
 /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect               _VECTOR(32)
-#define TIMER3_COMPA_vect_num           32
+#define TIMER3_COMPA_vect            _VECTOR(32)
+#define TIMER3_COMPA_vect_num        32
 
 /* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect               _VECTOR(33)
-#define TIMER3_COMPB_vect_num           33
+#define TIMER3_COMPB_vect            _VECTOR(33)
+#define TIMER3_COMPB_vect_num        33
 
 /* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect               _VECTOR(34)
-#define TIMER3_COMPC_vect_num           34
+#define TIMER3_COMPC_vect            _VECTOR(34)
+#define TIMER3_COMPC_vect_num        34
 
 /* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect                 _VECTOR(35)
-#define TIMER3_OVF_vect_num             35
+#define TIMER3_OVF_vect            _VECTOR(35)
+#define TIMER3_OVF_vect_num        35
 
 /* USART1, Rx Complete */
-#define USART1_RX_vect                  _VECTOR(36)
-#define USART1_RX_vect_num              36
+#define USART1_RX_vect            _VECTOR(36)
+#define USART1_RX_vect_num        36
 
 /* USART1 Data register Empty */
-#define USART1_UDRE_vect                _VECTOR(37)
-#define USART1_UDRE_vect_num            37
+#define USART1_UDRE_vect            _VECTOR(37)
+#define USART1_UDRE_vect_num        37
 
 /* USART1, Tx Complete */
-#define USART1_TX_vect                  _VECTOR(38)
-#define USART1_TX_vect_num              38
+#define USART1_TX_vect            _VECTOR(38)
+#define USART1_TX_vect_num        38
 
 /* 2-wire Serial Interface */
-#define TWI_vect                        _VECTOR(39)
-#define TWI_vect_num                    39
+#define TWI_vect            _VECTOR(39)
+#define TWI_vect_num        39
 
 /* Store Program Memory Read */
-#define SPM_READY_vect                  _VECTOR(40)
-#define SPM_READY_vect_num              40
+#define SPM_READY_vect            _VECTOR(40)
+#define SPM_READY_vect_num        40
 
 /* Timer/Counter4 Capture Event */
-#define TIMER4_CAPT_vect                _VECTOR(41)
-#define TIMER4_CAPT_vect_num            41
+#define TIMER4_CAPT_vect            _VECTOR(41)
+#define TIMER4_CAPT_vect_num        41
 
 /* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPA_vect               _VECTOR(42)
-#define TIMER4_COMPA_vect_num           42
+#define TIMER4_COMPA_vect            _VECTOR(42)
+#define TIMER4_COMPA_vect_num        42
 
 /* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPB_vect               _VECTOR(43)
-#define TIMER4_COMPB_vect_num           43
+#define TIMER4_COMPB_vect            _VECTOR(43)
+#define TIMER4_COMPB_vect_num        43
 
 /* Timer/Counter4 Compare Match C */
-#define TIMER4_COMPC_vect               _VECTOR(44)
-#define TIMER4_COMPC_vect_num           44
+#define TIMER4_COMPC_vect            _VECTOR(44)
+#define TIMER4_COMPC_vect_num        44
 
 /* Timer/Counter4 Overflow */
-#define TIMER4_OVF_vect                 _VECTOR(45)
-#define TIMER4_OVF_vect_num             45
+#define TIMER4_OVF_vect            _VECTOR(45)
+#define TIMER4_OVF_vect_num        45
 
 /* Timer/Counter5 Capture Event */
-#define TIMER5_CAPT_vect                _VECTOR(46)
-#define TIMER5_CAPT_vect_num            46
+#define TIMER5_CAPT_vect            _VECTOR(46)
+#define TIMER5_CAPT_vect_num        46
 
 /* Timer/Counter5 Compare Match A */
-#define TIMER5_COMPA_vect               _VECTOR(47)
-#define TIMER5_COMPA_vect_num           47
+#define TIMER5_COMPA_vect            _VECTOR(47)
+#define TIMER5_COMPA_vect_num        47
 
 /* Timer/Counter5 Compare Match B */
-#define TIMER5_COMPB_vect               _VECTOR(48)
-#define TIMER5_COMPB_vect_num           48
+#define TIMER5_COMPB_vect            _VECTOR(48)
+#define TIMER5_COMPB_vect_num        48
 
 /* Timer/Counter5 Compare Match C */
-#define TIMER5_COMPC_vect               _VECTOR(49)
-#define TIMER5_COMPC_vect_num           49
+#define TIMER5_COMPC_vect            _VECTOR(49)
+#define TIMER5_COMPC_vect_num        49
 
 /* Timer/Counter5 Overflow */
-#define TIMER5_OVF_vect                 _VECTOR(50)
-#define TIMER5_OVF_vect_num             50
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_51_vect                _VECTOR(51)
-#define RESERVED_51_vect_num            51
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_52_vect                _VECTOR(52)
-#define RESERVED_52_vect_num            52
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_53_vect                _VECTOR(53)
-#define RESERVED_53_vect_num            53
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_54_vect                _VECTOR(54)
-#define RESERVED_54_vect_num            54
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_55_vect                _VECTOR(55)
-#define RESERVED_55_vect_num            55
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_56_vect                _VECTOR(56)
-#define RESERVED_56_vect_num            56
+#define TIMER5_OVF_vect            _VECTOR(50)
+#define TIMER5_OVF_vect_num        50
 
 /* TRX24 - PLL lock interrupt */
-#define TRX24_PLL_LOCK_vect             _VECTOR(57)
-#define TRX24_PLL_LOCK_vect_num         57
+#define TRX24_PLL_LOCK_vect            _VECTOR(57)
+#define TRX24_PLL_LOCK_vect_num        57
 
 /* TRX24 - PLL unlock interrupt */
-#define TRX24_PLL_UNLOCK_vect           _VECTOR(58)
-#define TRX24_PLL_UNLOCK_vect_num       58
+#define TRX24_PLL_UNLOCK_vect            _VECTOR(58)
+#define TRX24_PLL_UNLOCK_vect_num        58
 
 /* TRX24 - Receive start interrupt */
-#define TRX24_RX_START_vect             _VECTOR(59)
-#define TRX24_RX_START_vect_num         59
+#define TRX24_RX_START_vect            _VECTOR(59)
+#define TRX24_RX_START_vect_num        59
 
 /* TRX24 - RX_END interrupt */
-#define TRX24_RX_END_vect               _VECTOR(60)
-#define TRX24_RX_END_vect_num           60
+#define TRX24_RX_END_vect            _VECTOR(60)
+#define TRX24_RX_END_vect_num        60
 
 /* TRX24 - CCA/ED done interrupt */
-#define TRX24_CCA_ED_DONE_vect          _VECTOR(61)
-#define TRX24_CCA_ED_DONE_vect_num      61
+#define TRX24_CCA_ED_DONE_vect            _VECTOR(61)
+#define TRX24_CCA_ED_DONE_vect_num        61
 
 /* TRX24 - XAH - AMI */
-#define TRX24_XAH_AMI_vect              _VECTOR(62)
-#define TRX24_XAH_AMI_vect_num          62
+#define TRX24_XAH_AMI_vect            _VECTOR(62)
+#define TRX24_XAH_AMI_vect_num        62
 
 /* TRX24 - TX_END interrupt */
-#define TRX24_TX_END_vect               _VECTOR(63)
-#define TRX24_TX_END_vect_num           63
+#define TRX24_TX_END_vect            _VECTOR(63)
+#define TRX24_TX_END_vect_num        63
 
 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
-#define TRX24_AWAKE_vect                _VECTOR(64)
-#define TRX24_AWAKE_vect_num            64
+#define TRX24_AWAKE_vect            _VECTOR(64)
+#define TRX24_AWAKE_vect_num        64
 
 /* Symbol counter - compare match 1 interrupt */
-#define SCNT_CMP1_vect                  _VECTOR(65)
-#define SCNT_CMP1_vect_num              65
+#define SCNT_CMP1_vect            _VECTOR(65)
+#define SCNT_CMP1_vect_num        65
 
 /* Symbol counter - compare match 2 interrupt */
-#define SCNT_CMP2_vect                  _VECTOR(66)
-#define SCNT_CMP2_vect_num              66
+#define SCNT_CMP2_vect            _VECTOR(66)
+#define SCNT_CMP2_vect_num        66
 
 /* Symbol counter - compare match 3 interrupt */
-#define SCNT_CMP3_vect                  _VECTOR(67)
-#define SCNT_CMP3_vect_num              67
+#define SCNT_CMP3_vect            _VECTOR(67)
+#define SCNT_CMP3_vect_num        67
 
 /* Symbol counter - overflow interrupt */
-#define SCNT_OVFL_vect                  _VECTOR(68)
-#define SCNT_OVFL_vect_num              68
+#define SCNT_OVFL_vect            _VECTOR(68)
+#define SCNT_OVFL_vect_num        68
 
 /* Symbol counter - backoff interrupt */
-#define SCNT_BACKOFF_vect               _VECTOR(69)
-#define SCNT_BACKOFF_vect_num           69
+#define SCNT_BACKOFF_vect            _VECTOR(69)
+#define SCNT_BACKOFF_vect_num        69
 
 /* AES engine ready interrupt */
-#define AES_READY_vect                  _VECTOR(70)
-#define AES_READY_vect_num              70
+#define AES_READY_vect            _VECTOR(70)
+#define AES_READY_vect_num        70
 
 /* Battery monitor indicates supply voltage below threshold */
-#define BAT_LOW_vect                    _VECTOR(71)
-#define BAT_LOW_vect_num                71
+#define BAT_LOW_vect            _VECTOR(71)
+#define BAT_LOW_vect_num        71
 
 /* TRX24 TX start interrupt */
-#define TRX24_TX_START_vect             _VECTOR(72)
-#define TRX24_TX_START_vect_num         72
+#define TRX24_TX_START_vect            _VECTOR(72)
+#define TRX24_TX_START_vect_num        72
 
 /* Address match interrupt of address filter 0 */
-#define TRX24_AMI0_vect                 _VECTOR(73)
-#define TRX24_AMI0_vect_num             73
+#define TRX24_AMI0_vect            _VECTOR(73)
+#define TRX24_AMI0_vect_num        73
 
 /* Address match interrupt of address filter 1 */
-#define TRX24_AMI1_vect                 _VECTOR(74)
-#define TRX24_AMI1_vect_num             74
+#define TRX24_AMI1_vect            _VECTOR(74)
+#define TRX24_AMI1_vect_num        74
 
 /* Address match interrupt of address filter 2 */
-#define TRX24_AMI2_vect                 _VECTOR(75)
-#define TRX24_AMI2_vect_num             75
+#define TRX24_AMI2_vect            _VECTOR(75)
+#define TRX24_AMI2_vect_num        75
 
 /* Address match interrupt of address filter 3 */
-#define TRX24_AMI3_vect                 _VECTOR(76)
-#define TRX24_AMI3_vect_num             76
+#define TRX24_AMI3_vect            _VECTOR(76)
+#define TRX24_AMI3_vect_num        76
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 308
+#else
+#  define _VECTORS_SIZE 308U
+#endif
 
 
-/* memory parameters */
+/* Constants */
 
-#define SPM_PAGESIZE                    (256)
-#define RAMSTART                        (0x200)
-#define RAMSIZE                         (0x4000)
-#define RAMEND                          (0x41FF)
-#define XRAMSTART                       (0x0000)
-#define XRAMSIZE                        (0x0000)
-#define XRAMEND                         RAMEND
-#define E2END                           (0xFFF)
-#define E2PAGESIZE                      (0x08)
-#define FLASHEND                        (0x1ffff)
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 256
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFFF
+#else
+#  define SPM_PAGESIZE 256U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      16384
+#  define RAMEND       0x41FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      16384U
+#  define RAMEND       0x41FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      4096
+#  define E2PAGESIZE  8
+#  define E2END       0x0FFF
+#else
+#  define E2START     0U
+#  define E2SIZE      4096U
+#  define E2PAGESIZE  8U
+#  define E2END       0x0FFFU
+#endif
+#define XRAMEND      RAMEND
 
 
 /* Fuses */
 
 #define FUSE_MEMORY_SIZE 3
 
-/* LFUSE Byte */
-#define FUSE_CKSEL0     ~_BV(0) /* Select Clock Source */
-#define FUSE_CKSEL1     ~_BV(1) /* Select Clock Source */
-#define FUSE_CKSEL2     ~_BV(2) /* Select Clock Source */
-#define FUSE_CKSEL3     ~_BV(3) /* Select Clock Source */
-#define FUSE_SUT0       ~_BV(4) /* Select start-up time */
-#define FUSE_SUT1       ~_BV(5) /* Select start-up time */
-#define FUSE_CKOUT      ~_BV(6) /* Clock output */
-#define FUSE_CKDIV8     ~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* HFUSE Byte */
-#define FUSE_BOOTRST    ~_BV(0) /* Select Reset Vector */
-#define FUSE_BOOTSZ0    ~_BV(1) /* Select Boot Size */
-#define FUSE_BOOTSZ1    ~_BV(2) /* Select Boot Size */
-#define FUSE_EESAVE     ~_BV(3) /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      ~_BV(4) /* Watchdog timer always on */
-#define FUSE_SPIEN      ~_BV(5) /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN     ~_BV(6) /* Enable JTAG */
-#define FUSE_OCDEN      ~_BV(7) /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* EFUSE Byte */
-#define FUSE_BODLEVEL0  ~_BV(0) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  ~_BV(1) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  ~_BV(2) /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
+/* Low Fuse Byte */
+#define FUSE_CKSEL_SUT0  (unsigned char)~_BV(0)
+#define FUSE_CKSEL_SUT1  (unsigned char)~_BV(1)
+#define FUSE_CKSEL_SUT2  (unsigned char)~_BV(2)
+#define FUSE_CKSEL_SUT3  (unsigned char)~_BV(3)
+#define FUSE_CKSEL_SUT4  (unsigned char)~_BV(4)
+#define FUSE_CKSEL_SUT5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_CKSEL_SUT0 & FUSE_CKSEL_SUT2 & FUSE_CKSEL_SUT3 & FUSE_CKSEL_SUT4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BODLEVEL0)
 
 
 
 /* Lock Bits */
-
+#define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST
-#define __LOCK_BITS_EXIST
 
 
 /* Signature */
-
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0xA7
 #define SIGNATURE_2 0x02
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 
-#endif /* _AVR_IOM128RFR2_H_ */
+
+#endif /* #ifdef _AVR_ATMEGA128RFR2_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom16.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom16.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom16.h 2228 2011-03-05 15:33:19Z arcanum $ */
 
 /* avr/iom16.h - definitions for ATmega16 */
 
@@ -666,7 +666,6 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_ADC (0x01<<4)
 #define SLEEP_MODE_PWR_DOWN (0x02<<4)
@@ -674,5 +673,4 @@
 #define SLEEP_MODE_STANDBY (0x0A<<4)
 #define SLEEP_MODE_EXT_STANDBY (0x0B<<4)
 
-
 #endif /* _AVR_IOM16_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom161.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom161.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom161.h 2229 2011-03-05 17:00:18Z arcanum $ */
 
 /* avr/iom161.h - definitions for ATmega161 */
 
@@ -690,6 +690,9 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x01
 
+#define SLEEP_MODE_IDLE         0
+#define SLEEP_MODE_PWR_DOWN     1
+#define SLEEP_MODE_PWR_SAVE     2
 
 /* Deprecated items */
 #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
@@ -720,9 +723,4 @@
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 
-#define SLEEP_MODE_IDLE         0
-#define SLEEP_MODE_PWR_DOWN     1
-#define SLEEP_MODE_PWR_SAVE     2
-
-
 #endif /* _AVR_IOM161_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom162.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom162.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom162.h 2230 2011-03-06 02:42:04Z arcanum $ */
 
 /* iom162.h - definitions for ATmega162 */
 
@@ -976,6 +976,12 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x04
 
+#define SLEEP_MODE_IDLE         0
+#define SLEEP_MODE_PWR_DOWN     1
+#define SLEEP_MODE_PWR_SAVE     2
+#define SLEEP_MODE_ADC          3
+#define SLEEP_MODE_STANDBY      4
+#define SLEEP_MODE_EXT_STANDBY  5
 
 /* Deprecated items */
 #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
@@ -1013,12 +1019,4 @@
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 
-#define SLEEP_MODE_IDLE         0
-#define SLEEP_MODE_PWR_DOWN     1
-#define SLEEP_MODE_PWR_SAVE     2
-#define SLEEP_MODE_ADC          3
-#define SLEEP_MODE_STANDBY      4
-#define SLEEP_MODE_EXT_STANDBY  5
-
-
 #endif  /* _AVR_IOM162_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom163.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom163.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom163.h 2231 2011-03-07 05:06:55Z arcanum $ */
 
 /* avr/iom163.h - definitions for ATmega163 */
 
@@ -653,6 +653,10 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x02
 
+#define SLEEP_MODE_IDLE         0
+#define SLEEP_MODE_ADC          _BV(SM0)
+#define SLEEP_MODE_PWR_DOWN     _BV(SM1)
+#define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
 
 /* Deprecated items */
 #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
@@ -679,13 +683,4 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
-
-
-#define SLEEP_MODE_IDLE         0
-#define SLEEP_MODE_ADC          _BV(SM0)
-#define SLEEP_MODE_PWR_DOWN     _BV(SM1)
-#define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
-
-
 #endif /* _AVR_IOM163_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom164a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom164a.h
@@ -0,0 +1,1005 @@
+/* Copyright (c) 2005, 2006 Anatoly Sokolov, 2011 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* avr/iom164a.h - definitions for ATmega164A */
+
+/* $Id: iom164.h 2115 2010-04-05 23:19:53Z arcanum $ */
+
+#ifndef _AVR_IOM164A_H_
+#define _AVR_IOM164A_H_ 1
+
+
+/* Registers and associated bit numbers */
+
+#define PINA	_SFR_IO8(0X00)
+#define PINA7	7
+#define PINA6	6
+#define PINA5	5
+#define PINA4	4
+#define PINA3	3
+#define PINA2	2
+#define PINA1	1
+#define PINA0	0
+
+#define DDRA	_SFR_IO8(0X01)
+#define DDA7	7
+#define DDA6	6
+#define DDA5	5
+#define DDA4	4
+#define DDA3	3
+#define DDA2	2
+#define DDA1	1
+#define DDA0	0
+
+#define PORTA	_SFR_IO8(0X02)
+#define PA7	7
+#define PA6	6
+#define PA5	5
+#define PA4	4
+#define PA3	3
+#define PA2	2
+#define PA1	1
+#define PA0	0
+
+#define PINB	_SFR_IO8(0X03)
+#define PINB7	7
+#define PINB6	6
+#define PINB5	5
+#define PINB4	4
+#define PINB3	3
+#define PINB2	2
+#define PINB1	1
+#define PINB0	0
+
+#define DDRB	_SFR_IO8(0x04)
+#define DDB7	7
+#define DDB6	6
+#define DDB5	5
+#define DDB4	4
+#define DDB3	3
+#define DDB2	2
+#define DDB1	1
+#define DDB0	0
+
+#define PORTB	_SFR_IO8(0x05)
+#define PB7	7
+#define PB6	6
+#define PB5	5
+#define PB4	4
+#define PB3	3
+#define PB2	2
+#define PB1	1
+#define PB0	0
+
+#define PINC	_SFR_IO8(0x06)
+#define PINC7	7
+#define PINC6	6
+#define PINC5	5
+#define PINC4	4
+#define PINC3	3
+#define PINC2	2
+#define PINC1	1
+#define PINC0	0
+
+#define DDRC	_SFR_IO8(0x07)
+#define DDC7	7
+#define DDC6	6
+#define DDC5	5
+#define DDC4	4
+#define DDC3	3
+#define DDC2	2
+#define DDC1	1
+#define DDC0	0
+
+#define PORTC	_SFR_IO8(0x08)
+#define PC7	7
+#define PC6	6
+#define PC5	5
+#define PC4	4
+#define PC3	3
+#define PC2	2
+#define PC1	1
+#define PC0	0
+
+#define PIND	_SFR_IO8(0x09)
+#define PIND7	7
+#define PIND6	6
+#define PIND5	5
+#define PIND4	4
+#define PIND3	3
+#define PIND2	2
+#define PIND1	1
+#define PIND0	0
+
+#define DDRD	_SFR_IO8(0x0A)
+#define DDD7	7
+#define DDD6	6
+#define DDD5	5
+#define DDD4	4
+#define DDD3	3
+#define DDD2	2
+#define DDD1	1
+#define DDD0	0
+
+#define PORTD	_SFR_IO8(0x0B)
+#define PD7	7
+#define PD6	6
+#define PD5	5
+#define PD4	4
+#define PD3	3
+#define PD2	2
+#define PD1	1
+#define PD0	0
+
+/* Reserved [0x0C..0x14] */
+
+#define TIFR0	_SFR_IO8(0x15)
+#define OCF0B	2
+#define OCF0A	1
+#define TOV0	0
+
+#define TIFR1	_SFR_IO8(0x16)
+#define ICF1	5
+#define OCF1B	2
+#define OCF1A	1
+#define TOV1	0
+
+#define TIFR2	_SFR_IO8(0x17)
+#define OCF2B	2
+#define OCF2A	1
+#define TOV2	0
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR	_SFR_IO8(0x1B)
+#define PCIF3	3
+#define PCIF2	2
+#define PCIF1	1
+#define PCIF0	0
+
+#define EIFR   _SFR_IO8(0x1C)
+#define INTF2	2
+#define INTF1	1
+#define INTF0	0
+
+#define EIMSK	_SFR_IO8(0x1D)
+#define INT2	2
+#define INT1	1
+#define INT0	0
+
+#define GPIOR0	_SFR_IO8(0x1E)
+
+#define EECR   _SFR_IO8(0x1F)
+/* EECR - EEPROM Control Register */
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR   _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR   _SFR_IO16(0x21)
+#define EEARL  _SFR_IO8(0x21)
+#define EEARH  _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR	_SFR_IO8(0x23)
+#define TSM	7
+#define PSRASY	1
+#define PSRSYNC 0
+
+#define TCCR0A	_SFR_IO8(0x24)
+#define COM0A1	7
+#define COM0A0	6
+#define COM0B1	5
+#define COM0B0	4
+#define WGM01	1
+#define WGM00	0
+
+#define TCCR0B	_SFR_IO8(0x25)
+#define FOC0A	7
+#define FOC0B	6
+#define WGM02	3
+#define CS02	2
+#define CS01	1
+#define CS00	0
+
+#define TCNT0	_SFR_IO8(0X26)
+
+#define OCR0A	_SFR_IO8(0X27)
+
+#define OCR0B	_SFR_IO8(0X28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1	_SFR_IO8(0x2A)
+
+#define GPIOR2	_SFR_IO8(0x2B)
+
+#define SPCR	_SFR_IO8(0x2C)
+#define SPIE	7
+#define SPE	6
+#define DORD	5
+#define MSTR	4
+#define CPOL	3
+#define CPHA	2
+#define SPR1	1
+#define SPR0	0
+
+#define SPSR	_SFR_IO8(0x2D)
+#define SPIF	7
+#define WCOL	6
+#define SPI2X	0
+
+#define SPDR	_SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR	_SFR_IO8(0x30)
+#define ACD	7
+#define ACBG	6
+#define ACO	5
+#define ACI	4
+#define ACIE	3
+#define ACIC	2
+#define ACIS1	1
+#define ACIS0	0
+
+#define MONDR	_SFR_IO8(0x31)
+#define OCDR	_SFR_IO8(0x31)
+#define IDRD	7
+#define OCDR7	7
+#define OCDR6	6
+#define OCDR5	5
+#define OCDR4	4
+#define OCDR3	3
+#define OCDR2	2
+#define OCDR1	1
+#define OCDR0	0
+
+/* Reserved [0x32] */
+
+#define SMCR	_SFR_IO8(0x33)
+#define SM2	3
+#define SM1	2
+#define SM0	1
+#define SE	0
+
+#define MCUSR	_SFR_IO8(0x34)
+#define JTRF	4
+#define WDRF	3
+#define BORF	2
+#define EXTRF	1
+#define PORF	0
+
+#define MCUCR	_SFR_IO8(0X35)
+#define JTD	7
+#if !defined(__AVR_ATmega644__)
+#define BODS    6
+#define BODSE   5
+#endif
+#define PUD	4
+#define IVSEL	1
+#define IVCE	0
+
+/* Reserved [0x36] */
+
+#define SPMCSR	_SFR_IO8(0x37)
+#define SPMIE	7
+#define RWWSB	6
+#define SIGRD	5
+#define RWWSRE	4
+#define BLBSET	3
+#define PGWRT	2
+#define PGERS	1
+#define SPMEN	0
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR	_SFR_MEM8(0x60)
+#define WDIF	7
+#define WDIE	6
+#define WDP3	5
+#define WDCE	4
+#define WDE	3
+#define WDP2	2
+#define WDP1	1
+#define WDP0	0
+
+#define CLKPR	_SFR_MEM8(0x61)
+#define CLKPCE	7
+#define CLKPS3	3
+#define CLKPS2	2
+#define CLKPS1	1
+#define CLKPS0	0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR	_SFR_MEM8(0x64)  /* Datasheets: ATmega164P/324P/644P 8011D-AVR-02/07
+                                   and ATmega644 2593L-AVR-02/07.  */
+#define PRR0	_SFR_MEM8(0x64)  /* AVR Studio 4.13, build 524.  */
+#define PRTWI		7
+#define PRTIM2		6
+#define PRTIM0		5
+#if !defined(__AVR_ATmega644__)
+# define PRUSART1	4
+#endif
+#define PRTIM1		3
+#define PRSPI		2
+#define PRUSART0	1
+#define PRADC		0
+
+#if !defined(__AVR_ATmega644__)
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#else
+#define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#endif
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRUSART0
+#if !defined(__AVR_ATmega644__)
+#define __AVR_HAVE_PRR0_PRUSART1
+#endif
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL	_SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR	_SFR_MEM8(0x68)
+#define PCIE3	3
+#define PCIE2	2
+#define PCIE1	1
+#define PCIE0	0
+
+#define EICRA	_SFR_MEM8(0x69)
+#define ISC21	5
+#define ISC20	4
+#define ISC11	3
+#define ISC10	2
+#define ISC01	1
+#define ISC00	0
+
+/* Reserved [0x6A] */
+
+#define PCMSK0	_SFR_MEM8(0x6B)
+#define PCINT7	7
+#define PCINT6	6
+#define PCINT5	5
+#define PCINT4	4
+#define PCINT3	3
+#define PCINT2	2
+#define PCINT1	1
+#define PCINT0	0
+
+#define PCMSK1	_SFR_MEM8(0x6C)
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9	1
+#define PCINT8	0
+
+#define PCMSK2	_SFR_MEM8(0x6D)
+#define PCINT23 7
+#define PCINT22 6
+#define PCINT21 5
+#define PCINT20 4
+#define PCINT19 3
+#define PCINT18 2
+#define PCINT17 1
+#define PCINT16 0
+
+#define TIMSK0	_SFR_MEM8(0x6E)
+#define OCIE0B	2
+#define OCIE0A	1
+#define TOIE0	0
+
+#define TIMSK1	_SFR_MEM8(0x6F)
+#define ICIE1	5
+#define OCIE1B	2
+#define OCIE1A	1
+#define TOIE1	0
+
+#define TIMSK2	_SFR_MEM8(0x70)
+#define OCIE2B	2
+#define OCIE2A	1
+#define TOIE2	0
+
+/* Reserved [0x71..0x72] */
+
+#define PCMSK3	_SFR_MEM8(0x73)
+#define PCINT31 7
+#define PCINT30 6
+#define PCINT29 5
+#define PCINT28 4
+#define PCINT27 3
+#define PCINT26 2
+#define PCINT25 1
+#define PCINT24 0
+
+/* Reserved [0x74..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC	_SFR_MEM16(0x78)
+#endif
+#define ADCW	_SFR_MEM16(0x78)
+#define ADCL	_SFR_MEM8(0x78)
+#define ADCH	_SFR_MEM8(0x79)
+
+#define ADCSRA	_SFR_MEM8(0x7A)
+#define ADEN	7
+#define ADSC	6
+#define ADATE	5
+#define ADIF	4
+#define ADIE	3
+#define ADPS2	2
+#define ADPS1	1
+#define ADPS0	0
+
+#define ADCSRB	_SFR_MEM8(0x7B)
+#define ACME	6
+#define ADTS2	2
+#define ADTS1	1
+#define ADTS0	0
+
+#define ADMUX	_SFR_MEM8(0x7C)
+#define REFS1	7
+#define REFS0	6
+#define ADLAR	5
+#define MUX4	4
+#define MUX3	3
+#define MUX2	2
+#define MUX1	1
+#define MUX0	0
+
+/* Reserved [0x7D] */
+
+#define DIDR0	_SFR_MEM8(0x7E)
+#define ADC7D	7
+#define ADC6D	6
+#define ADC5D	5
+#define ADC4D	4
+#define ADC3D	3
+#define ADC2D	2
+#define ADC1D	1
+#define ADC0D	0
+
+#define DIDR1	_SFR_MEM8(0x7F)
+#define AIN1D	1
+#define AIN0D	0
+
+#define TCCR1A	_SFR_MEM8(0x80)
+#define COM1A1	7
+#define COM1A0	6
+#define COM1B1	5
+#define COM1B0	4
+#define WGM11	1
+#define WGM10	0
+
+#define TCCR1B	_SFR_MEM8(0x81)
+#define ICNC1	7
+#define ICES1	6
+#define WGM13	4
+#define WGM12	3
+#define CS12	2
+#define CS11	1
+#define CS10	0
+
+#define TCCR1C	_SFR_MEM8(0x82)
+#define FOC1A	7
+#define FOC1B	6
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1	_SFR_MEM16(0x84)
+
+#define TCNT1L	_SFR_MEM8(0x84)
+#define TCNT1H	_SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1	_SFR_MEM16(0x86)
+
+#define ICR1L	_SFR_MEM8(0x86)
+#define ICR1H	_SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A	_SFR_MEM16(0x88)
+
+#define OCR1AL	_SFR_MEM8(0x88)
+#define OCR1AH	_SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B	_SFR_MEM16(0x8A)
+
+#define OCR1BL	_SFR_MEM8(0x8A)
+#define OCR1BH	_SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A	_SFR_MEM8(0xB0)
+#define COM2A1	7
+#define COM2A0	6
+#define COM2B1	5
+#define COM2B0	4
+#define WGM21	1
+#define WGM20	0
+
+#define TCCR2B	_SFR_MEM8(0xB1)
+#define FOC2A	7
+#define FOC2B	6
+#define WGM22	3
+#define CS22	2
+#define CS21	1
+#define CS20	0
+
+#define TCNT2	_SFR_MEM8(0xB2)
+
+#define OCR2A	_SFR_MEM8(0xB3)
+
+#define OCR2B	_SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR	_SFR_MEM8(0xB6)
+#define EXCLK	6
+#define AS2	5
+#define TCN2UB	4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR	_SFR_MEM8(0xB8)
+
+#define TWSR	_SFR_MEM8(0xB9)
+#define TWS7	7
+#define TWS6	6
+#define TWS5	5
+#define TWS4	4
+#define TWS3	3
+#define TWPS1	1
+#define TWPS0	0
+
+#define TWAR	_SFR_MEM8(0xBA)
+#define TWA6	7
+#define TWA5	6
+#define TWA4	5
+#define TWA3	4
+#define TWA2	3
+#define TWA1	2
+#define TWA0	1
+#define TWGCE	0
+
+#define TWDR	_SFR_MEM8(0xBB)
+
+#define TWCR	_SFR_MEM8(0xBC)
+#define TWINT	7
+#define TWEA	6
+#define TWSTA	5
+#define TWSTO	4
+#define TWWC	3
+#define TWEN	2
+#define TWIE	0
+
+#define TWAMR	_SFR_MEM8(0xBD)
+#define TWAM6	7
+#define TWAM5	6
+#define TWAM4	5
+#define TWAM3	4
+#define TWAM2	3
+#define TWAM1	2
+#define TWAM0	1
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A	_SFR_MEM8(0xC0)
+#define RXC0	7
+#define TXC0	6
+#define UDRE0	5
+#define FE0	4
+#define DOR0	3
+#define UPE0	2
+#define U2X0	1
+#define MPCM0	0
+
+#define UCSR0B	_SFR_MEM8(0XC1)
+#define RXCIE0	7
+#define TXCIE0	6
+#define UDRIE0	5
+#define RXEN0	4
+#define TXEN0	3
+#define UCSZ02	2
+#define RXB80	1
+#define TXB80	0
+
+#define UCSR0C	_SFR_MEM8(0xC2)
+#define UMSEL01 7
+#define UMSEL00 6
+#define UPM01	5
+#define UPM00	4
+#define USBS0	3
+#define UCSZ01	2
+#define UCSZ00	1
+#define UCPHA0  1
+#define UCPOL0	0
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0	_SFR_MEM16(0xC4)
+
+#define UBRR0L	_SFR_MEM8(0xC4)
+#define UBRR0H	_SFR_MEM8(0xC5)
+
+#define UDR0	_SFR_MEM8(0XC6)
+
+#if !defined(__AVR_ATmega644__)
+/*
+ * Only ATmega164P/324P/644P have a second USART.
+ */
+/* Reserved [0xC7] */
+
+#define UCSR1A	_SFR_MEM8(0xC8)
+#define RXC1	7
+#define TXC1	6
+#define UDRE1	5
+#define FE1	4
+#define DOR1	3
+#define UPE1	2
+#define U2X1	1
+#define MPCM1	0
+
+#define UCSR1B	_SFR_MEM8(0XC9)
+#define RXCIE1	7
+#define TXCIE1	6
+#define UDRIE1	5
+#define RXEN1	4
+#define TXEN1	3
+#define UCSZ12	2
+#define RXB81	1
+#define TXB81	0
+
+#define UCSR1C	_SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11	5
+#define UPM10	4
+#define USBS1	3
+#define UCSZ11	2
+#define UCSZ10	1
+#define UCPHA1  1
+#define UCPOL1	0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1	_SFR_MEM16(0xCC)
+
+#define UBRR1L	_SFR_MEM8(0xCC)
+#define UBRR1H	_SFR_MEM8(0xCD)
+
+#define UDR1	_SFR_MEM8(0XCE)
+#endif /* !defined(__AVR_ATmega644) */
+
+/* Reserved [0xCF..0xFF] */
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect_num			1
+#define INT0_vect			    _VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num			2
+#define INT1_vect			    _VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num			3
+#define INT2_vect	    		_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num			4
+#define PCINT0_vect			    _VECTOR(4)
+#define SIG_PIN_CHANGE0			_VECTOR(4)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num			5
+#define PCINT1_vect		    	_VECTOR(5)
+#define SIG_PIN_CHANGE1			_VECTOR(5)
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect_num  		6
+#define PCINT2_vect				_VECTOR(6)
+#define SIG_PIN_CHANGE2			_VECTOR(6)
+
+/* Pin Change Interrupt Request 3 */
+#define PCINT3_vect_num			7
+#define PCINT3_vect			    _VECTOR(7)
+#define SIG_PIN_CHANGE3			_VECTOR(7)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num			8
+#define WDT_vect		    	_VECTOR(8)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(8)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	9
+#define TIMER2_COMPA_vect		_VECTOR(9)
+#define SIG_OUTPUT_COMPARE2A	_VECTOR(9)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	10
+#define TIMER2_COMPB_vect		_VECTOR(10)
+#define SIG_OUTPUT_COMPARE2B	_VECTOR(10)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		11
+#define TIMER2_OVF_vect			_VECTOR(11)
+#define SIG_OVERFLOW2			_VECTOR(11)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	12
+#define TIMER1_CAPT_vect		_VECTOR(12)
+#define SIG_INPUT_CAPTURE1		_VECTOR(12)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	13
+#define TIMER1_COMPA_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(13)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	14
+#define TIMER1_COMPB_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(14)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		15
+#define TIMER1_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW1			_VECTOR(15)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	16
+#define TIMER0_COMPA_vect		_VECTOR(16)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(16)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	17
+#define TIMER0_COMPB_vect		_VECTOR(17)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(17)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		18
+#define TIMER0_OVF_vect			_VECTOR(18)
+#define SIG_OVERFLOW0			_VECTOR(18)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		19
+#define SPI_STC_vect			_VECTOR(19)
+#define SIG_SPI				    _VECTOR(19)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		20
+#define USART0_RX_vect			_VECTOR(20)
+#define SIG_USART_RECV			_VECTOR(20)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	21
+#define USART0_UDRE_vect		_VECTOR(21)
+#define SIG_USART_DATA			_VECTOR(21)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		22
+#define USART0_TX_vect			_VECTOR(22)
+#define SIG_USART_TRANS			_VECTOR(22)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	23
+#define ANALOG_COMP_vect		_VECTOR(23)
+#define SIG_COMPARATOR			_VECTOR(23)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			24
+#define ADC_vect	    		_VECTOR(24)
+#define SIG_ADC			    	_VECTOR(24)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		25
+#define EE_READY_vect			_VECTOR(25)
+#define SIG_EEPROM_READY		_VECTOR(25)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num			26
+#define TWI_vect	    		_VECTOR(26)
+#define SIG_2WIRE_SERIAL		_VECTOR(26)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		27
+#define SPM_READY_vect			_VECTOR(27)
+#define SIG_SPM_READY			_VECTOR(27)
+
+#if defined(__AVR_ATmega644__)
+
+# define _VECTORS_SIZE 112
+
+#else /* !defined(__AVR_ATmega644__) */
+
+/* USART1, Rx Complete */
+/* USART1 RX complete */
+#define USART1_RX_vect_num		28
+#define USART1_RX_vect			_VECTOR(28)
+#define SIG_USART1_RECV			_VECTOR(28)
+
+/* USART1 Data register Empty */
+/* USART1 Data Register Empty */
+#define USART1_UDRE_vect_num	29
+#define USART1_UDRE_vect		_VECTOR(29)
+#define SIG_USART1_DATA			_VECTOR(29)
+
+/* USART1, Tx Complete */
+/* USART1 TX complete */
+#define USART1_TX_vect_num		30
+#define USART1_TX_vect			_VECTOR(30)
+#define SIG_USART1_TRANS		_VECTOR(30)
+
+# define _VECTORS_SIZE 124
+
+#endif /* defined(__AVR_ATmega644__) */
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_INTERRUPT2
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_PIN_CHANGE3
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART_RECV
+#pragma GCC poison SIG_USART_DATA
+#pragma GCC poison SIG_USART_TRANS
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+#pragma GCC poison SIG_USART1_RECV
+#pragma GCC poison SIG_USART1_DATA
+#pragma GCC poison SIG_USART1_TRANS
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
+
+
+/* Constants */
+#define SPM_PAGESIZE    128
+#define RAMSTART        (0x100)
+#define RAMEND          0x04FF
+#define XRAMEND         RAMEND
+#define E2END           0x1FF
+#define E2PAGESIZE      4
+#define FLASHEND        0x3FFF
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST 
+
+
+/* Signature (ATmega164P) */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x0A
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+#endif /* _AVR_IOM164A_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom164p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom164p.h
@@ -0,0 +1,1005 @@
+/* Copyright (c) 2005, 2006 Anatoly Sokolov, 2011 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* avr/iom164a.h - definitions for ATmega164 */
+
+/* $Id: iom164.h 2115 2010-04-05 23:19:53Z arcanum $ */
+
+#ifndef _AVR_IOM164P_H_
+#define _AVR_IOM164P_H_ 1
+
+
+/* Registers and associated bit numbers */
+
+#define PINA	_SFR_IO8(0X00)
+#define PINA7	7
+#define PINA6	6
+#define PINA5	5
+#define PINA4	4
+#define PINA3	3
+#define PINA2	2
+#define PINA1	1
+#define PINA0	0
+
+#define DDRA	_SFR_IO8(0X01)
+#define DDA7	7
+#define DDA6	6
+#define DDA5	5
+#define DDA4	4
+#define DDA3	3
+#define DDA2	2
+#define DDA1	1
+#define DDA0	0
+
+#define PORTA	_SFR_IO8(0X02)
+#define PA7	7
+#define PA6	6
+#define PA5	5
+#define PA4	4
+#define PA3	3
+#define PA2	2
+#define PA1	1
+#define PA0	0
+
+#define PINB	_SFR_IO8(0X03)
+#define PINB7	7
+#define PINB6	6
+#define PINB5	5
+#define PINB4	4
+#define PINB3	3
+#define PINB2	2
+#define PINB1	1
+#define PINB0	0
+
+#define DDRB	_SFR_IO8(0x04)
+#define DDB7	7
+#define DDB6	6
+#define DDB5	5
+#define DDB4	4
+#define DDB3	3
+#define DDB2	2
+#define DDB1	1
+#define DDB0	0
+
+#define PORTB	_SFR_IO8(0x05)
+#define PB7	7
+#define PB6	6
+#define PB5	5
+#define PB4	4
+#define PB3	3
+#define PB2	2
+#define PB1	1
+#define PB0	0
+
+#define PINC	_SFR_IO8(0x06)
+#define PINC7	7
+#define PINC6	6
+#define PINC5	5
+#define PINC4	4
+#define PINC3	3
+#define PINC2	2
+#define PINC1	1
+#define PINC0	0
+
+#define DDRC	_SFR_IO8(0x07)
+#define DDC7	7
+#define DDC6	6
+#define DDC5	5
+#define DDC4	4
+#define DDC3	3
+#define DDC2	2
+#define DDC1	1
+#define DDC0	0
+
+#define PORTC	_SFR_IO8(0x08)
+#define PC7	7
+#define PC6	6
+#define PC5	5
+#define PC4	4
+#define PC3	3
+#define PC2	2
+#define PC1	1
+#define PC0	0
+
+#define PIND	_SFR_IO8(0x09)
+#define PIND7	7
+#define PIND6	6
+#define PIND5	5
+#define PIND4	4
+#define PIND3	3
+#define PIND2	2
+#define PIND1	1
+#define PIND0	0
+
+#define DDRD	_SFR_IO8(0x0A)
+#define DDD7	7
+#define DDD6	6
+#define DDD5	5
+#define DDD4	4
+#define DDD3	3
+#define DDD2	2
+#define DDD1	1
+#define DDD0	0
+
+#define PORTD	_SFR_IO8(0x0B)
+#define PD7	7
+#define PD6	6
+#define PD5	5
+#define PD4	4
+#define PD3	3
+#define PD2	2
+#define PD1	1
+#define PD0	0
+
+/* Reserved [0x0C..0x14] */
+
+#define TIFR0	_SFR_IO8(0x15)
+#define OCF0B	2
+#define OCF0A	1
+#define TOV0	0
+
+#define TIFR1	_SFR_IO8(0x16)
+#define ICF1	5
+#define OCF1B	2
+#define OCF1A	1
+#define TOV1	0
+
+#define TIFR2	_SFR_IO8(0x17)
+#define OCF2B	2
+#define OCF2A	1
+#define TOV2	0
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR	_SFR_IO8(0x1B)
+#define PCIF3	3
+#define PCIF2	2
+#define PCIF1	1
+#define PCIF0	0
+
+#define EIFR   _SFR_IO8(0x1C)
+#define INTF2	2
+#define INTF1	1
+#define INTF0	0
+
+#define EIMSK	_SFR_IO8(0x1D)
+#define INT2	2
+#define INT1	1
+#define INT0	0
+
+#define GPIOR0	_SFR_IO8(0x1E)
+
+#define EECR   _SFR_IO8(0x1F)
+/* EECR - EEPROM Control Register */
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR   _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR   _SFR_IO16(0x21)
+#define EEARL  _SFR_IO8(0x21)
+#define EEARH  _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR	_SFR_IO8(0x23)
+#define TSM	7
+#define PSRASY	1
+#define PSRSYNC 0
+
+#define TCCR0A	_SFR_IO8(0x24)
+#define COM0A1	7
+#define COM0A0	6
+#define COM0B1	5
+#define COM0B0	4
+#define WGM01	1
+#define WGM00	0
+
+#define TCCR0B	_SFR_IO8(0x25)
+#define FOC0A	7
+#define FOC0B	6
+#define WGM02	3
+#define CS02	2
+#define CS01	1
+#define CS00	0
+
+#define TCNT0	_SFR_IO8(0X26)
+
+#define OCR0A	_SFR_IO8(0X27)
+
+#define OCR0B	_SFR_IO8(0X28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1	_SFR_IO8(0x2A)
+
+#define GPIOR2	_SFR_IO8(0x2B)
+
+#define SPCR	_SFR_IO8(0x2C)
+#define SPIE	7
+#define SPE	6
+#define DORD	5
+#define MSTR	4
+#define CPOL	3
+#define CPHA	2
+#define SPR1	1
+#define SPR0	0
+
+#define SPSR	_SFR_IO8(0x2D)
+#define SPIF	7
+#define WCOL	6
+#define SPI2X	0
+
+#define SPDR	_SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR	_SFR_IO8(0x30)
+#define ACD	7
+#define ACBG	6
+#define ACO	5
+#define ACI	4
+#define ACIE	3
+#define ACIC	2
+#define ACIS1	1
+#define ACIS0	0
+
+#define MONDR	_SFR_IO8(0x31)
+#define OCDR	_SFR_IO8(0x31)
+#define IDRD	7
+#define OCDR7	7
+#define OCDR6	6
+#define OCDR5	5
+#define OCDR4	4
+#define OCDR3	3
+#define OCDR2	2
+#define OCDR1	1
+#define OCDR0	0
+
+/* Reserved [0x32] */
+
+#define SMCR	_SFR_IO8(0x33)
+#define SM2	3
+#define SM1	2
+#define SM0	1
+#define SE	0
+
+#define MCUSR	_SFR_IO8(0x34)
+#define JTRF	4
+#define WDRF	3
+#define BORF	2
+#define EXTRF	1
+#define PORF	0
+
+#define MCUCR	_SFR_IO8(0X35)
+#define JTD	7
+#if !defined(__AVR_ATmega644__)
+#define BODS    6
+#define BODSE   5
+#endif
+#define PUD	4
+#define IVSEL	1
+#define IVCE	0
+
+/* Reserved [0x36] */
+
+#define SPMCSR	_SFR_IO8(0x37)
+#define SPMIE	7
+#define RWWSB	6
+#define SIGRD	5
+#define RWWSRE	4
+#define BLBSET	3
+#define PGWRT	2
+#define PGERS	1
+#define SPMEN	0
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR	_SFR_MEM8(0x60)
+#define WDIF	7
+#define WDIE	6
+#define WDP3	5
+#define WDCE	4
+#define WDE	3
+#define WDP2	2
+#define WDP1	1
+#define WDP0	0
+
+#define CLKPR	_SFR_MEM8(0x61)
+#define CLKPCE	7
+#define CLKPS3	3
+#define CLKPS2	2
+#define CLKPS1	1
+#define CLKPS0	0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR	_SFR_MEM8(0x64)  /* Datasheets: ATmega164P/324P/644P 8011D-AVR-02/07
+                                   and ATmega644 2593L-AVR-02/07.  */
+#define PRR0	_SFR_MEM8(0x64)  /* AVR Studio 4.13, build 524.  */
+#define PRTWI		7
+#define PRTIM2		6
+#define PRTIM0		5
+#if !defined(__AVR_ATmega644__)
+# define PRUSART1	4
+#endif
+#define PRTIM1		3
+#define PRSPI		2
+#define PRUSART0	1
+#define PRADC		0
+
+#if !defined(__AVR_ATmega644__)
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#else
+#define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#endif
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRUSART0
+#if !defined(__AVR_ATmega644__)
+#define __AVR_HAVE_PRR0_PRUSART1
+#endif
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL	_SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR	_SFR_MEM8(0x68)
+#define PCIE3	3
+#define PCIE2	2
+#define PCIE1	1
+#define PCIE0	0
+
+#define EICRA	_SFR_MEM8(0x69)
+#define ISC21	5
+#define ISC20	4
+#define ISC11	3
+#define ISC10	2
+#define ISC01	1
+#define ISC00	0
+
+/* Reserved [0x6A] */
+
+#define PCMSK0	_SFR_MEM8(0x6B)
+#define PCINT7	7
+#define PCINT6	6
+#define PCINT5	5
+#define PCINT4	4
+#define PCINT3	3
+#define PCINT2	2
+#define PCINT1	1
+#define PCINT0	0
+
+#define PCMSK1	_SFR_MEM8(0x6C)
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9	1
+#define PCINT8	0
+
+#define PCMSK2	_SFR_MEM8(0x6D)
+#define PCINT23 7
+#define PCINT22 6
+#define PCINT21 5
+#define PCINT20 4
+#define PCINT19 3
+#define PCINT18 2
+#define PCINT17 1
+#define PCINT16 0
+
+#define TIMSK0	_SFR_MEM8(0x6E)
+#define OCIE0B	2
+#define OCIE0A	1
+#define TOIE0	0
+
+#define TIMSK1	_SFR_MEM8(0x6F)
+#define ICIE1	5
+#define OCIE1B	2
+#define OCIE1A	1
+#define TOIE1	0
+
+#define TIMSK2	_SFR_MEM8(0x70)
+#define OCIE2B	2
+#define OCIE2A	1
+#define TOIE2	0
+
+/* Reserved [0x71..0x72] */
+
+#define PCMSK3	_SFR_MEM8(0x73)
+#define PCINT31 7
+#define PCINT30 6
+#define PCINT29 5
+#define PCINT28 4
+#define PCINT27 3
+#define PCINT26 2
+#define PCINT25 1
+#define PCINT24 0
+
+/* Reserved [0x74..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC	_SFR_MEM16(0x78)
+#endif
+#define ADCW	_SFR_MEM16(0x78)
+#define ADCL	_SFR_MEM8(0x78)
+#define ADCH	_SFR_MEM8(0x79)
+
+#define ADCSRA	_SFR_MEM8(0x7A)
+#define ADEN	7
+#define ADSC	6
+#define ADATE	5
+#define ADIF	4
+#define ADIE	3
+#define ADPS2	2
+#define ADPS1	1
+#define ADPS0	0
+
+#define ADCSRB	_SFR_MEM8(0x7B)
+#define ACME	6
+#define ADTS2	2
+#define ADTS1	1
+#define ADTS0	0
+
+#define ADMUX	_SFR_MEM8(0x7C)
+#define REFS1	7
+#define REFS0	6
+#define ADLAR	5
+#define MUX4	4
+#define MUX3	3
+#define MUX2	2
+#define MUX1	1
+#define MUX0	0
+
+/* Reserved [0x7D] */
+
+#define DIDR0	_SFR_MEM8(0x7E)
+#define ADC7D	7
+#define ADC6D	6
+#define ADC5D	5
+#define ADC4D	4
+#define ADC3D	3
+#define ADC2D	2
+#define ADC1D	1
+#define ADC0D	0
+
+#define DIDR1	_SFR_MEM8(0x7F)
+#define AIN1D	1
+#define AIN0D	0
+
+#define TCCR1A	_SFR_MEM8(0x80)
+#define COM1A1	7
+#define COM1A0	6
+#define COM1B1	5
+#define COM1B0	4
+#define WGM11	1
+#define WGM10	0
+
+#define TCCR1B	_SFR_MEM8(0x81)
+#define ICNC1	7
+#define ICES1	6
+#define WGM13	4
+#define WGM12	3
+#define CS12	2
+#define CS11	1
+#define CS10	0
+
+#define TCCR1C	_SFR_MEM8(0x82)
+#define FOC1A	7
+#define FOC1B	6
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1	_SFR_MEM16(0x84)
+
+#define TCNT1L	_SFR_MEM8(0x84)
+#define TCNT1H	_SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1	_SFR_MEM16(0x86)
+
+#define ICR1L	_SFR_MEM8(0x86)
+#define ICR1H	_SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A	_SFR_MEM16(0x88)
+
+#define OCR1AL	_SFR_MEM8(0x88)
+#define OCR1AH	_SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B	_SFR_MEM16(0x8A)
+
+#define OCR1BL	_SFR_MEM8(0x8A)
+#define OCR1BH	_SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A	_SFR_MEM8(0xB0)
+#define COM2A1	7
+#define COM2A0	6
+#define COM2B1	5
+#define COM2B0	4
+#define WGM21	1
+#define WGM20	0
+
+#define TCCR2B	_SFR_MEM8(0xB1)
+#define FOC2A	7
+#define FOC2B	6
+#define WGM22	3
+#define CS22	2
+#define CS21	1
+#define CS20	0
+
+#define TCNT2	_SFR_MEM8(0xB2)
+
+#define OCR2A	_SFR_MEM8(0xB3)
+
+#define OCR2B	_SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR	_SFR_MEM8(0xB6)
+#define EXCLK	6
+#define AS2	5
+#define TCN2UB	4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR	_SFR_MEM8(0xB8)
+
+#define TWSR	_SFR_MEM8(0xB9)
+#define TWS7	7
+#define TWS6	6
+#define TWS5	5
+#define TWS4	4
+#define TWS3	3
+#define TWPS1	1
+#define TWPS0	0
+
+#define TWAR	_SFR_MEM8(0xBA)
+#define TWA6	7
+#define TWA5	6
+#define TWA4	5
+#define TWA3	4
+#define TWA2	3
+#define TWA1	2
+#define TWA0	1
+#define TWGCE	0
+
+#define TWDR	_SFR_MEM8(0xBB)
+
+#define TWCR	_SFR_MEM8(0xBC)
+#define TWINT	7
+#define TWEA	6
+#define TWSTA	5
+#define TWSTO	4
+#define TWWC	3
+#define TWEN	2
+#define TWIE	0
+
+#define TWAMR	_SFR_MEM8(0xBD)
+#define TWAM6	7
+#define TWAM5	6
+#define TWAM4	5
+#define TWAM3	4
+#define TWAM2	3
+#define TWAM1	2
+#define TWAM0	1
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A	_SFR_MEM8(0xC0)
+#define RXC0	7
+#define TXC0	6
+#define UDRE0	5
+#define FE0	4
+#define DOR0	3
+#define UPE0	2
+#define U2X0	1
+#define MPCM0	0
+
+#define UCSR0B	_SFR_MEM8(0XC1)
+#define RXCIE0	7
+#define TXCIE0	6
+#define UDRIE0	5
+#define RXEN0	4
+#define TXEN0	3
+#define UCSZ02	2
+#define RXB80	1
+#define TXB80	0
+
+#define UCSR0C	_SFR_MEM8(0xC2)
+#define UMSEL01 7
+#define UMSEL00 6
+#define UPM01	5
+#define UPM00	4
+#define USBS0	3
+#define UCSZ01	2
+#define UCSZ00	1
+#define UCPHA0  1
+#define UCPOL0	0
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0	_SFR_MEM16(0xC4)
+
+#define UBRR0L	_SFR_MEM8(0xC4)
+#define UBRR0H	_SFR_MEM8(0xC5)
+
+#define UDR0	_SFR_MEM8(0XC6)
+
+#if !defined(__AVR_ATmega644__)
+/*
+ * Only ATmega164P/324P/644P have a second USART.
+ */
+/* Reserved [0xC7] */
+
+#define UCSR1A	_SFR_MEM8(0xC8)
+#define RXC1	7
+#define TXC1	6
+#define UDRE1	5
+#define FE1	4
+#define DOR1	3
+#define UPE1	2
+#define U2X1	1
+#define MPCM1	0
+
+#define UCSR1B	_SFR_MEM8(0XC9)
+#define RXCIE1	7
+#define TXCIE1	6
+#define UDRIE1	5
+#define RXEN1	4
+#define TXEN1	3
+#define UCSZ12	2
+#define RXB81	1
+#define TXB81	0
+
+#define UCSR1C	_SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11	5
+#define UPM10	4
+#define USBS1	3
+#define UCSZ11	2
+#define UCSZ10	1
+#define UCPHA1  1
+#define UCPOL1	0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1	_SFR_MEM16(0xCC)
+
+#define UBRR1L	_SFR_MEM8(0xCC)
+#define UBRR1H	_SFR_MEM8(0xCD)
+
+#define UDR1	_SFR_MEM8(0XCE)
+#endif /* !defined(__AVR_ATmega644) */
+
+/* Reserved [0xCF..0xFF] */
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect_num			1
+#define INT0_vect			    _VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num			2
+#define INT1_vect			    _VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num			3
+#define INT2_vect	    		_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num			4
+#define PCINT0_vect			    _VECTOR(4)
+#define SIG_PIN_CHANGE0			_VECTOR(4)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num			5
+#define PCINT1_vect		    	_VECTOR(5)
+#define SIG_PIN_CHANGE1			_VECTOR(5)
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect_num  		6
+#define PCINT2_vect				_VECTOR(6)
+#define SIG_PIN_CHANGE2			_VECTOR(6)
+
+/* Pin Change Interrupt Request 3 */
+#define PCINT3_vect_num			7
+#define PCINT3_vect			    _VECTOR(7)
+#define SIG_PIN_CHANGE3			_VECTOR(7)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num			8
+#define WDT_vect		    	_VECTOR(8)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(8)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	9
+#define TIMER2_COMPA_vect		_VECTOR(9)
+#define SIG_OUTPUT_COMPARE2A	_VECTOR(9)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	10
+#define TIMER2_COMPB_vect		_VECTOR(10)
+#define SIG_OUTPUT_COMPARE2B	_VECTOR(10)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		11
+#define TIMER2_OVF_vect			_VECTOR(11)
+#define SIG_OVERFLOW2			_VECTOR(11)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	12
+#define TIMER1_CAPT_vect		_VECTOR(12)
+#define SIG_INPUT_CAPTURE1		_VECTOR(12)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	13
+#define TIMER1_COMPA_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(13)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	14
+#define TIMER1_COMPB_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(14)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		15
+#define TIMER1_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW1			_VECTOR(15)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	16
+#define TIMER0_COMPA_vect		_VECTOR(16)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(16)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	17
+#define TIMER0_COMPB_vect		_VECTOR(17)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(17)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		18
+#define TIMER0_OVF_vect			_VECTOR(18)
+#define SIG_OVERFLOW0			_VECTOR(18)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		19
+#define SPI_STC_vect			_VECTOR(19)
+#define SIG_SPI				    _VECTOR(19)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		20
+#define USART0_RX_vect			_VECTOR(20)
+#define SIG_USART_RECV			_VECTOR(20)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	21
+#define USART0_UDRE_vect		_VECTOR(21)
+#define SIG_USART_DATA			_VECTOR(21)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		22
+#define USART0_TX_vect			_VECTOR(22)
+#define SIG_USART_TRANS			_VECTOR(22)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	23
+#define ANALOG_COMP_vect		_VECTOR(23)
+#define SIG_COMPARATOR			_VECTOR(23)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			24
+#define ADC_vect	    		_VECTOR(24)
+#define SIG_ADC			    	_VECTOR(24)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		25
+#define EE_READY_vect			_VECTOR(25)
+#define SIG_EEPROM_READY		_VECTOR(25)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num			26
+#define TWI_vect	    		_VECTOR(26)
+#define SIG_2WIRE_SERIAL		_VECTOR(26)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		27
+#define SPM_READY_vect			_VECTOR(27)
+#define SIG_SPM_READY			_VECTOR(27)
+
+#if defined(__AVR_ATmega644__)
+
+# define _VECTORS_SIZE 112
+
+#else /* !defined(__AVR_ATmega644__) */
+
+/* USART1, Rx Complete */
+/* USART1 RX complete */
+#define USART1_RX_vect_num		28
+#define USART1_RX_vect			_VECTOR(28)
+#define SIG_USART1_RECV			_VECTOR(28)
+
+/* USART1 Data register Empty */
+/* USART1 Data Register Empty */
+#define USART1_UDRE_vect_num	29
+#define USART1_UDRE_vect		_VECTOR(29)
+#define SIG_USART1_DATA			_VECTOR(29)
+
+/* USART1, Tx Complete */
+/* USART1 TX complete */
+#define USART1_TX_vect_num		30
+#define USART1_TX_vect			_VECTOR(30)
+#define SIG_USART1_TRANS		_VECTOR(30)
+
+# define _VECTORS_SIZE 124
+
+#endif /* defined(__AVR_ATmega644__) */
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_INTERRUPT2
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_PIN_CHANGE3
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART_RECV
+#pragma GCC poison SIG_USART_DATA
+#pragma GCC poison SIG_USART_TRANS
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+#pragma GCC poison SIG_USART1_RECV
+#pragma GCC poison SIG_USART1_DATA
+#pragma GCC poison SIG_USART1_TRANS
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
+
+
+/* Constants */
+#define SPM_PAGESIZE    128
+#define RAMSTART        (0x100)
+#define RAMEND          0x04FF
+#define XRAMEND         RAMEND
+#define E2END           0x1FF
+#define E2PAGESIZE      4
+#define FLASHEND        0x3FFF
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST 
+
+
+/* Signature (ATmega164P) */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x0F
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+#endif /* _AVR_IOM164P_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom164pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom164pa.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA164PA_H_INCLUDED
 #define _AVR_ATMEGA164PA_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRA    _SFR_IO8(0x01)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x02)
 #define PORTA7  7
@@ -92,13 +91,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -122,13 +137,29 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC7  7
@@ -152,13 +183,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -382,19 +429,19 @@
 
 #define PRR0    _SFR_MEM8(0x64)
 #define PRADC   0
+#define PRUSART0 1
 #define PRSPI   2
 #define PRTIM1  3
-#define PRUSART0 1
 #define PRUSART1 4
 #define PRTIM0  5
 #define PRTIM2  6
 #define PRTWI   7
 
-#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
 #define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRUSART0
 #define __AVR_HAVE_PRR0_PRSPI
 #define __AVR_HAVE_PRR0_PRTIM1
-#define __AVR_HAVE_PRR0_PRUSART0
 #define __AVR_HAVE_PRR0_PRUSART1
 #define __AVR_HAVE_PRR0_PRTIM0
 #define __AVR_HAVE_PRR0_PRTIM2
@@ -752,6 +799,16 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -874,21 +931,44 @@
 #define USART1_TX_vect            _VECTOR(30)
 #define USART1_TX_vect_num        30
 
-#define _VECTORS_SIZE 124
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 124
+#else
+#  define _VECTORS_SIZE 124U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      1024
-#define RAMEND       0x04FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      1024
+#  define RAMEND       0x04FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x04FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -905,6 +985,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -915,11 +997,15 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_JTAGEN      (unsigned char)~_BV(6)
 #define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
 #define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
 #define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -935,12 +1021,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 #endif /* #ifdef _AVR_ATMEGA164PA_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom165.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom165.h
@@ -1,888 +1,887 @@
-/* Copyright (c) 2004,2005,2006 Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* $Id$ */
-
-/* avr/iom165.h - definitions for ATmega165 */
-
-#ifndef _AVR_IOM165_H_
-#define _AVR_IOM165_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom165.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   6
-#define PCIF1   7
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   6
-#define PCIE1   7
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCD     7   // The datasheet defines this but IMO it should be OCDR7.
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRUSART0
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRTIM1
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-/* Combine PCMSK0 and PCMSK1 */
-#define PCMSK   _SFR_MEM16(0x6B)
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSRA   _SFR_MEM8(0xC0)
-#define MPCM    0
-#define U2X     1
-#define UPE     2
-#define DOR     3
-#define FE      4
-#define UDRE    5
-#define TXC     6
-#define RXC     7
-
-#define UCSRB   _SFR_MEM8(0XC1)
-#define TXB8    0
-#define RXB8    1
-#define UCSZ2   2
-#define TXEN    3
-#define RXEN    4
-#define UDRIE   5
-#define TXCIE   6
-#define RXCIE   7
-
-#define UCSRC   _SFR_MEM8(0xC2)
-#define UCPOL   0
-#define UCSZ0   1
-#define UCSZ1   2
-#define USBS    3
-#define UPM0    4
-#define UPM1    5
-#define UMSEL   6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRRL and UBRRH */
-#define UBRR    _SFR_MEM16(0xC4)
-
-#define UBRRL   _SFR_MEM8(0xC4)
-#define UBRRH   _SFR_MEM8(0xC5)
-
-#define UDR     _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xFF] */
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect_num		1
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect_num		2
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect_num		3
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect_num	4
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect_num		5
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect_num	6
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect_num	7
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A	_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect_num	8
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B	_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect_num		9
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect_num	10
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect_num		11
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect_num		12
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				    _VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect_num		13
-#define USART0_RX_vect			_VECTOR(13)
-#define USART_RX_vect			_VECTOR(13)  /* Alias */
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect_num	14
-#define USART0_UDRE_vect		_VECTOR(14)
-#define USART_UDRE_vect		    _VECTOR(14)  /* Alias */
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect_num		15
-#define USART0_TX_vect			_VECTOR(15)
-#define USART_TX_vect			_VECTOR(15)  /* Alias */
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect_num		16
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect_num	17
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect_num	18
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect_num		19
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect_num		20
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect_num		21
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-#define _VECTORS_SIZE 88
-
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMSTART        0x100
-#define RAMEND          0x4FF
-#define XRAMEND         RAMEND
-#define E2END           0x1FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x05
-
-
-/* Deprecated items */
-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
-
-#pragma GCC system_header
-
-#pragma GCC poison SIG_INTERRUPT0
-#pragma GCC poison SIG_PIN_CHANGE0
-#pragma GCC poison SIG_PIN_CHANGE1
-#pragma GCC poison SIG_OUTPUT_COMPARE2
-#pragma GCC poison SIG_OVERFLOW2
-#pragma GCC poison SIG_INPUT_CAPTURE1
-#pragma GCC poison SIG_OUTPUT_COMPARE1A
-#pragma GCC poison SIG_OUTPUT_COMPARE1B
-#pragma GCC poison SIG_OVERFLOW1
-#pragma GCC poison SIG_OUTPUT_COMPARE0
-#pragma GCC poison SIG_OVERFLOW0
-#pragma GCC poison SIG_SPI
-#pragma GCC poison USART_RX_vect
-#pragma GCC poison SIG_UART_RECV
-#pragma GCC poison USART_UDRE_vect
-#pragma GCC poison SIG_UART_DATA
-#pragma GCC poison USART_TX_vect
-#pragma GCC poison SIG_UART_TRANS
-#pragma GCC poison SIG_USI_START
-#pragma GCC poison SIG_USI_OVERFLOW
-#pragma GCC poison SIG_COMPARATOR
-#pragma GCC poison SIG_ADC
-#pragma GCC poison SIG_EEPROM_READY
-#pragma GCC poison SIG_SPM_READY
-
-#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-
-
-#endif /* _AVR_IOM165_H_ */
+/* Copyright (c) 2004,2005,2006 Eric B. Weddington
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iom165.h 2231 2011-03-07 05:06:55Z arcanum $ */
+
+/* avr/iom165.h - definitions for ATmega165 */
+
+#ifndef _AVR_IOM165_H_
+#define _AVR_IOM165_H_ 1
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iom165.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PA7     7
+#define PA6     6
+#define PA5     5
+#define PA4     4
+#define PA3     3
+#define PA2     2
+#define PA1     1
+#define PA0     0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7     7
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC3     3
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7     7
+#define PE6     6
+#define PE5     5
+#define PE4     4
+#define PE3     3
+#define PE2     2
+#define PE1     1
+#define PE0     0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7     7
+#define PF6     6
+#define PF5     5
+#define PF4     4
+#define PF3     3
+#define PF2     2
+#define PF1     1
+#define PF0     0
+
+#define PING    _SFR_IO8(0x12)
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDG4    4
+#define DDG3    3
+#define DDG2    2
+#define DDG1    1
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PG4     4
+#define PG3     3
+#define PG2     2
+#define PG1     1
+#define PG0     0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+
+/* Reserved [0x18..0x1B] */
+
+#define EIFR   _SFR_IO8(0x1C)
+#define INTF0   0
+#define PCIF0   6
+#define PCIF1   7
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define PCIE0   6
+#define PCIE1   7
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+
+#define EEDR    _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSR10   0
+#define PSR2    1
+#define TSM     7
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM01   3
+#define COM0A0  4
+#define COM0A1  5
+#define WGM00   6
+#define FOC0A   7
+
+/* Reserved [0x25] */
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0X27)
+
+/* Reserved [0x28..0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0X2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define OCDR    _SFR_IO8(0x31)
+#define OCDR0   0
+#define OCDR1   1
+#define OCDR2   2
+#define OCDR3   3
+#define OCDR4   4
+#define OCDR5   5
+#define OCDR6   6
+#define OCD     7   // The datasheet defines this but IMO it should be OCDR7.
+#define OCDR7   7
+#define IDRD    7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+#define JTRF    4
+
+#define MCUCR   _SFR_IO8(0X35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+#define JTD     7
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDE     3
+#define WDCE    4
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62..0x63] */
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC       0
+#define PRUSART0    1
+#define PRSPI       2
+#define PRTIM1      3
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67..0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+
+/* Reserved [0x6A] */
+
+/* Combine PCMSK0 and PCMSK1 */
+#define PCMSK   _SFR_MEM16(0x6B)
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+
+/* Reserved [0x71..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0X80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0X81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM21   3
+#define COM2A0  4
+#define COM2A1  5
+#define WGM20   6
+#define FOC2A   7
+
+/* Reserved [0xB1] */
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+/* Reserved [0xB4..0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2UB  0
+#define OCR2UB  1
+#define TCN2UB  2
+#define AS2     3
+#define EXCLK   4
+
+/* Reserved [0xB7] */
+
+#define USICR   _SFR_MEM8(0xB8)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_MEM8(0xB9)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_MEM8(0xBA)
+
+/* Reserved [0xBB..0xBF] */
+
+#define UCSRA   _SFR_MEM8(0xC0)
+#define MPCM    0
+#define U2X     1
+#define UPE     2
+#define DOR     3
+#define FE      4
+#define UDRE    5
+#define TXC     6
+#define RXC     7
+
+#define UCSRB   _SFR_MEM8(0XC1)
+#define TXB8    0
+#define RXB8    1
+#define UCSZ2   2
+#define TXEN    3
+#define RXEN    4
+#define UDRIE   5
+#define TXCIE   6
+#define RXCIE   7
+
+#define UCSRC   _SFR_MEM8(0xC2)
+#define UCPOL   0
+#define UCSZ0   1
+#define UCSZ1   2
+#define USBS    3
+#define UPM0    4
+#define UPM1    5
+#define UMSEL   6
+
+/* Reserved [0xC3] */
+
+/* Combine UBRRL and UBRRH */
+#define UBRR    _SFR_MEM16(0xC4)
+
+#define UBRRL   _SFR_MEM8(0xC4)
+#define UBRRH   _SFR_MEM8(0xC5)
+
+#define UDR     _SFR_MEM8(0XC6)
+
+/* Reserved [0xC7..0xFF] */
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		2
+#define PCINT0_vect			_VECTOR(2)
+#define SIG_PIN_CHANGE0			_VECTOR(2)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		3
+#define PCINT1_vect			_VECTOR(3)
+#define SIG_PIN_CHANGE1			_VECTOR(3)
+
+/* Timer/Counter2 Compare Match */
+#define TIMER2_COMP_vect_num	4
+#define TIMER2_COMP_vect		_VECTOR(4)
+#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		5
+#define TIMER2_OVF_vect			_VECTOR(5)
+#define SIG_OVERFLOW2			_VECTOR(5)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	6
+#define TIMER1_CAPT_vect		_VECTOR(6)
+#define SIG_INPUT_CAPTURE1		_VECTOR(6)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	7
+#define TIMER1_COMPA_vect		_VECTOR(7)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(7)
+
+/* Timer/Counter Compare Match B */
+#define TIMER1_COMPB_vect_num	8
+#define TIMER1_COMPB_vect		_VECTOR(8)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(8)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		9
+#define TIMER1_OVF_vect			_VECTOR(9)
+#define SIG_OVERFLOW1			_VECTOR(9)
+
+/* Timer/Counter0 Compare Match */
+#define TIMER0_COMP_vect_num	10
+#define TIMER0_COMP_vect		_VECTOR(10)
+#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		11
+#define TIMER0_OVF_vect			_VECTOR(11)
+#define SIG_OVERFLOW0			_VECTOR(11)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		12
+#define SPI_STC_vect			_VECTOR(12)
+#define SIG_SPI				    _VECTOR(12)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		13
+#define USART0_RX_vect			_VECTOR(13)
+#define USART_RX_vect			_VECTOR(13)  /* Alias */
+#define SIG_UART_RECV			_VECTOR(13)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	14
+#define USART0_UDRE_vect		_VECTOR(14)
+#define USART_UDRE_vect		    _VECTOR(14)  /* Alias */
+#define SIG_UART_DATA			_VECTOR(14)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		15
+#define USART0_TX_vect			_VECTOR(15)
+#define USART_TX_vect			_VECTOR(15)  /* Alias */
+#define SIG_UART_TRANS			_VECTOR(15)
+
+/* USI Start Condition */
+#define USI_START_vect_num		16
+#define USI_START_vect			_VECTOR(16)
+#define SIG_USI_START			_VECTOR(16)
+
+/* USI Overflow */
+#define USI_OVERFLOW_vect_num	17
+#define USI_OVERFLOW_vect		_VECTOR(17)
+#define SIG_USI_OVERFLOW		_VECTOR(17)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	18
+#define ANALOG_COMP_vect		_VECTOR(18)
+#define SIG_COMPARATOR			_VECTOR(18)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		19
+#define ADC_vect			_VECTOR(19)
+#define SIG_ADC				_VECTOR(19)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		20
+#define EE_READY_vect			_VECTOR(20)
+#define SIG_EEPROM_READY		_VECTOR(20)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		21
+#define SPM_READY_vect			_VECTOR(21)
+#define SIG_SPM_READY			_VECTOR(21)
+
+#define _VECTORS_SIZE 88
+
+
+/* Constants */
+#define SPM_PAGESIZE    128
+#define RAMSTART        0x100
+#define RAMEND          0x4FF
+#define XRAMEND         RAMEND
+#define E2END           0x1FF
+#define E2PAGESIZE      4
+#define FLASHEND        0x3FFF
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST 
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x05
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_OUTPUT_COMPARE2
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison USART_RX_vect
+#pragma GCC poison SIG_UART_RECV
+#pragma GCC poison USART_UDRE_vect
+#pragma GCC poison SIG_UART_DATA
+#pragma GCC poison USART_TX_vect
+#pragma GCC poison SIG_UART_TRANS
+#pragma GCC poison SIG_USI_START
+#pragma GCC poison SIG_USI_OVERFLOW
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_SPM_READY
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
+
+#endif /* _AVR_IOM165_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom165a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom165a.h
@@ -32,7 +32,7 @@
  ****************************************************************************/
 
 
-/* $Id$ */
+/* $Id: iom165a.h 2442 2014-08-11 21:42:11Z joerg_wunsch $ */
 
 #ifndef _AVR_ATMEGA165A_H_INCLUDED
 #define _AVR_ATMEGA165A_H_INCLUDED
@@ -295,9 +295,10 @@
 #define EEARH   _SFR_IO8(0x22)
 
 #define GTCCR   _SFR_IO8(0x23)
-#define PSR310  0
-#define TSM     7
+#define PSR310  0 /* Kept for legacy reason */
+#define PSR10  0
 #define PSR2    1
+#define TSM     7
 
 #define TCCR0A  _SFR_IO8(0x24)
 #define CS00    0
@@ -823,12 +824,10 @@
 #define SIGNATURE_2 0x10
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
-
 #endif /* #ifdef _AVR_ATMEGA165A_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom165p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom165p.h
@@ -29,7 +29,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom165p.h 2231 2011-03-07 05:06:55Z arcanum $ */
 
 /* avr/iom165p.h - definitions for ATmega165P */
 
@@ -880,12 +880,10 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM165P_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom165pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom165pa.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA165PA_H_INCLUDED
 #define _AVR_ATMEGA165PA_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRA    _SFR_IO8(0x01)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x02)
 #define PORTA7  7
@@ -92,13 +91,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -122,13 +137,29 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC7  7
@@ -152,13 +183,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -182,13 +229,29 @@
 
 #define DDRE    _SFR_IO8(0x0D)
 #define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
 #define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
 #define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
 #define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
 #define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
 #define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
 #define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
 #define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
 
 #define PORTE   _SFR_IO8(0x0E)
 #define PORTE7  7
@@ -212,13 +275,29 @@
 
 #define DDRF    _SFR_IO8(0x10)
 #define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
 #define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
 #define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
 #define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
 #define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
 #define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
 #define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
 #define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
 
 #define PORTF   _SFR_IO8(0x11)
 #define PORTF7  7
@@ -240,10 +319,20 @@
 
 #define DDRG    _SFR_IO8(0x13)
 #define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
 #define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
 #define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
 #define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
 #define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
 
 #define PORTG   _SFR_IO8(0x14)
 #define PORTG4  4
@@ -678,6 +767,15 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -764,21 +862,44 @@
 #define SPM_READY_vect            _VECTOR(21)
 #define SPM_READY_vect_num        21
 
-#define _VECTORS_SIZE 88
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 88
+#else
+#  define _VECTORS_SIZE 88U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      1024
-#define RAMEND       0x04FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      1024
+#  define RAMEND       0x04FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x04FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -795,6 +916,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -805,12 +928,16 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_JTAGEN      (unsigned char)~_BV(6)
 #define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_RSTDISBL    (unsigned char)~_BV(0)
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
 #define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
 #define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -826,11 +953,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
 
 #endif /* #ifdef _AVR_ATMEGA165PA_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom168.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom168.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2004, Theodore A. Roth
+/* Copyright (c) 2004,2005 Theodore A. Roth
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,12 +28,769 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom168.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 #ifndef _AVR_IOM168_H_
 #define _AVR_IOM168_H_ 1
 
-#include <avr/iomx8.h>
+/* I/O registers */
+
+/* Port B */
+
+#define PINB    _SFR_IO8 (0x03)
+/* PINB */
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8 (0x04)
+/* DDRB */
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8 (0x05)
+/* PORTB */
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+/* Port C */
+
+#define PINC    _SFR_IO8 (0x06)
+/* PINC */
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8 (0x07)
+/* DDRC */
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8 (0x08)
+/* PORTC */
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC3     3
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+/* Port D */
+
+#define PIND    _SFR_IO8 (0x09)
+/* PIND */
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8 (0x0A)
+/* DDRD */
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8 (0x0B)
+/* PORTD */
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+#define TIFR0   _SFR_IO8 (0x15)
+/* TIFR0 */
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8 (0x16)
+/* TIFR1 */
+#define ICF1    5
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8 (0x17)
+/* TIFR2 */
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define PCIFR   _SFR_IO8 (0x1B)
+/* PCIFR */
+#define PCIF2   2
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8 (0x1C)
+/* EIFR */
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8 (0x1D)
+/* EIMSK */
+#define INT1    1
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8 (0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+/* EECT - EEPROM Control Register */
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0X22)
+/* 
+Even though EEARH is not used by the mega48, the EEAR8 bit in the register
+must be written to 0, according to the datasheet, hence the EEARH register
+must be defined for the mega48.
+*/
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+
+#define GTCCR   _SFR_IO8 (0x23)
+/* GTCCR */
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8 (0x24)
+/* TCCR0A */
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8 (0x25)
+/* TCCR0A */
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8 (0x26)
+#define OCR0A   _SFR_IO8 (0x27)
+#define OCR0B   _SFR_IO8 (0x28)
+
+#define GPIOR1  _SFR_IO8 (0x2A)
+#define GPIOR2  _SFR_IO8 (0x2B)
+
+#define SPCR    _SFR_IO8 (0x2C)
+/* SPCR */
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8 (0x2D)
+/* SPSR */
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8 (0x2E)
+
+#define ACSR    _SFR_IO8 (0x30)
+/* ACSR */
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8 (0x31)
+
+#define SMCR    _SFR_IO8 (0x33)
+/* SMCR */
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8 (0x34)
+/* MCUSR */
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8 (0x35)
+/* MCUCR */
+#define PUD     4
+#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)  || defined (__AVR_ATmega48A__) || defined(__AVR_ATmega48PA__)
+#define IVSEL   1
+#define IVCE    0
+#endif
+
+#define SPMCSR  _SFR_IO8 (0x37)
+/* SPMCSR */
+#define SPMIE     7
+#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || (__AVR_ATmega88P__) || defined (__AVR_ATmega168P__) || (__AVR_ATmega88A__) || defined (__AVR_ATmega168A__) || (__AVR_ATmega88PA__) || defined (__AVR_ATmega168PA__)
+#  define RWWSB   6
+#  define RWWSRE  4
+#endif
+#if defined(__AVR_ATmega48A) || defined(__AVR_ATmega48PA) || defined(__AVR_ATmega88A) || defined(__AVR_ATmega88PA) || defined(__AVR_ATmega168A) || defined(__AVR_ATmega168PA)
+	#define SIGRD 5
+#endif
+#define BLBSET    3
+#define PGWRT     2
+#define PGERS     1
+#define SELFPRGEN 0
+#define SPMEN     0
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+#define WDTCSR  _SFR_MEM8 (0x60)
+/* WDTCSR */
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8 (0x61)
+/* CLKPR */
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define PRR     _SFR_MEM8 (0x64)
+/* PRR */
+#define PRTWI    7
+#define PRTIM2   6
+#define PRTIM0   5
+#define PRTIM1   3
+#define PRSPI    2
+#define PRUSART0 1
+#define PRADC    0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRTWI
+
+#define OSCCAL  _SFR_MEM8 (0x66)
+
+#define PCICR   _SFR_MEM8 (0x68)
+/* PCICR */
+#define PCIE2   2
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8 (0x69)
+/* EICRA */
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define PCMSK0  _SFR_MEM8 (0x6B)
+/* PCMSK0 */
+#define PCINT7    7
+#define PCINT6    6
+#define PCINT5    5
+#define PCINT4    4
+#define PCINT3    3
+#define PCINT2    2
+#define PCINT1    1
+#define PCINT0    0
+
+#define PCMSK1  _SFR_MEM8 (0x6C)
+/* PCMSK1 */
+#define PCINT14   6
+#define PCINT13   5
+#define PCINT12   4
+#define PCINT11   3
+#define PCINT10   2
+#define PCINT9    1
+#define PCINT8    0
+
+#define PCMSK2  _SFR_MEM8 (0x6D)
+/* PCMSK2 */
+#define PCINT23   7
+#define PCINT22   6
+#define PCINT21   5
+#define PCINT20   4
+#define PCINT19   3
+#define PCINT18   2
+#define PCINT17   1
+#define PCINT16   0
+
+#define TIMSK0  _SFR_MEM8 (0x6E)
+/* TIMSK0 */
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8 (0x6F)
+/* TIMSK1 */
+#define ICIE1   5
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8 (0x70)
+/* TIMSK2 */
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16 (0x78)
+#endif
+#define ADCW    _SFR_MEM16 (0x78)
+#define ADCL    _SFR_MEM8 (0x78)
+#define ADCH    _SFR_MEM8 (0x79)
+
+#define ADCSRA  _SFR_MEM8 (0x7A)
+/* ADCSRA */
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8 (0x7B)
+/* ADCSRB */
+#define ACME    6
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8 (0x7C)
+/* ADMUX */
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define DIDR0   _SFR_MEM8 (0x7E)
+/* DIDR0 */
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8 (0x7F)
+/* DIDR1 */
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8 (0x80)
+/* TCCR1A */
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8 (0x81)
+/* TCCR1B */
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8 (0x82)
+/* TCCR1C */
+#define FOC1A   7
+#define FOC1B   6
+
+#define TCNT1   _SFR_MEM16 (0x84)
+#define TCNT1L  _SFR_MEM8 (0x84)
+#define TCNT1H  _SFR_MEM8 (0x85)
+
+#define ICR1    _SFR_MEM16 (0x86)
+#define ICR1L   _SFR_MEM8 (0x86)
+#define ICR1H   _SFR_MEM8 (0x87)
+
+#define OCR1A   _SFR_MEM16 (0x88)
+#define OCR1AL  _SFR_MEM8 (0x88)
+#define OCR1AH  _SFR_MEM8 (0x89)
+
+#define OCR1B   _SFR_MEM16 (0x8A)
+#define OCR1BL  _SFR_MEM8 (0x8A)
+#define OCR1BH  _SFR_MEM8 (0x8B)
+
+#define TCCR2A  _SFR_MEM8 (0xB0)
+/* TCCR2A */
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8 (0xB1)
+/* TCCR2B */
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8 (0xB2)
+#define OCR2A   _SFR_MEM8 (0xB3)
+#define OCR2B   _SFR_MEM8 (0xB4)
+
+#define ASSR    _SFR_MEM8 (0xB6)
+/* ASSR */
+#define EXCLK    6
+#define AS2      5
+#define TCN2UB   4
+#define OCR2AUB  3
+#define OCR2BUB  2
+#define TCR2AUB  1
+#define TCR2BUB  0
+
+#define TWBR    _SFR_MEM8 (0xB8)
+
+#define TWSR    _SFR_MEM8 (0xB9)
+/* TWSR */
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8 (0xBA)
+/* TWAR */
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8 (0xBB)
+
+#define TWCR    _SFR_MEM8 (0xBC)
+/* TWCR */
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8 (0xBD)
+/* TWAMR */
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+#define UCSR0A  _SFR_MEM8 (0xC0)
+/* UCSR0A */
+#define RXC0    7
+#define TXC0    6
+#define UDRE0   5
+#define FE0     4
+#define DOR0    3
+#define UPE0    2
+#define U2X0    1
+#define MPCM0   0
+
+#define UCSR0B  _SFR_MEM8 (0xC1)
+/* UCSR0B */
+#define RXCIE0  7
+#define TXCIE0  6
+#define UDRIE0  5
+#define RXEN0   4
+#define TXEN0   3
+#define UCSZ02  2
+#define RXB80   1
+#define TXB80   0
+
+#define UCSR0C  _SFR_MEM8 (0xC2)
+/* UCSR0C */
+#define UMSEL01  7
+#define UMSEL00  6
+#define UPM01    5
+#define UPM00    4
+#define USBS0    3
+#define UCSZ01   2
+#define UDORD0   2
+#define UCSZ00   1
+#define UCPHA0   1
+#define UCPOL0   0
+
+#define UBRR0   _SFR_MEM16 (0xC4)
+#define UBRR0L  _SFR_MEM8 (0xC4)
+#define UBRR0H  _SFR_MEM8 (0xC5)
+#define UDR0    _SFR_MEM8 (0xC6)
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		3
+#define PCINT0_vect			_VECTOR(3)
+#define SIG_PIN_CHANGE0			_VECTOR(3)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num		4
+#define PCINT1_vect			_VECTOR(4)
+#define SIG_PIN_CHANGE1			_VECTOR(4)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT2_vect_num		5
+#define PCINT2_vect			_VECTOR(5)
+#define SIG_PIN_CHANGE2			_VECTOR(5)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		6
+#define WDT_vect			_VECTOR(6)
+#define SIG_WATCHDOG_TIMEOUT		_VECTOR(6)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	7
+#define TIMER2_COMPA_vect		_VECTOR(7)
+#define SIG_OUTPUT_COMPARE2A		_VECTOR(7)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect_num	8
+#define TIMER2_COMPB_vect		_VECTOR(8)
+#define SIG_OUTPUT_COMPARE2B		_VECTOR(8)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		9
+#define TIMER2_OVF_vect			_VECTOR(9)
+#define SIG_OVERFLOW2			_VECTOR(9)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	10
+#define TIMER1_CAPT_vect		_VECTOR(10)
+#define SIG_INPUT_CAPTURE1		_VECTOR(10)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	11
+#define TIMER1_COMPA_vect		_VECTOR(11)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(11)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	12
+#define TIMER1_COMPB_vect		_VECTOR(12)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(12)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		13
+#define TIMER1_OVF_vect			_VECTOR(13)
+#define SIG_OVERFLOW1			_VECTOR(13)
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	14
+#define TIMER0_COMPA_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(14)
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	15
+#define TIMER0_COMPB_vect		_VECTOR(15)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(15)
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect_num		16
+#define TIMER0_OVF_vect			_VECTOR(16)
+#define SIG_OVERFLOW0			_VECTOR(16)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		17
+#define SPI_STC_vect			_VECTOR(17)
+#define SIG_SPI				_VECTOR(17)
+
+/* USART Rx Complete */
+#define USART_RX_vect_num		18
+#define USART_RX_vect			_VECTOR(18)
+#define SIG_USART_RECV			_VECTOR(18)
+
+/* USART, Data Register Empty */
+#define USART_UDRE_vect_num		19
+#define USART_UDRE_vect			_VECTOR(19)
+#define SIG_USART_DATA			_VECTOR(19)
+
+/* USART Tx Complete */
+#define USART_TX_vect_num		20
+#define USART_TX_vect			_VECTOR(20)
+#define SIG_USART_TRANS			_VECTOR(20)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		21
+#define ADC_vect			_VECTOR(21)
+#define SIG_ADC				_VECTOR(21)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		22
+#define EE_READY_vect			_VECTOR(22)
+#define SIG_EEPROM_READY		_VECTOR(22)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	23
+#define ANALOG_COMP_vect		_VECTOR(23)
+#define SIG_COMPARATOR			_VECTOR(23)
+
+/* Two-wire Serial Interface */
+#define TWI_vect_num		24
+#define TWI_vect			_VECTOR(24)
+#define SIG_TWI				_VECTOR(24)
+#define SIG_2WIRE_SERIAL		_VECTOR(24)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		25
+#define SPM_READY_vect			_VECTOR(25)
+#define SIG_SPM_READY			_VECTOR(25)
+
+/* The mega48 and mega88 vector tables are single instruction entries (16 bits
+   per entry for an RJMP) while the mega168 table has double instruction
+   entries (32 bits per entry for a JMP). */
+
+#if defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__)
+#  define _VECTORS_SIZE 104
+#else
+#  define _VECTORS_SIZE 52
+#endif
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART_RECV
+#pragma GCC poison SIG_USART_DATA
+#pragma GCC poison SIG_USART_TRANS
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_TWI
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
+
 
 /* Constants */
 #define SPM_PAGESIZE 128
@@ -88,12 +845,10 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x06
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM168_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom168a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom168a.h
@@ -1,35 +1,35 @@
-/*****************************************************************************
- *
- * Copyright (C) 2011 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-#include "iom168.h"
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom168.h"
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom168p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom168p.h
@@ -29,7 +29,7 @@
   POSSIBILITY OF SUCH DAMAGE. 
 */
 
-/* $Id$ */
+/* $Id: iom168p.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/iom168p.h - definitions for ATmega168P. */
 
@@ -932,7 +932,6 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x0B
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -940,5 +939,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif  /* _AVR_IOM168P_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom168pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom168pa.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA168PA_H_INCLUDED
 #define _AVR_ATMEGA168PA_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -91,12 +90,26 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC6  6
@@ -119,13 +132,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -274,11 +303,12 @@
 /* Reserved [0x36] */
 
 #define SPMCSR  _SFR_IO8(0x37)
-#define SELFPRGEN 0
+#define SPMEN   0
 #define PGERS   1
 #define PGWRT   2
 #define BLBSET  3
 #define RWWSRE  4
+#define SIGRD   5
 #define RWWSB   6
 #define SPMIE   7
 
@@ -616,6 +646,16 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -718,21 +758,44 @@
 #define SPM_Ready_vect            _VECTOR(25)
 #define SPM_Ready_vect_num        25
 
-#define _VECTORS_SIZE 104
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 104
+#else
+#  define _VECTORS_SIZE 104U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      1024
-#define RAMEND       0x04FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      1024
+#  define RAMEND       0x04FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x04FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -749,6 +812,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
@@ -759,11 +824,15 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_DWEN        (unsigned char)~_BV(6)
 #define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
 #define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
 #define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
+
 
 
 /* Lock Bits */
@@ -779,12 +848,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 #endif /* #ifdef _AVR_ATMEGA168PA_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom168pb.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom168pb.h
@@ -0,0 +1,907 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATMEGA168PB_H_INCLUDED
+#define _AVR_ATMEGA168PB_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iom168pb.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
+#define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
+#define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
+#define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+/* Reserved [0x0F..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM     7
+#define PSRASY  1
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define ACSRB   _SFR_IO8(0x2F)
+#define ACOE    0
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+/* Reserved [0x31..0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+#define BODSE   5
+#define BODS    6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62..0x63] */
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+/* Reserved [0x71..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+#define UCSR0D  _SFR_MEM8(0xC3)
+#define SFDE    5
+#define RXS     6
+#define RXSIE   7
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7..0xEF] */
+
+#define DEVID0  _SFR_MEM8(0xF0)
+
+#define DEVID1  _SFR_MEM8(0xF1)
+
+#define DEVID2  _SFR_MEM8(0xF2)
+
+#define DEVID3  _SFR_MEM8(0xF3)
+
+#define DEVID4  _SFR_MEM8(0xF4)
+
+#define DEVID5  _SFR_MEM8(0xF5)
+
+#define DEVID6  _SFR_MEM8(0xF6)
+
+#define DEVID7  _SFR_MEM8(0xF7)
+
+#define DEVID8  _SFR_MEM8(0xF8)
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT2_vect            _VECTOR(5)
+#define PCINT2_vect_num        5
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(6)
+#define WDT_vect_num        6
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(7)
+#define TIMER2_COMPA_vect_num        7
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect            _VECTOR(8)
+#define TIMER2_COMPB_vect_num        8
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(9)
+#define TIMER2_OVF_vect_num        9
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(10)
+#define TIMER1_CAPT_vect_num        10
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(11)
+#define TIMER1_COMPA_vect_num        11
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(12)
+#define TIMER1_COMPB_vect_num        12
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(13)
+#define TIMER1_OVF_vect_num        13
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(14)
+#define TIMER0_COMPA_vect_num        14
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(15)
+#define TIMER0_COMPB_vect_num        15
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(16)
+#define TIMER0_OVF_vect_num        16
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(17)
+#define SPI_STC_vect_num        17
+
+/* USART Rx Complete */
+#define USART_RX_vect            _VECTOR(18)
+#define USART_RX_vect_num        18
+
+/* USART, Data Register Empty */
+#define USART_UDRE_vect            _VECTOR(19)
+#define USART_UDRE_vect_num        19
+
+/* USART Tx Complete */
+#define USART_TX_vect            _VECTOR(20)
+#define USART_TX_vect_num        20
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(21)
+#define ADC_vect_num        21
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(22)
+#define EE_READY_vect_num        22
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect            _VECTOR(23)
+#define ANALOG_COMP_vect_num        23
+
+/* Two-wire Serial Interface */
+#define TWI_vect            _VECTOR(24)
+#define TWI_vect_num        24
+
+/* Store Program Memory Read */
+#define SPM_Ready_vect            _VECTOR(25)
+#define SPM_Ready_vect_num        25
+
+/* USART Start Edge Interrupt */
+#define USART_START_vect            _VECTOR(26)
+#define USART_START_vect_num        26
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 108
+#else
+#  define _VECTORS_SIZE 108U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      1024
+#  define RAMEND       0x04FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x04FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x15
+
+
+
+
+#endif /* #ifdef _AVR_ATMEGA168PB_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom169.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom169.h
@@ -30,7 +30,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom169.h 2231 2011-03-07 05:06:55Z arcanum $ */
 
 /* iom169.h - definitions for ATmega169 */
 
@@ -1165,12 +1165,10 @@
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif  /* _AVR_IOM169_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom169a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom169a.h
@@ -0,0 +1,1175 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2002, 2003, 2004, 2005 Juergen Schilling <juergen.schilling@honeywell.com>, Eric B. Weddington, 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+/* $Id: iom169.h 2231 2011-03-07 05:06:55Z arcanum $ */
+
+/* iom169.h - definitions for ATmega169 */
+
+/* This should be up to date with data sheet version 2514J-AVR-12/03. */
+
+#ifndef _AVR_IOM169A_H_
+#define _AVR_IOM169A_H_ 1
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iom169a.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* I/O registers */
+
+/* Port A */
+#define PINA   _SFR_IO8(0x00)
+#define DDRA   _SFR_IO8(0x01)
+#define PORTA  _SFR_IO8(0x02)
+
+/* Port B */
+#define PINB   _SFR_IO8(0x03)
+#define DDRB   _SFR_IO8(0x04)
+#define PORTB  _SFR_IO8(0x05)
+
+/* Port C */
+#define PINC   _SFR_IO8(0x06)
+#define DDRC   _SFR_IO8(0x07)
+#define PORTC  _SFR_IO8(0x08)
+
+/* Port D */
+#define PIND   _SFR_IO8(0x09)
+#define DDRD   _SFR_IO8(0x0A)
+#define PORTD  _SFR_IO8(0x0B)
+
+/* Port E */
+#define PINE   _SFR_IO8(0x0C)
+#define DDRE   _SFR_IO8(0x0D)
+#define PORTE  _SFR_IO8(0x0E)
+
+/* Port F */
+#define PINF   _SFR_IO8(0x0F)
+#define DDRF   _SFR_IO8(0x10)
+#define PORTF  _SFR_IO8(0x11)
+
+/* Port G */
+#define PING   _SFR_IO8(0x12)
+#define DDRG   _SFR_IO8(0x13)
+#define PORTG  _SFR_IO8(0x14)
+
+/* Timer/Counter 0 interrupt Flag Register */
+#define TIFR0  _SFR_IO8(0x15)
+
+/* Timer/Counter 1 interrupt Flag Register */
+#define TIFR1  _SFR_IO8(0x16)
+
+/* Timer/Counter 2 interrupt Flag Register */
+#define TIFR2  _SFR_IO8(0x17)
+
+/* External Interrupt Flag Register */
+#define EIFR   _SFR_IO8(0x1C)
+
+/* External Interrupt Mask Register */
+#define EIMSK  _SFR_IO8(0x1D)
+
+/* General Purpose I/O Register 0 */
+#define GPIOR0 _SFR_IO8(0x1E)
+
+#define EECR   _SFR_IO8(0x1F)
+
+#define EEDR   _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR   _SFR_IO16(0x21)
+#define EEARL  _SFR_IO8(0x21)
+#define EEARH  _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+/* General Timer/Counter Control Register */
+#define GTCCR  _SFR_IO8(0x23)
+
+/* Timer/Counter Control Register A */
+#define TCCR0A _SFR_IO8(0x24)
+
+/* Timer/Counter Register */
+#define TCNT0  _SFR_IO8(0x26)
+
+/* Output Compare Register A */
+#define OCR0A  _SFR_IO8(0x27)
+
+/* General Purpose I/O Register 1 */
+#define GPIOR1 _SFR_IO8(0x2A)
+
+/* General Purpose I/O Register 2 */
+#define GPIOR2 _SFR_IO8(0x2B)
+
+/* SPI Control Register */
+#define SPCR   _SFR_IO8(0x2C)
+
+/* SPI Status Register */
+#define SPSR   _SFR_IO8(0x2D)
+
+/* SPI Data Register */
+#define SPDR   _SFR_IO8(0x2E)
+
+/* Analog Comperator Control and Status Register */
+#define ACSR   _SFR_IO8(0x30)
+
+/* On-chip Debug Register */
+#define OCDR   _SFR_IO8(0x31)
+
+/* Sleep Mode Control Register */
+#define SMCR   _SFR_IO8(0x33)
+
+/* MCU Status Register */
+#define MCUSR  _SFR_IO8(0x34)
+
+/* MCU Control Rgeister */
+#define MCUCR  _SFR_IO8(0x35)
+
+/* Store Program Memory Control and Status Register */
+#define SPMCSR _SFR_IO8(0x37)
+
+/* Watchdog Timer Control Register */
+#define WDTCR  _SFR_MEM8(0x60)
+
+/* Clock Prescale Register */
+#define CLKPR  _SFR_MEM8(0x61)
+
+#define PRR    _SFR_MEM8(0x64)
+#define PRADC       0
+#define PRUSART0    1
+#define PRSPI       2
+#define PRTIM1      3
+#define PRLCD       4
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRLCD))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRLCD
+
+/* Oscillator Calibration Register */
+#define OSCCAL _SFR_MEM8(0x66)
+
+/* External Interrupt Control Register A */
+#define EICRA  _SFR_MEM8(0x69)
+
+/* Pin Change Mask Register */
+#define PCMSK  _SFR_MEM16(0x6B)
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCMSK1 _SFR_MEM8(0x6C)
+
+/* Timer/Counter 0 Interrupt Mask Register */
+#define TIMSK0 _SFR_MEM8(0x6E)
+
+/* Timer/Counter 1 Interrupt Mask Register */
+#define TIMSK1 _SFR_MEM8(0x6F)
+
+/* Timer/Counter 2 Interrupt Mask Register */
+#define TIMSK2 _SFR_MEM8(0x70)
+
+/* ADC Data Register */
+#ifndef __ASSEMBLER__
+#define ADC    _SFR_MEM16(0x78)
+#endif
+#define ADCW   _SFR_MEM16(0x78)
+#define ADCL   _SFR_MEM8(0x78)
+#define ADCH   _SFR_MEM8(0x79)
+
+/* ADC Control and Status Register A */
+#define ADCSRA _SFR_MEM8(0x7A)
+
+/* ADC Control and Status Register B */
+#define ADCSRB _SFR_MEM8(0x7B)
+
+/* ADC Multiplex Selection Register */
+#define ADMUX  _SFR_MEM8(0x7C)
+
+/* NOTE: DIDR0 and DIDR1 are swapped in the register summary of the data sheet
+   (2514D-AVR-01/03), but seem to be correct in the discussions of the
+   registers. */
+
+/* Digital Input Disable Register 0 */
+#define DIDR0  _SFR_MEM8(0x7E)
+
+/* Digital Input Disable Register 1 */
+#define DIDR1  _SFR_MEM8(0x7F)
+
+/* Timer/Counter1 Control Register A */
+#define TCCR1A _SFR_MEM8(0x80)
+
+/* Timer/Counter1 Control Register B */
+#define TCCR1B _SFR_MEM8(0x81)
+
+/* Timer/Counter1 Control Register C */
+#define TCCR1C _SFR_MEM8(0x82)
+
+/* Timer/Counter1 Register */
+#define TCNT1  _SFR_MEM16(0x84)
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1H _SFR_MEM8(0x85)
+
+/* Timer/Counter1 Input Capture Register */
+#define ICR1   _SFR_MEM16(0x86)
+#define ICR1L  _SFR_MEM8(0x86)
+#define ICR1H  _SFR_MEM8(0x87)
+
+/* Timer/Counter1 Output Compare Register A */
+#define OCR1A  _SFR_MEM16(0x88)
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AH _SFR_MEM8(0x89)
+
+/* Timer/Counter1 Output Compare Registare B */
+#define OCR1B  _SFR_MEM16(0x8A)
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BH _SFR_MEM8(0x8B)
+
+/* Timer/Counter2 Control Register A */
+#define TCCR2A _SFR_MEM8(0xB0)
+
+/* Timer/Counter2 Register */
+#define TCNT2  _SFR_MEM8(0xB2)
+
+/* Timer/Counter2 Output Compare Register */
+#define OCR2A  _SFR_MEM8(0xB3)
+
+/* Asynchronous Status Register */
+#define ASSR   _SFR_MEM8(0xB6)
+
+/* USI Control Register */
+#define USICR  _SFR_MEM8(0xB8)
+
+/* USI Status Register */
+#define USISR  _SFR_MEM8(0xB9)
+
+/* USI Data Register */
+#define USIDR  _SFR_MEM8(0xBA)
+
+/* USART0 Control and Status Register A */
+#define UCSRA  _SFR_MEM8(0xC0)
+
+/* USART0 Control and Status Register B */
+#define UCSRB  _SFR_MEM8(0xC1)
+
+/* USART0 Control and Status Register C */
+#define UCSRC  _SFR_MEM8(0xC2)
+
+/* USART0 Baud Rate Register */
+#define UBRR   _SFR_MEM16(0xC4)
+#define UBRRL  _SFR_MEM8(0xC4)
+#define UBRRH  _SFR_MEM8(0xC5)
+
+/* USART0 I/O Data Register */
+#define UDR    _SFR_MEM8(0xC6)
+
+/* LCD Control and Status Register A */
+#define LCDCRA _SFR_MEM8(0xE4)
+
+/* LCD Control and Status Register B */
+#define LCDCRB _SFR_MEM8(0xE5)
+
+/* LCD Frame Rate Register */
+#define LCDFRR _SFR_MEM8(0xE6)
+
+/* LCD Contrast Control Register */
+#define LCDCCR _SFR_MEM8(0xE7)
+
+/* LCD Memory mapping */
+#define LCDDR0 _SFR_MEM8(0xEC)
+#define LCDDR1 _SFR_MEM8(0xED)
+#define LCDDR2 _SFR_MEM8(0xEE)
+#define LCDDR3 _SFR_MEM8(0xEF)
+#define LCDDR5 _SFR_MEM8(0xF1)
+#define LCDDR6 _SFR_MEM8(0xF2)
+#define LCDDR7 _SFR_MEM8(0xF3)
+#define LCDDR8 _SFR_MEM8(0xF4)
+#define LCDDR10 _SFR_MEM8(0xF6)
+#define LCDDR11 _SFR_MEM8(0xF7)
+#define LCDDR12 _SFR_MEM8(0xF8)
+#define LCDDR13 _SFR_MEM8(0xF9)
+#define LCDDR15 _SFR_MEM8(0xFB)
+#define LCDDR16 _SFR_MEM8(0xFC)
+#define LCDDR17 _SFR_MEM8(0xFD)
+#define LCDDR18 _SFR_MEM8(0xFE)
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		2
+#define PCINT0_vect			_VECTOR(2)
+#define SIG_PIN_CHANGE0			_VECTOR(2)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		3
+#define PCINT1_vect			_VECTOR(3)
+#define SIG_PIN_CHANGE1			_VECTOR(3)
+
+/* Timer/Counter2 Compare Match */
+#define TIMER2_COMP_vect_num	4
+#define TIMER2_COMP_vect		_VECTOR(4)
+#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		5
+#define TIMER2_OVF_vect			_VECTOR(5)
+#define SIG_OVERFLOW2			_VECTOR(5)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	6
+#define TIMER1_CAPT_vect		_VECTOR(6)
+#define SIG_INPUT_CAPTURE1		_VECTOR(6)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	7
+#define TIMER1_COMPA_vect		_VECTOR(7)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
+
+/* Timer/Counter Compare Match B */
+#define TIMER1_COMPB_vect_num	8
+#define TIMER1_COMPB_vect		_VECTOR(8)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		9
+#define TIMER1_OVF_vect			_VECTOR(9)
+#define SIG_OVERFLOW1			_VECTOR(9)
+
+/* Timer/Counter0 Compare Match */
+#define TIMER0_COMP_vect_num	10
+#define TIMER0_COMP_vect		_VECTOR(10)
+#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		11
+#define TIMER0_OVF_vect			_VECTOR(11)
+#define SIG_OVERFLOW0			_VECTOR(11)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		12
+#define SPI_STC_vect			_VECTOR(12)
+#define SIG_SPI				_VECTOR(12)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		13
+#define USART0_RX_vect			_VECTOR(13)
+#define SIG_USART_RECV			_VECTOR(13)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	14
+#define USART0_UDRE_vect		_VECTOR(14)
+#define SIG_USART_DATA			_VECTOR(14)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		15
+#define USART0_TX_vect			_VECTOR(15)
+#define SIG_USART_TRANS			_VECTOR(15)
+
+/* USI Start Condition */
+#define USI_START_vect_num		16
+#define USI_START_vect			_VECTOR(16)
+#define SIG_USI_START			_VECTOR(16)
+
+/* USI Overflow */
+#define USI_OVERFLOW_vect_num	17
+#define USI_OVERFLOW_vect		_VECTOR(17)
+#define SIG_USI_OVERFLOW		_VECTOR(17)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	18
+#define ANALOG_COMP_vect		_VECTOR(18)
+#define SIG_COMPARATOR			_VECTOR(18)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		19
+#define ADC_vect			_VECTOR(19)
+#define SIG_ADC				_VECTOR(19)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		20
+#define EE_READY_vect			_VECTOR(20)
+#define SIG_EEPROM_READY		_VECTOR(20)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		21
+#define SPM_READY_vect			_VECTOR(21)
+#define SIG_SPM_READY			_VECTOR(21)
+
+/* LCD Start of Frame */
+#define LCD_vect_num		22
+#define LCD_vect			_VECTOR(22)
+#define SIG_LCD				_VECTOR(22)
+
+#define _VECTORS_SIZE 92
+
+/* Bit numbers */
+
+/*
+   PA7 = SEG3
+   PA6 = SEG2
+   PA5 = SEG1
+   PA4 = SEG0
+   PA3 = COM3
+   PA2 = COM2
+   PA1 = COM1
+   PA0 = COM0
+*/
+
+/* PORTA */
+#define PA7	7
+#define PA6	6
+#define PA5	5
+#define PA4	4
+#define PA3	3
+#define PA2	2
+#define PA1	1
+#define PA0	0
+
+/* DDRA */
+#define DDA7	7
+#define DDA6	6
+#define DDA5	5
+#define DDA4	4
+#define DDA3	3
+#define DDA2	2
+#define DDA1	1
+#define DDA0	0
+
+/* PINA */
+#define PINA7	7
+#define PINA6	6
+#define PINA5	5
+#define PINA4	4
+#define PINA3	3
+#define PINA2	2
+#define PINA1	1
+#define PINA0	0
+
+/*
+   PB7 = OC2A / PCINT15
+   PB6 = OC1B / PCINT14
+   PB5 = OC1A / PCINT13
+   PB4 = OC0A / PCINT12
+   PB3 = MISO / PCINT11
+   PB2 = MOSI / PCINT10
+   PB1 = SCK / PCINT9
+   PB0 = SS# / PCINT8
+ */
+
+/* PORTB */
+#define PB7	7
+#define PB6	6
+#define PB5	5
+#define PB4	4
+#define PB3	3
+#define PB2	2
+#define PB1	1
+#define PB0	0
+
+/* DDRB */
+#define DDB7	7
+#define DDB6	6
+#define DDB5	5
+#define DDB4	4
+#define DDB3	3
+#define DDB2	2
+#define DDB1	1
+#define DDB0	0
+
+/* PINB */
+#define PINB7	7
+#define PINB6	6
+#define PINB5	5
+#define PINB4	4
+#define PINB3	3
+#define PINB2	2
+#define PINB1	1
+#define PINB0	0
+
+/*
+   PC7 = SEG5
+   PC6 = SEG6
+   PC5 = SEG7
+   PC4 = SEG8
+   PC3 = SEG9
+   PC2 = SEG10
+   PC1 = SEG11
+   PC0 = SEG12
+*/
+
+/* PORTC */
+#define PC7	 7
+#define PC6	 6
+#define PC5	 5
+#define PC4	 4
+#define PC3	 3
+#define PC2	 2
+#define PC1	 1
+#define PC0	 0
+
+/* DDRC */
+#define DDC7	7
+#define DDC6	6
+#define DDC5	5
+#define DDC4	4
+#define DDC3	3
+#define DDC2	2
+#define DDC1	1
+#define DDC0	0
+
+/* PINC */
+#define PINC7	7
+#define PINC6	6
+#define PINC5	5
+#define PINC4	4
+#define PINC3	3
+#define PINC2	2
+#define PINC1	1
+#define PINC0	0
+
+/*
+   PD7 = SEG15
+   PD6 = SEG16
+   PD5 = SEG17
+   PD4 = SEG18
+   PD3 = SEG19
+   PD2 = SEG20
+   PD1 = INT0 / SEG21
+   PD0 = ICP / SEG22
+ */
+
+/* PORTD */
+#define PD7	 7
+#define PD6	 6
+#define PD5	 5
+#define PD4	 4
+#define PD3	 3
+#define PD2	 2
+#define PD1	 1
+#define PD0	 0
+
+/* DDRD */
+#define DDD7	7
+#define DDD6	6
+#define DDD5	5
+#define DDD4	4
+#define DDD3	3
+#define DDD2	2
+#define DDD1	1
+#define DDD0	0
+
+/* PIND */
+#define PIND7	7
+#define PIND6	6
+#define PIND5	5
+#define PIND4	4
+#define PIND3	3
+#define PIND2	2
+#define PIND1	1
+#define PIND0	0
+
+/*
+   PE7 = CLK0 / PCINT7
+   PE6 = DO / PCINT6
+   PE5 = DI / SDA / PCINT5
+   PE4 = USCK / SCL / PCINT4
+   PE3 = AIN1 / PCINT3
+   PE2 = XCK / AIN0 / PCINT2
+   PE1 = TXD / PCINT1
+   PE0 = RXD / PCINT0
+ */
+
+/* PORTE */
+#define PE7 7
+#define PE6 6
+#define PE5 5
+#define PE4 4
+#define PE3 3
+#define PE2 2
+#define PE1 1
+#define PE0 0
+
+/* DDRE */
+#define DDE7	7
+#define DDE6	6
+#define DDE5	5
+#define DDE4	4
+#define DDE3	3
+#define DDE2	2
+#define DDE1	1
+#define DDE0	0
+
+/* PINE */
+#define PINE7	7
+#define PINE6	6
+#define PINE5	5
+#define PINE4	4
+#define PINE3	3
+#define PINE2	2
+#define PINE1	1
+#define PINE0	0
+
+/*
+   PF7 = ADC7 / TDI
+   PF6 = ADC6 / TDO
+   PF5 = ADC5 / TMS
+   PF4 = ADC4 / TCK
+   PF3 = ADC3
+   PF2 = ADC2
+   PF1 = ADC1
+   PF0 = ADC0
+ */
+
+/* PORTF */
+#define PF7 7
+#define PF6 6
+#define PF5 5
+#define PF4 4
+#define PF3 3
+#define PF2 2
+#define PF1 1
+#define PF0 0
+
+/* DDRF */
+#define DDF7	7
+#define DDF6	6
+#define DDF5	5
+#define DDF4	4
+#define DDF3	3
+#define DDF2	2
+#define DDF1	1
+#define DDF0	0
+
+/* PINF */
+#define PINF7	7
+#define PINF6	6
+#define PINF5	5
+#define PINF4	4
+#define PINF3	3
+#define PINF2	2
+#define PINF1	1
+#define PINF0	0
+
+/*
+   PG5 = RESET#
+   PG4 = T0 / SEG23
+   PG3 = T1 / SEG24
+   PG2 = SEG4
+   PG1 = SEG13
+   PG0 = SEG14
+ */
+
+/* PORTG */
+#define PG4 4
+#define PG3 3
+#define PG2 2
+#define PG1 1
+#define PG0 0
+
+/* DDRG */
+#define DDG4	4
+#define DDG3	3
+#define DDG2	2
+#define DDG1	1
+#define DDG0	0
+
+/* PING */
+#define PING5	5
+#define PING4	4
+#define PING3	3
+#define PING2	2
+#define PING1	1
+#define PING0	0
+
+/* TIFR0 */
+#define OCF0A	1
+#define TOV0	0
+
+/* TIFR1 */
+#define ICF1   5
+#define OCF1B  2
+#define OCF1A	1
+#define TOV1	0
+
+/* TIFR2 */
+#define OCF2A	1
+#define TOV2	0
+
+/* EIFR */
+#define PCIF1  7
+#define PCIF0  6
+#define INTF0  0
+
+/* EIMSK */
+#define PCIE1  5
+#define PCIE0 4
+#define INT0   0
+
+/* EECR */
+#define EERIE   3
+#define EEMWE   2
+#define EEWE    1
+#define EERE    0
+
+/* GTCCR */
+#define TSM    7
+#define PSR2   1
+#define PSR10  0
+
+/* TCCR0A */
+#define FOC0A	7
+#define WGM00	6
+#define COM0A1	5
+#define COM0A0	4
+#define WGM01	3
+#define CS02	2
+#define CS01	1
+#define CS00	0
+
+/* SPCR */
+#define SPIE	7
+#define SPE	   6
+#define DORD	5
+#define MSTR	4
+#define CPOL	3
+#define CPHA	2
+#define SPR1	1
+#define SPR0	0
+
+/* SPSR */
+#define SPIF	7
+#define WCOL	6
+#define SPI2X	0
+
+/* ACSR */
+#define ACD	   7
+#define ACBG	6
+#define ACO	   5
+#define ACI	   4
+#define ACIE	3
+#define ACIC	2
+#define ACIS1	1
+#define ACIS0	0
+
+/* OCDR */
+#define IDRD   7
+#define OCD    7
+#define OCDR6  6
+#define OCDR5  5
+#define OCDR4  4
+#define OCDR3  3
+#define OCDR2  2
+#define OCDR1  1
+#define OCDR0  0
+
+/* SMCR */
+#define SM2    3
+#define SM1    2
+#define SM0    1
+#define SE     0
+
+/* MCUSR */
+#define JTRF   4
+#define WDRF   3
+#define BORF   2
+#define EXTRF  1
+#define PORF   0
+
+/* MCUCR */
+#define JTD    7
+#define PUD    4
+#define IVSEL  1
+#define IVCE   0
+
+/* SPMCSR */
+#define SPMIE  7
+#define RWWSB  6
+#define RWWSRE 4
+#define BLBSET 3
+#define PGWRT  2
+#define PGERS  1
+#define SPMEN  0
+
+/* WDTCR */
+#define WDCE	4
+#define WDE	   3
+#define WDP2	2
+#define WDP1	1
+#define WDP0	0
+
+/* CLKPR */
+#define CLKPCE 7
+#define CLKPS3 3
+#define CLKPS2 2
+#define CLKPS1 1
+#define CLKPS0 0
+
+/* EICRA */
+#define ISC01  1
+#define ISC00  0
+
+/* PCMSK0 */
+#define PCINT7 7
+#define PCINT6 6
+#define PCINT5 5
+#define PCINT4 4
+#define PCINT3 3
+#define PCINT2 2
+#define PCINT1 1
+#define PCINT0 0
+
+/* PCMSK1 */
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9 1
+#define PCINT8 0
+
+/* TIMSK0 */
+#define OCIE0A 1
+#define TOIE0  0
+
+/* TIMSK1 */
+#define ICIE1  5
+#define OCIE1B 2
+#define OCIE1A 1
+#define TOIE1  0
+
+/* TIMSK2 */
+#define OCIE2A 1
+#define TOIE2  0
+
+/* ADCSRA */
+#define ADEN   7
+#define ADSC   6
+#define ADATE  5
+#define ADIF   4
+#define ADIE   3
+#define ADPS2  2
+#define ADPS1  1
+#define ADPS0  0
+
+/* ADCSRB */
+#define ACME   6
+#define ADTS2  2
+#define ADTS1  1
+#define ADTS0  0
+
+/* ADMUX */
+#define REFS1  7
+#define REFS0  6
+#define ADLAR  5
+#define MUX4   4
+#define MUX3   3
+#define MUX2   2
+#define MUX1   1
+#define MUX0   0
+
+/* DIDR1 */
+#define AIN1D  1
+#define AIN0D  0
+
+/* DIDR0 */
+#define ADC7D  7
+#define ADC6D  6
+#define ADC5D  5
+#define ADC4D  4
+#define ADC3D  3
+#define ADC2D  2
+#define ADC1D  1
+#define ADC0D  0
+
+/* TCCR1A */
+#define COM1A1	7
+#define COM1A0	6
+#define COM1B1	5
+#define COM1B0	4
+#define WGM11	1
+#define WGM10	0
+
+/* TCCR1B */
+#define ICNC1	7
+#define ICES1	6
+#define WGM13  4
+#define WGM12	3
+#define CS12	2
+#define CS11	1
+#define CS10	0
+
+/* TCCR1C */
+#define FOC1A  7
+#define FOC1B  6
+
+/* TCCR2A */
+#define FOC2A	7
+#define WGM20	6
+#define COM2A1	5
+#define COM2A0	4
+#define WGM21	3
+#define CS22	2
+#define CS21	1
+#define CS20	0
+
+/* ASSR */
+#define EXCLK  4
+#define AS2	   3
+#define TCN2UB	2
+#define OCR2UB	1
+#define TCR2UB	0
+
+/* USICR */
+#define USISIE 7
+#define USIOIE 6
+#define USIWM1 5
+#define USIWM0 4
+#define USICS1 3
+#define USICS0 2
+#define USICLK 1
+#define USITC  0
+
+/* USISR */
+#define USISIF 7
+#define USIOIF 6
+#define USIPF  5
+#define USIDC  4
+#define USICNT3 3
+#define USICNT2 2
+#define USICNT1 1
+#define USICNT0 0
+
+/* UCSRA */
+#define RXC	7
+#define TXC	6
+#define UDRE	5
+#define FE	4
+#define DOR	3
+#define UPE 	2
+#define U2X     1
+#define MPCM	0
+
+/* UCSRB */
+#define RXCIE	7
+#define TXCIE	6
+#define UDRIE	5
+#define RXEN	4
+#define TXEN	3
+#define UCSZ2   2
+#define RXB8	1
+#define TXB8	0
+
+/* UCSRC */
+#define UMSEL   6
+#define UPM1    5
+#define UPM0    4
+#define USBS    3
+#define UCSZ1   2
+#define UCSZ0   1
+#define UCPOL   0
+
+/* LCDCRA */
+#define LCDEN  7
+#define LCDAB  6
+#define LCDIF  4
+#define LCDIE  3
+#define LCDBD  2 /* Only in Rev. F */
+#define LCDCCD 1 /* Only in Rev. F */
+#define LCDBL  0
+
+/* LCDCRB */
+#define LCDCS  7
+#define LCD2B  6
+#define LCDMUX1 5
+#define LCDMUX0 4
+#define LCDPM2 2
+#define LCDPM1 1
+#define LCDPM0 0
+
+/* LCDFRR */
+#define LCDPS2 6
+#define LCDPS1 5
+#define LCDPS0 4
+#define LCDCD2 2
+#define LCDCD1 1
+#define LCDCD0 0
+
+/* LCDCCR */
+#define LCDDC2 7
+#define LCDDC1 6
+#define LCDDC0 5
+#define LCDMDT 4 /* Only in Rev. F */
+#define LCDCC3 3
+#define LCDCC2 2
+#define LCDCC1 1
+#define LCDCC0 0
+
+/* LCDDR0-18 */
+#define SEG24  0
+
+#define SEG23  7
+#define SEG22  6
+#define SEG21  5
+#define SEG20  4
+#define SEG19  3
+#define SEG18  2
+#define SEG17  1
+#define SEG16  0
+
+#define SEG15  7
+#define SEG14  6
+#define SEG13  5
+#define SEG12  4
+#define SEG11  3
+#define SEG10  2
+#define SEG9   1
+#define SEG8   0
+
+#define SEG7   7
+#define SEG6   6
+#define SEG5   5
+#define SEG4   4
+#define SEG3   3
+#define SEG2   2
+#define SEG1   1
+#define SEG0   0
+
+/* Constants */
+#define SPM_PAGESIZE 128
+#define RAMSTART    0x100
+#define RAMEND		0x4FF
+#define XRAMEND		RAMEND
+#define E2END		0x1FF
+#define E2PAGESIZE  4
+#define FLASHEND	0x3FFF
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST 
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x05
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_OUTPUT_COMPARE2
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART_RECV
+#pragma GCC poison SIG_USART_DATA
+#pragma GCC poison SIG_USART_TRANS
+#pragma GCC poison SIG_USI_START
+#pragma GCC poison SIG_USI_OVERFLOW
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_SPM_READY
+#pragma GCC poison SIG_LCD
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+
+#endif  /* _AVR_IOM169A_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom169p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom169p.h
@@ -31,7 +31,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom169p.h 2231 2011-03-07 05:06:55Z arcanum $ */
 
 /* iom169p.h - definitions for ATmega169P */
 
@@ -1088,12 +1088,10 @@
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif  /* _AVR_IOM169P_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom169pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom169pa.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom169pa.h 2192 2010-11-08 13:53:24Z arcanum $ */
 
 /* avr/iom169pa.h - definitions for ATmega169PA */
 
@@ -42,7 +42,7 @@
 #  define _AVR_IOXXX_H_ "iom169pa.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega169PA_H_
@@ -321,7 +321,8 @@
 #define EEAR8 0
 
 #define GTCCR _SFR_IO8(0x23)
-#define PSR310 0
+#define PSR310 0 /* Kept for legacy reasons */
+#define PSR10 0
 #define PSR2 1
 #define TSM 7
 
@@ -1475,7 +1476,6 @@
 #define ADC0_PIN   PINF
 #define ADC0_BIT   0
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom16a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom16a.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom16a.h 2248 2011-05-23 19:54:32Z joerg_wunsch $ */
 
 /* avr/iom16a.h - definitions for ATmega16A */
 
@@ -678,8 +678,6 @@
 #define TIMER0_OVF_vect      _VECTOR(9)  /* Timer/Counter0 Overflow */
 #define SPI_STC_vect_num  10
 #define SPI_STC_vect      _VECTOR(10)  /* Serial Transfer Complete */
-#define SPISTC_vect_num  10
-#define SPISTC_vect      _VECTOR(10)  /* Keep for backward-compatibility */
 
 /* The following vectors use an inconsistent (to the ATmega16 etc.)
    naming scheme.  The inconsistent names are preserved here for softwares
@@ -914,7 +912,6 @@
 #define SS_PIN   PINB
 #define SS_BIT   4
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_ADC (0x01<<4)
 #define SLEEP_MODE_PWR_DOWN (0x02<<4)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom16hva.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom16hva.h
@@ -28,14 +28,508 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom16hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* iom16hva.h - definitions for ATmega16HVA.  */
 
 #ifndef _AVR_IOM16HVA_H_
 #define _AVR_IOM16HVA_H_ 1
 
-#include <avr/iomxxhva.h>
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PA1     1
+#define PA0     0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC0   0
+
+/* Reserved [0x7] */
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC0     0
+
+/* Reserved [0x9..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define ICF0    3
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define OSICSR  _SFR_IO8(0x17)
+#define OSISEL0 4
+#define OSIST   1
+#define OSIEN   0
+
+/* Reserved [0x18..0x1B] */
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO8(0x21)
+#define EEARL   _SFR_IO8(0x21)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+/* Reserved [0x22] */
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define TCW0    7
+#define ICEN0   6
+#define ICNC0   5
+#define ICES0   4
+#define ICS0    3
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO16(0X26)
+#define TCNT0L  _SFR_IO8(0X26)
+#define TCNT0H  _SFR_IO8(0X27)
+
+#define OCR0A   _SFR_IO8(0x28)
+
+#define OCR0B   _SFR_IO8(0X29)
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F..0x30] */
+
+#define DWDR    _SFR_IO8(0x31)
+#define IDRD    7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define OCDRF   4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define CKOE    5
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SIGRD   5
+#define CTPB    4
+#define RFLB    3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRVRM   5
+#define PRSPI   3
+#define PRTIM1  2
+#define PRTIM0  1
+#define PRVADC  0
+
+#define __AVR_HAVE_PRR0	((1<<PRVADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRVRM))
+#define __AVR_HAVE_PRR0_PRVADC
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRVRM
+
+/* Reserved [0x65] */
+
+#define FOSCCAL _SFR_MEM8(0x66)
+
+/* Reserved [0x67..0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+/* Reserved [0x6A..0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define ICIE0   3
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+/* Reserved [0x70..0x77] */
+
+#define VADC	_SFR_MEM16(0x78)
+#define VADCL	_SFR_MEM8(0x78)
+#define VADCH	_SFR_MEM8(0x79)
+
+#define VADCSR	_SFR_MEM8(0x7A)
+#define VADEN   3
+#define VADSC   2
+#define VADCCIF 1
+#define VADCCIE 0
+
+/* Reserved [0x7B] */
+
+#define VADMUX	_SFR_MEM8(0x7C)
+#define VADMUX3 3
+#define VADMUX2 2
+#define VADMUX1 1
+#define VADMUX0 0
+
+/* Reserved [0x7D] */
+
+#define DIDR0	_SFR_MEM8(0x7E)
+#define PA1DID  1
+#define PA0DID  0
+
+/* Reserved [0x7F] */
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define TCW1    7
+#define ICEN1   6
+#define ICNC1   5
+#define ICES1   4
+#define ICS1    3
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+/* Reserved [0x82..0x83] */
+
+#define TCNT1   _SFR_MEM16(0x84)
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Reserved [0x86..0x87] */
+
+#define OCR1A   _SFR_MEM8(0x88)
+
+#define OCR1B   _SFR_MEM8(0x89)
+
+/* Reserved [0x8A..0xC7] */
+
+#define ROCR    _SFR_MEM8(0xC8)
+#define ROCS    7
+#define ROCWIF  1
+#define ROCWIE  0
+
+/* Reserved [0xC9..0xCF] */
+
+#define BGCCR   _SFR_MEM8(0xD0)
+#define BGD     7
+#define BGCC5   5
+#define BGCC4   4
+#define BGCC3   3
+#define BGCC2   2
+#define BGCC1   1
+#define BGCC0   0
+
+#define BGCRR   _SFR_MEM8(0xD1)
+#define BGCR7   7
+#define BGCR6   6
+#define BGCR5   5
+#define BGCR4   4
+#define BGCR3   3
+#define BGCR2   2
+#define BGCR1   1
+#define BGCR0   0
+
+/* Reserved [0xD2..0xDF] */
+
+/* CC-ADC Accumulate Current */
+/* TODO: Add _SFR_MEM32 */
+/* #define CADAC   _SFR_MEM32(0xE0) */
+#define CADAC0  _SFR_MEM8(0xE0)
+#define CADAC1  _SFR_MEM8(0xE1)
+#define CADAC2  _SFR_MEM8(0xE2)
+#define CADAC3  _SFR_MEM8(0xE3)
+
+#define CADCSRA _SFR_MEM8(0xE4)
+#define CADEN   7
+#define CADPOL  6
+#define CADUB   5
+#define CADAS1  4
+#define CADAS0  3
+#define CADSI1  2
+#define CADSI0  1
+#define CADSE   0
+
+#define CADCSRB _SFR_MEM8(0xE5)
+#define CADACIE 6
+#define CADRCIE 5
+#define CADICIE 4
+#define CADACIF 2
+#define CADRCIF 1
+#define CADICIF 0
+
+#define CADRC   _SFR_MEM8(0xE6)
+
+/* Reserved [0xE7] */
+
+#define CADIC   _SFR_MEM16(0xE8)
+#define CADICL  _SFR_MEM8(0xE8)
+#define CADICH  _SFR_MEM8(0xE9)
+
+/* Reserved [0xEA..0xEF] */
+
+#define FCSR    _SFR_MEM8(0xF0)
+#define DUVRD   3
+#define CPS     2
+#define DFE     1
+#define CFE     0
+
+/* Reserved [0xF1] */
+
+#define BPIMSK  _SFR_MEM8(0xF2)
+#define SCIE    4
+#define DOCIE   3
+#define COCIE   2
+#define DHCIE   1
+#define CHCIE   0
+
+#define BPIFR   _SFR_MEM8(0xF3)
+#define SCIF    4
+#define DOCIF   3
+#define COCIF   2
+#define DHCIF   1
+#define CHCIF   0
+
+/* Reserved [0xF4] */
+
+#define BPSCD   _SFR_MEM8(0xF5)
+
+#define BPDOCD  _SFR_MEM8(0xF6)
+
+#define BPCOCD  _SFR_MEM8(0xF7)
+
+#define BPDHCD  _SFR_MEM8(0xF8)
+
+#define BPCHCD  _SFR_MEM8(0xF9)
+
+#define BPSCTR  _SFR_MEM8(0xFA)
+
+#define BPOCTR  _SFR_MEM8(0xFB)
+
+#define BPHCTR  _SFR_MEM8(0xFC)
+
+#define BPCR    _SFR_MEM8(0xFD)
+#define SCD     4
+#define DOCD    3
+#define COCD    2
+#define DHCD    1
+#define CHCD    0
+
+#define BPPLR   _SFR_MEM8(0xFE)
+#define BPPLE   1
+#define BPPL    0
+
+/* Reserved [0xFF] */
+
+/* Interrupt vectors */
+/* Battery Protection Interrupt */
+#define BPINT_vect_num		1
+#define BPINT_vect			_VECTOR(1)
+
+/* Voltage Regulator Monitor Interrupt */
+#define VREGMON_vect_num		2
+#define VREGMON_vect			_VECTOR(2)
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		3
+#define INT0_vect			_VECTOR(3)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		4
+#define INT1_vect			_VECTOR(4)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		5
+#define INT2_vect			_VECTOR(5)
+
+/* Watchdog Timeout Interrupt */
+#define WDT_vect_num		6
+#define WDT_vect			_VECTOR(6)
+
+/* Timer/Counter 1 Input Capture */
+#define TIMER1_IC_vect_num		7
+#define TIMER1_IC_vect			_VECTOR(7)
+
+/* Timer/Counter 1 Compare A Match */
+#define TIMER1_COMPA_vect_num	8
+#define TIMER1_COMPA_vect		_VECTOR(8)
+
+/* Timer/Counter 1 Compare B Match */
+#define TIMER1_COMPB_vect_num	9
+#define TIMER1_COMPB_vect		_VECTOR(9)
+
+/* Timer/Counter 1 Overflow */
+#define TIMER1_OVF_vect_num		10
+#define TIMER1_OVF_vect			_VECTOR(10)
+
+/* Timer/Counter 0 Input Capture */
+#define TIMER0_IC_vect_num		11
+#define TIMER0_IC_vect			_VECTOR(11)
+
+/* Timer/Counter0 Compare A Match */
+#define TIMER0_COMPA_vect_num	12
+#define TIMER0_COMPA_vect		_VECTOR(12)
+
+/* Timer/Counter0 Compare B Match */
+#define TIMER0_COMPB_vect_num	13
+#define TIMER0_COMPB_vect		_VECTOR(13)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		14
+#define TIMER0_OVF_vect			_VECTOR(14)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		15
+#define SPI_STC_vect			_VECTOR(15)
+
+/* Voltage ADC Conversion Complete */
+#define VADC_vect_num		16
+#define VADC_vect			_VECTOR(16)
+
+/* Coulomb Counter ADC Conversion Complete */
+#define CCADC_CONV_vect_num		17
+#define CCADC_CONV_vect			_VECTOR(17)
+
+/* Coloumb Counter ADC Regular Current */
+#define CCADC_REG_CUR_vect_num	18
+#define CCADC_REG_CUR_vect		_VECTOR(18)
+
+/* Coloumb Counter ADC Accumulator */
+#define CCADC_ACC_vect_num		19
+#define CCADC_ACC_vect			_VECTOR(19)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		20
+#define EE_READY_vect			_VECTOR(20)
+
+#define _VECTORS_SIZE 84
+
 
 /* Constants */
 #define SPM_PAGESIZE 128
@@ -72,11 +566,9 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x0C
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_PWR_OFF (0x04<<1)
 
-
 #endif /* _AVR_IOM16HVA_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom16hva2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom16hva2.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom16hva2.h 2192 2010-11-08 13:53:24Z arcanum $ */
 
 /* avr/iom16hva2.h - definitions for ATmega16HVA2 */
 
@@ -42,7 +42,7 @@
 #  define _AVR_IOXXX_H_ "iom16hva2.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega16HVA2_H_
@@ -146,6 +146,7 @@
 #define EEDR7 7
 
 #define EEAR _SFR_IO8(0x21)
+#define EEARL _SFR_IO8(0x21)
 #define EEAR0 0
 #define EEAR1 1
 #define EEAR2 2
@@ -817,7 +818,7 @@
 #define PI_DDR   DDRI
 #define PI_PORT  PORTI
 #define PI_PIN   PINI
-#define PI_BIT   
+#define PI_BIT
 
 #define NI_DDR   DDRNI
 #define NI_PORT  PORTNI
@@ -874,7 +875,6 @@
 #define OC_PIN   PINOC
 #define OC_BIT   OC
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom16hvb.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom16hvb.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom16hvb.h 2211 2011-02-14 14:04:25Z aboyapati $ */
 
 /* avr/iom16hvb.h - definitions for ATmega16HVB */
 
@@ -1043,7 +1043,6 @@
 #define OC_PIN   PINOC
 #define OC_BIT   OC
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom16hvbrevb.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom16hvbrevb.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom16hvbrevb.h 2086 2009-12-15 03:24:16Z arcanum $ */
 
 /* avr/iom16hvbrevb.h - definitions for ATmega16HVB revision B */
 
@@ -1043,7 +1043,6 @@
 #define OC_PIN   PINOC
 #define OC_BIT   OC
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom16m1.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom16m1.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom16m1.h 2183 2010-09-21 05:37:46Z aboyapati $ */
 
 /* avr/iom16m1.h - definitions for ATmega16M1 */
 
@@ -1562,7 +1562,6 @@
 #define SIGNATURE_2 0x84
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom16u2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom16u2.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom16u2.h 2240 2011-05-09 22:18:18Z arcanum $ */
 
 /* avr/iom16u2.h - definitions for ATmega16U2 */
 
@@ -990,8 +990,6 @@
 #define SIGNATURE_2 0x89
 
 
-/* Device Pin Definitions */
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom16u4.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom16u4.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom16u4.h 2185 2010-09-22 07:06:35Z aboyapati $ */
 
 /* avr/iom16u4.h - definitions for ATmega16U4 */
 
@@ -42,7 +42,7 @@
 #  define _AVR_IOXXX_H_ "iom16u4.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega16U4_H_
@@ -446,7 +446,7 @@
 #define PRTIM2 6
 #define PRTWI 7
 
-#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
 #define __AVR_HAVE_PRR0_PRADC
 #define __AVR_HAVE_PRR0_PRUSART0
 #define __AVR_HAVE_PRR0_PRSPI
@@ -458,11 +458,13 @@
 #define PRR1 _SFR_MEM8(0x65)
 #define PRUSART1 0
 #define PRTIM3 3
+#define PRTIM4 4
 #define PRUSB 7
 
-#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRUSB))
+#define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRTIM4)|(1<<PRTIM3)|(1<<PRUSB))
 #define __AVR_HAVE_PRR1_PRUSART1
 #define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRTIM4
 #define __AVR_HAVE_PRR1_PRUSB
 
 #define OSCCAL _SFR_MEM8(0x66)
@@ -1412,7 +1414,6 @@
 #define SIGNATURE_2 0x88
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom2560.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom2560.h
@@ -28,14 +28,1613 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id */
 
 /* avr/iom2560.h - definitions for ATmega2560 */
 
 #ifndef _AVR_IOM2560_H_
 #define _AVR_IOM2560_H_ 1
 
-#include <avr/iomxx0_1.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iomxx0_1.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0X01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0X02)
+#define PA7     7
+#define PA6     6
+#define PA5     5
+#define PA4     4
+#define PA3     3
+#define PA2     2
+#define PA1     1
+#define PA0     0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7     7
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC3     3
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7     7
+#define PE6     6
+#define PE5     5
+#define PE4     4
+#define PE3     3
+#define PE2     2
+#define PE1     1
+#define PE0     0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7     7
+#define PF6     6
+#define PF5     5
+#define PF4     4
+#define PF3     3
+#define PF2     2
+#define PF1     1
+#define PF0     0
+
+#define PING    _SFR_IO8(0x12)
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDG5    5
+#define DDG4    4
+#define DDG3    3
+#define DDG2    2
+#define DDG1    1
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PG5     5
+#define PG4     4
+#define PG3     3
+#define PG2     2
+#define PG1     1
+#define PG0     0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8(0x17)
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define TIFR3   _SFR_IO8(0x18)
+#define ICF3    5
+#define OCF3C   3
+#define OCF3B   2
+#define OCF3A   1
+#define TOV3    0
+
+#define TIFR4   _SFR_IO8(0x19)
+#define ICF4    5
+#define OCF4C   3
+#define OCF4B   2
+#define OCF4A   1
+#define TOV4    0
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define ICF5    5
+#define OCF5C   3
+#define OCF5B   2
+#define OCF5A   1
+#define TOV5    0
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF2  2
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR   _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0X27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0X2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8(0x31)
+#define OCDR    _SFR_IO8(0x31)
+#define IDRD    7
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0X35)
+#define JTD     7
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0X3B)
+#define RAMPZ0  0
+
+#define EIND    _SFR_IO8(0X3C)
+#define EIND0   0
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTWI       7
+#define PRTIM2      6
+#define PRTIM0      5
+#define PRTIM1      3
+#define PRSPI       2
+#define PRUSART0    1
+#define PRADC       0
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRUSART0
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRTIM5      5
+#define PRTIM4      4
+#define PRTIM3      3
+#define PRUSART3    2
+#define PRUSART2    1
+#define PRUSART1    0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRUSART2)|(1<<PRUSART3)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRUSART2
+#define __AVR_HAVE_PRR1_PRUSART3
+#define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRTIM4
+#define __AVR_HAVE_PRR1_PRTIM5
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE2  2
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+#define PCMSK2 _SFR_MEM8(0x6D)
+#define PCINT23 7
+#define PCINT22 6
+#define PCINT21 5
+#define PCINT20 4
+#define PCINT19 3
+#define PCINT18 2
+#define PCINT17 1
+#define PCINT16 0
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define ICIE3   5
+#define OCIE3C  3
+#define OCIE3B  2
+#define OCIE3A  1
+#define TOIE3   0
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define ICIE4   5
+#define OCIE4C  3
+#define OCIE4B  2
+#define OCIE4A  1
+#define TOIE4   0
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define ICIE5   5
+#define OCIE5C  3
+#define OCIE5B  2
+#define OCIE5A  1
+#define TOIE5   0
+
+#define XMCRA   _SFR_MEM8(0x74)
+#define SRE     7
+#define SRL2    6
+#define SRL1    5
+#define SRL0    4
+#define SRW11   3
+#define SRW10   2
+#define SRW01   1
+#define SRW00   0
+
+#define XMCRB   _SFR_MEM8(0x75)
+#define XMBK    7
+#define XMM2    2
+#define XMM1    1
+#define XMM0    0
+
+/* Reserved [0x76..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define MUX5    3
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC15D  7
+#define ADC14D  6
+#define ADC13D  5
+#define ADC12D  4
+#define ADC11D  3
+#define ADC10D  2
+#define ADC9D   1
+#define ADC8D   0
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define COM3A1  7
+#define COM3A0  6
+#define COM3B1  5
+#define COM3B0  4
+#define COM3C1  3
+#define COM3C0  2
+#define WGM31   1
+#define WGM30   0
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define ICNC3   7
+#define ICES3   6
+#define WGM33   4
+#define WGM32   3
+#define CS32    2
+#define CS31    1
+#define CS30    0
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3A   7
+#define FOC3B   6
+#define FOC3C   5
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define COM4A1  7
+#define COM4A0  6
+#define COM4B1  5
+#define COM4B0  4
+#define COM4C1  3
+#define COM4C0  2
+#define WGM41   1
+#define WGM40   0
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define ICNC4   7
+#define ICES4   6
+#define WGM43   4
+#define WGM42   3
+#define CS42    2
+#define CS41    1
+#define CS40    0
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4A   7
+#define FOC4B   6
+#define FOC4C   5
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define EXCLK   6
+#define AS2     5
+#define TCN2UB  4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define RXC0    7
+#define TXC0    6
+#define UDRE0   5
+#define FE0     4
+#define DOR0    3
+#define UPE0    2
+#define U2X0    1
+#define MPCM0   0
+
+#define UCSR0B  _SFR_MEM8(0XC1)
+#define RXCIE0  7
+#define TXCIE0  6
+#define UDRIE0  5
+#define RXEN0   4
+#define TXEN0   3
+#define UCSZ02  2
+#define RXB80   1
+#define TXB80   0
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UMSEL01 7
+#define UMSEL00 6
+#define UPM01   5
+#define UPM00   4
+#define USBS0   3
+#define UCSZ01  2
+#define UCSZ00  1
+#define UCPOL0  0
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0XC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF] */
+
+#define UCSR2A _SFR_MEM8(0xD0)
+#define RXC2   7
+#define TXC2   6
+#define UDRE2  5
+#define FE2    4
+#define DOR2   3
+#define UPE2   2
+#define U2X2   1
+#define MPCM2  0
+
+#define UCSR2B _SFR_MEM8(0XD1)
+#define RXCIE2 7
+#define TXCIE2 6
+#define UDRIE2 5
+#define RXEN2  4
+#define TXEN2  3
+#define UCSZ22 2
+#define RXB82  1
+#define TXB82  0
+
+#define UCSR2C _SFR_MEM8(0xD2)
+#define UMSEL21 7
+#define UMSEL20 6
+#define UPM21  5
+#define UPM20  4
+#define USBS2  3
+#define UCSZ21 2
+#define UCSZ20 1
+#define UCPOL2 0
+
+/* Reserved [0xD3] */
+
+/* Combine UBRR2L and UBRR2H */
+#define UBRR2  _SFR_MEM16(0xD4)
+
+#define UBRR2L _SFR_MEM8(0xD4)
+#define UBRR2H _SFR_MEM8(0xD5)
+
+#define UDR2   _SFR_MEM8(0XD6)
+
+/* Reserved [0xD7..0xFF] */
+
+#define PINH   _SFR_MEM8(0x100)
+#define PINH7  7
+#define PINH6  6
+#define PINH5  5
+#define PINH4  4
+#define PINH3  3
+#define PINH2  2
+#define PINH1  1
+#define PINH0  0
+
+#define DDRH   _SFR_MEM8(0x101)
+#define DDH7   7
+#define DDH6   6
+#define DDH5   5
+#define DDH4   4
+#define DDH3   3
+#define DDH2   2
+#define DDH1   1
+#define DDH0   0
+
+#define PORTH  _SFR_MEM8(0x102)
+#define PH7    7
+#define PH6    6
+#define PH5    5
+#define PH4    4
+#define PH3    3
+#define PH2    2
+#define PH1    1
+#define PH0    0
+
+#define PINJ   _SFR_MEM8(0x103)
+#define PINJ7  7
+#define PINJ6  6
+#define PINJ5  5
+#define PINJ4  4
+#define PINJ3  3
+#define PINJ2  2
+#define PINJ1  1
+#define PINJ0  0
+
+#define DDRJ   _SFR_MEM8(0x104)
+#define DDJ7   7
+#define DDJ6   6
+#define DDJ5   5
+#define DDJ4   4
+#define DDJ3   3
+#define DDJ2   2
+#define DDJ1   1
+#define DDJ0   0
+
+#define PORTJ  _SFR_MEM8(0x105)
+#define PJ7 7
+#define PJ6 6
+#define PJ5 5
+#define PJ4 4
+#define PJ3 3
+#define PJ2 2
+#define PJ1 1
+#define PJ0 0
+
+#define PINK   _SFR_MEM8(0x106)
+#define PINK7  7
+#define PINK6  6
+#define PINK5  5
+#define PINK4  4
+#define PINK3  3
+#define PINK2  2
+#define PINK1  1
+#define PINK0  0
+
+#define DDRK   _SFR_MEM8(0x107)
+#define DDK7   7
+#define DDK6   6
+#define DDK5   5
+#define DDK4   4
+#define DDK3   3
+#define DDK2   2
+#define DDK1   1
+#define DDK0   0
+
+#define PORTK  _SFR_MEM8(0x108)
+#define PK7 7
+#define PK6 6
+#define PK5 5
+#define PK4 4
+#define PK3 3
+#define PK2 2
+#define PK1 1
+#define PK0 0
+
+#define PINL   _SFR_MEM8(0x109)
+#define PINL7  7
+#define PINL6  6
+#define PINL5  5
+#define PINL4  4
+#define PINL3  3
+#define PINL2  2
+#define PINL1  1
+#define PINL0  0
+
+#define DDRL   _SFR_MEM8(0x10A)
+#define DDL7   7
+#define DDL6   6
+#define DDL5   5
+#define DDL4   4
+#define DDL3   3
+#define DDL2   2
+#define DDL1   1
+#define DDL0   0
+
+#define PORTL  _SFR_MEM8(0x10B)
+#define PL7 7
+#define PL6 6
+#define PL5 5
+#define PL4 4
+#define PL3 3
+#define PL2 2
+#define PL1 1
+#define PL0 0
+
+/* Reserved [0x10C..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define COM5A1  7
+#define COM5A0  6
+#define COM5B1  5
+#define COM5B0  4
+#define COM5C1  3
+#define COM5C0  2
+#define WGM51   1
+#define WGM50   0
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define ICNC5   7
+#define ICES5   6
+#define WGM53   4
+#define WGM52   3
+#define CS52    2
+#define CS51    1
+#define CS50    0
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5A   7
+#define FOC5B   6
+#define FOC5C   5
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E..0x12F] */
+
+#define UCSR3A _SFR_MEM8(0x130)
+#define RXC3   7
+#define TXC3   6
+#define UDRE3  5
+#define FE3    4
+#define DOR3   3
+#define UPE3   2
+#define U2X3   1
+#define MPCM3  0
+
+#define UCSR3B _SFR_MEM8(0X131)
+#define RXCIE3 7
+#define TXCIE3 6
+#define UDRIE3 5
+#define RXEN3  4
+#define TXEN3  3
+#define UCSZ32 2
+#define RXB83  1
+#define TXB83  0
+
+#define UCSR3C _SFR_MEM8(0x132)
+#define UMSEL31 7
+#define UMSEL30 6
+#define UPM31  5
+#define UPM30  4
+#define USBS3  3
+#define UCSZ31 2
+#define UCSZ30 1
+#define UCPOL3 0
+
+/* Reserved [0x133] */
+
+/* Combine UBRR3L and UBRR3H */
+#define UBRR3  _SFR_MEM16(0x134)
+
+#define UBRR3L _SFR_MEM8(0x134)
+#define UBRR3H _SFR_MEM8(0x135)
+
+#define UDR3   _SFR_MEM8(0X136)
+
+/* Reserved [0x137..1FF] */
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+#define SIG_INTERRUPT3			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+#define SIG_INTERRUPT4			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+#define SIG_INTERRUPT5			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num		7
+#define INT6_vect			_VECTOR(7)
+#define SIG_INTERRUPT6			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+#define SIG_INTERRUPT7			_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		9
+#define PCINT0_vect			_VECTOR(9)
+#define SIG_PIN_CHANGE0			_VECTOR(9)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		10
+#define PCINT1_vect			_VECTOR(10)
+#define SIG_PIN_CHANGE1			_VECTOR(10)
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect_num		11
+#define PCINT2_vect			_VECTOR(11)
+#define SIG_PIN_CHANGE2			_VECTOR(11)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		12
+#define WDT_vect			_VECTOR(12)
+#define SIG_WATCHDOG_TIMEOUT		_VECTOR(12)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	13
+#define TIMER2_COMPA_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE2A		_VECTOR(13)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	14
+#define TIMER2_COMPB_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE2B		_VECTOR(14)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		15
+#define TIMER2_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW2			_VECTOR(15)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	16
+#define TIMER1_CAPT_vect		_VECTOR(16)
+#define SIG_INPUT_CAPTURE1		_VECTOR(16)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	17
+#define TIMER1_COMPA_vect		_VECTOR(17)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(17)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	18
+#define TIMER1_COMPB_vect		_VECTOR(18)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(18)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	19
+#define TIMER1_COMPC_vect		_VECTOR(19)
+#define SIG_OUTPUT_COMPARE1C		_VECTOR(19)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		20
+#define TIMER1_OVF_vect			_VECTOR(20)
+#define SIG_OVERFLOW1			_VECTOR(20)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	21
+#define TIMER0_COMPA_vect		_VECTOR(21)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(21)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	22
+#define TIMER0_COMPB_vect		_VECTOR(22)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(22)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		23
+#define TIMER0_OVF_vect			_VECTOR(23)
+#define SIG_OVERFLOW0			_VECTOR(23)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		24
+#define SPI_STC_vect			_VECTOR(24)
+#define SIG_SPI				_VECTOR(24)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		25
+#define USART0_RX_vect			_VECTOR(25)
+#define SIG_USART0_RECV			_VECTOR(25)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	26
+#define USART0_UDRE_vect		_VECTOR(26)
+#define SIG_USART0_DATA			_VECTOR(26)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		27
+#define USART0_TX_vect			_VECTOR(27)
+#define SIG_USART0_TRANS		_VECTOR(27)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	28
+#define ANALOG_COMP_vect		_VECTOR(28)
+#define SIG_COMPARATOR			_VECTOR(28)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		29
+#define ADC_vect			_VECTOR(29)
+#define SIG_ADC				_VECTOR(29)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		30
+#define EE_READY_vect			_VECTOR(30)
+#define SIG_EEPROM_READY		_VECTOR(30)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	31
+#define TIMER3_CAPT_vect		_VECTOR(31)
+#define SIG_INPUT_CAPTURE3		_VECTOR(31)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	32
+#define TIMER3_COMPA_vect		_VECTOR(32)
+#define SIG_OUTPUT_COMPARE3A		_VECTOR(32)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	33
+#define TIMER3_COMPB_vect		_VECTOR(33)
+#define SIG_OUTPUT_COMPARE3B		_VECTOR(33)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	34
+#define TIMER3_COMPC_vect		_VECTOR(34)
+#define SIG_OUTPUT_COMPARE3C		_VECTOR(34)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		35
+#define TIMER3_OVF_vect			_VECTOR(35)
+#define SIG_OVERFLOW3			_VECTOR(35)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		36
+#define USART1_RX_vect			_VECTOR(36)
+#define SIG_USART1_RECV			_VECTOR(36)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num	37
+#define USART1_UDRE_vect		_VECTOR(37)
+#define SIG_USART1_DATA			_VECTOR(37)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		38
+#define USART1_TX_vect			_VECTOR(38)
+#define SIG_USART1_TRANS		_VECTOR(38)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num		39
+#define TWI_vect			_VECTOR(39)
+#define SIG_2WIRE_SERIAL		_VECTOR(39)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		40
+#define SPM_READY_vect			_VECTOR(40)
+#define SIG_SPM_READY			_VECTOR(40)
+
+/* Timer/Counter4 Capture Event */
+#define TIMER4_CAPT_vect_num	41
+#define TIMER4_CAPT_vect		_VECTOR(41)
+#define SIG_INPUT_CAPTURE4		_VECTOR(41)
+
+/* Timer/Counter4 Compare Match A */
+#define TIMER4_COMPA_vect_num	42
+#define TIMER4_COMPA_vect		_VECTOR(42)
+#define SIG_OUTPUT_COMPARE4A		_VECTOR(42)
+
+/* Timer/Counter4 Compare Match B */
+#define TIMER4_COMPB_vect_num	43
+#define TIMER4_COMPB_vect		_VECTOR(43)
+#define SIG_OUTPUT_COMPARE4B		_VECTOR(43)
+
+/* Timer/Counter4 Compare Match C */
+#define TIMER4_COMPC_vect_num	44
+#define TIMER4_COMPC_vect		_VECTOR(44)
+#define SIG_OUTPUT_COMPARE4C		_VECTOR(44)
+
+/* Timer/Counter4 Overflow */
+#define TIMER4_OVF_vect_num		45
+#define TIMER4_OVF_vect			_VECTOR(45)
+#define SIG_OVERFLOW4			_VECTOR(45)
+
+/* Timer/Counter5 Capture Event */
+#define TIMER5_CAPT_vect_num	46
+#define TIMER5_CAPT_vect		_VECTOR(46)
+#define SIG_INPUT_CAPTURE5		_VECTOR(46)
+
+/* Timer/Counter5 Compare Match A */
+#define TIMER5_COMPA_vect_num	47
+#define TIMER5_COMPA_vect		_VECTOR(47)
+#define SIG_OUTPUT_COMPARE5A		_VECTOR(47)
+
+/* Timer/Counter5 Compare Match B */
+#define TIMER5_COMPB_vect_num	48
+#define TIMER5_COMPB_vect		_VECTOR(48)
+#define SIG_OUTPUT_COMPARE5B		_VECTOR(48)
+
+/* Timer/Counter5 Compare Match C */
+#define TIMER5_COMPC_vect_num	49
+#define TIMER5_COMPC_vect		_VECTOR(49)
+#define SIG_OUTPUT_COMPARE5C		_VECTOR(49)
+
+/* Timer/Counter5 Overflow */
+#define TIMER5_OVF_vect_num		50
+#define TIMER5_OVF_vect			_VECTOR(50)
+#define SIG_OVERFLOW5			_VECTOR(50)
+
+/* USART2, Rx Complete */
+#define USART2_RX_vect_num		51
+#define USART2_RX_vect			_VECTOR(51)
+#define SIG_USART2_RECV			_VECTOR(51)
+
+/* USART2 Data register Empty */
+#define USART2_UDRE_vect_num		52
+#define USART2_UDRE_vect		_VECTOR(52)
+#define SIG_USART2_DATA			_VECTOR(52)
+
+/* USART2, Tx Complete */
+#define USART2_TX_vect_num		53
+#define USART2_TX_vect			_VECTOR(53)
+#define SIG_USART2_TRANS		_VECTOR(53)
+
+/* USART3, Rx Complete */
+#define USART3_RX_vect_num		54
+#define USART3_RX_vect			_VECTOR(54)
+#define SIG_USART3_RECV			_VECTOR(54)
+
+/* USART3 Data register Empty */
+#define USART3_UDRE_vect_num		55
+#define USART3_UDRE_vect		_VECTOR(55)
+#define SIG_USART3_DATA			_VECTOR(55)
+
+/* USART3, Tx Complete */
+#define USART3_TX_vect_num		56
+#define USART3_TX_vect			_VECTOR(56)
+#define SIG_USART3_TRANS		_VECTOR(56)
+
+# define _VECTORS_SIZE 228
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_INTERRUPT2
+#pragma GCC poison SIG_INTERRUPT3
+#pragma GCC poison SIG_INTERRUPT4
+#pragma GCC poison SIG_INTERRUPT5
+#pragma GCC poison SIG_INTERRUPT6
+#pragma GCC poison SIG_INTERRUPT7
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OUTPUT_COMPARE1C
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART0_RECV
+#pragma GCC poison SIG_USART0_DATA
+#pragma GCC poison SIG_USART0_TRANS
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_INPUT_CAPTURE3
+#pragma GCC poison SIG_OUTPUT_COMPARE3A
+#pragma GCC poison SIG_OUTPUT_COMPARE3B
+#pragma GCC poison SIG_OUTPUT_COMPARE3C
+#pragma GCC poison SIG_OVERFLOW3
+#pragma GCC poison SIG_USART1_RECV
+#pragma GCC poison SIG_USART1_DATA
+#pragma GCC poison SIG_USART1_TRANS
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+#pragma GCC poison SIG_INPUT_CAPTURE4
+#pragma GCC poison SIG_OUTPUT_COMPARE4A
+#pragma GCC poison SIG_OUTPUT_COMPARE4B
+#pragma GCC poison SIG_OUTPUT_COMPARE4C
+#pragma GCC poison SIG_OVERFLOW4
+#pragma GCC poison SIG_INPUT_CAPTURE5
+#pragma GCC poison SIG_OUTPUT_COMPARE5A
+#pragma GCC poison SIG_OUTPUT_COMPARE5B
+#pragma GCC poison SIG_OUTPUT_COMPARE5C
+#pragma GCC poison SIG_OVERFLOW5
+#pragma GCC poison SIG_USART2_RECV
+#pragma GCC poison SIG_USART2_DATA
+#pragma GCC poison SIG_USART2_TRANS
+#pragma GCC poison SIG_USART3_RECV
+#pragma GCC poison SIG_USART3_DATA
+#pragma GCC poison SIG_USART3_TRANS
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 /* Constants */
 #define SPM_PAGESIZE    256
@@ -91,7 +1690,6 @@
 #define SIGNATURE_1 0x98
 #define SIGNATURE_2 0x01
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -99,5 +1697,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_IOM2560_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom2561.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom2561.h
@@ -28,14 +28,1354 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id */
 
 /* avr/iom2561.h - definitions for ATmega2561 */
 
 #ifndef _AVR_IOM2561_H_
 #define _AVR_IOM2561_H_ 1
 
-#include <avr/iomxx0_1.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iomxx0_1.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0X01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0X02)
+#define PA7     7
+#define PA6     6
+#define PA5     5
+#define PA4     4
+#define PA3     3
+#define PA2     2
+#define PA1     1
+#define PA0     0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7     7
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC3     3
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7     7
+#define PE6     6
+#define PE5     5
+#define PE4     4
+#define PE3     3
+#define PE2     2
+#define PE1     1
+#define PE0     0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7     7
+#define PF6     6
+#define PF5     5
+#define PF4     4
+#define PF3     3
+#define PF2     2
+#define PF1     1
+#define PF0     0
+
+#define PING    _SFR_IO8(0x12)
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDG5    5
+#define DDG4    4
+#define DDG3    3
+#define DDG2    2
+#define DDG1    1
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PG5     5
+#define PG4     4
+#define PG3     3
+#define PG2     2
+#define PG1     1
+#define PG0     0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8(0x17)
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define TIFR3   _SFR_IO8(0x18)
+#define ICF3    5
+#define OCF3C   3
+#define OCF3B   2
+#define OCF3A   1
+#define TOV3    0
+
+#define TIFR4   _SFR_IO8(0x19)
+#define ICF4    5
+#define OCF4C   3
+#define OCF4B   2
+#define OCF4A   1
+#define TOV4    0
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define ICF5    5
+#define OCF5C   3
+#define OCF5B   2
+#define OCF5A   1
+#define TOV5    0
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR   _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0X27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0X2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8(0x31)
+#define OCDR    _SFR_IO8(0x31)
+#define IDRD    7
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0X35)
+#define JTD     7
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0X3B)
+#define RAMPZ0  0
+
+#define EIND    _SFR_IO8(0X3C)
+#define EIND0   0
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTWI       7
+#define PRTIM2      6
+#define PRTIM0      5
+#define PRTIM1      3
+#define PRSPI       2
+#define PRUSART0    1
+#define PRADC       0
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRUSART0
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRTIM5      5
+#define PRTIM4      4
+#define PRTIM3      3
+#define PRUSART3    2
+#define PRUSART2    1
+#define PRUSART1    0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRUSART2)|(1<<PRUSART3)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRUSART2
+#define __AVR_HAVE_PRR1_PRUSART3
+#define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRTIM4
+#define __AVR_HAVE_PRR1_PRTIM5
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define ICIE3   5
+#define OCIE3C  3
+#define OCIE3B  2
+#define OCIE3A  1
+#define TOIE3   0
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define ICIE4   5
+#define OCIE4C  3
+#define OCIE4B  2
+#define OCIE4A  1
+#define TOIE4   0
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define ICIE5   5
+#define OCIE5C  3
+#define OCIE5B  2
+#define OCIE5A  1
+#define TOIE5   0
+
+#define XMCRA   _SFR_MEM8(0x74)
+#define SRE     7
+#define SRL2    6
+#define SRL1    5
+#define SRL0    4
+#define SRW11   3
+#define SRW10   2
+#define SRW01   1
+#define SRW00   0
+
+#define XMCRB   _SFR_MEM8(0x75)
+#define XMBK    7
+#define XMM2    2
+#define XMM1    1
+#define XMM0    0
+
+/* Reserved [0x76..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC15D  7
+#define ADC14D  6
+#define ADC13D  5
+#define ADC12D  4
+#define ADC11D  3
+#define ADC10D  2
+#define ADC9D   1
+#define ADC8D   0
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define COM3A1  7
+#define COM3A0  6
+#define COM3B1  5
+#define COM3B0  4
+#define COM3C1  3
+#define COM3C0  2
+#define WGM31   1
+#define WGM30   0
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define ICNC3   7
+#define ICES3   6
+#define WGM33   4
+#define WGM32   3
+#define CS32    2
+#define CS31    1
+#define CS30    0
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3A   7
+#define FOC3B   6
+#define FOC3C   5
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define COM4A1  7
+#define COM4A0  6
+#define COM4B1  5
+#define COM4B0  4
+#define COM4C1  3
+#define COM4C0  2
+#define WGM41   1
+#define WGM40   0
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define ICNC4   7
+#define ICES4   6
+#define WGM43   4
+#define WGM42   3
+#define CS42    2
+#define CS41    1
+#define CS40    0
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4A   7
+#define FOC4B   6
+#define FOC4C   5
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define EXCLK   6
+#define AS2     5
+#define TCN2UB  4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define RXC0    7
+#define TXC0    6
+#define UDRE0   5
+#define FE0     4
+#define DOR0    3
+#define UPE0    2
+#define U2X0    1
+#define MPCM0   0
+
+#define UCSR0B  _SFR_MEM8(0XC1)
+#define RXCIE0  7
+#define TXCIE0  6
+#define UDRIE0  5
+#define RXEN0   4
+#define TXEN0   3
+#define UCSZ02  2
+#define RXB80   1
+#define TXB80   0
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UMSEL01 7
+#define UMSEL00 6
+#define UPM01   5
+#define UPM00   4
+#define USBS0   3
+#define UCSZ01  2
+#define UCSZ00  1
+#define UCPOL0  0
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0XC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF] */
+
+/* Reserved [0xD7..0xFF] */
+
+/* Reserved [0x10C..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define COM5A1  7
+#define COM5A0  6
+#define COM5B1  5
+#define COM5B0  4
+#define COM5C1  3
+#define COM5C0  2
+#define WGM51   1
+#define WGM50   0
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define ICNC5   7
+#define ICES5   6
+#define WGM53   4
+#define WGM52   3
+#define CS52    2
+#define CS51    1
+#define CS50    0
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5A   7
+#define FOC5B   6
+#define FOC5C   5
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E..0x12F] */
+
+/* Reserved [0x137..1FF] */
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+#define SIG_INTERRUPT3			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+#define SIG_INTERRUPT4			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+#define SIG_INTERRUPT5			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num		7
+#define INT6_vect			_VECTOR(7)
+#define SIG_INTERRUPT6			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+#define SIG_INTERRUPT7			_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		9
+#define PCINT0_vect			_VECTOR(9)
+#define SIG_PIN_CHANGE0			_VECTOR(9)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		10
+#define PCINT1_vect			_VECTOR(10)
+#define SIG_PIN_CHANGE1			_VECTOR(10)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		12
+#define WDT_vect			_VECTOR(12)
+#define SIG_WATCHDOG_TIMEOUT		_VECTOR(12)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	13
+#define TIMER2_COMPA_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE2A		_VECTOR(13)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	14
+#define TIMER2_COMPB_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE2B		_VECTOR(14)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		15
+#define TIMER2_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW2			_VECTOR(15)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	16
+#define TIMER1_CAPT_vect		_VECTOR(16)
+#define SIG_INPUT_CAPTURE1		_VECTOR(16)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	17
+#define TIMER1_COMPA_vect		_VECTOR(17)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(17)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	18
+#define TIMER1_COMPB_vect		_VECTOR(18)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(18)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	19
+#define TIMER1_COMPC_vect		_VECTOR(19)
+#define SIG_OUTPUT_COMPARE1C		_VECTOR(19)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		20
+#define TIMER1_OVF_vect			_VECTOR(20)
+#define SIG_OVERFLOW1			_VECTOR(20)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	21
+#define TIMER0_COMPA_vect		_VECTOR(21)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(21)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	22
+#define TIMER0_COMPB_vect		_VECTOR(22)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(22)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		23
+#define TIMER0_OVF_vect			_VECTOR(23)
+#define SIG_OVERFLOW0			_VECTOR(23)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		24
+#define SPI_STC_vect			_VECTOR(24)
+#define SIG_SPI				_VECTOR(24)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		25
+#define USART0_RX_vect			_VECTOR(25)
+#define SIG_USART0_RECV			_VECTOR(25)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	26
+#define USART0_UDRE_vect		_VECTOR(26)
+#define SIG_USART0_DATA			_VECTOR(26)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		27
+#define USART0_TX_vect			_VECTOR(27)
+#define SIG_USART0_TRANS		_VECTOR(27)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	28
+#define ANALOG_COMP_vect		_VECTOR(28)
+#define SIG_COMPARATOR			_VECTOR(28)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		29
+#define ADC_vect			_VECTOR(29)
+#define SIG_ADC				_VECTOR(29)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		30
+#define EE_READY_vect			_VECTOR(30)
+#define SIG_EEPROM_READY		_VECTOR(30)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	31
+#define TIMER3_CAPT_vect		_VECTOR(31)
+#define SIG_INPUT_CAPTURE3		_VECTOR(31)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	32
+#define TIMER3_COMPA_vect		_VECTOR(32)
+#define SIG_OUTPUT_COMPARE3A		_VECTOR(32)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	33
+#define TIMER3_COMPB_vect		_VECTOR(33)
+#define SIG_OUTPUT_COMPARE3B		_VECTOR(33)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	34
+#define TIMER3_COMPC_vect		_VECTOR(34)
+#define SIG_OUTPUT_COMPARE3C		_VECTOR(34)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		35
+#define TIMER3_OVF_vect			_VECTOR(35)
+#define SIG_OVERFLOW3			_VECTOR(35)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		36
+#define USART1_RX_vect			_VECTOR(36)
+#define SIG_USART1_RECV			_VECTOR(36)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num	37
+#define USART1_UDRE_vect		_VECTOR(37)
+#define SIG_USART1_DATA			_VECTOR(37)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		38
+#define USART1_TX_vect			_VECTOR(38)
+#define SIG_USART1_TRANS		_VECTOR(38)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num		39
+#define TWI_vect			_VECTOR(39)
+#define SIG_2WIRE_SERIAL		_VECTOR(39)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		40
+#define SPM_READY_vect			_VECTOR(40)
+#define SIG_SPM_READY			_VECTOR(40)
+
+/* Timer/Counter4 Compare Match A */
+#define TIMER4_COMPA_vect_num	42
+#define TIMER4_COMPA_vect		_VECTOR(42)
+#define SIG_OUTPUT_COMPARE4A		_VECTOR(42)
+
+/* Timer/Counter4 Compare Match B */
+#define TIMER4_COMPB_vect_num	43
+#define TIMER4_COMPB_vect		_VECTOR(43)
+#define SIG_OUTPUT_COMPARE4B		_VECTOR(43)
+
+/* Timer/Counter4 Compare Match C */
+#define TIMER4_COMPC_vect_num	44
+#define TIMER4_COMPC_vect		_VECTOR(44)
+#define SIG_OUTPUT_COMPARE4C		_VECTOR(44)
+
+/* Timer/Counter4 Overflow */
+#define TIMER4_OVF_vect_num		45
+#define TIMER4_OVF_vect			_VECTOR(45)
+#define SIG_OVERFLOW4			_VECTOR(45)
+
+/* Timer/Counter5 Compare Match A */
+#define TIMER5_COMPA_vect_num	47
+#define TIMER5_COMPA_vect		_VECTOR(47)
+#define SIG_OUTPUT_COMPARE5A		_VECTOR(47)
+
+/* Timer/Counter5 Compare Match B */
+#define TIMER5_COMPB_vect_num	48
+#define TIMER5_COMPB_vect		_VECTOR(48)
+#define SIG_OUTPUT_COMPARE5B		_VECTOR(48)
+
+/* Timer/Counter5 Compare Match C */
+#define TIMER5_COMPC_vect_num	49
+#define TIMER5_COMPC_vect		_VECTOR(49)
+#define SIG_OUTPUT_COMPARE5C		_VECTOR(49)
+
+/* Timer/Counter5 Overflow */
+#define TIMER5_OVF_vect_num		50
+#define TIMER5_OVF_vect			_VECTOR(50)
+#define SIG_OVERFLOW5			_VECTOR(50)
+
+#define _VECTORS_SIZE 204
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_INTERRUPT2
+#pragma GCC poison SIG_INTERRUPT3
+#pragma GCC poison SIG_INTERRUPT4
+#pragma GCC poison SIG_INTERRUPT5
+#pragma GCC poison SIG_INTERRUPT6
+#pragma GCC poison SIG_INTERRUPT7
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OUTPUT_COMPARE1C
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART0_RECV
+#pragma GCC poison SIG_USART0_DATA
+#pragma GCC poison SIG_USART0_TRANS
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_INPUT_CAPTURE3
+#pragma GCC poison SIG_OUTPUT_COMPARE3A
+#pragma GCC poison SIG_OUTPUT_COMPARE3B
+#pragma GCC poison SIG_OUTPUT_COMPARE3C
+#pragma GCC poison SIG_OVERFLOW3
+#pragma GCC poison SIG_USART1_RECV
+#pragma GCC poison SIG_USART1_DATA
+#pragma GCC poison SIG_USART1_TRANS
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+#pragma GCC poison SIG_INPUT_CAPTURE4
+#pragma GCC poison SIG_OUTPUT_COMPARE4A
+#pragma GCC poison SIG_OUTPUT_COMPARE4B
+#pragma GCC poison SIG_OUTPUT_COMPARE4C
+#pragma GCC poison SIG_OVERFLOW4
+#pragma GCC poison SIG_INPUT_CAPTURE5
+#pragma GCC poison SIG_OUTPUT_COMPARE5A
+#pragma GCC poison SIG_OUTPUT_COMPARE5B
+#pragma GCC poison SIG_OUTPUT_COMPARE5C
+#pragma GCC poison SIG_OVERFLOW5
+#pragma GCC poison SIG_USART2_RECV
+#pragma GCC poison SIG_USART2_DATA
+#pragma GCC poison SIG_USART2_TRANS
+#pragma GCC poison SIG_USART3_RECV
+#pragma GCC poison SIG_USART3_DATA
+#pragma GCC poison SIG_USART3_TRANS
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 /* Constants */
 #define SPM_PAGESIZE    256
@@ -91,7 +1431,6 @@
 #define SIGNATURE_1 0x98
 #define SIGNATURE_2 0x02
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -99,5 +1438,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_IOM2561_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom2564rfr2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom2564rfr2.h
@@ -1,41 +1,25 @@
-/* Copyright (c) 2013 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* $Id$ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
 
-/* avr/iom2564rfr2.h - definitions for ATmega2564RFR2 */
 
-#ifndef _AVR_IOM2564RFR2_H_
-#define _AVR_IOM2564RFR2_H_ 1
+#ifndef _AVR_ATMEGA2564RFR2_H_INCLUDED
+#define _AVR_ATMEGA2564RFR2_H_INCLUDED
 
-/* This file should only be included from <avr/io.h>, never directly. */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -47,1197 +31,581 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif
 
-#include <avr/sfr_defs.h>
+/* Registers and associated bit numbers */
 
-#ifndef __ASSEMBLER__
-#  define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr))
-#  define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type)
-#  define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type)
-#endif /* __ASSEMBLER__ */
-
-/*
- * USAGE:
- *
- * simple register assignment:
- * TIFR1 = 0x17
- * subregister assignment:
- * TIFR1_struct.ocf1a = 1
- * (subregister names are converted to small letters)
- */
-
-
-/* Port A Input Pins Address */
-#define PINA                            _SFR_IO8(0x00)
-
-  /* PINA */
-
-#define PINA0                           0
-#define PINA1                           1
-#define PINA2                           2
-#define PINA3                           3
-#define PINA4                           4
-#define PINA5                           5
-#define PINA6                           6
-#define PINA7                           7
-
-/* Port A Data Direction Register */
-#define DDRA                            _SFR_IO8(0x01)
-
-  /* DDRA */
-
-#define DDA0                            0
-#define DDA1                            1
-#define DDA2                            2
-#define DDA3                            3
-#define DDA4                            4
-#define DDA5                            5
-#define DDA6                            6
-#define DDA7                            7
-
-/* Port A Data Register */
-#define PORTA                           _SFR_IO8(0x02)
-
-  /* PORTA */
-
-#define PORTA0                          0
-#define PA0                             0
-#define PORTA1                          1
-#define PA1                             1
-#define PORTA2                          2
-#define PA2                             2
-#define PORTA3                          3
-#define PA3                             3
-#define PORTA4                          4
-#define PA4                             4
-#define PORTA5                          5
-#define PA5                             5
-#define PORTA6                          6
-#define PA6                             6
-#define PORTA7                          7
-#define PA7                             7
-
-/* Port B Input Pins Address */
-#define PINB                            _SFR_IO8(0x03)
-
-  /* PINB */
-
-#define PINB0                           0
-#define PINB1                           1
-#define PINB2                           2
-#define PINB3                           3
-#define PINB4                           4
-#define PINB5                           5
-#define PINB6                           6
-#define PINB7                           7
-
-/* Port B Data Direction Register */
-#define DDRB                            _SFR_IO8(0x04)
-
-  /* DDRB */
-
-#define DDB0                            0
-#define DDB1                            1
-#define DDB2                            2
-#define DDB3                            3
-#define DDB4                            4
-#define DDB5                            5
-#define DDB6                            6
-#define DDB7                            7
-
-/* Port B Data Register */
-#define PORTB                           _SFR_IO8(0x05)
-
-  /* PORTB */
-
-#define PORTB0                          0
-#define PB0                             0
-#define PORTB1                          1
-#define PB1                             1
-#define PORTB2                          2
-#define PB2                             2
-#define PORTB3                          3
-#define PB3                             3
-#define PORTB4                          4
-#define PB4                             4
-#define PORTB5                          5
-#define PB5                             5
-#define PORTB6                          6
-#define PB6                             6
-#define PORTB7                          7
-#define PB7                             7
-
-/* Port C Input Pins Address */
-#define PINC                            _SFR_IO8(0x06)
-
-  /* PINC */
-
-#define PINC0                           0
-#define PINC1                           1
-#define PINC2                           2
-#define PINC3                           3
-#define PINC4                           4
-#define PINC5                           5
-#define PINC6                           6
-#define PINC7                           7
-
-/* Port C Data Direction Register */
-#define DDRC                            _SFR_IO8(0x07)
-
-  /* DDRC */
-
-#define DDC0                            0
-#define DDC1                            1
-#define DDC2                            2
-#define DDC3                            3
-#define DDC4                            4
-#define DDC5                            5
-#define DDC6                            6
-#define DDC7                            7
-
-/* Port C Data Register */
-#define PORTC                           _SFR_IO8(0x08)
-
-  /* PORTC */
-
-#define PORTC0                          0
-#define PC0                             0
-#define PORTC1                          1
-#define PC1                             1
-#define PORTC2                          2
-#define PC2                             2
-#define PORTC3                          3
-#define PC3                             3
-#define PORTC4                          4
-#define PC4                             4
-#define PORTC5                          5
-#define PC5                             5
-#define PORTC6                          6
-#define PC6                             6
-#define PORTC7                          7
-#define PC7                             7
-
-/* Port D Input Pins Address */
-#define PIND                            _SFR_IO8(0x09)
-
-  /* PIND */
-
-#define PIND0                           0
-#define PIND1                           1
-#define PIND2                           2
-#define PIND3                           3
-#define PIND4                           4
-#define PIND5                           5
-#define PIND6                           6
-#define PIND7                           7
-
-/* Port D Data Direction Register */
-#define DDRD                            _SFR_IO8(0x0A)
-
-  /* DDRD */
-
-#define DDD0                            0
-#define DDD1                            1
-#define DDD2                            2
-#define DDD3                            3
-#define DDD4                            4
-#define DDD5                            5
-#define DDD6                            6
-#define DDD7                            7
-
-/* Port D Data Register */
-#define PORTD                           _SFR_IO8(0x0B)
-
-  /* PORTD */
-
-#define PORTD0                          0
-#define PD0                             0
-#define PORTD1                          1
-#define PD1                             1
-#define PORTD2                          2
-#define PD2                             2
-#define PORTD3                          3
-#define PD3                             3
-#define PORTD4                          4
-#define PD4                             4
-#define PORTD5                          5
-#define PD5                             5
-#define PORTD6                          6
-#define PD6                             6
-#define PORTD7                          7
-#define PD7                             7
-
-/* Port E Input Pins Address */
-#define PINE                            _SFR_IO8(0x0C)
-
-  /* PINE */
-
-#define PINE0                           0
-#define PINE1                           1
-#define PINE2                           2
-#define PINE3                           3
-#define PINE4                           4
-#define PINE5                           5
-#define PINE6                           6
-#define PINE7                           7
-
-/* Port E Data Direction Register */
-#define DDRE                            _SFR_IO8(0x0D)
-
-  /* DDRE */
-
-#define DDE0                            0
-#define DDE1                            1
-#define DDE2                            2
-#define DDE3                            3
-#define DDE4                            4
-#define DDE5                            5
-#define DDE6                            6
-#define DDE7                            7
-
-/* Port E Data Register */
-#define PORTE                           _SFR_IO8(0x0E)
-
-  /* PORTE */
-
-#define PORTE0                          0
-#define PE0                             0
-#define PORTE1                          1
-#define PE1                             1
-#define PORTE2                          2
-#define PE2                             2
-#define PORTE3                          3
-#define PE3                             3
-#define PORTE4                          4
-#define PE4                             4
-#define PORTE5                          5
-#define PE5                             5
-#define PORTE6                          6
-#define PE6                             6
-#define PORTE7                          7
-#define PE7                             7
-
-/* Port F Input Pins Address */
-#define PINF                            _SFR_IO8(0x0F)
-
-  /* PINF */
-
-#define PINF0                           0
-#define PINF1                           1
-#define PINF2                           2
-#define PINF3                           3
-#define PINF4                           4
-#define PINF5                           5
-#define PINF6                           6
-#define PINF7                           7
-
-/* Port F Data Direction Register */
-#define DDRF                            _SFR_IO8(0x10)
-
-  /* DDRF */
-
-#define DDF0                            0
-#define DDF1                            1
-#define DDF2                            2
-#define DDF3                            3
-#define DDF4                            4
-#define DDF5                            5
-#define DDF6                            6
-#define DDF7                            7
-
-/* Port F Data Register */
-#define PORTF                           _SFR_IO8(0x11)
-
-  /* PORTF */
-
-#define PORTF0                          0
-#define PF0                             0
-#define PORTF1                          1
-#define PF1                             1
-#define PORTF2                          2
-#define PF2                             2
-#define PORTF3                          3
-#define PF3                             3
-#define PORTF4                          4
-#define PF4                             4
-#define PORTF5                          5
-#define PF5                             5
-#define PORTF6                          6
-#define PF6                             6
-#define PORTF7                          7
-#define PF7                             7
-
-/* Port G Input Pins Address */
-#define PING                            _SFR_IO8(0x12)
-
-  /* PING */
-
-#define PING0                           0
-#define PING1                           1
-#define PING2                           2
-#define PING3                           3
-#define PING4                           4
-#define PING5                           5
-
-/* Port G Data Direction Register */
-#define DDRG                            _SFR_IO8(0x13)
-
-  /* DDRG */
-
-#define DDG0                            0
-#define DDG1                            1
-#define DDG2                            2
-#define DDG3                            3
-#define DDG4                            4
-#define DDG5                            5
-
-/* Port G Data Register */
-#define PORTG                           _SFR_IO8(0x14)
-
-  /* PORTG */
-
-#define PORTG0                          0
-#define PG0                             0
-#define PORTG1                          1
-#define PG1                             1
-#define PORTG2                          2
-#define PG2                             2
-#define PORTG3                          3
-#define PG3                             3
-#define PORTG4                          4
-#define PG4                             4
-#define PORTG5                          5
-#define PG5                             5
-
-/* Timer/Counter0 Interrupt Flag Register */
-#define TIFR0                           _SFR_IO8(0x15)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR0 {
-        unsigned int tov0 : 1;	/* Timer/Counter0 Overflow Flag */
-        unsigned int ocf0a : 1;	/* Timer/Counter0 Output Compare A Match Flag */
-        unsigned int ocf0b : 1;	/* Timer/Counter0 Output Compare B Match Flag */
-        unsigned int : 5;
-};
-
-#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR0 */
-
-#define TOV0                            0
-#define OCF0A                           1
-#define OCF0B                           2
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1                           _SFR_IO8(0x16)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR1 {
-        unsigned int tov1 : 1;	/* Timer/Counter1 Overflow Flag */
-        unsigned int ocf1a : 1;	/* Timer/Counter1 Output Compare A Match Flag */
-        unsigned int ocf1b : 1;	/* Timer/Counter1 Output Compare B Match Flag */
-        unsigned int ocf1c : 1;	/* Timer/Counter1 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf1 : 1;	/* Timer/Counter1 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR1 */
-
-#define TOV1                            0
-#define OCF1A                           1
-#define OCF1B                           2
-#define OCF1C                           3
-#define ICF1                            5
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR2                           _SFR_IO8(0x17)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR2 {
-        unsigned int tov2 : 1;	/* Timer/Counter2 Overflow Flag */
-        unsigned int ocf2a : 1;	/* Output Compare Flag 2 A */
-        unsigned int ocf2b : 1;	/* Output Compare Flag 2 B */
-        unsigned int : 5;
-};
-
-#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR2 */
-
-#define TOV2                            0
-#define OCF2A                           1
-#define OCF2B                           2
-
-/* Timer/Counter3 Interrupt Flag Register */
-#define TIFR3                           _SFR_IO8(0x18)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR3 {
-        unsigned int tov3 : 1;	/* Timer/Counter3 Overflow Flag */
-        unsigned int ocf3a : 1;	/* Timer/Counter3 Output Compare A Match Flag */
-        unsigned int ocf3b : 1;	/* Timer/Counter3 Output Compare B Match Flag */
-        unsigned int ocf3c : 1;	/* Timer/Counter3 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf3 : 1;	/* Timer/Counter3 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR3 */
-
-#define TOV3                            0
-#define OCF3A                           1
-#define OCF3B                           2
-#define OCF3C                           3
-#define ICF3                            5
-
-/* Timer/Counter4 Interrupt Flag Register */
-#define TIFR4                           _SFR_IO8(0x19)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR4 {
-        unsigned int tov4 : 1;	/* Timer/Counter4 Overflow Flag */
-        unsigned int ocf4a : 1;	/* Timer/Counter4 Output Compare A Match Flag */
-        unsigned int ocf4b : 1;	/* Timer/Counter4 Output Compare B Match Flag */
-        unsigned int ocf4c : 1;	/* Timer/Counter4 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf4 : 1;	/* Timer/Counter4 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR4 */
-
-#define TOV4                            0
-#define OCF4A                           1
-#define OCF4B                           2
-#define OCF4C                           3
-#define ICF4                            5
-
-/* Timer/Counter5 Interrupt Flag Register */
-#define TIFR5                           _SFR_IO8(0x1A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR5 {
-        unsigned int tov5 : 1;	/* Timer/Counter5 Overflow Flag */
-        unsigned int ocf5a : 1;	/* Timer/Counter5 Output Compare A Match Flag */
-        unsigned int ocf5b : 1;	/* Timer/Counter5 Output Compare B Match Flag */
-        unsigned int ocf5c : 1;	/* Timer/Counter5 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf5 : 1;	/* Timer/Counter5 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR5 */
-
-#define TOV5                            0
-#define OCF5A                           1
-#define OCF5B                           2
-#define OCF5C                           3
-#define ICF5                            5
-
-/* Pin Change Interrupt Flag Register */
-#define PCIFR                           _SFR_IO8(0x1B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCIFR {
-        unsigned int pcif : 3;	/* Pin Change Interrupt Flags */
-        unsigned int : 5;
-};
-
-#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCIFR */
-
-#define PCIF0                           0
-#define PCIF1                           1
-#define PCIF2                           2
-
-/* External Interrupt Flag Register */
-#define EIFR                            _SFR_IO8(0x1C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIFR {
-        unsigned int intf : 8;	/* External Interrupt Flag */
-};
-
-#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIFR */
-
-#define INTF0                           0
-#define INTF1                           1
-#define INTF2                           2
-#define INTF3                           3
-#define INTF4                           4
-#define INTF5                           5
-#define INTF6                           6
-#define INTF7                           7
-
-/* External Interrupt Mask Register */
-#define EIMSK                           _SFR_IO8(0x1D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIMSK {
-        unsigned int intm : 8;	/* External Interrupt Request Enable */
-};
-
-#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIMSK */
-
-#define INT0                            0
-#define INT1                            1
-#define INT2                            2
-#define INT3                            3
-#define INT4                            4
-#define INT5                            5
-#define INT6                            6
-#define INT7                            7
-
-/* General Purpose IO Register 0 */
-#define GPIOR0                          _SFR_IO8(0x1E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR0 {
-        unsigned int gpior00 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior01 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior02 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior03 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior04 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior05 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior06 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior07 : 1;	/* General Purpose I/O Register 0 Value */
-};
-
-#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR0 */
-
-#define GPIOR00                         0
-#define GPIOR01                         1
-#define GPIOR02                         2
-#define GPIOR03                         3
-#define GPIOR04                         4
-#define GPIOR05                         5
-#define GPIOR06                         6
-#define GPIOR07                         7
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* EEPROM Control Register */
-#define EECR                            _SFR_IO8(0x1F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EECR {
-        unsigned int eere : 1;	/* EEPROM Read Enable */
-        unsigned int eepe : 1;	/* EEPROM Programming Enable */
-        unsigned int eempe : 1;	/* EEPROM Master Write Enable */
-        unsigned int eerie : 1;	/* EEPROM Ready Interrupt Enable */
-        unsigned int eepm : 2;	/* EEPROM Programming Mode */
-        unsigned int : 2;
-};
-
-#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EECR */
-
-#define EERE                            0
-#define EEPE                            1
-#define EEMPE                           2
-#define EERIE                           3
-#define EEPM0                           4
-#define EEPM1                           5
-
-/* EEPROM Data Register */
-#define EEDR                            _SFR_IO8(0x20)
-
-  /* EEDR */
-
-#define EEDR0                           0
-#define EEDR1                           1
-#define EEDR2                           2
-#define EEDR3                           3
-#define EEDR4                           4
-#define EEDR5                           5
-#define EEDR6                           6
-#define EEDR7                           7
-
-/* EEPROM Address Register  Bytes */
-#define EEAR                            _SFR_IO16(0x21)
-#define EEARL                           _SFR_IO8(0x21)
-#define EEARH                           _SFR_IO8(0x22)
-
-/* General Timer/Counter Control Register */
-#define GTCCR                           _SFR_IO8(0x23)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GTCCR {
-        unsigned int psrsync : 1;	/* Prescaler Reset for Synchronous Timer/Counters */
-        unsigned int psrasy : 1;	/* Prescaler Reset Timer/Counter2 */
-        unsigned int : 5;
-        unsigned int tsm : 1;	/* Timer/Counter Synchronization Mode */
-};
-
-#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GTCCR */
-
-#define PSRSYNC                         0
-#define PSR10                           0
-#define PSRASY                          1
-#define PSR2                            1
-#define TSM                             7
-
-/* Timer/Counter0 Control Register A */
-#define TCCR0A                          _SFR_IO8(0x24)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0A {
-        unsigned int wgm0 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com0b : 2;	/* Compare Match Output B Mode */
-        unsigned int com0a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0A */
-
-#define WGM00                           0
-#define WGM01                           1
-#define COM0B0                          4
-#define COM0B1                          5
-#define COM0A0                          6
-#define COM0A1                          7
-
-/* Timer/Counter0 Control Register B */
-#define TCCR0B                          _SFR_IO8(0x25)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0B {
-        unsigned int cs0 : 3;	/* Clock Select */
-        unsigned int wgm02 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc0b : 1;	/* Force Output Compare B */
-        unsigned int foc0a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0B */
-
-#define CS00                            0
-#define CS01                            1
-#define CS02                            2
-#define WGM02                           3
-#define FOC0B                           6
-#define FOC0A                           7
-
-/* Timer/Counter0 Register */
-#define TCNT0                           _SFR_IO8(0x26)
-
-  /* TCNT0 */
-
-#define TCNT0_0                         0
-#define TCNT0_1                         1
-#define TCNT0_2                         2
-#define TCNT0_3                         3
-#define TCNT0_4                         4
-#define TCNT0_5                         5
-#define TCNT0_6                         6
-#define TCNT0_7                         7
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0A                           _SFR_IO8(0x27)
-
-  /* OCR0A */
-
-#define OCR0A_0                         0
-#define OCR0A_1                         1
-#define OCR0A_2                         2
-#define OCR0A_3                         3
-#define OCR0A_4                         4
-#define OCR0A_5                         5
-#define OCR0A_6                         6
-#define OCR0A_7                         7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B                           _SFR_IO8(0x28)
-
-  /* OCR0B */
-
-#define OCR0B_0                         0
-#define OCR0B_1                         1
-#define OCR0B_2                         2
-#define OCR0B_3                         3
-#define OCR0B_4                         4
-#define OCR0B_5                         5
-#define OCR0B_6                         6
-#define OCR0B_7                         7
-
-/* General Purpose IO Register 1 */
-#define GPIOR1                          _SFR_IO8(0x2A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR1 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 1 Value */
-};
-
-#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR1 */
-
-#define GPIOR10                         0
-#define GPIOR11                         1
-#define GPIOR12                         2
-#define GPIOR13                         3
-#define GPIOR14                         4
-#define GPIOR15                         5
-#define GPIOR16                         6
-#define GPIOR17                         7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2                          _SFR_IO8(0x2B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR2 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 2 Value */
-};
-
-#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR2 */
-
-#define GPIOR20                         0
-#define GPIOR21                         1
-#define GPIOR22                         2
-#define GPIOR23                         3
-#define GPIOR24                         4
-#define GPIOR25                         5
-#define GPIOR26                         6
-#define GPIOR27                         7
-
-/* SPI Control Register */
-#define SPCR                            _SFR_IO8(0x2C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPCR {
-        unsigned int spr : 2;	/* SPI Clock Rate Select 1 and 0 */
-        unsigned int cpha : 1;	/* Clock Phase */
-        unsigned int cpol : 1;	/* Clock polarity */
-        unsigned int mstr : 1;	/* Master/Slave Select */
-        unsigned int dord : 1;	/* Data Order */
-        unsigned int spe : 1;	/* SPI Enable */
-        unsigned int spie : 1;	/* SPI Interrupt Enable */
-};
-
-#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPCR */
-
-#define SPR0                            0
-#define SPR1                            1
-#define CPHA                            2
-#define CPOL                            3
-#define MSTR                            4
-#define DORD                            5
-#define SPE                             6
-#define SPIE                            7
-
-/* SPI Status Register */
-#define SPSR                            _SFR_IO8(0x2D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPSR {
-        unsigned int spi2x : 1;	/* Double SPI Speed Bit */
-        unsigned int : 5;
-        unsigned int wcol : 1;	/* Write Collision Flag */
-        unsigned int spif : 1;	/* SPI Interrupt Flag */
-};
-
-#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPSR */
-
-#define SPI2X                           0
-#define WCOL                            6
-#define SPIF                            7
-
-/* SPI Data Register */
-#define SPDR                            _SFR_IO8(0x2E)
-
-  /* SPDR */
-
-#define SPDR0                           0
-#define SPDR1                           1
-#define SPDR2                           2
-#define SPDR3                           3
-#define SPDR4                           4
-#define SPDR5                           5
-#define SPDR6                           6
-#define SPDR7                           7
-
-/* Analog Comparator Control And Status Register */
-#define ACSR                            _SFR_IO8(0x30)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ACSR {
-        unsigned int acis : 2;	/* Analog Comparator Interrupt Mode Select */
-        unsigned int acic : 1;	/* Analog Comparator Input Capture Enable */
-        unsigned int acie : 1;	/* Analog Comparator Interrupt Enable */
-        unsigned int aci : 1;	/* Analog Comparator Interrupt Flag */
-        unsigned int aco : 1;	/* Analog Compare Output */
-        unsigned int acbg : 1;	/* Analog Comparator Bandgap Select */
-        unsigned int acd : 1;	/* Analog Comparator Disable */
-};
-
-#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ACSR */
-
-#define ACIS0                           0
-#define ACIS1                           1
-#define ACIC                            2
-#define ACIE                            3
-#define ACI                             4
-#define ACO                             5
-#define ACBG                            6
-#define ACD                             7
-
-/* On-Chip Debug Register */
-#define OCDR                            _SFR_IO8(0x31)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OCDR {
-        unsigned int ocdr : 8;	/* On-Chip Debug Register Data */
-};
-
-#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OCDR */
-
-#define OCDR0                           0
-#define OCDR1                           1
-#define OCDR2                           2
-#define OCDR3                           3
-#define OCDR4                           4
-#define OCDR5                           5
-#define OCDR6                           6
-#define OCDR7                           7
-#define IDRD                            7
-
-/* Sleep Mode Control Register */
-#define SMCR                            _SFR_IO8(0x33)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SMCR {
-        unsigned int se : 1;	/* Sleep Enable */
-        unsigned int sm : 3;	/* Sleep Mode Select bits */
-        unsigned int : 4;
-};
-
-#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SMCR */
-
-#define SE                              0
-#define SM0                             1
-#define SM1                             2
-#define SM2                             3
-
-/* MCU Status Register */
-#define MCUSR                           _SFR_IO8(0x34)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUSR {
-        unsigned int porf : 1;	/* Power-on Reset Flag */
-        unsigned int extrf : 1;	/* External Reset Flag */
-        unsigned int borf : 1;	/* Brown-out Reset Flag */
-        unsigned int wdrf : 1;	/* Watchdog Reset Flag */
-        unsigned int jtrf : 1;	/* JTAG Reset Flag */
-        unsigned int : 3;
-};
-
-#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUSR */
-
-#define PORF                            0
-#define EXTRF                           1
-#define BORF                            2
-#define WDRF                            3
-#define JTRF                            4
-
-/* MCU Control Register */
-#define MCUCR                           _SFR_IO8(0x35)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUCR {
-        unsigned int ivce : 1;	/* Interrupt Vector Change Enable */
-        unsigned int ivsel : 1;	/* Interrupt Vector Select */
-        unsigned int : 2;
-        unsigned int pud : 1;	/* Pull-up Disable */
-        unsigned int : 2;
-        unsigned int jtd : 1;	/* JTAG Interface Disable */
-};
-
-#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUCR */
-
-#define IVCE                            0
-#define IVSEL                           1
-#define PUD                             4
-#define JTD                             7
-
-/* Store Program Memory Control Register */
-#define SPMCSR                          _SFR_IO8(0x37)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPMCSR {
-        unsigned int spmen : 1;	/* Store Program Memory Enable */
-        unsigned int pgers : 1;	/* Page Erase */
-        unsigned int pgwrt : 1;	/* Page Write */
-        unsigned int blbset : 1;	/* Boot Lock Bit Set */
-        unsigned int rwwsre : 1;	/* Read While Write Section Read Enable */
-        unsigned int sigrd : 1;	/* Signature Row Read */
-        unsigned int rwwsb : 1;	/* Read While Write Section Busy */
-        unsigned int spmie : 1;	/* SPM Interrupt Enable */
-};
-
-#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPMCSR */
-
-#define SPMEN                           0
-#define PGERS                           1
-#define PGWRT                           2
-#define BLBSET                          3
-#define RWWSRE                          4
-#define SIGRD                           5
-#define RWWSB                           6
-#define SPMIE                           7
-
-/* Extended Z-pointer Register for ELPM/SPM */
-#define RAMPZ                           _SFR_IO8(0x3B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RAMPZ {
-        unsigned int rampz : 2;	/* Extended Z-Pointer Value */
-        unsigned int : 6;
-};
-
-#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ)
-
-#endif /* __ASSEMBLER__ */
-
-  /* RAMPZ */
-
-#define RAMPZ0                          0
-#define RAMPZ1                          1
-
-/* Extended Indirect Register */
-#define EIND                            _SFR_IO8(0x3C)
-
-  /* EIND */
-
-#define EIND0                           0
-
-/* Stack Pointer */
-#define SP                              _SFR_IO16(0x3D)
-#define SPL                             _SFR_IO8(0x3D)
-#define SPH                             _SFR_IO8(0x3E)
-
-/* Status Register */
-#define SREG                            _SFR_IO8(0x3F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SREG {
-        unsigned int c : 1;	/* Carry Flag */
-        unsigned int z : 1;	/* Zero Flag */
-        unsigned int n : 1;	/* Negative Flag */
-        unsigned int v : 1;	/* Two's Complement Overflow Flag */
-        unsigned int s : 1;	/* Sign Bit */
-        unsigned int h : 1;	/* Half Carry Flag */
-        unsigned int t : 1;	/* Bit Copy Storage */
-        unsigned int i : 1;	/* Global Interrupt Enable */
-};
-
-#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SREG */
-
-#define SREG_C                          0
-#define SREG_Z                          1
-#define SREG_N                          2
-#define SREG_V                          3
-#define SREG_S                          4
-#define SREG_H                          5
-#define SREG_T                          6
-#define SREG_I                          7
-
-/* Watchdog Timer Control Register */
-#define WDTCSR                          _SFR_MEM8(0x60)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_WDTCSR {
-        unsigned int wdp : 3;	/* Watchdog Timer Prescaler Bits */
-        unsigned int wde : 1;	/* Watch Dog Enable */
-        unsigned int wdce : 1;	/* Watchdog Change Enable */
-        unsigned int : 1;
-        unsigned int wdie : 1;	/* Watchdog Timeout Interrupt Enable */
-        unsigned int wdif : 1;	/* Watchdog Timeout Interrupt Flag */
-};
-
-#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* WDTCSR */
-
-#define WDP0                            0
-#define WDP1                            1
-#define WDP2                            2
-#define WDE                             3
-#define WDCE                            4
-#define WDP3                            5
-#define WDIE                            6
-#define WDIF                            7
-
-/* Clock Prescale Register */
-#define CLKPR                           _SFR_MEM8(0x61)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CLKPR {
-        unsigned int clkps : 4;	/* Clock Prescaler Select Bits */
-        unsigned int : 3;
-        unsigned int clkpce : 1;	/* Clock Prescaler Change Enable */
-};
-
-#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CLKPR */
-
-#define CLKPS0                          0
-#define CLKPS1                          1
-#define CLKPS2                          2
-#define CLKPS3                          3
-#define CLKPCE                          7
-
-/* Power Reduction Register 2 */
-#define PRR2                            _SFR_MEM8(0x63)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR2 {
-        unsigned int prram : 4;	/* Power Reduction SRAMs */
-        unsigned int : 4;
-};
-
-#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR2 */
-
-#define PRRAM0                          0
-#define PRRAM1                          1
-#define PRRAM2                          2
-#define PRRAM3                          3
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
+#define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
+#define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
+#define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
+#define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
+#define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
+#define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
+#define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE7  7
+#define PORTE6  6
+#define PORTE5  5
+#define PORTE4  4
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
+#define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
+#define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
+#define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
+#define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
+#define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
+#define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
+#define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PORTF7  7
+#define PORTF6  6
+#define PORTF5  5
+#define PORTF4  4
+#define PORTF3  3
+#define PORTF2  2
+#define PORTF1  1
+#define PORTF0  0
+
+#define PING    _SFR_IO8(0x12)
+#define PING7   7
+#define PING6   6
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDRG7   7
+// Inserted "DDG7" from "DDRG7" due to compatibility
+#define DDG7    7
+#define DDRG6   6
+// Inserted "DDG6" from "DDRG6" due to compatibility
+#define DDG6    6
+#define DDRG5   5
+// Inserted "DDG5" from "DDRG5" due to compatibility
+#define DDG5    5
+#define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
+#define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
+#define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
+#define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
+#define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PORTG7  7
+#define PORTG6  6
+#define PORTG5  5
+#define PORTG4  4
+#define PORTG3  3
+#define PORTG2  2
+#define PORTG1  1
+#define PORTG0  0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define OCF1C   3
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+#define Res0    3
+#define Res1    4
+#define Res2    5
+#define Res3    6
+#define Res4    7
+
+#define TIFR3   _SFR_IO8(0x18)
+#define TOV3    0
+#define OCF3A   1
+#define OCF3B   2
+#define OCF3C   3
+#define ICF3    5
+
+#define TIFR4   _SFR_IO8(0x19)
+#define TOV4    0
+#define OCF4A   1
+#define OCF4B   2
+#define OCF4C   3
+#define ICF4    5
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define TOV5    0
+#define OCF5A   1
+#define OCF5B   2
+#define OCF5C   3
+#define ICF5    5
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+#define INTF2   2
+#define INTF3   3
+#define INTF4   4
+#define INTF5   5
+#define INTF6   6
+#define INTF7   7
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+#define INT2    2
+#define INT3    3
+#define INT4    4
+#define INT5    5
+#define INT6    6
+#define INT7    7
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define PSRASY  1
+#define TSM     7
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define OCDR    _SFR_IO8(0x31)
+#define OCDR0   0
+#define OCDR1   1
+#define OCDR2   2
+#define OCDR3   3
+#define OCDR4   4
+#define OCDR5   5
+#define OCDR6   6
+#define OCDR7   7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0x3B)
+#define RAMPZ0  0
+#define RAMPZ1  1
+
+#define EIND    _SFR_IO8(0x3C)
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62] */
+
+#define PRR2    _SFR_MEM8(0x63)
+#define PRRAM0  0
+#define PRRAM1  1
+#define PRRAM2  2
+#define PRRAM3  3
 
 #define __AVR_HAVE_PRR2	((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3))
 #define __AVR_HAVE_PRR2_PRRAM0
@@ -1245,36 +613,15 @@
 #define __AVR_HAVE_PRR2_PRRAM2
 #define __AVR_HAVE_PRR2_PRRAM3
 
-/* Power Reduction Register0 */
-#define PRR0                            _SFR_MEM8(0x64)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR0 {
-        unsigned int pradc : 1;	/* Power Reduction ADC */
-        unsigned int prusart0 : 1;	/* Power Reduction USART */
-        unsigned int prspi : 1;	/* Power Reduction Serial Peripheral Interface */
-        unsigned int prtim1 : 1;	/* Power Reduction Timer/Counter1 */
-        unsigned int prpga : 1;	/* Power Reduction PGA */
-        unsigned int prtim0 : 1;	/* Power Reduction Timer/Counter0 */
-        unsigned int prtim2 : 1;	/* Power Reduction Timer/Counter2 */
-        unsigned int prtwi : 1;	/* Power Reduction TWI */
-};
-
-#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR0 */
-
-#define PRADC                           0
-#define PRUSART0                        1
-#define PRSPI                           2
-#define PRTIM1                          3
-#define PRPGA                           4
-#define PRTIM0                          5
-#define PRTIM2                          6
-#define PRTWI                           7
+#define PRR0    _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRPGA   4
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
 
 #define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
 #define __AVR_HAVE_PRR0_PRADC
@@ -1286,32 +633,13 @@
 #define __AVR_HAVE_PRR0_PRTIM2
 #define __AVR_HAVE_PRR0_PRTWI
 
-/* Power Reduction Register 1 */
-#define PRR1                            _SFR_MEM8(0x65)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR1 {
-        unsigned int prusart1 : 1;	/* Power Reduction USART1 */
-        unsigned int : 2;
-        unsigned int prtim3 : 1;	/* Power Reduction Timer/Counter3 */
-        unsigned int prtim4 : 1;	/* Power Reduction Timer/Counter4 */
-        unsigned int prtim5 : 1;	/* Power Reduction Timer/Counter5 */
-        unsigned int prtrx24 : 1;	/* Power Reduction Transceiver */
-        unsigned int : 1;
-};
-
-#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR1 */
-
-#define PRUSART1                        0
-#define PRTIM3                          3
-#define PRTIM4                          4
-#define PRTIM5                          5
-#define PRTRX24                         6
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSART1 0
+#define PRTIM3  3
+#define PRTIM4  4
+#define PRTIM5  5
+#define PRTRX24 6
+#define Res     7
 
 #define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24))
 #define __AVR_HAVE_PRR1_PRUSART1
@@ -1320,4975 +648,2062 @@
 #define __AVR_HAVE_PRR1_PRTIM5
 #define __AVR_HAVE_PRR1_PRTRX24
 
-/* Oscillator Calibration Value */
-#define OSCCAL                          _SFR_MEM8(0x66)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OSCCAL {
-        unsigned int cal : 8;	/* Oscillator Calibration Tuning Value */
-};
-
-#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OSCCAL */
-
-#define CAL0                            0
-#define CAL1                            1
-#define CAL2                            2
-#define CAL3                            3
-#define CAL4                            4
-#define CAL5                            5
-#define CAL6                            6
-#define CAL7                            7
-
-/* Reference Voltage Calibration Register */
-#define BGCR                            _SFR_MEM8(0x67)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BGCR {
-        unsigned int bgcal : 3;	/* Coarse Calibration Bits */
-        unsigned int bgcal_fine : 4;	/* Fine Calibration Bits */
-        unsigned int : 1;
-};
-
-#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* BGCR */
-
-#define BGCAL0                          0
-#define BGCAL1                          1
-#define BGCAL2                          2
-#define BGCAL_FINE0                     3
-#define BGCAL_FINE1                     4
-#define BGCAL_FINE2                     5
-#define BGCAL_FINE3                     6
-
-/* Pin Change Interrupt Control Register */
-#define PCICR                           _SFR_MEM8(0x68)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCICR {
-        unsigned int pcie : 3;	/* Pin Change Interrupt Enables */
-        unsigned int : 5;
-};
-
-#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCICR */
-
-#define PCIE0                           0
-#define PCIE1                           1
-#define PCIE2                           2
-
-/* External Interrupt Control Register A */
-#define EICRA                           _SFR_MEM8(0x69)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRA {
-        unsigned int isc0 : 2;	/* External Interrupt 0 Sense Control Bit */
-        unsigned int isc1 : 2;	/* External Interrupt 1 Sense Control Bit */
-        unsigned int isc2 : 2;	/* External Interrupt 2 Sense Control Bit */
-        unsigned int isc3 : 2;	/* External Interrupt 3 Sense Control Bit */
-};
-
-#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRA */
-
-#define ISC00                           0
-#define ISC01                           1
-#define ISC10                           2
-#define ISC11                           3
-#define ISC20                           4
-#define ISC21                           5
-#define ISC30                           6
-#define ISC31                           7
-
-/* External Interrupt Control Register B */
-#define EICRB                           _SFR_MEM8(0x6A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRB {
-        unsigned int isc4 : 2;	/* External Interrupt 4 Sense Control Bit */
-        unsigned int isc5 : 2;	/* External Interrupt 5 Sense Control Bit */
-        unsigned int isc6 : 2;	/* External Interrupt 6 Sense Control Bit */
-        unsigned int isc7 : 2;	/* External Interrupt 7 Sense Control Bit */
-};
-
-#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRB */
-
-#define ISC40                           0
-#define ISC41                           1
-#define ISC50                           2
-#define ISC51                           3
-#define ISC60                           4
-#define ISC61                           5
-#define ISC70                           6
-#define ISC71                           7
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0                          _SFR_MEM8(0x6B)
-
-  /* PCMSK0 */
-
-#define PCINT0                          0
-#define PCINT1                          1
-#define PCINT2                          2
-#define PCINT3                          3
-#define PCINT4                          4
-#define PCINT5                          5
-#define PCINT6                          6
-#define PCINT7                          7
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1                          _SFR_MEM8(0x6C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK1 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK1 */
-
-#define PCINT8                          0
-#define PCINT9                          1
-#define PCINT10                         2
-#define PCINT11                         3
-#define PCINT12                         4
-#define PCINT13                         5
-#define PCINT14                         6
-#define PCINT15                         7
-
-/* Pin Change Mask Register 2 */
-#define PCMSK2                          _SFR_MEM8(0x6D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK2 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK2 */
-
-#define PCINT16                         0
-#define PCINT17                         1
-#define PCINT18                         2
-#define PCINT19                         3
-#define PCINT20                         4
-#define PCINT21                         5
-#define PCINT22                         6
-#define PCINT23                         7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0                          _SFR_MEM8(0x6E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK0 {
-        unsigned int toie0 : 1;	/* Timer/Counter0 Overflow Interrupt Enable */
-        unsigned int ocie0a : 1;	/* Timer/Counter0 Output Compare Match A Interrupt Enable */
-        unsigned int ocie0b : 1;	/* Timer/Counter0 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK0 */
-
-#define TOIE0                           0
-#define OCIE0A                          1
-#define OCIE0B                          2
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1                          _SFR_MEM8(0x6F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK1 {
-        unsigned int toie1 : 1;	/* Timer/Counter1 Overflow Interrupt Enable */
-        unsigned int ocie1a : 1;	/* Timer/Counter1 Output Compare A Match Interrupt Enable */
-        unsigned int ocie1b : 1;	/* Timer/Counter1 Output Compare B Match Interrupt Enable */
-        unsigned int ocie1c : 1;	/* Timer/Counter1 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie1 : 1;	/* Timer/Counter1 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK1 */
-
-#define TOIE1                           0
-#define OCIE1A                          1
-#define OCIE1B                          2
-#define OCIE1C                          3
-#define ICIE1                           5
-
-/* Timer/Counter Interrupt Mask register */
-#define TIMSK2                          _SFR_MEM8(0x70)
+#define OSCCAL  _SFR_MEM8(0x66)
+#define CAL0    0
+#define CAL1    1
+#define CAL2    2
+#define CAL3    3
+#define CAL4    4
+#define CAL5    5
+#define CAL6    6
+#define CAL7    7
+
+#define BGCR    _SFR_MEM8(0x67)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL_FINE0 3
+#define BGCAL_FINE1 4
+#define BGCAL_FINE2 5
+#define BGCAL_FINE3 6
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+#define ISC20   4
+#define ISC21   5
+#define ISC30   6
+#define ISC31   7
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC40   0
+#define ISC41   1
+#define ISC50   2
+#define ISC51   3
+#define ISC60   4
+#define ISC61   5
+#define ISC70   6
+#define ISC71   7
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define OCIE1C  3
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define TOIE3   0
+#define OCIE3A  1
+#define OCIE3B  2
+#define OCIE3C  3
+#define ICIE3   5
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define TOIE4   0
+#define OCIE4A  1
+#define OCIE4B  2
+#define OCIE4C  3
+#define ICIE4   5
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define TOIE5   0
+#define OCIE5A  1
+#define OCIE5B  2
+#define OCIE5C  3
+#define ICIE5   5
+
+/* Reserved [0x74] */
+
+#define NEMCR   _SFR_MEM8(0x75)
+#define AEAM0   4
+#define AEAM1   5
+#define ENEAM   6
+
+/* Reserved [0x76] */
+
+#define ADCSRC  _SFR_MEM8(0x77)
+#define ADSUT0  0
+#define ADSUT1  1
+#define ADSUT2  2
+#define ADSUT3  3
+#define ADSUT4  4
+#define ADTHT0  6
+#define ADTHT1  7
 
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK2 {
-        unsigned int toie2 : 1;	/* Timer/Counter2 Overflow Interrupt Enable */
-        unsigned int ocie2a : 1;	/* Timer/Counter2 Output Compare Match A Interrupt Enable */
-        unsigned int ocie2b : 1;	/* Timer/Counter2 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK2 */
-
-#define TOIE2                           0
-#define TOIE2A                          0
-#define OCIE2A                          1
-#define OCIE2B                          2
-
-/* Timer/Counter3 Interrupt Mask Register */
-#define TIMSK3                          _SFR_MEM8(0x71)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK3 {
-        unsigned int toie3 : 1;	/* Timer/Counter3 Overflow Interrupt Enable */
-        unsigned int ocie3a : 1;	/* Timer/Counter3 Output Compare A Match Interrupt Enable */
-        unsigned int ocie3b : 1;	/* Timer/Counter3 Output Compare B Match Interrupt Enable */
-        unsigned int ocie3c : 1;	/* Timer/Counter3 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie3 : 1;	/* Timer/Counter3 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK3 */
-
-#define TOIE3                           0
-#define OCIE3A                          1
-#define OCIE3B                          2
-#define OCIE3C                          3
-#define ICIE3                           5
-
-/* Timer/Counter4 Interrupt Mask Register */
-#define TIMSK4                          _SFR_MEM8(0x72)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK4 {
-        unsigned int toie4 : 1;	/* Timer/Counter4 Overflow Interrupt Enable */
-        unsigned int ocie4a : 1;	/* Timer/Counter4 Output Compare A Match Interrupt Enable */
-        unsigned int ocie4b : 1;	/* Timer/Counter4 Output Compare B Match Interrupt Enable */
-        unsigned int ocie4c : 1;	/* Timer/Counter4 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie4 : 1;	/* Timer/Counter4 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK4 */
-
-#define TOIE4                           0
-#define OCIE4A                          1
-#define OCIE4B                          2
-#define OCIE4C                          3
-#define ICIE4                           5
-
-/* Timer/Counter5 Interrupt Mask Register */
-#define TIMSK5                          _SFR_MEM8(0x73)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK5 {
-        unsigned int toie5 : 1;	/* Timer/Counter5 Overflow Interrupt Enable */
-        unsigned int ocie5a : 1;	/* Timer/Counter5 Output Compare A Match Interrupt Enable */
-        unsigned int ocie5b : 1;	/* Timer/Counter5 Output Compare B Match Interrupt Enable */
-        unsigned int ocie5c : 1;	/* Timer/Counter5 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie5 : 1;	/* Timer/Counter5 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK5 */
-
-#define TOIE5                           0
-#define OCIE5A                          1
-#define OCIE5B                          2
-#define OCIE5C                          3
-#define ICIE5                           5
-
-/* Flash Extended-Mode Control-Register */
-#define NEMCR                           _SFR_MEM8(0x75)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_NEMCR {
-        unsigned int : 4;
-        unsigned int aeam : 2;	/* Address for Extended Address Mode of Extra Rows */
-        unsigned int eneam : 1;	/* Enable Extended Address Mode for Extra Rows */
-        unsigned int : 1;
-};
-
-#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* NEMCR */
-
-#define AEAM0                           4
-#define AEAM1                           5
-#define ENEAM                           6
-
-/* The ADC Control and Status Register C */
-#define ADCSRC                          _SFR_MEM8(0x77)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRC {
-        unsigned int adsut : 5;	/* ADC Start-up Time */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int adtht : 2;	/* ADC Track-and-Hold Time */
-};
-
-#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRC */
-
-#define ADSUT0                          0
-#define ADSUT1                          1
-#define ADSUT2                          2
-#define ADSUT3                          3
-#define ADSUT4                          4
-#define ADTHT0                          6
-#define ADTHT1                          7
-
-/* ADC Data Register  Bytes */
+/* Combine ADCL and ADCH */
 #ifndef __ASSEMBLER__
-#define ADC                             _SFR_MEM16(0x78)
-#define ADCL                            _SFR_MEM8(0x78)
-#define ADCH                            _SFR_MEM8(0x79)
-#endif /* __ASSEMBLER__ */
-#define ADCW                            _SFR_MEM16(0x78)
-#define ADCWL                           _SFR_MEM8(0x78)
-#define ADCWH                           _SFR_MEM8(0x79)
-
-/* The ADC Control and Status Register A */
-#define ADCSRA                          _SFR_MEM8(0x7A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRA {
-        unsigned int adps : 3;	/* ADC  Prescaler Select Bits */
-        unsigned int adie : 1;	/* ADC Interrupt Enable */
-        unsigned int adif : 1;	/* ADC Interrupt Flag */
-        unsigned int adate : 1;	/* ADC Auto Trigger Enable */
-        unsigned int adsc : 1;	/* ADC Start Conversion */
-        unsigned int aden : 1;	/* ADC Enable */
-};
-
-#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRA */
-
-#define ADPS0                           0
-#define ADPS1                           1
-#define ADPS2                           2
-#define ADIE                            3
-#define ADIF                            4
-#define ADATE                           5
-#define ADSC                            6
-#define ADEN                            7
-
-/* ADC Control and Status Register B */
-#define ADCSRB                          _SFR_MEM8(0x7B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRB {
-        unsigned int adts : 3;	/* ADC Auto Trigger Source */
-        unsigned int mux5 : 1;	/* Analog Channel and Gain Selection Bits */
-        unsigned int acch : 1;	/* Analog Channel Change */
-        unsigned int refok : 1;	/* Reference Voltage OK */
-        unsigned int acme : 1;	/* Analog Comparator Multiplexer Enable */
-        unsigned int avddok : 1;	/* AVDD Supply Voltage OK */
-};
-
-#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRB */
-
-#define ADTS0                           0
-#define ADTS1                           1
-#define ADTS2                           2
-#define MUX5                            3
-#define ACCH                            4
-#define REFOK                           5
-#define ACME                            6
-#define AVDDOK                          7
-
-/* The ADC Multiplexer Selection Register */
-#define ADMUX                           _SFR_MEM8(0x7C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADMUX {
-        unsigned int mux : 5;	/* Analog Channel and Gain Selection Bits */
-        unsigned int adlar : 1;	/* ADC Left Adjust Result */
-        unsigned int refs : 2;	/* Reference Selection Bits */
-};
-
-#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADMUX */
-
-#define MUX0                            0
-#define MUX1                            1
-#define MUX2                            2
-#define MUX3                            3
-#define MUX4                            4
-#define ADLAR                           5
-#define REFS0                           6
-#define REFS1                           7
-
-/* Digital Input Disable Register 2 */
-#define DIDR2                           _SFR_MEM8(0x7D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR2 {
-        unsigned int adc8d : 1;	/* Reserved Bits */
-        unsigned int adc9d : 1;	/* Reserved Bits */
-        unsigned int adc10d : 1;	/* Reserved Bits */
-        unsigned int adc11d : 1;	/* Reserved Bits */
-        unsigned int adc12d : 1;	/* Reserved Bits */
-        unsigned int adc13d : 1;	/* Reserved Bits */
-        unsigned int adc14d : 1;	/* Reserved Bits */
-        unsigned int adc15d : 1;	/* Reserved Bits */
-};
-
-#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR2 */
-
-#define ADC8D                           0
-#define ADC9D                           1
-#define ADC10D                          2
-#define ADC11D                          3
-#define ADC12D                          4
-#define ADC13D                          5
-#define ADC14D                          6
-#define ADC15D                          7
-
-/* Digital Input Disable Register 0 */
-#define DIDR0                           _SFR_MEM8(0x7E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR0 {
-        unsigned int adc0d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc1d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc2d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc3d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc4d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc5d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc6d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc7d : 1;	/* Disable ADC7:0 Digital Input */
-};
-
-#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR0 */
-
-#define ADC0D                           0
-#define ADC1D                           1
-#define ADC2D                           2
-#define ADC3D                           3
-#define ADC4D                           4
-#define ADC5D                           5
-#define ADC6D                           6
-#define ADC7D                           7
-
-/* Digital Input Disable Register 1 */
-#define DIDR1                           _SFR_MEM8(0x7F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR1 {
-        unsigned int ain0d : 1;	/* AIN0 Digital Input Disable */
-        unsigned int ain1d : 1;	/* AIN1 Digital Input Disable */
-        unsigned int : 6;
-};
-
-#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR1 */
-
-#define AIN0D                           0
-#define AIN1D                           1
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A                          _SFR_MEM8(0x80)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1A {
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int com1c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com1b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com1a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1A */
-
-#define WGM10                           0
-#define WGM11                           1
-#define COM1C0                          2
-#define COM1C1                          3
-#define COM1B0                          4
-#define COM1B1                          5
-#define COM1A0                          6
-#define COM1A1                          7
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B                          _SFR_MEM8(0x81)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1B {
-        unsigned int cs1 : 3;	/* Clock Select */
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices1 : 1;	/* Input Capture 1 Edge Select */
-        unsigned int icnc1 : 1;	/* Input Capture 1 Noise Canceller */
-};
-
-#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1B */
-
-#define CS10                            0
-#define CS11                            1
-#define CS12                            2
-#define WGM12                           3
-#define WGM13                           4
-#define ICES1                           6
-#define ICNC1                           7
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C                          _SFR_MEM8(0x82)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1C {
-        unsigned int : 5;
-        unsigned int foc1c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc1b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc1a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1C */
-
-#define FOC1C                           5
-#define FOC1B                           6
-#define FOC1A                           7
-
-/* Timer/Counter1  Bytes */
-#define TCNT1                           _SFR_MEM16(0x84)
-#define TCNT1L                          _SFR_MEM8(0x84)
-#define TCNT1H                          _SFR_MEM8(0x85)
-
-/* Timer/Counter1 Input Capture Register  Bytes */
-#define ICR1                            _SFR_MEM16(0x86)
-#define ICR1L                           _SFR_MEM8(0x86)
-#define ICR1H                           _SFR_MEM8(0x87)
-
-/* Timer/Counter1 Output Compare Register A  Bytes */
-#define OCR1A                           _SFR_MEM16(0x88)
-#define OCR1AL                          _SFR_MEM8(0x88)
-#define OCR1AH                          _SFR_MEM8(0x89)
-
-/* Timer/Counter1 Output Compare Register B  Bytes */
-#define OCR1B                           _SFR_MEM16(0x8A)
-#define OCR1BL                          _SFR_MEM8(0x8A)
-#define OCR1BH                          _SFR_MEM8(0x8B)
-
-/* Timer/Counter1 Output Compare Register C  Bytes */
-#define OCR1C                           _SFR_MEM16(0x8C)
-#define OCR1CL                          _SFR_MEM8(0x8C)
-#define OCR1CH                          _SFR_MEM8(0x8D)
-
-/* Timer/Counter3 Control Register A */
-#define TCCR3A                          _SFR_MEM8(0x90)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3A {
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int com3c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com3b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com3a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3A */
-
-#define WGM30                           0
-#define WGM31                           1
-#define COM3C0                          2
-#define COM3C1                          3
-#define COM3B0                          4
-#define COM3B1                          5
-#define COM3A0                          6
-#define COM3A1                          7
-
-/* Timer/Counter3 Control Register B */
-#define TCCR3B                          _SFR_MEM8(0x91)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3B {
-        unsigned int cs3 : 3;	/* Clock Select */
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices3 : 1;	/* Input Capture 3 Edge Select */
-        unsigned int icnc3 : 1;	/* Input Capture 3 Noise Canceller */
-};
-
-#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3B */
-
-#define CS30                            0
-#define CS31                            1
-#define CS32                            2
-#define WGM32                           3
-#define WGM33                           4
-#define ICES3                           6
-#define ICNC3                           7
-
-/* Timer/Counter3 Control Register C */
-#define TCCR3C                          _SFR_MEM8(0x92)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3C {
-        unsigned int : 5;
-        unsigned int foc3c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc3b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc3a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3C */
-
-#define FOC3C                           5
-#define FOC3B                           6
-#define FOC3A                           7
-
-/* Timer/Counter3  Bytes */
-#define TCNT3                           _SFR_MEM16(0x94)
-#define TCNT3L                          _SFR_MEM8(0x94)
-#define TCNT3H                          _SFR_MEM8(0x95)
-
-/* Timer/Counter3 Input Capture Register  Bytes */
-#define ICR3                            _SFR_MEM16(0x96)
-#define ICR3L                           _SFR_MEM8(0x96)
-#define ICR3H                           _SFR_MEM8(0x97)
-
-/* Timer/Counter3 Output Compare Register A  Bytes */
-#define OCR3A                           _SFR_MEM16(0x98)
-#define OCR3AL                          _SFR_MEM8(0x98)
-#define OCR3AH                          _SFR_MEM8(0x99)
-
-/* Timer/Counter3 Output Compare Register B  Bytes */
-#define OCR3B                           _SFR_MEM16(0x9A)
-#define OCR3BL                          _SFR_MEM8(0x9A)
-#define OCR3BH                          _SFR_MEM8(0x9B)
-
-/* Timer/Counter3 Output Compare Register C  Bytes */
-#define OCR3C                           _SFR_MEM16(0x9C)
-#define OCR3CL                          _SFR_MEM8(0x9C)
-#define OCR3CH                          _SFR_MEM8(0x9D)
-
-/* Timer/Counter4 Control Register A */
-#define TCCR4A                          _SFR_MEM8(0xA0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4A {
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int com4c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com4b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com4a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4A */
-
-#define WGM40                           0
-#define WGM41                           1
-#define COM4C0                          2
-#define COM4C1                          3
-#define COM4B0                          4
-#define COM4B1                          5
-#define COM4A0                          6
-#define COM4A1                          7
-
-/* Timer/Counter4 Control Register B */
-#define TCCR4B                          _SFR_MEM8(0xA1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4B {
-        unsigned int cs4 : 3;	/* Clock Select */
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices4 : 1;	/* Input Capture 4 Edge Select */
-        unsigned int icnc4 : 1;	/* Input Capture 4 Noise Canceller */
-};
-
-#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4B */
-
-#define CS40                            0
-#define CS41                            1
-#define CS42                            2
-#define WGM42                           3
-#define WGM43                           4
-#define ICES4                           6
-#define ICNC4                           7
-
-/* Timer/Counter4 Control Register C */
-#define TCCR4C                          _SFR_MEM8(0xA2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4C {
-        unsigned int : 5;
-        unsigned int foc4c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc4b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc4a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4C */
-
-#define FOC4C                           5
-#define FOC4B                           6
-#define FOC4A                           7
-
-/* Timer/Counter4  Bytes */
-#define TCNT4                           _SFR_MEM16(0xA4)
-#define TCNT4L                          _SFR_MEM8(0xA4)
-#define TCNT4H                          _SFR_MEM8(0xA5)
-
-/* Timer/Counter4 Input Capture Register  Bytes */
-#define ICR4                            _SFR_MEM16(0xA6)
-#define ICR4L                           _SFR_MEM8(0xA6)
-#define ICR4H                           _SFR_MEM8(0xA7)
-
-/* Timer/Counter4 Output Compare Register A  Bytes */
-#define OCR4A                           _SFR_MEM16(0xA8)
-#define OCR4AL                          _SFR_MEM8(0xA8)
-#define OCR4AH                          _SFR_MEM8(0xA9)
-
-/* Timer/Counter4 Output Compare Register B  Bytes */
-#define OCR4B                           _SFR_MEM16(0xAA)
-#define OCR4BL                          _SFR_MEM8(0xAA)
-#define OCR4BH                          _SFR_MEM8(0xAB)
-
-/* Timer/Counter4 Output Compare Register C  Bytes */
-#define OCR4C                           _SFR_MEM16(0xAC)
-#define OCR4CL                          _SFR_MEM8(0xAC)
-#define OCR4CH                          _SFR_MEM8(0xAD)
-
-/* Timer/Counter2 Control Register A */
-#define TCCR2A                          _SFR_MEM8(0xB0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2A {
-        unsigned int wgm2 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com2b : 2;	/* Compare Match Output B Mode */
-        unsigned int com2a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2A */
-
-#define WGM20                           0
-#define WGM21                           1
-#define COM2B0                          4
-#define COM2B1                          5
-#define COM2A0                          6
-#define COM2A1                          7
-
-/* Timer/Counter2 Control Register B */
-#define TCCR2B                          _SFR_MEM8(0xB1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2B {
-        unsigned int cs2 : 3;	/* Clock Select */
-        unsigned int wgm22 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc2b : 1;	/* Force Output Compare B */
-        unsigned int foc2a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2B */
-
-#define CS20                            0
-#define CS21                            1
-#define CS22                            2
-#define WGM22                           3
-#define FOC2B                           6
-#define FOC2A                           7
-
-/* Timer/Counter2 */
-#define TCNT2                           _SFR_MEM8(0xB2)
-
-  /* TCNT2 */
-
-#define TCNT20                          0
-#define TCNT21                          1
-#define TCNT22                          2
-#define TCNT23                          3
-#define TCNT24                          4
-#define TCNT25                          5
-#define TCNT26                          6
-#define TCNT27                          7
-
-/* Timer/Counter2 Output Compare Register A */
-#define OCR2A                           _SFR_MEM8(0xB3)
-
-  /* OCR2A */
-
-#define OCR2A0                          0
-#define OCR2A1                          1
-#define OCR2A2                          2
-#define OCR2A3                          3
-#define OCR2A4                          4
-#define OCR2A5                          5
-#define OCR2A6                          6
-#define OCR2A7                          7
-
-/* Timer/Counter2 Output Compare Register B */
-#define OCR2B                           _SFR_MEM8(0xB4)
-
-  /* OCR2B */
-
-#define OCR2B0                          0
-#define OCR2B1                          1
-#define OCR2B2                          2
-#define OCR2B3                          3
-#define OCR2B4                          4
-#define OCR2B5                          5
-#define OCR2B6                          6
-#define OCR2B7                          7
-
-/* Asynchronous Status Register */
-#define ASSR                            _SFR_MEM8(0xB6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ASSR {
-        unsigned int tcr2bub : 1;	/* Timer/Counter2 Control Register B Update Busy */
-        unsigned int tcr2aub : 1;	/* Timer/Counter2 Control Register A Update Busy */
-        unsigned int ocr2bub : 1;	/* Timer/Counter2 Output Compare Register B Update Busy */
-        unsigned int ocr2aub : 1;	/* Timer/Counter2 Output Compare Register A Update Busy */
-        unsigned int tcn2ub : 1;	/* Timer/Counter2 Update Busy */
-        unsigned int as2 : 1;	/* Timer/Counter2 Asynchronous Mode */
-        unsigned int exclk : 1;	/* Enable External Clock Input */
-        unsigned int exclkamr : 1;	/* Enable External Clock Input for AMR */
-};
-
-#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ASSR */
-
-#define TCR2BUB                         0
-#define TCR2AUB                         1
-#define OCR2BUB                         2
-#define OCR2AUB                         3
-#define TCN2UB                          4
-#define AS2                             5
-#define EXCLK                           6
-#define EXCLKAMR                        7
-
-/* TWI Bit Rate Register */
-#define TWBR                            _SFR_MEM8(0xB8)
-
-  /* TWBR */
-
-#define TWBR0                           0
-#define TWBR1                           1
-#define TWBR2                           2
-#define TWBR3                           3
-#define TWBR4                           4
-#define TWBR5                           5
-#define TWBR6                           6
-#define TWBR7                           7
-
-/* TWI Status Register */
-#define TWSR                            _SFR_MEM8(0xB9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWSR {
-        unsigned int twps : 2;	/* TWI Prescaler Bits */
-        unsigned int : 1;
-        unsigned int tws : 5;	/* TWI Status */
-};
-
-#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWSR */
-
-#define TWPS0                           0
-#define TWPS1                           1
-#define TWS3                            3
-#define TWS4                            4
-#define TWS5                            5
-#define TWS6                            6
-#define TWS7                            7
-
-/* TWI (Slave) Address Register */
-#define TWAR                            _SFR_MEM8(0xBA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAR {
-        unsigned int twgce : 1;	/* TWI General Call Recognition Enable Bit */
-        unsigned int twa : 7;	/* TWI (Slave) Address */
-};
-
-#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAR */
-
-#define TWGCE                           0
-#define TWA0                            1
-#define TWA1                            2
-#define TWA2                            3
-#define TWA3                            4
-#define TWA4                            5
-#define TWA5                            6
-#define TWA6                            7
-
-/* TWI Data Register */
-#define TWDR                            _SFR_MEM8(0xBB)
-
-  /* TWDR */
-
-#define TWD0                            0
-#define TWD1                            1
-#define TWD2                            2
-#define TWD3                            3
-#define TWD4                            4
-#define TWD5                            5
-#define TWD6                            6
-#define TWD7                            7
-
-/* TWI Control Register */
-#define TWCR                            _SFR_MEM8(0xBC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWCR {
-        unsigned int twie : 1;	/* TWI Interrupt Enable */
-        unsigned int : 1;
-        unsigned int twen : 1;	/* TWI Enable Bit */
-        unsigned int twwc : 1;	/* TWI Write Collision Flag */
-        unsigned int twsto : 1;	/* TWI STOP Condition Bit */
-        unsigned int twsta : 1;	/* TWI START Condition Bit */
-        unsigned int twea : 1;	/* TWI Enable Acknowledge Bit */
-        unsigned int twint : 1;	/* TWI Interrupt Flag */
-};
-
-#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWCR */
-
-#define TWIE                            0
-#define TWEN                            2
-#define TWWC                            3
-#define TWSTO                           4
-#define TWSTA                           5
-#define TWEA                            6
-#define TWINT                           7
-
-/* TWI (Slave) Address Mask Register */
-#define TWAMR                           _SFR_MEM8(0xBD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAMR {
-        unsigned int : 1;
-        unsigned int twam : 7;	/* TWI Address Mask */
-};
-
-#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAMR */
-
-#define TWAM0                           1
-#define TWAMR0                          1
-#define TWAM1                           2
-#define TWAMR1                          2
-#define TWAM2                           3
-#define TWAMR2                          3
-#define TWAM3                           4
-#define TWAMR3                          4
-#define TWAM4                           5
-#define TWAMR4                          5
-#define TWAM5                           6
-#define TWAMR5                          6
-#define TWAM6                           7
-#define TWAMR6                          7
-
-/* Transceiver Interrupt Enable Register 1 */
-#define IRQ_MASK1                       _SFR_MEM8(0xBE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK1 {
-        unsigned int tx_start_en : 1;	/* Transmit Start Interrupt enable */
-        unsigned int maf_0_ami_en : 1;	/* Address Match Interrupt enable Address filter 0 */
-        unsigned int maf_1_ami_en : 1;	/* Address Match Interrupt enable Address filter 1 */
-        unsigned int maf_2_ami_en : 1;	/* Address Match Interrupt enable Address filter 2 */
-        unsigned int maf_3_ami_en : 1;	/* Address Match Interrupt enable Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_MASK1_struct _SFR_MEM8_STRUCT(0xbe, struct __reg_IRQ_MASK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK1 */
-
-#define TX_START_EN                     0
-#define MAF_0_AMI_EN                    1
-#define MAF_1_AMI_EN                    2
-#define MAF_2_AMI_EN                    3
-#define MAF_3_AMI_EN                    4
-
-/* Transceiver Interrupt Status Register 1 */
-#define IRQ_STATUS1                     _SFR_MEM8(0xBF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS1 {
-        unsigned int tx_start : 1;	/* Transmit Start Interrupt Status */
-        unsigned int maf_0_ami : 1;	/* Address Match Interrupt Status Address filter 0 */
-        unsigned int maf_1_ami : 1;	/* Address Match Interrupt Status Address filter 1 */
-        unsigned int maf_2_ami : 1;	/* Address Match Interrupt Status Address filter 2 */
-        unsigned int maf_3_ami : 1;	/* Address Match Interrupt Status Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_STATUS1_struct _SFR_MEM8_STRUCT(0xbf, struct __reg_IRQ_STATUS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS1 */
-
-#define TX_START                        0
-#define MAF_0_AMI                       1
-#define MAF_1_AMI                       2
-#define MAF_2_AMI                       3
-#define MAF_3_AMI                       4
-
-/* USART0 Control and Status Register A */
-#define UCSR0A                          _SFR_MEM8(0xC0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0A {
-        unsigned int mpcm0 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x0 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe0 : 1;	/* USART Parity Error */
-        unsigned int dor0 : 1;	/* Data OverRun */
-        unsigned int fe0 : 1;	/* Frame Error */
-        unsigned int udre0 : 1;	/* USART Data Register Empty */
-        unsigned int txc0 : 1;	/* USART Transmit Complete */
-        unsigned int rxc0 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0A */
-
-#define MPCM0                           0
-#define U2X0                            1
-#define UPE0                            2
-#define DOR0                            3
-#define FE0                             4
-#define UDRE0                           5
-#define TXC0                            6
-#define RXC0                            7
-
-/* USART0 Control and Status Register B */
-#define UCSR0B                          _SFR_MEM8(0xC1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0B {
-        unsigned int txb80 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb80 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz02 : 1;	/* Character Size */
-        unsigned int txen0 : 1;	/* Transmitter Enable */
-        unsigned int rxen0 : 1;	/* Receiver Enable */
-        unsigned int udrie0 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie0 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie0 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0B */
-
-#define TXB80                           0
-#define RXB80                           1
-#define UCSZ02                          2
-#define TXEN0                           3
-#define RXEN0                           4
-#define UDRIE0                          5
-#define TXCIE0                          6
-#define RXCIE0                          7
-
-/* USART0 Control and Status Register C */
-#define UCSR0C                          _SFR_MEM8(0xC2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0C {
-        unsigned int ucpol0 : 1;	/* Clock Polarity */
-        unsigned int ucsz0 : 2;	/* Character Size */
-        unsigned int ucpha0 : 1;	/* Clock Phase */
-        unsigned int udord0 : 1;	/* Data Order */
-        unsigned int usbs0 : 1;	/* Stop Bit Select */
-        unsigned int upm0 : 2;	/* Parity Mode */
-        unsigned int umsel0 : 2;	/* USART Mode Select */
-};
-
-#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0C */
-
-#define UCPOL0                          0
-#define UCPHA0                          1
-#define UCPHA0                          1
-#define UCSZ00                          1
-#define UDORD0                          2
-#define UDORD0                          2
-#define UCSZ01                          2
-#define USBS0                           3
-#define UPM00                           4
-#define UPM01                           5
-#define UMSEL00                         6
-#define UMSEL0                          6
-#define UMSEL01                         7
-#define UMSEL1                          7
-
-/* USART0 Baud Rate Register  Bytes */
-#define UBRR0                           _SFR_MEM16(0xC4)
-#define UBRR0L                          _SFR_MEM8(0xC4)
-#define UBRR0H                          _SFR_MEM8(0xC5)
-
-/* USART0 I/O Data Register */
-#define UDR0                            _SFR_MEM8(0xC6)
-
-  /* UDR0 */
-
-#define UDR00                           0
-#define UDR01                           1
-#define UDR02                           2
-#define UDR03                           3
-#define UDR04                           4
-#define UDR05                           5
-#define UDR06                           6
-#define UDR07                           7
-
-/* USART1 Control and Status Register A */
-#define UCSR1A                          _SFR_MEM8(0xC8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1A {
-        unsigned int mpcm1 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x1 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe1 : 1;	/* USART Parity Error */
-        unsigned int dor1 : 1;	/* Data OverRun */
-        unsigned int fe1 : 1;	/* Frame Error */
-        unsigned int udre1 : 1;	/* USART Data Register Empty */
-        unsigned int txc1 : 1;	/* USART Transmit Complete */
-        unsigned int rxc1 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1A */
-
-#define MPCM1                           0
-#define U2X1                            1
-#define UPE1                            2
-#define DOR1                            3
-#define FE1                             4
-#define UDRE1                           5
-#define TXC1                            6
-#define RXC1                            7
-
-/* USART1 Control and Status Register B */
-#define UCSR1B                          _SFR_MEM8(0xC9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1B {
-        unsigned int txb81 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb81 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz12 : 1;	/* Character Size */
-        unsigned int txen1 : 1;	/* Transmitter Enable */
-        unsigned int rxen1 : 1;	/* Receiver Enable */
-        unsigned int udrie1 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie1 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie1 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1B */
-
-#define TXB81                           0
-#define RXB81                           1
-#define UCSZ12                          2
-#define TXEN1                           3
-#define RXEN1                           4
-#define UDRIE1                          5
-#define TXCIE1                          6
-#define RXCIE1                          7
-
-/* USART1 Control and Status Register C */
-#define UCSR1C                          _SFR_MEM8(0xCA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1C {
-        unsigned int ucpol1 : 1;	/* Clock Polarity */
-        unsigned int ucsz1 : 2;	/* Character Size */
-        unsigned int ucpha1 : 1;	/* Clock Phase */
-        unsigned int udord1 : 1;	/* Data Order */
-        unsigned int usbs1 : 1;	/* Stop Bit Select */
-        unsigned int upm1 : 2;	/* Parity Mode */
-        unsigned int umsel1 : 2;	/* USART Mode Select */
-};
-
-#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1C */
-
-#define UCPOL1                          0
-#define UCPHA1                          1
-#define UCPHA1                          1
-#define UCSZ10                          1
-#define UDORD1                          2
-#define UDORD1                          2
-#define UCSZ11                          2
-#define USBS1                           3
-#define UPM10                           4
-#define UPM11                           5
-#define UMSEL10                         6
-#define UMSEL11                         7
-
-/* USART1 Baud Rate Register  Bytes */
-#define UBRR1                           _SFR_MEM16(0xCC)
-#define UBRR1L                          _SFR_MEM8(0xCC)
-#define UBRR1H                          _SFR_MEM8(0xCD)
-
-/* USART1 I/O Data Register */
-#define UDR1                            _SFR_MEM8(0xCE)
-
-  /* UDR1 */
-
-#define UDR10                           0
-#define UDR11                           1
-#define UDR12                           2
-#define UDR13                           3
-#define UDR14                           4
-#define UDR15                           5
-#define UDR16                           6
-#define UDR17                           7
-
-/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-#define SCRSTRLL                        _SFR_MEM8(0xD7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLL {
-        unsigned int scrstrll : 8;	/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-};
-
-#define SCRSTRLL_struct _SFR_MEM8_STRUCT(0xd7, struct __reg_SCRSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLL */
-
-#define SCRSTRLL0                       0
-#define SCRSTRLL1                       1
-#define SCRSTRLL2                       2
-#define SCRSTRLL3                       3
-#define SCRSTRLL4                       4
-#define SCRSTRLL5                       5
-#define SCRSTRLL6                       6
-#define SCRSTRLL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-#define SCRSTRLH                        _SFR_MEM8(0xD8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLH {
-        unsigned int scrstrlh : 8;	/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-};
-
-#define SCRSTRLH_struct _SFR_MEM8_STRUCT(0xd8, struct __reg_SCRSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLH */
-
-#define SCRSTRLH0                       0
-#define SCRSTRLH1                       1
-#define SCRSTRLH2                       2
-#define SCRSTRLH3                       3
-#define SCRSTRLH4                       4
-#define SCRSTRLH5                       5
-#define SCRSTRLH6                       6
-#define SCRSTRLH7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-#define SCRSTRHL                        _SFR_MEM8(0xD9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHL {
-        unsigned int scrstrhl : 8;	/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-};
-
-#define SCRSTRHL_struct _SFR_MEM8_STRUCT(0xd9, struct __reg_SCRSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHL */
-
-#define SCRSTRHL0                       0
-#define SCRSTRHL1                       1
-#define SCRSTRHL2                       2
-#define SCRSTRHL3                       3
-#define SCRSTRHL4                       4
-#define SCRSTRHL5                       5
-#define SCRSTRHL6                       6
-#define SCRSTRHL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-#define SCRSTRHH                        _SFR_MEM8(0xDA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHH {
-        unsigned int scrstrhh : 8;	/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-};
-
-#define SCRSTRHH_struct _SFR_MEM8_STRUCT(0xda, struct __reg_SCRSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHH */
-
-#define SCRSTRHH0                       0
-#define SCRSTRHH1                       1
-#define SCRSTRHH2                       2
-#define SCRSTRHH3                       3
-#define SCRSTRHH4                       4
-#define SCRSTRHH5                       5
-#define SCRSTRHH6                       6
-#define SCRSTRHH7                       7
-
-/* Symbol Counter Compare Source Register */
-#define SCCSR                           _SFR_MEM8(0xDB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCSR {
-        unsigned int sccs1 : 2;	/* Symbol Counter Compare Source select register for Compare Units */
-        unsigned int sccs2 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 2 */
-        unsigned int sccs3 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 3 */
-        unsigned int : 2;
-};
-
-#define SCCSR_struct _SFR_MEM8_STRUCT(0xdb, struct __reg_SCCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCSR */
-
-#define SCCS10                          0
-#define SCCS11                          1
-#define SCCS20                          2
-#define SCCS21                          3
-#define SCCS30                          4
-#define SCCS31                          5
-
-/* Symbol Counter Control Register 0 */
-#define SCCR0                           _SFR_MEM8(0xDC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR0 {
-        unsigned int sccmp : 3;	/* Symbol Counter Compare Unit 3 Mode select */
-        unsigned int sctse : 1;	/* Symbol Counter Automatic Timestamping enable */
-        unsigned int sccksel : 1;	/* Symbol Counter Clock Source select */
-        unsigned int scen : 1;	/* Symbol Counter enable */
-        unsigned int scmbts : 1;	/* Manual Beacon Timestamp */
-        unsigned int scres : 1;	/* Symbol Counter Synchronization */
-};
-
-#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR0 */
-
-#define SCCMP1                          0
-#define SCCMP2                          1
-#define SCCMP3                          2
-#define SCTSE                           3
-#define SCCKSEL                         4
-#define SCEN                            5
-#define SCMBTS                          6
-#define SCRES                           7
-
-/* Symbol Counter Control Register 1 */
-#define SCCR1                           _SFR_MEM8(0xDD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR1 {
-        unsigned int scenbo : 1;	/* Backoff Slot Counter enable */
-        unsigned int sceeclk : 1;	/* Enable External Clock Source on PG2 */
-        unsigned int scckdiv : 3;	/* Clock divider for synchronous clock source (16MHz Transceiver Clock) */
-        unsigned int scbtsm : 1;	/* Symbol Counter Beacon Timestamp Mask Register */
-        unsigned int : 2;
-};
-
-#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR1 */
-
-#define SCENBO                          0
-#define SCEECLK                         1
-#define SCCKDIV0                        2
-#define SCCKDIV1                        3
-#define SCCKDIV2                        4
-#define SCBTSM                          5
-
-/* Symbol Counter Status Register */
-#define SCSR                            _SFR_MEM8(0xDE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCSR {
-        unsigned int scbsy : 1;	/* Symbol Counter busy */
-        unsigned int : 7;
-};
-
-#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCSR */
-
-#define SCBSY                           0
-
-/* Symbol Counter Interrupt Mask Register */
-#define SCIRQM                          _SFR_MEM8(0xDF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQM {
-        unsigned int irqmcp : 3;	/* Symbol Counter Compare Match 3 IRQ enable */
-        unsigned int irqmof : 1;	/* Symbol Counter Overflow IRQ enable */
-        unsigned int irqmbo : 1;	/* Backoff Slot Counter IRQ enable */
-        unsigned int : 3;
-};
-
-#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQM */
-
-#define IRQMCP1                         0
-#define IRQMCP2                         1
-#define IRQMCP3                         2
-#define IRQMOF                          3
-#define IRQMBO                          4
-
-/* Symbol Counter Interrupt Status Register */
-#define SCIRQS                          _SFR_MEM8(0xE0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQS {
-        unsigned int irqscp : 3;	/* Compare Unit 3 Compare Match IRQ */
-        unsigned int irqsof : 1;	/* Symbol Counter Overflow IRQ */
-        unsigned int irqsbo : 1;	/* Backoff Slot Counter IRQ */
-        unsigned int : 3;
-};
-
-#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQS */
-
-#define IRQSCP1                         0
-#define IRQSCP2                         1
-#define IRQSCP3                         2
-#define IRQSOF                          3
-#define IRQSBO                          4
-
-/* Symbol Counter Register LL-Byte */
-#define SCCNTLL                         _SFR_MEM8(0xE1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLL {
-        unsigned int sccntll : 8;	/* Symbol Counter Register LL-Byte */
-};
-
-#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLL */
-
-#define SCCNTLL0                        0
-#define SCCNTLL1                        1
-#define SCCNTLL2                        2
-#define SCCNTLL3                        3
-#define SCCNTLL4                        4
-#define SCCNTLL5                        5
-#define SCCNTLL6                        6
-#define SCCNTLL7                        7
-
-/* Symbol Counter Register LH-Byte */
-#define SCCNTLH                         _SFR_MEM8(0xE2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLH {
-        unsigned int sccntlh : 8;	/* Symbol Counter Register LH-Byte */
-};
-
-#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLH */
-
-#define SCCNTLH0                        0
-#define SCCNTLH1                        1
-#define SCCNTLH2                        2
-#define SCCNTLH3                        3
-#define SCCNTLH4                        4
-#define SCCNTLH5                        5
-#define SCCNTLH6                        6
-#define SCCNTLH7                        7
-
-/* Symbol Counter Register HL-Byte */
-#define SCCNTHL                         _SFR_MEM8(0xE3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHL {
-        unsigned int sccnthl : 8;	/* Symbol Counter Register HL-Byte */
-};
-
-#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHL */
-
-#define SCCNTHL0                        0
-#define SCCNTHL1                        1
-#define SCCNTHL2                        2
-#define SCCNTHL3                        3
-#define SCCNTHL4                        4
-#define SCCNTHL5                        5
-#define SCCNTHL6                        6
-#define SCCNTHL7                        7
-
-/* Symbol Counter Register HH-Byte */
-#define SCCNTHH                         _SFR_MEM8(0xE4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHH {
-        unsigned int sccnthh : 8;	/* Symbol Counter Register HH-Byte */
-};
-
-#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHH */
-
-#define SCCNTHH0                        0
-#define SCCNTHH1                        1
-#define SCCNTHH2                        2
-#define SCCNTHH3                        3
-#define SCCNTHH4                        4
-#define SCCNTHH5                        5
-#define SCCNTHH6                        6
-#define SCCNTHH7                        7
-
-/* Symbol Counter Beacon Timestamp Register LL-Byte */
-#define SCBTSRLL                        _SFR_MEM8(0xE5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLL {
-        unsigned int scbtsrll : 8;	/* Symbol Counter Beacon Timestamp Register LL-Byte */
-};
-
-#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLL */
-
-#define SCBTSRLL0                       0
-#define SCBTSRLL1                       1
-#define SCBTSRLL2                       2
-#define SCBTSRLL3                       3
-#define SCBTSRLL4                       4
-#define SCBTSRLL5                       5
-#define SCBTSRLL6                       6
-#define SCBTSRLL7                       7
-
-/* Symbol Counter Beacon Timestamp Register LH-Byte */
-#define SCBTSRLH                        _SFR_MEM8(0xE6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLH {
-        unsigned int scbtsrlh : 8;	/* Symbol Counter Beacon Timestamp Register LH-Byte */
-};
-
-#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLH */
-
-#define SCBTSRLH0                       0
-#define SCBTSRLH1                       1
-#define SCBTSRLH2                       2
-#define SCBTSRLH3                       3
-#define SCBTSRLH4                       4
-#define SCBTSRLH5                       5
-#define SCBTSRLH6                       6
-#define SCBTSRLH7                       7
-
-/* Symbol Counter Beacon Timestamp Register HL-Byte */
-#define SCBTSRHL                        _SFR_MEM8(0xE7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHL {
-        unsigned int scbtsrhl : 8;	/* Symbol Counter Beacon Timestamp Register HL-Byte */
-};
-
-#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHL */
-
-#define SCBTSRHL0                       0
-#define SCBTSRHL1                       1
-#define SCBTSRHL2                       2
-#define SCBTSRHL3                       3
-#define SCBTSRHL4                       4
-#define SCBTSRHL5                       5
-#define SCBTSRHL6                       6
-#define SCBTSRHL7                       7
-
-/* Symbol Counter Beacon Timestamp Register HH-Byte */
-#define SCBTSRHH                        _SFR_MEM8(0xE8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHH {
-        unsigned int scbtsrhh : 8;	/* Symbol Counter Beacon Timestamp Register HH-Byte */
-};
-
-#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHH */
-
-#define SCBTSRHH0                       0
-#define SCBTSRHH1                       1
-#define SCBTSRHH2                       2
-#define SCBTSRHH3                       3
-#define SCBTSRHH4                       4
-#define SCBTSRHH5                       5
-#define SCBTSRHH6                       6
-#define SCBTSRHH7                       7
-
-/* Symbol Counter Frame Timestamp Register LL-Byte */
-#define SCTSRLL                         _SFR_MEM8(0xE9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLL {
-        unsigned int sctsrll : 8;	/* Symbol Counter Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLL */
-
-#define SCTSRLL0                        0
-#define SCTSRLL1                        1
-#define SCTSRLL2                        2
-#define SCTSRLL3                        3
-#define SCTSRLL4                        4
-#define SCTSRLL5                        5
-#define SCTSRLL6                        6
-#define SCTSRLL7                        7
-
-/* Symbol Counter Frame Timestamp Register LH-Byte */
-#define SCTSRLH                         _SFR_MEM8(0xEA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLH {
-        unsigned int sctsrlh : 8;	/* Symbol Counter Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLH */
-
-#define SCTSRLH0                        0
-#define SCTSRLH1                        1
-#define SCTSRLH2                        2
-#define SCTSRLH3                        3
-#define SCTSRLH4                        4
-#define SCTSRLH5                        5
-#define SCTSRLH6                        6
-#define SCTSRLH7                        7
-
-/* Symbol Counter Frame Timestamp Register HL-Byte */
-#define SCTSRHL                         _SFR_MEM8(0xEB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHL {
-        unsigned int sctsrhl : 8;	/* Symbol Counter Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHL */
-
-#define SCTSRHL0                        0
-#define SCTSRHL1                        1
-#define SCTSRHL2                        2
-#define SCTSRHL3                        3
-#define SCTSRHL4                        4
-#define SCTSRHL5                        5
-#define SCTSRHL6                        6
-#define SCTSRHL7                        7
-
-/* Symbol Counter Frame Timestamp Register HH-Byte */
-#define SCTSRHH                         _SFR_MEM8(0xEC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHH {
-        unsigned int sctsrhh : 8;	/* Symbol Counter Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHH */
-
-#define SCTSRHH0                        0
-#define SCTSRHH1                        1
-#define SCTSRHH2                        2
-#define SCTSRHH3                        3
-#define SCTSRHH4                        4
-#define SCTSRHH5                        5
-#define SCTSRHH6                        6
-#define SCTSRHH7                        7
-
-/* Symbol Counter Output Compare Register 3 LL-Byte */
-#define SCOCR3LL                        _SFR_MEM8(0xED)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LL {
-        unsigned int scocr3ll : 8;	/* Symbol Counter Output Compare Register 3 LL-Byte */
-};
-
-#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LL */
-
-#define SCOCR3LL0                       0
-#define SCOCR3LL1                       1
-#define SCOCR3LL2                       2
-#define SCOCR3LL3                       3
-#define SCOCR3LL4                       4
-#define SCOCR3LL5                       5
-#define SCOCR3LL6                       6
-#define SCOCR3LL7                       7
-
-/* Symbol Counter Output Compare Register 3 LH-Byte */
-#define SCOCR3LH                        _SFR_MEM8(0xEE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LH {
-        unsigned int scocr3lh : 8;	/* Symbol Counter Output Compare Register 3 LH-Byte */
-};
-
-#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LH */
-
-#define SCOCR3LH0                       0
-#define SCOCR3LH1                       1
-#define SCOCR3LH2                       2
-#define SCOCR3LH3                       3
-#define SCOCR3LH4                       4
-#define SCOCR3LH5                       5
-#define SCOCR3LH6                       6
-#define SCOCR3LH7                       7
-
-/* Symbol Counter Output Compare Register 3 HL-Byte */
-#define SCOCR3HL                        _SFR_MEM8(0xEF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HL {
-        unsigned int scocr3hl : 8;	/* Symbol Counter Output Compare Register 3 HL-Byte */
-};
-
-#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HL */
-
-#define SCOCR3HL0                       0
-#define SCOCR3HL1                       1
-#define SCOCR3HL2                       2
-#define SCOCR3HL3                       3
-#define SCOCR3HL4                       4
-#define SCOCR3HL5                       5
-#define SCOCR3HL6                       6
-#define SCOCR3HL7                       7
-
-/* Symbol Counter Output Compare Register 3 HH-Byte */
-#define SCOCR3HH                        _SFR_MEM8(0xF0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HH {
-        unsigned int scocr3hh : 8;	/* Symbol Counter Output Compare Register 3 HH-Byte */
-};
-
-#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HH */
-
-#define SCOCR3HH0                       0
-#define SCOCR3HH1                       1
-#define SCOCR3HH2                       2
-#define SCOCR3HH3                       3
-#define SCOCR3HH4                       4
-#define SCOCR3HH5                       5
-#define SCOCR3HH6                       6
-#define SCOCR3HH7                       7
-
-/* Symbol Counter Output Compare Register 2 LL-Byte */
-#define SCOCR2LL                        _SFR_MEM8(0xF1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LL {
-        unsigned int scocr2ll : 8;	/* Symbol Counter Output Compare Register 2 LL-Byte */
-};
-
-#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LL */
-
-#define SCOCR2LL0                       0
-#define SCOCR2LL1                       1
-#define SCOCR2LL2                       2
-#define SCOCR2LL3                       3
-#define SCOCR2LL4                       4
-#define SCOCR2LL5                       5
-#define SCOCR2LL6                       6
-#define SCOCR2LL7                       7
-
-/* Symbol Counter Output Compare Register 2 LH-Byte */
-#define SCOCR2LH                        _SFR_MEM8(0xF2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LH {
-        unsigned int scocr2lh : 8;	/* Symbol Counter Output Compare Register 2 LH-Byte */
-};
-
-#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LH */
-
-#define SCOCR2LH0                       0
-#define SCOCR2LH1                       1
-#define SCOCR2LH2                       2
-#define SCOCR2LH3                       3
-#define SCOCR2LH4                       4
-#define SCOCR2LH5                       5
-#define SCOCR2LH6                       6
-#define SCOCR2LH7                       7
-
-/* Symbol Counter Output Compare Register 2 HL-Byte */
-#define SCOCR2HL                        _SFR_MEM8(0xF3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HL {
-        unsigned int scocr2hl : 8;	/* Symbol Counter Output Compare Register 2 HL-Byte */
-};
-
-#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HL */
-
-#define SCOCR2HL0                       0
-#define SCOCR2HL1                       1
-#define SCOCR2HL2                       2
-#define SCOCR2HL3                       3
-#define SCOCR2HL4                       4
-#define SCOCR2HL5                       5
-#define SCOCR2HL6                       6
-#define SCOCR2HL7                       7
-
-/* Symbol Counter Output Compare Register 2 HH-Byte */
-#define SCOCR2HH                        _SFR_MEM8(0xF4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HH {
-        unsigned int scocr2hh : 8;	/* Symbol Counter Output Compare Register 2 HH-Byte */
-};
-
-#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HH */
-
-#define SCOCR2HH0                       0
-#define SCOCR2HH1                       1
-#define SCOCR2HH2                       2
-#define SCOCR2HH3                       3
-#define SCOCR2HH4                       4
-#define SCOCR2HH5                       5
-#define SCOCR2HH6                       6
-#define SCOCR2HH7                       7
-
-/* Symbol Counter Output Compare Register 1 LL-Byte */
-#define SCOCR1LL                        _SFR_MEM8(0xF5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LL {
-        unsigned int scocr1ll : 8;	/* Symbol Counter Output Compare Register 1 LL-Byte */
-};
-
-#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LL */
-
-#define SCOCR1LL0                       0
-#define SCOCR1LL1                       1
-#define SCOCR1LL2                       2
-#define SCOCR1LL3                       3
-#define SCOCR1LL4                       4
-#define SCOCR1LL5                       5
-#define SCOCR1LL6                       6
-#define SCOCR1LL7                       7
-
-/* Symbol Counter Output Compare Register 1 LH-Byte */
-#define SCOCR1LH                        _SFR_MEM8(0xF6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LH {
-        unsigned int scocr1lh : 8;	/* Symbol Counter Output Compare Register 1 LH-Byte */
-};
-
-#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LH */
-
-#define SCOCR1LH0                       0
-#define SCOCR1LH1                       1
-#define SCOCR1LH2                       2
-#define SCOCR1LH3                       3
-#define SCOCR1LH4                       4
-#define SCOCR1LH5                       5
-#define SCOCR1LH6                       6
-#define SCOCR1LH7                       7
-
-/* Symbol Counter Output Compare Register 1 HL-Byte */
-#define SCOCR1HL                        _SFR_MEM8(0xF7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HL {
-        unsigned int scocr1hl : 8;	/* Symbol Counter Output Compare Register 1 HL-Byte */
-};
-
-#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HL */
-
-#define SCOCR1HL0                       0
-#define SCOCR1HL1                       1
-#define SCOCR1HL2                       2
-#define SCOCR1HL3                       3
-#define SCOCR1HL4                       4
-#define SCOCR1HL5                       5
-#define SCOCR1HL6                       6
-#define SCOCR1HL7                       7
-
-/* Symbol Counter Output Compare Register 1 HH-Byte */
-#define SCOCR1HH                        _SFR_MEM8(0xF8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HH {
-        unsigned int scocr1hh : 8;	/* Symbol Counter Output Compare Register 1 HH-Byte */
-};
-
-#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HH */
-
-#define SCOCR1HH0                       0
-#define SCOCR1HH1                       1
-#define SCOCR1HH2                       2
-#define SCOCR1HH3                       3
-#define SCOCR1HH4                       4
-#define SCOCR1HH5                       5
-#define SCOCR1HH6                       6
-#define SCOCR1HH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-#define SCTSTRLL                        _SFR_MEM8(0xF9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLL {
-        unsigned int sctstrll : 8;	/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSTRLL_struct _SFR_MEM8_STRUCT(0xf9, struct __reg_SCTSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLL */
-
-#define SCTSTRLL0                       0
-#define SCTSTRLL1                       1
-#define SCTSTRLL2                       2
-#define SCTSTRLL3                       3
-#define SCTSTRLL4                       4
-#define SCTSTRLL5                       5
-#define SCTSTRLL6                       6
-#define SCTSTRLL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-#define SCTSTRLH                        _SFR_MEM8(0xFA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLH {
-        unsigned int sctstrlh : 8;	/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSTRLH_struct _SFR_MEM8_STRUCT(0xfa, struct __reg_SCTSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLH */
-
-#define SCTSTRLH0                       0
-#define SCTSTRLH1                       1
-#define SCTSTRLH2                       2
-#define SCTSTRLH3                       3
-#define SCTSTRLH4                       4
-#define SCTSTRLH5                       5
-#define SCTSTRLH6                       6
-#define SCTSTRLH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-#define SCTSTRHL                        _SFR_MEM8(0xFB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHL {
-        unsigned int sctstrhl : 8;	/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSTRHL_struct _SFR_MEM8_STRUCT(0xfb, struct __reg_SCTSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHL */
-
-#define SCTSTRHL0                       0
-#define SCTSTRHL1                       1
-#define SCTSTRHL2                       2
-#define SCTSTRHL3                       3
-#define SCTSTRHL4                       4
-#define SCTSTRHL5                       5
-#define SCTSTRHL6                       6
-#define SCTSTRHL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-#define SCTSTRHH                        _SFR_MEM8(0xFC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHH {
-        unsigned int sctstrhh : 8;	/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSTRHH_struct _SFR_MEM8_STRUCT(0xfc, struct __reg_SCTSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHH */
-
-#define SCTSTRHH0                       0
-#define SCTSTRHH1                       1
-#define SCTSTRHH2                       2
-#define SCTSTRHH3                       3
-#define SCTSTRHH4                       4
-#define SCTSTRHH5                       5
-#define SCTSTRHH6                       6
-#define SCTSTRHH7                       7
-
-/* Multiple Address Filter Configuration Register 0 */
-#define MAFCR0                          _SFR_MEM8(0x10C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR0 {
-        unsigned int maf0en : 1;	/* Multiple Address Filter 0 Enable */
-        unsigned int maf1en : 1;	/* Multiple Address Filter 1 Enable */
-        unsigned int maf2en : 1;	/* Multiple Address Filter 2 Enable */
-        unsigned int maf3en : 1;	/* Multiple Address Filter 3 Enable */
-        unsigned int : 4;
-};
-
-#define MAFCR0_struct _SFR_MEM8_STRUCT(0x10c, struct __reg_MAFCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR0 */
-
-#define MAF0EN                          0
-#define MAF1EN                          1
-#define MAF2EN                          2
-#define MAF3EN                          3
-
-/* Multiple Address Filter Configuration Register 1 */
-#define MAFCR1                          _SFR_MEM8(0x10D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR1 {
-        unsigned int aack_0_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 0. */
-        unsigned int aack_0_set_pd : 1;	/* Set Data Pending bit for address filter 0. */
-        unsigned int aack_1_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 1. */
-        unsigned int aack_1_set_pd : 1;	/* Set Data Pending bit for address filter 1. */
-        unsigned int aack_2_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 2. */
-        unsigned int aack_2_set_pd : 1;	/* Set Data Pending bit for address filter 2. */
-        unsigned int aack_3_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 3. */
-        unsigned int aack_3_set_pd : 1;	/* Set Data Pending bit for address filter 3. */
-};
-
-#define MAFCR1_struct _SFR_MEM8_STRUCT(0x10d, struct __reg_MAFCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR1 */
-
-#define AACK_0_I_AM_COORD               0
-#define AACK_0_SET_PD                   1
-#define AACK_1_I_AM_COORD               2
-#define AACK_1_SET_PD                   3
-#define AACK_2_I_AM_COORD               4
-#define AACK_2_SET_PD                   5
-#define AACK_3_I_AM_COORD               6
-#define AACK_3_SET_PD                   7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) */
-#define MAFSA0L                         _SFR_MEM8(0x10E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0L {
-        unsigned int mafsa0l : 8;	/* MAC Short Address low Byte for Frame Filter 0 */
-};
-
-#define MAFSA0L_struct _SFR_MEM8_STRUCT(0x10e, struct __reg_MAFSA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0L */
-
-#define MAFSA0L0                        0
-#define MAFSA0L1                        1
-#define MAFSA0L2                        2
-#define MAFSA0L3                        3
-#define MAFSA0L4                        4
-#define MAFSA0L5                        5
-#define MAFSA0L6                        6
-#define MAFSA0L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) */
-#define MAFSA0H                         _SFR_MEM8(0x10F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0H {
-        unsigned int mafsa0h : 8;	/* MAC Short Address high Byte for Frame Filter 0 */
-};
-
-#define MAFSA0H_struct _SFR_MEM8_STRUCT(0x10f, struct __reg_MAFSA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0H */
-
-#define MAFSA0H0                        0
-#define MAFSA0H1                        1
-#define MAFSA0H2                        2
-#define MAFSA0H3                        3
-#define MAFSA0H4                        4
-#define MAFSA0H5                        5
-#define MAFSA0H6                        6
-#define MAFSA0H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) */
-#define MAFPA0L                         _SFR_MEM8(0x110)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0L {
-        unsigned int mafpa0l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 0 */
-};
-
-#define MAFPA0L_struct _SFR_MEM8_STRUCT(0x110, struct __reg_MAFPA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0L */
-
-#define MAFPA0L0                        0
-#define MAFPA0L1                        1
-#define MAFPA0L2                        2
-#define MAFPA0L3                        3
-#define MAFPA0L4                        4
-#define MAFPA0L5                        5
-#define MAFPA0L6                        6
-#define MAFPA0L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) */
-#define MAFPA0H                         _SFR_MEM8(0x111)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0H {
-        unsigned int mafpa0h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 0 */
-};
-
-#define MAFPA0H_struct _SFR_MEM8_STRUCT(0x111, struct __reg_MAFPA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0H */
-
-#define MAFPA0H0                        0
-#define MAFPA0H1                        1
-#define MAFPA0H2                        2
-#define MAFPA0H3                        3
-#define MAFPA0H4                        4
-#define MAFPA0H5                        5
-#define MAFPA0H6                        6
-#define MAFPA0H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) */
-#define MAFSA1L                         _SFR_MEM8(0x112)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1L {
-        unsigned int mafsa1l : 8;	/* MAC Short Address low Byte for Frame Filter 1 */
-};
-
-#define MAFSA1L_struct _SFR_MEM8_STRUCT(0x112, struct __reg_MAFSA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1L */
-
-#define MAFSA1L0                        0
-#define MAFSA1L1                        1
-#define MAFSA1L2                        2
-#define MAFSA1L3                        3
-#define MAFSA1L4                        4
-#define MAFSA1L5                        5
-#define MAFSA1L6                        6
-#define MAFSA1L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) */
-#define MAFSA1H                         _SFR_MEM8(0x113)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1H {
-        unsigned int mafsa1h : 8;	/* MAC Short Address high Byte for Frame Filter 1 */
-};
-
-#define MAFSA1H_struct _SFR_MEM8_STRUCT(0x113, struct __reg_MAFSA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1H */
-
-#define MAFSA1H0                        0
-#define MAFSA1H1                        1
-#define MAFSA1H2                        2
-#define MAFSA1H3                        3
-#define MAFSA1H4                        4
-#define MAFSA1H5                        5
-#define MAFSA1H6                        6
-#define MAFSA1H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) */
-#define MAFPA1L                         _SFR_MEM8(0x114)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1L {
-        unsigned int mafpa1l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 1 */
-};
-
-#define MAFPA1L_struct _SFR_MEM8_STRUCT(0x114, struct __reg_MAFPA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1L */
-
-#define MAFPA1L0                        0
-#define MAFPA1L1                        1
-#define MAFPA1L2                        2
-#define MAFPA1L3                        3
-#define MAFPA1L4                        4
-#define MAFPA1L5                        5
-#define MAFPA1L6                        6
-#define MAFPA1L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) */
-#define MAFPA1H                         _SFR_MEM8(0x115)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1H {
-        unsigned int mafpa1h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 1 */
-};
-
-#define MAFPA1H_struct _SFR_MEM8_STRUCT(0x115, struct __reg_MAFPA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1H */
-
-#define MAFPA1H0                        0
-#define MAFPA1H1                        1
-#define MAFPA1H2                        2
-#define MAFPA1H3                        3
-#define MAFPA1H4                        4
-#define MAFPA1H5                        5
-#define MAFPA1H6                        6
-#define MAFPA1H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) */
-#define MAFSA2L                         _SFR_MEM8(0x116)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2L {
-        unsigned int mafsa2l : 8;	/* MAC Short Address low Byte for Frame Filter 2 */
-};
-
-#define MAFSA2L_struct _SFR_MEM8_STRUCT(0x116, struct __reg_MAFSA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2L */
-
-#define MAFSA2L0                        0
-#define MAFSA2L1                        1
-#define MAFSA2L2                        2
-#define MAFSA2L3                        3
-#define MAFSA2L4                        4
-#define MAFSA2L5                        5
-#define MAFSA2L6                        6
-#define MAFSA2L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) */
-#define MAFSA2H                         _SFR_MEM8(0x117)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2H {
-        unsigned int mafsa2h : 8;	/* MAC Short Address high Byte for Frame Filter 2 */
-};
-
-#define MAFSA2H_struct _SFR_MEM8_STRUCT(0x117, struct __reg_MAFSA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2H */
-
-#define MAFSA2H0                        0
-#define MAFSA2H1                        1
-#define MAFSA2H2                        2
-#define MAFSA2H3                        3
-#define MAFSA2H4                        4
-#define MAFSA2H5                        5
-#define MAFSA2H6                        6
-#define MAFSA2H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) */
-#define MAFPA2L                         _SFR_MEM8(0x118)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2L {
-        unsigned int mafpa2l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 2 */
-};
-
-#define MAFPA2L_struct _SFR_MEM8_STRUCT(0x118, struct __reg_MAFPA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2L */
-
-#define MAFPA2L0                        0
-#define MAFPA2L1                        1
-#define MAFPA2L2                        2
-#define MAFPA2L3                        3
-#define MAFPA2L4                        4
-#define MAFPA2L5                        5
-#define MAFPA2L6                        6
-#define MAFPA2L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) */
-#define MAFPA2H                         _SFR_MEM8(0x119)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2H {
-        unsigned int mafpa2h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 2 */
-};
-
-#define MAFPA2H_struct _SFR_MEM8_STRUCT(0x119, struct __reg_MAFPA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2H */
-
-#define MAFPA2H0                        0
-#define MAFPA2H1                        1
-#define MAFPA2H2                        2
-#define MAFPA2H3                        3
-#define MAFPA2H4                        4
-#define MAFPA2H5                        5
-#define MAFPA2H6                        6
-#define MAFPA2H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) */
-#define MAFSA3L                         _SFR_MEM8(0x11A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3L {
-        unsigned int mafsa3l : 8;	/* MAC Short Address low Byte for Frame Filter 3 */
-};
-
-#define MAFSA3L_struct _SFR_MEM8_STRUCT(0x11a, struct __reg_MAFSA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3L */
-
-#define MAFSA3L0                        0
-#define MAFSA3L1                        1
-#define MAFSA3L2                        2
-#define MAFSA3L3                        3
-#define MAFSA3L4                        4
-#define MAFSA3L5                        5
-#define MAFSA3L6                        6
-#define MAFSA3L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) */
-#define MAFSA3H                         _SFR_MEM8(0x11B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3H {
-        unsigned int mafsa3h : 8;	/* MAC Short Address high Byte for Frame Filter 3 */
-};
-
-#define MAFSA3H_struct _SFR_MEM8_STRUCT(0x11b, struct __reg_MAFSA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3H */
-
-#define MAFSA3H0                        0
-#define MAFSA3H1                        1
-#define MAFSA3H2                        2
-#define MAFSA3H3                        3
-#define MAFSA3H4                        4
-#define MAFSA3H5                        5
-#define MAFSA3H6                        6
-#define MAFSA3H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) */
-#define MAFPA3L                         _SFR_MEM8(0x11C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3L {
-        unsigned int mafpa3l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 3 */
-};
-
-#define MAFPA3L_struct _SFR_MEM8_STRUCT(0x11c, struct __reg_MAFPA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3L */
-
-#define MAFPA3L0                        0
-#define MAFPA3L1                        1
-#define MAFPA3L2                        2
-#define MAFPA3L3                        3
-#define MAFPA3L4                        4
-#define MAFPA3L5                        5
-#define MAFPA3L6                        6
-#define MAFPA3L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) */
-#define MAFPA3H                         _SFR_MEM8(0x11D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3H {
-        unsigned int mafpa3h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 3 */
-};
-
-#define MAFPA3H_struct _SFR_MEM8_STRUCT(0x11d, struct __reg_MAFPA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3H */
-
-#define MAFPA3H0                        0
-#define MAFPA3H1                        1
-#define MAFPA3H2                        2
-#define MAFPA3H3                        3
-#define MAFPA3H4                        4
-#define MAFPA3H5                        5
-#define MAFPA3H6                        6
-#define MAFPA3H7                        7
-
-/* Timer/Counter5 Control Register A */
-#define TCCR5A                          _SFR_MEM8(0x120)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5A {
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int com5c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com5b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com5a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5A */
-
-#define WGM50                           0
-#define WGM51                           1
-#define COM5C0                          2
-#define COM5C1                          3
-#define COM5B0                          4
-#define COM5B1                          5
-#define COM5A0                          6
-#define COM5A1                          7
-
-/* Timer/Counter5 Control Register B */
-#define TCCR5B                          _SFR_MEM8(0x121)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5B {
-        unsigned int cs5 : 3;	/* Clock Select */
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices5 : 1;	/* Input Capture 5 Edge Select */
-        unsigned int icnc5 : 1;	/* Input Capture 5 Noise Canceller */
-};
-
-#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5B */
-
-#define CS50                            0
-#define CS51                            1
-#define CS52                            2
-#define WGM52                           3
-#define WGM53                           4
-#define ICES5                           6
-#define ICNC5                           7
-
-/* Timer/Counter5 Control Register C */
-#define TCCR5C                          _SFR_MEM8(0x122)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5C {
-        unsigned int : 5;
-        unsigned int foc5c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc5b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc5a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5C */
-
-#define FOC5C                           5
-#define FOC5B                           6
-#define FOC5A                           7
-
-/* Timer/Counter5  Bytes */
-#define TCNT5                           _SFR_MEM16(0x124)
-#define TCNT5L                          _SFR_MEM8(0x124)
-#define TCNT5H                          _SFR_MEM8(0x125)
-
-/* Timer/Counter5 Input Capture Register  Bytes */
-#define ICR5                            _SFR_MEM16(0x126)
-#define ICR5L                           _SFR_MEM8(0x126)
-#define ICR5H                           _SFR_MEM8(0x127)
-
-/* Timer/Counter5 Output Compare Register A  Bytes */
-#define OCR5A                           _SFR_MEM16(0x128)
-#define OCR5AL                          _SFR_MEM8(0x128)
-#define OCR5AH                          _SFR_MEM8(0x129)
-
-/* Timer/Counter5 Output Compare Register B  Bytes */
-#define OCR5B                           _SFR_MEM16(0x12A)
-#define OCR5BL                          _SFR_MEM8(0x12A)
-#define OCR5BH                          _SFR_MEM8(0x12B)
-
-/* Timer/Counter5 Output Compare Register C  Bytes */
-#define OCR5C                           _SFR_MEM16(0x12C)
-#define OCR5CL                          _SFR_MEM8(0x12C)
-#define OCR5CH                          _SFR_MEM8(0x12D)
-
-/* Low Leakage Voltage Regulator Control Register */
-#define LLCR                            _SFR_MEM8(0x12F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLCR {
-        unsigned int llencal : 1;	/* Enable Automatic Calibration */
-        unsigned int llshort : 1;	/* Short Lower Calibration Circuit */
-        unsigned int lltco : 1;	/* Temperature Coefficient of Current Source */
-        unsigned int llcal : 1;	/* Calibration Active */
-        unsigned int llcomp : 1;	/* Comparator Output */
-        unsigned int lldone : 1;	/* Calibration Done */
-        unsigned int : 2;
-};
-
-#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLCR */
-
-#define LLENCAL                         0
-#define LLSHORT                         1
-#define LLTCO                           2
-#define LLCAL                           3
-#define LLCOMP                          4
-#define LLDONE                          5
-
-/* Low Leakage Voltage Regulator Data Register (Low-Byte) */
-#define LLDRL                           _SFR_MEM8(0x130)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRL {
-        unsigned int lldrl : 4;	/* Low-Byte Data Register Bits */
-        unsigned int : 4;
-};
-
-#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRL */
-
-#define LLDRL0                          0
-#define LLDRL1                          1
-#define LLDRL2                          2
-#define LLDRL3                          3
-
-/* Low Leakage Voltage Regulator Data Register (High-Byte) */
-#define LLDRH                           _SFR_MEM8(0x131)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRH {
-        unsigned int lldrh : 5;	/* High-Byte Data Register Bits */
-        unsigned int : 3;
-};
-
-#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRH */
-
-#define LLDRH0                          0
-#define LLDRH1                          1
-#define LLDRH2                          2
-#define LLDRH3                          3
-#define LLDRH4                          4
-
-/* Data Retention Configuration Register #3 */
-#define DRTRAM3                         _SFR_MEM8(0x132)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM3 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM3 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #2 */
-#define DRTRAM2                         _SFR_MEM8(0x133)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM2 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM2 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #1 */
-#define DRTRAM1                         _SFR_MEM8(0x134)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM1 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM1 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #0 */
-#define DRTRAM0                         _SFR_MEM8(0x135)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM0 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM0 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Port Driver Strength Register 0 */
-#define DPDS0                           _SFR_MEM8(0x136)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS0 {
-        unsigned int pbdrv : 2;	/* Driver Strength Port B */
-        unsigned int pddrv : 2;	/* Driver Strength Port D */
-        unsigned int pedrv : 2;	/* Driver Strength Port E */
-        unsigned int pfdrv : 2;	/* Driver Strength Port F */
-};
-
-#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS0 */
-
-#define PBDRV0                          0
-#define PBDRV1                          1
-#define PDDRV0                          2
-#define PDDRV1                          3
-#define PEDRV0                          4
-#define PEDRV1                          5
-#define PFDRV0                          6
-#define PFDRV1                          7
-
-/* Port Driver Strength Register 1 */
-#define DPDS1                           _SFR_MEM8(0x137)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS1 {
-        unsigned int pgdrv : 2;	/* Driver Strength Port G */
-        unsigned int : 6;
-};
-
-#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS1 */
-
-#define PGDRV0                          0
-#define PGDRV1                          1
-
-/* Power Amplifier Ramp up/down Control Register */
-#define PARCR                           _SFR_MEM8(0x138)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PARCR {
-        unsigned int parufi : 1;	/* Power Amplifier Ramp Up Frequency Inversion */
-        unsigned int pardfi : 1;	/* Power Amplifier Ramp Down Frequency Inversion */
-        unsigned int paltu : 3;	/* ext. PA Ramp Up Lead Time */
-        unsigned int paltd : 3;	/* ext. PA Ramp Down Lead Time */
-};
-
-#define PARCR_struct _SFR_MEM8_STRUCT(0x138, struct __reg_PARCR)
-
-/* symbolic names */
-
-#define PALTU_MINUS_3US                 0
-#define PALTU_MINUS_2US                 1
-#define PALTU_MINUS_1US                 2
-#define PALTU_0US                       3
-#define PALTU_1US                       4
-#define PALTU_2US                       5
-#define PALTU_3US                       6
-#define PALTU_4US                       7
-#define PALTD_MINUS_3US                 0
-#define PALTD_MINUS_2US                 1
-#define PALTD_MINUS_1US                 2
-#define PALTD_0US                       3
-#define PALTD_1US                       4
-#define PALTD_2US                       5
-#define PALTD_3US                       6
-#define PALTD_4US                       7
-
-#endif /* __ASSEMBLER__ */
-
-  /* PARCR */
-
-#define PARUFI                          0
-#define PARDFI                          1
-#define PALTU0                          2
-#define PALTU1                          3
-#define PALTU2                          4
-#define PALTD0                          5
-#define PALTD1                          6
-#define PALTD2                          7
-
-/* Transceiver Pin Register */
-#define TRXPR                           _SFR_MEM8(0x139)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRXPR {
-        unsigned int trxrst : 1;	/* Force Transceiver Reset */
-        unsigned int slptr : 1;	/* Multi-purpose Transceiver Control Bit */
-        unsigned int : 6;
-};
-
-#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRXPR */
-
-#define TRXRST                          0
-#define SLPTR                           1
-
-/* AES Control Register */
-#define AES_CTRL                        _SFR_MEM8(0x13C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_CTRL {
-        unsigned int : 2;
-        unsigned int aes_im : 1;	/* AES Interrupt Enable */
-        unsigned int aes_dir : 1;	/* Set AES Operation Direction */
-        unsigned int : 1;
-        unsigned int aes_mode : 1;	/* Set AES Operation Mode */
-        unsigned int : 1;
-        unsigned int aes_request : 1;	/* Request AES Operation. */
-};
-
-#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL)
-
-/* symbolic names */
-
-#define AES_DIR_ENC                     0
-#define AES_DIR_DEC                     1
-#define AES_MODE_ECB                    0
-#define AES_MODE_CBC                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_CTRL */
-
-#define AES_IM                          2
-#define AES_DIR                         3
-#define AES_MODE                        5
-#define AES_REQUEST                     7
-
-/* AES Status Register */
-#define AES_STATUS                      _SFR_MEM8(0x13D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATUS {
-        unsigned int aes_done : 1;	/* AES Operation Finished with Success */
-        unsigned int : 6;
-        unsigned int aes_er : 1;	/* AES Operation Finished with Error */
-};
-
-#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATUS */
-
-#define AES_DONE                        0
-#define AES_ER                          7
-
-/* AES Plain and Cipher Text Buffer Register */
-#define AES_STATE                       _SFR_MEM8(0x13E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATE {
-        unsigned int aes_state : 8;	/* AES Plain and Cipher Text Buffer */
-};
-
-#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATE */
-
-#define AES_STATE0                      0
-#define AES_STATE1                      1
-#define AES_STATE2                      2
-#define AES_STATE3                      3
-#define AES_STATE4                      4
-#define AES_STATE5                      5
-#define AES_STATE6                      6
-#define AES_STATE7                      7
-
-/* AES Encryption and Decryption Key Buffer Register */
-#define AES_KEY                         _SFR_MEM8(0x13F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_KEY {
-        unsigned int aes_key : 8;	/* AES Encryption/Decryption Key Buffer */
-};
-
-#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_KEY */
-
-#define AES_KEY0                        0
-#define AES_KEY1                        1
-#define AES_KEY2                        2
-#define AES_KEY3                        3
-#define AES_KEY4                        4
-#define AES_KEY5                        5
-#define AES_KEY6                        6
-#define AES_KEY7                        7
-
-/* Transceiver Status Register */
-#define TRX_STATUS                      _SFR_MEM8(0x141)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATUS {
-        unsigned int trx_status : 5;	/* Transceiver Main Status */
-        unsigned int tst_status : 1;	/* Test mode status */
-        unsigned int cca_status : 1;	/* CCA Status Result */
-        unsigned int cca_done : 1;	/* CCA Algorithm Status */
-};
-
-#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS)
-
-/* symbolic names */
-
-#define BUSY_RX                         1
-#define BUSY_TX                         2
-#define RX_ON                           6
-#define TRX_OFF                         8
-#define PLL_ON                          9
-#define SLEEP                           15
-#define BUSY_RX_AACK                    17
-#define BUSY_TX_ARET                    18
-#define RX_AACK_ON                      22
-#define TX_ARET_ON                      25
-#define STATE_TRANSITION_IN_PROGRESS    31
-#define TST_DISABLED                    0
-#define TST_ENABLED                     1
-#define CCA_BUSY                        0
-#define CCA_IDLE                        1
-#define CCA_NOT_FIN                     0
-#define CCA_FIN                         1
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATUS */
-
-#define TRX_STATUS0                     0
-#define TRX_STATUS1                     1
-#define TRX_STATUS2                     2
-#define TRX_STATUS3                     3
-#define TRX_STATUS4                     4
-#define TST_STATUS                      5
-#define CCA_STATUS                      6
-#define CCA_DONE                        7
-
-/* Transceiver State Control Register */
-#define TRX_STATE                       _SFR_MEM8(0x142)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATE {
-        unsigned int trx_cmd : 5;	/* State Control Command */
-        unsigned int trac_status : 3;	/* Transaction Status */
-};
-
-#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE)
-
-/* symbolic names */
-
-#define CMD_NOP                         0
-#define CMD_TX_START                    2
-#define CMD_FORCE_TRX_OFF               3
-#define CMD_FORCE_PLL_ON                4
-#define CMD_RX_ON                       6
-#define CMD_TRX_OFF                     8
-#define CMD_PLL_ON                      9
-#define CMD_RX_AACK_ON                  22
-#define CMD_TX_ARET_ON                  25
-#define TRAC_SUCCESS                    0
-#define TRAC_SUCCESS_DATA_PENDING       1
-#define TRAC_SUCCESS_WAIT_FOR_ACK       2
-#define TRAC_CHANNEL_ACCESS_FAILURE     3
-#define TRAC_NO_ACK                     5
-#define TRAC_INVALID                    7
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATE */
-
-#define TRX_CMD0                        0
-#define TRX_CMD1                        1
-#define TRX_CMD2                        2
-#define TRX_CMD3                        3
-#define TRX_CMD4                        4
-#define TRAC_STATUS0                    5
-#define TRAC_STATUS1                    6
-#define TRAC_STATUS2                    7
-
-/* Reserved */
-#define TRX_CTRL_0                      _SFR_MEM8(0x143)
-
-/* Transceiver Control Register 1 */
-#define TRX_CTRL_1                      _SFR_MEM8(0x144)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_1 {
-        unsigned int : 4;
-        unsigned int pll_tx_flt : 1;	/* Enable PLL TX Filter */
-        unsigned int tx_auto_crc_on : 1;	/* Enable Automatic CRC Calculation */
-        unsigned int irq_2_ext_en : 1;	/* Connect Frame Start IRQ to TC1 */
-        unsigned int pa_ext_en : 1;	/* External PA support enable */
-};
-
-#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_1 */
-
-#define PLL_TX_FLT                      4
-#define TX_AUTO_CRC_ON                  5
-#define IRQ_2_EXT_EN                    6
-#define PA_EXT_EN                       7
-
-/* Transceiver Transmit Power Control Register */
-#define PHY_TX_PWR                      _SFR_MEM8(0x145)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_TX_PWR {
-        unsigned int tx_pwr : 4;	/* Transmit Power Setting */
-        unsigned int : 4;
-};
-
-#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_TX_PWR */
-
-#define TX_PWR0                         0
-#define TX_PWR1                         1
-#define TX_PWR2                         2
-#define TX_PWR3                         3
-
-/* Receiver Signal Strength Indicator Register */
-#define PHY_RSSI                        _SFR_MEM8(0x146)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_RSSI {
-        unsigned int rssi : 5;	/* Receiver Signal Strength Indicator */
-        unsigned int rnd_value : 2;	/* Random Value */
-        unsigned int rx_crc_valid : 1;	/* Received Frame CRC Status */
-};
-
-#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI)
-
-/* symbolic names */
-
-#define RSSI_MIN                        0
-#define RSSI_MIN_PLUS_3dB               1
-#define RSSI_MAX                        28
-#define CRC_INVALID                     0
-#define CRC_VALID                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_RSSI */
-
-#define RSSI0                           0
-#define RSSI1                           1
-#define RSSI2                           2
-#define RSSI3                           3
-#define RSSI4                           4
-#define RND_VALUE0                      5
-#define RND_VALUE1                      6
-#define RX_CRC_VALID                    7
-
-/* Transceiver Energy Detection Level Register */
-#define PHY_ED_LEVEL                    _SFR_MEM8(0x147)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_ED_LEVEL {
-        unsigned int ed_level : 8;	/* Energy Detection Level */
-};
-
-#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL)
-
-/* symbolic names */
-
-#define ED_MIN                          0
-#define ED_MIN_PLUS_1dB                 1
-#define ED_MAX                          83
-#define ED_RESET                        255
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_ED_LEVEL */
-
-#define ED_LEVEL0                       0
-#define ED_LEVEL1                       1
-#define ED_LEVEL2                       2
-#define ED_LEVEL3                       3
-#define ED_LEVEL4                       4
-#define ED_LEVEL5                       5
-#define ED_LEVEL6                       6
-#define ED_LEVEL7                       7
-
-/* Transceiver Clear Channel Assessment (CCA) Control Register */
-#define PHY_CC_CCA                      _SFR_MEM8(0x148)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_CC_CCA {
-        unsigned int channel : 5;	/* RX/TX Channel Selection */
-        unsigned int cca_mode : 2;	/* Select CCA Measurement Mode */
-        unsigned int cca_request : 1;	/* Manual CCA Measurement Request */
-};
-
-#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA)
-
-/* symbolic names */
-
-#define F_2405MHZ                       11
-#define F_2410MHZ                       12
-#define F_2415MHZ                       13
-#define F_2420MHZ                       14
-#define F_2425MHZ                       15
-#define F_2430MHZ                       16
-#define F_2435MHZ                       17
-#define F_2440MHZ                       18
-#define F_2445MHZ                       19
-#define F_2450MHZ                       20
-#define F_2455MHZ                       21
-#define F_2460MHZ                       22
-#define F_2465MHZ                       23
-#define F_2470MHZ                       24
-#define F_2475MHZ                       25
-#define F_2480MHZ                       26
-#define CCA_CS_OR_ED                    0
-#define CCA_ED                          1
-#define CCA_CS                          2
-#define CCA_CS_AND_ED                   3
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_CC_CCA */
-
-#define CHANNEL0                        0
-#define CHANNEL1                        1
-#define CHANNEL2                        2
-#define CHANNEL3                        3
-#define CHANNEL4                        4
-#define CCA_MODE0                       5
-#define CCA_MODE1                       6
-#define CCA_REQUEST                     7
-
-/* Transceiver CCA Threshold Setting Register */
-#define CCA_THRES                       _SFR_MEM8(0x149)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CCA_THRES {
-        unsigned int cca_ed_thres : 4;	/* ED Threshold Level for CCA Measurement */
-        unsigned int cca_cs_thres : 4;	/* CS Threshold Level for CCA Measurement */
-};
-
-#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CCA_THRES */
-
-#define CCA_ED_THRES0                   0
-#define CCA_ED_THRES1                   1
-#define CCA_ED_THRES2                   2
-#define CCA_ED_THRES3                   3
-#define CCA_CS_THRES0                   4
-#define CCA_CS_THRES1                   5
-#define CCA_CS_THRES2                   6
-#define CCA_CS_THRES3                   7
-
-/* Transceiver Receive Control Register */
-#define RX_CTRL                         _SFR_MEM8(0x14A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_CTRL {
-        unsigned int pdt_thres : 4;	/* Receiver Sensitivity Control */
-        unsigned int : 4;
-};
-
-#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL)
-
-/* symbolic names */
-
-#define PDT_THRES_ANT_DIV_OFF           7
-#define PDT_THRES_ANT_DIV_ON            3
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_CTRL */
-
-#define PDT_THRES0                      0
-#define PDT_THRES1                      1
-#define PDT_THRES2                      2
-#define PDT_THRES3                      3
-
-/* Start of Frame Delimiter Value Register */
-#define SFD_VALUE                       _SFR_MEM8(0x14B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SFD_VALUE {
-        unsigned int sfd_value : 8;	/* Start of Frame Delimiter Value */
-};
-
-#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE)
-
-/* symbolic names */
-
-#define IEEE_SFD                        167
-
-#endif /* __ASSEMBLER__ */
-
-  /* SFD_VALUE */
-
-#define SFD_VALUE0                      0
-#define SFD_VALUE1                      1
-#define SFD_VALUE2                      2
-#define SFD_VALUE3                      3
-#define SFD_VALUE4                      4
-#define SFD_VALUE5                      5
-#define SFD_VALUE6                      6
-#define SFD_VALUE7                      7
-
-/* Transceiver Control Register 2 */
-#define TRX_CTRL_2                      _SFR_MEM8(0x14C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_2 {
-        unsigned int oqpsk_data_rate : 2;	/* Data Rate Selection */
-        unsigned int : 5;
-        unsigned int rx_safe_mode : 1;	/* RX Safe Mode */
-};
-
-#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2)
-
-/* symbolic names */
-
-#define RATE_250KB                      0
-#define RATE_500KB                      1
-#define RATE_1000KB                     2
-#define RATE_2000KB                     3
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_2 */
-
-#define OQPSK_DATA_RATE0                0
-#define OQPSK_DATA_RATE1                1
-#define RX_SAFE_MODE                    7
-
-/* Antenna Diversity Control Register */
-#define ANT_DIV                         _SFR_MEM8(0x14D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ANT_DIV {
-        unsigned int ant_ctrl : 2;	/* Static Antenna Diversity Switch Control */
-        unsigned int ant_ext_sw_en : 1;	/* Enable External Antenna Switch Control */
-        unsigned int ant_div_en : 1;	/* Enable Antenna Diversity */
-        unsigned int : 3;
-        unsigned int ant_sel : 1;	/* Antenna Diversity Antenna Status */
-};
-
-#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV)
-
-/* symbolic names */
-
-#define ANT_1                           1
-#define ANT_0                           2
-#define ANT_RESET                       3
-#define ANT_DIV_EXT_SW_DIS              0
-#define ANT_DIV_EXT_SW_EN               1
-#define ANTENNA_0                       0
-#define ANTENNA_1                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* ANT_DIV */
-
-#define ANT_CTRL0                       0
-#define ANT_CTRL1                       1
-#define ANT_EXT_SW_EN                   2
-#define ANT_DIV_EN                      3
-#define ANT_SEL                         7
-
-/* Transceiver Interrupt Enable Register */
-#define IRQ_MASK                        _SFR_MEM8(0x14E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK {
-        unsigned int pll_lock_en : 1;	/* PLL Lock Interrupt Enable */
-        unsigned int pll_unlock_en : 1;	/* PLL Unlock Interrupt Enable */
-        unsigned int rx_start_en : 1;	/* RX_START Interrupt Enable */
-        unsigned int rx_end_en : 1;	/* RX_END Interrupt Enable */
-        unsigned int cca_ed_done_en : 1;	/* End of ED Measurement Interrupt Enable */
-        unsigned int ami_en : 1;	/* Address Match Interrupt Enable */
-        unsigned int tx_end_en : 1;	/* TX_END Interrupt Enable */
-        unsigned int awake_en : 1;	/* Awake Interrupt Enable */
-};
-
-#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK */
-
-#define PLL_LOCK_EN                     0
-#define PLL_UNLOCK_EN                   1
-#define RX_START_EN                     2
-#define RX_END_EN                       3
-#define CCA_ED_DONE_EN                  4
-#define AMI_EN                          5
-#define TX_END_EN                       6
-#define AWAKE_EN                        7
-
-/* Transceiver Interrupt Status Register */
-#define IRQ_STATUS                      _SFR_MEM8(0x14F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS {
-        unsigned int pll_lock : 1;	/* PLL Lock Interrupt Status */
-        unsigned int pll_unlock : 1;	/* PLL Unlock Interrupt Status */
-        unsigned int rx_start : 1;	/* RX_START Interrupt Status */
-        unsigned int rx_end : 1;	/* RX_END Interrupt Status */
-        unsigned int cca_ed_done : 1;	/* End of ED Measurement Interrupt Status */
-        unsigned int ami : 1;	/* Address Match Interrupt Status */
-        unsigned int tx_end : 1;	/* TX_END Interrupt Status */
-        unsigned int awake : 1;	/* Awake Interrupt Status */
-};
-
-#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS */
-
-#define PLL_LOCK                        0
-#define PLL_UNLOCK                      1
-#define RX_START                        2
-#define RX_END                          3
-#define CCA_ED_DONE                     4
-#define AMI                             5
-#define TX_END                          6
-#define AWAKE                           7
-
-/* Voltage Regulator Control and Status Register */
-#define VREG_CTRL                       _SFR_MEM8(0x150)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VREG_CTRL {
-        unsigned int : 2;
-        unsigned int dvdd_ok : 1;	/* DVDD Supply Voltage Valid */
-        unsigned int dvreg_ext : 1;	/* Use External DVDD Regulator */
-        unsigned int : 2;
-        unsigned int avdd_ok : 1;	/* AVDD Supply Voltage Valid */
-        unsigned int avreg_ext : 1;	/* Use External AVDD Regulator */
-};
-
-#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL)
-
-/* symbolic names */
-
-#define DVDD_INT                        0
-#define DVDD_EXT                        1
-#define AVDD_INT                        0
-#define AVDD_EXT                        1
-
-#endif /* __ASSEMBLER__ */
-
-  /* VREG_CTRL */
-
-#define DVDD_OK                         2
-#define DVREG_EXT                       3
-#define AVDD_OK                         6
-#define AVREG_EXT                       7
-
-/* Battery Monitor Control and Status Register */
-#define BATMON                          _SFR_MEM8(0x151)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BATMON {
-        unsigned int batmon_vth : 4;	/* Battery Monitor Threshold Voltage */
-        unsigned int batmon_hr : 1;	/* Battery Monitor Voltage Range */
-        unsigned int batmon_ok : 1;	/* Battery Monitor Status */
-        unsigned int bat_low_en : 1;	/* Battery Monitor Interrupt Enable */
-        unsigned int bat_low : 1;	/* Battery Monitor Interrupt Status */
-};
-
-#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON)
-
-/* symbolic names */
-
-#define BATMON_HR_DIS                   0
-#define BATMON_HR_EN                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* BATMON */
-
-#define BATMON_VTH0                     0
-#define BATMON_VTH1                     1
-#define BATMON_VTH2                     2
-#define BATMON_VTH3                     3
-#define BATMON_HR                       4
-#define BATMON_OK                       5
-#define BAT_LOW_EN                      6
-#define BAT_LOW                         7
-
-/* Crystal Oscillator Control Register */
-#define XOSC_CTRL                       _SFR_MEM8(0x152)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XOSC_CTRL {
-        unsigned int xtal_trim : 4;	/* Crystal Oscillator Load Capacitance Trimming */
-        unsigned int xtal_mode : 4;	/* Crystal Oscillator Operating Mode */
-};
-
-#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL)
-
-/* symbolic names */
-
-#define XTAL_TRIM_MIN                   0
-#define XTAL_TRIM_MAX                   15
-
-#endif /* __ASSEMBLER__ */
-
-  /* XOSC_CTRL */
-
-#define XTAL_TRIM0                      0
-#define XTAL_TRIM1                      1
-#define XTAL_TRIM2                      2
-#define XTAL_TRIM3                      3
-#define XTAL_MODE0                      4
-#define XTAL_MODE1                      5
-#define XTAL_MODE2                      6
-#define XTAL_MODE3                      7
-
-/* Channel Control Register 0 */
-#define CC_CTRL_0                       _SFR_MEM8(0x153)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_0 {
-        unsigned int cc_number : 8;	/* Channel Number */
-};
-
-#define CC_CTRL_0_struct _SFR_MEM8_STRUCT(0x153, struct __reg_CC_CTRL_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_0 */
-
-#define CC_NUMBER0                      0
-#define CC_NUMBER1                      1
-#define CC_NUMBER2                      2
-#define CC_NUMBER3                      3
-#define CC_NUMBER4                      4
-#define CC_NUMBER5                      5
-#define CC_NUMBER6                      6
-#define CC_NUMBER7                      7
-
-/* Channel Control Register 1 */
-#define CC_CTRL_1                       _SFR_MEM8(0x154)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_1 {
-        unsigned int cc_band : 4;	/* Channel Band */
-        unsigned int : 4;
-};
-
-#define CC_CTRL_1_struct _SFR_MEM8_STRUCT(0x154, struct __reg_CC_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_1 */
-
-#define CC_BAND0                        0
-#define CC_BAND1                        1
-#define CC_BAND2                        2
-#define CC_BAND3                        3
-
-/* Transceiver Receiver Sensitivity Control Register */
-#define RX_SYN                          _SFR_MEM8(0x155)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_SYN {
-        unsigned int rx_pdt_level : 4;	/* Reduce Receiver Sensitivity */
-        unsigned int : 2;
-        unsigned int rx_override : 1;	/* Receiver Override Function */
-        unsigned int rx_pdt_dis : 1;	/* Prevent Frame Reception */
-};
-
-#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN)
-
-/* symbolic names */
-
-#define RX_PDT_LEVEL_MIN                0
-#define RX_PDT_LEVEL_MAX                15
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_SYN */
-
-#define RX_PDT_LEVEL0                   0
-#define RX_PDT_LEVEL1                   1
-#define RX_PDT_LEVEL2                   2
-#define RX_PDT_LEVEL3                   3
-#define RX_OVERRIDE                     6
-#define RX_PDT_DIS                      7
-
-/* Transceiver Reduced Power Consumption Control */
-#define TRX_RPC                         _SFR_MEM8(0x156)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_RPC {
-        unsigned int : 1;
-        unsigned int ipan_rpc_en : 1;	/* Smart Receiving Mode IPAN Handling Enable */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int pll_rpc_en : 1;	/* PLL Smart Receiving Mode Enable */
-        unsigned int pdt_rpc_en : 1;	/* Smart Receiving Mode Reduced Sensitivity Enable */
-        unsigned int rx_rpc_en : 1;	/* Receiver Smart Receiving Mode Enable */
-        unsigned int rx_rpc_ctrl : 2;	/* Smart Receiving Mode Timing */
-};
-
-#define TRX_RPC_struct _SFR_MEM8_STRUCT(0x156, struct __reg_TRX_RPC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_RPC */
-
-#define IPAN_RPC_EN                     1
-#define PLL_RPC_EN                      3
-#define PDT_RPC_EN                      4
-#define RX_RPC_EN                       5
-#define RX_RPC_CTRL0                    6
-#define RX_RPC_CTRL1                    7
-
-/* Transceiver Acknowledgment Frame Control Register 1 */
-#define XAH_CTRL_1                      _SFR_MEM8(0x157)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_1 {
-        unsigned int : 1;
-        unsigned int aack_prom_mode : 1;	/* Enable Promiscuous Mode */
-        unsigned int aack_ack_time : 1;	/* Reduce Acknowledgment Time */
-        unsigned int : 1;
-        unsigned int aack_upld_res_ft : 1;	/* Process Reserved Frames */
-        unsigned int aack_fltr_res_ft : 1;	/* Filter Reserved Frames */
-        unsigned int : 2;
-};
-
-#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1)
-
-/* symbolic names */
-
-#define AACK_ACK_TIME_12_SYM            0
-#define AACK_ACK_TIME_2_SYM             1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_1 */
-
-#define AACK_PROM_MODE                  1
-#define AACK_ACK_TIME                   2
-#define AACK_UPLD_RES_FT                4
-#define AACK_FLTR_RES_FT                5
-
-/* Transceiver Filter Tuning Control Register */
-#define FTN_CTRL                        _SFR_MEM8(0x158)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_FTN_CTRL {
-        unsigned int : 7;
-        unsigned int ftn_start : 1;	/* Start Calibration Loop of Filter Tuning Network */
-};
-
-#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* FTN_CTRL */
-
-#define FTN_START                       7
-
-/* Transceiver Center Frequency Calibration Control Register */
-#define PLL_CF                          _SFR_MEM8(0x15A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_CF {
-        unsigned int : 7;
-        unsigned int pll_cf_start : 1;	/* Start Center Frequency Calibration */
-};
-
-#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_CF */
-
-#define PLL_CF_START                    7
-
-/* Transceiver Delay Cell Calibration Control Register */
-#define PLL_DCU                         _SFR_MEM8(0x15B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_DCU {
-        unsigned int : 7;
-        unsigned int pll_dcu_start : 1;	/* Start Delay Cell Calibration */
-};
-
-#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_DCU */
-
-#define PLL_DCU_START                   7
-
-/* Device Identification Register (Part Number) */
-#define PART_NUM                        _SFR_MEM8(0x15C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PART_NUM {
-        unsigned int part_num : 8;	/* Part Number */
-};
-
-#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM)
-
-/* symbolic names */
-
-#define P_RFR2                          148
-
-#endif /* __ASSEMBLER__ */
-
-  /* PART_NUM */
-
-#define PART_NUM0                       0
-#define PART_NUM1                       1
-#define PART_NUM2                       2
-#define PART_NUM3                       3
-#define PART_NUM4                       4
-#define PART_NUM5                       5
-#define PART_NUM6                       6
-#define PART_NUM7                       7
-
-/* Device Identification Register (Version Number) */
-#define VERSION_NUM                     _SFR_MEM8(0x15D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VERSION_NUM {
-        unsigned int version_num : 8;	/* Version Number */
-};
-
-#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM)
-
-/* symbolic names */
-
-#define REV_A                           12
-#define REV_B                           1
-#define REV_C                           3
-#define REV_D                           4
-
-#endif /* __ASSEMBLER__ */
-
-  /* VERSION_NUM */
-
-#define VERSION_NUM0                    0
-#define VERSION_NUM1                    1
-#define VERSION_NUM2                    2
-#define VERSION_NUM3                    3
-#define VERSION_NUM4                    4
-#define VERSION_NUM5                    5
-#define VERSION_NUM6                    6
-#define VERSION_NUM7                    7
-
-/* Device Identification Register (Manufacture ID Low Byte) */
-#define MAN_ID_0                        _SFR_MEM8(0x15E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_0 {
-        unsigned int man_id_00 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_01 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_02 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_03 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_04 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_05 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_06 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_07 : 1;	/* Manufacturer ID (Low Byte) */
-};
-
-#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_0                    31
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_0 */
-
-#define MAN_ID_00                       0
-#define MAN_ID_01                       1
-#define MAN_ID_02                       2
-#define MAN_ID_03                       3
-#define MAN_ID_04                       4
-#define MAN_ID_05                       5
-#define MAN_ID_06                       6
-#define MAN_ID_07                       7
-
-/* Device Identification Register (Manufacture ID High Byte) */
-#define MAN_ID_1                        _SFR_MEM8(0x15F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_1 {
-        unsigned int man_id_ : 8;	/* Manufacturer ID (High Byte) */
-};
-
-#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_1                    0
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_1 */
-
-#define MAN_ID_10                       0
-#define MAN_ID_11                       1
-#define MAN_ID_12                       2
-#define MAN_ID_13                       3
-#define MAN_ID_14                       4
-#define MAN_ID_15                       5
-#define MAN_ID_16                       6
-#define MAN_ID_17                       7
-
-/* Transceiver MAC Short Address Register (Low Byte) */
-#define SHORT_ADDR_0                    _SFR_MEM8(0x160)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_0 {
-        unsigned int short_addr_00 : 1;	/* MAC Short Address */
-        unsigned int short_addr_01 : 1;	/* MAC Short Address */
-        unsigned int short_addr_02 : 1;	/* MAC Short Address */
-        unsigned int short_addr_03 : 1;	/* MAC Short Address */
-        unsigned int short_addr_04 : 1;	/* MAC Short Address */
-        unsigned int short_addr_05 : 1;	/* MAC Short Address */
-        unsigned int short_addr_06 : 1;	/* MAC Short Address */
-        unsigned int short_addr_07 : 1;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_0 */
-
-#define SHORT_ADDR_00                   0
-#define SHORT_ADDR_01                   1
-#define SHORT_ADDR_02                   2
-#define SHORT_ADDR_03                   3
-#define SHORT_ADDR_04                   4
-#define SHORT_ADDR_05                   5
-#define SHORT_ADDR_06                   6
-#define SHORT_ADDR_07                   7
-
-/* Transceiver MAC Short Address Register (High Byte) */
-#define SHORT_ADDR_1                    _SFR_MEM8(0x161)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_1 {
-        unsigned int short_addr_ : 8;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_1 */
-
-#define SHORT_ADDR_10                   0
-#define SHORT_ADDR_11                   1
-#define SHORT_ADDR_12                   2
-#define SHORT_ADDR_13                   3
-#define SHORT_ADDR_14                   4
-#define SHORT_ADDR_15                   5
-#define SHORT_ADDR_16                   6
-#define SHORT_ADDR_17                   7
-
-/* Transceiver Personal Area Network ID Register (Low Byte) */
-#define PAN_ID_0                        _SFR_MEM8(0x162)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_0 {
-        unsigned int pan_id_00 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_01 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_02 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_03 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_04 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_05 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_06 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_07 : 1;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_0 */
-
-#define PAN_ID_00                       0
-#define PAN_ID_01                       1
-#define PAN_ID_02                       2
-#define PAN_ID_03                       3
-#define PAN_ID_04                       4
-#define PAN_ID_05                       5
-#define PAN_ID_06                       6
-#define PAN_ID_07                       7
-
-/* Transceiver Personal Area Network ID Register (High Byte) */
-#define PAN_ID_1                        _SFR_MEM8(0x163)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_1 {
-        unsigned int pan_id_ : 8;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_1 */
-
-#define PAN_ID_10                       0
-#define PAN_ID_11                       1
-#define PAN_ID_12                       2
-#define PAN_ID_13                       3
-#define PAN_ID_14                       4
-#define PAN_ID_15                       5
-#define PAN_ID_16                       6
-#define PAN_ID_17                       7
-
-/* Transceiver MAC IEEE Address Register 0 */
-#define IEEE_ADDR_0                     _SFR_MEM8(0x164)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_0 {
-        unsigned int ieee_addr_00 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_01 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_02 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_03 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_04 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_05 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_06 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_07 : 1;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_0 */
-
-#define IEEE_ADDR_00                    0
-#define IEEE_ADDR_01                    1
-#define IEEE_ADDR_02                    2
-#define IEEE_ADDR_03                    3
-#define IEEE_ADDR_04                    4
-#define IEEE_ADDR_05                    5
-#define IEEE_ADDR_06                    6
-#define IEEE_ADDR_07                    7
-
-/* Transceiver MAC IEEE Address Register 1 */
-#define IEEE_ADDR_1                     _SFR_MEM8(0x165)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_1 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_1 */
-
-#define IEEE_ADDR_10                    0
-#define IEEE_ADDR_11                    1
-#define IEEE_ADDR_12                    2
-#define IEEE_ADDR_13                    3
-#define IEEE_ADDR_14                    4
-#define IEEE_ADDR_15                    5
-#define IEEE_ADDR_16                    6
-#define IEEE_ADDR_17                    7
-
-/* Transceiver MAC IEEE Address Register 2 */
-#define IEEE_ADDR_2                     _SFR_MEM8(0x166)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_2 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_2 */
-
-#define IEEE_ADDR_20                    0
-#define IEEE_ADDR_21                    1
-#define IEEE_ADDR_22                    2
-#define IEEE_ADDR_23                    3
-#define IEEE_ADDR_24                    4
-#define IEEE_ADDR_25                    5
-#define IEEE_ADDR_26                    6
-#define IEEE_ADDR_27                    7
-
-/* Transceiver MAC IEEE Address Register 3 */
-#define IEEE_ADDR_3                     _SFR_MEM8(0x167)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_3 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_3 */
-
-#define IEEE_ADDR_30                    0
-#define IEEE_ADDR_31                    1
-#define IEEE_ADDR_32                    2
-#define IEEE_ADDR_33                    3
-#define IEEE_ADDR_34                    4
-#define IEEE_ADDR_35                    5
-#define IEEE_ADDR_36                    6
-#define IEEE_ADDR_37                    7
-
-/* Transceiver MAC IEEE Address Register 4 */
-#define IEEE_ADDR_4                     _SFR_MEM8(0x168)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_4 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_4 */
-
-#define IEEE_ADDR_40                    0
-#define IEEE_ADDR_41                    1
-#define IEEE_ADDR_42                    2
-#define IEEE_ADDR_43                    3
-#define IEEE_ADDR_44                    4
-#define IEEE_ADDR_45                    5
-#define IEEE_ADDR_46                    6
-#define IEEE_ADDR_47                    7
-
-/* Transceiver MAC IEEE Address Register 5 */
-#define IEEE_ADDR_5                     _SFR_MEM8(0x169)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_5 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_5 */
-
-#define IEEE_ADDR_50                    0
-#define IEEE_ADDR_51                    1
-#define IEEE_ADDR_52                    2
-#define IEEE_ADDR_53                    3
-#define IEEE_ADDR_54                    4
-#define IEEE_ADDR_55                    5
-#define IEEE_ADDR_56                    6
-#define IEEE_ADDR_57                    7
-
-/* Transceiver MAC IEEE Address Register 6 */
-#define IEEE_ADDR_6                     _SFR_MEM8(0x16A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_6 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_6 */
-
-#define IEEE_ADDR_60                    0
-#define IEEE_ADDR_61                    1
-#define IEEE_ADDR_62                    2
-#define IEEE_ADDR_63                    3
-#define IEEE_ADDR_64                    4
-#define IEEE_ADDR_65                    5
-#define IEEE_ADDR_66                    6
-#define IEEE_ADDR_67                    7
-
-/* Transceiver MAC IEEE Address Register 7 */
-#define IEEE_ADDR_7                     _SFR_MEM8(0x16B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_7 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_7 */
-
-#define IEEE_ADDR_70                    0
-#define IEEE_ADDR_71                    1
-#define IEEE_ADDR_72                    2
-#define IEEE_ADDR_73                    3
-#define IEEE_ADDR_74                    4
-#define IEEE_ADDR_75                    5
-#define IEEE_ADDR_76                    6
-#define IEEE_ADDR_77                    7
-
-/* Transceiver Extended Operating Mode Control Register */
-#define XAH_CTRL_0                      _SFR_MEM8(0x16C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_0 {
-        unsigned int slotted_operation : 1;	/* Set Slotted Acknowledgment */
-        unsigned int max_csma_retries : 3;	/* Maximum Number of CSMA-CA Procedure Repetition Attempts */
-        unsigned int max_frame_retries : 4;	/* Maximum Number of Frame Re-transmission Attempts */
-};
-
-#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0)
-
-/* symbolic names */
-
-#define SLOTTED_OP_DIS                  0
-#define SLOTTED_OP_EN                   1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_0 */
-
-#define SLOTTED_OPERATION               0
-#define MAX_CSMA_RETRIES0               1
-#define MAX_CSMA_RETRIES1               2
-#define MAX_CSMA_RETRIES2               3
-#define MAX_FRAME_RETRIES0              4
-#define MAX_FRAME_RETRIES1              5
-#define MAX_FRAME_RETRIES2              6
-#define MAX_FRAME_RETRIES3              7
-
-/* Transceiver CSMA-CA Random Number Generator Seed Register */
-#define CSMA_SEED_0                     _SFR_MEM8(0x16D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_0 {
-        unsigned int csma_seed_00 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_01 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_02 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_03 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_04 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_05 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_06 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_07 : 1;	/* Seed Value for CSMA Random Number Generator */
-};
-
-#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_0 */
-
-#define CSMA_SEED_00                    0
-#define CSMA_SEED_01                    1
-#define CSMA_SEED_02                    2
-#define CSMA_SEED_03                    3
-#define CSMA_SEED_04                    4
-#define CSMA_SEED_05                    5
-#define CSMA_SEED_06                    6
-#define CSMA_SEED_07                    7
-
-/* Transceiver Acknowledgment Frame Control Register 2 */
-#define CSMA_SEED_1                     _SFR_MEM8(0x16E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_1 {
-        unsigned int csma_seed_1 : 3;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int aack_i_am_coord : 1;	/* Set Personal Area Network Coordinator */
-        unsigned int aack_dis_ack : 1;	/* Disable Acknowledgment Frame Transmission */
-        unsigned int aack_set_pd : 1;	/* Set Frame Pending Sub-field */
-        unsigned int aack_fvn_mode : 2;	/* Acknowledgment Frame Filter Mode */
-};
-
-#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_1 */
-
-#define CSMA_SEED_10                    0
-#define CSMA_SEED_11                    1
-#define CSMA_SEED_12                    2
-#define AACK_I_AM_COORD                 3
-#define AACK_DIS_ACK                    4
-#define AACK_SET_PD                     5
-#define AACK_FVN_MODE0                  6
-#define AACK_FVN_MODE1                  7
-
-/* Transceiver CSMA-CA Back-off Exponent Control Register */
-#define CSMA_BE                         _SFR_MEM8(0x16F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_BE {
-        unsigned int min_be : 4;	/* Minimum Back-off Exponent */
-        unsigned int max_be : 4;	/* Maximum Back-off Exponent */
-};
-
-#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_BE */
-
-#define MIN_BE0                         0
-#define MIN_BE1                         1
-#define MIN_BE2                         2
-#define MIN_BE3                         3
-#define MAX_BE0                         4
-#define MAX_BE1                         5
-#define MAX_BE2                         6
-#define MAX_BE3                         7
-
-/* Transceiver Digital Test Control Register */
-#define TST_CTRL_DIGI                   _SFR_MEM8(0x176)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_CTRL_DIGI {
-        unsigned int tst_ctrl_dig : 4;	/* Digital Test Controller Register */
-        unsigned int : 4;
-};
-
-#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_CTRL_DIGI */
-
-#define TST_CTRL_DIG0                   0
-#define TST_CTRL_DIG1                   1
-#define TST_CTRL_DIG2                   2
-#define TST_CTRL_DIG3                   3
-
-/* Transceiver Received Frame Length Register */
-#define TST_RX_LENGTH                   _SFR_MEM8(0x17B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_RX_LENGTH {
-        unsigned int rx_length : 8;	/* Received Frame Length */
-};
-
-#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH)
-
-#endif /* __ASSEMBLER__ */
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
 
-  /* TST_RX_LENGTH */
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
 
-#define RX_LENGTH0                      0
-#define RX_LENGTH1                      1
-#define RX_LENGTH2                      2
-#define RX_LENGTH3                      3
-#define RX_LENGTH4                      4
-#define RX_LENGTH5                      5
-#define RX_LENGTH6                      6
-#define RX_LENGTH7                      7
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define MUX5    3
+#define ACCH    4
+#define REFOK   5
+#define AVDDOK  7
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC8D   0
+#define ADC9D   1
+#define ADC10D  2
+#define ADC11D  3
+#define ADC12D  4
+#define ADC13D  5
+#define ADC14D  6
+#define ADC15D  7
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1C0  2
+#define COM1C1  3
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1C   5
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define WGM30   0
+#define WGM31   1
+#define COM3C0  2
+#define COM3C1  3
+#define COM3B0  4
+#define COM3B1  5
+#define COM3A0  6
+#define COM3A1  7
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define CS30    0
+#define CS31    1
+#define CS32    2
+#define WGM32   3
+#define WGM33   4
+#define ICES3   6
+#define ICNC3   7
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3C   5
+#define FOC3B   6
+#define FOC3A   7
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define WGM40   0
+#define WGM41   1
+#define COM4C0  2
+#define COM4C1  3
+#define COM4B0  4
+#define COM4B1  5
+#define COM4A0  6
+#define COM4A1  7
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define CS40    0
+#define CS41    1
+#define CS42    2
+#define WGM42   3
+#define WGM43   4
+#define ICES4   6
+#define ICNC4   7
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4C   5
+#define FOC4B   6
+#define FOC4A   7
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+#define EXCLKAMR 7
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+#define IRQ_MASK1 _SFR_MEM8(0xBE)
+#define TX_START_EN 0
+#define MAF_0_AMI_EN 1
+#define MAF_1_AMI_EN 2
+#define MAF_2_AMI_EN 3
+#define MAF_3_AMI_EN 4
+
+#define IRQ_STATUS1 _SFR_MEM8(0xBF)
+#define TX_START 0
+#define MAF_0_AMI 1
+#define MAF_1_AMI 2
+#define MAF_2_AMI 3
+#define MAF_3_AMI 4
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+#define UCPHA0  1
+#define UDORD0  2
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+#define UCSR1B  _SFR_MEM8(0xC9)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+#define UCPHA1  1
+#define UDORD1  2
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0xCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define SCRSTRLL _SFR_MEM8(0xD7)
+#define SCRSTRLL0 0
+#define SCRSTRLL1 1
+#define SCRSTRLL2 2
+#define SCRSTRLL3 3
+#define SCRSTRLL4 4
+#define SCRSTRLL5 5
+#define SCRSTRLL6 6
+#define SCRSTRLL7 7
+
+#define SCRSTRLH _SFR_MEM8(0xD8)
+#define SCRSTRLH0 0
+#define SCRSTRLH1 1
+#define SCRSTRLH2 2
+#define SCRSTRLH3 3
+#define SCRSTRLH4 4
+#define SCRSTRLH5 5
+#define SCRSTRLH6 6
+#define SCRSTRLH7 7
+
+#define SCRSTRHL _SFR_MEM8(0xD9)
+#define SCRSTRHL0 0
+#define SCRSTRHL1 1
+#define SCRSTRHL2 2
+#define SCRSTRHL3 3
+#define SCRSTRHL4 4
+#define SCRSTRHL5 5
+#define SCRSTRHL6 6
+#define SCRSTRHL7 7
+
+#define SCRSTRHH _SFR_MEM8(0xDA)
+#define SCRSTRHH0 0
+#define SCRSTRHH1 1
+#define SCRSTRHH2 2
+#define SCRSTRHH3 3
+#define SCRSTRHH4 4
+#define SCRSTRHH5 5
+#define SCRSTRHH6 6
+#define SCRSTRHH7 7
+
+#define SCCSR   _SFR_MEM8(0xDB)
+#define SCCS10  0
+#define SCCS11  1
+#define SCCS20  2
+#define SCCS21  3
+#define SCCS30  4
+#define SCCS31  5
+
+#define SCCR0   _SFR_MEM8(0xDC)
+#define SCCMP1  0
+#define SCCMP2  1
+#define SCCMP3  2
+#define SCTSE   3
+#define SCCKSEL 4
+#define SCEN    5
+#define SCMBTS  6
+#define SCRES   7
+
+#define SCCR1   _SFR_MEM8(0xDD)
+#define SCENBO  0
+#define SCEECLK 1
+#define SCCKDIV0 2
+#define SCCKDIV1 3
+#define SCCKDIV2 4
+#define SCBTSM  5
+#define Res5    6
+#define Res6    7
+
+#define SCSR    _SFR_MEM8(0xDE)
+#define SCBSY   0
+
+#define SCIRQM  _SFR_MEM8(0xDF)
+#define IRQMCP1 0
+#define IRQMCP2 1
+#define IRQMCP3 2
+#define IRQMOF  3
+#define IRQMBO  4
+
+#define SCIRQS  _SFR_MEM8(0xE0)
+#define IRQSCP1 0
+#define IRQSCP2 1
+#define IRQSCP3 2
+#define IRQSOF  3
+#define IRQSBO  4
+
+#define SCCNTLL _SFR_MEM8(0xE1)
+#define SCCNTLL0 0
+#define SCCNTLL1 1
+#define SCCNTLL2 2
+#define SCCNTLL3 3
+#define SCCNTLL4 4
+#define SCCNTLL5 5
+#define SCCNTLL6 6
+#define SCCNTLL7 7
+
+#define SCCNTLH _SFR_MEM8(0xE2)
+#define SCCNTLH0 0
+#define SCCNTLH1 1
+#define SCCNTLH2 2
+#define SCCNTLH3 3
+#define SCCNTLH4 4
+#define SCCNTLH5 5
+#define SCCNTLH6 6
+#define SCCNTLH7 7
+
+#define SCCNTHL _SFR_MEM8(0xE3)
+#define SCCNTHL0 0
+#define SCCNTHL1 1
+#define SCCNTHL2 2
+#define SCCNTHL3 3
+#define SCCNTHL4 4
+#define SCCNTHL5 5
+#define SCCNTHL6 6
+#define SCCNTHL7 7
+
+#define SCCNTHH _SFR_MEM8(0xE4)
+#define SCCNTHH0 0
+#define SCCNTHH1 1
+#define SCCNTHH2 2
+#define SCCNTHH3 3
+#define SCCNTHH4 4
+#define SCCNTHH5 5
+#define SCCNTHH6 6
+#define SCCNTHH7 7
+
+#define SCBTSRLL _SFR_MEM8(0xE5)
+#define SCBTSRLL0 0
+#define SCBTSRLL1 1
+#define SCBTSRLL2 2
+#define SCBTSRLL3 3
+#define SCBTSRLL4 4
+#define SCBTSRLL5 5
+#define SCBTSRLL6 6
+#define SCBTSRLL7 7
+
+#define SCBTSRLH _SFR_MEM8(0xE6)
+#define SCBTSRLH0 0
+#define SCBTSRLH1 1
+#define SCBTSRLH2 2
+#define SCBTSRLH3 3
+#define SCBTSRLH4 4
+#define SCBTSRLH5 5
+#define SCBTSRLH6 6
+#define SCBTSRLH7 7
+
+#define SCBTSRHL _SFR_MEM8(0xE7)
+#define SCBTSRHL0 0
+#define SCBTSRHL1 1
+#define SCBTSRHL2 2
+#define SCBTSRHL3 3
+#define SCBTSRHL4 4
+#define SCBTSRHL5 5
+#define SCBTSRHL6 6
+#define SCBTSRHL7 7
+
+#define SCBTSRHH _SFR_MEM8(0xE8)
+#define SCBTSRHH0 0
+#define SCBTSRHH1 1
+#define SCBTSRHH2 2
+#define SCBTSRHH3 3
+#define SCBTSRHH4 4
+#define SCBTSRHH5 5
+#define SCBTSRHH6 6
+#define SCBTSRHH7 7
+
+#define SCTSRLL _SFR_MEM8(0xE9)
+#define SCTSRLL0 0
+#define SCTSRLL1 1
+#define SCTSRLL2 2
+#define SCTSRLL3 3
+#define SCTSRLL4 4
+#define SCTSRLL5 5
+#define SCTSRLL6 6
+#define SCTSRLL7 7
+
+#define SCTSRLH _SFR_MEM8(0xEA)
+#define SCTSRLH0 0
+#define SCTSRLH1 1
+#define SCTSRLH2 2
+#define SCTSRLH3 3
+#define SCTSRLH4 4
+#define SCTSRLH5 5
+#define SCTSRLH6 6
+#define SCTSRLH7 7
+
+#define SCTSRHL _SFR_MEM8(0xEB)
+#define SCTSRHL0 0
+#define SCTSRHL1 1
+#define SCTSRHL2 2
+#define SCTSRHL3 3
+#define SCTSRHL4 4
+#define SCTSRHL5 5
+#define SCTSRHL6 6
+#define SCTSRHL7 7
+
+#define SCTSRHH _SFR_MEM8(0xEC)
+#define SCTSRHH0 0
+#define SCTSRHH1 1
+#define SCTSRHH2 2
+#define SCTSRHH3 3
+#define SCTSRHH4 4
+#define SCTSRHH5 5
+#define SCTSRHH6 6
+#define SCTSRHH7 7
+
+#define SCOCR3LL _SFR_MEM8(0xED)
+#define SCOCR3LL0 0
+#define SCOCR3LL1 1
+#define SCOCR3LL2 2
+#define SCOCR3LL3 3
+#define SCOCR3LL4 4
+#define SCOCR3LL5 5
+#define SCOCR3LL6 6
+#define SCOCR3LL7 7
+
+#define SCOCR3LH _SFR_MEM8(0xEE)
+#define SCOCR3LH0 0
+#define SCOCR3LH1 1
+#define SCOCR3LH2 2
+#define SCOCR3LH3 3
+#define SCOCR3LH4 4
+#define SCOCR3LH5 5
+#define SCOCR3LH6 6
+#define SCOCR3LH7 7
+
+#define SCOCR3HL _SFR_MEM8(0xEF)
+#define SCOCR3HL0 0
+#define SCOCR3HL1 1
+#define SCOCR3HL2 2
+#define SCOCR3HL3 3
+#define SCOCR3HL4 4
+#define SCOCR3HL5 5
+#define SCOCR3HL6 6
+#define SCOCR3HL7 7
+
+#define SCOCR3HH _SFR_MEM8(0xF0)
+#define SCOCR3HH0 0
+#define SCOCR3HH1 1
+#define SCOCR3HH2 2
+#define SCOCR3HH3 3
+#define SCOCR3HH4 4
+#define SCOCR3HH5 5
+#define SCOCR3HH6 6
+#define SCOCR3HH7 7
+
+#define SCOCR2LL _SFR_MEM8(0xF1)
+#define SCOCR2LL0 0
+#define SCOCR2LL1 1
+#define SCOCR2LL2 2
+#define SCOCR2LL3 3
+#define SCOCR2LL4 4
+#define SCOCR2LL5 5
+#define SCOCR2LL6 6
+#define SCOCR2LL7 7
+
+#define SCOCR2LH _SFR_MEM8(0xF2)
+#define SCOCR2LH0 0
+#define SCOCR2LH1 1
+#define SCOCR2LH2 2
+#define SCOCR2LH3 3
+#define SCOCR2LH4 4
+#define SCOCR2LH5 5
+#define SCOCR2LH6 6
+#define SCOCR2LH7 7
+
+#define SCOCR2HL _SFR_MEM8(0xF3)
+#define SCOCR2HL0 0
+#define SCOCR2HL1 1
+#define SCOCR2HL2 2
+#define SCOCR2HL3 3
+#define SCOCR2HL4 4
+#define SCOCR2HL5 5
+#define SCOCR2HL6 6
+#define SCOCR2HL7 7
+
+#define SCOCR2HH _SFR_MEM8(0xF4)
+#define SCOCR2HH0 0
+#define SCOCR2HH1 1
+#define SCOCR2HH2 2
+#define SCOCR2HH3 3
+#define SCOCR2HH4 4
+#define SCOCR2HH5 5
+#define SCOCR2HH6 6
+#define SCOCR2HH7 7
+
+#define SCOCR1LL _SFR_MEM8(0xF5)
+#define SCOCR1LL0 0
+#define SCOCR1LL1 1
+#define SCOCR1LL2 2
+#define SCOCR1LL3 3
+#define SCOCR1LL4 4
+#define SCOCR1LL5 5
+#define SCOCR1LL6 6
+#define SCOCR1LL7 7
+
+#define SCOCR1LH _SFR_MEM8(0xF6)
+#define SCOCR1LH0 0
+#define SCOCR1LH1 1
+#define SCOCR1LH2 2
+#define SCOCR1LH3 3
+#define SCOCR1LH4 4
+#define SCOCR1LH5 5
+#define SCOCR1LH6 6
+#define SCOCR1LH7 7
+
+#define SCOCR1HL _SFR_MEM8(0xF7)
+#define SCOCR1HL0 0
+#define SCOCR1HL1 1
+#define SCOCR1HL2 2
+#define SCOCR1HL3 3
+#define SCOCR1HL4 4
+#define SCOCR1HL5 5
+#define SCOCR1HL6 6
+#define SCOCR1HL7 7
+
+#define SCOCR1HH _SFR_MEM8(0xF8)
+#define SCOCR1HH0 0
+#define SCOCR1HH1 1
+#define SCOCR1HH2 2
+#define SCOCR1HH3 3
+#define SCOCR1HH4 4
+#define SCOCR1HH5 5
+#define SCOCR1HH6 6
+#define SCOCR1HH7 7
+
+#define SCTSTRLL _SFR_MEM8(0xF9)
+#define SCTSTRLL0 0
+#define SCTSTRLL1 1
+#define SCTSTRLL2 2
+#define SCTSTRLL3 3
+#define SCTSTRLL4 4
+#define SCTSTRLL5 5
+#define SCTSTRLL6 6
+#define SCTSTRLL7 7
+
+#define SCTSTRLH _SFR_MEM8(0xFA)
+#define SCTSTRLH0 0
+#define SCTSTRLH1 1
+#define SCTSTRLH2 2
+#define SCTSTRLH3 3
+#define SCTSTRLH4 4
+#define SCTSTRLH5 5
+#define SCTSTRLH6 6
+#define SCTSTRLH7 7
+
+#define SCTSTRHL _SFR_MEM8(0xFB)
+#define SCTSTRHL0 0
+#define SCTSTRHL1 1
+#define SCTSTRHL2 2
+#define SCTSTRHL3 3
+#define SCTSTRHL4 4
+#define SCTSTRHL5 5
+#define SCTSTRHL6 6
+#define SCTSTRHL7 7
+
+#define SCTSTRHH _SFR_MEM8(0xFC)
+#define SCTSTRHH0 0
+#define SCTSTRHH1 1
+#define SCTSTRHH2 2
+#define SCTSTRHH3 3
+#define SCTSTRHH4 4
+#define SCTSTRHH5 5
+#define SCTSTRHH6 6
+#define SCTSTRHH7 7
+
+/* Reserved [0xFD..0x10B] */
+
+#define MAFCR0  _SFR_MEM8(0x10C)
+#define MAF0EN  0
+#define MAF1EN  1
+#define MAF2EN  2
+#define MAF3EN  3
+
+#define MAFCR1  _SFR_MEM8(0x10D)
+#define AACK_0_I_AM_COORD 0
+#define AACK_0_SET_PD 1
+#define AACK_1_I_AM_COORD 2
+#define AACK_1_SET_PD 3
+#define AACK_2_I_AM_COORD 4
+#define AACK_2_SET_PD 5
+#define AACK_3_I_AM_COORD 6
+#define AACK_3_SET_PD 7
+
+#define MAFSA0L _SFR_MEM8(0x10E)
+#define MAFSA0L0 0
+#define MAFSA0L1 1
+#define MAFSA0L2 2
+#define MAFSA0L3 3
+#define MAFSA0L4 4
+#define MAFSA0L5 5
+#define MAFSA0L6 6
+#define MAFSA0L7 7
+
+#define MAFSA0H _SFR_MEM8(0x10F)
+#define MAFSA0H0 0
+#define MAFSA0H1 1
+#define MAFSA0H2 2
+#define MAFSA0H3 3
+#define MAFSA0H4 4
+#define MAFSA0H5 5
+#define MAFSA0H6 6
+#define MAFSA0H7 7
+
+#define MAFPA0L _SFR_MEM8(0x110)
+#define MAFPA0L0 0
+#define MAFPA0L1 1
+#define MAFPA0L2 2
+#define MAFPA0L3 3
+#define MAFPA0L4 4
+#define MAFPA0L5 5
+#define MAFPA0L6 6
+#define MAFPA0L7 7
+
+#define MAFPA0H _SFR_MEM8(0x111)
+#define MAFPA0H0 0
+#define MAFPA0H1 1
+#define MAFPA0H2 2
+#define MAFPA0H3 3
+#define MAFPA0H4 4
+#define MAFPA0H5 5
+#define MAFPA0H6 6
+#define MAFPA0H7 7
+
+#define MAFSA1L _SFR_MEM8(0x112)
+#define MAFSA1L0 0
+#define MAFSA1L1 1
+#define MAFSA1L2 2
+#define MAFSA1L3 3
+#define MAFSA1L4 4
+#define MAFSA1L5 5
+#define MAFSA1L6 6
+#define MAFSA1L7 7
+
+#define MAFSA1H _SFR_MEM8(0x113)
+#define MAFSA1H0 0
+#define MAFSA1H1 1
+#define MAFSA1H2 2
+#define MAFSA1H3 3
+#define MAFSA1H4 4
+#define MAFSA1H5 5
+#define MAFSA1H6 6
+#define MAFSA1H7 7
+
+#define MAFPA1L _SFR_MEM8(0x114)
+#define MAFPA1L0 0
+#define MAFPA1L1 1
+#define MAFPA1L2 2
+#define MAFPA1L3 3
+#define MAFPA1L4 4
+#define MAFPA1L5 5
+#define MAFPA1L6 6
+#define MAFPA1L7 7
+
+#define MAFPA1H _SFR_MEM8(0x115)
+#define MAFPA1H0 0
+#define MAFPA1H1 1
+#define MAFPA1H2 2
+#define MAFPA1H3 3
+#define MAFPA1H4 4
+#define MAFPA1H5 5
+#define MAFPA1H6 6
+#define MAFPA1H7 7
+
+#define MAFSA2L _SFR_MEM8(0x116)
+#define MAFSA2L0 0
+#define MAFSA2L1 1
+#define MAFSA2L2 2
+#define MAFSA2L3 3
+#define MAFSA2L4 4
+#define MAFSA2L5 5
+#define MAFSA2L6 6
+#define MAFSA2L7 7
+
+#define MAFSA2H _SFR_MEM8(0x117)
+#define MAFSA2H0 0
+#define MAFSA2H1 1
+#define MAFSA2H2 2
+#define MAFSA2H3 3
+#define MAFSA2H4 4
+#define MAFSA2H5 5
+#define MAFSA2H6 6
+#define MAFSA2H7 7
+
+#define MAFPA2L _SFR_MEM8(0x118)
+#define MAFPA2L0 0
+#define MAFPA2L1 1
+#define MAFPA2L2 2
+#define MAFPA2L3 3
+#define MAFPA2L4 4
+#define MAFPA2L5 5
+#define MAFPA2L6 6
+#define MAFPA2L7 7
+
+#define MAFPA2H _SFR_MEM8(0x119)
+#define MAFPA2H0 0
+#define MAFPA2H1 1
+#define MAFPA2H2 2
+#define MAFPA2H3 3
+#define MAFPA2H4 4
+#define MAFPA2H5 5
+#define MAFPA2H6 6
+#define MAFPA2H7 7
+
+#define MAFSA3L _SFR_MEM8(0x11A)
+#define MAFSA3L0 0
+#define MAFSA3L1 1
+#define MAFSA3L2 2
+#define MAFSA3L3 3
+#define MAFSA3L4 4
+#define MAFSA3L5 5
+#define MAFSA3L6 6
+#define MAFSA3L7 7
+
+#define MAFSA3H _SFR_MEM8(0x11B)
+#define MAFSA3H0 0
+#define MAFSA3H1 1
+#define MAFSA3H2 2
+#define MAFSA3H3 3
+#define MAFSA3H4 4
+#define MAFSA3H5 5
+#define MAFSA3H6 6
+#define MAFSA3H7 7
+
+#define MAFPA3L _SFR_MEM8(0x11C)
+#define MAFPA3L0 0
+#define MAFPA3L1 1
+#define MAFPA3L2 2
+#define MAFPA3L3 3
+#define MAFPA3L4 4
+#define MAFPA3L5 5
+#define MAFPA3L6 6
+#define MAFPA3L7 7
+
+#define MAFPA3H _SFR_MEM8(0x11D)
+#define MAFPA3H0 0
+#define MAFPA3H1 1
+#define MAFPA3H2 2
+#define MAFPA3H3 3
+#define MAFPA3H4 4
+#define MAFPA3H5 5
+#define MAFPA3H6 6
+#define MAFPA3H7 7
+
+/* Reserved [0x11E..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define WGM50   0
+#define WGM51   1
+#define COM5C0  2
+#define COM5C1  3
+#define COM5B0  4
+#define COM5B1  5
+#define COM5A0  6
+#define COM5A1  7
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define CS50    0
+#define CS51    1
+#define CS52    2
+#define WGM52   3
+#define WGM53   4
+#define ICES5   6
+#define ICNC5   7
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5C   5
+#define FOC5B   6
+#define FOC5A   7
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E] */
+
+#define LLCR    _SFR_MEM8(0x12F)
+#define LLENCAL 0
+#define LLSHORT 1
+#define LLTCO   2
+#define LLCAL   3
+#define LLCOMP  4
+#define LLDONE  5
+
+#define LLDRL   _SFR_MEM8(0x130)
+#define LLDRL0  0
+#define LLDRL1  1
+#define LLDRL2  2
+#define LLDRL3  3
+
+#define LLDRH   _SFR_MEM8(0x131)
+#define LLDRH0  0
+#define LLDRH1  1
+#define LLDRH2  2
+#define LLDRH3  3
+#define LLDRH4  4
+
+#define DRTRAM3 _SFR_MEM8(0x132)
+#define ENDRT   4
+#define DRTSWOK 5
+
+#define DRTRAM2 _SFR_MEM8(0x133)
+
+#define DRTRAM1 _SFR_MEM8(0x134)
+
+#define DRTRAM0 _SFR_MEM8(0x135)
+
+#define DPDS0   _SFR_MEM8(0x136)
+#define PBDRV0  0
+#define PBDRV1  1
+#define PDDRV0  2
+#define PDDRV1  3
+#define PEDRV0  4
+#define PEDRV1  5
+#define PFDRV0  6
+#define PFDRV1  7
+
+#define DPDS1   _SFR_MEM8(0x137)
+#define PGDRV0  0
+#define PGDRV1  1
+
+#define PARCR   _SFR_MEM8(0x138)
+#define PARUFI  0
+#define PARDFI  1
+#define PALTU0  2
+#define PALTU1  3
+#define PALTU2  4
+#define PALTD0  5
+#define PALTD1  6
+#define PALTD2  7
+
+#define TRXPR   _SFR_MEM8(0x139)
+#define TRXRST  0
+#define SLPTR   1
+
+/* Reserved [0x13A..0x13B] */
+
+#define AES_CTRL _SFR_MEM8(0x13C)
+#define AES_IM  2
+#define AES_DIR 3
+#define AES_MODE 5
+#define AES_REQUEST 7
+
+#define AES_STATUS _SFR_MEM8(0x13D)
+#define AES_DONE 0
+#define AES_ER  7
+
+#define AES_STATE _SFR_MEM8(0x13E)
+#define AES_STATE0 0
+#define AES_STATE1 1
+#define AES_STATE2 2
+#define AES_STATE3 3
+#define AES_STATE4 4
+#define AES_STATE5 5
+#define AES_STATE6 6
+#define AES_STATE7 7
+
+#define AES_KEY _SFR_MEM8(0x13F)
+#define AES_KEY0 0
+#define AES_KEY1 1
+#define AES_KEY2 2
+#define AES_KEY3 3
+#define AES_KEY4 4
+#define AES_KEY5 5
+#define AES_KEY6 6
+#define AES_KEY7 7
+
+/* Reserved [0x140] */
+
+#define TRX_STATUS _SFR_MEM8(0x141)
+#define TRX_STATUS0 0
+#define TRX_STATUS1 1
+#define TRX_STATUS2 2
+#define TRX_STATUS3 3
+#define TRX_STATUS4 4
+#define TST_STATUS 5
+#define CCA_STATUS 6
+#define CCA_DONE 7
+
+#define TRX_STATE _SFR_MEM8(0x142)
+#define TRX_CMD0 0
+#define TRX_CMD1 1
+#define TRX_CMD2 2
+#define TRX_CMD3 3
+#define TRX_CMD4 4
+#define TRAC_STATUS0 5
+#define TRAC_STATUS1 6
+#define TRAC_STATUS2 7
+
+#define TRX_CTRL_0 _SFR_MEM8(0x143)
+#define PMU_IF_INV 4
+#define PMU_START 5
+#define PMU_EN  6
+#define Res7    7
+
+#define TRX_CTRL_1 _SFR_MEM8(0x144)
+#define PLL_TX_FLT 4
+#define TX_AUTO_CRC_ON 5
+#define IRQ_2_EXT_EN 6
+#define PA_EXT_EN 7
+
+#define PHY_TX_PWR _SFR_MEM8(0x145)
+#define TX_PWR0 0
+#define TX_PWR1 1
+#define TX_PWR2 2
+#define TX_PWR3 3
+
+#define PHY_RSSI _SFR_MEM8(0x146)
+#define RSSI0   0
+#define RSSI1   1
+#define RSSI2   2
+#define RSSI3   3
+#define RSSI4   4
+#define RND_VALUE0 5
+#define RND_VALUE1 6
+#define RX_CRC_VALID 7
+
+#define PHY_ED_LEVEL _SFR_MEM8(0x147)
+#define ED_LEVEL0 0
+#define ED_LEVEL1 1
+#define ED_LEVEL2 2
+#define ED_LEVEL3 3
+#define ED_LEVEL4 4
+#define ED_LEVEL5 5
+#define ED_LEVEL6 6
+#define ED_LEVEL7 7
+
+#define PHY_CC_CCA _SFR_MEM8(0x148)
+#define CHANNEL0 0
+#define CHANNEL1 1
+#define CHANNEL2 2
+#define CHANNEL3 3
+#define CHANNEL4 4
+#define CCA_MODE0 5
+#define CCA_MODE1 6
+#define CCA_REQUEST 7
+
+#define CCA_THRES _SFR_MEM8(0x149)
+#define CCA_ED_THRES0 0
+#define CCA_ED_THRES1 1
+#define CCA_ED_THRES2 2
+#define CCA_ED_THRES3 3
+#define CCA_CS_THRES0 4
+#define CCA_CS_THRES1 5
+#define CCA_CS_THRES2 6
+#define CCA_CS_THRES3 7
+
+#define RX_CTRL _SFR_MEM8(0x14A)
+#define PDT_THRES0 0
+#define PDT_THRES1 1
+#define PDT_THRES2 2
+#define PDT_THRES3 3
+
+#define SFD_VALUE _SFR_MEM8(0x14B)
+#define SFD_VALUE0 0
+#define SFD_VALUE1 1
+#define SFD_VALUE2 2
+#define SFD_VALUE3 3
+#define SFD_VALUE4 4
+#define SFD_VALUE5 5
+#define SFD_VALUE6 6
+#define SFD_VALUE7 7
+
+#define TRX_CTRL_2 _SFR_MEM8(0x14C)
+#define OQPSK_DATA_RATE0 0
+#define OQPSK_DATA_RATE1 1
+#define RX_SAFE_MODE 7
+
+#define ANT_DIV _SFR_MEM8(0x14D)
+#define ANT_CTRL0 0
+#define ANT_CTRL1 1
+#define ANT_EXT_SW_EN 2
+#define ANT_DIV_EN 3
+#define ANT_SEL 7
+
+#define IRQ_MASK _SFR_MEM8(0x14E)
+#define PLL_LOCK_EN 0
+#define PLL_UNLOCK_EN 1
+#define RX_START_EN 2
+#define RX_END_EN 3
+#define CCA_ED_DONE_EN 4
+#define AMI_EN  5
+#define TX_END_EN 6
+#define AWAKE_EN 7
+
+#define IRQ_STATUS _SFR_MEM8(0x14F)
+#define PLL_LOCK 0
+#define PLL_UNLOCK 1
+#define RX_START 2
+#define RX_END  3
+#define CCA_ED_DONE 4
+#define AMI     5
+#define TX_END  6
+#define AWAKE   7
+
+#define VREG_CTRL _SFR_MEM8(0x150)
+#define DVDD_OK 2
+#define DVREG_EXT 3
+#define AVDD_OK 6
+#define AVREG_EXT 7
+
+#define BATMON  _SFR_MEM8(0x151)
+#define BATMON_VTH0 0
+#define BATMON_VTH1 1
+#define BATMON_VTH2 2
+#define BATMON_VTH3 3
+#define BATMON_HR 4
+#define BATMON_OK 5
+#define BAT_LOW_EN 6
+#define BAT_LOW 7
+
+#define XOSC_CTRL _SFR_MEM8(0x152)
+#define XTAL_TRIM0 0
+#define XTAL_TRIM1 1
+#define XTAL_TRIM2 2
+#define XTAL_TRIM3 3
+#define XTAL_MODE0 4
+#define XTAL_MODE1 5
+#define XTAL_MODE2 6
+#define XTAL_MODE3 7
+
+#define CC_CTRL_0 _SFR_MEM8(0x153)
+#define CC_NUMBER0 0
+#define CC_NUMBER1 1
+#define CC_NUMBER2 2
+#define CC_NUMBER3 3
+#define CC_NUMBER4 4
+#define CC_NUMBER5 5
+#define CC_NUMBER6 6
+#define CC_NUMBER7 7
+
+#define CC_CTRL_1 _SFR_MEM8(0x154)
+#define CC_BAND0 0
+#define CC_BAND1 1
+#define CC_BAND2 2
+#define CC_BAND3 3
+
+#define RX_SYN  _SFR_MEM8(0x155)
+#define RX_PDT_LEVEL0 0
+#define RX_PDT_LEVEL1 1
+#define RX_PDT_LEVEL2 2
+#define RX_PDT_LEVEL3 3
+#define RX_OVERRIDE 6
+#define RX_PDT_DIS 7
+
+#define TRX_RPC _SFR_MEM8(0x156)
+#define XAH_RPC_EN 0
+#define IPAN_RPC_EN 1
+#define PLL_RPC_EN 3
+#define PDT_RPC_EN 4
+#define RX_RPC_EN 5
+#define RX_RPC_CTRL0 6
+#define RX_RPC_CTRL1 7
+
+#define XAH_CTRL_1 _SFR_MEM8(0x157)
+#define AACK_PROM_MODE 1
+#define AACK_ACK_TIME 2
+#define AACK_UPLD_RES_FT 4
+#define AACK_FLTR_RES_FT 5
+
+#define FTN_CTRL _SFR_MEM8(0x158)
+#define FTN_START 7
+
+/* Reserved [0x159] */
+
+#define PLL_CF  _SFR_MEM8(0x15A)
+#define PLL_CF_START 7
+
+#define PLL_DCU _SFR_MEM8(0x15B)
+#define PLL_DCU_START 7
+
+#define PART_NUM _SFR_MEM8(0x15C)
+#define PART_NUM0 0
+#define PART_NUM1 1
+#define PART_NUM2 2
+#define PART_NUM3 3
+#define PART_NUM4 4
+#define PART_NUM5 5
+#define PART_NUM6 6
+#define PART_NUM7 7
+
+#define VERSION_NUM _SFR_MEM8(0x15D)
+#define VERSION_NUM0 0
+#define VERSION_NUM1 1
+#define VERSION_NUM2 2
+#define VERSION_NUM3 3
+#define VERSION_NUM4 4
+#define VERSION_NUM5 5
+#define VERSION_NUM6 6
+#define VERSION_NUM7 7
+
+#define MAN_ID_0 _SFR_MEM8(0x15E)
+#define MAN_ID_00 0
+#define MAN_ID_01 1
+#define MAN_ID_02 2
+#define MAN_ID_03 3
+#define MAN_ID_04 4
+#define MAN_ID_05 5
+#define MAN_ID_06 6
+#define MAN_ID_07 7
+
+#define MAN_ID_1 _SFR_MEM8(0x15F)
+#define MAN_ID_10 0
+#define MAN_ID_11 1
+#define MAN_ID_12 2
+#define MAN_ID_13 3
+#define MAN_ID_14 4
+#define MAN_ID_15 5
+#define MAN_ID_16 6
+#define MAN_ID_17 7
+
+#define SHORT_ADDR_0 _SFR_MEM8(0x160)
+#define SHORT_ADDR_00 0
+#define SHORT_ADDR_01 1
+#define SHORT_ADDR_02 2
+#define SHORT_ADDR_03 3
+#define SHORT_ADDR_04 4
+#define SHORT_ADDR_05 5
+#define SHORT_ADDR_06 6
+#define SHORT_ADDR_07 7
+
+#define SHORT_ADDR_1 _SFR_MEM8(0x161)
+#define SHORT_ADDR_10 0
+#define SHORT_ADDR_11 1
+#define SHORT_ADDR_12 2
+#define SHORT_ADDR_13 3
+#define SHORT_ADDR_14 4
+#define SHORT_ADDR_15 5
+#define SHORT_ADDR_16 6
+#define SHORT_ADDR_17 7
+
+#define PAN_ID_0 _SFR_MEM8(0x162)
+#define PAN_ID_00 0
+#define PAN_ID_01 1
+#define PAN_ID_02 2
+#define PAN_ID_03 3
+#define PAN_ID_04 4
+#define PAN_ID_05 5
+#define PAN_ID_06 6
+#define PAN_ID_07 7
+
+#define PAN_ID_1 _SFR_MEM8(0x163)
+#define PAN_ID_10 0
+#define PAN_ID_11 1
+#define PAN_ID_12 2
+#define PAN_ID_13 3
+#define PAN_ID_14 4
+#define PAN_ID_15 5
+#define PAN_ID_16 6
+#define PAN_ID_17 7
+
+#define IEEE_ADDR_0 _SFR_MEM8(0x164)
+#define IEEE_ADDR_00 0
+#define IEEE_ADDR_01 1
+#define IEEE_ADDR_02 2
+#define IEEE_ADDR_03 3
+#define IEEE_ADDR_04 4
+#define IEEE_ADDR_05 5
+#define IEEE_ADDR_06 6
+#define IEEE_ADDR_07 7
+
+#define IEEE_ADDR_1 _SFR_MEM8(0x165)
+#define IEEE_ADDR_10 0
+#define IEEE_ADDR_11 1
+#define IEEE_ADDR_12 2
+#define IEEE_ADDR_13 3
+#define IEEE_ADDR_14 4
+#define IEEE_ADDR_15 5
+#define IEEE_ADDR_16 6
+#define IEEE_ADDR_17 7
+
+#define IEEE_ADDR_2 _SFR_MEM8(0x166)
+#define IEEE_ADDR_20 0
+#define IEEE_ADDR_21 1
+#define IEEE_ADDR_22 2
+#define IEEE_ADDR_23 3
+#define IEEE_ADDR_24 4
+#define IEEE_ADDR_25 5
+#define IEEE_ADDR_26 6
+#define IEEE_ADDR_27 7
+
+#define IEEE_ADDR_3 _SFR_MEM8(0x167)
+#define IEEE_ADDR_30 0
+#define IEEE_ADDR_31 1
+#define IEEE_ADDR_32 2
+#define IEEE_ADDR_33 3
+#define IEEE_ADDR_34 4
+#define IEEE_ADDR_35 5
+#define IEEE_ADDR_36 6
+#define IEEE_ADDR_37 7
+
+#define IEEE_ADDR_4 _SFR_MEM8(0x168)
+#define IEEE_ADDR_40 0
+#define IEEE_ADDR_41 1
+#define IEEE_ADDR_42 2
+#define IEEE_ADDR_43 3
+#define IEEE_ADDR_44 4
+#define IEEE_ADDR_45 5
+#define IEEE_ADDR_46 6
+#define IEEE_ADDR_47 7
+
+#define IEEE_ADDR_5 _SFR_MEM8(0x169)
+#define IEEE_ADDR_50 0
+#define IEEE_ADDR_51 1
+#define IEEE_ADDR_52 2
+#define IEEE_ADDR_53 3
+#define IEEE_ADDR_54 4
+#define IEEE_ADDR_55 5
+#define IEEE_ADDR_56 6
+#define IEEE_ADDR_57 7
+
+#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
+#define IEEE_ADDR_60 0
+#define IEEE_ADDR_61 1
+#define IEEE_ADDR_62 2
+#define IEEE_ADDR_63 3
+#define IEEE_ADDR_64 4
+#define IEEE_ADDR_65 5
+#define IEEE_ADDR_66 6
+#define IEEE_ADDR_67 7
+
+#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
+#define IEEE_ADDR_70 0
+#define IEEE_ADDR_71 1
+#define IEEE_ADDR_72 2
+#define IEEE_ADDR_73 3
+#define IEEE_ADDR_74 4
+#define IEEE_ADDR_75 5
+#define IEEE_ADDR_76 6
+#define IEEE_ADDR_77 7
+
+#define XAH_CTRL_0 _SFR_MEM8(0x16C)
+#define SLOTTED_OPERATION 0
+#define MAX_CSMA_RETRIES0 1
+#define MAX_CSMA_RETRIES1 2
+#define MAX_CSMA_RETRIES2 3
+#define MAX_FRAME_RETRIES0 4
+#define MAX_FRAME_RETRIES1 5
+#define MAX_FRAME_RETRIES2 6
+#define MAX_FRAME_RETRIES3 7
+
+#define CSMA_SEED_0 _SFR_MEM8(0x16D)
+#define CSMA_SEED_00 0
+#define CSMA_SEED_01 1
+#define CSMA_SEED_02 2
+#define CSMA_SEED_03 3
+#define CSMA_SEED_04 4
+#define CSMA_SEED_05 5
+#define CSMA_SEED_06 6
+#define CSMA_SEED_07 7
+
+#define CSMA_SEED_1 _SFR_MEM8(0x16E)
+#define CSMA_SEED_10 0
+#define CSMA_SEED_11 1
+#define CSMA_SEED_12 2
+#define AACK_I_AM_COORD 3
+#define AACK_DIS_ACK 4
+#define AACK_SET_PD 5
+#define AACK_FVN_MODE0 6
+#define AACK_FVN_MODE1 7
+
+#define CSMA_BE _SFR_MEM8(0x16F)
+#define MIN_BE0 0
+#define MIN_BE1 1
+#define MIN_BE2 2
+#define MIN_BE3 3
+#define MAX_BE0 4
+#define MAX_BE1 5
+#define MAX_BE2 6
+#define MAX_BE3 7
+
+/* Reserved [0x170..0x175] */
+
+#define TST_CTRL_DIGI _SFR_MEM8(0x176)
+#define TST_CTRL_DIG0 0
+#define TST_CTRL_DIG1 1
+#define TST_CTRL_DIG2 2
+#define TST_CTRL_DIG3 3
+
+/* Reserved [0x177..0x17A] */
+
+#define TST_RX_LENGTH _SFR_MEM8(0x17B)
+#define RX_LENGTH0 0
+#define RX_LENGTH1 1
+#define RX_LENGTH2 2
+#define RX_LENGTH3 3
+#define RX_LENGTH4 4
+#define RX_LENGTH5 5
+#define RX_LENGTH6 6
+#define RX_LENGTH7 7
+
+/* Reserved [0x17C..0x17F] */
+
+#define TRXFBST _SFR_MEM8(0x180)
 
-/* Start of frame buffer */
-#define TRXFBST                         _SFR_MEM8(0x180)
+/* Reserved [0x181..0x1FE] */
 
-  /* TRXFBST */
+#define TRXFBEND _SFR_MEM8(0x1FF)
 
-#define TRXFBST0                        0
-#define TRXFBST1                        1
-#define TRXFBST2                        2
-#define TRXFBST3                        3
-#define TRXFBST4                        4
-#define TRXFBST5                        5
-#define TRXFBST6                        6
-#define TRXFBST7                        7
 
-/* End of frame buffer */
-#define TRXFBEND                        _SFR_MEM8(0x1FF)
 
-  /* TRXFBEND */
+/* Values and associated defines */
 
-#define TRXFBEND0                       0
-#define TRXFBEND1                       1
-#define TRXFBEND2                       2
-#define TRXFBEND3                       3
-#define TRXFBEND4                       4
-#define TRXFBEND5                       5
-#define TRXFBEND6                       6
-#define TRXFBEND7                       7
 
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
-
-#define _VECTORS_SIZE                  308
-
 /* External Interrupt Request 0 */
-#define INT0_vect                       _VECTOR(1)
-#define INT0_vect_num                   1
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
 
 /* External Interrupt Request 1 */
-#define INT1_vect                       _VECTOR(2)
-#define INT1_vect_num                   2
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
 
 /* External Interrupt Request 2 */
-#define INT2_vect                       _VECTOR(3)
-#define INT2_vect_num                   3
+#define INT2_vect            _VECTOR(3)
+#define INT2_vect_num        3
 
 /* External Interrupt Request 3 */
-#define INT3_vect                       _VECTOR(4)
-#define INT3_vect_num                   4
+#define INT3_vect            _VECTOR(4)
+#define INT3_vect_num        4
 
 /* External Interrupt Request 4 */
-#define INT4_vect                       _VECTOR(5)
-#define INT4_vect_num                   5
+#define INT4_vect            _VECTOR(5)
+#define INT4_vect_num        5
 
 /* External Interrupt Request 5 */
-#define INT5_vect                       _VECTOR(6)
-#define INT5_vect_num                   6
+#define INT5_vect            _VECTOR(6)
+#define INT5_vect_num        6
 
 /* External Interrupt Request 6 */
-#define INT6_vect                       _VECTOR(7)
-#define INT6_vect_num                   7
+#define INT6_vect            _VECTOR(7)
+#define INT6_vect_num        7
 
 /* External Interrupt Request 7 */
-#define INT7_vect                       _VECTOR(8)
-#define INT7_vect_num                   8
+#define INT7_vect            _VECTOR(8)
+#define INT7_vect_num        8
 
 /* Pin Change Interrupt Request 0 */
-#define PCINT0_vect                     _VECTOR(9)
-#define PCINT0_vect_num                 9
+#define PCINT0_vect            _VECTOR(9)
+#define PCINT0_vect_num        9
 
 /* Pin Change Interrupt Request 1 */
-#define PCINT1_vect                     _VECTOR(10)
-#define PCINT1_vect_num                 10
+#define PCINT1_vect            _VECTOR(10)
+#define PCINT1_vect_num        10
 
 /* Pin Change Interrupt Request 2 */
-#define PCINT2_vect                     _VECTOR(11)
-#define PCINT2_vect_num                 11
+#define PCINT2_vect            _VECTOR(11)
+#define PCINT2_vect_num        11
 
 /* Watchdog Time-out Interrupt */
-#define WDT_vect                        _VECTOR(12)
-#define WDT_vect_num                    12
+#define WDT_vect            _VECTOR(12)
+#define WDT_vect_num        12
 
 /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect               _VECTOR(13)
-#define TIMER2_COMPA_vect_num           13
+#define TIMER2_COMPA_vect            _VECTOR(13)
+#define TIMER2_COMPA_vect_num        13
 
 /* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect               _VECTOR(14)
-#define TIMER2_COMPB_vect_num           14
+#define TIMER2_COMPB_vect            _VECTOR(14)
+#define TIMER2_COMPB_vect_num        14
 
 /* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect                 _VECTOR(15)
-#define TIMER2_OVF_vect_num             15
+#define TIMER2_OVF_vect            _VECTOR(15)
+#define TIMER2_OVF_vect_num        15
 
 /* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect                _VECTOR(16)
-#define TIMER1_CAPT_vect_num            16
+#define TIMER1_CAPT_vect            _VECTOR(16)
+#define TIMER1_CAPT_vect_num        16
 
 /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect               _VECTOR(17)
-#define TIMER1_COMPA_vect_num           17
+#define TIMER1_COMPA_vect            _VECTOR(17)
+#define TIMER1_COMPA_vect_num        17
 
 /* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect               _VECTOR(18)
-#define TIMER1_COMPB_vect_num           18
+#define TIMER1_COMPB_vect            _VECTOR(18)
+#define TIMER1_COMPB_vect_num        18
 
 /* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect               _VECTOR(19)
-#define TIMER1_COMPC_vect_num           19
+#define TIMER1_COMPC_vect            _VECTOR(19)
+#define TIMER1_COMPC_vect_num        19
 
 /* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect                 _VECTOR(20)
-#define TIMER1_OVF_vect_num             20
+#define TIMER1_OVF_vect            _VECTOR(20)
+#define TIMER1_OVF_vect_num        20
 
 /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect               _VECTOR(21)
-#define TIMER0_COMPA_vect_num           21
+#define TIMER0_COMPA_vect            _VECTOR(21)
+#define TIMER0_COMPA_vect_num        21
 
 /* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect               _VECTOR(22)
-#define TIMER0_COMPB_vect_num           22
+#define TIMER0_COMPB_vect            _VECTOR(22)
+#define TIMER0_COMPB_vect_num        22
 
 /* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect                 _VECTOR(23)
-#define TIMER0_OVF_vect_num             23
+#define TIMER0_OVF_vect            _VECTOR(23)
+#define TIMER0_OVF_vect_num        23
 
 /* SPI Serial Transfer Complete */
-#define SPI_STC_vect                    _VECTOR(24)
-#define SPI_STC_vect_num                24
+#define SPI_STC_vect            _VECTOR(24)
+#define SPI_STC_vect_num        24
 
 /* USART0, Rx Complete */
-#define USART0_RX_vect                  _VECTOR(25)
-#define USART0_RX_vect_num              25
+#define USART0_RX_vect            _VECTOR(25)
+#define USART0_RX_vect_num        25
 
 /* USART0 Data register Empty */
-#define USART0_UDRE_vect                _VECTOR(26)
-#define USART0_UDRE_vect_num            26
+#define USART0_UDRE_vect            _VECTOR(26)
+#define USART0_UDRE_vect_num        26
 
 /* USART0, Tx Complete */
-#define USART0_TX_vect                  _VECTOR(27)
-#define USART0_TX_vect_num              27
+#define USART0_TX_vect            _VECTOR(27)
+#define USART0_TX_vect_num        27
 
 /* Analog Comparator */
-#define ANALOG_COMP_vect                _VECTOR(28)
-#define ANALOG_COMP_vect_num            28
+#define ANALOG_COMP_vect            _VECTOR(28)
+#define ANALOG_COMP_vect_num        28
 
 /* ADC Conversion Complete */
-#define ADC_vect                        _VECTOR(29)
-#define ADC_vect_num                    29
+#define ADC_vect            _VECTOR(29)
+#define ADC_vect_num        29
 
 /* EEPROM Ready */
-#define EE_READY_vect                   _VECTOR(30)
-#define EE_READY_vect_num               30
+#define EE_READY_vect            _VECTOR(30)
+#define EE_READY_vect_num        30
 
 /* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect                _VECTOR(31)
-#define TIMER3_CAPT_vect_num            31
+#define TIMER3_CAPT_vect            _VECTOR(31)
+#define TIMER3_CAPT_vect_num        31
 
 /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect               _VECTOR(32)
-#define TIMER3_COMPA_vect_num           32
+#define TIMER3_COMPA_vect            _VECTOR(32)
+#define TIMER3_COMPA_vect_num        32
 
 /* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect               _VECTOR(33)
-#define TIMER3_COMPB_vect_num           33
+#define TIMER3_COMPB_vect            _VECTOR(33)
+#define TIMER3_COMPB_vect_num        33
 
 /* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect               _VECTOR(34)
-#define TIMER3_COMPC_vect_num           34
+#define TIMER3_COMPC_vect            _VECTOR(34)
+#define TIMER3_COMPC_vect_num        34
 
 /* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect                 _VECTOR(35)
-#define TIMER3_OVF_vect_num             35
+#define TIMER3_OVF_vect            _VECTOR(35)
+#define TIMER3_OVF_vect_num        35
 
 /* USART1, Rx Complete */
-#define USART1_RX_vect                  _VECTOR(36)
-#define USART1_RX_vect_num              36
+#define USART1_RX_vect            _VECTOR(36)
+#define USART1_RX_vect_num        36
 
 /* USART1 Data register Empty */
-#define USART1_UDRE_vect                _VECTOR(37)
-#define USART1_UDRE_vect_num            37
+#define USART1_UDRE_vect            _VECTOR(37)
+#define USART1_UDRE_vect_num        37
 
 /* USART1, Tx Complete */
-#define USART1_TX_vect                  _VECTOR(38)
-#define USART1_TX_vect_num              38
+#define USART1_TX_vect            _VECTOR(38)
+#define USART1_TX_vect_num        38
 
 /* 2-wire Serial Interface */
-#define TWI_vect                        _VECTOR(39)
-#define TWI_vect_num                    39
+#define TWI_vect            _VECTOR(39)
+#define TWI_vect_num        39
 
 /* Store Program Memory Read */
-#define SPM_READY_vect                  _VECTOR(40)
-#define SPM_READY_vect_num              40
+#define SPM_READY_vect            _VECTOR(40)
+#define SPM_READY_vect_num        40
 
 /* Timer/Counter4 Capture Event */
-#define TIMER4_CAPT_vect                _VECTOR(41)
-#define TIMER4_CAPT_vect_num            41
+#define TIMER4_CAPT_vect            _VECTOR(41)
+#define TIMER4_CAPT_vect_num        41
 
 /* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPA_vect               _VECTOR(42)
-#define TIMER4_COMPA_vect_num           42
+#define TIMER4_COMPA_vect            _VECTOR(42)
+#define TIMER4_COMPA_vect_num        42
 
 /* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPB_vect               _VECTOR(43)
-#define TIMER4_COMPB_vect_num           43
+#define TIMER4_COMPB_vect            _VECTOR(43)
+#define TIMER4_COMPB_vect_num        43
 
 /* Timer/Counter4 Compare Match C */
-#define TIMER4_COMPC_vect               _VECTOR(44)
-#define TIMER4_COMPC_vect_num           44
+#define TIMER4_COMPC_vect            _VECTOR(44)
+#define TIMER4_COMPC_vect_num        44
 
 /* Timer/Counter4 Overflow */
-#define TIMER4_OVF_vect                 _VECTOR(45)
-#define TIMER4_OVF_vect_num             45
+#define TIMER4_OVF_vect            _VECTOR(45)
+#define TIMER4_OVF_vect_num        45
 
 /* Timer/Counter5 Capture Event */
-#define TIMER5_CAPT_vect                _VECTOR(46)
-#define TIMER5_CAPT_vect_num            46
+#define TIMER5_CAPT_vect            _VECTOR(46)
+#define TIMER5_CAPT_vect_num        46
 
 /* Timer/Counter5 Compare Match A */
-#define TIMER5_COMPA_vect               _VECTOR(47)
-#define TIMER5_COMPA_vect_num           47
+#define TIMER5_COMPA_vect            _VECTOR(47)
+#define TIMER5_COMPA_vect_num        47
 
 /* Timer/Counter5 Compare Match B */
-#define TIMER5_COMPB_vect               _VECTOR(48)
-#define TIMER5_COMPB_vect_num           48
+#define TIMER5_COMPB_vect            _VECTOR(48)
+#define TIMER5_COMPB_vect_num        48
 
 /* Timer/Counter5 Compare Match C */
-#define TIMER5_COMPC_vect               _VECTOR(49)
-#define TIMER5_COMPC_vect_num           49
+#define TIMER5_COMPC_vect            _VECTOR(49)
+#define TIMER5_COMPC_vect_num        49
 
 /* Timer/Counter5 Overflow */
-#define TIMER5_OVF_vect                 _VECTOR(50)
-#define TIMER5_OVF_vect_num             50
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_51_vect                _VECTOR(51)
-#define RESERVED_51_vect_num            51
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_52_vect                _VECTOR(52)
-#define RESERVED_52_vect_num            52
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_53_vect                _VECTOR(53)
-#define RESERVED_53_vect_num            53
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_54_vect                _VECTOR(54)
-#define RESERVED_54_vect_num            54
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_55_vect                _VECTOR(55)
-#define RESERVED_55_vect_num            55
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_56_vect                _VECTOR(56)
-#define RESERVED_56_vect_num            56
+#define TIMER5_OVF_vect            _VECTOR(50)
+#define TIMER5_OVF_vect_num        50
 
 /* TRX24 - PLL lock interrupt */
-#define TRX24_PLL_LOCK_vect             _VECTOR(57)
-#define TRX24_PLL_LOCK_vect_num         57
+#define TRX24_PLL_LOCK_vect            _VECTOR(57)
+#define TRX24_PLL_LOCK_vect_num        57
 
 /* TRX24 - PLL unlock interrupt */
-#define TRX24_PLL_UNLOCK_vect           _VECTOR(58)
-#define TRX24_PLL_UNLOCK_vect_num       58
+#define TRX24_PLL_UNLOCK_vect            _VECTOR(58)
+#define TRX24_PLL_UNLOCK_vect_num        58
 
 /* TRX24 - Receive start interrupt */
-#define TRX24_RX_START_vect             _VECTOR(59)
-#define TRX24_RX_START_vect_num         59
+#define TRX24_RX_START_vect            _VECTOR(59)
+#define TRX24_RX_START_vect_num        59
 
 /* TRX24 - RX_END interrupt */
-#define TRX24_RX_END_vect               _VECTOR(60)
-#define TRX24_RX_END_vect_num           60
+#define TRX24_RX_END_vect            _VECTOR(60)
+#define TRX24_RX_END_vect_num        60
 
 /* TRX24 - CCA/ED done interrupt */
-#define TRX24_CCA_ED_DONE_vect          _VECTOR(61)
-#define TRX24_CCA_ED_DONE_vect_num      61
+#define TRX24_CCA_ED_DONE_vect            _VECTOR(61)
+#define TRX24_CCA_ED_DONE_vect_num        61
 
 /* TRX24 - XAH - AMI */
-#define TRX24_XAH_AMI_vect              _VECTOR(62)
-#define TRX24_XAH_AMI_vect_num          62
+#define TRX24_XAH_AMI_vect            _VECTOR(62)
+#define TRX24_XAH_AMI_vect_num        62
 
 /* TRX24 - TX_END interrupt */
-#define TRX24_TX_END_vect               _VECTOR(63)
-#define TRX24_TX_END_vect_num           63
+#define TRX24_TX_END_vect            _VECTOR(63)
+#define TRX24_TX_END_vect_num        63
 
 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
-#define TRX24_AWAKE_vect                _VECTOR(64)
-#define TRX24_AWAKE_vect_num            64
+#define TRX24_AWAKE_vect            _VECTOR(64)
+#define TRX24_AWAKE_vect_num        64
 
 /* Symbol counter - compare match 1 interrupt */
-#define SCNT_CMP1_vect                  _VECTOR(65)
-#define SCNT_CMP1_vect_num              65
+#define SCNT_CMP1_vect            _VECTOR(65)
+#define SCNT_CMP1_vect_num        65
 
 /* Symbol counter - compare match 2 interrupt */
-#define SCNT_CMP2_vect                  _VECTOR(66)
-#define SCNT_CMP2_vect_num              66
+#define SCNT_CMP2_vect            _VECTOR(66)
+#define SCNT_CMP2_vect_num        66
 
 /* Symbol counter - compare match 3 interrupt */
-#define SCNT_CMP3_vect                  _VECTOR(67)
-#define SCNT_CMP3_vect_num              67
+#define SCNT_CMP3_vect            _VECTOR(67)
+#define SCNT_CMP3_vect_num        67
 
 /* Symbol counter - overflow interrupt */
-#define SCNT_OVFL_vect                  _VECTOR(68)
-#define SCNT_OVFL_vect_num              68
+#define SCNT_OVFL_vect            _VECTOR(68)
+#define SCNT_OVFL_vect_num        68
 
 /* Symbol counter - backoff interrupt */
-#define SCNT_BACKOFF_vect               _VECTOR(69)
-#define SCNT_BACKOFF_vect_num           69
+#define SCNT_BACKOFF_vect            _VECTOR(69)
+#define SCNT_BACKOFF_vect_num        69
 
 /* AES engine ready interrupt */
-#define AES_READY_vect                  _VECTOR(70)
-#define AES_READY_vect_num              70
+#define AES_READY_vect            _VECTOR(70)
+#define AES_READY_vect_num        70
 
 /* Battery monitor indicates supply voltage below threshold */
-#define BAT_LOW_vect                    _VECTOR(71)
-#define BAT_LOW_vect_num                71
+#define BAT_LOW_vect            _VECTOR(71)
+#define BAT_LOW_vect_num        71
 
 /* TRX24 TX start interrupt */
-#define TRX24_TX_START_vect             _VECTOR(72)
-#define TRX24_TX_START_vect_num         72
+#define TRX24_TX_START_vect            _VECTOR(72)
+#define TRX24_TX_START_vect_num        72
 
 /* Address match interrupt of address filter 0 */
-#define TRX24_AMI0_vect                 _VECTOR(73)
-#define TRX24_AMI0_vect_num             73
+#define TRX24_AMI0_vect            _VECTOR(73)
+#define TRX24_AMI0_vect_num        73
 
 /* Address match interrupt of address filter 1 */
-#define TRX24_AMI1_vect                 _VECTOR(74)
-#define TRX24_AMI1_vect_num             74
+#define TRX24_AMI1_vect            _VECTOR(74)
+#define TRX24_AMI1_vect_num        74
 
 /* Address match interrupt of address filter 2 */
-#define TRX24_AMI2_vect                 _VECTOR(75)
-#define TRX24_AMI2_vect_num             75
+#define TRX24_AMI2_vect            _VECTOR(75)
+#define TRX24_AMI2_vect_num        75
 
 /* Address match interrupt of address filter 3 */
-#define TRX24_AMI3_vect                 _VECTOR(76)
-#define TRX24_AMI3_vect_num             76
+#define TRX24_AMI3_vect            _VECTOR(76)
+#define TRX24_AMI3_vect_num        76
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 308
+#else
+#  define _VECTORS_SIZE 308U
+#endif
 
 
-/* memory parameters */
+/* Constants */
 
-#define SPM_PAGESIZE                    (256)
-#define RAMSTART                        (0x200)
-#define RAMSIZE                         (0x8000)
-#define RAMEND                          (0x81FF)
-#define XRAMSTART                       (0x0000)
-#define XRAMSIZE                        (0x0000)
-#define XRAMEND                         RAMEND
-#define E2END                           (0x1FFF)
-#define E2PAGESIZE                      (0x08)
-#define FLASHEND                        (0x3ffff)
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 256
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFFF
+#else
+#  define SPM_PAGESIZE 256U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      32768
+#  define RAMEND       0x81FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      32768U
+#  define RAMEND       0x81FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      8192
+#  define E2PAGESIZE  8
+#  define E2END       0x1FFF
+#else
+#  define E2START     0U
+#  define E2SIZE      8192U
+#  define E2PAGESIZE  8U
+#  define E2END       0x1FFFU
+#endif
+#define XRAMEND      RAMEND
 
 
 /* Fuses */
 
 #define FUSE_MEMORY_SIZE 3
 
-/* LFUSE Byte */
-#define FUSE_CKSEL0     ~_BV(0) /* Select Clock Source */
-#define FUSE_CKSEL1     ~_BV(1) /* Select Clock Source */
-#define FUSE_CKSEL2     ~_BV(2) /* Select Clock Source */
-#define FUSE_CKSEL3     ~_BV(3) /* Select Clock Source */
-#define FUSE_SUT0       ~_BV(4) /* Select start-up time */
-#define FUSE_SUT1       ~_BV(5) /* Select start-up time */
-#define FUSE_CKOUT      ~_BV(6) /* Clock output */
-#define FUSE_CKDIV8     ~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* HFUSE Byte */
-#define FUSE_BOOTRST    ~_BV(0) /* Select Reset Vector */
-#define FUSE_BOOTSZ0    ~_BV(1) /* Select Boot Size */
-#define FUSE_BOOTSZ1    ~_BV(2) /* Select Boot Size */
-#define FUSE_EESAVE     ~_BV(3) /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      ~_BV(4) /* Watchdog timer always on */
-#define FUSE_SPIEN      ~_BV(5) /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN     ~_BV(6) /* Enable JTAG */
-#define FUSE_OCDEN      ~_BV(7) /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* EFUSE Byte */
-#define FUSE_BODLEVEL0  ~_BV(0) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  ~_BV(1) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  ~_BV(2) /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
+/* Low Fuse Byte */
+#define FUSE_CKSEL_SUT0  (unsigned char)~_BV(0)
+#define FUSE_CKSEL_SUT1  (unsigned char)~_BV(1)
+#define FUSE_CKSEL_SUT2  (unsigned char)~_BV(2)
+#define FUSE_CKSEL_SUT3  (unsigned char)~_BV(3)
+#define FUSE_CKSEL_SUT4  (unsigned char)~_BV(4)
+#define FUSE_CKSEL_SUT5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_CKSEL_SUT0 & FUSE_CKSEL_SUT2 & FUSE_CKSEL_SUT3 & FUSE_CKSEL_SUT4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BODLEVEL0)
 
 
 
 /* Lock Bits */
-
+#define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST
-#define __LOCK_BITS_EXIST
 
 
 /* Signature */
-
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0xA8
 #define SIGNATURE_2 0x03
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 
-#endif /* _AVR_IOM2564RFR2_H_ */
+
+#endif /* #ifdef _AVR_ATMEGA2564RFR2_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom256rfr2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom256rfr2.h
@@ -1,41 +1,25 @@
-/* Copyright (c) 2013 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* $Id$ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
 
-/* avr/iom256rfr2.h - definitions for ATmega256RFR2 */
 
-#ifndef _AVR_IOM256RFR2_H_
-#define _AVR_IOM256RFR2_H_ 1
+#ifndef _AVR_ATMEGA256RFR2_H_INCLUDED
+#define _AVR_ATMEGA256RFR2_H_INCLUDED
 
-/* This file should only be included from <avr/io.h>, never directly. */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -47,1197 +31,581 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif
 
-#include <avr/sfr_defs.h>
+/* Registers and associated bit numbers */
 
-#ifndef __ASSEMBLER__
-#  define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr))
-#  define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type)
-#  define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type)
-#endif /* __ASSEMBLER__ */
-
-/*
- * USAGE:
- *
- * simple register assignment:
- * TIFR1 = 0x17
- * subregister assignment:
- * TIFR1_struct.ocf1a = 1
- * (subregister names are converted to small letters)
- */
-
-
-/* Port A Input Pins Address */
-#define PINA                            _SFR_IO8(0x00)
-
-  /* PINA */
-
-#define PINA0                           0
-#define PINA1                           1
-#define PINA2                           2
-#define PINA3                           3
-#define PINA4                           4
-#define PINA5                           5
-#define PINA6                           6
-#define PINA7                           7
-
-/* Port A Data Direction Register */
-#define DDRA                            _SFR_IO8(0x01)
-
-  /* DDRA */
-
-#define DDA0                            0
-#define DDA1                            1
-#define DDA2                            2
-#define DDA3                            3
-#define DDA4                            4
-#define DDA5                            5
-#define DDA6                            6
-#define DDA7                            7
-
-/* Port A Data Register */
-#define PORTA                           _SFR_IO8(0x02)
-
-  /* PORTA */
-
-#define PORTA0                          0
-#define PA0                             0
-#define PORTA1                          1
-#define PA1                             1
-#define PORTA2                          2
-#define PA2                             2
-#define PORTA3                          3
-#define PA3                             3
-#define PORTA4                          4
-#define PA4                             4
-#define PORTA5                          5
-#define PA5                             5
-#define PORTA6                          6
-#define PA6                             6
-#define PORTA7                          7
-#define PA7                             7
-
-/* Port B Input Pins Address */
-#define PINB                            _SFR_IO8(0x03)
-
-  /* PINB */
-
-#define PINB0                           0
-#define PINB1                           1
-#define PINB2                           2
-#define PINB3                           3
-#define PINB4                           4
-#define PINB5                           5
-#define PINB6                           6
-#define PINB7                           7
-
-/* Port B Data Direction Register */
-#define DDRB                            _SFR_IO8(0x04)
-
-  /* DDRB */
-
-#define DDB0                            0
-#define DDB1                            1
-#define DDB2                            2
-#define DDB3                            3
-#define DDB4                            4
-#define DDB5                            5
-#define DDB6                            6
-#define DDB7                            7
-
-/* Port B Data Register */
-#define PORTB                           _SFR_IO8(0x05)
-
-  /* PORTB */
-
-#define PORTB0                          0
-#define PB0                             0
-#define PORTB1                          1
-#define PB1                             1
-#define PORTB2                          2
-#define PB2                             2
-#define PORTB3                          3
-#define PB3                             3
-#define PORTB4                          4
-#define PB4                             4
-#define PORTB5                          5
-#define PB5                             5
-#define PORTB6                          6
-#define PB6                             6
-#define PORTB7                          7
-#define PB7                             7
-
-/* Port C Input Pins Address */
-#define PINC                            _SFR_IO8(0x06)
-
-  /* PINC */
-
-#define PINC0                           0
-#define PINC1                           1
-#define PINC2                           2
-#define PINC3                           3
-#define PINC4                           4
-#define PINC5                           5
-#define PINC6                           6
-#define PINC7                           7
-
-/* Port C Data Direction Register */
-#define DDRC                            _SFR_IO8(0x07)
-
-  /* DDRC */
-
-#define DDC0                            0
-#define DDC1                            1
-#define DDC2                            2
-#define DDC3                            3
-#define DDC4                            4
-#define DDC5                            5
-#define DDC6                            6
-#define DDC7                            7
-
-/* Port C Data Register */
-#define PORTC                           _SFR_IO8(0x08)
-
-  /* PORTC */
-
-#define PORTC0                          0
-#define PC0                             0
-#define PORTC1                          1
-#define PC1                             1
-#define PORTC2                          2
-#define PC2                             2
-#define PORTC3                          3
-#define PC3                             3
-#define PORTC4                          4
-#define PC4                             4
-#define PORTC5                          5
-#define PC5                             5
-#define PORTC6                          6
-#define PC6                             6
-#define PORTC7                          7
-#define PC7                             7
-
-/* Port D Input Pins Address */
-#define PIND                            _SFR_IO8(0x09)
-
-  /* PIND */
-
-#define PIND0                           0
-#define PIND1                           1
-#define PIND2                           2
-#define PIND3                           3
-#define PIND4                           4
-#define PIND5                           5
-#define PIND6                           6
-#define PIND7                           7
-
-/* Port D Data Direction Register */
-#define DDRD                            _SFR_IO8(0x0A)
-
-  /* DDRD */
-
-#define DDD0                            0
-#define DDD1                            1
-#define DDD2                            2
-#define DDD3                            3
-#define DDD4                            4
-#define DDD5                            5
-#define DDD6                            6
-#define DDD7                            7
-
-/* Port D Data Register */
-#define PORTD                           _SFR_IO8(0x0B)
-
-  /* PORTD */
-
-#define PORTD0                          0
-#define PD0                             0
-#define PORTD1                          1
-#define PD1                             1
-#define PORTD2                          2
-#define PD2                             2
-#define PORTD3                          3
-#define PD3                             3
-#define PORTD4                          4
-#define PD4                             4
-#define PORTD5                          5
-#define PD5                             5
-#define PORTD6                          6
-#define PD6                             6
-#define PORTD7                          7
-#define PD7                             7
-
-/* Port E Input Pins Address */
-#define PINE                            _SFR_IO8(0x0C)
-
-  /* PINE */
-
-#define PINE0                           0
-#define PINE1                           1
-#define PINE2                           2
-#define PINE3                           3
-#define PINE4                           4
-#define PINE5                           5
-#define PINE6                           6
-#define PINE7                           7
-
-/* Port E Data Direction Register */
-#define DDRE                            _SFR_IO8(0x0D)
-
-  /* DDRE */
-
-#define DDE0                            0
-#define DDE1                            1
-#define DDE2                            2
-#define DDE3                            3
-#define DDE4                            4
-#define DDE5                            5
-#define DDE6                            6
-#define DDE7                            7
-
-/* Port E Data Register */
-#define PORTE                           _SFR_IO8(0x0E)
-
-  /* PORTE */
-
-#define PORTE0                          0
-#define PE0                             0
-#define PORTE1                          1
-#define PE1                             1
-#define PORTE2                          2
-#define PE2                             2
-#define PORTE3                          3
-#define PE3                             3
-#define PORTE4                          4
-#define PE4                             4
-#define PORTE5                          5
-#define PE5                             5
-#define PORTE6                          6
-#define PE6                             6
-#define PORTE7                          7
-#define PE7                             7
-
-/* Port F Input Pins Address */
-#define PINF                            _SFR_IO8(0x0F)
-
-  /* PINF */
-
-#define PINF0                           0
-#define PINF1                           1
-#define PINF2                           2
-#define PINF3                           3
-#define PINF4                           4
-#define PINF5                           5
-#define PINF6                           6
-#define PINF7                           7
-
-/* Port F Data Direction Register */
-#define DDRF                            _SFR_IO8(0x10)
-
-  /* DDRF */
-
-#define DDF0                            0
-#define DDF1                            1
-#define DDF2                            2
-#define DDF3                            3
-#define DDF4                            4
-#define DDF5                            5
-#define DDF6                            6
-#define DDF7                            7
-
-/* Port F Data Register */
-#define PORTF                           _SFR_IO8(0x11)
-
-  /* PORTF */
-
-#define PORTF0                          0
-#define PF0                             0
-#define PORTF1                          1
-#define PF1                             1
-#define PORTF2                          2
-#define PF2                             2
-#define PORTF3                          3
-#define PF3                             3
-#define PORTF4                          4
-#define PF4                             4
-#define PORTF5                          5
-#define PF5                             5
-#define PORTF6                          6
-#define PF6                             6
-#define PORTF7                          7
-#define PF7                             7
-
-/* Port G Input Pins Address */
-#define PING                            _SFR_IO8(0x12)
-
-  /* PING */
-
-#define PING0                           0
-#define PING1                           1
-#define PING2                           2
-#define PING3                           3
-#define PING4                           4
-#define PING5                           5
-
-/* Port G Data Direction Register */
-#define DDRG                            _SFR_IO8(0x13)
-
-  /* DDRG */
-
-#define DDG0                            0
-#define DDG1                            1
-#define DDG2                            2
-#define DDG3                            3
-#define DDG4                            4
-#define DDG5                            5
-
-/* Port G Data Register */
-#define PORTG                           _SFR_IO8(0x14)
-
-  /* PORTG */
-
-#define PORTG0                          0
-#define PG0                             0
-#define PORTG1                          1
-#define PG1                             1
-#define PORTG2                          2
-#define PG2                             2
-#define PORTG3                          3
-#define PG3                             3
-#define PORTG4                          4
-#define PG4                             4
-#define PORTG5                          5
-#define PG5                             5
-
-/* Timer/Counter0 Interrupt Flag Register */
-#define TIFR0                           _SFR_IO8(0x15)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR0 {
-        unsigned int tov0 : 1;	/* Timer/Counter0 Overflow Flag */
-        unsigned int ocf0a : 1;	/* Timer/Counter0 Output Compare A Match Flag */
-        unsigned int ocf0b : 1;	/* Timer/Counter0 Output Compare B Match Flag */
-        unsigned int : 5;
-};
-
-#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR0 */
-
-#define TOV0                            0
-#define OCF0A                           1
-#define OCF0B                           2
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1                           _SFR_IO8(0x16)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR1 {
-        unsigned int tov1 : 1;	/* Timer/Counter1 Overflow Flag */
-        unsigned int ocf1a : 1;	/* Timer/Counter1 Output Compare A Match Flag */
-        unsigned int ocf1b : 1;	/* Timer/Counter1 Output Compare B Match Flag */
-        unsigned int ocf1c : 1;	/* Timer/Counter1 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf1 : 1;	/* Timer/Counter1 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR1 */
-
-#define TOV1                            0
-#define OCF1A                           1
-#define OCF1B                           2
-#define OCF1C                           3
-#define ICF1                            5
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR2                           _SFR_IO8(0x17)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR2 {
-        unsigned int tov2 : 1;	/* Timer/Counter2 Overflow Flag */
-        unsigned int ocf2a : 1;	/* Output Compare Flag 2 A */
-        unsigned int ocf2b : 1;	/* Output Compare Flag 2 B */
-        unsigned int : 5;
-};
-
-#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR2 */
-
-#define TOV2                            0
-#define OCF2A                           1
-#define OCF2B                           2
-
-/* Timer/Counter3 Interrupt Flag Register */
-#define TIFR3                           _SFR_IO8(0x18)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR3 {
-        unsigned int tov3 : 1;	/* Timer/Counter3 Overflow Flag */
-        unsigned int ocf3a : 1;	/* Timer/Counter3 Output Compare A Match Flag */
-        unsigned int ocf3b : 1;	/* Timer/Counter3 Output Compare B Match Flag */
-        unsigned int ocf3c : 1;	/* Timer/Counter3 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf3 : 1;	/* Timer/Counter3 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR3 */
-
-#define TOV3                            0
-#define OCF3A                           1
-#define OCF3B                           2
-#define OCF3C                           3
-#define ICF3                            5
-
-/* Timer/Counter4 Interrupt Flag Register */
-#define TIFR4                           _SFR_IO8(0x19)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR4 {
-        unsigned int tov4 : 1;	/* Timer/Counter4 Overflow Flag */
-        unsigned int ocf4a : 1;	/* Timer/Counter4 Output Compare A Match Flag */
-        unsigned int ocf4b : 1;	/* Timer/Counter4 Output Compare B Match Flag */
-        unsigned int ocf4c : 1;	/* Timer/Counter4 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf4 : 1;	/* Timer/Counter4 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR4 */
-
-#define TOV4                            0
-#define OCF4A                           1
-#define OCF4B                           2
-#define OCF4C                           3
-#define ICF4                            5
-
-/* Timer/Counter5 Interrupt Flag Register */
-#define TIFR5                           _SFR_IO8(0x1A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR5 {
-        unsigned int tov5 : 1;	/* Timer/Counter5 Overflow Flag */
-        unsigned int ocf5a : 1;	/* Timer/Counter5 Output Compare A Match Flag */
-        unsigned int ocf5b : 1;	/* Timer/Counter5 Output Compare B Match Flag */
-        unsigned int ocf5c : 1;	/* Timer/Counter5 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf5 : 1;	/* Timer/Counter5 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR5 */
-
-#define TOV5                            0
-#define OCF5A                           1
-#define OCF5B                           2
-#define OCF5C                           3
-#define ICF5                            5
-
-/* Pin Change Interrupt Flag Register */
-#define PCIFR                           _SFR_IO8(0x1B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCIFR {
-        unsigned int pcif : 3;	/* Pin Change Interrupt Flags */
-        unsigned int : 5;
-};
-
-#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCIFR */
-
-#define PCIF0                           0
-#define PCIF1                           1
-#define PCIF2                           2
-
-/* External Interrupt Flag Register */
-#define EIFR                            _SFR_IO8(0x1C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIFR {
-        unsigned int intf : 8;	/* External Interrupt Flag */
-};
-
-#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIFR */
-
-#define INTF0                           0
-#define INTF1                           1
-#define INTF2                           2
-#define INTF3                           3
-#define INTF4                           4
-#define INTF5                           5
-#define INTF6                           6
-#define INTF7                           7
-
-/* External Interrupt Mask Register */
-#define EIMSK                           _SFR_IO8(0x1D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIMSK {
-        unsigned int intm : 8;	/* External Interrupt Request Enable */
-};
-
-#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIMSK */
-
-#define INT0                            0
-#define INT1                            1
-#define INT2                            2
-#define INT3                            3
-#define INT4                            4
-#define INT5                            5
-#define INT6                            6
-#define INT7                            7
-
-/* General Purpose IO Register 0 */
-#define GPIOR0                          _SFR_IO8(0x1E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR0 {
-        unsigned int gpior00 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior01 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior02 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior03 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior04 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior05 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior06 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior07 : 1;	/* General Purpose I/O Register 0 Value */
-};
-
-#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR0 */
-
-#define GPIOR00                         0
-#define GPIOR01                         1
-#define GPIOR02                         2
-#define GPIOR03                         3
-#define GPIOR04                         4
-#define GPIOR05                         5
-#define GPIOR06                         6
-#define GPIOR07                         7
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* EEPROM Control Register */
-#define EECR                            _SFR_IO8(0x1F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EECR {
-        unsigned int eere : 1;	/* EEPROM Read Enable */
-        unsigned int eepe : 1;	/* EEPROM Programming Enable */
-        unsigned int eempe : 1;	/* EEPROM Master Write Enable */
-        unsigned int eerie : 1;	/* EEPROM Ready Interrupt Enable */
-        unsigned int eepm : 2;	/* EEPROM Programming Mode */
-        unsigned int : 2;
-};
-
-#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EECR */
-
-#define EERE                            0
-#define EEPE                            1
-#define EEMPE                           2
-#define EERIE                           3
-#define EEPM0                           4
-#define EEPM1                           5
-
-/* EEPROM Data Register */
-#define EEDR                            _SFR_IO8(0x20)
-
-  /* EEDR */
-
-#define EEDR0                           0
-#define EEDR1                           1
-#define EEDR2                           2
-#define EEDR3                           3
-#define EEDR4                           4
-#define EEDR5                           5
-#define EEDR6                           6
-#define EEDR7                           7
-
-/* EEPROM Address Register  Bytes */
-#define EEAR                            _SFR_IO16(0x21)
-#define EEARL                           _SFR_IO8(0x21)
-#define EEARH                           _SFR_IO8(0x22)
-
-/* General Timer/Counter Control Register */
-#define GTCCR                           _SFR_IO8(0x23)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GTCCR {
-        unsigned int psrsync : 1;	/* Prescaler Reset for Synchronous Timer/Counters */
-        unsigned int psrasy : 1;	/* Prescaler Reset Timer/Counter2 */
-        unsigned int : 5;
-        unsigned int tsm : 1;	/* Timer/Counter Synchronization Mode */
-};
-
-#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GTCCR */
-
-#define PSRSYNC                         0
-#define PSR10                           0
-#define PSRASY                          1
-#define PSR2                            1
-#define TSM                             7
-
-/* Timer/Counter0 Control Register A */
-#define TCCR0A                          _SFR_IO8(0x24)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0A {
-        unsigned int wgm0 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com0b : 2;	/* Compare Match Output B Mode */
-        unsigned int com0a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0A */
-
-#define WGM00                           0
-#define WGM01                           1
-#define COM0B0                          4
-#define COM0B1                          5
-#define COM0A0                          6
-#define COM0A1                          7
-
-/* Timer/Counter0 Control Register B */
-#define TCCR0B                          _SFR_IO8(0x25)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0B {
-        unsigned int cs0 : 3;	/* Clock Select */
-        unsigned int wgm02 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc0b : 1;	/* Force Output Compare B */
-        unsigned int foc0a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0B */
-
-#define CS00                            0
-#define CS01                            1
-#define CS02                            2
-#define WGM02                           3
-#define FOC0B                           6
-#define FOC0A                           7
-
-/* Timer/Counter0 Register */
-#define TCNT0                           _SFR_IO8(0x26)
-
-  /* TCNT0 */
-
-#define TCNT0_0                         0
-#define TCNT0_1                         1
-#define TCNT0_2                         2
-#define TCNT0_3                         3
-#define TCNT0_4                         4
-#define TCNT0_5                         5
-#define TCNT0_6                         6
-#define TCNT0_7                         7
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0A                           _SFR_IO8(0x27)
-
-  /* OCR0A */
-
-#define OCR0A_0                         0
-#define OCR0A_1                         1
-#define OCR0A_2                         2
-#define OCR0A_3                         3
-#define OCR0A_4                         4
-#define OCR0A_5                         5
-#define OCR0A_6                         6
-#define OCR0A_7                         7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B                           _SFR_IO8(0x28)
-
-  /* OCR0B */
-
-#define OCR0B_0                         0
-#define OCR0B_1                         1
-#define OCR0B_2                         2
-#define OCR0B_3                         3
-#define OCR0B_4                         4
-#define OCR0B_5                         5
-#define OCR0B_6                         6
-#define OCR0B_7                         7
-
-/* General Purpose IO Register 1 */
-#define GPIOR1                          _SFR_IO8(0x2A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR1 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 1 Value */
-};
-
-#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR1 */
-
-#define GPIOR10                         0
-#define GPIOR11                         1
-#define GPIOR12                         2
-#define GPIOR13                         3
-#define GPIOR14                         4
-#define GPIOR15                         5
-#define GPIOR16                         6
-#define GPIOR17                         7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2                          _SFR_IO8(0x2B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR2 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 2 Value */
-};
-
-#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR2 */
-
-#define GPIOR20                         0
-#define GPIOR21                         1
-#define GPIOR22                         2
-#define GPIOR23                         3
-#define GPIOR24                         4
-#define GPIOR25                         5
-#define GPIOR26                         6
-#define GPIOR27                         7
-
-/* SPI Control Register */
-#define SPCR                            _SFR_IO8(0x2C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPCR {
-        unsigned int spr : 2;	/* SPI Clock Rate Select 1 and 0 */
-        unsigned int cpha : 1;	/* Clock Phase */
-        unsigned int cpol : 1;	/* Clock polarity */
-        unsigned int mstr : 1;	/* Master/Slave Select */
-        unsigned int dord : 1;	/* Data Order */
-        unsigned int spe : 1;	/* SPI Enable */
-        unsigned int spie : 1;	/* SPI Interrupt Enable */
-};
-
-#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPCR */
-
-#define SPR0                            0
-#define SPR1                            1
-#define CPHA                            2
-#define CPOL                            3
-#define MSTR                            4
-#define DORD                            5
-#define SPE                             6
-#define SPIE                            7
-
-/* SPI Status Register */
-#define SPSR                            _SFR_IO8(0x2D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPSR {
-        unsigned int spi2x : 1;	/* Double SPI Speed Bit */
-        unsigned int : 5;
-        unsigned int wcol : 1;	/* Write Collision Flag */
-        unsigned int spif : 1;	/* SPI Interrupt Flag */
-};
-
-#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPSR */
-
-#define SPI2X                           0
-#define WCOL                            6
-#define SPIF                            7
-
-/* SPI Data Register */
-#define SPDR                            _SFR_IO8(0x2E)
-
-  /* SPDR */
-
-#define SPDR0                           0
-#define SPDR1                           1
-#define SPDR2                           2
-#define SPDR3                           3
-#define SPDR4                           4
-#define SPDR5                           5
-#define SPDR6                           6
-#define SPDR7                           7
-
-/* Analog Comparator Control And Status Register */
-#define ACSR                            _SFR_IO8(0x30)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ACSR {
-        unsigned int acis : 2;	/* Analog Comparator Interrupt Mode Select */
-        unsigned int acic : 1;	/* Analog Comparator Input Capture Enable */
-        unsigned int acie : 1;	/* Analog Comparator Interrupt Enable */
-        unsigned int aci : 1;	/* Analog Comparator Interrupt Flag */
-        unsigned int aco : 1;	/* Analog Compare Output */
-        unsigned int acbg : 1;	/* Analog Comparator Bandgap Select */
-        unsigned int acd : 1;	/* Analog Comparator Disable */
-};
-
-#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ACSR */
-
-#define ACIS0                           0
-#define ACIS1                           1
-#define ACIC                            2
-#define ACIE                            3
-#define ACI                             4
-#define ACO                             5
-#define ACBG                            6
-#define ACD                             7
-
-/* On-Chip Debug Register */
-#define OCDR                            _SFR_IO8(0x31)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OCDR {
-        unsigned int ocdr : 8;	/* On-Chip Debug Register Data */
-};
-
-#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OCDR */
-
-#define OCDR0                           0
-#define OCDR1                           1
-#define OCDR2                           2
-#define OCDR3                           3
-#define OCDR4                           4
-#define OCDR5                           5
-#define OCDR6                           6
-#define OCDR7                           7
-#define IDRD                            7
-
-/* Sleep Mode Control Register */
-#define SMCR                            _SFR_IO8(0x33)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SMCR {
-        unsigned int se : 1;	/* Sleep Enable */
-        unsigned int sm : 3;	/* Sleep Mode Select bits */
-        unsigned int : 4;
-};
-
-#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SMCR */
-
-#define SE                              0
-#define SM0                             1
-#define SM1                             2
-#define SM2                             3
-
-/* MCU Status Register */
-#define MCUSR                           _SFR_IO8(0x34)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUSR {
-        unsigned int porf : 1;	/* Power-on Reset Flag */
-        unsigned int extrf : 1;	/* External Reset Flag */
-        unsigned int borf : 1;	/* Brown-out Reset Flag */
-        unsigned int wdrf : 1;	/* Watchdog Reset Flag */
-        unsigned int jtrf : 1;	/* JTAG Reset Flag */
-        unsigned int : 3;
-};
-
-#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUSR */
-
-#define PORF                            0
-#define EXTRF                           1
-#define BORF                            2
-#define WDRF                            3
-#define JTRF                            4
-
-/* MCU Control Register */
-#define MCUCR                           _SFR_IO8(0x35)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUCR {
-        unsigned int ivce : 1;	/* Interrupt Vector Change Enable */
-        unsigned int ivsel : 1;	/* Interrupt Vector Select */
-        unsigned int : 2;
-        unsigned int pud : 1;	/* Pull-up Disable */
-        unsigned int : 2;
-        unsigned int jtd : 1;	/* JTAG Interface Disable */
-};
-
-#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUCR */
-
-#define IVCE                            0
-#define IVSEL                           1
-#define PUD                             4
-#define JTD                             7
-
-/* Store Program Memory Control Register */
-#define SPMCSR                          _SFR_IO8(0x37)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPMCSR {
-        unsigned int spmen : 1;	/* Store Program Memory Enable */
-        unsigned int pgers : 1;	/* Page Erase */
-        unsigned int pgwrt : 1;	/* Page Write */
-        unsigned int blbset : 1;	/* Boot Lock Bit Set */
-        unsigned int rwwsre : 1;	/* Read While Write Section Read Enable */
-        unsigned int sigrd : 1;	/* Signature Row Read */
-        unsigned int rwwsb : 1;	/* Read While Write Section Busy */
-        unsigned int spmie : 1;	/* SPM Interrupt Enable */
-};
-
-#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPMCSR */
-
-#define SPMEN                           0
-#define PGERS                           1
-#define PGWRT                           2
-#define BLBSET                          3
-#define RWWSRE                          4
-#define SIGRD                           5
-#define RWWSB                           6
-#define SPMIE                           7
-
-/* Extended Z-pointer Register for ELPM/SPM */
-#define RAMPZ                           _SFR_IO8(0x3B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RAMPZ {
-        unsigned int rampz : 2;	/* Extended Z-Pointer Value */
-        unsigned int : 6;
-};
-
-#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ)
-
-#endif /* __ASSEMBLER__ */
-
-  /* RAMPZ */
-
-#define RAMPZ0                          0
-#define RAMPZ1                          1
-
-/* Extended Indirect Register */
-#define EIND                            _SFR_IO8(0x3C)
-
-  /* EIND */
-
-#define EIND0                           0
-
-/* Stack Pointer */
-#define SP                              _SFR_IO16(0x3D)
-#define SPL                             _SFR_IO8(0x3D)
-#define SPH                             _SFR_IO8(0x3E)
-
-/* Status Register */
-#define SREG                            _SFR_IO8(0x3F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SREG {
-        unsigned int c : 1;	/* Carry Flag */
-        unsigned int z : 1;	/* Zero Flag */
-        unsigned int n : 1;	/* Negative Flag */
-        unsigned int v : 1;	/* Two's Complement Overflow Flag */
-        unsigned int s : 1;	/* Sign Bit */
-        unsigned int h : 1;	/* Half Carry Flag */
-        unsigned int t : 1;	/* Bit Copy Storage */
-        unsigned int i : 1;	/* Global Interrupt Enable */
-};
-
-#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SREG */
-
-#define SREG_C                          0
-#define SREG_Z                          1
-#define SREG_N                          2
-#define SREG_V                          3
-#define SREG_S                          4
-#define SREG_H                          5
-#define SREG_T                          6
-#define SREG_I                          7
-
-/* Watchdog Timer Control Register */
-#define WDTCSR                          _SFR_MEM8(0x60)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_WDTCSR {
-        unsigned int wdp : 3;	/* Watchdog Timer Prescaler Bits */
-        unsigned int wde : 1;	/* Watch Dog Enable */
-        unsigned int wdce : 1;	/* Watchdog Change Enable */
-        unsigned int : 1;
-        unsigned int wdie : 1;	/* Watchdog Timeout Interrupt Enable */
-        unsigned int wdif : 1;	/* Watchdog Timeout Interrupt Flag */
-};
-
-#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* WDTCSR */
-
-#define WDP0                            0
-#define WDP1                            1
-#define WDP2                            2
-#define WDE                             3
-#define WDCE                            4
-#define WDP3                            5
-#define WDIE                            6
-#define WDIF                            7
-
-/* Clock Prescale Register */
-#define CLKPR                           _SFR_MEM8(0x61)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CLKPR {
-        unsigned int clkps : 4;	/* Clock Prescaler Select Bits */
-        unsigned int : 3;
-        unsigned int clkpce : 1;	/* Clock Prescaler Change Enable */
-};
-
-#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CLKPR */
-
-#define CLKPS0                          0
-#define CLKPS1                          1
-#define CLKPS2                          2
-#define CLKPS3                          3
-#define CLKPCE                          7
-
-/* Power Reduction Register 2 */
-#define PRR2                            _SFR_MEM8(0x63)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR2 {
-        unsigned int prram : 4;	/* Power Reduction SRAMs */
-        unsigned int : 4;
-};
-
-#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR2 */
-
-#define PRRAM0                          0
-#define PRRAM1                          1
-#define PRRAM2                          2
-#define PRRAM3                          3
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
+#define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
+#define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
+#define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
+#define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
+#define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
+#define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
+#define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE7  7
+#define PORTE6  6
+#define PORTE5  5
+#define PORTE4  4
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
+#define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
+#define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
+#define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
+#define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
+#define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
+#define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
+#define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PORTF7  7
+#define PORTF6  6
+#define PORTF5  5
+#define PORTF4  4
+#define PORTF3  3
+#define PORTF2  2
+#define PORTF1  1
+#define PORTF0  0
+
+#define PING    _SFR_IO8(0x12)
+#define PING7   7
+#define PING6   6
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDRG7   7
+// Inserted "DDG7" from "DDRG7" due to compatibility
+#define DDG7    7
+#define DDRG6   6
+// Inserted "DDG6" from "DDRG6" due to compatibility
+#define DDG6    6
+#define DDRG5   5
+// Inserted "DDG5" from "DDRG5" due to compatibility
+#define DDG5    5
+#define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
+#define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
+#define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
+#define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
+#define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PORTG7  7
+#define PORTG6  6
+#define PORTG5  5
+#define PORTG4  4
+#define PORTG3  3
+#define PORTG2  2
+#define PORTG1  1
+#define PORTG0  0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define OCF1C   3
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+#define Res0    3
+#define Res1    4
+#define Res2    5
+#define Res3    6
+#define Res4    7
+
+#define TIFR3   _SFR_IO8(0x18)
+#define TOV3    0
+#define OCF3A   1
+#define OCF3B   2
+#define OCF3C   3
+#define ICF3    5
+
+#define TIFR4   _SFR_IO8(0x19)
+#define TOV4    0
+#define OCF4A   1
+#define OCF4B   2
+#define OCF4C   3
+#define ICF4    5
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define TOV5    0
+#define OCF5A   1
+#define OCF5B   2
+#define OCF5C   3
+#define ICF5    5
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+#define INTF2   2
+#define INTF3   3
+#define INTF4   4
+#define INTF5   5
+#define INTF6   6
+#define INTF7   7
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+#define INT2    2
+#define INT3    3
+#define INT4    4
+#define INT5    5
+#define INT6    6
+#define INT7    7
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define PSRASY  1
+#define TSM     7
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define OCDR    _SFR_IO8(0x31)
+#define OCDR0   0
+#define OCDR1   1
+#define OCDR2   2
+#define OCDR3   3
+#define OCDR4   4
+#define OCDR5   5
+#define OCDR6   6
+#define OCDR7   7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0x3B)
+#define RAMPZ0  0
+#define RAMPZ1  1
+
+#define EIND    _SFR_IO8(0x3C)
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62] */
+
+#define PRR2    _SFR_MEM8(0x63)
+#define PRRAM0  0
+#define PRRAM1  1
+#define PRRAM2  2
+#define PRRAM3  3
 
 #define __AVR_HAVE_PRR2	((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3))
 #define __AVR_HAVE_PRR2_PRRAM0
@@ -1245,36 +613,15 @@
 #define __AVR_HAVE_PRR2_PRRAM2
 #define __AVR_HAVE_PRR2_PRRAM3
 
-/* Power Reduction Register0 */
-#define PRR0                            _SFR_MEM8(0x64)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR0 {
-        unsigned int pradc : 1;	/* Power Reduction ADC */
-        unsigned int prusart0 : 1;	/* Power Reduction USART */
-        unsigned int prspi : 1;	/* Power Reduction Serial Peripheral Interface */
-        unsigned int prtim1 : 1;	/* Power Reduction Timer/Counter1 */
-        unsigned int prpga : 1;	/* Power Reduction PGA */
-        unsigned int prtim0 : 1;	/* Power Reduction Timer/Counter0 */
-        unsigned int prtim2 : 1;	/* Power Reduction Timer/Counter2 */
-        unsigned int prtwi : 1;	/* Power Reduction TWI */
-};
-
-#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR0 */
-
-#define PRADC                           0
-#define PRUSART0                        1
-#define PRSPI                           2
-#define PRTIM1                          3
-#define PRPGA                           4
-#define PRTIM0                          5
-#define PRTIM2                          6
-#define PRTWI                           7
+#define PRR0    _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRPGA   4
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
 
 #define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
 #define __AVR_HAVE_PRR0_PRADC
@@ -1286,32 +633,13 @@
 #define __AVR_HAVE_PRR0_PRTIM2
 #define __AVR_HAVE_PRR0_PRTWI
 
-/* Power Reduction Register 1 */
-#define PRR1                            _SFR_MEM8(0x65)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR1 {
-        unsigned int prusart1 : 1;	/* Power Reduction USART1 */
-        unsigned int : 2;
-        unsigned int prtim3 : 1;	/* Power Reduction Timer/Counter3 */
-        unsigned int prtim4 : 1;	/* Power Reduction Timer/Counter4 */
-        unsigned int prtim5 : 1;	/* Power Reduction Timer/Counter5 */
-        unsigned int prtrx24 : 1;	/* Power Reduction Transceiver */
-        unsigned int : 1;
-};
-
-#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR1 */
-
-#define PRUSART1                        0
-#define PRTIM3                          3
-#define PRTIM4                          4
-#define PRTIM5                          5
-#define PRTRX24                         6
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSART1 0
+#define PRTIM3  3
+#define PRTIM4  4
+#define PRTIM5  5
+#define PRTRX24 6
+#define Res     7
 
 #define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24))
 #define __AVR_HAVE_PRR1_PRUSART1
@@ -1320,5056 +648,2070 @@
 #define __AVR_HAVE_PRR1_PRTIM5
 #define __AVR_HAVE_PRR1_PRTRX24
 
-/* Oscillator Calibration Value */
-#define OSCCAL                          _SFR_MEM8(0x66)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OSCCAL {
-        unsigned int cal : 8;	/* Oscillator Calibration Tuning Value */
-};
-
-#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OSCCAL */
-
-#define CAL0                            0
-#define CAL1                            1
-#define CAL2                            2
-#define CAL3                            3
-#define CAL4                            4
-#define CAL5                            5
-#define CAL6                            6
-#define CAL7                            7
-
-/* Reference Voltage Calibration Register */
-#define BGCR                            _SFR_MEM8(0x67)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BGCR {
-        unsigned int bgcal : 3;	/* Coarse Calibration Bits */
-        unsigned int bgcal_fine : 4;	/* Fine Calibration Bits */
-        unsigned int : 1;
-};
-
-#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* BGCR */
-
-#define BGCAL0                          0
-#define BGCAL1                          1
-#define BGCAL2                          2
-#define BGCAL_FINE0                     3
-#define BGCAL_FINE1                     4
-#define BGCAL_FINE2                     5
-#define BGCAL_FINE3                     6
-
-/* Pin Change Interrupt Control Register */
-#define PCICR                           _SFR_MEM8(0x68)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCICR {
-        unsigned int pcie : 3;	/* Pin Change Interrupt Enables */
-        unsigned int : 5;
-};
-
-#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCICR */
-
-#define PCIE0                           0
-#define PCIE1                           1
-#define PCIE2                           2
-
-/* External Interrupt Control Register A */
-#define EICRA                           _SFR_MEM8(0x69)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRA {
-        unsigned int isc0 : 2;	/* External Interrupt 0 Sense Control Bit */
-        unsigned int isc1 : 2;	/* External Interrupt 1 Sense Control Bit */
-        unsigned int isc2 : 2;	/* External Interrupt 2 Sense Control Bit */
-        unsigned int isc3 : 2;	/* External Interrupt 3 Sense Control Bit */
-};
-
-#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRA */
-
-#define ISC00                           0
-#define ISC01                           1
-#define ISC10                           2
-#define ISC11                           3
-#define ISC20                           4
-#define ISC21                           5
-#define ISC30                           6
-#define ISC31                           7
-
-/* External Interrupt Control Register B */
-#define EICRB                           _SFR_MEM8(0x6A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRB {
-        unsigned int isc4 : 2;	/* External Interrupt 4 Sense Control Bit */
-        unsigned int isc5 : 2;	/* External Interrupt 5 Sense Control Bit */
-        unsigned int isc6 : 2;	/* External Interrupt 6 Sense Control Bit */
-        unsigned int isc7 : 2;	/* External Interrupt 7 Sense Control Bit */
-};
-
-#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRB */
-
-#define ISC40                           0
-#define ISC41                           1
-#define ISC50                           2
-#define ISC51                           3
-#define ISC60                           4
-#define ISC61                           5
-#define ISC70                           6
-#define ISC71                           7
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0                          _SFR_MEM8(0x6B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK0 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK0_struct _SFR_MEM8_STRUCT(0x6b, struct __reg_PCMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK0 */
-
-#define PCINT0                          0
-#define PCINT1                          1
-#define PCINT2                          2
-#define PCINT3                          3
-#define PCINT4                          4
-#define PCINT5                          5
-#define PCINT6                          6
-#define PCINT7                          7
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1                          _SFR_MEM8(0x6C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK1 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK1 */
-
-#define PCINT8                          0
-#define PCINT9                          1
-#define PCINT10                         2
-#define PCINT11                         3
-#define PCINT12                         4
-#define PCINT13                         5
-#define PCINT14                         6
-#define PCINT15                         7
-
-/* Pin Change Mask Register 2 */
-#define PCMSK2                          _SFR_MEM8(0x6D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK2 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK2 */
-
-#define PCINT16                         0
-#define PCINT17                         1
-#define PCINT18                         2
-#define PCINT19                         3
-#define PCINT20                         4
-#define PCINT21                         5
-#define PCINT22                         6
-#define PCINT23                         7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0                          _SFR_MEM8(0x6E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK0 {
-        unsigned int toie0 : 1;	/* Timer/Counter0 Overflow Interrupt Enable */
-        unsigned int ocie0a : 1;	/* Timer/Counter0 Output Compare Match A Interrupt Enable */
-        unsigned int ocie0b : 1;	/* Timer/Counter0 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK0 */
-
-#define TOIE0                           0
-#define OCIE0A                          1
-#define OCIE0B                          2
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1                          _SFR_MEM8(0x6F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK1 {
-        unsigned int toie1 : 1;	/* Timer/Counter1 Overflow Interrupt Enable */
-        unsigned int ocie1a : 1;	/* Timer/Counter1 Output Compare A Match Interrupt Enable */
-        unsigned int ocie1b : 1;	/* Timer/Counter1 Output Compare B Match Interrupt Enable */
-        unsigned int ocie1c : 1;	/* Timer/Counter1 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie1 : 1;	/* Timer/Counter1 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK1 */
+#define OSCCAL  _SFR_MEM8(0x66)
+#define CAL0    0
+#define CAL1    1
+#define CAL2    2
+#define CAL3    3
+#define CAL4    4
+#define CAL5    5
+#define CAL6    6
+#define CAL7    7
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+#define BGCR    _SFR_MEM8(0x67)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL_FINE0 3
+#define BGCAL_FINE1 4
+#define BGCAL_FINE2 5
+#define BGCAL_FINE3 6
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+#define ISC20   4
+#define ISC21   5
+#define ISC30   6
+#define ISC31   7
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC40   0
+#define ISC41   1
+#define ISC50   2
+#define ISC51   3
+#define ISC60   4
+#define ISC61   5
+#define ISC70   6
+#define ISC71   7
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define OCIE1C  3
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define TOIE3   0
+#define OCIE3A  1
+#define OCIE3B  2
+#define OCIE3C  3
+#define ICIE3   5
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define TOIE4   0
+#define OCIE4A  1
+#define OCIE4B  2
+#define OCIE4C  3
+#define ICIE4   5
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define TOIE5   0
+#define OCIE5A  1
+#define OCIE5B  2
+#define OCIE5C  3
+#define ICIE5   5
+
+/* Reserved [0x74] */
+
+#define NEMCR   _SFR_MEM8(0x75)
+#define AEAM0   4
+#define AEAM1   5
+#define ENEAM   6
+
+/* Reserved [0x76] */
+
+#define ADCSRC  _SFR_MEM8(0x77)
+#define ADSUT0  0
+#define ADSUT1  1
+#define ADSUT2  2
+#define ADSUT3  3
+#define ADSUT4  4
+#define ADTHT0  6
+#define ADTHT1  7
 
-#define TOIE1                           0
-#define OCIE1A                          1
-#define OCIE1B                          2
-#define OCIE1C                          3
-#define ICIE1                           5
-
-/* Timer/Counter Interrupt Mask register */
-#define TIMSK2                          _SFR_MEM8(0x70)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK2 {
-        unsigned int toie2 : 1;	/* Timer/Counter2 Overflow Interrupt Enable */
-        unsigned int ocie2a : 1;	/* Timer/Counter2 Output Compare Match A Interrupt Enable */
-        unsigned int ocie2b : 1;	/* Timer/Counter2 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK2 */
-
-#define TOIE2                           0
-#define TOIE2A                          0
-#define OCIE2A                          1
-#define OCIE2B                          2
-
-/* Timer/Counter3 Interrupt Mask Register */
-#define TIMSK3                          _SFR_MEM8(0x71)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK3 {
-        unsigned int toie3 : 1;	/* Timer/Counter3 Overflow Interrupt Enable */
-        unsigned int ocie3a : 1;	/* Timer/Counter3 Output Compare A Match Interrupt Enable */
-        unsigned int ocie3b : 1;	/* Timer/Counter3 Output Compare B Match Interrupt Enable */
-        unsigned int ocie3c : 1;	/* Timer/Counter3 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie3 : 1;	/* Timer/Counter3 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK3 */
-
-#define TOIE3                           0
-#define OCIE3A                          1
-#define OCIE3B                          2
-#define OCIE3C                          3
-#define ICIE3                           5
-
-/* Timer/Counter4 Interrupt Mask Register */
-#define TIMSK4                          _SFR_MEM8(0x72)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK4 {
-        unsigned int toie4 : 1;	/* Timer/Counter4 Overflow Interrupt Enable */
-        unsigned int ocie4a : 1;	/* Timer/Counter4 Output Compare A Match Interrupt Enable */
-        unsigned int ocie4b : 1;	/* Timer/Counter4 Output Compare B Match Interrupt Enable */
-        unsigned int ocie4c : 1;	/* Timer/Counter4 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie4 : 1;	/* Timer/Counter4 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK4 */
-
-#define TOIE4                           0
-#define OCIE4A                          1
-#define OCIE4B                          2
-#define OCIE4C                          3
-#define ICIE4                           5
-
-/* Timer/Counter5 Interrupt Mask Register */
-#define TIMSK5                          _SFR_MEM8(0x73)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK5 {
-        unsigned int toie5 : 1;	/* Timer/Counter5 Overflow Interrupt Enable */
-        unsigned int ocie5a : 1;	/* Timer/Counter5 Output Compare A Match Interrupt Enable */
-        unsigned int ocie5b : 1;	/* Timer/Counter5 Output Compare B Match Interrupt Enable */
-        unsigned int ocie5c : 1;	/* Timer/Counter5 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie5 : 1;	/* Timer/Counter5 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK5 */
-
-#define TOIE5                           0
-#define OCIE5A                          1
-#define OCIE5B                          2
-#define OCIE5C                          3
-#define ICIE5                           5
-
-/* Flash Extended-Mode Control-Register */
-#define NEMCR                           _SFR_MEM8(0x75)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_NEMCR {
-        unsigned int : 4;
-        unsigned int aeam : 2;	/* Address for Extended Address Mode of Extra Rows */
-        unsigned int eneam : 1;	/* Enable Extended Address Mode for Extra Rows */
-        unsigned int : 1;
-};
-
-#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* NEMCR */
-
-#define AEAM0                           4
-#define AEAM1                           5
-#define ENEAM                           6
-
-/* The ADC Control and Status Register C */
-#define ADCSRC                          _SFR_MEM8(0x77)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRC {
-        unsigned int adsut : 5;	/* ADC Start-up Time */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int adtht : 2;	/* ADC Track-and-Hold Time */
-};
-
-#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRC */
-
-#define ADSUT0                          0
-#define ADSUT1                          1
-#define ADSUT2                          2
-#define ADSUT3                          3
-#define ADSUT4                          4
-#define ADTHT0                          6
-#define ADTHT1                          7
-
-/* ADC Data Register  Bytes */
+/* Combine ADCL and ADCH */
 #ifndef __ASSEMBLER__
-#define ADC                             _SFR_MEM16(0x78)
-#define ADCL                            _SFR_MEM8(0x78)
-#define ADCH                            _SFR_MEM8(0x79)
-#endif /* __ASSEMBLER__ */
-#define ADCW                            _SFR_MEM16(0x78)
-#define ADCWL                           _SFR_MEM8(0x78)
-#define ADCWH                           _SFR_MEM8(0x79)
-
-/* The ADC Control and Status Register A */
-#define ADCSRA                          _SFR_MEM8(0x7A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRA {
-        unsigned int adps : 3;	/* ADC  Prescaler Select Bits */
-        unsigned int adie : 1;	/* ADC Interrupt Enable */
-        unsigned int adif : 1;	/* ADC Interrupt Flag */
-        unsigned int adate : 1;	/* ADC Auto Trigger Enable */
-        unsigned int adsc : 1;	/* ADC Start Conversion */
-        unsigned int aden : 1;	/* ADC Enable */
-};
-
-#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRA */
-
-#define ADPS0                           0
-#define ADPS1                           1
-#define ADPS2                           2
-#define ADIE                            3
-#define ADIF                            4
-#define ADATE                           5
-#define ADSC                            6
-#define ADEN                            7
-
-/* ADC Control and Status Register B */
-#define ADCSRB                          _SFR_MEM8(0x7B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRB {
-        unsigned int adts : 3;	/* ADC Auto Trigger Source */
-        unsigned int mux5 : 1;	/* Analog Channel and Gain Selection Bits */
-        unsigned int acch : 1;	/* Analog Channel Change */
-        unsigned int refok : 1;	/* Reference Voltage OK */
-        unsigned int acme : 1;	/* Analog Comparator Multiplexer Enable */
-        unsigned int avddok : 1;	/* AVDD Supply Voltage OK */
-};
-
-#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRB */
-
-#define ADTS0                           0
-#define ADTS1                           1
-#define ADTS2                           2
-#define MUX5                            3
-#define ACCH                            4
-#define REFOK                           5
-#define ACME                            6
-#define AVDDOK                          7
-
-/* The ADC Multiplexer Selection Register */
-#define ADMUX                           _SFR_MEM8(0x7C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADMUX {
-        unsigned int mux : 5;	/* Analog Channel and Gain Selection Bits */
-        unsigned int adlar : 1;	/* ADC Left Adjust Result */
-        unsigned int refs : 2;	/* Reference Selection Bits */
-};
-
-#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADMUX */
-
-#define MUX0                            0
-#define MUX1                            1
-#define MUX2                            2
-#define MUX3                            3
-#define MUX4                            4
-#define ADLAR                           5
-#define REFS0                           6
-#define REFS1                           7
-
-/* Digital Input Disable Register 2 */
-#define DIDR2                           _SFR_MEM8(0x7D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR2 {
-        unsigned int adc8d : 1;	/* Reserved Bits */
-        unsigned int adc9d : 1;	/* Reserved Bits */
-        unsigned int adc10d : 1;	/* Reserved Bits */
-        unsigned int adc11d : 1;	/* Reserved Bits */
-        unsigned int adc12d : 1;	/* Reserved Bits */
-        unsigned int adc13d : 1;	/* Reserved Bits */
-        unsigned int adc14d : 1;	/* Reserved Bits */
-        unsigned int adc15d : 1;	/* Reserved Bits */
-};
-
-#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR2 */
-
-#define ADC8D                           0
-#define ADC9D                           1
-#define ADC10D                          2
-#define ADC11D                          3
-#define ADC12D                          4
-#define ADC13D                          5
-#define ADC14D                          6
-#define ADC15D                          7
-
-/* Digital Input Disable Register 0 */
-#define DIDR0                           _SFR_MEM8(0x7E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR0 {
-        unsigned int adc0d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc1d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc2d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc3d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc4d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc5d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc6d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc7d : 1;	/* Disable ADC7:0 Digital Input */
-};
-
-#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR0 */
-
-#define ADC0D                           0
-#define ADC1D                           1
-#define ADC2D                           2
-#define ADC3D                           3
-#define ADC4D                           4
-#define ADC5D                           5
-#define ADC6D                           6
-#define ADC7D                           7
-
-/* Digital Input Disable Register 1 */
-#define DIDR1                           _SFR_MEM8(0x7F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR1 {
-        unsigned int ain0d : 1;	/* AIN0 Digital Input Disable */
-        unsigned int ain1d : 1;	/* AIN1 Digital Input Disable */
-        unsigned int : 6;
-};
-
-#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR1 */
-
-#define AIN0D                           0
-#define AIN1D                           1
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A                          _SFR_MEM8(0x80)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1A {
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int com1c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com1b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com1a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1A */
-
-#define WGM10                           0
-#define WGM11                           1
-#define COM1C0                          2
-#define COM1C1                          3
-#define COM1B0                          4
-#define COM1B1                          5
-#define COM1A0                          6
-#define COM1A1                          7
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B                          _SFR_MEM8(0x81)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1B {
-        unsigned int cs1 : 3;	/* Clock Select */
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices1 : 1;	/* Input Capture 1 Edge Select */
-        unsigned int icnc1 : 1;	/* Input Capture 1 Noise Canceller */
-};
-
-#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1B */
-
-#define CS10                            0
-#define CS11                            1
-#define CS12                            2
-#define WGM12                           3
-#define WGM13                           4
-#define ICES1                           6
-#define ICNC1                           7
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C                          _SFR_MEM8(0x82)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1C {
-        unsigned int : 5;
-        unsigned int foc1c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc1b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc1a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1C */
-
-#define FOC1C                           5
-#define FOC1B                           6
-#define FOC1A                           7
-
-/* Timer/Counter1  Bytes */
-#define TCNT1                           _SFR_MEM16(0x84)
-#define TCNT1L                          _SFR_MEM8(0x84)
-#define TCNT1H                          _SFR_MEM8(0x85)
-
-/* Timer/Counter1 Input Capture Register  Bytes */
-#define ICR1                            _SFR_MEM16(0x86)
-#define ICR1L                           _SFR_MEM8(0x86)
-#define ICR1H                           _SFR_MEM8(0x87)
-
-/* Timer/Counter1 Output Compare Register A  Bytes */
-#define OCR1A                           _SFR_MEM16(0x88)
-#define OCR1AL                          _SFR_MEM8(0x88)
-#define OCR1AH                          _SFR_MEM8(0x89)
-
-/* Timer/Counter1 Output Compare Register B  Bytes */
-#define OCR1B                           _SFR_MEM16(0x8A)
-#define OCR1BL                          _SFR_MEM8(0x8A)
-#define OCR1BH                          _SFR_MEM8(0x8B)
-
-/* Timer/Counter1 Output Compare Register C  Bytes */
-#define OCR1C                           _SFR_MEM16(0x8C)
-#define OCR1CL                          _SFR_MEM8(0x8C)
-#define OCR1CH                          _SFR_MEM8(0x8D)
-
-/* Timer/Counter3 Control Register A */
-#define TCCR3A                          _SFR_MEM8(0x90)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3A {
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int com3c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com3b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com3a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3A */
-
-#define WGM30                           0
-#define WGM31                           1
-#define COM3C0                          2
-#define COM3C1                          3
-#define COM3B0                          4
-#define COM3B1                          5
-#define COM3A0                          6
-#define COM3A1                          7
-
-/* Timer/Counter3 Control Register B */
-#define TCCR3B                          _SFR_MEM8(0x91)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3B {
-        unsigned int cs3 : 3;	/* Clock Select */
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices3 : 1;	/* Input Capture 3 Edge Select */
-        unsigned int icnc3 : 1;	/* Input Capture 3 Noise Canceller */
-};
-
-#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3B */
-
-#define CS30                            0
-#define CS31                            1
-#define CS32                            2
-#define WGM32                           3
-#define WGM33                           4
-#define ICES3                           6
-#define ICNC3                           7
-
-/* Timer/Counter3 Control Register C */
-#define TCCR3C                          _SFR_MEM8(0x92)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3C {
-        unsigned int : 5;
-        unsigned int foc3c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc3b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc3a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3C */
-
-#define FOC3C                           5
-#define FOC3B                           6
-#define FOC3A                           7
-
-/* Timer/Counter3  Bytes */
-#define TCNT3                           _SFR_MEM16(0x94)
-#define TCNT3L                          _SFR_MEM8(0x94)
-#define TCNT3H                          _SFR_MEM8(0x95)
-
-/* Timer/Counter3 Input Capture Register  Bytes */
-#define ICR3                            _SFR_MEM16(0x96)
-#define ICR3L                           _SFR_MEM8(0x96)
-#define ICR3H                           _SFR_MEM8(0x97)
-
-/* Timer/Counter3 Output Compare Register A  Bytes */
-#define OCR3A                           _SFR_MEM16(0x98)
-#define OCR3AL                          _SFR_MEM8(0x98)
-#define OCR3AH                          _SFR_MEM8(0x99)
-
-/* Timer/Counter3 Output Compare Register B  Bytes */
-#define OCR3B                           _SFR_MEM16(0x9A)
-#define OCR3BL                          _SFR_MEM8(0x9A)
-#define OCR3BH                          _SFR_MEM8(0x9B)
-
-/* Timer/Counter3 Output Compare Register C  Bytes */
-#define OCR3C                           _SFR_MEM16(0x9C)
-#define OCR3CL                          _SFR_MEM8(0x9C)
-#define OCR3CH                          _SFR_MEM8(0x9D)
-
-/* Timer/Counter4 Control Register A */
-#define TCCR4A                          _SFR_MEM8(0xA0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4A {
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int com4c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com4b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com4a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4A */
-
-#define WGM40                           0
-#define WGM41                           1
-#define COM4C0                          2
-#define COM4C1                          3
-#define COM4B0                          4
-#define COM4B1                          5
-#define COM4A0                          6
-#define COM4A1                          7
-
-/* Timer/Counter4 Control Register B */
-#define TCCR4B                          _SFR_MEM8(0xA1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4B {
-        unsigned int cs4 : 3;	/* Clock Select */
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices4 : 1;	/* Input Capture 4 Edge Select */
-        unsigned int icnc4 : 1;	/* Input Capture 4 Noise Canceller */
-};
-
-#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4B */
-
-#define CS40                            0
-#define CS41                            1
-#define CS42                            2
-#define WGM42                           3
-#define WGM43                           4
-#define ICES4                           6
-#define ICNC4                           7
-
-/* Timer/Counter4 Control Register C */
-#define TCCR4C                          _SFR_MEM8(0xA2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4C {
-        unsigned int : 5;
-        unsigned int foc4c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc4b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc4a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4C */
-
-#define FOC4C                           5
-#define FOC4B                           6
-#define FOC4A                           7
-
-/* Timer/Counter4  Bytes */
-#define TCNT4                           _SFR_MEM16(0xA4)
-#define TCNT4L                          _SFR_MEM8(0xA4)
-#define TCNT4H                          _SFR_MEM8(0xA5)
-
-/* Timer/Counter4 Input Capture Register  Bytes */
-#define ICR4                            _SFR_MEM16(0xA6)
-#define ICR4L                           _SFR_MEM8(0xA6)
-#define ICR4H                           _SFR_MEM8(0xA7)
-
-/* Timer/Counter4 Output Compare Register A  Bytes */
-#define OCR4A                           _SFR_MEM16(0xA8)
-#define OCR4AL                          _SFR_MEM8(0xA8)
-#define OCR4AH                          _SFR_MEM8(0xA9)
-
-/* Timer/Counter4 Output Compare Register B  Bytes */
-#define OCR4B                           _SFR_MEM16(0xAA)
-#define OCR4BL                          _SFR_MEM8(0xAA)
-#define OCR4BH                          _SFR_MEM8(0xAB)
-
-/* Timer/Counter4 Output Compare Register C  Bytes */
-#define OCR4C                           _SFR_MEM16(0xAC)
-#define OCR4CL                          _SFR_MEM8(0xAC)
-#define OCR4CH                          _SFR_MEM8(0xAD)
-
-/* Timer/Counter2 Control Register A */
-#define TCCR2A                          _SFR_MEM8(0xB0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2A {
-        unsigned int wgm2 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com2b : 2;	/* Compare Match Output B Mode */
-        unsigned int com2a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2A */
-
-#define WGM20                           0
-#define WGM21                           1
-#define COM2B0                          4
-#define COM2B1                          5
-#define COM2A0                          6
-#define COM2A1                          7
-
-/* Timer/Counter2 Control Register B */
-#define TCCR2B                          _SFR_MEM8(0xB1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2B {
-        unsigned int cs2 : 3;	/* Clock Select */
-        unsigned int wgm22 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc2b : 1;	/* Force Output Compare B */
-        unsigned int foc2a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2B */
-
-#define CS20                            0
-#define CS21                            1
-#define CS22                            2
-#define WGM22                           3
-#define FOC2B                           6
-#define FOC2A                           7
-
-/* Timer/Counter2 */
-#define TCNT2                           _SFR_MEM8(0xB2)
-
-  /* TCNT2 */
-
-#define TCNT20                          0
-#define TCNT21                          1
-#define TCNT22                          2
-#define TCNT23                          3
-#define TCNT24                          4
-#define TCNT25                          5
-#define TCNT26                          6
-#define TCNT27                          7
-
-/* Timer/Counter2 Output Compare Register A */
-#define OCR2A                           _SFR_MEM8(0xB3)
-
-  /* OCR2A */
-
-#define OCR2A0                          0
-#define OCR2A1                          1
-#define OCR2A2                          2
-#define OCR2A3                          3
-#define OCR2A4                          4
-#define OCR2A5                          5
-#define OCR2A6                          6
-#define OCR2A7                          7
-
-/* Timer/Counter2 Output Compare Register B */
-#define OCR2B                           _SFR_MEM8(0xB4)
-
-  /* OCR2B */
-
-#define OCR2B0                          0
-#define OCR2B1                          1
-#define OCR2B2                          2
-#define OCR2B3                          3
-#define OCR2B4                          4
-#define OCR2B5                          5
-#define OCR2B6                          6
-#define OCR2B7                          7
-
-/* Asynchronous Status Register */
-#define ASSR                            _SFR_MEM8(0xB6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ASSR {
-        unsigned int tcr2bub : 1;	/* Timer/Counter2 Control Register B Update Busy */
-        unsigned int tcr2aub : 1;	/* Timer/Counter2 Control Register A Update Busy */
-        unsigned int ocr2bub : 1;	/* Timer/Counter2 Output Compare Register B Update Busy */
-        unsigned int ocr2aub : 1;	/* Timer/Counter2 Output Compare Register A Update Busy */
-        unsigned int tcn2ub : 1;	/* Timer/Counter2 Update Busy */
-        unsigned int as2 : 1;	/* Timer/Counter2 Asynchronous Mode */
-        unsigned int exclk : 1;	/* Enable External Clock Input */
-        unsigned int exclkamr : 1;	/* Enable External Clock Input for AMR */
-};
-
-#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ASSR */
-
-#define TCR2BUB                         0
-#define TCR2AUB                         1
-#define OCR2BUB                         2
-#define OCR2AUB                         3
-#define TCN2UB                          4
-#define AS2                             5
-#define EXCLK                           6
-#define EXCLKAMR                        7
-
-/* TWI Bit Rate Register */
-#define TWBR                            _SFR_MEM8(0xB8)
-
-  /* TWBR */
-
-#define TWBR0                           0
-#define TWBR1                           1
-#define TWBR2                           2
-#define TWBR3                           3
-#define TWBR4                           4
-#define TWBR5                           5
-#define TWBR6                           6
-#define TWBR7                           7
-
-/* TWI Status Register */
-#define TWSR                            _SFR_MEM8(0xB9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWSR {
-        unsigned int twps : 2;	/* TWI Prescaler Bits */
-        unsigned int : 1;
-        unsigned int tws : 5;	/* TWI Status */
-};
-
-#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWSR */
-
-#define TWPS0                           0
-#define TWPS1                           1
-#define TWS3                            3
-#define TWS4                            4
-#define TWS5                            5
-#define TWS6                            6
-#define TWS7                            7
-
-/* TWI (Slave) Address Register */
-#define TWAR                            _SFR_MEM8(0xBA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAR {
-        unsigned int twgce : 1;	/* TWI General Call Recognition Enable Bit */
-        unsigned int twa : 7;	/* TWI (Slave) Address */
-};
-
-#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAR */
-
-#define TWGCE                           0
-#define TWA0                            1
-#define TWA1                            2
-#define TWA2                            3
-#define TWA3                            4
-#define TWA4                            5
-#define TWA5                            6
-#define TWA6                            7
-
-/* TWI Data Register */
-#define TWDR                            _SFR_MEM8(0xBB)
-
-  /* TWDR */
-
-#define TWD0                            0
-#define TWD1                            1
-#define TWD2                            2
-#define TWD3                            3
-#define TWD4                            4
-#define TWD5                            5
-#define TWD6                            6
-#define TWD7                            7
-
-/* TWI Control Register */
-#define TWCR                            _SFR_MEM8(0xBC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWCR {
-        unsigned int twie : 1;	/* TWI Interrupt Enable */
-        unsigned int : 1;
-        unsigned int twen : 1;	/* TWI Enable Bit */
-        unsigned int twwc : 1;	/* TWI Write Collision Flag */
-        unsigned int twsto : 1;	/* TWI STOP Condition Bit */
-        unsigned int twsta : 1;	/* TWI START Condition Bit */
-        unsigned int twea : 1;	/* TWI Enable Acknowledge Bit */
-        unsigned int twint : 1;	/* TWI Interrupt Flag */
-};
-
-#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWCR */
-
-#define TWIE                            0
-#define TWEN                            2
-#define TWWC                            3
-#define TWSTO                           4
-#define TWSTA                           5
-#define TWEA                            6
-#define TWINT                           7
-
-/* TWI (Slave) Address Mask Register */
-#define TWAMR                           _SFR_MEM8(0xBD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAMR {
-        unsigned int : 1;
-        unsigned int twam : 7;	/* TWI Address Mask */
-};
-
-#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAMR */
-
-#define TWAM0                           1
-#define TWAMR0                          1
-#define TWAM1                           2
-#define TWAMR1                          2
-#define TWAM2                           3
-#define TWAMR2                          3
-#define TWAM3                           4
-#define TWAMR3                          4
-#define TWAM4                           5
-#define TWAMR4                          5
-#define TWAM5                           6
-#define TWAMR5                          6
-#define TWAM6                           7
-#define TWAMR6                          7
-
-/* Transceiver Interrupt Enable Register 1 */
-#define IRQ_MASK1                       _SFR_MEM8(0xBE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK1 {
-        unsigned int tx_start_en : 1;	/* Transmit Start Interrupt enable */
-        unsigned int maf_0_ami_en : 1;	/* Address Match Interrupt enable Address filter 0 */
-        unsigned int maf_1_ami_en : 1;	/* Address Match Interrupt enable Address filter 1 */
-        unsigned int maf_2_ami_en : 1;	/* Address Match Interrupt enable Address filter 2 */
-        unsigned int maf_3_ami_en : 1;	/* Address Match Interrupt enable Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_MASK1_struct _SFR_MEM8_STRUCT(0xbe, struct __reg_IRQ_MASK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK1 */
-
-#define TX_START_EN                     0
-#define MAF_0_AMI_EN                    1
-#define MAF_1_AMI_EN                    2
-#define MAF_2_AMI_EN                    3
-#define MAF_3_AMI_EN                    4
-
-/* Transceiver Interrupt Status Register 1 */
-#define IRQ_STATUS1                     _SFR_MEM8(0xBF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS1 {
-        unsigned int tx_start : 1;	/* Transmit Start Interrupt Status */
-        unsigned int maf_0_ami : 1;	/* Address Match Interrupt Status Address filter 0 */
-        unsigned int maf_1_ami : 1;	/* Address Match Interrupt Status Address filter 1 */
-        unsigned int maf_2_ami : 1;	/* Address Match Interrupt Status Address filter 2 */
-        unsigned int maf_3_ami : 1;	/* Address Match Interrupt Status Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_STATUS1_struct _SFR_MEM8_STRUCT(0xbf, struct __reg_IRQ_STATUS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS1 */
-
-#define TX_START                        0
-#define MAF_0_AMI                       1
-#define MAF_1_AMI                       2
-#define MAF_2_AMI                       3
-#define MAF_3_AMI                       4
-
-/* USART0 Control and Status Register A */
-#define UCSR0A                          _SFR_MEM8(0xC0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0A {
-        unsigned int mpcm0 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x0 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe0 : 1;	/* USART Parity Error */
-        unsigned int dor0 : 1;	/* Data OverRun */
-        unsigned int fe0 : 1;	/* Frame Error */
-        unsigned int udre0 : 1;	/* USART Data Register Empty */
-        unsigned int txc0 : 1;	/* USART Transmit Complete */
-        unsigned int rxc0 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0A */
-
-#define MPCM0                           0
-#define U2X0                            1
-#define UPE0                            2
-#define DOR0                            3
-#define FE0                             4
-#define UDRE0                           5
-#define TXC0                            6
-#define RXC0                            7
-
-/* USART0 Control and Status Register B */
-#define UCSR0B                          _SFR_MEM8(0xC1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0B {
-        unsigned int txb80 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb80 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz02 : 1;	/* Character Size */
-        unsigned int txen0 : 1;	/* Transmitter Enable */
-        unsigned int rxen0 : 1;	/* Receiver Enable */
-        unsigned int udrie0 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie0 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie0 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0B */
-
-#define TXB80                           0
-#define RXB80                           1
-#define UCSZ02                          2
-#define TXEN0                           3
-#define RXEN0                           4
-#define UDRIE0                          5
-#define TXCIE0                          6
-#define RXCIE0                          7
-
-/* USART0 Control and Status Register C */
-#define UCSR0C                          _SFR_MEM8(0xC2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0C {
-        unsigned int ucpol0 : 1;	/* Clock Polarity */
-        unsigned int ucsz0 : 2;	/* Character Size */
-        unsigned int ucpha0 : 1;	/* Clock Phase */
-        unsigned int udord0 : 1;	/* Data Order */
-        unsigned int usbs0 : 1;	/* Stop Bit Select */
-        unsigned int upm0 : 2;	/* Parity Mode */
-        unsigned int umsel0 : 2;	/* USART Mode Select */
-};
-
-#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0C */
-
-#define UCPOL0                          0
-#define UCPHA0                          1
-#define UCPHA0                          1
-#define UCSZ00                          1
-#define UDORD0                          2
-#define UDORD0                          2
-#define UCSZ01                          2
-#define USBS0                           3
-#define UPM00                           4
-#define UPM01                           5
-#define UMSEL00                         6
-#define UMSEL0                          6
-#define UMSEL01                         7
-#define UMSEL1                          7
-
-/* USART0 Baud Rate Register  Bytes */
-#define UBRR0                           _SFR_MEM16(0xC4)
-#define UBRR0L                          _SFR_MEM8(0xC4)
-#define UBRR0H                          _SFR_MEM8(0xC5)
-
-/* USART0 I/O Data Register */
-#define UDR0                            _SFR_MEM8(0xC6)
-
-  /* UDR0 */
-
-#define UDR00                           0
-#define UDR01                           1
-#define UDR02                           2
-#define UDR03                           3
-#define UDR04                           4
-#define UDR05                           5
-#define UDR06                           6
-#define UDR07                           7
-
-/* USART1 Control and Status Register A */
-#define UCSR1A                          _SFR_MEM8(0xC8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1A {
-        unsigned int mpcm1 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x1 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe1 : 1;	/* USART Parity Error */
-        unsigned int dor1 : 1;	/* Data OverRun */
-        unsigned int fe1 : 1;	/* Frame Error */
-        unsigned int udre1 : 1;	/* USART Data Register Empty */
-        unsigned int txc1 : 1;	/* USART Transmit Complete */
-        unsigned int rxc1 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1A */
-
-#define MPCM1                           0
-#define U2X1                            1
-#define UPE1                            2
-#define DOR1                            3
-#define FE1                             4
-#define UDRE1                           5
-#define TXC1                            6
-#define RXC1                            7
-
-/* USART1 Control and Status Register B */
-#define UCSR1B                          _SFR_MEM8(0xC9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1B {
-        unsigned int txb81 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb81 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz12 : 1;	/* Character Size */
-        unsigned int txen1 : 1;	/* Transmitter Enable */
-        unsigned int rxen1 : 1;	/* Receiver Enable */
-        unsigned int udrie1 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie1 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie1 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1B */
-
-#define TXB81                           0
-#define RXB81                           1
-#define UCSZ12                          2
-#define TXEN1                           3
-#define RXEN1                           4
-#define UDRIE1                          5
-#define TXCIE1                          6
-#define RXCIE1                          7
-
-/* USART1 Control and Status Register C */
-#define UCSR1C                          _SFR_MEM8(0xCA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1C {
-        unsigned int ucpol1 : 1;	/* Clock Polarity */
-        unsigned int ucsz1 : 2;	/* Character Size */
-        unsigned int ucpha1 : 1;	/* Clock Phase */
-        unsigned int udord1 : 1;	/* Data Order */
-        unsigned int usbs1 : 1;	/* Stop Bit Select */
-        unsigned int upm1 : 2;	/* Parity Mode */
-        unsigned int umsel1 : 2;	/* USART Mode Select */
-};
-
-#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1C */
-
-#define UCPOL1                          0
-#define UCPHA1                          1
-#define UCPHA1                          1
-#define UCSZ10                          1
-#define UDORD1                          2
-#define UDORD1                          2
-#define UCSZ11                          2
-#define USBS1                           3
-#define UPM10                           4
-#define UPM11                           5
-#define UMSEL10                         6
-#define UMSEL11                         7
-
-/* USART1 Baud Rate Register  Bytes */
-#define UBRR1                           _SFR_MEM16(0xCC)
-#define UBRR1L                          _SFR_MEM8(0xCC)
-#define UBRR1H                          _SFR_MEM8(0xCD)
-
-/* USART1 I/O Data Register */
-#define UDR1                            _SFR_MEM8(0xCE)
-
-  /* UDR1 */
-
-#define UDR10                           0
-#define UDR11                           1
-#define UDR12                           2
-#define UDR13                           3
-#define UDR14                           4
-#define UDR15                           5
-#define UDR16                           6
-#define UDR17                           7
-
-/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-#define SCRSTRLL                        _SFR_MEM8(0xD7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLL {
-        unsigned int scrstrll : 8;	/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-};
-
-#define SCRSTRLL_struct _SFR_MEM8_STRUCT(0xd7, struct __reg_SCRSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLL */
-
-#define SCRSTRLL0                       0
-#define SCRSTRLL1                       1
-#define SCRSTRLL2                       2
-#define SCRSTRLL3                       3
-#define SCRSTRLL4                       4
-#define SCRSTRLL5                       5
-#define SCRSTRLL6                       6
-#define SCRSTRLL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-#define SCRSTRLH                        _SFR_MEM8(0xD8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLH {
-        unsigned int scrstrlh : 8;	/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-};
-
-#define SCRSTRLH_struct _SFR_MEM8_STRUCT(0xd8, struct __reg_SCRSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLH */
-
-#define SCRSTRLH0                       0
-#define SCRSTRLH1                       1
-#define SCRSTRLH2                       2
-#define SCRSTRLH3                       3
-#define SCRSTRLH4                       4
-#define SCRSTRLH5                       5
-#define SCRSTRLH6                       6
-#define SCRSTRLH7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-#define SCRSTRHL                        _SFR_MEM8(0xD9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHL {
-        unsigned int scrstrhl : 8;	/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-};
-
-#define SCRSTRHL_struct _SFR_MEM8_STRUCT(0xd9, struct __reg_SCRSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHL */
-
-#define SCRSTRHL0                       0
-#define SCRSTRHL1                       1
-#define SCRSTRHL2                       2
-#define SCRSTRHL3                       3
-#define SCRSTRHL4                       4
-#define SCRSTRHL5                       5
-#define SCRSTRHL6                       6
-#define SCRSTRHL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-#define SCRSTRHH                        _SFR_MEM8(0xDA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHH {
-        unsigned int scrstrhh : 8;	/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-};
-
-#define SCRSTRHH_struct _SFR_MEM8_STRUCT(0xda, struct __reg_SCRSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHH */
-
-#define SCRSTRHH0                       0
-#define SCRSTRHH1                       1
-#define SCRSTRHH2                       2
-#define SCRSTRHH3                       3
-#define SCRSTRHH4                       4
-#define SCRSTRHH5                       5
-#define SCRSTRHH6                       6
-#define SCRSTRHH7                       7
-
-/* Symbol Counter Compare Source Register */
-#define SCCSR                           _SFR_MEM8(0xDB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCSR {
-        unsigned int sccs1 : 2;	/* Symbol Counter Compare Source select register for Compare Units */
-        unsigned int sccs2 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 2 */
-        unsigned int sccs3 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 3 */
-        unsigned int : 2;
-};
-
-#define SCCSR_struct _SFR_MEM8_STRUCT(0xdb, struct __reg_SCCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCSR */
-
-#define SCCS10                          0
-#define SCCS11                          1
-#define SCCS20                          2
-#define SCCS21                          3
-#define SCCS30                          4
-#define SCCS31                          5
-
-/* Symbol Counter Control Register 0 */
-#define SCCR0                           _SFR_MEM8(0xDC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR0 {
-        unsigned int sccmp : 3;	/* Symbol Counter Compare Unit 3 Mode select */
-        unsigned int sctse : 1;	/* Symbol Counter Automatic Timestamping enable */
-        unsigned int sccksel : 1;	/* Symbol Counter Clock Source select */
-        unsigned int scen : 1;	/* Symbol Counter enable */
-        unsigned int scmbts : 1;	/* Manual Beacon Timestamp */
-        unsigned int scres : 1;	/* Symbol Counter Synchronization */
-};
-
-#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR0 */
-
-#define SCCMP1                          0
-#define SCCMP2                          1
-#define SCCMP3                          2
-#define SCTSE                           3
-#define SCCKSEL                         4
-#define SCEN                            5
-#define SCMBTS                          6
-#define SCRES                           7
-
-/* Symbol Counter Control Register 1 */
-#define SCCR1                           _SFR_MEM8(0xDD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR1 {
-        unsigned int scenbo : 1;	/* Backoff Slot Counter enable */
-        unsigned int sceeclk : 1;	/* Enable External Clock Source on PG2 */
-        unsigned int scckdiv : 3;	/* Clock divider for synchronous clock source (16MHz Transceiver Clock) */
-        unsigned int scbtsm : 1;	/* Symbol Counter Beacon Timestamp Mask Register */
-        unsigned int : 2;
-};
-
-#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR1 */
-
-#define SCENBO                          0
-#define SCEECLK                         1
-#define SCCKDIV0                        2
-#define SCCKDIV1                        3
-#define SCCKDIV2                        4
-#define SCBTSM                          5
-
-/* Symbol Counter Status Register */
-#define SCSR                            _SFR_MEM8(0xDE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCSR {
-        unsigned int scbsy : 1;	/* Symbol Counter busy */
-        unsigned int : 7;
-};
-
-#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCSR */
-
-#define SCBSY                           0
-
-/* Symbol Counter Interrupt Mask Register */
-#define SCIRQM                          _SFR_MEM8(0xDF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQM {
-        unsigned int irqmcp : 3;	/* Symbol Counter Compare Match 3 IRQ enable */
-        unsigned int irqmof : 1;	/* Symbol Counter Overflow IRQ enable */
-        unsigned int irqmbo : 1;	/* Backoff Slot Counter IRQ enable */
-        unsigned int : 3;
-};
-
-#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQM */
-
-#define IRQMCP1                         0
-#define IRQMCP2                         1
-#define IRQMCP3                         2
-#define IRQMOF                          3
-#define IRQMBO                          4
-
-/* Symbol Counter Interrupt Status Register */
-#define SCIRQS                          _SFR_MEM8(0xE0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQS {
-        unsigned int irqscp : 3;	/* Compare Unit 3 Compare Match IRQ */
-        unsigned int irqsof : 1;	/* Symbol Counter Overflow IRQ */
-        unsigned int irqsbo : 1;	/* Backoff Slot Counter IRQ */
-        unsigned int : 3;
-};
-
-#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQS */
-
-#define IRQSCP1                         0
-#define IRQSCP2                         1
-#define IRQSCP3                         2
-#define IRQSOF                          3
-#define IRQSBO                          4
-
-/* Symbol Counter Register LL-Byte */
-#define SCCNTLL                         _SFR_MEM8(0xE1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLL {
-        unsigned int sccntll : 8;	/* Symbol Counter Register LL-Byte */
-};
-
-#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLL */
-
-#define SCCNTLL0                        0
-#define SCCNTLL1                        1
-#define SCCNTLL2                        2
-#define SCCNTLL3                        3
-#define SCCNTLL4                        4
-#define SCCNTLL5                        5
-#define SCCNTLL6                        6
-#define SCCNTLL7                        7
-
-/* Symbol Counter Register LH-Byte */
-#define SCCNTLH                         _SFR_MEM8(0xE2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLH {
-        unsigned int sccntlh : 8;	/* Symbol Counter Register LH-Byte */
-};
-
-#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLH */
-
-#define SCCNTLH0                        0
-#define SCCNTLH1                        1
-#define SCCNTLH2                        2
-#define SCCNTLH3                        3
-#define SCCNTLH4                        4
-#define SCCNTLH5                        5
-#define SCCNTLH6                        6
-#define SCCNTLH7                        7
-
-/* Symbol Counter Register HL-Byte */
-#define SCCNTHL                         _SFR_MEM8(0xE3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHL {
-        unsigned int sccnthl : 8;	/* Symbol Counter Register HL-Byte */
-};
-
-#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHL */
-
-#define SCCNTHL0                        0
-#define SCCNTHL1                        1
-#define SCCNTHL2                        2
-#define SCCNTHL3                        3
-#define SCCNTHL4                        4
-#define SCCNTHL5                        5
-#define SCCNTHL6                        6
-#define SCCNTHL7                        7
-
-/* Symbol Counter Register HH-Byte */
-#define SCCNTHH                         _SFR_MEM8(0xE4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHH {
-        unsigned int sccnthh : 8;	/* Symbol Counter Register HH-Byte */
-};
-
-#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHH */
-
-#define SCCNTHH0                        0
-#define SCCNTHH1                        1
-#define SCCNTHH2                        2
-#define SCCNTHH3                        3
-#define SCCNTHH4                        4
-#define SCCNTHH5                        5
-#define SCCNTHH6                        6
-#define SCCNTHH7                        7
-
-/* Symbol Counter Beacon Timestamp Register LL-Byte */
-#define SCBTSRLL                        _SFR_MEM8(0xE5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLL {
-        unsigned int scbtsrll : 8;	/* Symbol Counter Beacon Timestamp Register LL-Byte */
-};
-
-#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLL */
-
-#define SCBTSRLL0                       0
-#define SCBTSRLL1                       1
-#define SCBTSRLL2                       2
-#define SCBTSRLL3                       3
-#define SCBTSRLL4                       4
-#define SCBTSRLL5                       5
-#define SCBTSRLL6                       6
-#define SCBTSRLL7                       7
-
-/* Symbol Counter Beacon Timestamp Register LH-Byte */
-#define SCBTSRLH                        _SFR_MEM8(0xE6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLH {
-        unsigned int scbtsrlh : 8;	/* Symbol Counter Beacon Timestamp Register LH-Byte */
-};
-
-#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLH */
-
-#define SCBTSRLH0                       0
-#define SCBTSRLH1                       1
-#define SCBTSRLH2                       2
-#define SCBTSRLH3                       3
-#define SCBTSRLH4                       4
-#define SCBTSRLH5                       5
-#define SCBTSRLH6                       6
-#define SCBTSRLH7                       7
-
-/* Symbol Counter Beacon Timestamp Register HL-Byte */
-#define SCBTSRHL                        _SFR_MEM8(0xE7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHL {
-        unsigned int scbtsrhl : 8;	/* Symbol Counter Beacon Timestamp Register HL-Byte */
-};
-
-#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHL */
-
-#define SCBTSRHL0                       0
-#define SCBTSRHL1                       1
-#define SCBTSRHL2                       2
-#define SCBTSRHL3                       3
-#define SCBTSRHL4                       4
-#define SCBTSRHL5                       5
-#define SCBTSRHL6                       6
-#define SCBTSRHL7                       7
-
-/* Symbol Counter Beacon Timestamp Register HH-Byte */
-#define SCBTSRHH                        _SFR_MEM8(0xE8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHH {
-        unsigned int scbtsrhh : 8;	/* Symbol Counter Beacon Timestamp Register HH-Byte */
-};
-
-#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHH */
-
-#define SCBTSRHH0                       0
-#define SCBTSRHH1                       1
-#define SCBTSRHH2                       2
-#define SCBTSRHH3                       3
-#define SCBTSRHH4                       4
-#define SCBTSRHH5                       5
-#define SCBTSRHH6                       6
-#define SCBTSRHH7                       7
-
-/* Symbol Counter Frame Timestamp Register LL-Byte */
-#define SCTSRLL                         _SFR_MEM8(0xE9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLL {
-        unsigned int sctsrll : 8;	/* Symbol Counter Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLL */
-
-#define SCTSRLL0                        0
-#define SCTSRLL1                        1
-#define SCTSRLL2                        2
-#define SCTSRLL3                        3
-#define SCTSRLL4                        4
-#define SCTSRLL5                        5
-#define SCTSRLL6                        6
-#define SCTSRLL7                        7
-
-/* Symbol Counter Frame Timestamp Register LH-Byte */
-#define SCTSRLH                         _SFR_MEM8(0xEA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLH {
-        unsigned int sctsrlh : 8;	/* Symbol Counter Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLH */
-
-#define SCTSRLH0                        0
-#define SCTSRLH1                        1
-#define SCTSRLH2                        2
-#define SCTSRLH3                        3
-#define SCTSRLH4                        4
-#define SCTSRLH5                        5
-#define SCTSRLH6                        6
-#define SCTSRLH7                        7
-
-/* Symbol Counter Frame Timestamp Register HL-Byte */
-#define SCTSRHL                         _SFR_MEM8(0xEB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHL {
-        unsigned int sctsrhl : 8;	/* Symbol Counter Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHL */
-
-#define SCTSRHL0                        0
-#define SCTSRHL1                        1
-#define SCTSRHL2                        2
-#define SCTSRHL3                        3
-#define SCTSRHL4                        4
-#define SCTSRHL5                        5
-#define SCTSRHL6                        6
-#define SCTSRHL7                        7
-
-/* Symbol Counter Frame Timestamp Register HH-Byte */
-#define SCTSRHH                         _SFR_MEM8(0xEC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHH {
-        unsigned int sctsrhh : 8;	/* Symbol Counter Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHH */
-
-#define SCTSRHH0                        0
-#define SCTSRHH1                        1
-#define SCTSRHH2                        2
-#define SCTSRHH3                        3
-#define SCTSRHH4                        4
-#define SCTSRHH5                        5
-#define SCTSRHH6                        6
-#define SCTSRHH7                        7
-
-/* Symbol Counter Output Compare Register 3 LL-Byte */
-#define SCOCR3LL                        _SFR_MEM8(0xED)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LL {
-        unsigned int scocr3ll : 8;	/* Symbol Counter Output Compare Register 3 LL-Byte */
-};
-
-#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LL */
-
-#define SCOCR3LL0                       0
-#define SCOCR3LL1                       1
-#define SCOCR3LL2                       2
-#define SCOCR3LL3                       3
-#define SCOCR3LL4                       4
-#define SCOCR3LL5                       5
-#define SCOCR3LL6                       6
-#define SCOCR3LL7                       7
-
-/* Symbol Counter Output Compare Register 3 LH-Byte */
-#define SCOCR3LH                        _SFR_MEM8(0xEE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LH {
-        unsigned int scocr3lh : 8;	/* Symbol Counter Output Compare Register 3 LH-Byte */
-};
-
-#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LH */
-
-#define SCOCR3LH0                       0
-#define SCOCR3LH1                       1
-#define SCOCR3LH2                       2
-#define SCOCR3LH3                       3
-#define SCOCR3LH4                       4
-#define SCOCR3LH5                       5
-#define SCOCR3LH6                       6
-#define SCOCR3LH7                       7
-
-/* Symbol Counter Output Compare Register 3 HL-Byte */
-#define SCOCR3HL                        _SFR_MEM8(0xEF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HL {
-        unsigned int scocr3hl : 8;	/* Symbol Counter Output Compare Register 3 HL-Byte */
-};
-
-#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HL */
-
-#define SCOCR3HL0                       0
-#define SCOCR3HL1                       1
-#define SCOCR3HL2                       2
-#define SCOCR3HL3                       3
-#define SCOCR3HL4                       4
-#define SCOCR3HL5                       5
-#define SCOCR3HL6                       6
-#define SCOCR3HL7                       7
-
-/* Symbol Counter Output Compare Register 3 HH-Byte */
-#define SCOCR3HH                        _SFR_MEM8(0xF0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HH {
-        unsigned int scocr3hh : 8;	/* Symbol Counter Output Compare Register 3 HH-Byte */
-};
-
-#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HH */
-
-#define SCOCR3HH0                       0
-#define SCOCR3HH1                       1
-#define SCOCR3HH2                       2
-#define SCOCR3HH3                       3
-#define SCOCR3HH4                       4
-#define SCOCR3HH5                       5
-#define SCOCR3HH6                       6
-#define SCOCR3HH7                       7
-
-/* Symbol Counter Output Compare Register 2 LL-Byte */
-#define SCOCR2LL                        _SFR_MEM8(0xF1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LL {
-        unsigned int scocr2ll : 8;	/* Symbol Counter Output Compare Register 2 LL-Byte */
-};
-
-#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LL */
-
-#define SCOCR2LL0                       0
-#define SCOCR2LL1                       1
-#define SCOCR2LL2                       2
-#define SCOCR2LL3                       3
-#define SCOCR2LL4                       4
-#define SCOCR2LL5                       5
-#define SCOCR2LL6                       6
-#define SCOCR2LL7                       7
-
-/* Symbol Counter Output Compare Register 2 LH-Byte */
-#define SCOCR2LH                        _SFR_MEM8(0xF2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LH {
-        unsigned int scocr2lh : 8;	/* Symbol Counter Output Compare Register 2 LH-Byte */
-};
-
-#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LH */
-
-#define SCOCR2LH0                       0
-#define SCOCR2LH1                       1
-#define SCOCR2LH2                       2
-#define SCOCR2LH3                       3
-#define SCOCR2LH4                       4
-#define SCOCR2LH5                       5
-#define SCOCR2LH6                       6
-#define SCOCR2LH7                       7
-
-/* Symbol Counter Output Compare Register 2 HL-Byte */
-#define SCOCR2HL                        _SFR_MEM8(0xF3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HL {
-        unsigned int scocr2hl : 8;	/* Symbol Counter Output Compare Register 2 HL-Byte */
-};
-
-#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HL */
-
-#define SCOCR2HL0                       0
-#define SCOCR2HL1                       1
-#define SCOCR2HL2                       2
-#define SCOCR2HL3                       3
-#define SCOCR2HL4                       4
-#define SCOCR2HL5                       5
-#define SCOCR2HL6                       6
-#define SCOCR2HL7                       7
-
-/* Symbol Counter Output Compare Register 2 HH-Byte */
-#define SCOCR2HH                        _SFR_MEM8(0xF4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HH {
-        unsigned int scocr2hh : 8;	/* Symbol Counter Output Compare Register 2 HH-Byte */
-};
-
-#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HH */
-
-#define SCOCR2HH0                       0
-#define SCOCR2HH1                       1
-#define SCOCR2HH2                       2
-#define SCOCR2HH3                       3
-#define SCOCR2HH4                       4
-#define SCOCR2HH5                       5
-#define SCOCR2HH6                       6
-#define SCOCR2HH7                       7
-
-/* Symbol Counter Output Compare Register 1 LL-Byte */
-#define SCOCR1LL                        _SFR_MEM8(0xF5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LL {
-        unsigned int scocr1ll : 8;	/* Symbol Counter Output Compare Register 1 LL-Byte */
-};
-
-#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LL */
-
-#define SCOCR1LL0                       0
-#define SCOCR1LL1                       1
-#define SCOCR1LL2                       2
-#define SCOCR1LL3                       3
-#define SCOCR1LL4                       4
-#define SCOCR1LL5                       5
-#define SCOCR1LL6                       6
-#define SCOCR1LL7                       7
-
-/* Symbol Counter Output Compare Register 1 LH-Byte */
-#define SCOCR1LH                        _SFR_MEM8(0xF6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LH {
-        unsigned int scocr1lh : 8;	/* Symbol Counter Output Compare Register 1 LH-Byte */
-};
-
-#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LH */
-
-#define SCOCR1LH0                       0
-#define SCOCR1LH1                       1
-#define SCOCR1LH2                       2
-#define SCOCR1LH3                       3
-#define SCOCR1LH4                       4
-#define SCOCR1LH5                       5
-#define SCOCR1LH6                       6
-#define SCOCR1LH7                       7
-
-/* Symbol Counter Output Compare Register 1 HL-Byte */
-#define SCOCR1HL                        _SFR_MEM8(0xF7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HL {
-        unsigned int scocr1hl : 8;	/* Symbol Counter Output Compare Register 1 HL-Byte */
-};
-
-#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HL */
-
-#define SCOCR1HL0                       0
-#define SCOCR1HL1                       1
-#define SCOCR1HL2                       2
-#define SCOCR1HL3                       3
-#define SCOCR1HL4                       4
-#define SCOCR1HL5                       5
-#define SCOCR1HL6                       6
-#define SCOCR1HL7                       7
-
-/* Symbol Counter Output Compare Register 1 HH-Byte */
-#define SCOCR1HH                        _SFR_MEM8(0xF8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HH {
-        unsigned int scocr1hh : 8;	/* Symbol Counter Output Compare Register 1 HH-Byte */
-};
-
-#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HH */
-
-#define SCOCR1HH0                       0
-#define SCOCR1HH1                       1
-#define SCOCR1HH2                       2
-#define SCOCR1HH3                       3
-#define SCOCR1HH4                       4
-#define SCOCR1HH5                       5
-#define SCOCR1HH6                       6
-#define SCOCR1HH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-#define SCTSTRLL                        _SFR_MEM8(0xF9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLL {
-        unsigned int sctstrll : 8;	/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSTRLL_struct _SFR_MEM8_STRUCT(0xf9, struct __reg_SCTSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLL */
-
-#define SCTSTRLL0                       0
-#define SCTSTRLL1                       1
-#define SCTSTRLL2                       2
-#define SCTSTRLL3                       3
-#define SCTSTRLL4                       4
-#define SCTSTRLL5                       5
-#define SCTSTRLL6                       6
-#define SCTSTRLL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-#define SCTSTRLH                        _SFR_MEM8(0xFA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLH {
-        unsigned int sctstrlh : 8;	/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSTRLH_struct _SFR_MEM8_STRUCT(0xfa, struct __reg_SCTSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLH */
-
-#define SCTSTRLH0                       0
-#define SCTSTRLH1                       1
-#define SCTSTRLH2                       2
-#define SCTSTRLH3                       3
-#define SCTSTRLH4                       4
-#define SCTSTRLH5                       5
-#define SCTSTRLH6                       6
-#define SCTSTRLH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-#define SCTSTRHL                        _SFR_MEM8(0xFB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHL {
-        unsigned int sctstrhl : 8;	/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSTRHL_struct _SFR_MEM8_STRUCT(0xfb, struct __reg_SCTSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHL */
-
-#define SCTSTRHL0                       0
-#define SCTSTRHL1                       1
-#define SCTSTRHL2                       2
-#define SCTSTRHL3                       3
-#define SCTSTRHL4                       4
-#define SCTSTRHL5                       5
-#define SCTSTRHL6                       6
-#define SCTSTRHL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-#define SCTSTRHH                        _SFR_MEM8(0xFC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHH {
-        unsigned int sctstrhh : 8;	/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSTRHH_struct _SFR_MEM8_STRUCT(0xfc, struct __reg_SCTSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHH */
-
-#define SCTSTRHH0                       0
-#define SCTSTRHH1                       1
-#define SCTSTRHH2                       2
-#define SCTSTRHH3                       3
-#define SCTSTRHH4                       4
-#define SCTSTRHH5                       5
-#define SCTSTRHH6                       6
-#define SCTSTRHH7                       7
-
-/* Multiple Address Filter Configuration Register 0 */
-#define MAFCR0                          _SFR_MEM8(0x10C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR0 {
-        unsigned int maf0en : 1;	/* Multiple Address Filter 0 Enable */
-        unsigned int maf1en : 1;	/* Multiple Address Filter 1 Enable */
-        unsigned int maf2en : 1;	/* Multiple Address Filter 2 Enable */
-        unsigned int maf3en : 1;	/* Multiple Address Filter 3 Enable */
-        unsigned int : 4;
-};
-
-#define MAFCR0_struct _SFR_MEM8_STRUCT(0x10c, struct __reg_MAFCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR0 */
-
-#define MAF0EN                          0
-#define MAF1EN                          1
-#define MAF2EN                          2
-#define MAF3EN                          3
-
-/* Multiple Address Filter Configuration Register 1 */
-#define MAFCR1                          _SFR_MEM8(0x10D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR1 {
-        unsigned int aack_0_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 0. */
-        unsigned int aack_0_set_pd : 1;	/* Set Data Pending bit for address filter 0. */
-        unsigned int aack_1_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 1. */
-        unsigned int aack_1_set_pd : 1;	/* Set Data Pending bit for address filter 1. */
-        unsigned int aack_2_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 2. */
-        unsigned int aack_2_set_pd : 1;	/* Set Data Pending bit for address filter 2. */
-        unsigned int aack_3_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 3. */
-        unsigned int aack_3_set_pd : 1;	/* Set Data Pending bit for address filter 3. */
-};
-
-#define MAFCR1_struct _SFR_MEM8_STRUCT(0x10d, struct __reg_MAFCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR1 */
-
-#define AACK_0_I_AM_COORD               0
-#define AACK_0_SET_PD                   1
-#define AACK_1_I_AM_COORD               2
-#define AACK_1_SET_PD                   3
-#define AACK_2_I_AM_COORD               4
-#define AACK_2_SET_PD                   5
-#define AACK_3_I_AM_COORD               6
-#define AACK_3_SET_PD                   7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) */
-#define MAFSA0L                         _SFR_MEM8(0x10E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0L {
-        unsigned int mafsa0l : 8;	/* MAC Short Address low Byte for Frame Filter 0 */
-};
-
-#define MAFSA0L_struct _SFR_MEM8_STRUCT(0x10e, struct __reg_MAFSA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0L */
-
-#define MAFSA0L0                        0
-#define MAFSA0L1                        1
-#define MAFSA0L2                        2
-#define MAFSA0L3                        3
-#define MAFSA0L4                        4
-#define MAFSA0L5                        5
-#define MAFSA0L6                        6
-#define MAFSA0L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) */
-#define MAFSA0H                         _SFR_MEM8(0x10F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0H {
-        unsigned int mafsa0h : 8;	/* MAC Short Address high Byte for Frame Filter 0 */
-};
-
-#define MAFSA0H_struct _SFR_MEM8_STRUCT(0x10f, struct __reg_MAFSA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0H */
-
-#define MAFSA0H0                        0
-#define MAFSA0H1                        1
-#define MAFSA0H2                        2
-#define MAFSA0H3                        3
-#define MAFSA0H4                        4
-#define MAFSA0H5                        5
-#define MAFSA0H6                        6
-#define MAFSA0H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) */
-#define MAFPA0L                         _SFR_MEM8(0x110)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0L {
-        unsigned int mafpa0l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 0 */
-};
-
-#define MAFPA0L_struct _SFR_MEM8_STRUCT(0x110, struct __reg_MAFPA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0L */
-
-#define MAFPA0L0                        0
-#define MAFPA0L1                        1
-#define MAFPA0L2                        2
-#define MAFPA0L3                        3
-#define MAFPA0L4                        4
-#define MAFPA0L5                        5
-#define MAFPA0L6                        6
-#define MAFPA0L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) */
-#define MAFPA0H                         _SFR_MEM8(0x111)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0H {
-        unsigned int mafpa0h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 0 */
-};
-
-#define MAFPA0H_struct _SFR_MEM8_STRUCT(0x111, struct __reg_MAFPA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0H */
-
-#define MAFPA0H0                        0
-#define MAFPA0H1                        1
-#define MAFPA0H2                        2
-#define MAFPA0H3                        3
-#define MAFPA0H4                        4
-#define MAFPA0H5                        5
-#define MAFPA0H6                        6
-#define MAFPA0H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) */
-#define MAFSA1L                         _SFR_MEM8(0x112)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1L {
-        unsigned int mafsa1l : 8;	/* MAC Short Address low Byte for Frame Filter 1 */
-};
-
-#define MAFSA1L_struct _SFR_MEM8_STRUCT(0x112, struct __reg_MAFSA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1L */
-
-#define MAFSA1L0                        0
-#define MAFSA1L1                        1
-#define MAFSA1L2                        2
-#define MAFSA1L3                        3
-#define MAFSA1L4                        4
-#define MAFSA1L5                        5
-#define MAFSA1L6                        6
-#define MAFSA1L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) */
-#define MAFSA1H                         _SFR_MEM8(0x113)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1H {
-        unsigned int mafsa1h : 8;	/* MAC Short Address high Byte for Frame Filter 1 */
-};
-
-#define MAFSA1H_struct _SFR_MEM8_STRUCT(0x113, struct __reg_MAFSA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1H */
-
-#define MAFSA1H0                        0
-#define MAFSA1H1                        1
-#define MAFSA1H2                        2
-#define MAFSA1H3                        3
-#define MAFSA1H4                        4
-#define MAFSA1H5                        5
-#define MAFSA1H6                        6
-#define MAFSA1H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) */
-#define MAFPA1L                         _SFR_MEM8(0x114)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1L {
-        unsigned int mafpa1l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 1 */
-};
-
-#define MAFPA1L_struct _SFR_MEM8_STRUCT(0x114, struct __reg_MAFPA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1L */
-
-#define MAFPA1L0                        0
-#define MAFPA1L1                        1
-#define MAFPA1L2                        2
-#define MAFPA1L3                        3
-#define MAFPA1L4                        4
-#define MAFPA1L5                        5
-#define MAFPA1L6                        6
-#define MAFPA1L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) */
-#define MAFPA1H                         _SFR_MEM8(0x115)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1H {
-        unsigned int mafpa1h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 1 */
-};
-
-#define MAFPA1H_struct _SFR_MEM8_STRUCT(0x115, struct __reg_MAFPA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1H */
-
-#define MAFPA1H0                        0
-#define MAFPA1H1                        1
-#define MAFPA1H2                        2
-#define MAFPA1H3                        3
-#define MAFPA1H4                        4
-#define MAFPA1H5                        5
-#define MAFPA1H6                        6
-#define MAFPA1H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) */
-#define MAFSA2L                         _SFR_MEM8(0x116)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2L {
-        unsigned int mafsa2l : 8;	/* MAC Short Address low Byte for Frame Filter 2 */
-};
-
-#define MAFSA2L_struct _SFR_MEM8_STRUCT(0x116, struct __reg_MAFSA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2L */
-
-#define MAFSA2L0                        0
-#define MAFSA2L1                        1
-#define MAFSA2L2                        2
-#define MAFSA2L3                        3
-#define MAFSA2L4                        4
-#define MAFSA2L5                        5
-#define MAFSA2L6                        6
-#define MAFSA2L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) */
-#define MAFSA2H                         _SFR_MEM8(0x117)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2H {
-        unsigned int mafsa2h : 8;	/* MAC Short Address high Byte for Frame Filter 2 */
-};
-
-#define MAFSA2H_struct _SFR_MEM8_STRUCT(0x117, struct __reg_MAFSA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2H */
-
-#define MAFSA2H0                        0
-#define MAFSA2H1                        1
-#define MAFSA2H2                        2
-#define MAFSA2H3                        3
-#define MAFSA2H4                        4
-#define MAFSA2H5                        5
-#define MAFSA2H6                        6
-#define MAFSA2H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) */
-#define MAFPA2L                         _SFR_MEM8(0x118)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2L {
-        unsigned int mafpa2l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 2 */
-};
-
-#define MAFPA2L_struct _SFR_MEM8_STRUCT(0x118, struct __reg_MAFPA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2L */
-
-#define MAFPA2L0                        0
-#define MAFPA2L1                        1
-#define MAFPA2L2                        2
-#define MAFPA2L3                        3
-#define MAFPA2L4                        4
-#define MAFPA2L5                        5
-#define MAFPA2L6                        6
-#define MAFPA2L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) */
-#define MAFPA2H                         _SFR_MEM8(0x119)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2H {
-        unsigned int mafpa2h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 2 */
-};
-
-#define MAFPA2H_struct _SFR_MEM8_STRUCT(0x119, struct __reg_MAFPA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2H */
-
-#define MAFPA2H0                        0
-#define MAFPA2H1                        1
-#define MAFPA2H2                        2
-#define MAFPA2H3                        3
-#define MAFPA2H4                        4
-#define MAFPA2H5                        5
-#define MAFPA2H6                        6
-#define MAFPA2H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) */
-#define MAFSA3L                         _SFR_MEM8(0x11A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3L {
-        unsigned int mafsa3l : 8;	/* MAC Short Address low Byte for Frame Filter 3 */
-};
-
-#define MAFSA3L_struct _SFR_MEM8_STRUCT(0x11a, struct __reg_MAFSA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3L */
-
-#define MAFSA3L0                        0
-#define MAFSA3L1                        1
-#define MAFSA3L2                        2
-#define MAFSA3L3                        3
-#define MAFSA3L4                        4
-#define MAFSA3L5                        5
-#define MAFSA3L6                        6
-#define MAFSA3L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) */
-#define MAFSA3H                         _SFR_MEM8(0x11B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3H {
-        unsigned int mafsa3h : 8;	/* MAC Short Address high Byte for Frame Filter 3 */
-};
-
-#define MAFSA3H_struct _SFR_MEM8_STRUCT(0x11b, struct __reg_MAFSA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3H */
-
-#define MAFSA3H0                        0
-#define MAFSA3H1                        1
-#define MAFSA3H2                        2
-#define MAFSA3H3                        3
-#define MAFSA3H4                        4
-#define MAFSA3H5                        5
-#define MAFSA3H6                        6
-#define MAFSA3H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) */
-#define MAFPA3L                         _SFR_MEM8(0x11C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3L {
-        unsigned int mafpa3l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 3 */
-};
-
-#define MAFPA3L_struct _SFR_MEM8_STRUCT(0x11c, struct __reg_MAFPA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3L */
-
-#define MAFPA3L0                        0
-#define MAFPA3L1                        1
-#define MAFPA3L2                        2
-#define MAFPA3L3                        3
-#define MAFPA3L4                        4
-#define MAFPA3L5                        5
-#define MAFPA3L6                        6
-#define MAFPA3L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) */
-#define MAFPA3H                         _SFR_MEM8(0x11D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3H {
-        unsigned int mafpa3h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 3 */
-};
-
-#define MAFPA3H_struct _SFR_MEM8_STRUCT(0x11d, struct __reg_MAFPA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3H */
-
-#define MAFPA3H0                        0
-#define MAFPA3H1                        1
-#define MAFPA3H2                        2
-#define MAFPA3H3                        3
-#define MAFPA3H4                        4
-#define MAFPA3H5                        5
-#define MAFPA3H6                        6
-#define MAFPA3H7                        7
-
-/* Timer/Counter5 Control Register A */
-#define TCCR5A                          _SFR_MEM8(0x120)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5A {
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int com5c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com5b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com5a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5A */
-
-#define WGM50                           0
-#define WGM51                           1
-#define COM5C0                          2
-#define COM5C1                          3
-#define COM5B0                          4
-#define COM5B1                          5
-#define COM5A0                          6
-#define COM5A1                          7
-
-/* Timer/Counter5 Control Register B */
-#define TCCR5B                          _SFR_MEM8(0x121)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5B {
-        unsigned int cs5 : 3;	/* Clock Select */
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices5 : 1;	/* Input Capture 5 Edge Select */
-        unsigned int icnc5 : 1;	/* Input Capture 5 Noise Canceller */
-};
-
-#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5B */
-
-#define CS50                            0
-#define CS51                            1
-#define CS52                            2
-#define WGM52                           3
-#define WGM53                           4
-#define ICES5                           6
-#define ICNC5                           7
-
-/* Timer/Counter5 Control Register C */
-#define TCCR5C                          _SFR_MEM8(0x122)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5C {
-        unsigned int : 5;
-        unsigned int foc5c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc5b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc5a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5C */
-
-#define FOC5C                           5
-#define FOC5B                           6
-#define FOC5A                           7
-
-/* Timer/Counter5  Bytes */
-#define TCNT5                           _SFR_MEM16(0x124)
-#define TCNT5L                          _SFR_MEM8(0x124)
-#define TCNT5H                          _SFR_MEM8(0x125)
-
-/* Timer/Counter5 Input Capture Register  Bytes */
-#define ICR5                            _SFR_MEM16(0x126)
-#define ICR5L                           _SFR_MEM8(0x126)
-#define ICR5H                           _SFR_MEM8(0x127)
-
-/* Timer/Counter5 Output Compare Register A  Bytes */
-#define OCR5A                           _SFR_MEM16(0x128)
-#define OCR5AL                          _SFR_MEM8(0x128)
-#define OCR5AH                          _SFR_MEM8(0x129)
-
-/* Timer/Counter5 Output Compare Register B  Bytes */
-#define OCR5B                           _SFR_MEM16(0x12A)
-#define OCR5BL                          _SFR_MEM8(0x12A)
-#define OCR5BH                          _SFR_MEM8(0x12B)
-
-/* Timer/Counter5 Output Compare Register C  Bytes */
-#define OCR5C                           _SFR_MEM16(0x12C)
-#define OCR5CL                          _SFR_MEM8(0x12C)
-#define OCR5CH                          _SFR_MEM8(0x12D)
-
-/* Low Leakage Voltage Regulator Control Register */
-#define LLCR                            _SFR_MEM8(0x12F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLCR {
-        unsigned int llencal : 1;	/* Enable Automatic Calibration */
-        unsigned int llshort : 1;	/* Short Lower Calibration Circuit */
-        unsigned int lltco : 1;	/* Temperature Coefficient of Current Source */
-        unsigned int llcal : 1;	/* Calibration Active */
-        unsigned int llcomp : 1;	/* Comparator Output */
-        unsigned int lldone : 1;	/* Calibration Done */
-        unsigned int : 2;
-};
-
-#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLCR */
-
-#define LLENCAL                         0
-#define LLSHORT                         1
-#define LLTCO                           2
-#define LLCAL                           3
-#define LLCOMP                          4
-#define LLDONE                          5
-
-/* Low Leakage Voltage Regulator Data Register (Low-Byte) */
-#define LLDRL                           _SFR_MEM8(0x130)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRL {
-        unsigned int lldrl : 4;	/* Low-Byte Data Register Bits */
-        unsigned int : 4;
-};
-
-#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRL */
-
-#define LLDRL0                          0
-#define LLDRL1                          1
-#define LLDRL2                          2
-#define LLDRL3                          3
-
-/* Low Leakage Voltage Regulator Data Register (High-Byte) */
-#define LLDRH                           _SFR_MEM8(0x131)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRH {
-        unsigned int lldrh : 5;	/* High-Byte Data Register Bits */
-        unsigned int : 3;
-};
-
-#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRH */
-
-#define LLDRH0                          0
-#define LLDRH1                          1
-#define LLDRH2                          2
-#define LLDRH3                          3
-#define LLDRH4                          4
-
-/* Data Retention Configuration Register #3 */
-#define DRTRAM3                         _SFR_MEM8(0x132)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM3 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM3 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #2 */
-#define DRTRAM2                         _SFR_MEM8(0x133)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM2 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM2 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #1 */
-#define DRTRAM1                         _SFR_MEM8(0x134)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM1 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM1 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #0 */
-#define DRTRAM0                         _SFR_MEM8(0x135)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM0 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM0 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Port Driver Strength Register 0 */
-#define DPDS0                           _SFR_MEM8(0x136)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS0 {
-        unsigned int pbdrv : 2;	/* Driver Strength Port B */
-        unsigned int pddrv : 2;	/* Driver Strength Port D */
-        unsigned int pedrv : 2;	/* Driver Strength Port E */
-        unsigned int pfdrv : 2;	/* Driver Strength Port F */
-};
-
-#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS0 */
-
-#define PBDRV0                          0
-#define PBDRV1                          1
-#define PDDRV0                          2
-#define PDDRV1                          3
-#define PEDRV0                          4
-#define PEDRV1                          5
-#define PFDRV0                          6
-#define PFDRV1                          7
-
-/* Port Driver Strength Register 1 */
-#define DPDS1                           _SFR_MEM8(0x137)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS1 {
-        unsigned int pgdrv : 2;	/* Driver Strength Port G */
-        unsigned int : 6;
-};
-
-#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS1 */
-
-#define PGDRV0                          0
-#define PGDRV1                          1
-
-/* Power Amplifier Ramp up/down Control Register */
-#define PARCR                           _SFR_MEM8(0x138)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PARCR {
-        unsigned int parufi : 1;	/* Power Amplifier Ramp Up Frequency Inversion */
-        unsigned int pardfi : 1;	/* Power Amplifier Ramp Down Frequency Inversion */
-        unsigned int paltu : 3;	/* ext. PA Ramp Up Lead Time */
-        unsigned int paltd : 3;	/* ext. PA Ramp Down Lead Time */
-};
-
-#define PARCR_struct _SFR_MEM8_STRUCT(0x138, struct __reg_PARCR)
-
-/* symbolic names */
-
-#define PALTU_MINUS_3US                 0
-#define PALTU_MINUS_2US                 1
-#define PALTU_MINUS_1US                 2
-#define PALTU_0US                       3
-#define PALTU_1US                       4
-#define PALTU_2US                       5
-#define PALTU_3US                       6
-#define PALTU_4US                       7
-#define PALTD_MINUS_3US                 0
-#define PALTD_MINUS_2US                 1
-#define PALTD_MINUS_1US                 2
-#define PALTD_0US                       3
-#define PALTD_1US                       4
-#define PALTD_2US                       5
-#define PALTD_3US                       6
-#define PALTD_4US                       7
-
-#endif /* __ASSEMBLER__ */
-
-  /* PARCR */
-
-#define PARUFI                          0
-#define PARDFI                          1
-#define PALTU0                          2
-#define PALTU1                          3
-#define PALTU2                          4
-#define PALTD0                          5
-#define PALTD1                          6
-#define PALTD2                          7
-
-/* Transceiver Pin Register */
-#define TRXPR                           _SFR_MEM8(0x139)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRXPR {
-        unsigned int trxrst : 1;	/* Force Transceiver Reset */
-        unsigned int slptr : 1;	/* Multi-purpose Transceiver Control Bit */
-        unsigned int : 6;
-};
-
-#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRXPR */
-
-#define TRXRST                          0
-#define SLPTR                           1
-
-/* AES Control Register */
-#define AES_CTRL                        _SFR_MEM8(0x13C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_CTRL {
-        unsigned int : 2;
-        unsigned int aes_im : 1;	/* AES Interrupt Enable */
-        unsigned int aes_dir : 1;	/* Set AES Operation Direction */
-        unsigned int : 1;
-        unsigned int aes_mode : 1;	/* Set AES Operation Mode */
-        unsigned int : 1;
-        unsigned int aes_request : 1;	/* Request AES Operation. */
-};
-
-#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL)
-
-/* symbolic names */
-
-#define AES_DIR_ENC                     0
-#define AES_DIR_DEC                     1
-#define AES_MODE_ECB                    0
-#define AES_MODE_CBC                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_CTRL */
-
-#define AES_IM                          2
-#define AES_DIR                         3
-#define AES_MODE                        5
-#define AES_REQUEST                     7
-
-/* AES Status Register */
-#define AES_STATUS                      _SFR_MEM8(0x13D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATUS {
-        unsigned int aes_done : 1;	/* AES Operation Finished with Success */
-        unsigned int : 6;
-        unsigned int aes_er : 1;	/* AES Operation Finished with Error */
-};
-
-#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATUS */
-
-#define AES_DONE                        0
-#define AES_ER                          7
-
-/* AES Plain and Cipher Text Buffer Register */
-#define AES_STATE                       _SFR_MEM8(0x13E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATE {
-        unsigned int aes_state : 8;	/* AES Plain and Cipher Text Buffer */
-};
-
-#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATE */
-
-#define AES_STATE0                      0
-#define AES_STATE1                      1
-#define AES_STATE2                      2
-#define AES_STATE3                      3
-#define AES_STATE4                      4
-#define AES_STATE5                      5
-#define AES_STATE6                      6
-#define AES_STATE7                      7
-
-/* AES Encryption and Decryption Key Buffer Register */
-#define AES_KEY                         _SFR_MEM8(0x13F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_KEY {
-        unsigned int aes_key : 8;	/* AES Encryption/Decryption Key Buffer */
-};
-
-#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_KEY */
-
-#define AES_KEY0                        0
-#define AES_KEY1                        1
-#define AES_KEY2                        2
-#define AES_KEY3                        3
-#define AES_KEY4                        4
-#define AES_KEY5                        5
-#define AES_KEY6                        6
-#define AES_KEY7                        7
-
-/* Transceiver Status Register */
-#define TRX_STATUS                      _SFR_MEM8(0x141)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATUS {
-        unsigned int trx_status : 5;	/* Transceiver Main Status */
-        unsigned int tst_status : 1;	/* Test mode status */
-        unsigned int cca_status : 1;	/* CCA Status Result */
-        unsigned int cca_done : 1;	/* CCA Algorithm Status */
-};
-
-#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS)
-
-/* symbolic names */
-
-#define BUSY_RX                         1
-#define BUSY_TX                         2
-#define RX_ON                           6
-#define TRX_OFF                         8
-#define PLL_ON                          9
-#define SLEEP                           15
-#define BUSY_RX_AACK                    17
-#define BUSY_TX_ARET                    18
-#define RX_AACK_ON                      22
-#define TX_ARET_ON                      25
-#define STATE_TRANSITION_IN_PROGRESS    31
-#define TST_DISABLED                    0
-#define TST_ENABLED                     1
-#define CCA_BUSY                        0
-#define CCA_IDLE                        1
-#define CCA_NOT_FIN                     0
-#define CCA_FIN                         1
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATUS */
-
-#define TRX_STATUS0                     0
-#define TRX_STATUS1                     1
-#define TRX_STATUS2                     2
-#define TRX_STATUS3                     3
-#define TRX_STATUS4                     4
-#define TST_STATUS                      5
-#define CCA_STATUS                      6
-#define CCA_DONE                        7
-
-/* Transceiver State Control Register */
-#define TRX_STATE                       _SFR_MEM8(0x142)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATE {
-        unsigned int trx_cmd : 5;	/* State Control Command */
-        unsigned int trac_status : 3;	/* Transaction Status */
-};
-
-#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE)
-
-/* symbolic names */
-
-#define CMD_NOP                         0
-#define CMD_TX_START                    2
-#define CMD_FORCE_TRX_OFF               3
-#define CMD_FORCE_PLL_ON                4
-#define CMD_RX_ON                       6
-#define CMD_TRX_OFF                     8
-#define CMD_PLL_ON                      9
-#define CMD_RX_AACK_ON                  22
-#define CMD_TX_ARET_ON                  25
-#define TRAC_SUCCESS                    0
-#define TRAC_SUCCESS_DATA_PENDING       1
-#define TRAC_SUCCESS_WAIT_FOR_ACK       2
-#define TRAC_CHANNEL_ACCESS_FAILURE     3
-#define TRAC_NO_ACK                     5
-#define TRAC_INVALID                    7
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATE */
-
-#define TRX_CMD0                        0
-#define TRX_CMD1                        1
-#define TRX_CMD2                        2
-#define TRX_CMD3                        3
-#define TRX_CMD4                        4
-#define TRAC_STATUS0                    5
-#define TRAC_STATUS1                    6
-#define TRAC_STATUS2                    7
-
-/* Tranceiver Control Register 0 */
-#define TRX_CTRL_0                      _SFR_MEM8(0x143)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_0 {
-        unsigned int : 4;
-        unsigned int pmu_if_inv : 1;	/* PMU IF Inverse */
-        unsigned int pmu_start : 1;	/* Start of Phase Measurement Unit */
-        unsigned int pmu_en : 1;	/* Enable Phase Measurement Unit */
-        unsigned int res7 : 1;	/* Reserved */
-};
-
-#define TRX_CTRL_0_struct _SFR_MEM8_STRUCT(0x143, struct __reg_TRX_CTRL_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_0 */
-
-#define PMU_IF_INV                      4
-#define PMU_START                       5
-#define PMU_EN                          6
-
-/* Transceiver Control Register 1 */
-#define TRX_CTRL_1                      _SFR_MEM8(0x144)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_1 {
-        unsigned int : 4;
-        unsigned int pll_tx_flt : 1;	/* Enable PLL TX Filter */
-        unsigned int tx_auto_crc_on : 1;	/* Enable Automatic CRC Calculation */
-        unsigned int irq_2_ext_en : 1;	/* Connect Frame Start IRQ to TC1 */
-        unsigned int pa_ext_en : 1;	/* External PA support enable */
-};
-
-#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_1 */
-
-#define PLL_TX_FLT                      4
-#define TX_AUTO_CRC_ON                  5
-#define IRQ_2_EXT_EN                    6
-#define PA_EXT_EN                       7
-
-/* Transceiver Transmit Power Control Register */
-#define PHY_TX_PWR                      _SFR_MEM8(0x145)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_TX_PWR {
-        unsigned int tx_pwr : 4;	/* Transmit Power Setting */
-        unsigned int : 4;
-};
-
-#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_TX_PWR */
-
-#define TX_PWR0                         0
-#define TX_PWR1                         1
-#define TX_PWR2                         2
-#define TX_PWR3                         3
-
-/* Receiver Signal Strength Indicator Register */
-#define PHY_RSSI                        _SFR_MEM8(0x146)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_RSSI {
-        unsigned int rssi : 5;	/* Receiver Signal Strength Indicator */
-        unsigned int rnd_value : 2;	/* Random Value */
-        unsigned int rx_crc_valid : 1;	/* Received Frame CRC Status */
-};
-
-#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI)
-
-/* symbolic names */
-
-#define RSSI_MIN                        0
-#define RSSI_MIN_PLUS_3dB               1
-#define RSSI_MAX                        28
-#define CRC_INVALID                     0
-#define CRC_VALID                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_RSSI */
-
-#define RSSI0                           0
-#define RSSI1                           1
-#define RSSI2                           2
-#define RSSI3                           3
-#define RSSI4                           4
-#define RND_VALUE0                      5
-#define RND_VALUE1                      6
-#define RX_CRC_VALID                    7
-
-/* Transceiver Energy Detection Level Register */
-#define PHY_ED_LEVEL                    _SFR_MEM8(0x147)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_ED_LEVEL {
-        unsigned int ed_level : 8;	/* Energy Detection Level */
-};
-
-#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL)
-
-/* symbolic names */
-
-#define ED_MIN                          0
-#define ED_MIN_PLUS_1dB                 1
-#define ED_MAX                          83
-#define ED_RESET                        255
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_ED_LEVEL */
-
-#define ED_LEVEL0                       0
-#define ED_LEVEL1                       1
-#define ED_LEVEL2                       2
-#define ED_LEVEL3                       3
-#define ED_LEVEL4                       4
-#define ED_LEVEL5                       5
-#define ED_LEVEL6                       6
-#define ED_LEVEL7                       7
-
-/* Transceiver Clear Channel Assessment (CCA) Control Register */
-#define PHY_CC_CCA                      _SFR_MEM8(0x148)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_CC_CCA {
-        unsigned int channel : 5;	/* RX/TX Channel Selection */
-        unsigned int cca_mode : 2;	/* Select CCA Measurement Mode */
-        unsigned int cca_request : 1;	/* Manual CCA Measurement Request */
-};
-
-#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA)
-
-/* symbolic names */
-
-#define F_2405MHZ                       11
-#define F_2410MHZ                       12
-#define F_2415MHZ                       13
-#define F_2420MHZ                       14
-#define F_2425MHZ                       15
-#define F_2430MHZ                       16
-#define F_2435MHZ                       17
-#define F_2440MHZ                       18
-#define F_2445MHZ                       19
-#define F_2450MHZ                       20
-#define F_2455MHZ                       21
-#define F_2460MHZ                       22
-#define F_2465MHZ                       23
-#define F_2470MHZ                       24
-#define F_2475MHZ                       25
-#define F_2480MHZ                       26
-#define CCA_CS_OR_ED                    0
-#define CCA_ED                          1
-#define CCA_CS                          2
-#define CCA_CS_AND_ED                   3
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_CC_CCA */
-
-#define CHANNEL0                        0
-#define CHANNEL1                        1
-#define CHANNEL2                        2
-#define CHANNEL3                        3
-#define CHANNEL4                        4
-#define CCA_MODE0                       5
-#define CCA_MODE1                       6
-#define CCA_REQUEST                     7
-
-/* Transceiver CCA Threshold Setting Register */
-#define CCA_THRES                       _SFR_MEM8(0x149)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CCA_THRES {
-        unsigned int cca_ed_thres : 4;	/* ED Threshold Level for CCA Measurement */
-        unsigned int cca_cs_thres : 4;	/* CS Threshold Level for CCA Measurement */
-};
-
-#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CCA_THRES */
-
-#define CCA_ED_THRES0                   0
-#define CCA_ED_THRES1                   1
-#define CCA_ED_THRES2                   2
-#define CCA_ED_THRES3                   3
-#define CCA_CS_THRES0                   4
-#define CCA_CS_THRES1                   5
-#define CCA_CS_THRES2                   6
-#define CCA_CS_THRES3                   7
-
-/* Transceiver Receive Control Register */
-#define RX_CTRL                         _SFR_MEM8(0x14A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_CTRL {
-        unsigned int pdt_thres : 4;	/* Receiver Sensitivity Control */
-        unsigned int : 4;
-};
-
-#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL)
-
-/* symbolic names */
-
-#define PDT_THRES_ANT_DIV_OFF           7
-#define PDT_THRES_ANT_DIV_ON            3
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_CTRL */
-
-#define PDT_THRES0                      0
-#define PDT_THRES1                      1
-#define PDT_THRES2                      2
-#define PDT_THRES3                      3
-
-/* Start of Frame Delimiter Value Register */
-#define SFD_VALUE                       _SFR_MEM8(0x14B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SFD_VALUE {
-        unsigned int sfd_value : 8;	/* Start of Frame Delimiter Value */
-};
-
-#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE)
-
-/* symbolic names */
-
-#define IEEE_SFD                        167
-
-#endif /* __ASSEMBLER__ */
-
-  /* SFD_VALUE */
-
-#define SFD_VALUE0                      0
-#define SFD_VALUE1                      1
-#define SFD_VALUE2                      2
-#define SFD_VALUE3                      3
-#define SFD_VALUE4                      4
-#define SFD_VALUE5                      5
-#define SFD_VALUE6                      6
-#define SFD_VALUE7                      7
-
-/* Transceiver Control Register 2 */
-#define TRX_CTRL_2                      _SFR_MEM8(0x14C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_2 {
-        unsigned int oqpsk_data_rate : 2;	/* Data Rate Selection */
-        unsigned int : 5;
-        unsigned int rx_safe_mode : 1;	/* RX Safe Mode */
-};
-
-#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2)
-
-/* symbolic names */
-
-#define RATE_250KB                      0
-#define RATE_500KB                      1
-#define RATE_1000KB                     2
-#define RATE_2000KB                     3
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_2 */
-
-#define OQPSK_DATA_RATE0                0
-#define OQPSK_DATA_RATE1                1
-#define RX_SAFE_MODE                    7
-
-/* Antenna Diversity Control Register */
-#define ANT_DIV                         _SFR_MEM8(0x14D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ANT_DIV {
-        unsigned int ant_ctrl : 2;	/* Static Antenna Diversity Switch Control */
-        unsigned int ant_ext_sw_en : 1;	/* Enable External Antenna Switch Control */
-        unsigned int ant_div_en : 1;	/* Enable Antenna Diversity */
-        unsigned int : 3;
-        unsigned int ant_sel : 1;	/* Antenna Diversity Antenna Status */
-};
-
-#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV)
-
-/* symbolic names */
-
-#define ANT_1                           1
-#define ANT_0                           2
-#define ANT_RESET                       3
-#define ANT_DIV_EXT_SW_DIS              0
-#define ANT_DIV_EXT_SW_EN               1
-#define ANTENNA_0                       0
-#define ANTENNA_1                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* ANT_DIV */
-
-#define ANT_CTRL0                       0
-#define ANT_CTRL1                       1
-#define ANT_EXT_SW_EN                   2
-#define ANT_DIV_EN                      3
-#define ANT_SEL                         7
-
-/* Transceiver Interrupt Enable Register */
-#define IRQ_MASK                        _SFR_MEM8(0x14E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK {
-        unsigned int pll_lock_en : 1;	/* PLL Lock Interrupt Enable */
-        unsigned int pll_unlock_en : 1;	/* PLL Unlock Interrupt Enable */
-        unsigned int rx_start_en : 1;	/* RX_START Interrupt Enable */
-        unsigned int rx_end_en : 1;	/* RX_END Interrupt Enable */
-        unsigned int cca_ed_done_en : 1;	/* End of ED Measurement Interrupt Enable */
-        unsigned int ami_en : 1;	/* Address Match Interrupt Enable */
-        unsigned int tx_end_en : 1;	/* TX_END Interrupt Enable */
-        unsigned int awake_en : 1;	/* Awake Interrupt Enable */
-};
-
-#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK */
-
-#define PLL_LOCK_EN                     0
-#define PLL_UNLOCK_EN                   1
-#define RX_START_EN                     2
-#define RX_END_EN                       3
-#define CCA_ED_DONE_EN                  4
-#define AMI_EN                          5
-#define TX_END_EN                       6
-#define AWAKE_EN                        7
-
-/* Transceiver Interrupt Status Register */
-#define IRQ_STATUS                      _SFR_MEM8(0x14F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS {
-        unsigned int pll_lock : 1;	/* PLL Lock Interrupt Status */
-        unsigned int pll_unlock : 1;	/* PLL Unlock Interrupt Status */
-        unsigned int rx_start : 1;	/* RX_START Interrupt Status */
-        unsigned int rx_end : 1;	/* RX_END Interrupt Status */
-        unsigned int cca_ed_done : 1;	/* End of ED Measurement Interrupt Status */
-        unsigned int ami : 1;	/* Address Match Interrupt Status */
-        unsigned int tx_end : 1;	/* TX_END Interrupt Status */
-        unsigned int awake : 1;	/* Awake Interrupt Status */
-};
-
-#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS */
-
-#define PLL_LOCK                        0
-#define PLL_UNLOCK                      1
-#define RX_START                        2
-#define RX_END                          3
-#define CCA_ED_DONE                     4
-#define AMI                             5
-#define TX_END                          6
-#define AWAKE                           7
-
-/* Voltage Regulator Control and Status Register */
-#define VREG_CTRL                       _SFR_MEM8(0x150)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VREG_CTRL {
-        unsigned int : 2;
-        unsigned int dvdd_ok : 1;	/* DVDD Supply Voltage Valid */
-        unsigned int dvreg_ext : 1;	/* Use External DVDD Regulator */
-        unsigned int : 2;
-        unsigned int avdd_ok : 1;	/* AVDD Supply Voltage Valid */
-        unsigned int avreg_ext : 1;	/* Use External AVDD Regulator */
-};
-
-#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL)
-
-/* symbolic names */
-
-#define DVDD_INT                        0
-#define DVDD_EXT                        1
-#define AVDD_INT                        0
-#define AVDD_EXT                        1
-
-#endif /* __ASSEMBLER__ */
-
-  /* VREG_CTRL */
-
-#define DVDD_OK                         2
-#define DVREG_EXT                       3
-#define AVDD_OK                         6
-#define AVREG_EXT                       7
-
-/* Battery Monitor Control and Status Register */
-#define BATMON                          _SFR_MEM8(0x151)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BATMON {
-        unsigned int batmon_vth : 4;	/* Battery Monitor Threshold Voltage */
-        unsigned int batmon_hr : 1;	/* Battery Monitor Voltage Range */
-        unsigned int batmon_ok : 1;	/* Battery Monitor Status */
-        unsigned int bat_low_en : 1;	/* Battery Monitor Interrupt Enable */
-        unsigned int bat_low : 1;	/* Battery Monitor Interrupt Status */
-};
-
-#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON)
-
-/* symbolic names */
-
-#define BATMON_HR_DIS                   0
-#define BATMON_HR_EN                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* BATMON */
-
-#define BATMON_VTH0                     0
-#define BATMON_VTH1                     1
-#define BATMON_VTH2                     2
-#define BATMON_VTH3                     3
-#define BATMON_HR                       4
-#define BATMON_OK                       5
-#define BAT_LOW_EN                      6
-#define BAT_LOW                         7
-
-/* Crystal Oscillator Control Register */
-#define XOSC_CTRL                       _SFR_MEM8(0x152)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XOSC_CTRL {
-        unsigned int xtal_trim : 4;	/* Crystal Oscillator Load Capacitance Trimming */
-        unsigned int xtal_mode : 4;	/* Crystal Oscillator Operating Mode */
-};
-
-#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL)
-
-/* symbolic names */
-
-#define XTAL_TRIM_MIN                   0
-#define XTAL_TRIM_MAX                   15
-
-#endif /* __ASSEMBLER__ */
-
-  /* XOSC_CTRL */
-
-#define XTAL_TRIM0                      0
-#define XTAL_TRIM1                      1
-#define XTAL_TRIM2                      2
-#define XTAL_TRIM3                      3
-#define XTAL_MODE0                      4
-#define XTAL_MODE1                      5
-#define XTAL_MODE2                      6
-#define XTAL_MODE3                      7
-
-/* Channel Control Register 0 */
-#define CC_CTRL_0                       _SFR_MEM8(0x153)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_0 {
-        unsigned int cc_number : 8;	/* Channel Number */
-};
-
-#define CC_CTRL_0_struct _SFR_MEM8_STRUCT(0x153, struct __reg_CC_CTRL_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_0 */
-
-#define CC_NUMBER0                      0
-#define CC_NUMBER1                      1
-#define CC_NUMBER2                      2
-#define CC_NUMBER3                      3
-#define CC_NUMBER4                      4
-#define CC_NUMBER5                      5
-#define CC_NUMBER6                      6
-#define CC_NUMBER7                      7
-
-/* Channel Control Register 1 */
-#define CC_CTRL_1                       _SFR_MEM8(0x154)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_1 {
-        unsigned int cc_band : 4;	/* Channel Band */
-        unsigned int : 4;
-};
-
-#define CC_CTRL_1_struct _SFR_MEM8_STRUCT(0x154, struct __reg_CC_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_1 */
-
-#define CC_BAND0                        0
-#define CC_BAND1                        1
-#define CC_BAND2                        2
-#define CC_BAND3                        3
-
-/* Transceiver Receiver Sensitivity Control Register */
-#define RX_SYN                          _SFR_MEM8(0x155)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_SYN {
-        unsigned int rx_pdt_level : 4;	/* Reduce Receiver Sensitivity */
-        unsigned int : 2;
-        unsigned int rx_override : 1;	/* Receiver Override Function */
-        unsigned int rx_pdt_dis : 1;	/* Prevent Frame Reception */
-};
-
-#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN)
-
-/* symbolic names */
-
-#define RX_PDT_LEVEL_MIN                0
-#define RX_PDT_LEVEL_MAX                15
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_SYN */
-
-#define RX_PDT_LEVEL0                   0
-#define RX_PDT_LEVEL1                   1
-#define RX_PDT_LEVEL2                   2
-#define RX_PDT_LEVEL3                   3
-#define RX_OVERRIDE                     6
-#define RX_PDT_DIS                      7
-
-/* Transceiver Reduced Power Consumption Control */
-#define TRX_RPC                         _SFR_MEM8(0x156)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_RPC {
-        unsigned int : 1;
-        unsigned int ipan_rpc_en : 1;	/* Smart Receiving Mode IPAN Handling Enable */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int pll_rpc_en : 1;	/* PLL Smart Receiving Mode Enable */
-        unsigned int pdt_rpc_en : 1;	/* Smart Receiving Mode Reduced Sensitivity Enable */
-        unsigned int rx_rpc_en : 1;	/* Receiver Smart Receiving Mode Enable */
-        unsigned int rx_rpc_ctrl : 2;	/* Smart Receiving Mode Timing */
-};
-
-#define TRX_RPC_struct _SFR_MEM8_STRUCT(0x156, struct __reg_TRX_RPC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_RPC */
-
-#define IPAN_RPC_EN                     1
-#define PLL_RPC_EN                      3
-#define PDT_RPC_EN                      4
-#define RX_RPC_EN                       5
-#define RX_RPC_CTRL0                    6
-#define RX_RPC_CTRL1                    7
-
-/* Transceiver Acknowledgment Frame Control Register 1 */
-#define XAH_CTRL_1                      _SFR_MEM8(0x157)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_1 {
-        unsigned int : 1;
-        unsigned int aack_prom_mode : 1;	/* Enable Promiscuous Mode */
-        unsigned int aack_ack_time : 1;	/* Reduce Acknowledgment Time */
-        unsigned int : 1;
-        unsigned int aack_upld_res_ft : 1;	/* Process Reserved Frames */
-        unsigned int aack_fltr_res_ft : 1;	/* Filter Reserved Frames */
-        unsigned int : 2;
-};
-
-#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1)
-
-/* symbolic names */
-
-#define AACK_ACK_TIME_12_SYM            0
-#define AACK_ACK_TIME_2_SYM             1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_1 */
-
-#define AACK_PROM_MODE                  1
-#define AACK_ACK_TIME                   2
-#define AACK_UPLD_RES_FT                4
-#define AACK_FLTR_RES_FT                5
-
-/* Transceiver Filter Tuning Control Register */
-#define FTN_CTRL                        _SFR_MEM8(0x158)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_FTN_CTRL {
-        unsigned int : 7;
-        unsigned int ftn_start : 1;	/* Start Calibration Loop of Filter Tuning Network */
-};
-
-#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* FTN_CTRL */
-
-#define FTN_START                       7
-
-/* Transceiver Center Frequency Calibration Control Register */
-#define PLL_CF                          _SFR_MEM8(0x15A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_CF {
-        unsigned int : 7;
-        unsigned int pll_cf_start : 1;	/* Start Center Frequency Calibration */
-};
-
-#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_CF */
-
-#define PLL_CF_START                    7
-
-/* Transceiver Delay Cell Calibration Control Register */
-#define PLL_DCU                         _SFR_MEM8(0x15B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_DCU {
-        unsigned int : 7;
-        unsigned int pll_dcu_start : 1;	/* Start Delay Cell Calibration */
-};
-
-#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_DCU */
-
-#define PLL_DCU_START                   7
-
-/* Device Identification Register (Part Number) */
-#define PART_NUM                        _SFR_MEM8(0x15C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PART_NUM {
-        unsigned int part_num : 8;	/* Part Number */
-};
-
-#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM)
-
-/* symbolic names */
-
-#define P_RFR2                          148
-
-#endif /* __ASSEMBLER__ */
-
-  /* PART_NUM */
-
-#define PART_NUM0                       0
-#define PART_NUM1                       1
-#define PART_NUM2                       2
-#define PART_NUM3                       3
-#define PART_NUM4                       4
-#define PART_NUM5                       5
-#define PART_NUM6                       6
-#define PART_NUM7                       7
-
-/* Device Identification Register (Version Number) */
-#define VERSION_NUM                     _SFR_MEM8(0x15D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VERSION_NUM {
-        unsigned int version_num : 8;	/* Version Number */
-};
-
-#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM)
-
-/* symbolic names */
-
-#define REV_A                           12
-#define REV_B                           1
-#define REV_C                           3
-#define REV_D                           4
-
-#endif /* __ASSEMBLER__ */
-
-  /* VERSION_NUM */
-
-#define VERSION_NUM0                    0
-#define VERSION_NUM1                    1
-#define VERSION_NUM2                    2
-#define VERSION_NUM3                    3
-#define VERSION_NUM4                    4
-#define VERSION_NUM5                    5
-#define VERSION_NUM6                    6
-#define VERSION_NUM7                    7
-
-/* Device Identification Register (Manufacture ID Low Byte) */
-#define MAN_ID_0                        _SFR_MEM8(0x15E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_0 {
-        unsigned int man_id_00 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_01 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_02 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_03 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_04 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_05 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_06 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_07 : 1;	/* Manufacturer ID (Low Byte) */
-};
-
-#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_0                    31
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_0 */
-
-#define MAN_ID_00                       0
-#define MAN_ID_01                       1
-#define MAN_ID_02                       2
-#define MAN_ID_03                       3
-#define MAN_ID_04                       4
-#define MAN_ID_05                       5
-#define MAN_ID_06                       6
-#define MAN_ID_07                       7
-
-/* Device Identification Register (Manufacture ID High Byte) */
-#define MAN_ID_1                        _SFR_MEM8(0x15F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_1 {
-        unsigned int man_id_ : 8;	/* Manufacturer ID (High Byte) */
-};
-
-#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_1                    0
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_1 */
-
-#define MAN_ID_10                       0
-#define MAN_ID_11                       1
-#define MAN_ID_12                       2
-#define MAN_ID_13                       3
-#define MAN_ID_14                       4
-#define MAN_ID_15                       5
-#define MAN_ID_16                       6
-#define MAN_ID_17                       7
-
-/* Transceiver MAC Short Address Register (Low Byte) */
-#define SHORT_ADDR_0                    _SFR_MEM8(0x160)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_0 {
-        unsigned int short_addr_00 : 1;	/* MAC Short Address */
-        unsigned int short_addr_01 : 1;	/* MAC Short Address */
-        unsigned int short_addr_02 : 1;	/* MAC Short Address */
-        unsigned int short_addr_03 : 1;	/* MAC Short Address */
-        unsigned int short_addr_04 : 1;	/* MAC Short Address */
-        unsigned int short_addr_05 : 1;	/* MAC Short Address */
-        unsigned int short_addr_06 : 1;	/* MAC Short Address */
-        unsigned int short_addr_07 : 1;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_0 */
-
-#define SHORT_ADDR_00                   0
-#define SHORT_ADDR_01                   1
-#define SHORT_ADDR_02                   2
-#define SHORT_ADDR_03                   3
-#define SHORT_ADDR_04                   4
-#define SHORT_ADDR_05                   5
-#define SHORT_ADDR_06                   6
-#define SHORT_ADDR_07                   7
-
-/* Transceiver MAC Short Address Register (High Byte) */
-#define SHORT_ADDR_1                    _SFR_MEM8(0x161)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_1 {
-        unsigned int short_addr_ : 8;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_1 */
-
-#define SHORT_ADDR_10                   0
-#define SHORT_ADDR_11                   1
-#define SHORT_ADDR_12                   2
-#define SHORT_ADDR_13                   3
-#define SHORT_ADDR_14                   4
-#define SHORT_ADDR_15                   5
-#define SHORT_ADDR_16                   6
-#define SHORT_ADDR_17                   7
-
-/* Transceiver Personal Area Network ID Register (Low Byte) */
-#define PAN_ID_0                        _SFR_MEM8(0x162)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_0 {
-        unsigned int pan_id_00 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_01 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_02 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_03 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_04 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_05 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_06 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_07 : 1;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_0 */
-
-#define PAN_ID_00                       0
-#define PAN_ID_01                       1
-#define PAN_ID_02                       2
-#define PAN_ID_03                       3
-#define PAN_ID_04                       4
-#define PAN_ID_05                       5
-#define PAN_ID_06                       6
-#define PAN_ID_07                       7
-
-/* Transceiver Personal Area Network ID Register (High Byte) */
-#define PAN_ID_1                        _SFR_MEM8(0x163)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_1 {
-        unsigned int pan_id_ : 8;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_1 */
-
-#define PAN_ID_10                       0
-#define PAN_ID_11                       1
-#define PAN_ID_12                       2
-#define PAN_ID_13                       3
-#define PAN_ID_14                       4
-#define PAN_ID_15                       5
-#define PAN_ID_16                       6
-#define PAN_ID_17                       7
-
-/* Transceiver MAC IEEE Address Register 0 */
-#define IEEE_ADDR_0                     _SFR_MEM8(0x164)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_0 {
-        unsigned int ieee_addr_00 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_01 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_02 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_03 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_04 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_05 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_06 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_07 : 1;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_0 */
-
-#define IEEE_ADDR_00                    0
-#define IEEE_ADDR_01                    1
-#define IEEE_ADDR_02                    2
-#define IEEE_ADDR_03                    3
-#define IEEE_ADDR_04                    4
-#define IEEE_ADDR_05                    5
-#define IEEE_ADDR_06                    6
-#define IEEE_ADDR_07                    7
-
-/* Transceiver MAC IEEE Address Register 1 */
-#define IEEE_ADDR_1                     _SFR_MEM8(0x165)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_1 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_1 */
-
-#define IEEE_ADDR_10                    0
-#define IEEE_ADDR_11                    1
-#define IEEE_ADDR_12                    2
-#define IEEE_ADDR_13                    3
-#define IEEE_ADDR_14                    4
-#define IEEE_ADDR_15                    5
-#define IEEE_ADDR_16                    6
-#define IEEE_ADDR_17                    7
-
-/* Transceiver MAC IEEE Address Register 2 */
-#define IEEE_ADDR_2                     _SFR_MEM8(0x166)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_2 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_2 */
-
-#define IEEE_ADDR_20                    0
-#define IEEE_ADDR_21                    1
-#define IEEE_ADDR_22                    2
-#define IEEE_ADDR_23                    3
-#define IEEE_ADDR_24                    4
-#define IEEE_ADDR_25                    5
-#define IEEE_ADDR_26                    6
-#define IEEE_ADDR_27                    7
-
-/* Transceiver MAC IEEE Address Register 3 */
-#define IEEE_ADDR_3                     _SFR_MEM8(0x167)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_3 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_3 */
-
-#define IEEE_ADDR_30                    0
-#define IEEE_ADDR_31                    1
-#define IEEE_ADDR_32                    2
-#define IEEE_ADDR_33                    3
-#define IEEE_ADDR_34                    4
-#define IEEE_ADDR_35                    5
-#define IEEE_ADDR_36                    6
-#define IEEE_ADDR_37                    7
-
-/* Transceiver MAC IEEE Address Register 4 */
-#define IEEE_ADDR_4                     _SFR_MEM8(0x168)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_4 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_4 */
-
-#define IEEE_ADDR_40                    0
-#define IEEE_ADDR_41                    1
-#define IEEE_ADDR_42                    2
-#define IEEE_ADDR_43                    3
-#define IEEE_ADDR_44                    4
-#define IEEE_ADDR_45                    5
-#define IEEE_ADDR_46                    6
-#define IEEE_ADDR_47                    7
-
-/* Transceiver MAC IEEE Address Register 5 */
-#define IEEE_ADDR_5                     _SFR_MEM8(0x169)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_5 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_5 */
-
-#define IEEE_ADDR_50                    0
-#define IEEE_ADDR_51                    1
-#define IEEE_ADDR_52                    2
-#define IEEE_ADDR_53                    3
-#define IEEE_ADDR_54                    4
-#define IEEE_ADDR_55                    5
-#define IEEE_ADDR_56                    6
-#define IEEE_ADDR_57                    7
-
-/* Transceiver MAC IEEE Address Register 6 */
-#define IEEE_ADDR_6                     _SFR_MEM8(0x16A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_6 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_6 */
-
-#define IEEE_ADDR_60                    0
-#define IEEE_ADDR_61                    1
-#define IEEE_ADDR_62                    2
-#define IEEE_ADDR_63                    3
-#define IEEE_ADDR_64                    4
-#define IEEE_ADDR_65                    5
-#define IEEE_ADDR_66                    6
-#define IEEE_ADDR_67                    7
-
-/* Transceiver MAC IEEE Address Register 7 */
-#define IEEE_ADDR_7                     _SFR_MEM8(0x16B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_7 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_7 */
-
-#define IEEE_ADDR_70                    0
-#define IEEE_ADDR_71                    1
-#define IEEE_ADDR_72                    2
-#define IEEE_ADDR_73                    3
-#define IEEE_ADDR_74                    4
-#define IEEE_ADDR_75                    5
-#define IEEE_ADDR_76                    6
-#define IEEE_ADDR_77                    7
-
-/* Transceiver Extended Operating Mode Control Register */
-#define XAH_CTRL_0                      _SFR_MEM8(0x16C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_0 {
-        unsigned int slotted_operation : 1;	/* Set Slotted Acknowledgment */
-        unsigned int max_csma_retries : 3;	/* Maximum Number of CSMA-CA Procedure Repetition Attempts */
-        unsigned int max_frame_retries : 4;	/* Maximum Number of Frame Re-transmission Attempts */
-};
-
-#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0)
-
-/* symbolic names */
-
-#define SLOTTED_OP_DIS                  0
-#define SLOTTED_OP_EN                   1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_0 */
-
-#define SLOTTED_OPERATION               0
-#define MAX_CSMA_RETRIES0               1
-#define MAX_CSMA_RETRIES1               2
-#define MAX_CSMA_RETRIES2               3
-#define MAX_FRAME_RETRIES0              4
-#define MAX_FRAME_RETRIES1              5
-#define MAX_FRAME_RETRIES2              6
-#define MAX_FRAME_RETRIES3              7
-
-/* Transceiver CSMA-CA Random Number Generator Seed Register */
-#define CSMA_SEED_0                     _SFR_MEM8(0x16D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_0 {
-        unsigned int csma_seed_00 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_01 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_02 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_03 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_04 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_05 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_06 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_07 : 1;	/* Seed Value for CSMA Random Number Generator */
-};
-
-#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_0 */
-
-#define CSMA_SEED_00                    0
-#define CSMA_SEED_01                    1
-#define CSMA_SEED_02                    2
-#define CSMA_SEED_03                    3
-#define CSMA_SEED_04                    4
-#define CSMA_SEED_05                    5
-#define CSMA_SEED_06                    6
-#define CSMA_SEED_07                    7
-
-/* Transceiver Acknowledgment Frame Control Register 2 */
-#define CSMA_SEED_1                     _SFR_MEM8(0x16E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_1 {
-        unsigned int csma_seed_1 : 3;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int aack_i_am_coord : 1;	/* Set Personal Area Network Coordinator */
-        unsigned int aack_dis_ack : 1;	/* Disable Acknowledgment Frame Transmission */
-        unsigned int aack_set_pd : 1;	/* Set Frame Pending Sub-field */
-        unsigned int aack_fvn_mode : 2;	/* Acknowledgment Frame Filter Mode */
-};
-
-#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_1 */
-
-#define CSMA_SEED_10                    0
-#define CSMA_SEED_11                    1
-#define CSMA_SEED_12                    2
-#define AACK_I_AM_COORD                 3
-#define AACK_DIS_ACK                    4
-#define AACK_SET_PD                     5
-#define AACK_FVN_MODE0                  6
-#define AACK_FVN_MODE1                  7
-
-/* Transceiver CSMA-CA Back-off Exponent Control Register */
-#define CSMA_BE                         _SFR_MEM8(0x16F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_BE {
-        unsigned int min_be : 4;	/* Minimum Back-off Exponent */
-        unsigned int max_be : 4;	/* Maximum Back-off Exponent */
-};
-
-#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_BE */
-
-#define MIN_BE0                         0
-#define MIN_BE1                         1
-#define MIN_BE2                         2
-#define MIN_BE3                         3
-#define MAX_BE0                         4
-#define MAX_BE1                         5
-#define MAX_BE2                         6
-#define MAX_BE3                         7
-
-/* Transceiver Digital Test Control Register */
-#define TST_CTRL_DIGI                   _SFR_MEM8(0x176)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_CTRL_DIGI {
-        unsigned int tst_ctrl_dig : 4;	/* Digital Test Controller Register */
-        unsigned int : 4;
-};
-
-#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_CTRL_DIGI */
-
-#define TST_CTRL_DIG0                   0
-#define TST_CTRL_DIG1                   1
-#define TST_CTRL_DIG2                   2
-#define TST_CTRL_DIG3                   3
-
-/* Transceiver Received Frame Length Register */
-#define TST_RX_LENGTH                   _SFR_MEM8(0x17B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_RX_LENGTH {
-        unsigned int rx_length : 8;	/* Received Frame Length */
-};
-
-#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_RX_LENGTH */
-
-#define RX_LENGTH0                      0
-#define RX_LENGTH1                      1
-#define RX_LENGTH2                      2
-#define RX_LENGTH3                      3
-#define RX_LENGTH4                      4
-#define RX_LENGTH5                      5
-#define RX_LENGTH6                      6
-#define RX_LENGTH7                      7
-
-/* Transceiver Automatic Gain Control and Test Register */
-#define TST_AGC                         _SFR_MEM8(0x17C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_AGC {
-        unsigned int gc : 2;	/* Receiver Gain Control Word */
-        unsigned int agc_hold : 1;	/* Select AGC Hold Function */
-        unsigned int agc_off : 1;	/* Disable AGC Regulation */
-        unsigned int agc_rst : 1;	/* Reset AGC Gain */
-        unsigned int agc_hold_sel : 1;	/* Enable AGC Hold Function */
-        unsigned int : 2;
-};
-
-#define TST_AGC_struct _SFR_MEM8_STRUCT(0x17c, struct __reg_TST_AGC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_AGC */
-
-#define GC0                             0
-#define GC1                             1
-#define AGC_HOLD                        2
-#define AGC_OFF                         3
-#define AGC_RST                         4
-#define AGC_HOLD_SEL                    5
-
-/* Transceiver Sigma-Delta Modulator Control and Test Register */
-#define TST_SDM                         _SFR_MEM8(0x17D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_SDM {
-        unsigned int : 4;
-        unsigned int tx_rx_sel : 1;	/* Select Transmit/Receive Control Signal */
-        unsigned int tx_rx : 1;	/* Switch between Transmit and Receive */
-        unsigned int mod : 1;	/* Select Modulation Signal Type */
-        unsigned int mod_sel : 1;	/* Select Modulation Data Source */
-};
-
-#define TST_SDM_struct _SFR_MEM8_STRUCT(0x17d, struct __reg_TST_SDM)
-
-#endif /* __ASSEMBLER__ */
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
 
-  /* TST_SDM */
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
 
-#define TX_RX_SEL                       4
-#define TX_RX                           5
-#define MOD                             6
-#define MOD_SEL                         7
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define MUX5    3
+#define ACCH    4
+#define REFOK   5
+#define AVDDOK  7
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC8D   0
+#define ADC9D   1
+#define ADC10D  2
+#define ADC11D  3
+#define ADC12D  4
+#define ADC13D  5
+#define ADC14D  6
+#define ADC15D  7
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1C0  2
+#define COM1C1  3
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1C   5
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define WGM30   0
+#define WGM31   1
+#define COM3C0  2
+#define COM3C1  3
+#define COM3B0  4
+#define COM3B1  5
+#define COM3A0  6
+#define COM3A1  7
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define CS30    0
+#define CS31    1
+#define CS32    2
+#define WGM32   3
+#define WGM33   4
+#define ICES3   6
+#define ICNC3   7
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3C   5
+#define FOC3B   6
+#define FOC3A   7
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define WGM40   0
+#define WGM41   1
+#define COM4C0  2
+#define COM4C1  3
+#define COM4B0  4
+#define COM4B1  5
+#define COM4A0  6
+#define COM4A1  7
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define CS40    0
+#define CS41    1
+#define CS42    2
+#define WGM42   3
+#define WGM43   4
+#define ICES4   6
+#define ICNC4   7
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4C   5
+#define FOC4B   6
+#define FOC4A   7
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+#define EXCLKAMR 7
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+#define IRQ_MASK1 _SFR_MEM8(0xBE)
+#define TX_START_EN 0
+#define MAF_0_AMI_EN 1
+#define MAF_1_AMI_EN 2
+#define MAF_2_AMI_EN 3
+#define MAF_3_AMI_EN 4
+
+#define IRQ_STATUS1 _SFR_MEM8(0xBF)
+#define TX_START 0
+#define MAF_0_AMI 1
+#define MAF_1_AMI 2
+#define MAF_2_AMI 3
+#define MAF_3_AMI 4
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+#define UCPHA0  1
+#define UDORD0  2
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+#define UCSR1B  _SFR_MEM8(0xC9)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+#define UCPHA1  1
+#define UDORD1  2
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0xCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define SCRSTRLL _SFR_MEM8(0xD7)
+#define SCRSTRLL0 0
+#define SCRSTRLL1 1
+#define SCRSTRLL2 2
+#define SCRSTRLL3 3
+#define SCRSTRLL4 4
+#define SCRSTRLL5 5
+#define SCRSTRLL6 6
+#define SCRSTRLL7 7
+
+#define SCRSTRLH _SFR_MEM8(0xD8)
+#define SCRSTRLH0 0
+#define SCRSTRLH1 1
+#define SCRSTRLH2 2
+#define SCRSTRLH3 3
+#define SCRSTRLH4 4
+#define SCRSTRLH5 5
+#define SCRSTRLH6 6
+#define SCRSTRLH7 7
+
+#define SCRSTRHL _SFR_MEM8(0xD9)
+#define SCRSTRHL0 0
+#define SCRSTRHL1 1
+#define SCRSTRHL2 2
+#define SCRSTRHL3 3
+#define SCRSTRHL4 4
+#define SCRSTRHL5 5
+#define SCRSTRHL6 6
+#define SCRSTRHL7 7
+
+#define SCRSTRHH _SFR_MEM8(0xDA)
+#define SCRSTRHH0 0
+#define SCRSTRHH1 1
+#define SCRSTRHH2 2
+#define SCRSTRHH3 3
+#define SCRSTRHH4 4
+#define SCRSTRHH5 5
+#define SCRSTRHH6 6
+#define SCRSTRHH7 7
+
+#define SCCSR   _SFR_MEM8(0xDB)
+#define SCCS10  0
+#define SCCS11  1
+#define SCCS20  2
+#define SCCS21  3
+#define SCCS30  4
+#define SCCS31  5
+
+#define SCCR0   _SFR_MEM8(0xDC)
+#define SCCMP1  0
+#define SCCMP2  1
+#define SCCMP3  2
+#define SCTSE   3
+#define SCCKSEL 4
+#define SCEN    5
+#define SCMBTS  6
+#define SCRES   7
+
+#define SCCR1   _SFR_MEM8(0xDD)
+#define SCENBO  0
+#define SCEECLK 1
+#define SCCKDIV0 2
+#define SCCKDIV1 3
+#define SCCKDIV2 4
+#define SCBTSM  5
+#define Res5    6
+#define Res6    7
+
+#define SCSR    _SFR_MEM8(0xDE)
+#define SCBSY   0
+
+#define SCIRQM  _SFR_MEM8(0xDF)
+#define IRQMCP1 0
+#define IRQMCP2 1
+#define IRQMCP3 2
+#define IRQMOF  3
+#define IRQMBO  4
+
+#define SCIRQS  _SFR_MEM8(0xE0)
+#define IRQSCP1 0
+#define IRQSCP2 1
+#define IRQSCP3 2
+#define IRQSOF  3
+#define IRQSBO  4
+
+#define SCCNTLL _SFR_MEM8(0xE1)
+#define SCCNTLL0 0
+#define SCCNTLL1 1
+#define SCCNTLL2 2
+#define SCCNTLL3 3
+#define SCCNTLL4 4
+#define SCCNTLL5 5
+#define SCCNTLL6 6
+#define SCCNTLL7 7
+
+#define SCCNTLH _SFR_MEM8(0xE2)
+#define SCCNTLH0 0
+#define SCCNTLH1 1
+#define SCCNTLH2 2
+#define SCCNTLH3 3
+#define SCCNTLH4 4
+#define SCCNTLH5 5
+#define SCCNTLH6 6
+#define SCCNTLH7 7
+
+#define SCCNTHL _SFR_MEM8(0xE3)
+#define SCCNTHL0 0
+#define SCCNTHL1 1
+#define SCCNTHL2 2
+#define SCCNTHL3 3
+#define SCCNTHL4 4
+#define SCCNTHL5 5
+#define SCCNTHL6 6
+#define SCCNTHL7 7
+
+#define SCCNTHH _SFR_MEM8(0xE4)
+#define SCCNTHH0 0
+#define SCCNTHH1 1
+#define SCCNTHH2 2
+#define SCCNTHH3 3
+#define SCCNTHH4 4
+#define SCCNTHH5 5
+#define SCCNTHH6 6
+#define SCCNTHH7 7
+
+#define SCBTSRLL _SFR_MEM8(0xE5)
+#define SCBTSRLL0 0
+#define SCBTSRLL1 1
+#define SCBTSRLL2 2
+#define SCBTSRLL3 3
+#define SCBTSRLL4 4
+#define SCBTSRLL5 5
+#define SCBTSRLL6 6
+#define SCBTSRLL7 7
+
+#define SCBTSRLH _SFR_MEM8(0xE6)
+#define SCBTSRLH0 0
+#define SCBTSRLH1 1
+#define SCBTSRLH2 2
+#define SCBTSRLH3 3
+#define SCBTSRLH4 4
+#define SCBTSRLH5 5
+#define SCBTSRLH6 6
+#define SCBTSRLH7 7
+
+#define SCBTSRHL _SFR_MEM8(0xE7)
+#define SCBTSRHL0 0
+#define SCBTSRHL1 1
+#define SCBTSRHL2 2
+#define SCBTSRHL3 3
+#define SCBTSRHL4 4
+#define SCBTSRHL5 5
+#define SCBTSRHL6 6
+#define SCBTSRHL7 7
+
+#define SCBTSRHH _SFR_MEM8(0xE8)
+#define SCBTSRHH0 0
+#define SCBTSRHH1 1
+#define SCBTSRHH2 2
+#define SCBTSRHH3 3
+#define SCBTSRHH4 4
+#define SCBTSRHH5 5
+#define SCBTSRHH6 6
+#define SCBTSRHH7 7
+
+#define SCTSRLL _SFR_MEM8(0xE9)
+#define SCTSRLL0 0
+#define SCTSRLL1 1
+#define SCTSRLL2 2
+#define SCTSRLL3 3
+#define SCTSRLL4 4
+#define SCTSRLL5 5
+#define SCTSRLL6 6
+#define SCTSRLL7 7
+
+#define SCTSRLH _SFR_MEM8(0xEA)
+#define SCTSRLH0 0
+#define SCTSRLH1 1
+#define SCTSRLH2 2
+#define SCTSRLH3 3
+#define SCTSRLH4 4
+#define SCTSRLH5 5
+#define SCTSRLH6 6
+#define SCTSRLH7 7
+
+#define SCTSRHL _SFR_MEM8(0xEB)
+#define SCTSRHL0 0
+#define SCTSRHL1 1
+#define SCTSRHL2 2
+#define SCTSRHL3 3
+#define SCTSRHL4 4
+#define SCTSRHL5 5
+#define SCTSRHL6 6
+#define SCTSRHL7 7
+
+#define SCTSRHH _SFR_MEM8(0xEC)
+#define SCTSRHH0 0
+#define SCTSRHH1 1
+#define SCTSRHH2 2
+#define SCTSRHH3 3
+#define SCTSRHH4 4
+#define SCTSRHH5 5
+#define SCTSRHH6 6
+#define SCTSRHH7 7
+
+#define SCOCR3LL _SFR_MEM8(0xED)
+#define SCOCR3LL0 0
+#define SCOCR3LL1 1
+#define SCOCR3LL2 2
+#define SCOCR3LL3 3
+#define SCOCR3LL4 4
+#define SCOCR3LL5 5
+#define SCOCR3LL6 6
+#define SCOCR3LL7 7
+
+#define SCOCR3LH _SFR_MEM8(0xEE)
+#define SCOCR3LH0 0
+#define SCOCR3LH1 1
+#define SCOCR3LH2 2
+#define SCOCR3LH3 3
+#define SCOCR3LH4 4
+#define SCOCR3LH5 5
+#define SCOCR3LH6 6
+#define SCOCR3LH7 7
+
+#define SCOCR3HL _SFR_MEM8(0xEF)
+#define SCOCR3HL0 0
+#define SCOCR3HL1 1
+#define SCOCR3HL2 2
+#define SCOCR3HL3 3
+#define SCOCR3HL4 4
+#define SCOCR3HL5 5
+#define SCOCR3HL6 6
+#define SCOCR3HL7 7
+
+#define SCOCR3HH _SFR_MEM8(0xF0)
+#define SCOCR3HH0 0
+#define SCOCR3HH1 1
+#define SCOCR3HH2 2
+#define SCOCR3HH3 3
+#define SCOCR3HH4 4
+#define SCOCR3HH5 5
+#define SCOCR3HH6 6
+#define SCOCR3HH7 7
+
+#define SCOCR2LL _SFR_MEM8(0xF1)
+#define SCOCR2LL0 0
+#define SCOCR2LL1 1
+#define SCOCR2LL2 2
+#define SCOCR2LL3 3
+#define SCOCR2LL4 4
+#define SCOCR2LL5 5
+#define SCOCR2LL6 6
+#define SCOCR2LL7 7
+
+#define SCOCR2LH _SFR_MEM8(0xF2)
+#define SCOCR2LH0 0
+#define SCOCR2LH1 1
+#define SCOCR2LH2 2
+#define SCOCR2LH3 3
+#define SCOCR2LH4 4
+#define SCOCR2LH5 5
+#define SCOCR2LH6 6
+#define SCOCR2LH7 7
+
+#define SCOCR2HL _SFR_MEM8(0xF3)
+#define SCOCR2HL0 0
+#define SCOCR2HL1 1
+#define SCOCR2HL2 2
+#define SCOCR2HL3 3
+#define SCOCR2HL4 4
+#define SCOCR2HL5 5
+#define SCOCR2HL6 6
+#define SCOCR2HL7 7
+
+#define SCOCR2HH _SFR_MEM8(0xF4)
+#define SCOCR2HH0 0
+#define SCOCR2HH1 1
+#define SCOCR2HH2 2
+#define SCOCR2HH3 3
+#define SCOCR2HH4 4
+#define SCOCR2HH5 5
+#define SCOCR2HH6 6
+#define SCOCR2HH7 7
+
+#define SCOCR1LL _SFR_MEM8(0xF5)
+#define SCOCR1LL0 0
+#define SCOCR1LL1 1
+#define SCOCR1LL2 2
+#define SCOCR1LL3 3
+#define SCOCR1LL4 4
+#define SCOCR1LL5 5
+#define SCOCR1LL6 6
+#define SCOCR1LL7 7
+
+#define SCOCR1LH _SFR_MEM8(0xF6)
+#define SCOCR1LH0 0
+#define SCOCR1LH1 1
+#define SCOCR1LH2 2
+#define SCOCR1LH3 3
+#define SCOCR1LH4 4
+#define SCOCR1LH5 5
+#define SCOCR1LH6 6
+#define SCOCR1LH7 7
+
+#define SCOCR1HL _SFR_MEM8(0xF7)
+#define SCOCR1HL0 0
+#define SCOCR1HL1 1
+#define SCOCR1HL2 2
+#define SCOCR1HL3 3
+#define SCOCR1HL4 4
+#define SCOCR1HL5 5
+#define SCOCR1HL6 6
+#define SCOCR1HL7 7
+
+#define SCOCR1HH _SFR_MEM8(0xF8)
+#define SCOCR1HH0 0
+#define SCOCR1HH1 1
+#define SCOCR1HH2 2
+#define SCOCR1HH3 3
+#define SCOCR1HH4 4
+#define SCOCR1HH5 5
+#define SCOCR1HH6 6
+#define SCOCR1HH7 7
+
+#define SCTSTRLL _SFR_MEM8(0xF9)
+#define SCTSTRLL0 0
+#define SCTSTRLL1 1
+#define SCTSTRLL2 2
+#define SCTSTRLL3 3
+#define SCTSTRLL4 4
+#define SCTSTRLL5 5
+#define SCTSTRLL6 6
+#define SCTSTRLL7 7
+
+#define SCTSTRLH _SFR_MEM8(0xFA)
+#define SCTSTRLH0 0
+#define SCTSTRLH1 1
+#define SCTSTRLH2 2
+#define SCTSTRLH3 3
+#define SCTSTRLH4 4
+#define SCTSTRLH5 5
+#define SCTSTRLH6 6
+#define SCTSTRLH7 7
+
+#define SCTSTRHL _SFR_MEM8(0xFB)
+#define SCTSTRHL0 0
+#define SCTSTRHL1 1
+#define SCTSTRHL2 2
+#define SCTSTRHL3 3
+#define SCTSTRHL4 4
+#define SCTSTRHL5 5
+#define SCTSTRHL6 6
+#define SCTSTRHL7 7
+
+#define SCTSTRHH _SFR_MEM8(0xFC)
+#define SCTSTRHH0 0
+#define SCTSTRHH1 1
+#define SCTSTRHH2 2
+#define SCTSTRHH3 3
+#define SCTSTRHH4 4
+#define SCTSTRHH5 5
+#define SCTSTRHH6 6
+#define SCTSTRHH7 7
+
+/* Reserved [0xFD..0x10B] */
+
+#define MAFCR0  _SFR_MEM8(0x10C)
+#define MAF0EN  0
+#define MAF1EN  1
+#define MAF2EN  2
+#define MAF3EN  3
+
+#define MAFCR1  _SFR_MEM8(0x10D)
+#define AACK_0_I_AM_COORD 0
+#define AACK_0_SET_PD 1
+#define AACK_1_I_AM_COORD 2
+#define AACK_1_SET_PD 3
+#define AACK_2_I_AM_COORD 4
+#define AACK_2_SET_PD 5
+#define AACK_3_I_AM_COORD 6
+#define AACK_3_SET_PD 7
+
+#define MAFSA0L _SFR_MEM8(0x10E)
+#define MAFSA0L0 0
+#define MAFSA0L1 1
+#define MAFSA0L2 2
+#define MAFSA0L3 3
+#define MAFSA0L4 4
+#define MAFSA0L5 5
+#define MAFSA0L6 6
+#define MAFSA0L7 7
+
+#define MAFSA0H _SFR_MEM8(0x10F)
+#define MAFSA0H0 0
+#define MAFSA0H1 1
+#define MAFSA0H2 2
+#define MAFSA0H3 3
+#define MAFSA0H4 4
+#define MAFSA0H5 5
+#define MAFSA0H6 6
+#define MAFSA0H7 7
+
+#define MAFPA0L _SFR_MEM8(0x110)
+#define MAFPA0L0 0
+#define MAFPA0L1 1
+#define MAFPA0L2 2
+#define MAFPA0L3 3
+#define MAFPA0L4 4
+#define MAFPA0L5 5
+#define MAFPA0L6 6
+#define MAFPA0L7 7
+
+#define MAFPA0H _SFR_MEM8(0x111)
+#define MAFPA0H0 0
+#define MAFPA0H1 1
+#define MAFPA0H2 2
+#define MAFPA0H3 3
+#define MAFPA0H4 4
+#define MAFPA0H5 5
+#define MAFPA0H6 6
+#define MAFPA0H7 7
+
+#define MAFSA1L _SFR_MEM8(0x112)
+#define MAFSA1L0 0
+#define MAFSA1L1 1
+#define MAFSA1L2 2
+#define MAFSA1L3 3
+#define MAFSA1L4 4
+#define MAFSA1L5 5
+#define MAFSA1L6 6
+#define MAFSA1L7 7
+
+#define MAFSA1H _SFR_MEM8(0x113)
+#define MAFSA1H0 0
+#define MAFSA1H1 1
+#define MAFSA1H2 2
+#define MAFSA1H3 3
+#define MAFSA1H4 4
+#define MAFSA1H5 5
+#define MAFSA1H6 6
+#define MAFSA1H7 7
+
+#define MAFPA1L _SFR_MEM8(0x114)
+#define MAFPA1L0 0
+#define MAFPA1L1 1
+#define MAFPA1L2 2
+#define MAFPA1L3 3
+#define MAFPA1L4 4
+#define MAFPA1L5 5
+#define MAFPA1L6 6
+#define MAFPA1L7 7
+
+#define MAFPA1H _SFR_MEM8(0x115)
+#define MAFPA1H0 0
+#define MAFPA1H1 1
+#define MAFPA1H2 2
+#define MAFPA1H3 3
+#define MAFPA1H4 4
+#define MAFPA1H5 5
+#define MAFPA1H6 6
+#define MAFPA1H7 7
+
+#define MAFSA2L _SFR_MEM8(0x116)
+#define MAFSA2L0 0
+#define MAFSA2L1 1
+#define MAFSA2L2 2
+#define MAFSA2L3 3
+#define MAFSA2L4 4
+#define MAFSA2L5 5
+#define MAFSA2L6 6
+#define MAFSA2L7 7
+
+#define MAFSA2H _SFR_MEM8(0x117)
+#define MAFSA2H0 0
+#define MAFSA2H1 1
+#define MAFSA2H2 2
+#define MAFSA2H3 3
+#define MAFSA2H4 4
+#define MAFSA2H5 5
+#define MAFSA2H6 6
+#define MAFSA2H7 7
+
+#define MAFPA2L _SFR_MEM8(0x118)
+#define MAFPA2L0 0
+#define MAFPA2L1 1
+#define MAFPA2L2 2
+#define MAFPA2L3 3
+#define MAFPA2L4 4
+#define MAFPA2L5 5
+#define MAFPA2L6 6
+#define MAFPA2L7 7
+
+#define MAFPA2H _SFR_MEM8(0x119)
+#define MAFPA2H0 0
+#define MAFPA2H1 1
+#define MAFPA2H2 2
+#define MAFPA2H3 3
+#define MAFPA2H4 4
+#define MAFPA2H5 5
+#define MAFPA2H6 6
+#define MAFPA2H7 7
+
+#define MAFSA3L _SFR_MEM8(0x11A)
+#define MAFSA3L0 0
+#define MAFSA3L1 1
+#define MAFSA3L2 2
+#define MAFSA3L3 3
+#define MAFSA3L4 4
+#define MAFSA3L5 5
+#define MAFSA3L6 6
+#define MAFSA3L7 7
+
+#define MAFSA3H _SFR_MEM8(0x11B)
+#define MAFSA3H0 0
+#define MAFSA3H1 1
+#define MAFSA3H2 2
+#define MAFSA3H3 3
+#define MAFSA3H4 4
+#define MAFSA3H5 5
+#define MAFSA3H6 6
+#define MAFSA3H7 7
+
+#define MAFPA3L _SFR_MEM8(0x11C)
+#define MAFPA3L0 0
+#define MAFPA3L1 1
+#define MAFPA3L2 2
+#define MAFPA3L3 3
+#define MAFPA3L4 4
+#define MAFPA3L5 5
+#define MAFPA3L6 6
+#define MAFPA3L7 7
+
+#define MAFPA3H _SFR_MEM8(0x11D)
+#define MAFPA3H0 0
+#define MAFPA3H1 1
+#define MAFPA3H2 2
+#define MAFPA3H3 3
+#define MAFPA3H4 4
+#define MAFPA3H5 5
+#define MAFPA3H6 6
+#define MAFPA3H7 7
+
+/* Reserved [0x11E..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define WGM50   0
+#define WGM51   1
+#define COM5C0  2
+#define COM5C1  3
+#define COM5B0  4
+#define COM5B1  5
+#define COM5A0  6
+#define COM5A1  7
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define CS50    0
+#define CS51    1
+#define CS52    2
+#define WGM52   3
+#define WGM53   4
+#define ICES5   6
+#define ICNC5   7
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5C   5
+#define FOC5B   6
+#define FOC5A   7
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E] */
+
+#define LLCR    _SFR_MEM8(0x12F)
+#define LLENCAL 0
+#define LLSHORT 1
+#define LLTCO   2
+#define LLCAL   3
+#define LLCOMP  4
+#define LLDONE  5
+
+#define LLDRL   _SFR_MEM8(0x130)
+#define LLDRL0  0
+#define LLDRL1  1
+#define LLDRL2  2
+#define LLDRL3  3
+
+#define LLDRH   _SFR_MEM8(0x131)
+#define LLDRH0  0
+#define LLDRH1  1
+#define LLDRH2  2
+#define LLDRH3  3
+#define LLDRH4  4
+
+#define DRTRAM3 _SFR_MEM8(0x132)
+#define ENDRT   4
+#define DRTSWOK 5
+
+#define DRTRAM2 _SFR_MEM8(0x133)
+
+#define DRTRAM1 _SFR_MEM8(0x134)
+
+#define DRTRAM0 _SFR_MEM8(0x135)
+
+#define DPDS0   _SFR_MEM8(0x136)
+#define PBDRV0  0
+#define PBDRV1  1
+#define PDDRV0  2
+#define PDDRV1  3
+#define PEDRV0  4
+#define PEDRV1  5
+#define PFDRV0  6
+#define PFDRV1  7
+
+#define DPDS1   _SFR_MEM8(0x137)
+#define PGDRV0  0
+#define PGDRV1  1
+
+#define PARCR   _SFR_MEM8(0x138)
+#define PARUFI  0
+#define PARDFI  1
+#define PALTU0  2
+#define PALTU1  3
+#define PALTU2  4
+#define PALTD0  5
+#define PALTD1  6
+#define PALTD2  7
+
+#define TRXPR   _SFR_MEM8(0x139)
+#define TRXRST  0
+#define SLPTR   1
+
+/* Reserved [0x13A..0x13B] */
+
+#define AES_CTRL _SFR_MEM8(0x13C)
+#define AES_IM  2
+#define AES_DIR 3
+#define AES_MODE 5
+#define AES_REQUEST 7
+
+#define AES_STATUS _SFR_MEM8(0x13D)
+#define AES_DONE 0
+#define AES_ER  7
+
+#define AES_STATE _SFR_MEM8(0x13E)
+#define AES_STATE0 0
+#define AES_STATE1 1
+#define AES_STATE2 2
+#define AES_STATE3 3
+#define AES_STATE4 4
+#define AES_STATE5 5
+#define AES_STATE6 6
+#define AES_STATE7 7
+
+#define AES_KEY _SFR_MEM8(0x13F)
+#define AES_KEY0 0
+#define AES_KEY1 1
+#define AES_KEY2 2
+#define AES_KEY3 3
+#define AES_KEY4 4
+#define AES_KEY5 5
+#define AES_KEY6 6
+#define AES_KEY7 7
+
+/* Reserved [0x140] */
+
+#define TRX_STATUS _SFR_MEM8(0x141)
+#define TRX_STATUS0 0
+#define TRX_STATUS1 1
+#define TRX_STATUS2 2
+#define TRX_STATUS3 3
+#define TRX_STATUS4 4
+#define TST_STATUS 5
+#define CCA_STATUS 6
+#define CCA_DONE 7
+
+#define TRX_STATE _SFR_MEM8(0x142)
+#define TRX_CMD0 0
+#define TRX_CMD1 1
+#define TRX_CMD2 2
+#define TRX_CMD3 3
+#define TRX_CMD4 4
+#define TRAC_STATUS0 5
+#define TRAC_STATUS1 6
+#define TRAC_STATUS2 7
+
+#define TRX_CTRL_0 _SFR_MEM8(0x143)
+#define PMU_IF_INV 4
+#define PMU_START 5
+#define PMU_EN  6
+#define Res7    7
+
+#define TRX_CTRL_1 _SFR_MEM8(0x144)
+#define PLL_TX_FLT 4
+#define TX_AUTO_CRC_ON 5
+#define IRQ_2_EXT_EN 6
+#define PA_EXT_EN 7
+
+#define PHY_TX_PWR _SFR_MEM8(0x145)
+#define TX_PWR0 0
+#define TX_PWR1 1
+#define TX_PWR2 2
+#define TX_PWR3 3
+
+#define PHY_RSSI _SFR_MEM8(0x146)
+#define RSSI0   0
+#define RSSI1   1
+#define RSSI2   2
+#define RSSI3   3
+#define RSSI4   4
+#define RND_VALUE0 5
+#define RND_VALUE1 6
+#define RX_CRC_VALID 7
+
+#define PHY_ED_LEVEL _SFR_MEM8(0x147)
+#define ED_LEVEL0 0
+#define ED_LEVEL1 1
+#define ED_LEVEL2 2
+#define ED_LEVEL3 3
+#define ED_LEVEL4 4
+#define ED_LEVEL5 5
+#define ED_LEVEL6 6
+#define ED_LEVEL7 7
+
+#define PHY_CC_CCA _SFR_MEM8(0x148)
+#define CHANNEL0 0
+#define CHANNEL1 1
+#define CHANNEL2 2
+#define CHANNEL3 3
+#define CHANNEL4 4
+#define CCA_MODE0 5
+#define CCA_MODE1 6
+#define CCA_REQUEST 7
+
+#define CCA_THRES _SFR_MEM8(0x149)
+#define CCA_ED_THRES0 0
+#define CCA_ED_THRES1 1
+#define CCA_ED_THRES2 2
+#define CCA_ED_THRES3 3
+#define CCA_CS_THRES0 4
+#define CCA_CS_THRES1 5
+#define CCA_CS_THRES2 6
+#define CCA_CS_THRES3 7
+
+#define RX_CTRL _SFR_MEM8(0x14A)
+#define PDT_THRES0 0
+#define PDT_THRES1 1
+#define PDT_THRES2 2
+#define PDT_THRES3 3
+
+#define SFD_VALUE _SFR_MEM8(0x14B)
+#define SFD_VALUE0 0
+#define SFD_VALUE1 1
+#define SFD_VALUE2 2
+#define SFD_VALUE3 3
+#define SFD_VALUE4 4
+#define SFD_VALUE5 5
+#define SFD_VALUE6 6
+#define SFD_VALUE7 7
+
+#define TRX_CTRL_2 _SFR_MEM8(0x14C)
+#define OQPSK_DATA_RATE0 0
+#define OQPSK_DATA_RATE1 1
+#define RX_SAFE_MODE 7
+
+#define ANT_DIV _SFR_MEM8(0x14D)
+#define ANT_CTRL0 0
+#define ANT_CTRL1 1
+#define ANT_EXT_SW_EN 2
+#define ANT_DIV_EN 3
+#define ANT_SEL 7
+
+#define IRQ_MASK _SFR_MEM8(0x14E)
+#define PLL_LOCK_EN 0
+#define PLL_UNLOCK_EN 1
+#define RX_START_EN 2
+#define RX_END_EN 3
+#define CCA_ED_DONE_EN 4
+#define AMI_EN  5
+#define TX_END_EN 6
+#define AWAKE_EN 7
+
+#define IRQ_STATUS _SFR_MEM8(0x14F)
+#define PLL_LOCK 0
+#define PLL_UNLOCK 1
+#define RX_START 2
+#define RX_END  3
+#define CCA_ED_DONE 4
+#define AMI     5
+#define TX_END  6
+#define AWAKE   7
+
+#define VREG_CTRL _SFR_MEM8(0x150)
+#define DVDD_OK 2
+#define DVREG_EXT 3
+#define AVDD_OK 6
+#define AVREG_EXT 7
+
+#define BATMON  _SFR_MEM8(0x151)
+#define BATMON_VTH0 0
+#define BATMON_VTH1 1
+#define BATMON_VTH2 2
+#define BATMON_VTH3 3
+#define BATMON_HR 4
+#define BATMON_OK 5
+#define BAT_LOW_EN 6
+#define BAT_LOW 7
+
+#define XOSC_CTRL _SFR_MEM8(0x152)
+#define XTAL_TRIM0 0
+#define XTAL_TRIM1 1
+#define XTAL_TRIM2 2
+#define XTAL_TRIM3 3
+#define XTAL_MODE0 4
+#define XTAL_MODE1 5
+#define XTAL_MODE2 6
+#define XTAL_MODE3 7
+
+#define CC_CTRL_0 _SFR_MEM8(0x153)
+#define CC_NUMBER0 0
+#define CC_NUMBER1 1
+#define CC_NUMBER2 2
+#define CC_NUMBER3 3
+#define CC_NUMBER4 4
+#define CC_NUMBER5 5
+#define CC_NUMBER6 6
+#define CC_NUMBER7 7
+
+#define CC_CTRL_1 _SFR_MEM8(0x154)
+#define CC_BAND0 0
+#define CC_BAND1 1
+#define CC_BAND2 2
+#define CC_BAND3 3
+
+#define RX_SYN  _SFR_MEM8(0x155)
+#define RX_PDT_LEVEL0 0
+#define RX_PDT_LEVEL1 1
+#define RX_PDT_LEVEL2 2
+#define RX_PDT_LEVEL3 3
+#define RX_OVERRIDE 6
+#define RX_PDT_DIS 7
+
+#define TRX_RPC _SFR_MEM8(0x156)
+#define XAH_RPC_EN 0
+#define IPAN_RPC_EN 1
+#define PLL_RPC_EN 3
+#define PDT_RPC_EN 4
+#define RX_RPC_EN 5
+#define RX_RPC_CTRL0 6
+#define RX_RPC_CTRL1 7
+
+#define XAH_CTRL_1 _SFR_MEM8(0x157)
+#define AACK_PROM_MODE 1
+#define AACK_ACK_TIME 2
+#define AACK_UPLD_RES_FT 4
+#define AACK_FLTR_RES_FT 5
+
+#define FTN_CTRL _SFR_MEM8(0x158)
+#define FTN_START 7
+
+/* Reserved [0x159] */
+
+#define PLL_CF  _SFR_MEM8(0x15A)
+#define PLL_CF_START 7
+
+#define PLL_DCU _SFR_MEM8(0x15B)
+#define PLL_DCU_START 7
+
+#define PART_NUM _SFR_MEM8(0x15C)
+#define PART_NUM0 0
+#define PART_NUM1 1
+#define PART_NUM2 2
+#define PART_NUM3 3
+#define PART_NUM4 4
+#define PART_NUM5 5
+#define PART_NUM6 6
+#define PART_NUM7 7
+
+#define VERSION_NUM _SFR_MEM8(0x15D)
+#define VERSION_NUM0 0
+#define VERSION_NUM1 1
+#define VERSION_NUM2 2
+#define VERSION_NUM3 3
+#define VERSION_NUM4 4
+#define VERSION_NUM5 5
+#define VERSION_NUM6 6
+#define VERSION_NUM7 7
+
+#define MAN_ID_0 _SFR_MEM8(0x15E)
+#define MAN_ID_00 0
+#define MAN_ID_01 1
+#define MAN_ID_02 2
+#define MAN_ID_03 3
+#define MAN_ID_04 4
+#define MAN_ID_05 5
+#define MAN_ID_06 6
+#define MAN_ID_07 7
+
+#define MAN_ID_1 _SFR_MEM8(0x15F)
+#define MAN_ID_10 0
+#define MAN_ID_11 1
+#define MAN_ID_12 2
+#define MAN_ID_13 3
+#define MAN_ID_14 4
+#define MAN_ID_15 5
+#define MAN_ID_16 6
+#define MAN_ID_17 7
+
+#define SHORT_ADDR_0 _SFR_MEM8(0x160)
+#define SHORT_ADDR_00 0
+#define SHORT_ADDR_01 1
+#define SHORT_ADDR_02 2
+#define SHORT_ADDR_03 3
+#define SHORT_ADDR_04 4
+#define SHORT_ADDR_05 5
+#define SHORT_ADDR_06 6
+#define SHORT_ADDR_07 7
+
+#define SHORT_ADDR_1 _SFR_MEM8(0x161)
+#define SHORT_ADDR_10 0
+#define SHORT_ADDR_11 1
+#define SHORT_ADDR_12 2
+#define SHORT_ADDR_13 3
+#define SHORT_ADDR_14 4
+#define SHORT_ADDR_15 5
+#define SHORT_ADDR_16 6
+#define SHORT_ADDR_17 7
+
+#define PAN_ID_0 _SFR_MEM8(0x162)
+#define PAN_ID_00 0
+#define PAN_ID_01 1
+#define PAN_ID_02 2
+#define PAN_ID_03 3
+#define PAN_ID_04 4
+#define PAN_ID_05 5
+#define PAN_ID_06 6
+#define PAN_ID_07 7
+
+#define PAN_ID_1 _SFR_MEM8(0x163)
+#define PAN_ID_10 0
+#define PAN_ID_11 1
+#define PAN_ID_12 2
+#define PAN_ID_13 3
+#define PAN_ID_14 4
+#define PAN_ID_15 5
+#define PAN_ID_16 6
+#define PAN_ID_17 7
+
+#define IEEE_ADDR_0 _SFR_MEM8(0x164)
+#define IEEE_ADDR_00 0
+#define IEEE_ADDR_01 1
+#define IEEE_ADDR_02 2
+#define IEEE_ADDR_03 3
+#define IEEE_ADDR_04 4
+#define IEEE_ADDR_05 5
+#define IEEE_ADDR_06 6
+#define IEEE_ADDR_07 7
+
+#define IEEE_ADDR_1 _SFR_MEM8(0x165)
+#define IEEE_ADDR_10 0
+#define IEEE_ADDR_11 1
+#define IEEE_ADDR_12 2
+#define IEEE_ADDR_13 3
+#define IEEE_ADDR_14 4
+#define IEEE_ADDR_15 5
+#define IEEE_ADDR_16 6
+#define IEEE_ADDR_17 7
+
+#define IEEE_ADDR_2 _SFR_MEM8(0x166)
+#define IEEE_ADDR_20 0
+#define IEEE_ADDR_21 1
+#define IEEE_ADDR_22 2
+#define IEEE_ADDR_23 3
+#define IEEE_ADDR_24 4
+#define IEEE_ADDR_25 5
+#define IEEE_ADDR_26 6
+#define IEEE_ADDR_27 7
+
+#define IEEE_ADDR_3 _SFR_MEM8(0x167)
+#define IEEE_ADDR_30 0
+#define IEEE_ADDR_31 1
+#define IEEE_ADDR_32 2
+#define IEEE_ADDR_33 3
+#define IEEE_ADDR_34 4
+#define IEEE_ADDR_35 5
+#define IEEE_ADDR_36 6
+#define IEEE_ADDR_37 7
+
+#define IEEE_ADDR_4 _SFR_MEM8(0x168)
+#define IEEE_ADDR_40 0
+#define IEEE_ADDR_41 1
+#define IEEE_ADDR_42 2
+#define IEEE_ADDR_43 3
+#define IEEE_ADDR_44 4
+#define IEEE_ADDR_45 5
+#define IEEE_ADDR_46 6
+#define IEEE_ADDR_47 7
+
+#define IEEE_ADDR_5 _SFR_MEM8(0x169)
+#define IEEE_ADDR_50 0
+#define IEEE_ADDR_51 1
+#define IEEE_ADDR_52 2
+#define IEEE_ADDR_53 3
+#define IEEE_ADDR_54 4
+#define IEEE_ADDR_55 5
+#define IEEE_ADDR_56 6
+#define IEEE_ADDR_57 7
+
+#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
+#define IEEE_ADDR_60 0
+#define IEEE_ADDR_61 1
+#define IEEE_ADDR_62 2
+#define IEEE_ADDR_63 3
+#define IEEE_ADDR_64 4
+#define IEEE_ADDR_65 5
+#define IEEE_ADDR_66 6
+#define IEEE_ADDR_67 7
+
+#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
+#define IEEE_ADDR_70 0
+#define IEEE_ADDR_71 1
+#define IEEE_ADDR_72 2
+#define IEEE_ADDR_73 3
+#define IEEE_ADDR_74 4
+#define IEEE_ADDR_75 5
+#define IEEE_ADDR_76 6
+#define IEEE_ADDR_77 7
+
+#define XAH_CTRL_0 _SFR_MEM8(0x16C)
+#define SLOTTED_OPERATION 0
+#define MAX_CSMA_RETRIES0 1
+#define MAX_CSMA_RETRIES1 2
+#define MAX_CSMA_RETRIES2 3
+#define MAX_FRAME_RETRIES0 4
+#define MAX_FRAME_RETRIES1 5
+#define MAX_FRAME_RETRIES2 6
+#define MAX_FRAME_RETRIES3 7
+
+#define CSMA_SEED_0 _SFR_MEM8(0x16D)
+#define CSMA_SEED_00 0
+#define CSMA_SEED_01 1
+#define CSMA_SEED_02 2
+#define CSMA_SEED_03 3
+#define CSMA_SEED_04 4
+#define CSMA_SEED_05 5
+#define CSMA_SEED_06 6
+#define CSMA_SEED_07 7
+
+#define CSMA_SEED_1 _SFR_MEM8(0x16E)
+#define CSMA_SEED_10 0
+#define CSMA_SEED_11 1
+#define CSMA_SEED_12 2
+#define AACK_I_AM_COORD 3
+#define AACK_DIS_ACK 4
+#define AACK_SET_PD 5
+#define AACK_FVN_MODE0 6
+#define AACK_FVN_MODE1 7
+
+#define CSMA_BE _SFR_MEM8(0x16F)
+#define MIN_BE0 0
+#define MIN_BE1 1
+#define MIN_BE2 2
+#define MIN_BE3 3
+#define MAX_BE0 4
+#define MAX_BE1 5
+#define MAX_BE2 6
+#define MAX_BE3 7
+
+/* Reserved [0x170..0x175] */
+
+#define TST_CTRL_DIGI _SFR_MEM8(0x176)
+#define TST_CTRL_DIG0 0
+#define TST_CTRL_DIG1 1
+#define TST_CTRL_DIG2 2
+#define TST_CTRL_DIG3 3
+
+/* Reserved [0x177..0x17A] */
+
+#define TST_RX_LENGTH _SFR_MEM8(0x17B)
+#define RX_LENGTH0 0
+#define RX_LENGTH1 1
+#define RX_LENGTH2 2
+#define RX_LENGTH3 3
+#define RX_LENGTH4 4
+#define RX_LENGTH5 5
+#define RX_LENGTH6 6
+#define RX_LENGTH7 7
+
+/* Reserved [0x17C..0x17F] */
+
+#define TRXFBST _SFR_MEM8(0x180)
 
-/* Start of frame buffer */
-#define TRXFBST                         _SFR_MEM8(0x180)
+/* Reserved [0x181..0x1FE] */
 
-  /* TRXFBST */
+#define TRXFBEND _SFR_MEM8(0x1FF)
 
-#define TRXFBST0                        0
-#define TRXFBST1                        1
-#define TRXFBST2                        2
-#define TRXFBST3                        3
-#define TRXFBST4                        4
-#define TRXFBST5                        5
-#define TRXFBST6                        6
-#define TRXFBST7                        7
 
-/* End of frame buffer */
-#define TRXFBEND                        _SFR_MEM8(0x1FF)
 
-  /* TRXFBEND */
+/* Values and associated defines */
 
-#define TRXFBEND0                       0
-#define TRXFBEND1                       1
-#define TRXFBEND2                       2
-#define TRXFBEND3                       3
-#define TRXFBEND4                       4
-#define TRXFBEND5                       5
-#define TRXFBEND6                       6
-#define TRXFBEND7                       7
 
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
-
-#define _VECTORS_SIZE                  308
-
 /* External Interrupt Request 0 */
-#define INT0_vect                       _VECTOR(1)
-#define INT0_vect_num                   1
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
 
 /* External Interrupt Request 1 */
-#define INT1_vect                       _VECTOR(2)
-#define INT1_vect_num                   2
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
 
 /* External Interrupt Request 2 */
-#define INT2_vect                       _VECTOR(3)
-#define INT2_vect_num                   3
+#define INT2_vect            _VECTOR(3)
+#define INT2_vect_num        3
 
 /* External Interrupt Request 3 */
-#define INT3_vect                       _VECTOR(4)
-#define INT3_vect_num                   4
+#define INT3_vect            _VECTOR(4)
+#define INT3_vect_num        4
 
 /* External Interrupt Request 4 */
-#define INT4_vect                       _VECTOR(5)
-#define INT4_vect_num                   5
+#define INT4_vect            _VECTOR(5)
+#define INT4_vect_num        5
 
 /* External Interrupt Request 5 */
-#define INT5_vect                       _VECTOR(6)
-#define INT5_vect_num                   6
+#define INT5_vect            _VECTOR(6)
+#define INT5_vect_num        6
 
 /* External Interrupt Request 6 */
-#define INT6_vect                       _VECTOR(7)
-#define INT6_vect_num                   7
+#define INT6_vect            _VECTOR(7)
+#define INT6_vect_num        7
 
 /* External Interrupt Request 7 */
-#define INT7_vect                       _VECTOR(8)
-#define INT7_vect_num                   8
+#define INT7_vect            _VECTOR(8)
+#define INT7_vect_num        8
 
 /* Pin Change Interrupt Request 0 */
-#define PCINT0_vect                     _VECTOR(9)
-#define PCINT0_vect_num                 9
+#define PCINT0_vect            _VECTOR(9)
+#define PCINT0_vect_num        9
 
 /* Pin Change Interrupt Request 1 */
-#define PCINT1_vect                     _VECTOR(10)
-#define PCINT1_vect_num                 10
+#define PCINT1_vect            _VECTOR(10)
+#define PCINT1_vect_num        10
 
 /* Pin Change Interrupt Request 2 */
-#define PCINT2_vect                     _VECTOR(11)
-#define PCINT2_vect_num                 11
+#define PCINT2_vect            _VECTOR(11)
+#define PCINT2_vect_num        11
 
 /* Watchdog Time-out Interrupt */
-#define WDT_vect                        _VECTOR(12)
-#define WDT_vect_num                    12
+#define WDT_vect            _VECTOR(12)
+#define WDT_vect_num        12
 
 /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect               _VECTOR(13)
-#define TIMER2_COMPA_vect_num           13
+#define TIMER2_COMPA_vect            _VECTOR(13)
+#define TIMER2_COMPA_vect_num        13
 
 /* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect               _VECTOR(14)
-#define TIMER2_COMPB_vect_num           14
+#define TIMER2_COMPB_vect            _VECTOR(14)
+#define TIMER2_COMPB_vect_num        14
 
 /* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect                 _VECTOR(15)
-#define TIMER2_OVF_vect_num             15
+#define TIMER2_OVF_vect            _VECTOR(15)
+#define TIMER2_OVF_vect_num        15
 
 /* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect                _VECTOR(16)
-#define TIMER1_CAPT_vect_num            16
+#define TIMER1_CAPT_vect            _VECTOR(16)
+#define TIMER1_CAPT_vect_num        16
 
 /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect               _VECTOR(17)
-#define TIMER1_COMPA_vect_num           17
+#define TIMER1_COMPA_vect            _VECTOR(17)
+#define TIMER1_COMPA_vect_num        17
 
 /* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect               _VECTOR(18)
-#define TIMER1_COMPB_vect_num           18
+#define TIMER1_COMPB_vect            _VECTOR(18)
+#define TIMER1_COMPB_vect_num        18
 
 /* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect               _VECTOR(19)
-#define TIMER1_COMPC_vect_num           19
+#define TIMER1_COMPC_vect            _VECTOR(19)
+#define TIMER1_COMPC_vect_num        19
 
 /* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect                 _VECTOR(20)
-#define TIMER1_OVF_vect_num             20
+#define TIMER1_OVF_vect            _VECTOR(20)
+#define TIMER1_OVF_vect_num        20
 
 /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect               _VECTOR(21)
-#define TIMER0_COMPA_vect_num           21
+#define TIMER0_COMPA_vect            _VECTOR(21)
+#define TIMER0_COMPA_vect_num        21
 
 /* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect               _VECTOR(22)
-#define TIMER0_COMPB_vect_num           22
+#define TIMER0_COMPB_vect            _VECTOR(22)
+#define TIMER0_COMPB_vect_num        22
 
 /* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect                 _VECTOR(23)
-#define TIMER0_OVF_vect_num             23
+#define TIMER0_OVF_vect            _VECTOR(23)
+#define TIMER0_OVF_vect_num        23
 
 /* SPI Serial Transfer Complete */
-#define SPI_STC_vect                    _VECTOR(24)
-#define SPI_STC_vect_num                24
+#define SPI_STC_vect            _VECTOR(24)
+#define SPI_STC_vect_num        24
 
 /* USART0, Rx Complete */
-#define USART0_RX_vect                  _VECTOR(25)
-#define USART0_RX_vect_num              25
+#define USART0_RX_vect            _VECTOR(25)
+#define USART0_RX_vect_num        25
 
 /* USART0 Data register Empty */
-#define USART0_UDRE_vect                _VECTOR(26)
-#define USART0_UDRE_vect_num            26
+#define USART0_UDRE_vect            _VECTOR(26)
+#define USART0_UDRE_vect_num        26
 
 /* USART0, Tx Complete */
-#define USART0_TX_vect                  _VECTOR(27)
-#define USART0_TX_vect_num              27
+#define USART0_TX_vect            _VECTOR(27)
+#define USART0_TX_vect_num        27
 
 /* Analog Comparator */
-#define ANALOG_COMP_vect                _VECTOR(28)
-#define ANALOG_COMP_vect_num            28
+#define ANALOG_COMP_vect            _VECTOR(28)
+#define ANALOG_COMP_vect_num        28
 
 /* ADC Conversion Complete */
-#define ADC_vect                        _VECTOR(29)
-#define ADC_vect_num                    29
+#define ADC_vect            _VECTOR(29)
+#define ADC_vect_num        29
 
 /* EEPROM Ready */
-#define EE_READY_vect                   _VECTOR(30)
-#define EE_READY_vect_num               30
+#define EE_READY_vect            _VECTOR(30)
+#define EE_READY_vect_num        30
 
 /* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect                _VECTOR(31)
-#define TIMER3_CAPT_vect_num            31
+#define TIMER3_CAPT_vect            _VECTOR(31)
+#define TIMER3_CAPT_vect_num        31
 
 /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect               _VECTOR(32)
-#define TIMER3_COMPA_vect_num           32
+#define TIMER3_COMPA_vect            _VECTOR(32)
+#define TIMER3_COMPA_vect_num        32
 
 /* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect               _VECTOR(33)
-#define TIMER3_COMPB_vect_num           33
+#define TIMER3_COMPB_vect            _VECTOR(33)
+#define TIMER3_COMPB_vect_num        33
 
 /* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect               _VECTOR(34)
-#define TIMER3_COMPC_vect_num           34
+#define TIMER3_COMPC_vect            _VECTOR(34)
+#define TIMER3_COMPC_vect_num        34
 
 /* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect                 _VECTOR(35)
-#define TIMER3_OVF_vect_num             35
+#define TIMER3_OVF_vect            _VECTOR(35)
+#define TIMER3_OVF_vect_num        35
 
 /* USART1, Rx Complete */
-#define USART1_RX_vect                  _VECTOR(36)
-#define USART1_RX_vect_num              36
+#define USART1_RX_vect            _VECTOR(36)
+#define USART1_RX_vect_num        36
 
 /* USART1 Data register Empty */
-#define USART1_UDRE_vect                _VECTOR(37)
-#define USART1_UDRE_vect_num            37
+#define USART1_UDRE_vect            _VECTOR(37)
+#define USART1_UDRE_vect_num        37
 
 /* USART1, Tx Complete */
-#define USART1_TX_vect                  _VECTOR(38)
-#define USART1_TX_vect_num              38
+#define USART1_TX_vect            _VECTOR(38)
+#define USART1_TX_vect_num        38
 
 /* 2-wire Serial Interface */
-#define TWI_vect                        _VECTOR(39)
-#define TWI_vect_num                    39
+#define TWI_vect            _VECTOR(39)
+#define TWI_vect_num        39
 
 /* Store Program Memory Read */
-#define SPM_READY_vect                  _VECTOR(40)
-#define SPM_READY_vect_num              40
+#define SPM_READY_vect            _VECTOR(40)
+#define SPM_READY_vect_num        40
 
 /* Timer/Counter4 Capture Event */
-#define TIMER4_CAPT_vect                _VECTOR(41)
-#define TIMER4_CAPT_vect_num            41
+#define TIMER4_CAPT_vect            _VECTOR(41)
+#define TIMER4_CAPT_vect_num        41
 
 /* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPA_vect               _VECTOR(42)
-#define TIMER4_COMPA_vect_num           42
+#define TIMER4_COMPA_vect            _VECTOR(42)
+#define TIMER4_COMPA_vect_num        42
 
 /* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPB_vect               _VECTOR(43)
-#define TIMER4_COMPB_vect_num           43
+#define TIMER4_COMPB_vect            _VECTOR(43)
+#define TIMER4_COMPB_vect_num        43
 
 /* Timer/Counter4 Compare Match C */
-#define TIMER4_COMPC_vect               _VECTOR(44)
-#define TIMER4_COMPC_vect_num           44
+#define TIMER4_COMPC_vect            _VECTOR(44)
+#define TIMER4_COMPC_vect_num        44
 
 /* Timer/Counter4 Overflow */
-#define TIMER4_OVF_vect                 _VECTOR(45)
-#define TIMER4_OVF_vect_num             45
+#define TIMER4_OVF_vect            _VECTOR(45)
+#define TIMER4_OVF_vect_num        45
 
 /* Timer/Counter5 Capture Event */
-#define TIMER5_CAPT_vect                _VECTOR(46)
-#define TIMER5_CAPT_vect_num            46
+#define TIMER5_CAPT_vect            _VECTOR(46)
+#define TIMER5_CAPT_vect_num        46
 
 /* Timer/Counter5 Compare Match A */
-#define TIMER5_COMPA_vect               _VECTOR(47)
-#define TIMER5_COMPA_vect_num           47
+#define TIMER5_COMPA_vect            _VECTOR(47)
+#define TIMER5_COMPA_vect_num        47
 
 /* Timer/Counter5 Compare Match B */
-#define TIMER5_COMPB_vect               _VECTOR(48)
-#define TIMER5_COMPB_vect_num           48
+#define TIMER5_COMPB_vect            _VECTOR(48)
+#define TIMER5_COMPB_vect_num        48
 
 /* Timer/Counter5 Compare Match C */
-#define TIMER5_COMPC_vect               _VECTOR(49)
-#define TIMER5_COMPC_vect_num           49
+#define TIMER5_COMPC_vect            _VECTOR(49)
+#define TIMER5_COMPC_vect_num        49
 
 /* Timer/Counter5 Overflow */
-#define TIMER5_OVF_vect                 _VECTOR(50)
-#define TIMER5_OVF_vect_num             50
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_51_vect                _VECTOR(51)
-#define RESERVED_51_vect_num            51
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_52_vect                _VECTOR(52)
-#define RESERVED_52_vect_num            52
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_53_vect                _VECTOR(53)
-#define RESERVED_53_vect_num            53
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_54_vect                _VECTOR(54)
-#define RESERVED_54_vect_num            54
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_55_vect                _VECTOR(55)
-#define RESERVED_55_vect_num            55
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_56_vect                _VECTOR(56)
-#define RESERVED_56_vect_num            56
+#define TIMER5_OVF_vect            _VECTOR(50)
+#define TIMER5_OVF_vect_num        50
 
 /* TRX24 - PLL lock interrupt */
-#define TRX24_PLL_LOCK_vect             _VECTOR(57)
-#define TRX24_PLL_LOCK_vect_num         57
+#define TRX24_PLL_LOCK_vect            _VECTOR(57)
+#define TRX24_PLL_LOCK_vect_num        57
 
 /* TRX24 - PLL unlock interrupt */
-#define TRX24_PLL_UNLOCK_vect           _VECTOR(58)
-#define TRX24_PLL_UNLOCK_vect_num       58
+#define TRX24_PLL_UNLOCK_vect            _VECTOR(58)
+#define TRX24_PLL_UNLOCK_vect_num        58
 
 /* TRX24 - Receive start interrupt */
-#define TRX24_RX_START_vect             _VECTOR(59)
-#define TRX24_RX_START_vect_num         59
+#define TRX24_RX_START_vect            _VECTOR(59)
+#define TRX24_RX_START_vect_num        59
 
 /* TRX24 - RX_END interrupt */
-#define TRX24_RX_END_vect               _VECTOR(60)
-#define TRX24_RX_END_vect_num           60
+#define TRX24_RX_END_vect            _VECTOR(60)
+#define TRX24_RX_END_vect_num        60
 
 /* TRX24 - CCA/ED done interrupt */
-#define TRX24_CCA_ED_DONE_vect          _VECTOR(61)
-#define TRX24_CCA_ED_DONE_vect_num      61
+#define TRX24_CCA_ED_DONE_vect            _VECTOR(61)
+#define TRX24_CCA_ED_DONE_vect_num        61
 
 /* TRX24 - XAH - AMI */
-#define TRX24_XAH_AMI_vect              _VECTOR(62)
-#define TRX24_XAH_AMI_vect_num          62
+#define TRX24_XAH_AMI_vect            _VECTOR(62)
+#define TRX24_XAH_AMI_vect_num        62
 
 /* TRX24 - TX_END interrupt */
-#define TRX24_TX_END_vect               _VECTOR(63)
-#define TRX24_TX_END_vect_num           63
+#define TRX24_TX_END_vect            _VECTOR(63)
+#define TRX24_TX_END_vect_num        63
 
 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
-#define TRX24_AWAKE_vect                _VECTOR(64)
-#define TRX24_AWAKE_vect_num            64
+#define TRX24_AWAKE_vect            _VECTOR(64)
+#define TRX24_AWAKE_vect_num        64
 
 /* Symbol counter - compare match 1 interrupt */
-#define SCNT_CMP1_vect                  _VECTOR(65)
-#define SCNT_CMP1_vect_num              65
+#define SCNT_CMP1_vect            _VECTOR(65)
+#define SCNT_CMP1_vect_num        65
 
 /* Symbol counter - compare match 2 interrupt */
-#define SCNT_CMP2_vect                  _VECTOR(66)
-#define SCNT_CMP2_vect_num              66
+#define SCNT_CMP2_vect            _VECTOR(66)
+#define SCNT_CMP2_vect_num        66
 
 /* Symbol counter - compare match 3 interrupt */
-#define SCNT_CMP3_vect                  _VECTOR(67)
-#define SCNT_CMP3_vect_num              67
+#define SCNT_CMP3_vect            _VECTOR(67)
+#define SCNT_CMP3_vect_num        67
 
 /* Symbol counter - overflow interrupt */
-#define SCNT_OVFL_vect                  _VECTOR(68)
-#define SCNT_OVFL_vect_num              68
+#define SCNT_OVFL_vect            _VECTOR(68)
+#define SCNT_OVFL_vect_num        68
 
 /* Symbol counter - backoff interrupt */
-#define SCNT_BACKOFF_vect               _VECTOR(69)
-#define SCNT_BACKOFF_vect_num           69
+#define SCNT_BACKOFF_vect            _VECTOR(69)
+#define SCNT_BACKOFF_vect_num        69
 
 /* AES engine ready interrupt */
-#define AES_READY_vect                  _VECTOR(70)
-#define AES_READY_vect_num              70
+#define AES_READY_vect            _VECTOR(70)
+#define AES_READY_vect_num        70
 
 /* Battery monitor indicates supply voltage below threshold */
-#define BAT_LOW_vect                    _VECTOR(71)
-#define BAT_LOW_vect_num                71
+#define BAT_LOW_vect            _VECTOR(71)
+#define BAT_LOW_vect_num        71
 
 /* TRX24 TX start interrupt */
-#define TRX24_TX_START_vect             _VECTOR(72)
-#define TRX24_TX_START_vect_num         72
+#define TRX24_TX_START_vect            _VECTOR(72)
+#define TRX24_TX_START_vect_num        72
 
 /* Address match interrupt of address filter 0 */
-#define TRX24_AMI0_vect                 _VECTOR(73)
-#define TRX24_AMI0_vect_num             73
+#define TRX24_AMI0_vect            _VECTOR(73)
+#define TRX24_AMI0_vect_num        73
 
 /* Address match interrupt of address filter 1 */
-#define TRX24_AMI1_vect                 _VECTOR(74)
-#define TRX24_AMI1_vect_num             74
+#define TRX24_AMI1_vect            _VECTOR(74)
+#define TRX24_AMI1_vect_num        74
 
 /* Address match interrupt of address filter 2 */
-#define TRX24_AMI2_vect                 _VECTOR(75)
-#define TRX24_AMI2_vect_num             75
+#define TRX24_AMI2_vect            _VECTOR(75)
+#define TRX24_AMI2_vect_num        75
 
 /* Address match interrupt of address filter 3 */
-#define TRX24_AMI3_vect                 _VECTOR(76)
-#define TRX24_AMI3_vect_num             76
+#define TRX24_AMI3_vect            _VECTOR(76)
+#define TRX24_AMI3_vect_num        76
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 308
+#else
+#  define _VECTORS_SIZE 308U
+#endif
 
 
-/* memory parameters */
+/* Constants */
 
-#define SPM_PAGESIZE                    (256)
-#define RAMSTART                        (0x200)
-#define RAMSIZE                         (0x8000)
-#define RAMEND                          (0x81FF)
-#define XRAMSTART                       (0x0000)
-#define XRAMSIZE                        (0x0000)
-#define XRAMEND                         RAMEND
-#define E2END                           (0x1FFF)
-#define E2PAGESIZE                      (0x08)
-#define FLASHEND                        (0x3ffff)
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 256
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFFF
+#else
+#  define SPM_PAGESIZE 256U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      32768
+#  define RAMEND       0x81FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      32768U
+#  define RAMEND       0x81FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      8192
+#  define E2PAGESIZE  8
+#  define E2END       0x1FFF
+#else
+#  define E2START     0U
+#  define E2SIZE      8192U
+#  define E2PAGESIZE  8U
+#  define E2END       0x1FFFU
+#endif
+#define XRAMEND      RAMEND
 
 
 /* Fuses */
 
 #define FUSE_MEMORY_SIZE 3
 
-/* LFUSE Byte */
-#define FUSE_CKSEL0     ~_BV(0) /* Select Clock Source */
-#define FUSE_CKSEL1     ~_BV(1) /* Select Clock Source */
-#define FUSE_CKSEL2     ~_BV(2) /* Select Clock Source */
-#define FUSE_CKSEL3     ~_BV(3) /* Select Clock Source */
-#define FUSE_SUT0       ~_BV(4) /* Select start-up time */
-#define FUSE_SUT1       ~_BV(5) /* Select start-up time */
-#define FUSE_CKOUT      ~_BV(6) /* Clock output */
-#define FUSE_CKDIV8     ~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* HFUSE Byte */
-#define FUSE_BOOTRST    ~_BV(0) /* Select Reset Vector */
-#define FUSE_BOOTSZ0    ~_BV(1) /* Select Boot Size */
-#define FUSE_BOOTSZ1    ~_BV(2) /* Select Boot Size */
-#define FUSE_EESAVE     ~_BV(3) /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      ~_BV(4) /* Watchdog timer always on */
-#define FUSE_SPIEN      ~_BV(5) /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN     ~_BV(6) /* Enable JTAG */
-#define FUSE_OCDEN      ~_BV(7) /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* EFUSE Byte */
-#define FUSE_BODLEVEL0  ~_BV(0) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  ~_BV(1) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  ~_BV(2) /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
+/* Low Fuse Byte */
+#define FUSE_CKSEL_SUT0  (unsigned char)~_BV(0)
+#define FUSE_CKSEL_SUT1  (unsigned char)~_BV(1)
+#define FUSE_CKSEL_SUT2  (unsigned char)~_BV(2)
+#define FUSE_CKSEL_SUT3  (unsigned char)~_BV(3)
+#define FUSE_CKSEL_SUT4  (unsigned char)~_BV(4)
+#define FUSE_CKSEL_SUT5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_CKSEL_SUT0 & FUSE_CKSEL_SUT2 & FUSE_CKSEL_SUT3 & FUSE_CKSEL_SUT4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BODLEVEL0)
 
 
 
 /* Lock Bits */
-
+#define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST
-#define __LOCK_BITS_EXIST
 
 
 /* Signature */
-
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0xA8
 #define SIGNATURE_2 0x02
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 
-#endif /* _AVR_IOM256RFR2_H_ */
+
+#endif /* #ifdef _AVR_ATMEGA256RFR2_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom32.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom32.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom32.h 2233 2011-03-15 15:49:50Z arcanum $ */
 
 /* avr/iom32.h - definitions for ATmega32 */
 
@@ -745,7 +745,6 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_ADC (0x01<<4)
 #define SLEEP_MODE_PWR_DOWN (0x02<<4)
@@ -753,5 +752,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<4)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<4)
 
-
 #endif /* _AVR_IOM32_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom323.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom323.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom323.h 2234 2011-03-16 04:32:21Z arcanum $ */
 
 /* avr/iom323.h - definitions for ATmega323 */
 
@@ -734,7 +734,6 @@
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_ADC (0x01<<4)
 #define SLEEP_MODE_PWR_DOWN (0x02<<4)
@@ -742,5 +741,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<4)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<4)
 
-
 #endif /* _AVR_IOM323_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom324a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom324a.h
@@ -0,0 +1,1024 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATMEGA324A_H_INCLUDED
+#define _AVR_ATMEGA324A_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iom324a.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+/* Reserved [0x0C..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+#define PCIF3   3
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+#define INTF2   2
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+#define INT2    2
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM     7
+#define PSRASY  1
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR0   _SFR_IO8(0x2C)
+#define SPR00   0
+#define SPR10   1
+#define CPHA0   2
+#define CPOL0   3
+#define MSTR0   4
+#define DORD0   5
+#define SPE0    6
+#define SPIE0   7
+
+#define SPSR0   _SFR_IO8(0x2D)
+#define SPI2X0  0
+#define WCOL0   6
+#define SPIF0   7
+
+#define SPDR0   _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define OCDR    _SFR_IO8(0x31)
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRUSART1 4
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRUSART0
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRUSART1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+#define PCIE3   3
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+#define ISC20   4
+#define ISC21   5
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+/* Reserved [0x71..0x72] */
+
+#define PCMSK3  _SFR_MEM8(0x73)
+#define PCINT24 0
+#define PCINT25 1
+#define PCINT26 2
+#define PCINT27 3
+#define PCINT28 4
+#define PCINT29 5
+#define PCINT30 6
+#define PCINT31 7
+
+/* Reserved [0x74..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+#define UCSR1B  _SFR_MEM8(0xC9)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0xCE)
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* External Interrupt Request 2 */
+#define INT2_vect            _VECTOR(3)
+#define INT2_vect_num        3
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(4)
+#define PCINT0_vect_num        4
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(5)
+#define PCINT1_vect_num        5
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect            _VECTOR(6)
+#define PCINT2_vect_num        6
+
+/* Pin Change Interrupt Request 3 */
+#define PCINT3_vect            _VECTOR(7)
+#define PCINT3_vect_num        7
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(8)
+#define WDT_vect_num        8
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(9)
+#define TIMER2_COMPA_vect_num        9
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect            _VECTOR(10)
+#define TIMER2_COMPB_vect_num        10
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(11)
+#define TIMER2_OVF_vect_num        11
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(12)
+#define TIMER1_CAPT_vect_num        12
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(13)
+#define TIMER1_COMPA_vect_num        13
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(14)
+#define TIMER1_COMPB_vect_num        14
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(15)
+#define TIMER1_OVF_vect_num        15
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(16)
+#define TIMER0_COMPA_vect_num        16
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(17)
+#define TIMER0_COMPB_vect_num        17
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(18)
+#define TIMER0_OVF_vect_num        18
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(19)
+#define SPI_STC_vect_num        19
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect            _VECTOR(20)
+#define USART0_RX_vect_num        20
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect            _VECTOR(21)
+#define USART0_UDRE_vect_num        21
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect            _VECTOR(22)
+#define USART0_TX_vect_num        22
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect            _VECTOR(23)
+#define ANALOG_COMP_vect_num        23
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(24)
+#define ADC_vect_num        24
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(25)
+#define EE_READY_vect_num        25
+
+/* 2-wire Serial Interface */
+#define TWI_vect            _VECTOR(26)
+#define TWI_vect_num        26
+
+/* Store Program Memory Read */
+#define SPM_READY_vect            _VECTOR(27)
+#define SPM_READY_vect_num        27
+
+/* USART1 RX complete */
+#define USART1_RX_vect            _VECTOR(28)
+#define USART1_RX_vect_num        28
+
+/* USART1 Data Register Empty */
+#define USART1_UDRE_vect            _VECTOR(29)
+#define USART1_UDRE_vect_num        29
+
+/* USART1 TX complete */
+#define USART1_TX_vect            _VECTOR(30)
+#define USART1_TX_vect_num        30
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 124
+#else
+#  define _VECTORS_SIZE 124U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x7FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x7FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      2048
+#  define RAMEND       0x08FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      2048U
+#  define RAMEND       0x08FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  4
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  4U
+#  define E2END       0x03FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x15
+
+
+
+
+#endif /* #ifdef _AVR_ATMEGA324A_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom324p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom324p.h
@@ -0,0 +1,1026 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATMEGA324P_H_INCLUDED
+#define _AVR_ATMEGA324P_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iom324p.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+/* Reserved [0x0C..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+#define PCIF3   3
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+#define INTF2   2
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+#define INT2    2
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM     7
+#define PSRASY  1
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR0   _SFR_IO8(0x2C)
+#define SPR00   0
+#define SPR10   1
+#define CPHA0   2
+#define CPOL0   3
+#define MSTR0   4
+#define DORD0   5
+#define SPE0    6
+#define SPIE0   7
+
+#define SPSR0   _SFR_IO8(0x2D)
+#define SPI2X0  0
+#define WCOL0   6
+#define SPIF0   7
+
+#define SPDR0   _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define OCDR    _SFR_IO8(0x31)
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+#define BODSE   5
+#define BODS    6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRUSART1 4
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRUSART0
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRUSART1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+#define PCIE3   3
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+#define ISC20   4
+#define ISC21   5
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+/* Reserved [0x71..0x72] */
+
+#define PCMSK3  _SFR_MEM8(0x73)
+#define PCINT24 0
+#define PCINT25 1
+#define PCINT26 2
+#define PCINT27 3
+#define PCINT28 4
+#define PCINT29 5
+#define PCINT30 6
+#define PCINT31 7
+
+/* Reserved [0x74..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+#define UCSR1B  _SFR_MEM8(0xC9)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0xCE)
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* External Interrupt Request 2 */
+#define INT2_vect            _VECTOR(3)
+#define INT2_vect_num        3
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(4)
+#define PCINT0_vect_num        4
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(5)
+#define PCINT1_vect_num        5
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect            _VECTOR(6)
+#define PCINT2_vect_num        6
+
+/* Pin Change Interrupt Request 3 */
+#define PCINT3_vect            _VECTOR(7)
+#define PCINT3_vect_num        7
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(8)
+#define WDT_vect_num        8
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(9)
+#define TIMER2_COMPA_vect_num        9
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect            _VECTOR(10)
+#define TIMER2_COMPB_vect_num        10
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(11)
+#define TIMER2_OVF_vect_num        11
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(12)
+#define TIMER1_CAPT_vect_num        12
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(13)
+#define TIMER1_COMPA_vect_num        13
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(14)
+#define TIMER1_COMPB_vect_num        14
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(15)
+#define TIMER1_OVF_vect_num        15
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(16)
+#define TIMER0_COMPA_vect_num        16
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(17)
+#define TIMER0_COMPB_vect_num        17
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(18)
+#define TIMER0_OVF_vect_num        18
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(19)
+#define SPI_STC_vect_num        19
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect            _VECTOR(20)
+#define USART0_RX_vect_num        20
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect            _VECTOR(21)
+#define USART0_UDRE_vect_num        21
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect            _VECTOR(22)
+#define USART0_TX_vect_num        22
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect            _VECTOR(23)
+#define ANALOG_COMP_vect_num        23
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(24)
+#define ADC_vect_num        24
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(25)
+#define EE_READY_vect_num        25
+
+/* 2-wire Serial Interface */
+#define TWI_vect            _VECTOR(26)
+#define TWI_vect_num        26
+
+/* Store Program Memory Read */
+#define SPM_READY_vect            _VECTOR(27)
+#define SPM_READY_vect_num        27
+
+/* USART1 RX complete */
+#define USART1_RX_vect            _VECTOR(28)
+#define USART1_RX_vect_num        28
+
+/* USART1 Data Register Empty */
+#define USART1_UDRE_vect            _VECTOR(29)
+#define USART1_UDRE_vect_num        29
+
+/* USART1 TX complete */
+#define USART1_TX_vect            _VECTOR(30)
+#define USART1_TX_vect_num        30
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 124
+#else
+#  define _VECTORS_SIZE 124U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x7FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x7FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      2048
+#  define RAMEND       0x08FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      2048U
+#  define RAMEND       0x08FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  4
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  4U
+#  define E2END       0x03FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x08
+
+
+
+
+#endif /* #ifdef _AVR_ATMEGA324P_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom324pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom324pa.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom324pa.h 2063 2009-11-18 22:06:28Z arcanum $ */
 
 /* avr/iom324pa.h - definitions for ATmega324PA */
 
@@ -1361,7 +1361,6 @@
 #define PCINT12_PIN   PINB
 #define PCINT12_BIT   4
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom325.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom325.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom325.h 2234 2011-03-16 04:32:21Z arcanum $ */
 
 /* avr/iom325.h - definitions for ATmega325 and ATmega325P.  */
 
@@ -877,12 +877,10 @@
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM325_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom3250.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom3250.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom3250.h 2234 2011-03-16 04:32:21Z arcanum $ */
 
 /* avr/iom3250.h - definitions for ATmega3250 and ATmega3250P.  */
 
@@ -973,12 +973,10 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM3250_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom3250a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom3250a.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom3250.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom3250p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom3250p.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom3250.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom3250pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom3250pa.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA3250PA_H_INCLUDED
 #define _AVR_ATMEGA3250PA_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRA    _SFR_IO8(0x01)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x02)
 #define PORTA7  7
@@ -92,13 +91,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -122,13 +137,29 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC7  7
@@ -152,13 +183,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -182,13 +229,29 @@
 
 #define DDRE    _SFR_IO8(0x0D)
 #define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
 #define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
 #define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
 #define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
 #define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
 #define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
 #define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
 #define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
 
 #define PORTE   _SFR_IO8(0x0E)
 #define PORTE7  7
@@ -212,13 +275,29 @@
 
 #define DDRF    _SFR_IO8(0x10)
 #define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
 #define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
 #define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
 #define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
 #define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
 #define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
 #define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
 #define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
 
 #define PORTF   _SFR_IO8(0x11)
 #define PORTF7  7
@@ -240,10 +319,20 @@
 
 #define DDRG    _SFR_IO8(0x13)
 #define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
 #define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
 #define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
 #define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
 #define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
 
 #define PORTG   _SFR_IO8(0x14)
 #define PORTG4  4
@@ -684,13 +773,29 @@
 
 #define DDRH    _SFR_MEM8(0xD9)
 #define DDRH7   7
+// Inserted "DDH7" from "DDRH7" due to compatibility
+#define DDH7    7
 #define DDRH6   6
+// Inserted "DDH6" from "DDRH6" due to compatibility
+#define DDH6    6
 #define DDRH5   5
+// Inserted "DDH5" from "DDRH5" due to compatibility
+#define DDH5    5
 #define DDRH4   4
+// Inserted "DDH4" from "DDRH4" due to compatibility
+#define DDH4    4
 #define DDRH3   3
+// Inserted "DDH3" from "DDRH3" due to compatibility
+#define DDH3    3
 #define DDRH2   2
+// Inserted "DDH2" from "DDRH2" due to compatibility
+#define DDH2    2
 #define DDRH1   1
+// Inserted "DDH1" from "DDRH1" due to compatibility
+#define DDH1    1
 #define DDRH0   0
+// Inserted "DDH0" from "DDRH0" due to compatibility
+#define DDH0    0
 
 #define PORTH   _SFR_MEM8(0xDA)
 #define PORTH7  7
@@ -713,12 +818,26 @@
 
 #define DDRJ    _SFR_MEM8(0xDC)
 #define DDRJ6   6
+// Inserted "DDJ6" from "DDRJ6" due to compatibility
+#define DDJ6    6
 #define DDRJ5   5
+// Inserted "DDJ5" from "DDRJ5" due to compatibility
+#define DDJ5    5
 #define DDRJ4   4
+// Inserted "DDJ4" from "DDRJ4" due to compatibility
+#define DDJ4    4
 #define DDRJ3   3
+// Inserted "DDJ3" from "DDRJ3" due to compatibility
+#define DDJ3    3
 #define DDRJ2   2
+// Inserted "DDJ2" from "DDRJ2" due to compatibility
+#define DDJ2    2
 #define DDRJ1   1
+// Inserted "DDJ1" from "DDRJ1" due to compatibility
+#define DDJ1    1
 #define DDRJ0   0
+// Inserted "DDJ0" from "DDRJ0" due to compatibility
+#define DDJ0    0
 
 #define PORTJ   _SFR_MEM8(0xDD)
 #define PORTJ6  6
@@ -731,6 +850,15 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -829,21 +957,44 @@
 #define PCINT3_vect            _VECTOR(24)
 #define PCINT3_vect_num        24
 
-#define _VECTORS_SIZE 100
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 100
+#else
+#  define _VECTORS_SIZE 100U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x7FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      2048
-#define RAMEND       0x08FF
-#define E2START     0
-#define E2SIZE      1024
-#define E2PAGESIZE  4
-#define E2END       0x03FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x7FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x7FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      2048
+#  define RAMEND       0x08FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      2048U
+#  define RAMEND       0x08FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  4
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  4U
+#  define E2END       0x03FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -860,6 +1011,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -870,11 +1023,15 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_JTAGEN      (unsigned char)~_BV(6)
 #define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_RSTDISBL    (unsigned char)~_BV(0)
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
 #define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -890,11 +1047,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
 
 #endif /* #ifdef _AVR_ATMEGA3250PA_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom325a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom325a.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom325.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom325p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom325p.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom325.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom325pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom325pa.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA325PA_H_INCLUDED
 #define _AVR_ATMEGA325PA_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRA    _SFR_IO8(0x01)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x02)
 #define PORTA7  7
@@ -92,13 +91,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -122,13 +137,29 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC7  7
@@ -152,13 +183,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -182,13 +229,29 @@
 
 #define DDRE    _SFR_IO8(0x0D)
 #define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
 #define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
 #define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
 #define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
 #define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
 #define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
 #define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
 #define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
 
 #define PORTE   _SFR_IO8(0x0E)
 #define PORTE7  7
@@ -212,13 +275,29 @@
 
 #define DDRF    _SFR_IO8(0x10)
 #define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
 #define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
 #define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
 #define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
 #define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
 #define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
 #define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
 #define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
 
 #define PORTF   _SFR_IO8(0x11)
 #define PORTF7  7
@@ -240,10 +319,20 @@
 
 #define DDRG    _SFR_IO8(0x13)
 #define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
 #define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
 #define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
 #define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
 #define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
 
 #define PORTG   _SFR_IO8(0x14)
 #define PORTG4  4
@@ -668,6 +757,15 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -754,21 +852,44 @@
 #define SPM_READY_vect            _VECTOR(21)
 #define SPM_READY_vect_num        21
 
-#define _VECTORS_SIZE 88
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 88
+#else
+#  define _VECTORS_SIZE 88U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x7FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      2048
-#define RAMEND       0x08FF
-#define E2START     0
-#define E2SIZE      1024
-#define E2PAGESIZE  4
-#define E2END       0x03FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x7FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x7FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      2048
+#  define RAMEND       0x08FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      2048U
+#  define RAMEND       0x08FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  4
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  4U
+#  define E2END       0x03FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -785,6 +906,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -795,11 +918,15 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_JTAGEN      (unsigned char)~_BV(6)
 #define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_RSTDISBL    (unsigned char)~_BV(0)
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
 #define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -815,11 +942,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
 
 #endif /* #ifdef _AVR_ATMEGA325PA_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom328.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom328.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom328p.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom328p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom328p.h
@@ -29,7 +29,7 @@
   POSSIBILITY OF SUCH DAMAGE. 
 */
 
-/* $Id$ */
+/* $Id: iom328p.h 2444 2014-08-11 22:10:47Z joerg_wunsch $ */
 
 /* avr/iom328p.h - definitions for ATmega328P. */
 
@@ -938,7 +938,6 @@
 #  define SIGNATURE_2 0x0F
 #endif
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -946,5 +945,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif  /* _AVR_IOM328P_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom329.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom329.h
@@ -31,8 +31,6 @@
 
 /* avr/iom329.h - definitions for ATmega329 and ATmega329P.  */
 
-/* $Id$ */
-
 #ifndef _AVR_IOM329_H_
 #define _AVR_IOM329_H_ 1
 
@@ -1062,12 +1060,10 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM329_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom3290.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom3290.h
@@ -31,8 +31,6 @@
 
 /* avr/iom3290.h - definitions for ATmega3290 and ATmega3290P.  */
 
-/* $Id$ */
-
 #ifndef _AVR_IOM3290_H_
 #define _AVR_IOM3290_H_ 1
 
@@ -1220,12 +1218,10 @@
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM3290_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom3290a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom3290a.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom3290.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom3290pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom3290pa.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA3290PA_H_INCLUDED
 #define _AVR_ATMEGA3290PA_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRA    _SFR_IO8(0x01)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x02)
 #define PORTA7  7
@@ -92,13 +91,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -122,13 +137,29 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC7  7
@@ -152,13 +183,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -182,13 +229,29 @@
 
 #define DDRE    _SFR_IO8(0x0D)
 #define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
 #define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
 #define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
 #define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
 #define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
 #define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
 #define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
 #define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
 
 #define PORTE   _SFR_IO8(0x0E)
 #define PORTE7  7
@@ -212,13 +275,29 @@
 
 #define DDRF    _SFR_IO8(0x10)
 #define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
 #define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
 #define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
 #define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
 #define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
 #define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
 #define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
 #define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
 
 #define PORTF   _SFR_IO8(0x11)
 #define PORTF7  7
@@ -240,10 +319,20 @@
 
 #define DDRG    _SFR_IO8(0x13)
 #define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
 #define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
 #define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
 #define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
 #define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
 
 #define PORTG   _SFR_IO8(0x14)
 #define PORTG4  4
@@ -684,13 +773,29 @@
 
 #define DDRH    _SFR_MEM8(0xD9)
 #define DDRH7   7
+// Inserted "DDH7" from "DDRH7" due to compatibility
+#define DDH7    7
 #define DDRH6   6
+// Inserted "DDH6" from "DDRH6" due to compatibility
+#define DDH6    6
 #define DDRH5   5
+// Inserted "DDH5" from "DDRH5" due to compatibility
+#define DDH5    5
 #define DDRH4   4
+// Inserted "DDH4" from "DDRH4" due to compatibility
+#define DDH4    4
 #define DDRH3   3
+// Inserted "DDH3" from "DDRH3" due to compatibility
+#define DDH3    3
 #define DDRH2   2
+// Inserted "DDH2" from "DDRH2" due to compatibility
+#define DDH2    2
 #define DDRH1   1
+// Inserted "DDH1" from "DDRH1" due to compatibility
+#define DDH1    1
 #define DDRH0   0
+// Inserted "DDH0" from "DDRH0" due to compatibility
+#define DDH0    0
 
 #define PORTH   _SFR_MEM8(0xDA)
 #define PORTH7  7
@@ -713,12 +818,26 @@
 
 #define DDRJ    _SFR_MEM8(0xDC)
 #define DDRJ6   6
+// Inserted "DDJ6" from "DDRJ6" due to compatibility
+#define DDJ6    6
 #define DDRJ5   5
+// Inserted "DDJ5" from "DDRJ5" due to compatibility
+#define DDJ5    5
 #define DDRJ4   4
+// Inserted "DDJ4" from "DDRJ4" due to compatibility
+#define DDJ4    4
 #define DDRJ3   3
+// Inserted "DDJ3" from "DDRJ3" due to compatibility
+#define DDJ3    3
 #define DDRJ2   2
+// Inserted "DDJ2" from "DDRJ2" due to compatibility
+#define DDJ2    2
 #define DDRJ1   1
+// Inserted "DDJ1" from "DDRJ1" due to compatibility
+#define DDJ1    1
 #define DDRJ0   0
+// Inserted "DDJ0" from "DDRJ0" due to compatibility
+#define DDJ0    0
 
 #define PORTJ   _SFR_MEM8(0xDD)
 #define PORTJ6  6
@@ -812,6 +931,15 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -910,21 +1038,44 @@
 #define PCINT3_vect            _VECTOR(24)
 #define PCINT3_vect_num        24
 
-#define _VECTORS_SIZE 100
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 100
+#else
+#  define _VECTORS_SIZE 100U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x7FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      2048
-#define RAMEND       0x08FF
-#define E2START     0
-#define E2SIZE      1024
-#define E2PAGESIZE  4
-#define E2END       0x03FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x7FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x7FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      2048
+#  define RAMEND       0x08FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      2048U
+#  define RAMEND       0x08FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  4
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  4U
+#  define E2END       0x03FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -941,6 +1092,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -951,11 +1104,15 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_JTAGEN      (unsigned char)~_BV(6)
 #define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_RSTDISBL    (unsigned char)~_BV(0)
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
 #define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -971,11 +1128,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
 
 #endif /* #ifdef _AVR_ATMEGA3290PA_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom329a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom329a.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom329.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom329p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom329p.h
@@ -0,0 +1,1174 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATMEGA329P_H_INCLUDED
+#define _AVR_ATMEGA329P_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iom329p.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
+#define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
+#define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
+#define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
+#define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
+#define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
+#define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
+#define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE7  7
+#define PORTE6  6
+#define PORTE5  5
+#define PORTE4  4
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
+#define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
+#define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
+#define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
+#define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
+#define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
+#define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
+#define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PORTF7  7
+#define PORTF6  6
+#define PORTF5  5
+#define PORTF4  4
+#define PORTF3  3
+#define PORTF2  2
+#define PORTF1  1
+#define PORTF0  0
+
+#define PING    _SFR_IO8(0x12)
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
+#define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
+#define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
+#define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
+#define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PORTG4  4
+#define PORTG3  3
+#define PORTG2  2
+#define PORTG1  1
+#define PORTG0  0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+
+/* Reserved [0x18..0x1B] */
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define PCIF0   4
+#define PCIF1   5
+#define PCIF2   6
+#define PCIF3   7
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define PCIE0   4
+#define PCIE1   5
+#define PCIE2   6
+#define PCIE3   7
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSR10   0
+#define TSM     7
+#define PSR2    1
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM01   3
+#define COM0A0  4
+#define COM0A1  5
+#define WGM00   6
+#define FOC0A   7
+
+/* Reserved [0x25] */
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+/* Reserved [0x28..0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define OCDR    _SFR_IO8(0x31)
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+#define BODSE   5
+#define BODS    6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDE     3
+#define WDCE    4
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62..0x63] */
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRLCD   4
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRLCD))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRLCD
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67..0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+
+/* Reserved [0x71..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM21   3
+#define COM2A0  4
+#define COM2A1  5
+#define WGM20   6
+#define FOC2A   7
+
+/* Reserved [0xB1] */
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+/* Reserved [0xB4..0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2UB  0
+#define OCR2UB  1
+#define TCN2UB  2
+#define AS2     3
+#define EXCLK   4
+
+/* Reserved [0xB7] */
+
+#define USICR   _SFR_MEM8(0xB8)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_MEM8(0xB9)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_MEM8(0xBA)
+
+/* Reserved [0xBB..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL0  6
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7..0xE3] */
+
+#define LCDCRA  _SFR_MEM8(0xE4)
+#define LCDBL   0
+#define LCDCCD  1
+#define LCDBD   2
+#define LCDIE   3
+#define LCDIF   4
+#define LCDAB   6
+#define LCDEN   7
+
+#define LCDCRB  _SFR_MEM8(0xE5)
+#define LCDPM0  0
+#define LCDPM1  1
+#define LCDPM2  2
+#define LCDPM3  3
+#define LCDMUX0 4
+#define LCDMUX1 5
+#define LCD2B   6
+#define LCDCS   7
+
+#define LCDFRR  _SFR_MEM8(0xE6)
+#define LCDCD0  0
+#define LCDCD1  1
+#define LCDCD2  2
+#define LCDPS0  4
+#define LCDPS1  5
+#define LCDPS2  6
+
+#define LCDCCR  _SFR_MEM8(0xE7)
+#define LCDCC0  0
+#define LCDCC1  1
+#define LCDCC2  2
+#define LCDCC3  3
+#define LCDMDT  4
+#define LCDDC0  5
+#define LCDDC1  6
+#define LCDDC2  7
+
+/* Reserved [0xE8..0xEB] */
+
+#define LCDDR0  _SFR_MEM8(0xEC)
+#define SEG000  0
+#define SEG001  1
+#define SEG002  2
+#define SEG003  3
+#define SEG004  4
+#define SEG005  5
+#define SEG006  6
+#define SEG007  7
+
+#define LCDDR1  _SFR_MEM8(0xED)
+#define SEG008  0
+#define SEG009  1
+#define SEG010  2
+#define SEG011  3
+#define SEG012  4
+#define SEG013  5
+#define SEG014  6
+#define SEG015  7
+
+#define LCDDR2  _SFR_MEM8(0xEE)
+#define SEG016  0
+#define SEG017  1
+#define SEG018  2
+#define SEG019  3
+#define SEG020  4
+#define SEG021  5
+#define SEG022  6
+#define SEG023  7
+
+#define LCDDR3  _SFR_MEM8(0xEF)
+#define SEG024  0
+#define SEG025  1
+#define SEG026  2
+#define SEG027  3
+#define SEG028  4
+#define SEG029  5
+#define SEG030  6
+#define SEG031  7
+
+/* Reserved [0xF0] */
+
+#define LCDDR5  _SFR_MEM8(0xF1)
+#define SEG100  0
+#define SEG101  1
+#define SEG102  2
+#define SEG103  3
+#define SEG104  4
+#define SEG105  5
+#define SEG106  6
+#define SEG107  7
+
+#define LCDDR6  _SFR_MEM8(0xF2)
+#define SEG108  0
+#define SEG109  1
+#define SEG110  2
+#define SEG111  3
+#define SEG112  4
+#define SEG113  5
+#define SEG114  6
+#define SEG115  7
+
+#define LCDDR7  _SFR_MEM8(0xF3)
+#define SEG116  0
+#define SEG117  1
+#define SEG118  2
+#define SEG119  3
+#define SEG120  4
+#define SEG121  5
+#define SEG122  6
+#define SEG123  7
+
+#define LCDDR8  _SFR_MEM8(0xF4)
+#define SEG124  0
+#define SEG125  1
+#define SEG126  2
+#define SEG127  3
+#define SEG128  4
+#define SEG129  5
+#define SEG130  6
+#define SEG131  7
+
+/* Reserved [0xF5] */
+
+#define LCDDR10 _SFR_MEM8(0xF6)
+#define SEG200  0
+#define SEG201  1
+#define SEG202  2
+#define SEG203  3
+#define SEG204  4
+#define SEG205  5
+#define SEG206  6
+#define SEG207  7
+
+#define LCDDR11 _SFR_MEM8(0xF7)
+#define SEG208  0
+#define SEG209  1
+#define SEG210  2
+#define SEG211  3
+#define SEG212  4
+#define SEG213  5
+#define SEG214  6
+#define SEG215  7
+
+#define LCDDR12 _SFR_MEM8(0xF8)
+#define SEG216  0
+#define SEG217  1
+#define SEG218  2
+#define SEG219  3
+#define SEG220  4
+#define SEG221  5
+#define SEG222  6
+#define SEG223  7
+
+#define LCDDR13 _SFR_MEM8(0xF9)
+#define SEG224  0
+#define SEG225  1
+#define SEG226  2
+#define SEG227  3
+#define SEG228  4
+#define SEG229  5
+#define SEG230  6
+#define SEG231  7
+
+/* Reserved [0xFA] */
+
+#define LCDDR15 _SFR_MEM8(0xFB)
+#define SEG300  0
+#define SEG301  1
+#define SEG302  2
+#define SEG303  3
+#define SEG304  4
+#define SEG305  5
+#define SEG306  6
+#define SEG307  7
+
+#define LCDDR16 _SFR_MEM8(0xFC)
+#define SEG308  0
+#define SEG309  1
+#define SEG310  2
+#define SEG311  3
+#define SEG312  4
+#define SEG313  5
+#define SEG314  6
+#define SEG315  7
+
+#define LCDDR17 _SFR_MEM8(0xFD)
+#define SEG316  0
+#define SEG317  1
+#define SEG318  2
+#define SEG319  3
+#define SEG320  4
+#define SEG321  5
+#define SEG322  6
+#define SEG323  7
+
+#define LCDDR18 _SFR_MEM8(0xFE)
+#define SEG324  0
+#define SEG325  1
+#define SEG326  2
+#define SEG327  3
+#define SEG328  4
+#define SEG329  5
+#define SEG330  6
+#define SEG331  7
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(2)
+#define PCINT0_vect_num        2
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(3)
+#define PCINT1_vect_num        3
+
+/* Timer/Counter2 Compare Match */
+#define TIMER2_COMP_vect            _VECTOR(4)
+#define TIMER2_COMP_vect_num        4
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(5)
+#define TIMER2_OVF_vect_num        5
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(6)
+#define TIMER1_CAPT_vect_num        6
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(7)
+#define TIMER1_COMPA_vect_num        7
+
+/* Timer/Counter Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(8)
+#define TIMER1_COMPB_vect_num        8
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(9)
+#define TIMER1_OVF_vect_num        9
+
+/* Timer/Counter0 Compare Match */
+#define TIMER0_COMP_vect            _VECTOR(10)
+#define TIMER0_COMP_vect_num        10
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(11)
+#define TIMER0_OVF_vect_num        11
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(12)
+#define SPI_STC_vect_num        12
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect            _VECTOR(13)
+#define USART0_RX_vect_num        13
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect            _VECTOR(14)
+#define USART0_UDRE_vect_num        14
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect            _VECTOR(15)
+#define USART0_TX_vect_num        15
+
+/* USI Start Condition */
+#define USI_START_vect            _VECTOR(16)
+#define USI_START_vect_num        16
+
+/* USI Overflow */
+#define USI_OVERFLOW_vect            _VECTOR(17)
+#define USI_OVERFLOW_vect_num        17
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect            _VECTOR(18)
+#define ANALOG_COMP_vect_num        18
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(19)
+#define ADC_vect_num        19
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(20)
+#define EE_READY_vect_num        20
+
+/* Store Program Memory Read */
+#define SPM_READY_vect            _VECTOR(21)
+#define SPM_READY_vect_num        21
+
+/* LCD Start of Frame */
+#define LCD_vect            _VECTOR(22)
+#define LCD_vect_num        22
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 92
+#else
+#  define _VECTORS_SIZE 92U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x7FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x7FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      2048
+#  define RAMEND       0x08FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      2048U
+#  define RAMEND       0x08FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  4
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  4U
+#  define E2END       0x03FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x0B
+
+
+
+
+#endif /* #ifdef _AVR_ATMEGA329P_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom329pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom329pa.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom329.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom32a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom32a.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA32A_H_INCLUDED
 #define _AVR_ATMEGA32A_H_INCLUDED
 
@@ -157,13 +140,29 @@
 
 #define DDRD    _SFR_IO8(0x11)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x12)
 #define PORTD7  7
@@ -187,13 +186,29 @@
 
 #define DDRC    _SFR_IO8(0x14)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x15)
 #define PORTC7  7
@@ -217,13 +232,29 @@
 
 #define DDRB    _SFR_IO8(0x17)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x18)
 #define PORTB7  7
@@ -247,13 +278,29 @@
 
 #define DDRA    _SFR_IO8(0x1A)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x1B)
 #define PORTA7  7
@@ -362,8 +409,8 @@
 #define COM1A1  7
 
 #define SFIOR   _SFR_IO8(0x30)
-#define PSR2    0
 #define PSR10   0
+#define PSR2    1
 #define PUD     2
 #define ACME    3
 #define ADTS0   5
@@ -469,6 +516,16 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<4)
+#define SLEEP_MODE_ADC (0x01<<4)
+#define SLEEP_MODE_PWR_DOWN (0x02<<4)
+#define SLEEP_MODE_PWR_SAVE (0x03<<4)
+#define SLEEP_MODE_STANDBY (0x06<<4)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<4)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -551,21 +608,44 @@
 #define SPM_RDY_vect            _VECTOR(20)
 #define SPM_RDY_vect_num        20
 
-#define _VECTORS_SIZE 84
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 84
+#else
+#  define _VECTORS_SIZE 84U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0x7FFF
-#define RAMSTART     0x0060
-#define RAMSIZE      2048
-#define RAMEND       0x085F
-#define E2START     0
-#define E2SIZE      1024
-#define E2PAGESIZE  4
-#define E2END       0x03FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x7FFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x7FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0060
+#  define RAMSIZE      2048
+#  define RAMEND       0x085F
+#else
+#  define RAMSTART     0x0060U
+#  define RAMSIZE      2048U
+#  define RAMEND       0x085FU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  4
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  4U
+#  define E2END       0x03FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -582,6 +662,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_BODEN       (unsigned char)~_BV(6)
 #define FUSE_BODLEVEL    (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -592,6 +674,8 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_JTAGEN      (unsigned char)~_BV(6)
 #define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
 
 
 /* Lock Bits */
@@ -607,12 +691,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<4)
-#define SLEEP_MODE_ADC (0x01<<4)
-#define SLEEP_MODE_PWR_DOWN (0x02<<4)
-#define SLEEP_MODE_PWR_SAVE (0x03<<4)
-#define SLEEP_MODE_STANDBY (0x06<<4)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<4)
 
 #endif /* #ifdef _AVR_ATMEGA32A_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom32c1.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom32c1.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom32c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */
 
 /* avr/iom32c1.h - definitions for ATmega32C1 */
 
@@ -1311,7 +1311,6 @@
 #define SIGNATURE_2 0x86
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom32hvb.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom32hvb.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom32hvb.h 2211 2011-02-14 14:04:25Z aboyapati $ */
 
 /* avr/iom32hvb.h - definitions for ATmega32HVB */
 
@@ -1043,7 +1043,6 @@
 #define OC_PIN   PINOC
 #define OC_BIT   OC
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom32hvbrevb.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom32hvbrevb.h
@@ -29,7 +29,7 @@
   POSSIBILITY OF SUCH DAMAGE. 
 */
 
-/* $Id$ */
+/* $Id: iom32hvbrevb.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* avr/iom32hvbrevb.h - definitions for ATmega32HVB revision B. */
 
@@ -945,11 +945,9 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_PWR_OFF (0x04<<1)
 
-
 #endif  /* _AVR_IOM32HVBREVB_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom32m1.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom32m1.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom32m1.h 2235 2011-03-17 04:13:14Z arcanum $ */
 
 /* avr/iom32m1.h - definitions for ATmega32M1 */
 
@@ -1616,7 +1616,6 @@
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom32u2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom32u2.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom32u2.h 2240 2011-05-09 22:18:18Z arcanum $ */
 
 /* avr/iom32u2.h - definitions for ATmega32U2 */
 
@@ -990,8 +990,6 @@
 #define SIGNATURE_2 0x8A
 
 
-/* Device Pin Definitions */
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom32u4.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom32u4.h
@@ -26,10 +26,10 @@
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
+  POSSIBILITY OF SUCH DAMAGE.
 */
 
-/* $Id$ */
+/* $Id: iom32u4.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/iom32u4.h - definitions for ATmega32U4. */
 
@@ -43,7 +43,7 @@
 #  define _AVR_IOXXX_H_ "iom32u4.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_IOM32U4_H_
@@ -462,11 +462,13 @@
 #define PRR1 _SFR_MEM8(0x65)
 #define PRUSART1 0
 #define PRTIM3 3
+#define PRTIM4 4
 #define PRUSB 7
 
-#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRUSB))
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM4)|(1<<PRTIM3)|(1<<PRUSB))
 #define __AVR_HAVE_PRR1_PRUSART1
 #define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRTIM4
 #define __AVR_HAVE_PRR1_PRUSB
 
 #define OSCCAL _SFR_MEM8(0x66)
@@ -642,9 +644,9 @@
 #define ICNC1 7
 
 #define TCCR1C _SFR_MEM8(0x82)
-#define FOC1C 5 
-#define FOC1B 6 
-#define FOC1A 7 
+#define FOC1C 5
+#define FOC1B 6
+#define FOC1A 7
 
 /* Reserved [0x83] */
 
@@ -1448,7 +1450,7 @@
 #define XRAMSIZE     (0x10000)
 #define XRAMEND      (XRAMSIZE - 1)
 #define E2END        (0x3FF)
-#define E2PAGESIZE   (4) 
+#define E2PAGESIZE   (4)
 #define FLASHEND     (0x7FFF)
 
 
@@ -1490,7 +1492,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom32u6.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom32u6.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom32u6.h 1873 2009-02-11 17:53:39Z arcanum $ */
 
 /* avr/iom32u6.h - definitions for ATmega32U6 */
 
@@ -1420,7 +1420,6 @@
 #define SIGNATURE_2 0x88
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom406.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom406.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom406.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/iom406.h - definitions for ATmega406 */
 
@@ -780,5 +780,4 @@
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_PWR_OFF (0x04<<1)
 
-
 #endif /* _AVR_IOM406_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom48.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom48.h
@@ -28,12 +28,769 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom48.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 #ifndef _AVR_IOM48_H_
 #define _AVR_IOM48_H_ 1
 
-#include <avr/iomx8.h>
+/* I/O registers */
+
+/* Port B */
+
+#define PINB    _SFR_IO8 (0x03)
+/* PINB */
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8 (0x04)
+/* DDRB */
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8 (0x05)
+/* PORTB */
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+/* Port C */
+
+#define PINC    _SFR_IO8 (0x06)
+/* PINC */
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8 (0x07)
+/* DDRC */
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8 (0x08)
+/* PORTC */
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC3     3
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+/* Port D */
+
+#define PIND    _SFR_IO8 (0x09)
+/* PIND */
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8 (0x0A)
+/* DDRD */
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8 (0x0B)
+/* PORTD */
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+#define TIFR0   _SFR_IO8 (0x15)
+/* TIFR0 */
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8 (0x16)
+/* TIFR1 */
+#define ICF1    5
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8 (0x17)
+/* TIFR2 */
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define PCIFR   _SFR_IO8 (0x1B)
+/* PCIFR */
+#define PCIF2   2
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8 (0x1C)
+/* EIFR */
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8 (0x1D)
+/* EIMSK */
+#define INT1    1
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8 (0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+/* EECT - EEPROM Control Register */
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0X22)
+/* 
+Even though EEARH is not used by the mega48, the EEAR8 bit in the register
+must be written to 0, according to the datasheet, hence the EEARH register
+must be defined for the mega48.
+*/
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+
+#define GTCCR   _SFR_IO8 (0x23)
+/* GTCCR */
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8 (0x24)
+/* TCCR0A */
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8 (0x25)
+/* TCCR0A */
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8 (0x26)
+#define OCR0A   _SFR_IO8 (0x27)
+#define OCR0B   _SFR_IO8 (0x28)
+
+#define GPIOR1  _SFR_IO8 (0x2A)
+#define GPIOR2  _SFR_IO8 (0x2B)
+
+#define SPCR    _SFR_IO8 (0x2C)
+/* SPCR */
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8 (0x2D)
+/* SPSR */
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8 (0x2E)
+
+#define ACSR    _SFR_IO8 (0x30)
+/* ACSR */
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8 (0x31)
+
+#define SMCR    _SFR_IO8 (0x33)
+/* SMCR */
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8 (0x34)
+/* MCUSR */
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8 (0x35)
+/* MCUCR */
+#define PUD     4
+#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)  || defined (__AVR_ATmega48A__) || defined(__AVR_ATmega48PA__)
+#define IVSEL   1
+#define IVCE    0
+#endif
+
+#define SPMCSR  _SFR_IO8 (0x37)
+/* SPMCSR */
+#define SPMIE     7
+#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || (__AVR_ATmega88P__) || defined (__AVR_ATmega168P__) || (__AVR_ATmega88A__) || defined (__AVR_ATmega168A__) || (__AVR_ATmega88PA__) || defined (__AVR_ATmega168PA__)
+#  define RWWSB   6
+#  define RWWSRE  4
+#endif
+#if defined(__AVR_ATmega48A) || defined(__AVR_ATmega48PA) || defined(__AVR_ATmega88A) || defined(__AVR_ATmega88PA) || defined(__AVR_ATmega168A) || defined(__AVR_ATmega168PA)
+	#define SIGRD 5
+#endif
+#define BLBSET    3
+#define PGWRT     2
+#define PGERS     1
+#define SELFPRGEN 0
+#define SPMEN     0
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+#define WDTCSR  _SFR_MEM8 (0x60)
+/* WDTCSR */
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8 (0x61)
+/* CLKPR */
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define PRR     _SFR_MEM8 (0x64)
+/* PRR */
+#define PRTWI    7
+#define PRTIM2   6
+#define PRTIM0   5
+#define PRTIM1   3
+#define PRSPI    2
+#define PRUSART0 1
+#define PRADC    0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRTWI
+
+#define OSCCAL  _SFR_MEM8 (0x66)
+
+#define PCICR   _SFR_MEM8 (0x68)
+/* PCICR */
+#define PCIE2   2
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8 (0x69)
+/* EICRA */
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define PCMSK0  _SFR_MEM8 (0x6B)
+/* PCMSK0 */
+#define PCINT7    7
+#define PCINT6    6
+#define PCINT5    5
+#define PCINT4    4
+#define PCINT3    3
+#define PCINT2    2
+#define PCINT1    1
+#define PCINT0    0
+
+#define PCMSK1  _SFR_MEM8 (0x6C)
+/* PCMSK1 */
+#define PCINT14   6
+#define PCINT13   5
+#define PCINT12   4
+#define PCINT11   3
+#define PCINT10   2
+#define PCINT9    1
+#define PCINT8    0
+
+#define PCMSK2  _SFR_MEM8 (0x6D)
+/* PCMSK2 */
+#define PCINT23   7
+#define PCINT22   6
+#define PCINT21   5
+#define PCINT20   4
+#define PCINT19   3
+#define PCINT18   2
+#define PCINT17   1
+#define PCINT16   0
+
+#define TIMSK0  _SFR_MEM8 (0x6E)
+/* TIMSK0 */
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8 (0x6F)
+/* TIMSK1 */
+#define ICIE1   5
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8 (0x70)
+/* TIMSK2 */
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16 (0x78)
+#endif
+#define ADCW    _SFR_MEM16 (0x78)
+#define ADCL    _SFR_MEM8 (0x78)
+#define ADCH    _SFR_MEM8 (0x79)
+
+#define ADCSRA  _SFR_MEM8 (0x7A)
+/* ADCSRA */
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8 (0x7B)
+/* ADCSRB */
+#define ACME    6
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8 (0x7C)
+/* ADMUX */
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define DIDR0   _SFR_MEM8 (0x7E)
+/* DIDR0 */
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8 (0x7F)
+/* DIDR1 */
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8 (0x80)
+/* TCCR1A */
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8 (0x81)
+/* TCCR1B */
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8 (0x82)
+/* TCCR1C */
+#define FOC1A   7
+#define FOC1B   6
+
+#define TCNT1   _SFR_MEM16 (0x84)
+#define TCNT1L  _SFR_MEM8 (0x84)
+#define TCNT1H  _SFR_MEM8 (0x85)
+
+#define ICR1    _SFR_MEM16 (0x86)
+#define ICR1L   _SFR_MEM8 (0x86)
+#define ICR1H   _SFR_MEM8 (0x87)
+
+#define OCR1A   _SFR_MEM16 (0x88)
+#define OCR1AL  _SFR_MEM8 (0x88)
+#define OCR1AH  _SFR_MEM8 (0x89)
+
+#define OCR1B   _SFR_MEM16 (0x8A)
+#define OCR1BL  _SFR_MEM8 (0x8A)
+#define OCR1BH  _SFR_MEM8 (0x8B)
+
+#define TCCR2A  _SFR_MEM8 (0xB0)
+/* TCCR2A */
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8 (0xB1)
+/* TCCR2B */
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8 (0xB2)
+#define OCR2A   _SFR_MEM8 (0xB3)
+#define OCR2B   _SFR_MEM8 (0xB4)
+
+#define ASSR    _SFR_MEM8 (0xB6)
+/* ASSR */
+#define EXCLK    6
+#define AS2      5
+#define TCN2UB   4
+#define OCR2AUB  3
+#define OCR2BUB  2
+#define TCR2AUB  1
+#define TCR2BUB  0
+
+#define TWBR    _SFR_MEM8 (0xB8)
+
+#define TWSR    _SFR_MEM8 (0xB9)
+/* TWSR */
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8 (0xBA)
+/* TWAR */
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8 (0xBB)
+
+#define TWCR    _SFR_MEM8 (0xBC)
+/* TWCR */
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8 (0xBD)
+/* TWAMR */
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+#define UCSR0A  _SFR_MEM8 (0xC0)
+/* UCSR0A */
+#define RXC0    7
+#define TXC0    6
+#define UDRE0   5
+#define FE0     4
+#define DOR0    3
+#define UPE0    2
+#define U2X0    1
+#define MPCM0   0
+
+#define UCSR0B  _SFR_MEM8 (0xC1)
+/* UCSR0B */
+#define RXCIE0  7
+#define TXCIE0  6
+#define UDRIE0  5
+#define RXEN0   4
+#define TXEN0   3
+#define UCSZ02  2
+#define RXB80   1
+#define TXB80   0
+
+#define UCSR0C  _SFR_MEM8 (0xC2)
+/* UCSR0C */
+#define UMSEL01  7
+#define UMSEL00  6
+#define UPM01    5
+#define UPM00    4
+#define USBS0    3
+#define UCSZ01   2
+#define UDORD0   2
+#define UCSZ00   1
+#define UCPHA0   1
+#define UCPOL0   0
+
+#define UBRR0   _SFR_MEM16 (0xC4)
+#define UBRR0L  _SFR_MEM8 (0xC4)
+#define UBRR0H  _SFR_MEM8 (0xC5)
+#define UDR0    _SFR_MEM8 (0xC6)
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		3
+#define PCINT0_vect			_VECTOR(3)
+#define SIG_PIN_CHANGE0			_VECTOR(3)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num		4
+#define PCINT1_vect			_VECTOR(4)
+#define SIG_PIN_CHANGE1			_VECTOR(4)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT2_vect_num		5
+#define PCINT2_vect			_VECTOR(5)
+#define SIG_PIN_CHANGE2			_VECTOR(5)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		6
+#define WDT_vect			_VECTOR(6)
+#define SIG_WATCHDOG_TIMEOUT		_VECTOR(6)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	7
+#define TIMER2_COMPA_vect		_VECTOR(7)
+#define SIG_OUTPUT_COMPARE2A		_VECTOR(7)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect_num	8
+#define TIMER2_COMPB_vect		_VECTOR(8)
+#define SIG_OUTPUT_COMPARE2B		_VECTOR(8)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		9
+#define TIMER2_OVF_vect			_VECTOR(9)
+#define SIG_OVERFLOW2			_VECTOR(9)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	10
+#define TIMER1_CAPT_vect		_VECTOR(10)
+#define SIG_INPUT_CAPTURE1		_VECTOR(10)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	11
+#define TIMER1_COMPA_vect		_VECTOR(11)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(11)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	12
+#define TIMER1_COMPB_vect		_VECTOR(12)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(12)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		13
+#define TIMER1_OVF_vect			_VECTOR(13)
+#define SIG_OVERFLOW1			_VECTOR(13)
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	14
+#define TIMER0_COMPA_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(14)
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	15
+#define TIMER0_COMPB_vect		_VECTOR(15)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(15)
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect_num		16
+#define TIMER0_OVF_vect			_VECTOR(16)
+#define SIG_OVERFLOW0			_VECTOR(16)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		17
+#define SPI_STC_vect			_VECTOR(17)
+#define SIG_SPI				_VECTOR(17)
+
+/* USART Rx Complete */
+#define USART_RX_vect_num		18
+#define USART_RX_vect			_VECTOR(18)
+#define SIG_USART_RECV			_VECTOR(18)
+
+/* USART, Data Register Empty */
+#define USART_UDRE_vect_num		19
+#define USART_UDRE_vect			_VECTOR(19)
+#define SIG_USART_DATA			_VECTOR(19)
+
+/* USART Tx Complete */
+#define USART_TX_vect_num		20
+#define USART_TX_vect			_VECTOR(20)
+#define SIG_USART_TRANS			_VECTOR(20)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		21
+#define ADC_vect			_VECTOR(21)
+#define SIG_ADC				_VECTOR(21)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		22
+#define EE_READY_vect			_VECTOR(22)
+#define SIG_EEPROM_READY		_VECTOR(22)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	23
+#define ANALOG_COMP_vect		_VECTOR(23)
+#define SIG_COMPARATOR			_VECTOR(23)
+
+/* Two-wire Serial Interface */
+#define TWI_vect_num		24
+#define TWI_vect			_VECTOR(24)
+#define SIG_TWI				_VECTOR(24)
+#define SIG_2WIRE_SERIAL		_VECTOR(24)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		25
+#define SPM_READY_vect			_VECTOR(25)
+#define SIG_SPM_READY			_VECTOR(25)
+
+/* The mega48 and mega88 vector tables are single instruction entries (16 bits
+   per entry for an RJMP) while the mega168 table has double instruction
+   entries (32 bits per entry for a JMP). */
+
+#if defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__)
+#  define _VECTORS_SIZE 104
+#else
+#  define _VECTORS_SIZE 52
+#endif
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART_RECV
+#pragma GCC poison SIG_USART_DATA
+#pragma GCC poison SIG_USART_TRANS
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_TWI
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
+
 
 /* Constants */
 #define SPM_PAGESIZE 64
@@ -84,12 +841,10 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x05
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM48_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom48a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom48a.h
@@ -1,36 +1,35 @@
-
-/* Copyright (c) 2004, Theodore A. Roth
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* $Id$ */
-
-#include "iom48.h"
-
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom48.h"
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom48p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom48p.h
@@ -29,7 +29,7 @@
   POSSIBILITY OF SUCH DAMAGE. 
 */
 
-/* $Id$ */
+/* $Id: iom48p.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/iom48p.h - definitions for ATmega48P. */
 
@@ -926,7 +926,6 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x0A
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -934,5 +933,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif  /* _AVR_IOM48P_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom48pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom48pa.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA48PA_H_INCLUDED
 #define _AVR_ATMEGA48PA_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRB    _SFR_IO8(0x04)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x05)
 #define PORTB7  7
@@ -91,12 +90,26 @@
 
 #define DDRC    _SFR_IO8(0x07)
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x08)
 #define PORTC6  6
@@ -119,13 +132,29 @@
 
 #define DDRD    _SFR_IO8(0x0A)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0B)
 #define PORTD7  7
@@ -184,7 +213,9 @@
 
 #define EEARL   _SFR_IO8(0x21)
 
-/* Reserved [0x22] */
+#define EEARH   _SFR_IO8(0x22)
+#define EEAR8   0
+#define EEAR9   1
 
 #define GTCCR   _SFR_IO8(0x23)
 #define PSRSYNC 0
@@ -263,6 +294,8 @@
 #define WDRF    3
 
 #define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
 #define PUD     4
 #define BODSE   5
 #define BODS    6
@@ -270,11 +303,12 @@
 /* Reserved [0x36] */
 
 #define SPMCSR  _SFR_IO8(0x37)
-#define SELFPRGEN 0
+#define SPMEN   0
 #define PGERS   1
 #define PGWRT   2
 #define BLBSET  3
 #define RWWSRE  4
+#define SIGRD   5
 #define RWWSB   6
 #define SPMIE   7
 
@@ -612,6 +646,16 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -714,21 +758,44 @@
 #define SPM_Ready_vect            _VECTOR(25)
 #define SPM_Ready_vect_num        25
 
-#define _VECTORS_SIZE 52
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 52
+#else
+#  define _VECTORS_SIZE 52U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x0000
-#define FLASHEND     0x0FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      256
-#define E2PAGESIZE  4
-#define E2END       0x00FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x0FFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x0FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      256
+#  define E2PAGESIZE  4
+#  define E2END       0x00FF
+#else
+#  define E2START     0U
+#  define E2SIZE      256U
+#  define E2PAGESIZE  4U
+#  define E2END       0x00FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -745,6 +812,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
@@ -755,9 +824,13 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_DWEN        (unsigned char)~_BV(6)
 #define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -771,12 +844,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 #endif /* #ifdef _AVR_ATMEGA48PA_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom48pb.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom48pb.h
@@ -1,890 +1,898 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATMEGA48PB_H_INCLUDED
-#define _AVR_ATMEGA48PB_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom48pb.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDRB7   7
-// Inserted "DDB7" from "DDRB7" due to compatibility
-#define DDB7    7
-#define DDRB6   6
-// Inserted "DDB6" from "DDRB6" due to compatibility
-#define DDB6    6
-#define DDRB5   5
-// Inserted "DDB5" from "DDRB5" due to compatibility
-#define DDB5    5
-#define DDRB4   4
-// Inserted "DDB4" from "DDRB4" due to compatibility
-#define DDB4    4
-#define DDRB3   3
-// Inserted "DDB3" from "DDRB3" due to compatibility
-#define DDB3    3
-#define DDRB2   2
-// Inserted "DDB2" from "DDRB2" due to compatibility
-#define DDB2    2
-#define DDRB1   1
-// Inserted "DDB1" from "DDRB1" due to compatibility
-#define DDB1    1
-#define DDRB0   0
-// Inserted "DDB0" from "DDRB0" due to compatibility
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDRC6   6
-// Inserted "DDC6" from "DDRC6" due to compatibility
-#define DDC6    6
-#define DDRC5   5
-// Inserted "DDC5" from "DDRC5" due to compatibility
-#define DDC5    5
-#define DDRC4   4
-// Inserted "DDC4" from "DDRC4" due to compatibility
-#define DDC4    4
-#define DDRC3   3
-// Inserted "DDC3" from "DDRC3" due to compatibility
-#define DDC3    3
-#define DDRC2   2
-// Inserted "DDC2" from "DDRC2" due to compatibility
-#define DDC2    2
-#define DDRC1   1
-// Inserted "DDC1" from "DDRC1" due to compatibility
-#define DDC1    1
-#define DDRC0   0
-// Inserted "DDC0" from "DDRC0" due to compatibility
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PORTC6  6
-#define PORTC5  5
-#define PORTC4  4
-#define PORTC3  3
-#define PORTC2  2
-#define PORTC1  1
-#define PORTC0  0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDRD7   7
-// Inserted "DDD7" from "DDRD7" due to compatibility
-#define DDD7    7
-#define DDRD6   6
-// Inserted "DDD6" from "DDRD6" due to compatibility
-#define DDD6    6
-#define DDRD5   5
-// Inserted "DDD5" from "DDRD5" due to compatibility
-#define DDD5    5
-#define DDRD4   4
-// Inserted "DDD4" from "DDRD4" due to compatibility
-#define DDD4    4
-#define DDRD3   3
-// Inserted "DDD3" from "DDRD3" due to compatibility
-#define DDD3    3
-#define DDRD2   2
-// Inserted "DDD2" from "DDRD2" due to compatibility
-#define DDD2    2
-#define DDRD1   1
-// Inserted "DDD1" from "DDRD1" due to compatibility
-#define DDD1    1
-#define DDRD0   0
-// Inserted "DDD0" from "DDRD0" due to compatibility
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PORTD7  7
-#define PORTD6  6
-#define PORTD5  5
-#define PORTD4  4
-#define PORTD3  3
-#define PORTD2  2
-#define PORTD1  1
-#define PORTD0  0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDRE3   3
-// Inserted "DDE3" from "DDRE3" due to compatibility
-#define DDE3    3
-#define DDRE2   2
-// Inserted "DDE2" from "DDRE2" due to compatibility
-#define DDE2    2
-#define DDRE1   1
-// Inserted "DDE1" from "DDRE1" due to compatibility
-#define DDE1    1
-#define DDRE0   0
-// Inserted "DDE0" from "DDRE0" due to compatibility
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PORTE3  3
-#define PORTE2  2
-#define PORTE1  1
-#define PORTE0  0
-
-#define ACSRB   _SFR_IO8(0x0F)
-#define ACOE    0
-
-/* Reserved [0x10..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-#define OCF0B   2
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-#define OCF2B   2
-
-/* Reserved [0x18..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-#define PCIF1   1
-#define PCIF2   2
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define INT1    1
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x20)
-
-#define EEARL   _SFR_IO8(0x21)
-
-/* Reserved [0x22] */
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM     7
-#define PSRASY  1
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0
-#define WGM01   1
-#define COM0B0  4
-#define COM0B1  5
-#define COM0A0  6
-#define COM0A1  7
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM02   3
-#define FOC0B   6
-#define FOC0A   7
-
-#define TCNT0   _SFR_IO8(0x26)
-
-#define OCR0A   _SFR_IO8(0x27)
-
-#define OCR0B   _SFR_IO8(0x28)
-
-/* Reserved [0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-/* Reserved [0x31..0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define PUD     4
-#define BODSE   5
-#define BODS    6
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDE     3
-#define WDCE    4
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0
-#define PRUSART0 1
-#define PRSPI   2
-#define PRTIM1  3
-#define PRTIM0  5
-#define PRTIM2  6
-#define PRTWI   7
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRUSART0
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRTIM1
-#define __AVR_HAVE_PRR_PRTIM0
-#define __AVR_HAVE_PRR_PRTIM2
-#define __AVR_HAVE_PRR_PRTWI
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-#define OSCCAL0 0
-#define OSCCAL1 1
-#define OSCCAL2 2
-#define OSCCAL3 3
-#define OSCCAL4 4
-#define OSCCAL5 5
-#define OSCCAL6 6
-#define OSCCAL7 7
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-#define PCIE1   1
-#define PCIE2   2
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2  _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-#define OCIE0B  2
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-#define OCIE2B  2
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define WGM20   0
-#define WGM21   1
-#define COM2B0  4
-#define COM2B1  5
-#define COM2A0  6
-#define COM2A1  7
-
-#define TCCR2B  _SFR_MEM8(0xB1)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM22   3
-#define FOC2B   6
-#define FOC2A   7
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-#define OCR2B   _SFR_MEM8(0xB4)
-
-/* Reserved [0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB  4
-#define AS2     5
-#define EXCLK   6
-
-/* Reserved [0xB7] */
-
-#define TWBR    _SFR_MEM8(0xB8)
-
-#define TWSR    _SFR_MEM8(0xB9)
-#define TWPS0   0
-#define TWPS1   1
-#define TWS3    3
-#define TWS4    4
-#define TWS5    5
-#define TWS6    6
-#define TWS7    7
-
-#define TWAR    _SFR_MEM8(0xBA)
-#define TWGCE   0
-#define TWA0    1
-#define TWA1    2
-#define TWA2    3
-#define TWA3    4
-#define TWA4    5
-#define TWA5    6
-#define TWA6    7
-
-#define TWDR    _SFR_MEM8(0xBB)
-
-#define TWCR    _SFR_MEM8(0xBC)
-#define TWIE    0
-#define TWEN    2
-#define TWWC    3
-#define TWSTO   4
-#define TWSTA   5
-#define TWEA    6
-#define TWINT   7
-
-#define TWAMR   _SFR_MEM8(0xBD)
-#define TWAM0   1
-#define TWAM1   2
-#define TWAM2   3
-#define TWAM3   4
-#define TWAM4   5
-#define TWAM5   6
-#define TWAM6   7
-
-/* Reserved [0xBE..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0xC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UCSR0D  _SFR_MEM8(0xC3)
-#define SFDE    5
-#define RXS     6
-#define RXSIE   7
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0xC6)
-
-/* Reserved [0xC7..0xEF] */
-
-#define DEVID0  _SFR_MEM8(0xF0)
-
-#define DEVID1  _SFR_MEM8(0xF1)
-
-#define DEVID2  _SFR_MEM8(0xF2)
-
-#define DEVID3  _SFR_MEM8(0xF3)
-
-#define DEVID4  _SFR_MEM8(0xF4)
-
-#define DEVID5  _SFR_MEM8(0xF5)
-
-#define DEVID6  _SFR_MEM8(0xF6)
-
-#define DEVID7  _SFR_MEM8(0xF7)
-
-#define DEVID8  _SFR_MEM8(0xF8)
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(3)
-#define PCINT0_vect_num        3
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT1_vect            _VECTOR(4)
-#define PCINT1_vect_num        4
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT2_vect            _VECTOR(5)
-#define PCINT2_vect_num        5
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect            _VECTOR(6)
-#define WDT_vect_num        6
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect            _VECTOR(7)
-#define TIMER2_COMPA_vect_num        7
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect            _VECTOR(8)
-#define TIMER2_COMPB_vect_num        8
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect            _VECTOR(9)
-#define TIMER2_OVF_vect_num        9
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(10)
-#define TIMER1_CAPT_vect_num        10
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect            _VECTOR(11)
-#define TIMER1_COMPA_vect_num        11
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect            _VECTOR(12)
-#define TIMER1_COMPB_vect_num        12
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(13)
-#define TIMER1_OVF_vect_num        13
-
-/* TimerCounter0 Compare Match A */
-#define TIMER0_COMPA_vect            _VECTOR(14)
-#define TIMER0_COMPA_vect_num        14
-
-/* TimerCounter0 Compare Match B */
-#define TIMER0_COMPB_vect            _VECTOR(15)
-#define TIMER0_COMPB_vect_num        15
-
-/* Timer/Couner0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(16)
-#define TIMER0_OVF_vect_num        16
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect            _VECTOR(17)
-#define SPI_STC_vect_num        17
-
-/* USART Rx Complete */
-#define USART_RX_vect            _VECTOR(18)
-#define USART_RX_vect_num        18
-
-/* USART, Data Register Empty */
-#define USART_UDRE_vect            _VECTOR(19)
-#define USART_UDRE_vect_num        19
-
-/* USART Tx Complete */
-#define USART_TX_vect            _VECTOR(20)
-#define USART_TX_vect_num        20
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(21)
-#define ADC_vect_num        21
-
-/* EEPROM Ready */
-#define EE_READY_vect            _VECTOR(22)
-#define EE_READY_vect_num        22
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect            _VECTOR(23)
-#define ANALOG_COMP_vect_num        23
-
-/* Two-wire Serial Interface */
-#define TWI_vect            _VECTOR(24)
-#define TWI_vect_num        24
-
-/* Store Program Memory Read */
-#define SPM_Ready_vect            _VECTOR(25)
-#define SPM_Ready_vect_num        25
-
-/* USART Start Edge Interrupt */
-#define USART_START_vect            _VECTOR(26)
-#define USART_START_vect_num        26
-
-#define _VECTORS_SIZE 54
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x0000
-#define FLASHEND     0x0FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      256
-#define E2PAGESIZE  4
-#define E2END       0x00FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT    (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x10
-
-
-#endif /* #ifdef _AVR_ATMEGA48PB_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATMEGA48PB_H_INCLUDED
+#define _AVR_ATMEGA48PB_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iom48pb.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
+#define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
+#define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
+#define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+/* Reserved [0x0F..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEARL   _SFR_IO8(0x21)
+
+/* Reserved [0x22] */
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM     7
+#define PSRASY  1
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define ACSRB   _SFR_IO8(0x2F)
+#define ACOE    0
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+/* Reserved [0x31..0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define PUD     4
+#define BODSE   5
+#define BODS    6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62..0x63] */
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+/* Reserved [0x71..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+#define UCSR0D  _SFR_MEM8(0xC3)
+#define SFDE    5
+#define RXS     6
+#define RXSIE   7
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7..0xEF] */
+
+#define DEVID0  _SFR_MEM8(0xF0)
+
+#define DEVID1  _SFR_MEM8(0xF1)
+
+#define DEVID2  _SFR_MEM8(0xF2)
+
+#define DEVID3  _SFR_MEM8(0xF3)
+
+#define DEVID4  _SFR_MEM8(0xF4)
+
+#define DEVID5  _SFR_MEM8(0xF5)
+
+#define DEVID6  _SFR_MEM8(0xF6)
+
+#define DEVID7  _SFR_MEM8(0xF7)
+
+#define DEVID8  _SFR_MEM8(0xF8)
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT2_vect            _VECTOR(5)
+#define PCINT2_vect_num        5
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(6)
+#define WDT_vect_num        6
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(7)
+#define TIMER2_COMPA_vect_num        7
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect            _VECTOR(8)
+#define TIMER2_COMPB_vect_num        8
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(9)
+#define TIMER2_OVF_vect_num        9
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(10)
+#define TIMER1_CAPT_vect_num        10
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(11)
+#define TIMER1_COMPA_vect_num        11
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(12)
+#define TIMER1_COMPB_vect_num        12
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(13)
+#define TIMER1_OVF_vect_num        13
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(14)
+#define TIMER0_COMPA_vect_num        14
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(15)
+#define TIMER0_COMPB_vect_num        15
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(16)
+#define TIMER0_OVF_vect_num        16
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(17)
+#define SPI_STC_vect_num        17
+
+/* USART Rx Complete */
+#define USART_RX_vect            _VECTOR(18)
+#define USART_RX_vect_num        18
+
+/* USART, Data Register Empty */
+#define USART_UDRE_vect            _VECTOR(19)
+#define USART_UDRE_vect_num        19
+
+/* USART Tx Complete */
+#define USART_TX_vect            _VECTOR(20)
+#define USART_TX_vect_num        20
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(21)
+#define ADC_vect_num        21
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(22)
+#define EE_READY_vect_num        22
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect            _VECTOR(23)
+#define ANALOG_COMP_vect_num        23
+
+/* Two-wire Serial Interface */
+#define TWI_vect            _VECTOR(24)
+#define TWI_vect_num        24
+
+/* Store Program Memory Read */
+#define SPM_Ready_vect            _VECTOR(25)
+#define SPM_Ready_vect_num        25
+
+/* USART Start Edge Interrupt */
+#define USART_START_vect            _VECTOR(26)
+#define USART_START_vect_num        26
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 54
+#else
+#  define _VECTORS_SIZE 54U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x0FFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x0FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      256
+#  define E2PAGESIZE  4
+#  define E2END       0x00FF
+#else
+#  define E2START     0U
+#  define E2SIZE      256U
+#  define E2PAGESIZE  4U
+#  define E2END       0x00FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x92
+#define SIGNATURE_2 0x10
+
+
+
+
+#endif /* #ifdef _AVR_ATMEGA48PB_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom64.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom64.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom64.h 2235 2011-03-17 04:13:14Z arcanum $ */
 
 /* avr/iom64.h - defines for ATmega64 
 
@@ -1301,7 +1301,6 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<2)
 #define SLEEP_MODE_ADC (0x02<<2)
 #define SLEEP_MODE_PWR_DOWN (0x04<<2)
@@ -1309,5 +1308,4 @@
 #define SLEEP_MODE_STANDBY (0x05<<2)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<2)
 
-
 #endif /* _AVR_IOM64_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom640.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom640.h
@@ -28,14 +28,1613 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom640.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* avr/iom640.h - definitions for ATmega640 */
 
 #ifndef _AVR_IOM640_H_
 #define _AVR_IOM640_H_ 1
 
-#include <avr/iomxx0_1.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iomxx0_1.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0X01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0X02)
+#define PA7     7
+#define PA6     6
+#define PA5     5
+#define PA4     4
+#define PA3     3
+#define PA2     2
+#define PA1     1
+#define PA0     0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7     7
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC3     3
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7     7
+#define PE6     6
+#define PE5     5
+#define PE4     4
+#define PE3     3
+#define PE2     2
+#define PE1     1
+#define PE0     0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7     7
+#define PF6     6
+#define PF5     5
+#define PF4     4
+#define PF3     3
+#define PF2     2
+#define PF1     1
+#define PF0     0
+
+#define PING    _SFR_IO8(0x12)
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDG5    5
+#define DDG4    4
+#define DDG3    3
+#define DDG2    2
+#define DDG1    1
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PG5     5
+#define PG4     4
+#define PG3     3
+#define PG2     2
+#define PG1     1
+#define PG0     0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8(0x17)
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define TIFR3   _SFR_IO8(0x18)
+#define ICF3    5
+#define OCF3C   3
+#define OCF3B   2
+#define OCF3A   1
+#define TOV3    0
+
+#define TIFR4   _SFR_IO8(0x19)
+#define ICF4    5
+#define OCF4C   3
+#define OCF4B   2
+#define OCF4A   1
+#define TOV4    0
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define ICF5    5
+#define OCF5C   3
+#define OCF5B   2
+#define OCF5A   1
+#define TOV5    0
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF2  2
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR   _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0X27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0X2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8(0x31)
+#define OCDR    _SFR_IO8(0x31)
+#define IDRD    7
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0X35)
+#define JTD     7
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0X3B)
+#define RAMPZ0  0
+
+#define EIND    _SFR_IO8(0X3C)
+#define EIND0   0
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTWI       7
+#define PRTIM2      6
+#define PRTIM0      5
+#define PRTIM1      3
+#define PRSPI       2
+#define PRUSART0    1
+#define PRADC       0
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRUSART0
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRTIM5      5
+#define PRTIM4      4
+#define PRTIM3      3
+#define PRUSART3    2
+#define PRUSART2    1
+#define PRUSART1    0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRUSART2)|(1<<PRUSART3)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRUSART2
+#define __AVR_HAVE_PRR1_PRUSART3
+#define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRTIM4
+#define __AVR_HAVE_PRR1_PRTIM5
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE2  2
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+#define PCMSK2 _SFR_MEM8(0x6D)
+#define PCINT23 7
+#define PCINT22 6
+#define PCINT21 5
+#define PCINT20 4
+#define PCINT19 3
+#define PCINT18 2
+#define PCINT17 1
+#define PCINT16 0
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define ICIE3   5
+#define OCIE3C  3
+#define OCIE3B  2
+#define OCIE3A  1
+#define TOIE3   0
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define ICIE4   5
+#define OCIE4C  3
+#define OCIE4B  2
+#define OCIE4A  1
+#define TOIE4   0
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define ICIE5   5
+#define OCIE5C  3
+#define OCIE5B  2
+#define OCIE5A  1
+#define TOIE5   0
+
+#define XMCRA   _SFR_MEM8(0x74)
+#define SRE     7
+#define SRL2    6
+#define SRL1    5
+#define SRL0    4
+#define SRW11   3
+#define SRW10   2
+#define SRW01   1
+#define SRW00   0
+
+#define XMCRB   _SFR_MEM8(0x75)
+#define XMBK    7
+#define XMM2    2
+#define XMM1    1
+#define XMM0    0
+
+/* Reserved [0x76..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define MUX5    3
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC15D  7
+#define ADC14D  6
+#define ADC13D  5
+#define ADC12D  4
+#define ADC11D  3
+#define ADC10D  2
+#define ADC9D   1
+#define ADC8D   0
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define COM3A1  7
+#define COM3A0  6
+#define COM3B1  5
+#define COM3B0  4
+#define COM3C1  3
+#define COM3C0  2
+#define WGM31   1
+#define WGM30   0
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define ICNC3   7
+#define ICES3   6
+#define WGM33   4
+#define WGM32   3
+#define CS32    2
+#define CS31    1
+#define CS30    0
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3A   7
+#define FOC3B   6
+#define FOC3C   5
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define COM4A1  7
+#define COM4A0  6
+#define COM4B1  5
+#define COM4B0  4
+#define COM4C1  3
+#define COM4C0  2
+#define WGM41   1
+#define WGM40   0
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define ICNC4   7
+#define ICES4   6
+#define WGM43   4
+#define WGM42   3
+#define CS42    2
+#define CS41    1
+#define CS40    0
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4A   7
+#define FOC4B   6
+#define FOC4C   5
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define EXCLK   6
+#define AS2     5
+#define TCN2UB  4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define RXC0    7
+#define TXC0    6
+#define UDRE0   5
+#define FE0     4
+#define DOR0    3
+#define UPE0    2
+#define U2X0    1
+#define MPCM0   0
+
+#define UCSR0B  _SFR_MEM8(0XC1)
+#define RXCIE0  7
+#define TXCIE0  6
+#define UDRIE0  5
+#define RXEN0   4
+#define TXEN0   3
+#define UCSZ02  2
+#define RXB80   1
+#define TXB80   0
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UMSEL01 7
+#define UMSEL00 6
+#define UPM01   5
+#define UPM00   4
+#define USBS0   3
+#define UCSZ01  2
+#define UCSZ00  1
+#define UCPOL0  0
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0XC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF] */
+
+#define UCSR2A _SFR_MEM8(0xD0)
+#define RXC2   7
+#define TXC2   6
+#define UDRE2  5
+#define FE2    4
+#define DOR2   3
+#define UPE2   2
+#define U2X2   1
+#define MPCM2  0
+
+#define UCSR2B _SFR_MEM8(0XD1)
+#define RXCIE2 7
+#define TXCIE2 6
+#define UDRIE2 5
+#define RXEN2  4
+#define TXEN2  3
+#define UCSZ22 2
+#define RXB82  1
+#define TXB82  0
+
+#define UCSR2C _SFR_MEM8(0xD2)
+#define UMSEL21 7
+#define UMSEL20 6
+#define UPM21  5
+#define UPM20  4
+#define USBS2  3
+#define UCSZ21 2
+#define UCSZ20 1
+#define UCPOL2 0
+
+/* Reserved [0xD3] */
+
+/* Combine UBRR2L and UBRR2H */
+#define UBRR2  _SFR_MEM16(0xD4)
+
+#define UBRR2L _SFR_MEM8(0xD4)
+#define UBRR2H _SFR_MEM8(0xD5)
+
+#define UDR2   _SFR_MEM8(0XD6)
+
+/* Reserved [0xD7..0xFF] */
+
+#define PINH   _SFR_MEM8(0x100)
+#define PINH7  7
+#define PINH6  6
+#define PINH5  5
+#define PINH4  4
+#define PINH3  3
+#define PINH2  2
+#define PINH1  1
+#define PINH0  0
+
+#define DDRH   _SFR_MEM8(0x101)
+#define DDH7   7
+#define DDH6   6
+#define DDH5   5
+#define DDH4   4
+#define DDH3   3
+#define DDH2   2
+#define DDH1   1
+#define DDH0   0
+
+#define PORTH  _SFR_MEM8(0x102)
+#define PH7    7
+#define PH6    6
+#define PH5    5
+#define PH4    4
+#define PH3    3
+#define PH2    2
+#define PH1    1
+#define PH0    0
+
+#define PINJ   _SFR_MEM8(0x103)
+#define PINJ7  7
+#define PINJ6  6
+#define PINJ5  5
+#define PINJ4  4
+#define PINJ3  3
+#define PINJ2  2
+#define PINJ1  1
+#define PINJ0  0
+
+#define DDRJ   _SFR_MEM8(0x104)
+#define DDJ7   7
+#define DDJ6   6
+#define DDJ5   5
+#define DDJ4   4
+#define DDJ3   3
+#define DDJ2   2
+#define DDJ1   1
+#define DDJ0   0
+
+#define PORTJ  _SFR_MEM8(0x105)
+#define PJ7 7
+#define PJ6 6
+#define PJ5 5
+#define PJ4 4
+#define PJ3 3
+#define PJ2 2
+#define PJ1 1
+#define PJ0 0
+
+#define PINK   _SFR_MEM8(0x106)
+#define PINK7  7
+#define PINK6  6
+#define PINK5  5
+#define PINK4  4
+#define PINK3  3
+#define PINK2  2
+#define PINK1  1
+#define PINK0  0
+
+#define DDRK   _SFR_MEM8(0x107)
+#define DDK7   7
+#define DDK6   6
+#define DDK5   5
+#define DDK4   4
+#define DDK3   3
+#define DDK2   2
+#define DDK1   1
+#define DDK0   0
+
+#define PORTK  _SFR_MEM8(0x108)
+#define PK7 7
+#define PK6 6
+#define PK5 5
+#define PK4 4
+#define PK3 3
+#define PK2 2
+#define PK1 1
+#define PK0 0
+
+#define PINL   _SFR_MEM8(0x109)
+#define PINL7  7
+#define PINL6  6
+#define PINL5  5
+#define PINL4  4
+#define PINL3  3
+#define PINL2  2
+#define PINL1  1
+#define PINL0  0
+
+#define DDRL   _SFR_MEM8(0x10A)
+#define DDL7   7
+#define DDL6   6
+#define DDL5   5
+#define DDL4   4
+#define DDL3   3
+#define DDL2   2
+#define DDL1   1
+#define DDL0   0
+
+#define PORTL  _SFR_MEM8(0x10B)
+#define PL7 7
+#define PL6 6
+#define PL5 5
+#define PL4 4
+#define PL3 3
+#define PL2 2
+#define PL1 1
+#define PL0 0
+
+/* Reserved [0x10C..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define COM5A1  7
+#define COM5A0  6
+#define COM5B1  5
+#define COM5B0  4
+#define COM5C1  3
+#define COM5C0  2
+#define WGM51   1
+#define WGM50   0
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define ICNC5   7
+#define ICES5   6
+#define WGM53   4
+#define WGM52   3
+#define CS52    2
+#define CS51    1
+#define CS50    0
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5A   7
+#define FOC5B   6
+#define FOC5C   5
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E..0x12F] */
+
+#define UCSR3A _SFR_MEM8(0x130)
+#define RXC3   7
+#define TXC3   6
+#define UDRE3  5
+#define FE3    4
+#define DOR3   3
+#define UPE3   2
+#define U2X3   1
+#define MPCM3  0
+
+#define UCSR3B _SFR_MEM8(0X131)
+#define RXCIE3 7
+#define TXCIE3 6
+#define UDRIE3 5
+#define RXEN3  4
+#define TXEN3  3
+#define UCSZ32 2
+#define RXB83  1
+#define TXB83  0
+
+#define UCSR3C _SFR_MEM8(0x132)
+#define UMSEL31 7
+#define UMSEL30 6
+#define UPM31  5
+#define UPM30  4
+#define USBS3  3
+#define UCSZ31 2
+#define UCSZ30 1
+#define UCPOL3 0
+
+/* Reserved [0x133] */
+
+/* Combine UBRR3L and UBRR3H */
+#define UBRR3  _SFR_MEM16(0x134)
+
+#define UBRR3L _SFR_MEM8(0x134)
+#define UBRR3H _SFR_MEM8(0x135)
+
+#define UDR3   _SFR_MEM8(0X136)
+
+/* Reserved [0x137..1FF] */
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+#define SIG_INTERRUPT3			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+#define SIG_INTERRUPT4			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+#define SIG_INTERRUPT5			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num		7
+#define INT6_vect			_VECTOR(7)
+#define SIG_INTERRUPT6			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+#define SIG_INTERRUPT7			_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		9
+#define PCINT0_vect			_VECTOR(9)
+#define SIG_PIN_CHANGE0			_VECTOR(9)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		10
+#define PCINT1_vect			_VECTOR(10)
+#define SIG_PIN_CHANGE1			_VECTOR(10)
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect_num		11
+#define PCINT2_vect			_VECTOR(11)
+#define SIG_PIN_CHANGE2			_VECTOR(11)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		12
+#define WDT_vect			_VECTOR(12)
+#define SIG_WATCHDOG_TIMEOUT		_VECTOR(12)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	13
+#define TIMER2_COMPA_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE2A		_VECTOR(13)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	14
+#define TIMER2_COMPB_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE2B		_VECTOR(14)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		15
+#define TIMER2_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW2			_VECTOR(15)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	16
+#define TIMER1_CAPT_vect		_VECTOR(16)
+#define SIG_INPUT_CAPTURE1		_VECTOR(16)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	17
+#define TIMER1_COMPA_vect		_VECTOR(17)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(17)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	18
+#define TIMER1_COMPB_vect		_VECTOR(18)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(18)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	19
+#define TIMER1_COMPC_vect		_VECTOR(19)
+#define SIG_OUTPUT_COMPARE1C		_VECTOR(19)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		20
+#define TIMER1_OVF_vect			_VECTOR(20)
+#define SIG_OVERFLOW1			_VECTOR(20)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	21
+#define TIMER0_COMPA_vect		_VECTOR(21)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(21)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	22
+#define TIMER0_COMPB_vect		_VECTOR(22)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(22)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		23
+#define TIMER0_OVF_vect			_VECTOR(23)
+#define SIG_OVERFLOW0			_VECTOR(23)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		24
+#define SPI_STC_vect			_VECTOR(24)
+#define SIG_SPI				_VECTOR(24)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		25
+#define USART0_RX_vect			_VECTOR(25)
+#define SIG_USART0_RECV			_VECTOR(25)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	26
+#define USART0_UDRE_vect		_VECTOR(26)
+#define SIG_USART0_DATA			_VECTOR(26)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		27
+#define USART0_TX_vect			_VECTOR(27)
+#define SIG_USART0_TRANS		_VECTOR(27)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	28
+#define ANALOG_COMP_vect		_VECTOR(28)
+#define SIG_COMPARATOR			_VECTOR(28)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		29
+#define ADC_vect			_VECTOR(29)
+#define SIG_ADC				_VECTOR(29)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		30
+#define EE_READY_vect			_VECTOR(30)
+#define SIG_EEPROM_READY		_VECTOR(30)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	31
+#define TIMER3_CAPT_vect		_VECTOR(31)
+#define SIG_INPUT_CAPTURE3		_VECTOR(31)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	32
+#define TIMER3_COMPA_vect		_VECTOR(32)
+#define SIG_OUTPUT_COMPARE3A		_VECTOR(32)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	33
+#define TIMER3_COMPB_vect		_VECTOR(33)
+#define SIG_OUTPUT_COMPARE3B		_VECTOR(33)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	34
+#define TIMER3_COMPC_vect		_VECTOR(34)
+#define SIG_OUTPUT_COMPARE3C		_VECTOR(34)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		35
+#define TIMER3_OVF_vect			_VECTOR(35)
+#define SIG_OVERFLOW3			_VECTOR(35)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		36
+#define USART1_RX_vect			_VECTOR(36)
+#define SIG_USART1_RECV			_VECTOR(36)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num	37
+#define USART1_UDRE_vect		_VECTOR(37)
+#define SIG_USART1_DATA			_VECTOR(37)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		38
+#define USART1_TX_vect			_VECTOR(38)
+#define SIG_USART1_TRANS		_VECTOR(38)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num		39
+#define TWI_vect			_VECTOR(39)
+#define SIG_2WIRE_SERIAL		_VECTOR(39)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		40
+#define SPM_READY_vect			_VECTOR(40)
+#define SIG_SPM_READY			_VECTOR(40)
+
+/* Timer/Counter4 Capture Event */
+#define TIMER4_CAPT_vect_num	41
+#define TIMER4_CAPT_vect		_VECTOR(41)
+#define SIG_INPUT_CAPTURE4		_VECTOR(41)
+
+/* Timer/Counter4 Compare Match A */
+#define TIMER4_COMPA_vect_num	42
+#define TIMER4_COMPA_vect		_VECTOR(42)
+#define SIG_OUTPUT_COMPARE4A		_VECTOR(42)
+
+/* Timer/Counter4 Compare Match B */
+#define TIMER4_COMPB_vect_num	43
+#define TIMER4_COMPB_vect		_VECTOR(43)
+#define SIG_OUTPUT_COMPARE4B		_VECTOR(43)
+
+/* Timer/Counter4 Compare Match C */
+#define TIMER4_COMPC_vect_num	44
+#define TIMER4_COMPC_vect		_VECTOR(44)
+#define SIG_OUTPUT_COMPARE4C		_VECTOR(44)
+
+/* Timer/Counter4 Overflow */
+#define TIMER4_OVF_vect_num		45
+#define TIMER4_OVF_vect			_VECTOR(45)
+#define SIG_OVERFLOW4			_VECTOR(45)
+
+/* Timer/Counter5 Capture Event */
+#define TIMER5_CAPT_vect_num	46
+#define TIMER5_CAPT_vect		_VECTOR(46)
+#define SIG_INPUT_CAPTURE5		_VECTOR(46)
+
+/* Timer/Counter5 Compare Match A */
+#define TIMER5_COMPA_vect_num	47
+#define TIMER5_COMPA_vect		_VECTOR(47)
+#define SIG_OUTPUT_COMPARE5A		_VECTOR(47)
+
+/* Timer/Counter5 Compare Match B */
+#define TIMER5_COMPB_vect_num	48
+#define TIMER5_COMPB_vect		_VECTOR(48)
+#define SIG_OUTPUT_COMPARE5B		_VECTOR(48)
+
+/* Timer/Counter5 Compare Match C */
+#define TIMER5_COMPC_vect_num	49
+#define TIMER5_COMPC_vect		_VECTOR(49)
+#define SIG_OUTPUT_COMPARE5C		_VECTOR(49)
+
+/* Timer/Counter5 Overflow */
+#define TIMER5_OVF_vect_num		50
+#define TIMER5_OVF_vect			_VECTOR(50)
+#define SIG_OVERFLOW5			_VECTOR(50)
+
+/* USART2, Rx Complete */
+#define USART2_RX_vect_num		51
+#define USART2_RX_vect			_VECTOR(51)
+#define SIG_USART2_RECV			_VECTOR(51)
+
+/* USART2 Data register Empty */
+#define USART2_UDRE_vect_num		52
+#define USART2_UDRE_vect		_VECTOR(52)
+#define SIG_USART2_DATA			_VECTOR(52)
+
+/* USART2, Tx Complete */
+#define USART2_TX_vect_num		53
+#define USART2_TX_vect			_VECTOR(53)
+#define SIG_USART2_TRANS		_VECTOR(53)
+
+/* USART3, Rx Complete */
+#define USART3_RX_vect_num		54
+#define USART3_RX_vect			_VECTOR(54)
+#define SIG_USART3_RECV			_VECTOR(54)
+
+/* USART3 Data register Empty */
+#define USART3_UDRE_vect_num		55
+#define USART3_UDRE_vect		_VECTOR(55)
+#define SIG_USART3_DATA			_VECTOR(55)
+
+/* USART3, Tx Complete */
+#define USART3_TX_vect_num		56
+#define USART3_TX_vect			_VECTOR(56)
+#define SIG_USART3_TRANS		_VECTOR(56)
+
+# define _VECTORS_SIZE 228
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_INTERRUPT2
+#pragma GCC poison SIG_INTERRUPT3
+#pragma GCC poison SIG_INTERRUPT4
+#pragma GCC poison SIG_INTERRUPT5
+#pragma GCC poison SIG_INTERRUPT6
+#pragma GCC poison SIG_INTERRUPT7
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OUTPUT_COMPARE1C
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART0_RECV
+#pragma GCC poison SIG_USART0_DATA
+#pragma GCC poison SIG_USART0_TRANS
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_INPUT_CAPTURE3
+#pragma GCC poison SIG_OUTPUT_COMPARE3A
+#pragma GCC poison SIG_OUTPUT_COMPARE3B
+#pragma GCC poison SIG_OUTPUT_COMPARE3C
+#pragma GCC poison SIG_OVERFLOW3
+#pragma GCC poison SIG_USART1_RECV
+#pragma GCC poison SIG_USART1_DATA
+#pragma GCC poison SIG_USART1_TRANS
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+#pragma GCC poison SIG_INPUT_CAPTURE4
+#pragma GCC poison SIG_OUTPUT_COMPARE4A
+#pragma GCC poison SIG_OUTPUT_COMPARE4B
+#pragma GCC poison SIG_OUTPUT_COMPARE4C
+#pragma GCC poison SIG_OVERFLOW4
+#pragma GCC poison SIG_INPUT_CAPTURE5
+#pragma GCC poison SIG_OUTPUT_COMPARE5A
+#pragma GCC poison SIG_OUTPUT_COMPARE5B
+#pragma GCC poison SIG_OUTPUT_COMPARE5C
+#pragma GCC poison SIG_OVERFLOW5
+#pragma GCC poison SIG_USART2_RECV
+#pragma GCC poison SIG_USART2_DATA
+#pragma GCC poison SIG_USART2_TRANS
+#pragma GCC poison SIG_USART3_RECV
+#pragma GCC poison SIG_USART3_DATA
+#pragma GCC poison SIG_USART3_TRANS
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 /* Constants */
 #define SPM_PAGESIZE    256
@@ -91,7 +1690,6 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x08
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -99,5 +1697,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_IOM640_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom644.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom644.h
@@ -30,12 +30,916 @@
 
 /* avr/iom644.h - definitions for ATmega644 */
 
-/* $Id$ */
+/* $Id: iom644.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 #ifndef _AVR_IOM644_H_
 #define _AVR_IOM644_H_ 1
 
-#include <avr/iomxx4.h>
+
+/* Registers and associated bit numbers */
+
+#define PINA	_SFR_IO8(0X00)
+#define PINA7	7
+#define PINA6	6
+#define PINA5	5
+#define PINA4	4
+#define PINA3	3
+#define PINA2	2
+#define PINA1	1
+#define PINA0	0
+
+#define DDRA	_SFR_IO8(0X01)
+#define DDA7	7
+#define DDA6	6
+#define DDA5	5
+#define DDA4	4
+#define DDA3	3
+#define DDA2	2
+#define DDA1	1
+#define DDA0	0
+
+#define PORTA	_SFR_IO8(0X02)
+#define PA7	7
+#define PA6	6
+#define PA5	5
+#define PA4	4
+#define PA3	3
+#define PA2	2
+#define PA1	1
+#define PA0	0
+
+#define PINB	_SFR_IO8(0X03)
+#define PINB7	7
+#define PINB6	6
+#define PINB5	5
+#define PINB4	4
+#define PINB3	3
+#define PINB2	2
+#define PINB1	1
+#define PINB0	0
+
+#define DDRB	_SFR_IO8(0x04)
+#define DDB7	7
+#define DDB6	6
+#define DDB5	5
+#define DDB4	4
+#define DDB3	3
+#define DDB2	2
+#define DDB1	1
+#define DDB0	0
+
+#define PORTB	_SFR_IO8(0x05)
+#define PB7	7
+#define PB6	6
+#define PB5	5
+#define PB4	4
+#define PB3	3
+#define PB2	2
+#define PB1	1
+#define PB0	0
+
+#define PINC	_SFR_IO8(0x06)
+#define PINC7	7
+#define PINC6	6
+#define PINC5	5
+#define PINC4	4
+#define PINC3	3
+#define PINC2	2
+#define PINC1	1
+#define PINC0	0
+
+#define DDRC	_SFR_IO8(0x07)
+#define DDC7	7
+#define DDC6	6
+#define DDC5	5
+#define DDC4	4
+#define DDC3	3
+#define DDC2	2
+#define DDC1	1
+#define DDC0	0
+
+#define PORTC	_SFR_IO8(0x08)
+#define PC7	7
+#define PC6	6
+#define PC5	5
+#define PC4	4
+#define PC3	3
+#define PC2	2
+#define PC1	1
+#define PC0	0
+
+#define PIND	_SFR_IO8(0x09)
+#define PIND7	7
+#define PIND6	6
+#define PIND5	5
+#define PIND4	4
+#define PIND3	3
+#define PIND2	2
+#define PIND1	1
+#define PIND0	0
+
+#define DDRD	_SFR_IO8(0x0A)
+#define DDD7	7
+#define DDD6	6
+#define DDD5	5
+#define DDD4	4
+#define DDD3	3
+#define DDD2	2
+#define DDD1	1
+#define DDD0	0
+
+#define PORTD	_SFR_IO8(0x0B)
+#define PD7	7
+#define PD6	6
+#define PD5	5
+#define PD4	4
+#define PD3	3
+#define PD2	2
+#define PD1	1
+#define PD0	0
+
+/* Reserved [0x0C..0x14] */
+
+#define TIFR0	_SFR_IO8(0x15)
+#define OCF0B	2
+#define OCF0A	1
+#define TOV0	0
+
+#define TIFR1	_SFR_IO8(0x16)
+#define ICF1	5
+#define OCF1B	2
+#define OCF1A	1
+#define TOV1	0
+
+#define TIFR2	_SFR_IO8(0x17)
+#define OCF2B	2
+#define OCF2A	1
+#define TOV2	0
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR	_SFR_IO8(0x1B)
+#define PCIF3	3
+#define PCIF2	2
+#define PCIF1	1
+#define PCIF0	0
+
+#define EIFR   _SFR_IO8(0x1C)
+#define INTF2	2
+#define INTF1	1
+#define INTF0	0
+
+#define EIMSK	_SFR_IO8(0x1D)
+#define INT2	2
+#define INT1	1
+#define INT0	0
+
+#define GPIOR0	_SFR_IO8(0x1E)
+
+#define EECR   _SFR_IO8(0x1F)
+/* EECR - EEPROM Control Register */
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR   _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR   _SFR_IO16(0x21)
+#define EEARL  _SFR_IO8(0x21)
+#define EEARH  _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR	_SFR_IO8(0x23)
+#define TSM	7
+#define PSRASY	1
+#define PSRSYNC 0
+
+#define TCCR0A	_SFR_IO8(0x24)
+#define COM0A1	7
+#define COM0A0	6
+#define COM0B1	5
+#define COM0B0	4
+#define WGM01	1
+#define WGM00	0
+
+#define TCCR0B	_SFR_IO8(0x25)
+#define FOC0A	7
+#define FOC0B	6
+#define WGM02	3
+#define CS02	2
+#define CS01	1
+#define CS00	0
+
+#define TCNT0	_SFR_IO8(0X26)
+
+#define OCR0A	_SFR_IO8(0X27)
+
+#define OCR0B	_SFR_IO8(0X28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1	_SFR_IO8(0x2A)
+
+#define GPIOR2	_SFR_IO8(0x2B)
+
+#define SPCR	_SFR_IO8(0x2C)
+#define SPIE	7
+#define SPE	6
+#define DORD	5
+#define MSTR	4
+#define CPOL	3
+#define CPHA	2
+#define SPR1	1
+#define SPR0	0
+
+#define SPSR	_SFR_IO8(0x2D)
+#define SPIF	7
+#define WCOL	6
+#define SPI2X	0
+
+#define SPDR	_SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR	_SFR_IO8(0x30)
+#define ACD	7
+#define ACBG	6
+#define ACO	5
+#define ACI	4
+#define ACIE	3
+#define ACIC	2
+#define ACIS1	1
+#define ACIS0	0
+
+#define MONDR	_SFR_IO8(0x31)
+#define OCDR	_SFR_IO8(0x31)
+#define IDRD	7
+#define OCDR7	7
+#define OCDR6	6
+#define OCDR5	5
+#define OCDR4	4
+#define OCDR3	3
+#define OCDR2	2
+#define OCDR1	1
+#define OCDR0	0
+
+/* Reserved [0x32] */
+
+#define SMCR	_SFR_IO8(0x33)
+#define SM2	3
+#define SM1	2
+#define SM0	1
+#define SE	0
+
+#define MCUSR	_SFR_IO8(0x34)
+#define JTRF	4
+#define WDRF	3
+#define BORF	2
+#define EXTRF	1
+#define PORF	0
+
+#define MCUCR	_SFR_IO8(0X35)
+#define JTD	7
+#if !defined(__AVR_ATmega644__)
+#define BODS    6
+#define BODSE   5
+#endif
+#define PUD	4
+#define IVSEL	1
+#define IVCE	0
+
+/* Reserved [0x36] */
+
+#define SPMCSR	_SFR_IO8(0x37)
+#define SPMIE	7
+#define RWWSB	6
+#define SIGRD	5
+#define RWWSRE	4
+#define BLBSET	3
+#define PGWRT	2
+#define PGERS	1
+#define SPMEN	0
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR	_SFR_MEM8(0x60)
+#define WDIF	7
+#define WDIE	6
+#define WDP3	5
+#define WDCE	4
+#define WDE	3
+#define WDP2	2
+#define WDP1	1
+#define WDP0	0
+
+#define CLKPR	_SFR_MEM8(0x61)
+#define CLKPCE	7
+#define CLKPS3	3
+#define CLKPS2	2
+#define CLKPS1	1
+#define CLKPS0	0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR	_SFR_MEM8(0x64)  /* Datasheets: ATmega164P/324P/644P 8011D-AVR-02/07
+                                   and ATmega644 2593L-AVR-02/07.  */
+#define PRR0	_SFR_MEM8(0x64)  /* AVR Studio 4.13, build 524.  */
+#define PRTWI		7
+#define PRTIM2		6
+#define PRTIM0		5
+#if !defined(__AVR_ATmega644__)
+# define PRUSART1	4
+#endif
+#define PRTIM1		3
+#define PRSPI		2
+#define PRUSART0	1
+#define PRADC		0
+
+#if !defined(__AVR_ATmega644__)
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#else
+#define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#endif
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRUSART0
+#if !defined(__AVR_ATmega644__)
+#define __AVR_HAVE_PRR0_PRUSART1
+#endif
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL	_SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR	_SFR_MEM8(0x68)
+#define PCIE3	3
+#define PCIE2	2
+#define PCIE1	1
+#define PCIE0	0
+
+#define EICRA	_SFR_MEM8(0x69)
+#define ISC21	5
+#define ISC20	4
+#define ISC11	3
+#define ISC10	2
+#define ISC01	1
+#define ISC00	0
+
+/* Reserved [0x6A] */
+
+#define PCMSK0	_SFR_MEM8(0x6B)
+#define PCINT7	7
+#define PCINT6	6
+#define PCINT5	5
+#define PCINT4	4
+#define PCINT3	3
+#define PCINT2	2
+#define PCINT1	1
+#define PCINT0	0
+
+#define PCMSK1	_SFR_MEM8(0x6C)
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9	1
+#define PCINT8	0
+
+#define PCMSK2	_SFR_MEM8(0x6D)
+#define PCINT23 7
+#define PCINT22 6
+#define PCINT21 5
+#define PCINT20 4
+#define PCINT19 3
+#define PCINT18 2
+#define PCINT17 1
+#define PCINT16 0
+
+#define TIMSK0	_SFR_MEM8(0x6E)
+#define OCIE0B	2
+#define OCIE0A	1
+#define TOIE0	0
+
+#define TIMSK1	_SFR_MEM8(0x6F)
+#define ICIE1	5
+#define OCIE1B	2
+#define OCIE1A	1
+#define TOIE1	0
+
+#define TIMSK2	_SFR_MEM8(0x70)
+#define OCIE2B	2
+#define OCIE2A	1
+#define TOIE2	0
+
+/* Reserved [0x71..0x72] */
+
+#define PCMSK3	_SFR_MEM8(0x73)
+#define PCINT31 7
+#define PCINT30 6
+#define PCINT29 5
+#define PCINT28 4
+#define PCINT27 3
+#define PCINT26 2
+#define PCINT25 1
+#define PCINT24 0
+
+/* Reserved [0x74..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC	_SFR_MEM16(0x78)
+#endif
+#define ADCW	_SFR_MEM16(0x78)
+#define ADCL	_SFR_MEM8(0x78)
+#define ADCH	_SFR_MEM8(0x79)
+
+#define ADCSRA	_SFR_MEM8(0x7A)
+#define ADEN	7
+#define ADSC	6
+#define ADATE	5
+#define ADIF	4
+#define ADIE	3
+#define ADPS2	2
+#define ADPS1	1
+#define ADPS0	0
+
+#define ADCSRB	_SFR_MEM8(0x7B)
+#define ACME	6
+#define ADTS2	2
+#define ADTS1	1
+#define ADTS0	0
+
+#define ADMUX	_SFR_MEM8(0x7C)
+#define REFS1	7
+#define REFS0	6
+#define ADLAR	5
+#define MUX4	4
+#define MUX3	3
+#define MUX2	2
+#define MUX1	1
+#define MUX0	0
+
+/* Reserved [0x7D] */
+
+#define DIDR0	_SFR_MEM8(0x7E)
+#define ADC7D	7
+#define ADC6D	6
+#define ADC5D	5
+#define ADC4D	4
+#define ADC3D	3
+#define ADC2D	2
+#define ADC1D	1
+#define ADC0D	0
+
+#define DIDR1	_SFR_MEM8(0x7F)
+#define AIN1D	1
+#define AIN0D	0
+
+#define TCCR1A	_SFR_MEM8(0x80)
+#define COM1A1	7
+#define COM1A0	6
+#define COM1B1	5
+#define COM1B0	4
+#define WGM11	1
+#define WGM10	0
+
+#define TCCR1B	_SFR_MEM8(0x81)
+#define ICNC1	7
+#define ICES1	6
+#define WGM13	4
+#define WGM12	3
+#define CS12	2
+#define CS11	1
+#define CS10	0
+
+#define TCCR1C	_SFR_MEM8(0x82)
+#define FOC1A	7
+#define FOC1B	6
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1	_SFR_MEM16(0x84)
+
+#define TCNT1L	_SFR_MEM8(0x84)
+#define TCNT1H	_SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1	_SFR_MEM16(0x86)
+
+#define ICR1L	_SFR_MEM8(0x86)
+#define ICR1H	_SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A	_SFR_MEM16(0x88)
+
+#define OCR1AL	_SFR_MEM8(0x88)
+#define OCR1AH	_SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B	_SFR_MEM16(0x8A)
+
+#define OCR1BL	_SFR_MEM8(0x8A)
+#define OCR1BH	_SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A	_SFR_MEM8(0xB0)
+#define COM2A1	7
+#define COM2A0	6
+#define COM2B1	5
+#define COM2B0	4
+#define WGM21	1
+#define WGM20	0
+
+#define TCCR2B	_SFR_MEM8(0xB1)
+#define FOC2A	7
+#define FOC2B	6
+#define WGM22	3
+#define CS22	2
+#define CS21	1
+#define CS20	0
+
+#define TCNT2	_SFR_MEM8(0xB2)
+
+#define OCR2A	_SFR_MEM8(0xB3)
+
+#define OCR2B	_SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR	_SFR_MEM8(0xB6)
+#define EXCLK	6
+#define AS2	5
+#define TCN2UB	4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR	_SFR_MEM8(0xB8)
+
+#define TWSR	_SFR_MEM8(0xB9)
+#define TWS7	7
+#define TWS6	6
+#define TWS5	5
+#define TWS4	4
+#define TWS3	3
+#define TWPS1	1
+#define TWPS0	0
+
+#define TWAR	_SFR_MEM8(0xBA)
+#define TWA6	7
+#define TWA5	6
+#define TWA4	5
+#define TWA3	4
+#define TWA2	3
+#define TWA1	2
+#define TWA0	1
+#define TWGCE	0
+
+#define TWDR	_SFR_MEM8(0xBB)
+
+#define TWCR	_SFR_MEM8(0xBC)
+#define TWINT	7
+#define TWEA	6
+#define TWSTA	5
+#define TWSTO	4
+#define TWWC	3
+#define TWEN	2
+#define TWIE	0
+
+#define TWAMR	_SFR_MEM8(0xBD)
+#define TWAM6	7
+#define TWAM5	6
+#define TWAM4	5
+#define TWAM3	4
+#define TWAM2	3
+#define TWAM1	2
+#define TWAM0	1
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A	_SFR_MEM8(0xC0)
+#define RXC0	7
+#define TXC0	6
+#define UDRE0	5
+#define FE0	4
+#define DOR0	3
+#define UPE0	2
+#define U2X0	1
+#define MPCM0	0
+
+#define UCSR0B	_SFR_MEM8(0XC1)
+#define RXCIE0	7
+#define TXCIE0	6
+#define UDRIE0	5
+#define RXEN0	4
+#define TXEN0	3
+#define UCSZ02	2
+#define RXB80	1
+#define TXB80	0
+
+#define UCSR0C	_SFR_MEM8(0xC2)
+#define UMSEL01 7
+#define UMSEL00 6
+#define UPM01	5
+#define UPM00	4
+#define USBS0	3
+#define UCSZ01	2
+#define UCSZ00	1
+#define UCPHA0  1
+#define UCPOL0	0
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0	_SFR_MEM16(0xC4)
+
+#define UBRR0L	_SFR_MEM8(0xC4)
+#define UBRR0H	_SFR_MEM8(0xC5)
+
+#define UDR0	_SFR_MEM8(0XC6)
+
+#if !defined(__AVR_ATmega644__)
+/*
+ * Only ATmega164P/324P/644P have a second USART.
+ */
+/* Reserved [0xC7] */
+
+#define UCSR1A	_SFR_MEM8(0xC8)
+#define RXC1	7
+#define TXC1	6
+#define UDRE1	5
+#define FE1	4
+#define DOR1	3
+#define UPE1	2
+#define U2X1	1
+#define MPCM1	0
+
+#define UCSR1B	_SFR_MEM8(0XC9)
+#define RXCIE1	7
+#define TXCIE1	6
+#define UDRIE1	5
+#define RXEN1	4
+#define TXEN1	3
+#define UCSZ12	2
+#define RXB81	1
+#define TXB81	0
+
+#define UCSR1C	_SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11	5
+#define UPM10	4
+#define USBS1	3
+#define UCSZ11	2
+#define UCSZ10	1
+#define UCPHA1  1
+#define UCPOL1	0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1	_SFR_MEM16(0xCC)
+
+#define UBRR1L	_SFR_MEM8(0xCC)
+#define UBRR1H	_SFR_MEM8(0xCD)
+
+#define UDR1	_SFR_MEM8(0XCE)
+#endif /* !defined(__AVR_ATmega644) */
+
+/* Reserved [0xCF..0xFF] */
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect_num			1
+#define INT0_vect			    _VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num			2
+#define INT1_vect			    _VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num			3
+#define INT2_vect	    		_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num			4
+#define PCINT0_vect			    _VECTOR(4)
+#define SIG_PIN_CHANGE0			_VECTOR(4)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num			5
+#define PCINT1_vect		    	_VECTOR(5)
+#define SIG_PIN_CHANGE1			_VECTOR(5)
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect_num  		6
+#define PCINT2_vect				_VECTOR(6)
+#define SIG_PIN_CHANGE2			_VECTOR(6)
+
+/* Pin Change Interrupt Request 3 */
+#define PCINT3_vect_num			7
+#define PCINT3_vect			    _VECTOR(7)
+#define SIG_PIN_CHANGE3			_VECTOR(7)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num			8
+#define WDT_vect		    	_VECTOR(8)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(8)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	9
+#define TIMER2_COMPA_vect		_VECTOR(9)
+#define SIG_OUTPUT_COMPARE2A	_VECTOR(9)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	10
+#define TIMER2_COMPB_vect		_VECTOR(10)
+#define SIG_OUTPUT_COMPARE2B	_VECTOR(10)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		11
+#define TIMER2_OVF_vect			_VECTOR(11)
+#define SIG_OVERFLOW2			_VECTOR(11)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	12
+#define TIMER1_CAPT_vect		_VECTOR(12)
+#define SIG_INPUT_CAPTURE1		_VECTOR(12)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	13
+#define TIMER1_COMPA_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(13)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	14
+#define TIMER1_COMPB_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(14)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		15
+#define TIMER1_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW1			_VECTOR(15)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	16
+#define TIMER0_COMPA_vect		_VECTOR(16)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(16)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	17
+#define TIMER0_COMPB_vect		_VECTOR(17)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(17)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		18
+#define TIMER0_OVF_vect			_VECTOR(18)
+#define SIG_OVERFLOW0			_VECTOR(18)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		19
+#define SPI_STC_vect			_VECTOR(19)
+#define SIG_SPI				    _VECTOR(19)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		20
+#define USART0_RX_vect			_VECTOR(20)
+#define SIG_USART_RECV			_VECTOR(20)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	21
+#define USART0_UDRE_vect		_VECTOR(21)
+#define SIG_USART_DATA			_VECTOR(21)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		22
+#define USART0_TX_vect			_VECTOR(22)
+#define SIG_USART_TRANS			_VECTOR(22)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	23
+#define ANALOG_COMP_vect		_VECTOR(23)
+#define SIG_COMPARATOR			_VECTOR(23)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			24
+#define ADC_vect	    		_VECTOR(24)
+#define SIG_ADC			    	_VECTOR(24)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		25
+#define EE_READY_vect			_VECTOR(25)
+#define SIG_EEPROM_READY		_VECTOR(25)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num			26
+#define TWI_vect	    		_VECTOR(26)
+#define SIG_2WIRE_SERIAL		_VECTOR(26)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		27
+#define SPM_READY_vect			_VECTOR(27)
+#define SIG_SPM_READY			_VECTOR(27)
+
+#if defined(__AVR_ATmega644__)
+
+# define _VECTORS_SIZE 112
+
+#else /* !defined(__AVR_ATmega644__) */
+
+/* USART1, Rx Complete */
+/* USART1 RX complete */
+#define USART1_RX_vect_num		28
+#define USART1_RX_vect			_VECTOR(28)
+#define SIG_USART1_RECV			_VECTOR(28)
+
+/* USART1 Data register Empty */
+/* USART1 Data Register Empty */
+#define USART1_UDRE_vect_num	29
+#define USART1_UDRE_vect		_VECTOR(29)
+#define SIG_USART1_DATA			_VECTOR(29)
+
+/* USART1, Tx Complete */
+/* USART1 TX complete */
+#define USART1_TX_vect_num		30
+#define USART1_TX_vect			_VECTOR(30)
+#define SIG_USART1_TRANS		_VECTOR(30)
+
+# define _VECTORS_SIZE 124
+
+#endif /* defined(__AVR_ATmega644__) */
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_INTERRUPT2
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_PIN_CHANGE3
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART_RECV
+#pragma GCC poison SIG_USART_DATA
+#pragma GCC poison SIG_USART_TRANS
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+#pragma GCC poison SIG_USART1_RECV
+#pragma GCC poison SIG_USART1_DATA
+#pragma GCC poison SIG_USART1_TRANS
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
+
 
 /* Constants */
 #define SPM_PAGESIZE 256
@@ -91,7 +995,6 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x09
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -99,5 +1002,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_IOM644_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom644a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom644a.h
@@ -1,1066 +1,34 @@
-/*****************************************************************************
- *
- * Copyright (C) 2015 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-/* $Id$ */
-
-#ifndef _AVR_ATMEGA644A_H_INCLUDED
-#define _AVR_ATMEGA644A_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom644a.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PORTA7  7
-#define PORTA6  6
-#define PORTA5  5
-#define PORTA4  4
-#define PORTA3  3
-#define PORTA2  2
-#define PORTA1  1
-#define PORTA0  0
-// retain PAn macros for backward compatibility
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-// retain PBn macros for backward compatibility
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PORTC7  7
-#define PORTC6  6
-#define PORTC5  5
-#define PORTC4  4
-#define PORTC3  3
-#define PORTC2  2
-#define PORTC1  1
-#define PORTC0  0
-// retain PCn macros for backward compatibility
-#define PC7	7
-#define PC6	6
-#define PC5	5
-#define PC4	4
-#define PC3	3
-#define PC2	2
-#define PC1	1
-#define PC0	0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PORTD7  7
-#define PORTD6  6
-#define PORTD5  5
-#define PORTD4  4
-#define PORTD3  3
-#define PORTD2  2
-#define PORTD1  1
-#define PORTD0  0
-// retain PDn macros for backward compatibility
-#define PD7	7
-#define PD6	6
-#define PD5	5
-#define PD4	4
-#define PD3	3
-#define PD2	2
-#define PD1	1
-#define PD0	0
-
-/* Reserved [0x0C..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-#define OCF0B   2
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-#define OCF2B   2
-
-/* Reserved [0x18..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-#define PCIF1   1
-#define PCIF2   2
-#define PCIF3   3
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-#define INTF2   2
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define INT1    1
-#define INT2    2
-
-#define GPIOR0  _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-#define GTCCR   _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM     7
-#define PSRASY  1
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0
-#define WGM01   1
-#define COM0B0  4
-#define COM0B1  5
-#define COM0A0  6
-#define COM0A1  7
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM02   3
-#define FOC0B   6
-#define FOC0A   7
-
-#define TCNT0   _SFR_IO8(0x26)
-
-#define OCR0A   _SFR_IO8(0x27)
-
-#define OCR0B   _SFR_IO8(0x28)
-
-/* Reserved [0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2  _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define MONDR	_SFR_IO8(0x31)
-#define OCDR    _SFR_IO8(0x31)
-#define IDRD	7
-#define OCDR7   7
-#define OCDR6   6
-#define OCDR5   5
-#define OCDR4   4
-#define OCDR3   3
-#define OCDR2   2
-#define OCDR1   1
-#define OCDR0   0
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define JTRF    4
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define JTD     7
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define SIGRD   5
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDE     3
-#define WDCE    4
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-#define PRR     _SFR_MEM8(0x64) /* for backward compatibility */
-#define PRR0    _SFR_MEM8(0x64)
-#define PRADC   0
-#define PRSPI   2
-#define PRTIM1  3
-#define PRUSART0 1
-#define PRUSART1 4
-#define PRTIM0  5
-#define PRTIM2  6
-#define PRTWI   7
-
-#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
-#define __AVR_HAVE_PRR0_PRADC
-#define __AVR_HAVE_PRR0_PRSPI
-#define __AVR_HAVE_PRR0_PRTIM1
-#define __AVR_HAVE_PRR0_PRUSART0
-#define __AVR_HAVE_PRR0_PRUSART1
-#define __AVR_HAVE_PRR0_PRTIM0
-#define __AVR_HAVE_PRR0_PRTIM2
-#define __AVR_HAVE_PRR0_PRTWI
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-#define OSCCAL0 0
-#define OSCCAL1 1
-#define OSCCAL2 2
-#define OSCCAL3 3
-#define OSCCAL4 4
-#define OSCCAL5 5
-#define OSCCAL6 6
-#define OSCCAL7 7
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-#define PCIE1   1
-#define PCIE2   2
-#define PCIE3   3
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-#define ISC20   4
-#define ISC21   5
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2  _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-#define OCIE0B  2
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-#define OCIE2B  2
-
-/* Reserved [0x71..0x72] */
-
-#define PCMSK3  _SFR_MEM8(0x73)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-#define PCINT28 4
-#define PCINT29 5
-#define PCINT30 6
-#define PCINT31 7
-
-/* Reserved [0x74..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ACME    6
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define WGM20   0
-#define WGM21   1
-#define COM2B0  4
-#define COM2B1  5
-#define COM2A0  6
-#define COM2A1  7
-
-#define TCCR2B  _SFR_MEM8(0xB1)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM22   3
-#define FOC2B   6
-#define FOC2A   7
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-#define OCR2B   _SFR_MEM8(0xB4)
-
-/* Reserved [0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB  4
-#define AS2     5
-#define EXCLK   6
-
-/* Reserved [0xB7] */
-
-#define TWBR    _SFR_MEM8(0xB8)
-
-#define TWSR    _SFR_MEM8(0xB9)
-#define TWPS0   0
-#define TWPS1   1
-#define TWS3    3
-#define TWS4    4
-#define TWS5    5
-#define TWS6    6
-#define TWS7    7
-
-#define TWAR    _SFR_MEM8(0xBA)
-#define TWGCE   0
-#define TWA0    1
-#define TWA1    2
-#define TWA2    3
-#define TWA3    4
-#define TWA4    5
-#define TWA5    6
-#define TWA6    7
-
-#define TWDR    _SFR_MEM8(0xBB)
-
-#define TWCR    _SFR_MEM8(0xBC)
-#define TWIE    0
-#define TWEN    2
-#define TWWC    3
-#define TWSTO   4
-#define TWSTA   5
-#define TWEA    6
-#define TWINT   7
-
-#define TWAMR   _SFR_MEM8(0xBD)
-#define TWAM0   1
-#define TWAM1   2
-#define TWAM2   3
-#define TWAM3   4
-#define TWAM4   5
-#define TWAM5   6
-#define TWAM6   7
-
-/* Reserved [0xBE..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0xC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL00 6
-#define UMSEL01 7
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0xC6)
-
-/* Reserved [0xC7] */
-
-#define UCSR1A  _SFR_MEM8(0xC8)
-#define MPCM1   0
-#define U2X1    1
-#define UPE1    2
-#define DOR1    3
-#define FE1     4
-#define UDRE1   5
-#define TXC1    6
-#define RXC1    7
-
-#define UCSR1B  _SFR_MEM8(0xC9)
-#define TXB81   0
-#define RXB81   1
-#define UCSZ12  2
-#define TXEN1   3
-#define RXEN1   4
-#define UDRIE1  5
-#define TXCIE1  6
-#define RXCIE1  7
-
-#define UCSR1C  _SFR_MEM8(0xCA)
-#define UCPOL1  0
-#define UCSZ10  1
-#define UCSZ11  2
-#define USBS1   3
-#define UPM10   4
-#define UPM11   5
-#define UMSEL10 6
-#define UMSEL11 7
-
-/* Reserved [0xCB] */
-
-/* Combine UBRR1L and UBRR1H */
-#define UBRR1   _SFR_MEM16(0xCC)
-
-#define UBRR1L  _SFR_MEM8(0xCC)
-#define UBRR1H  _SFR_MEM8(0xCD)
-
-#define UDR1    _SFR_MEM8(0xCE)
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect            _VECTOR(3)
-#define INT2_vect_num        3
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(4)
-#define PCINT0_vect_num        4
-#define SIG_PIN_CHANGE0			_VECTOR(4)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect            _VECTOR(5)
-#define PCINT1_vect_num        5
-#define SIG_PIN_CHANGE1			_VECTOR(5)
-
-/* Pin Change Interrupt Request 2 */
-#define PCINT2_vect            _VECTOR(6)
-#define PCINT2_vect_num        6
-#define SIG_PIN_CHANGE2			_VECTOR(6)
-
-/* Pin Change Interrupt Request 3 */
-#define PCINT3_vect            _VECTOR(7)
-#define PCINT3_vect_num        7
-#define SIG_PIN_CHANGE3			_VECTOR(7)
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect            _VECTOR(8)
-#define WDT_vect_num        8
-#define SIG_WATCHDOG_TIMEOUT	_VECTOR(8)
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect            _VECTOR(9)
-#define TIMER2_COMPA_vect_num        9
-#define SIG_OUTPUT_COMPARE2A	_VECTOR(9)
-
-/* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect            _VECTOR(10)
-#define TIMER2_COMPB_vect_num        10
-#define SIG_OUTPUT_COMPARE2B	_VECTOR(10)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect            _VECTOR(11)
-#define TIMER2_OVF_vect_num        11
-#define SIG_OVERFLOW2			_VECTOR(11)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(12)
-#define TIMER1_CAPT_vect_num        12
-#define SIG_INPUT_CAPTURE1		_VECTOR(12)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect            _VECTOR(13)
-#define TIMER1_COMPA_vect_num        13
-#define SIG_OUTPUT_COMPARE1A	_VECTOR(13)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect            _VECTOR(14)
-#define TIMER1_COMPB_vect_num        14
-#define SIG_OUTPUT_COMPARE1B	_VECTOR(14)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(15)
-#define TIMER1_OVF_vect_num        15
-#define SIG_OVERFLOW1			_VECTOR(15)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect            _VECTOR(16)
-#define TIMER0_COMPA_vect_num        16
-#define SIG_OUTPUT_COMPARE0A	_VECTOR(16)
-
-/* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect            _VECTOR(17)
-#define TIMER0_COMPB_vect_num        17
-#define SIG_OUTPUT_COMPARE0B	_VECTOR(17)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(18)
-#define TIMER0_OVF_vect_num        18
-#define SIG_OVERFLOW0			_VECTOR(18)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect            _VECTOR(19)
-#define SPI_STC_vect_num        19
-#define SIG_SPI				    _VECTOR(19)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect            _VECTOR(20)
-#define USART0_RX_vect_num        20
-#define SIG_USART_RECV			_VECTOR(20)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect            _VECTOR(21)
-#define USART0_UDRE_vect_num        21
-#define SIG_USART_DATA			_VECTOR(21)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect            _VECTOR(22)
-#define USART0_TX_vect_num        22
-#define SIG_USART_TRANS			_VECTOR(22)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect            _VECTOR(23)
-#define ANALOG_COMP_vect_num        23
-#define SIG_COMPARATOR			_VECTOR(23)
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(24)
-#define ADC_vect_num        24
-#define SIG_ADC			    	_VECTOR(24)
-
-/* EEPROM Ready */
-#define EE_READY_vect            _VECTOR(25)
-#define EE_READY_vect_num        25
-#define SIG_EEPROM_READY		_VECTOR(25)
-
-/* 2-wire Serial Interface */
-#define TWI_vect            _VECTOR(26)
-#define TWI_vect_num        26
-#define SIG_2WIRE_SERIAL		_VECTOR(26)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect            _VECTOR(27)
-#define SPM_READY_vect_num        27
-#define SIG_SPM_READY			_VECTOR(27)
-
-/* USART1 RX complete */
-#define USART1_RX_vect            _VECTOR(28)
-#define USART1_RX_vect_num        28
-
-/* USART1 Data Register Empty */
-#define USART1_UDRE_vect            _VECTOR(29)
-#define USART1_UDRE_vect_num        29
-
-/* USART1 TX complete */
-#define USART1_TX_vect            _VECTOR(30)
-#define USART1_TX_vect_num        30
-#define SIG_USART1_TRANS		_VECTOR(30)
-
-#define _VECTORS_SIZE 124
-
-/* Deprecated items */
-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
-
-#pragma GCC system_header
-
-#pragma GCC poison SIG_INTERRUPT0
-#pragma GCC poison SIG_INTERRUPT1
-#pragma GCC poison SIG_INTERRUPT2
-#pragma GCC poison SIG_PIN_CHANGE0
-#pragma GCC poison SIG_PIN_CHANGE1
-#pragma GCC poison SIG_PIN_CHANGE2
-#pragma GCC poison SIG_PIN_CHANGE3
-#pragma GCC poison SIG_WATCHDOG_TIMEOUT
-#pragma GCC poison SIG_OUTPUT_COMPARE2A
-#pragma GCC poison SIG_OUTPUT_COMPARE2B
-#pragma GCC poison SIG_OVERFLOW2
-#pragma GCC poison SIG_INPUT_CAPTURE1
-#pragma GCC poison SIG_OUTPUT_COMPARE1A
-#pragma GCC poison SIG_OUTPUT_COMPARE1B
-#pragma GCC poison SIG_OVERFLOW1
-#pragma GCC poison SIG_OUTPUT_COMPARE0A
-#pragma GCC poison SIG_OUTPUT_COMPARE0B
-#pragma GCC poison SIG_OVERFLOW0
-#pragma GCC poison SIG_SPI
-#pragma GCC poison SIG_USART_RECV
-#pragma GCC poison SIG_USART_DATA
-#pragma GCC poison SIG_USART_TRANS
-#pragma GCC poison SIG_COMPARATOR
-#pragma GCC poison SIG_ADC
-#pragma GCC poison SIG_EEPROM_READY
-#pragma GCC poison SIG_2WIRE_SERIAL
-#pragma GCC poison SIG_SPM_READY
-#pragma GCC poison SIG_USART1_RECV
-#pragma GCC poison SIG_USART1_DATA
-#pragma GCC poison SIG_USART1_TRANS
-
-#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
-
-/* Constants */
-
-#define SPM_PAGESIZE 256
-#define FLASHSTART   0x0000
-#define FLASHEND     0xFFFF
-#define RAMSTART     0x0100
-#define RAMSIZE      4096
-#define RAMEND       0x10FF
-#define E2START     0
-#define E2SIZE      2048
-#define E2PAGESIZE  8
-#define E2END       0x07FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
-#define FUSE_CKSEL0      (unsigned char)~_BV(0) /* for backward compatibility */
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT    (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x09
-
-
-#endif /* #ifdef _AVR_ATMEGA644A_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom644.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom644p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom644p.h
@@ -30,12 +30,916 @@
 
 /* avr/iom644p.h - definitions for ATmega644P */
 
-/* $Id$ */
+/* $Id: iom644p.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 #ifndef _AVR_IOM644P_H_
 #define _AVR_IOM644P_H_ 1
 
-#include <avr/iomxx4.h>
+
+/* Registers and associated bit numbers */
+
+#define PINA	_SFR_IO8(0X00)
+#define PINA7	7
+#define PINA6	6
+#define PINA5	5
+#define PINA4	4
+#define PINA3	3
+#define PINA2	2
+#define PINA1	1
+#define PINA0	0
+
+#define DDRA	_SFR_IO8(0X01)
+#define DDA7	7
+#define DDA6	6
+#define DDA5	5
+#define DDA4	4
+#define DDA3	3
+#define DDA2	2
+#define DDA1	1
+#define DDA0	0
+
+#define PORTA	_SFR_IO8(0X02)
+#define PA7	7
+#define PA6	6
+#define PA5	5
+#define PA4	4
+#define PA3	3
+#define PA2	2
+#define PA1	1
+#define PA0	0
+
+#define PINB	_SFR_IO8(0X03)
+#define PINB7	7
+#define PINB6	6
+#define PINB5	5
+#define PINB4	4
+#define PINB3	3
+#define PINB2	2
+#define PINB1	1
+#define PINB0	0
+
+#define DDRB	_SFR_IO8(0x04)
+#define DDB7	7
+#define DDB6	6
+#define DDB5	5
+#define DDB4	4
+#define DDB3	3
+#define DDB2	2
+#define DDB1	1
+#define DDB0	0
+
+#define PORTB	_SFR_IO8(0x05)
+#define PB7	7
+#define PB6	6
+#define PB5	5
+#define PB4	4
+#define PB3	3
+#define PB2	2
+#define PB1	1
+#define PB0	0
+
+#define PINC	_SFR_IO8(0x06)
+#define PINC7	7
+#define PINC6	6
+#define PINC5	5
+#define PINC4	4
+#define PINC3	3
+#define PINC2	2
+#define PINC1	1
+#define PINC0	0
+
+#define DDRC	_SFR_IO8(0x07)
+#define DDC7	7
+#define DDC6	6
+#define DDC5	5
+#define DDC4	4
+#define DDC3	3
+#define DDC2	2
+#define DDC1	1
+#define DDC0	0
+
+#define PORTC	_SFR_IO8(0x08)
+#define PC7	7
+#define PC6	6
+#define PC5	5
+#define PC4	4
+#define PC3	3
+#define PC2	2
+#define PC1	1
+#define PC0	0
+
+#define PIND	_SFR_IO8(0x09)
+#define PIND7	7
+#define PIND6	6
+#define PIND5	5
+#define PIND4	4
+#define PIND3	3
+#define PIND2	2
+#define PIND1	1
+#define PIND0	0
+
+#define DDRD	_SFR_IO8(0x0A)
+#define DDD7	7
+#define DDD6	6
+#define DDD5	5
+#define DDD4	4
+#define DDD3	3
+#define DDD2	2
+#define DDD1	1
+#define DDD0	0
+
+#define PORTD	_SFR_IO8(0x0B)
+#define PD7	7
+#define PD6	6
+#define PD5	5
+#define PD4	4
+#define PD3	3
+#define PD2	2
+#define PD1	1
+#define PD0	0
+
+/* Reserved [0x0C..0x14] */
+
+#define TIFR0	_SFR_IO8(0x15)
+#define OCF0B	2
+#define OCF0A	1
+#define TOV0	0
+
+#define TIFR1	_SFR_IO8(0x16)
+#define ICF1	5
+#define OCF1B	2
+#define OCF1A	1
+#define TOV1	0
+
+#define TIFR2	_SFR_IO8(0x17)
+#define OCF2B	2
+#define OCF2A	1
+#define TOV2	0
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR	_SFR_IO8(0x1B)
+#define PCIF3	3
+#define PCIF2	2
+#define PCIF1	1
+#define PCIF0	0
+
+#define EIFR   _SFR_IO8(0x1C)
+#define INTF2	2
+#define INTF1	1
+#define INTF0	0
+
+#define EIMSK	_SFR_IO8(0x1D)
+#define INT2	2
+#define INT1	1
+#define INT0	0
+
+#define GPIOR0	_SFR_IO8(0x1E)
+
+#define EECR   _SFR_IO8(0x1F)
+/* EECR - EEPROM Control Register */
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR   _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR   _SFR_IO16(0x21)
+#define EEARL  _SFR_IO8(0x21)
+#define EEARH  _SFR_IO8(0X22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR	_SFR_IO8(0x23)
+#define TSM	7
+#define PSRASY	1
+#define PSRSYNC 0
+
+#define TCCR0A	_SFR_IO8(0x24)
+#define COM0A1	7
+#define COM0A0	6
+#define COM0B1	5
+#define COM0B0	4
+#define WGM01	1
+#define WGM00	0
+
+#define TCCR0B	_SFR_IO8(0x25)
+#define FOC0A	7
+#define FOC0B	6
+#define WGM02	3
+#define CS02	2
+#define CS01	1
+#define CS00	0
+
+#define TCNT0	_SFR_IO8(0X26)
+
+#define OCR0A	_SFR_IO8(0X27)
+
+#define OCR0B	_SFR_IO8(0X28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1	_SFR_IO8(0x2A)
+
+#define GPIOR2	_SFR_IO8(0x2B)
+
+#define SPCR	_SFR_IO8(0x2C)
+#define SPIE	7
+#define SPE	6
+#define DORD	5
+#define MSTR	4
+#define CPOL	3
+#define CPHA	2
+#define SPR1	1
+#define SPR0	0
+
+#define SPSR	_SFR_IO8(0x2D)
+#define SPIF	7
+#define WCOL	6
+#define SPI2X	0
+
+#define SPDR	_SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR	_SFR_IO8(0x30)
+#define ACD	7
+#define ACBG	6
+#define ACO	5
+#define ACI	4
+#define ACIE	3
+#define ACIC	2
+#define ACIS1	1
+#define ACIS0	0
+
+#define MONDR	_SFR_IO8(0x31)
+#define OCDR	_SFR_IO8(0x31)
+#define IDRD	7
+#define OCDR7	7
+#define OCDR6	6
+#define OCDR5	5
+#define OCDR4	4
+#define OCDR3	3
+#define OCDR2	2
+#define OCDR1	1
+#define OCDR0	0
+
+/* Reserved [0x32] */
+
+#define SMCR	_SFR_IO8(0x33)
+#define SM2	3
+#define SM1	2
+#define SM0	1
+#define SE	0
+
+#define MCUSR	_SFR_IO8(0x34)
+#define JTRF	4
+#define WDRF	3
+#define BORF	2
+#define EXTRF	1
+#define PORF	0
+
+#define MCUCR	_SFR_IO8(0X35)
+#define JTD	7
+#if !defined(__AVR_ATmega644__)
+#define BODS    6
+#define BODSE   5
+#endif
+#define PUD	4
+#define IVSEL	1
+#define IVCE	0
+
+/* Reserved [0x36] */
+
+#define SPMCSR	_SFR_IO8(0x37)
+#define SPMIE	7
+#define RWWSB	6
+#define SIGRD	5
+#define RWWSRE	4
+#define BLBSET	3
+#define PGWRT	2
+#define PGERS	1
+#define SPMEN	0
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR	_SFR_MEM8(0x60)
+#define WDIF	7
+#define WDIE	6
+#define WDP3	5
+#define WDCE	4
+#define WDE	3
+#define WDP2	2
+#define WDP1	1
+#define WDP0	0
+
+#define CLKPR	_SFR_MEM8(0x61)
+#define CLKPCE	7
+#define CLKPS3	3
+#define CLKPS2	2
+#define CLKPS1	1
+#define CLKPS0	0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR	_SFR_MEM8(0x64)  /* Datasheets: ATmega164P/324P/644P 8011D-AVR-02/07
+                                   and ATmega644 2593L-AVR-02/07.  */
+#define PRR0	_SFR_MEM8(0x64)  /* AVR Studio 4.13, build 524.  */
+#define PRTWI		7
+#define PRTIM2		6
+#define PRTIM0		5
+#if !defined(__AVR_ATmega644__)
+# define PRUSART1	4
+#endif
+#define PRTIM1		3
+#define PRSPI		2
+#define PRUSART0	1
+#define PRADC		0
+
+#if !defined(__AVR_ATmega644__)
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#else
+#define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#endif
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRUSART0
+#if !defined(__AVR_ATmega644__)
+#define __AVR_HAVE_PRR0_PRUSART1
+#endif
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL	_SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR	_SFR_MEM8(0x68)
+#define PCIE3	3
+#define PCIE2	2
+#define PCIE1	1
+#define PCIE0	0
+
+#define EICRA	_SFR_MEM8(0x69)
+#define ISC21	5
+#define ISC20	4
+#define ISC11	3
+#define ISC10	2
+#define ISC01	1
+#define ISC00	0
+
+/* Reserved [0x6A] */
+
+#define PCMSK0	_SFR_MEM8(0x6B)
+#define PCINT7	7
+#define PCINT6	6
+#define PCINT5	5
+#define PCINT4	4
+#define PCINT3	3
+#define PCINT2	2
+#define PCINT1	1
+#define PCINT0	0
+
+#define PCMSK1	_SFR_MEM8(0x6C)
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9	1
+#define PCINT8	0
+
+#define PCMSK2	_SFR_MEM8(0x6D)
+#define PCINT23 7
+#define PCINT22 6
+#define PCINT21 5
+#define PCINT20 4
+#define PCINT19 3
+#define PCINT18 2
+#define PCINT17 1
+#define PCINT16 0
+
+#define TIMSK0	_SFR_MEM8(0x6E)
+#define OCIE0B	2
+#define OCIE0A	1
+#define TOIE0	0
+
+#define TIMSK1	_SFR_MEM8(0x6F)
+#define ICIE1	5
+#define OCIE1B	2
+#define OCIE1A	1
+#define TOIE1	0
+
+#define TIMSK2	_SFR_MEM8(0x70)
+#define OCIE2B	2
+#define OCIE2A	1
+#define TOIE2	0
+
+/* Reserved [0x71..0x72] */
+
+#define PCMSK3	_SFR_MEM8(0x73)
+#define PCINT31 7
+#define PCINT30 6
+#define PCINT29 5
+#define PCINT28 4
+#define PCINT27 3
+#define PCINT26 2
+#define PCINT25 1
+#define PCINT24 0
+
+/* Reserved [0x74..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC	_SFR_MEM16(0x78)
+#endif
+#define ADCW	_SFR_MEM16(0x78)
+#define ADCL	_SFR_MEM8(0x78)
+#define ADCH	_SFR_MEM8(0x79)
+
+#define ADCSRA	_SFR_MEM8(0x7A)
+#define ADEN	7
+#define ADSC	6
+#define ADATE	5
+#define ADIF	4
+#define ADIE	3
+#define ADPS2	2
+#define ADPS1	1
+#define ADPS0	0
+
+#define ADCSRB	_SFR_MEM8(0x7B)
+#define ACME	6
+#define ADTS2	2
+#define ADTS1	1
+#define ADTS0	0
+
+#define ADMUX	_SFR_MEM8(0x7C)
+#define REFS1	7
+#define REFS0	6
+#define ADLAR	5
+#define MUX4	4
+#define MUX3	3
+#define MUX2	2
+#define MUX1	1
+#define MUX0	0
+
+/* Reserved [0x7D] */
+
+#define DIDR0	_SFR_MEM8(0x7E)
+#define ADC7D	7
+#define ADC6D	6
+#define ADC5D	5
+#define ADC4D	4
+#define ADC3D	3
+#define ADC2D	2
+#define ADC1D	1
+#define ADC0D	0
+
+#define DIDR1	_SFR_MEM8(0x7F)
+#define AIN1D	1
+#define AIN0D	0
+
+#define TCCR1A	_SFR_MEM8(0x80)
+#define COM1A1	7
+#define COM1A0	6
+#define COM1B1	5
+#define COM1B0	4
+#define WGM11	1
+#define WGM10	0
+
+#define TCCR1B	_SFR_MEM8(0x81)
+#define ICNC1	7
+#define ICES1	6
+#define WGM13	4
+#define WGM12	3
+#define CS12	2
+#define CS11	1
+#define CS10	0
+
+#define TCCR1C	_SFR_MEM8(0x82)
+#define FOC1A	7
+#define FOC1B	6
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1	_SFR_MEM16(0x84)
+
+#define TCNT1L	_SFR_MEM8(0x84)
+#define TCNT1H	_SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1	_SFR_MEM16(0x86)
+
+#define ICR1L	_SFR_MEM8(0x86)
+#define ICR1H	_SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A	_SFR_MEM16(0x88)
+
+#define OCR1AL	_SFR_MEM8(0x88)
+#define OCR1AH	_SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B	_SFR_MEM16(0x8A)
+
+#define OCR1BL	_SFR_MEM8(0x8A)
+#define OCR1BH	_SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A	_SFR_MEM8(0xB0)
+#define COM2A1	7
+#define COM2A0	6
+#define COM2B1	5
+#define COM2B0	4
+#define WGM21	1
+#define WGM20	0
+
+#define TCCR2B	_SFR_MEM8(0xB1)
+#define FOC2A	7
+#define FOC2B	6
+#define WGM22	3
+#define CS22	2
+#define CS21	1
+#define CS20	0
+
+#define TCNT2	_SFR_MEM8(0xB2)
+
+#define OCR2A	_SFR_MEM8(0xB3)
+
+#define OCR2B	_SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR	_SFR_MEM8(0xB6)
+#define EXCLK	6
+#define AS2	5
+#define TCN2UB	4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR	_SFR_MEM8(0xB8)
+
+#define TWSR	_SFR_MEM8(0xB9)
+#define TWS7	7
+#define TWS6	6
+#define TWS5	5
+#define TWS4	4
+#define TWS3	3
+#define TWPS1	1
+#define TWPS0	0
+
+#define TWAR	_SFR_MEM8(0xBA)
+#define TWA6	7
+#define TWA5	6
+#define TWA4	5
+#define TWA3	4
+#define TWA2	3
+#define TWA1	2
+#define TWA0	1
+#define TWGCE	0
+
+#define TWDR	_SFR_MEM8(0xBB)
+
+#define TWCR	_SFR_MEM8(0xBC)
+#define TWINT	7
+#define TWEA	6
+#define TWSTA	5
+#define TWSTO	4
+#define TWWC	3
+#define TWEN	2
+#define TWIE	0
+
+#define TWAMR	_SFR_MEM8(0xBD)
+#define TWAM6	7
+#define TWAM5	6
+#define TWAM4	5
+#define TWAM3	4
+#define TWAM2	3
+#define TWAM1	2
+#define TWAM0	1
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A	_SFR_MEM8(0xC0)
+#define RXC0	7
+#define TXC0	6
+#define UDRE0	5
+#define FE0	4
+#define DOR0	3
+#define UPE0	2
+#define U2X0	1
+#define MPCM0	0
+
+#define UCSR0B	_SFR_MEM8(0XC1)
+#define RXCIE0	7
+#define TXCIE0	6
+#define UDRIE0	5
+#define RXEN0	4
+#define TXEN0	3
+#define UCSZ02	2
+#define RXB80	1
+#define TXB80	0
+
+#define UCSR0C	_SFR_MEM8(0xC2)
+#define UMSEL01 7
+#define UMSEL00 6
+#define UPM01	5
+#define UPM00	4
+#define USBS0	3
+#define UCSZ01	2
+#define UCSZ00	1
+#define UCPHA0  1
+#define UCPOL0	0
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0	_SFR_MEM16(0xC4)
+
+#define UBRR0L	_SFR_MEM8(0xC4)
+#define UBRR0H	_SFR_MEM8(0xC5)
+
+#define UDR0	_SFR_MEM8(0XC6)
+
+#if !defined(__AVR_ATmega644__)
+/*
+ * Only ATmega164P/324P/644P have a second USART.
+ */
+/* Reserved [0xC7] */
+
+#define UCSR1A	_SFR_MEM8(0xC8)
+#define RXC1	7
+#define TXC1	6
+#define UDRE1	5
+#define FE1	4
+#define DOR1	3
+#define UPE1	2
+#define U2X1	1
+#define MPCM1	0
+
+#define UCSR1B	_SFR_MEM8(0XC9)
+#define RXCIE1	7
+#define TXCIE1	6
+#define UDRIE1	5
+#define RXEN1	4
+#define TXEN1	3
+#define UCSZ12	2
+#define RXB81	1
+#define TXB81	0
+
+#define UCSR1C	_SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11	5
+#define UPM10	4
+#define USBS1	3
+#define UCSZ11	2
+#define UCSZ10	1
+#define UCPHA1  1
+#define UCPOL1	0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1	_SFR_MEM16(0xCC)
+
+#define UBRR1L	_SFR_MEM8(0xCC)
+#define UBRR1H	_SFR_MEM8(0xCD)
+
+#define UDR1	_SFR_MEM8(0XCE)
+#endif /* !defined(__AVR_ATmega644) */
+
+/* Reserved [0xCF..0xFF] */
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect_num			1
+#define INT0_vect			    _VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num			2
+#define INT1_vect			    _VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num			3
+#define INT2_vect	    		_VECTOR(3)
+#define SIG_INTERRUPT2			_VECTOR(3)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num			4
+#define PCINT0_vect			    _VECTOR(4)
+#define SIG_PIN_CHANGE0			_VECTOR(4)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num			5
+#define PCINT1_vect		    	_VECTOR(5)
+#define SIG_PIN_CHANGE1			_VECTOR(5)
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect_num  		6
+#define PCINT2_vect				_VECTOR(6)
+#define SIG_PIN_CHANGE2			_VECTOR(6)
+
+/* Pin Change Interrupt Request 3 */
+#define PCINT3_vect_num			7
+#define PCINT3_vect			    _VECTOR(7)
+#define SIG_PIN_CHANGE3			_VECTOR(7)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num			8
+#define WDT_vect		    	_VECTOR(8)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(8)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	9
+#define TIMER2_COMPA_vect		_VECTOR(9)
+#define SIG_OUTPUT_COMPARE2A	_VECTOR(9)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	10
+#define TIMER2_COMPB_vect		_VECTOR(10)
+#define SIG_OUTPUT_COMPARE2B	_VECTOR(10)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		11
+#define TIMER2_OVF_vect			_VECTOR(11)
+#define SIG_OVERFLOW2			_VECTOR(11)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	12
+#define TIMER1_CAPT_vect		_VECTOR(12)
+#define SIG_INPUT_CAPTURE1		_VECTOR(12)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	13
+#define TIMER1_COMPA_vect		_VECTOR(13)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(13)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	14
+#define TIMER1_COMPB_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(14)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		15
+#define TIMER1_OVF_vect			_VECTOR(15)
+#define SIG_OVERFLOW1			_VECTOR(15)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	16
+#define TIMER0_COMPA_vect		_VECTOR(16)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(16)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	17
+#define TIMER0_COMPB_vect		_VECTOR(17)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(17)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		18
+#define TIMER0_OVF_vect			_VECTOR(18)
+#define SIG_OVERFLOW0			_VECTOR(18)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		19
+#define SPI_STC_vect			_VECTOR(19)
+#define SIG_SPI				    _VECTOR(19)
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect_num		20
+#define USART0_RX_vect			_VECTOR(20)
+#define SIG_USART_RECV			_VECTOR(20)
+
+/* USART0 Data register Empty */
+#define USART0_UDRE_vect_num	21
+#define USART0_UDRE_vect		_VECTOR(21)
+#define SIG_USART_DATA			_VECTOR(21)
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect_num		22
+#define USART0_TX_vect			_VECTOR(22)
+#define SIG_USART_TRANS			_VECTOR(22)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	23
+#define ANALOG_COMP_vect		_VECTOR(23)
+#define SIG_COMPARATOR			_VECTOR(23)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			24
+#define ADC_vect	    		_VECTOR(24)
+#define SIG_ADC			    	_VECTOR(24)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		25
+#define EE_READY_vect			_VECTOR(25)
+#define SIG_EEPROM_READY		_VECTOR(25)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num			26
+#define TWI_vect	    		_VECTOR(26)
+#define SIG_2WIRE_SERIAL		_VECTOR(26)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		27
+#define SPM_READY_vect			_VECTOR(27)
+#define SIG_SPM_READY			_VECTOR(27)
+
+#if defined(__AVR_ATmega644__)
+
+# define _VECTORS_SIZE 112
+
+#else /* !defined(__AVR_ATmega644__) */
+
+/* USART1, Rx Complete */
+/* USART1 RX complete */
+#define USART1_RX_vect_num		28
+#define USART1_RX_vect			_VECTOR(28)
+#define SIG_USART1_RECV			_VECTOR(28)
+
+/* USART1 Data register Empty */
+/* USART1 Data Register Empty */
+#define USART1_UDRE_vect_num	29
+#define USART1_UDRE_vect		_VECTOR(29)
+#define SIG_USART1_DATA			_VECTOR(29)
+
+/* USART1, Tx Complete */
+/* USART1 TX complete */
+#define USART1_TX_vect_num		30
+#define USART1_TX_vect			_VECTOR(30)
+#define SIG_USART1_TRANS		_VECTOR(30)
+
+# define _VECTORS_SIZE 124
+
+#endif /* defined(__AVR_ATmega644__) */
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_INTERRUPT2
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_PIN_CHANGE3
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART_RECV
+#pragma GCC poison SIG_USART_DATA
+#pragma GCC poison SIG_USART_TRANS
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+#pragma GCC poison SIG_USART1_RECV
+#pragma GCC poison SIG_USART1_DATA
+#pragma GCC poison SIG_USART1_TRANS
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
+
 
 /* Constants */
 #define SPM_PAGESIZE 256
@@ -91,7 +995,6 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x0A
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -99,5 +1002,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_IOM644P_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom644pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom644pa.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom644pa.h 2035 2009-11-02 02:44:17Z arcanum $ */
 
 /* avr/iom644PA.h - definitions for ATmega644PA */
 
@@ -1376,7 +1376,6 @@
 #define PCINT12_PIN   PINB
 #define PCINT12_BIT   4
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom644rfr2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom644rfr2.h
@@ -1,41 +1,25 @@
-/* Copyright (c) 2013 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* $Id$ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
 
-/* avr/iom644rfr2.h - definitions for ATmega644RFR2 */
 
-#ifndef _AVR_IOM644RFR2_H_
-#define _AVR_IOM644RFR2_H_ 1
+#ifndef _AVR_ATMEGA644RFR2_H_INCLUDED
+#define _AVR_ATMEGA644RFR2_H_INCLUDED
 
-/* This file should only be included from <avr/io.h>, never directly. */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -47,1171 +31,575 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif
 
-#include <avr/sfr_defs.h>
+/* Registers and associated bit numbers */
 
-#ifndef __ASSEMBLER__
-#  define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr))
-#  define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type)
-#  define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type)
-#endif /* __ASSEMBLER__ */
-
-/*
- * USAGE:
- *
- * simple register assignment:
- * TIFR1 = 0x17
- * subregister assignment:
- * TIFR1_struct.ocf1a = 1
- * (subregister names are converted to small letters)
- */
-
-
-/* Port A Input Pins Address */
-#define PINA                            _SFR_IO8(0x00)
-
-  /* PINA */
-
-#define PINA0                           0
-#define PINA1                           1
-#define PINA2                           2
-#define PINA3                           3
-#define PINA4                           4
-#define PINA5                           5
-#define PINA6                           6
-#define PINA7                           7
-
-/* Port A Data Direction Register */
-#define DDRA                            _SFR_IO8(0x01)
-
-  /* DDRA */
-
-#define DDA0                            0
-#define DDA1                            1
-#define DDA2                            2
-#define DDA3                            3
-#define DDA4                            4
-#define DDA5                            5
-#define DDA6                            6
-#define DDA7                            7
-
-/* Port A Data Register */
-#define PORTA                           _SFR_IO8(0x02)
-
-  /* PORTA */
-
-#define PORTA0                          0
-#define PA0                             0
-#define PORTA1                          1
-#define PA1                             1
-#define PORTA2                          2
-#define PA2                             2
-#define PORTA3                          3
-#define PA3                             3
-#define PORTA4                          4
-#define PA4                             4
-#define PORTA5                          5
-#define PA5                             5
-#define PORTA6                          6
-#define PA6                             6
-#define PORTA7                          7
-#define PA7                             7
-
-/* Port B Input Pins Address */
-#define PINB                            _SFR_IO8(0x03)
-
-  /* PINB */
-
-#define PINB0                           0
-#define PINB1                           1
-#define PINB2                           2
-#define PINB3                           3
-#define PINB4                           4
-#define PINB5                           5
-#define PINB6                           6
-#define PINB7                           7
-
-/* Port B Data Direction Register */
-#define DDRB                            _SFR_IO8(0x04)
-
-  /* DDRB */
-
-#define DDB0                            0
-#define DDB1                            1
-#define DDB2                            2
-#define DDB3                            3
-#define DDB4                            4
-#define DDB5                            5
-#define DDB6                            6
-#define DDB7                            7
-
-/* Port B Data Register */
-#define PORTB                           _SFR_IO8(0x05)
-
-  /* PORTB */
-
-#define PORTB0                          0
-#define PB0                             0
-#define PORTB1                          1
-#define PB1                             1
-#define PORTB2                          2
-#define PB2                             2
-#define PORTB3                          3
-#define PB3                             3
-#define PORTB4                          4
-#define PB4                             4
-#define PORTB5                          5
-#define PB5                             5
-#define PORTB6                          6
-#define PB6                             6
-#define PORTB7                          7
-#define PB7                             7
-
-/* Port C Input Pins Address */
-#define PINC                            _SFR_IO8(0x06)
-
-  /* PINC */
-
-#define PINC0                           0
-#define PINC1                           1
-#define PINC2                           2
-#define PINC3                           3
-#define PINC4                           4
-#define PINC5                           5
-#define PINC6                           6
-#define PINC7                           7
-
-/* Port C Data Direction Register */
-#define DDRC                            _SFR_IO8(0x07)
-
-  /* DDRC */
-
-#define DDC0                            0
-#define DDC1                            1
-#define DDC2                            2
-#define DDC3                            3
-#define DDC4                            4
-#define DDC5                            5
-#define DDC6                            6
-#define DDC7                            7
-
-/* Port C Data Register */
-#define PORTC                           _SFR_IO8(0x08)
-
-  /* PORTC */
-
-#define PORTC0                          0
-#define PC0                             0
-#define PORTC1                          1
-#define PC1                             1
-#define PORTC2                          2
-#define PC2                             2
-#define PORTC3                          3
-#define PC3                             3
-#define PORTC4                          4
-#define PC4                             4
-#define PORTC5                          5
-#define PC5                             5
-#define PORTC6                          6
-#define PC6                             6
-#define PORTC7                          7
-#define PC7                             7
-
-/* Port D Input Pins Address */
-#define PIND                            _SFR_IO8(0x09)
-
-  /* PIND */
-
-#define PIND0                           0
-#define PIND1                           1
-#define PIND2                           2
-#define PIND3                           3
-#define PIND4                           4
-#define PIND5                           5
-#define PIND6                           6
-#define PIND7                           7
-
-/* Port D Data Direction Register */
-#define DDRD                            _SFR_IO8(0x0A)
-
-  /* DDRD */
-
-#define DDD0                            0
-#define DDD1                            1
-#define DDD2                            2
-#define DDD3                            3
-#define DDD4                            4
-#define DDD5                            5
-#define DDD6                            6
-#define DDD7                            7
-
-/* Port D Data Register */
-#define PORTD                           _SFR_IO8(0x0B)
-
-  /* PORTD */
-
-#define PORTD0                          0
-#define PD0                             0
-#define PORTD1                          1
-#define PD1                             1
-#define PORTD2                          2
-#define PD2                             2
-#define PORTD3                          3
-#define PD3                             3
-#define PORTD4                          4
-#define PD4                             4
-#define PORTD5                          5
-#define PD5                             5
-#define PORTD6                          6
-#define PD6                             6
-#define PORTD7                          7
-#define PD7                             7
-
-/* Port E Input Pins Address */
-#define PINE                            _SFR_IO8(0x0C)
-
-  /* PINE */
-
-#define PINE0                           0
-#define PINE1                           1
-#define PINE2                           2
-#define PINE3                           3
-#define PINE4                           4
-#define PINE5                           5
-#define PINE6                           6
-#define PINE7                           7
-
-/* Port E Data Direction Register */
-#define DDRE                            _SFR_IO8(0x0D)
-
-  /* DDRE */
-
-#define DDE0                            0
-#define DDE1                            1
-#define DDE2                            2
-#define DDE3                            3
-#define DDE4                            4
-#define DDE5                            5
-#define DDE6                            6
-#define DDE7                            7
-
-/* Port E Data Register */
-#define PORTE                           _SFR_IO8(0x0E)
-
-  /* PORTE */
-
-#define PORTE0                          0
-#define PE0                             0
-#define PORTE1                          1
-#define PE1                             1
-#define PORTE2                          2
-#define PE2                             2
-#define PORTE3                          3
-#define PE3                             3
-#define PORTE4                          4
-#define PE4                             4
-#define PORTE5                          5
-#define PE5                             5
-#define PORTE6                          6
-#define PE6                             6
-#define PORTE7                          7
-#define PE7                             7
-
-/* Port F Input Pins Address */
-#define PINF                            _SFR_IO8(0x0F)
-
-  /* PINF */
-
-#define PINF0                           0
-#define PINF1                           1
-#define PINF2                           2
-#define PINF3                           3
-#define PINF4                           4
-#define PINF5                           5
-#define PINF6                           6
-#define PINF7                           7
-
-/* Port F Data Direction Register */
-#define DDRF                            _SFR_IO8(0x10)
-
-  /* DDRF */
-
-#define DDF0                            0
-#define DDF1                            1
-#define DDF2                            2
-#define DDF3                            3
-#define DDF4                            4
-#define DDF5                            5
-#define DDF6                            6
-#define DDF7                            7
-
-/* Port F Data Register */
-#define PORTF                           _SFR_IO8(0x11)
-
-  /* PORTF */
-
-#define PORTF0                          0
-#define PF0                             0
-#define PORTF1                          1
-#define PF1                             1
-#define PORTF2                          2
-#define PF2                             2
-#define PORTF3                          3
-#define PF3                             3
-#define PORTF4                          4
-#define PF4                             4
-#define PORTF5                          5
-#define PF5                             5
-#define PORTF6                          6
-#define PF6                             6
-#define PORTF7                          7
-#define PF7                             7
-
-/* Port G Input Pins Address */
-#define PING                            _SFR_IO8(0x12)
-
-  /* PING */
-
-#define PING0                           0
-#define PING1                           1
-#define PING2                           2
-#define PING3                           3
-#define PING4                           4
-#define PING5                           5
-
-/* Port G Data Direction Register */
-#define DDRG                            _SFR_IO8(0x13)
-
-  /* DDRG */
-
-#define DDG0                            0
-#define DDG1                            1
-#define DDG2                            2
-#define DDG3                            3
-#define DDG4                            4
-#define DDG5                            5
-
-/* Port G Data Register */
-#define PORTG                           _SFR_IO8(0x14)
-
-  /* PORTG */
-
-#define PORTG0                          0
-#define PG0                             0
-#define PORTG1                          1
-#define PG1                             1
-#define PORTG2                          2
-#define PG2                             2
-#define PORTG3                          3
-#define PG3                             3
-#define PORTG4                          4
-#define PG4                             4
-#define PORTG5                          5
-#define PG5                             5
-
-/* Timer/Counter0 Interrupt Flag Register */
-#define TIFR0                           _SFR_IO8(0x15)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR0 {
-        unsigned int tov0 : 1;	/* Timer/Counter0 Overflow Flag */
-        unsigned int ocf0a : 1;	/* Timer/Counter0 Output Compare A Match Flag */
-        unsigned int ocf0b : 1;	/* Timer/Counter0 Output Compare B Match Flag */
-        unsigned int : 5;
-};
-
-#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR0 */
-
-#define TOV0                            0
-#define OCF0A                           1
-#define OCF0B                           2
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1                           _SFR_IO8(0x16)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR1 {
-        unsigned int tov1 : 1;	/* Timer/Counter1 Overflow Flag */
-        unsigned int ocf1a : 1;	/* Timer/Counter1 Output Compare A Match Flag */
-        unsigned int ocf1b : 1;	/* Timer/Counter1 Output Compare B Match Flag */
-        unsigned int ocf1c : 1;	/* Timer/Counter1 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf1 : 1;	/* Timer/Counter1 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR1 */
-
-#define TOV1                            0
-#define OCF1A                           1
-#define OCF1B                           2
-#define OCF1C                           3
-#define ICF1                            5
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR2                           _SFR_IO8(0x17)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR2 {
-        unsigned int tov2 : 1;	/* Timer/Counter2 Overflow Flag */
-        unsigned int ocf2a : 1;	/* Output Compare Flag 2 A */
-        unsigned int ocf2b : 1;	/* Output Compare Flag 2 B */
-        unsigned int : 5;
-};
-
-#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR2 */
-
-#define TOV2                            0
-#define OCF2A                           1
-#define OCF2B                           2
-
-/* Timer/Counter3 Interrupt Flag Register */
-#define TIFR3                           _SFR_IO8(0x18)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR3 {
-        unsigned int tov3 : 1;	/* Timer/Counter3 Overflow Flag */
-        unsigned int ocf3a : 1;	/* Timer/Counter3 Output Compare A Match Flag */
-        unsigned int ocf3b : 1;	/* Timer/Counter3 Output Compare B Match Flag */
-        unsigned int ocf3c : 1;	/* Timer/Counter3 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf3 : 1;	/* Timer/Counter3 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR3 */
-
-#define TOV3                            0
-#define OCF3A                           1
-#define OCF3B                           2
-#define OCF3C                           3
-#define ICF3                            5
-
-/* Timer/Counter4 Interrupt Flag Register */
-#define TIFR4                           _SFR_IO8(0x19)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR4 {
-        unsigned int tov4 : 1;	/* Timer/Counter4 Overflow Flag */
-        unsigned int ocf4a : 1;	/* Timer/Counter4 Output Compare A Match Flag */
-        unsigned int ocf4b : 1;	/* Timer/Counter4 Output Compare B Match Flag */
-        unsigned int ocf4c : 1;	/* Timer/Counter4 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf4 : 1;	/* Timer/Counter4 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR4 */
-
-#define TOV4                            0
-#define OCF4A                           1
-#define OCF4B                           2
-#define OCF4C                           3
-#define ICF4                            5
-
-/* Timer/Counter5 Interrupt Flag Register */
-#define TIFR5                           _SFR_IO8(0x1A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR5 {
-        unsigned int tov5 : 1;	/* Timer/Counter5 Overflow Flag */
-        unsigned int ocf5a : 1;	/* Timer/Counter5 Output Compare A Match Flag */
-        unsigned int ocf5b : 1;	/* Timer/Counter5 Output Compare B Match Flag */
-        unsigned int ocf5c : 1;	/* Timer/Counter5 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf5 : 1;	/* Timer/Counter5 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR5 */
-
-#define TOV5                            0
-#define OCF5A                           1
-#define OCF5B                           2
-#define OCF5C                           3
-#define ICF5                            5
-
-/* Pin Change Interrupt Flag Register */
-#define PCIFR                           _SFR_IO8(0x1B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCIFR {
-        unsigned int pcif : 3;	/* Pin Change Interrupt Flags */
-        unsigned int : 5;
-};
-
-#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCIFR */
-
-#define PCIF0                           0
-#define PCIF1                           1
-#define PCIF2                           2
-
-/* External Interrupt Flag Register */
-#define EIFR                            _SFR_IO8(0x1C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIFR {
-        unsigned int intf : 8;	/* External Interrupt Flag */
-};
-
-#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIFR */
-
-#define INTF0                           0
-#define INTF1                           1
-#define INTF2                           2
-#define INTF3                           3
-#define INTF4                           4
-#define INTF5                           5
-#define INTF6                           6
-#define INTF7                           7
-
-/* External Interrupt Mask Register */
-#define EIMSK                           _SFR_IO8(0x1D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIMSK {
-        unsigned int intm : 8;	/* External Interrupt Request Enable */
-};
-
-#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIMSK */
-
-#define INT0                            0
-#define INT1                            1
-#define INT2                            2
-#define INT3                            3
-#define INT4                            4
-#define INT5                            5
-#define INT6                            6
-#define INT7                            7
-
-/* General Purpose IO Register 0 */
-#define GPIOR0                          _SFR_IO8(0x1E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR0 {
-        unsigned int gpior00 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior01 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior02 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior03 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior04 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior05 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior06 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior07 : 1;	/* General Purpose I/O Register 0 Value */
-};
-
-#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR0 */
-
-#define GPIOR00                         0
-#define GPIOR01                         1
-#define GPIOR02                         2
-#define GPIOR03                         3
-#define GPIOR04                         4
-#define GPIOR05                         5
-#define GPIOR06                         6
-#define GPIOR07                         7
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* EEPROM Control Register */
-#define EECR                            _SFR_IO8(0x1F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EECR {
-        unsigned int eere : 1;	/* EEPROM Read Enable */
-        unsigned int eepe : 1;	/* EEPROM Programming Enable */
-        unsigned int eempe : 1;	/* EEPROM Master Write Enable */
-        unsigned int eerie : 1;	/* EEPROM Ready Interrupt Enable */
-        unsigned int eepm : 2;	/* EEPROM Programming Mode */
-        unsigned int : 2;
-};
-
-#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EECR */
-
-#define EERE                            0
-#define EEPE                            1
-#define EEMPE                           2
-#define EERIE                           3
-#define EEPM0                           4
-#define EEPM1                           5
-
-/* EEPROM Data Register */
-#define EEDR                            _SFR_IO8(0x20)
-
-  /* EEDR */
-
-#define EEDR0                           0
-#define EEDR1                           1
-#define EEDR2                           2
-#define EEDR3                           3
-#define EEDR4                           4
-#define EEDR5                           5
-#define EEDR6                           6
-#define EEDR7                           7
-
-/* EEPROM Address Register  Bytes */
-#define EEAR                            _SFR_IO16(0x21)
-#define EEARL                           _SFR_IO8(0x21)
-#define EEARH                           _SFR_IO8(0x22)
-
-/* General Timer/Counter Control Register */
-#define GTCCR                           _SFR_IO8(0x23)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GTCCR {
-        unsigned int psrsync : 1;	/* Prescaler Reset for Synchronous Timer/Counters */
-        unsigned int psrasy : 1;	/* Prescaler Reset Timer/Counter2 */
-        unsigned int : 5;
-        unsigned int tsm : 1;	/* Timer/Counter Synchronization Mode */
-};
-
-#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GTCCR */
-
-#define PSRSYNC                         0
-#define PSR10                           0
-#define PSRASY                          1
-#define PSR2                            1
-#define TSM                             7
-
-/* Timer/Counter0 Control Register A */
-#define TCCR0A                          _SFR_IO8(0x24)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0A {
-        unsigned int wgm0 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com0b : 2;	/* Compare Match Output B Mode */
-        unsigned int com0a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0A */
-
-#define WGM00                           0
-#define WGM01                           1
-#define COM0B0                          4
-#define COM0B1                          5
-#define COM0A0                          6
-#define COM0A1                          7
-
-/* Timer/Counter0 Control Register B */
-#define TCCR0B                          _SFR_IO8(0x25)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0B {
-        unsigned int cs0 : 3;	/* Clock Select */
-        unsigned int wgm02 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc0b : 1;	/* Force Output Compare B */
-        unsigned int foc0a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0B */
-
-#define CS00                            0
-#define CS01                            1
-#define CS02                            2
-#define WGM02                           3
-#define FOC0B                           6
-#define FOC0A                           7
-
-/* Timer/Counter0 Register */
-#define TCNT0                           _SFR_IO8(0x26)
-
-  /* TCNT0 */
-
-#define TCNT0_0                         0
-#define TCNT0_1                         1
-#define TCNT0_2                         2
-#define TCNT0_3                         3
-#define TCNT0_4                         4
-#define TCNT0_5                         5
-#define TCNT0_6                         6
-#define TCNT0_7                         7
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0A                           _SFR_IO8(0x27)
-
-  /* OCR0A */
-
-#define OCR0A_0                         0
-#define OCR0A_1                         1
-#define OCR0A_2                         2
-#define OCR0A_3                         3
-#define OCR0A_4                         4
-#define OCR0A_5                         5
-#define OCR0A_6                         6
-#define OCR0A_7                         7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B                           _SFR_IO8(0x28)
-
-  /* OCR0B */
-
-#define OCR0B_0                         0
-#define OCR0B_1                         1
-#define OCR0B_2                         2
-#define OCR0B_3                         3
-#define OCR0B_4                         4
-#define OCR0B_5                         5
-#define OCR0B_6                         6
-#define OCR0B_7                         7
-
-/* General Purpose IO Register 1 */
-#define GPIOR1                          _SFR_IO8(0x2A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR1 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 1 Value */
-};
-
-#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR1 */
-
-#define GPIOR10                         0
-#define GPIOR11                         1
-#define GPIOR12                         2
-#define GPIOR13                         3
-#define GPIOR14                         4
-#define GPIOR15                         5
-#define GPIOR16                         6
-#define GPIOR17                         7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2                          _SFR_IO8(0x2B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR2 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 2 Value */
-};
-
-#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR2 */
-
-#define GPIOR20                         0
-#define GPIOR21                         1
-#define GPIOR22                         2
-#define GPIOR23                         3
-#define GPIOR24                         4
-#define GPIOR25                         5
-#define GPIOR26                         6
-#define GPIOR27                         7
-
-/* SPI Control Register */
-#define SPCR                            _SFR_IO8(0x2C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPCR {
-        unsigned int spr : 2;	/* SPI Clock Rate Select 1 and 0 */
-        unsigned int cpha : 1;	/* Clock Phase */
-        unsigned int cpol : 1;	/* Clock polarity */
-        unsigned int mstr : 1;	/* Master/Slave Select */
-        unsigned int dord : 1;	/* Data Order */
-        unsigned int spe : 1;	/* SPI Enable */
-        unsigned int spie : 1;	/* SPI Interrupt Enable */
-};
-
-#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPCR */
-
-#define SPR0                            0
-#define SPR1                            1
-#define CPHA                            2
-#define CPOL                            3
-#define MSTR                            4
-#define DORD                            5
-#define SPE                             6
-#define SPIE                            7
-
-/* SPI Status Register */
-#define SPSR                            _SFR_IO8(0x2D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPSR {
-        unsigned int spi2x : 1;	/* Double SPI Speed Bit */
-        unsigned int : 5;
-        unsigned int wcol : 1;	/* Write Collision Flag */
-        unsigned int spif : 1;	/* SPI Interrupt Flag */
-};
-
-#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPSR */
-
-#define SPI2X                           0
-#define WCOL                            6
-#define SPIF                            7
-
-/* SPI Data Register */
-#define SPDR                            _SFR_IO8(0x2E)
-
-  /* SPDR */
-
-#define SPDR0                           0
-#define SPDR1                           1
-#define SPDR2                           2
-#define SPDR3                           3
-#define SPDR4                           4
-#define SPDR5                           5
-#define SPDR6                           6
-#define SPDR7                           7
-
-/* Analog Comparator Control And Status Register */
-#define ACSR                            _SFR_IO8(0x30)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ACSR {
-        unsigned int acis : 2;	/* Analog Comparator Interrupt Mode Select */
-        unsigned int acic : 1;	/* Analog Comparator Input Capture Enable */
-        unsigned int acie : 1;	/* Analog Comparator Interrupt Enable */
-        unsigned int aci : 1;	/* Analog Comparator Interrupt Flag */
-        unsigned int aco : 1;	/* Analog Compare Output */
-        unsigned int acbg : 1;	/* Analog Comparator Bandgap Select */
-        unsigned int acd : 1;	/* Analog Comparator Disable */
-};
-
-#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ACSR */
-
-#define ACIS0                           0
-#define ACIS1                           1
-#define ACIC                            2
-#define ACIE                            3
-#define ACI                             4
-#define ACO                             5
-#define ACBG                            6
-#define ACD                             7
-
-/* On-Chip Debug Register */
-#define OCDR                            _SFR_IO8(0x31)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OCDR {
-        unsigned int ocdr : 8;	/* On-Chip Debug Register Data */
-};
-
-#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OCDR */
-
-#define OCDR0                           0
-#define OCDR1                           1
-#define OCDR2                           2
-#define OCDR3                           3
-#define OCDR4                           4
-#define OCDR5                           5
-#define OCDR6                           6
-#define OCDR7                           7
-#define IDRD                            7
-
-/* Sleep Mode Control Register */
-#define SMCR                            _SFR_IO8(0x33)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SMCR {
-        unsigned int se : 1;	/* Sleep Enable */
-        unsigned int sm : 3;	/* Sleep Mode Select bits */
-        unsigned int : 4;
-};
-
-#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SMCR */
-
-#define SE                              0
-#define SM0                             1
-#define SM1                             2
-#define SM2                             3
-
-/* MCU Status Register */
-#define MCUSR                           _SFR_IO8(0x34)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUSR {
-        unsigned int porf : 1;	/* Power-on Reset Flag */
-        unsigned int extrf : 1;	/* External Reset Flag */
-        unsigned int borf : 1;	/* Brown-out Reset Flag */
-        unsigned int wdrf : 1;	/* Watchdog Reset Flag */
-        unsigned int jtrf : 1;	/* JTAG Reset Flag */
-        unsigned int : 3;
-};
-
-#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUSR */
-
-#define PORF                            0
-#define EXTRF                           1
-#define BORF                            2
-#define WDRF                            3
-#define JTRF                            4
-
-/* MCU Control Register */
-#define MCUCR                           _SFR_IO8(0x35)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUCR {
-        unsigned int ivce : 1;	/* Interrupt Vector Change Enable */
-        unsigned int ivsel : 1;	/* Interrupt Vector Select */
-        unsigned int : 2;
-        unsigned int pud : 1;	/* Pull-up Disable */
-        unsigned int : 2;
-        unsigned int jtd : 1;	/* JTAG Interface Disable */
-};
-
-#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUCR */
-
-#define IVCE                            0
-#define IVSEL                           1
-#define PUD                             4
-#define JTD                             7
-
-/* Store Program Memory Control Register */
-#define SPMCSR                          _SFR_IO8(0x37)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPMCSR {
-        unsigned int spmen : 1;	/* Store Program Memory Enable */
-        unsigned int pgers : 1;	/* Page Erase */
-        unsigned int pgwrt : 1;	/* Page Write */
-        unsigned int blbset : 1;	/* Boot Lock Bit Set */
-        unsigned int rwwsre : 1;	/* Read While Write Section Read Enable */
-        unsigned int sigrd : 1;	/* Signature Row Read */
-        unsigned int rwwsb : 1;	/* Read While Write Section Busy */
-        unsigned int spmie : 1;	/* SPM Interrupt Enable */
-};
-
-#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPMCSR */
-
-#define SPMEN                           0
-#define PGERS                           1
-#define PGWRT                           2
-#define BLBSET                          3
-#define RWWSRE                          4
-#define SIGRD                           5
-#define RWWSB                           6
-#define SPMIE                           7
-
-/* Stack Pointer */
-#define SP                              _SFR_IO16(0x3D)
-#define SPL                             _SFR_IO8(0x3D)
-#define SPH                             _SFR_IO8(0x3E)
-
-/* Status Register */
-#define SREG                            _SFR_IO8(0x3F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SREG {
-        unsigned int c : 1;	/* Carry Flag */
-        unsigned int z : 1;	/* Zero Flag */
-        unsigned int n : 1;	/* Negative Flag */
-        unsigned int v : 1;	/* Two's Complement Overflow Flag */
-        unsigned int s : 1;	/* Sign Bit */
-        unsigned int h : 1;	/* Half Carry Flag */
-        unsigned int t : 1;	/* Bit Copy Storage */
-        unsigned int i : 1;	/* Global Interrupt Enable */
-};
-
-#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SREG */
-
-#define SREG_C                          0
-#define SREG_Z                          1
-#define SREG_N                          2
-#define SREG_V                          3
-#define SREG_S                          4
-#define SREG_H                          5
-#define SREG_T                          6
-#define SREG_I                          7
-
-/* Watchdog Timer Control Register */
-#define WDTCSR                          _SFR_MEM8(0x60)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_WDTCSR {
-        unsigned int wdp : 3;	/* Watchdog Timer Prescaler Bits */
-        unsigned int wde : 1;	/* Watch Dog Enable */
-        unsigned int wdce : 1;	/* Watchdog Change Enable */
-        unsigned int : 1;
-        unsigned int wdie : 1;	/* Watchdog Timeout Interrupt Enable */
-        unsigned int wdif : 1;	/* Watchdog Timeout Interrupt Flag */
-};
-
-#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* WDTCSR */
-
-#define WDP0                            0
-#define WDP1                            1
-#define WDP2                            2
-#define WDE                             3
-#define WDCE                            4
-#define WDP3                            5
-#define WDIE                            6
-#define WDIF                            7
-
-/* Clock Prescale Register */
-#define CLKPR                           _SFR_MEM8(0x61)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CLKPR {
-        unsigned int clkps : 4;	/* Clock Prescaler Select Bits */
-        unsigned int : 3;
-        unsigned int clkpce : 1;	/* Clock Prescaler Change Enable */
-};
-
-#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CLKPR */
-
-#define CLKPS0                          0
-#define CLKPS1                          1
-#define CLKPS2                          2
-#define CLKPS3                          3
-#define CLKPCE                          7
-
-/* Power Reduction Register 2 */
-#define PRR2                            _SFR_MEM8(0x63)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR2 {
-        unsigned int prram : 4;	/* Power Reduction SRAMs */
-        unsigned int : 4;
-};
-
-#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR2 */
-
-#define PRRAM0                          0
-#define PRRAM1                          1
-#define PRRAM2                          2
-#define PRRAM3                          3
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
+#define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
+#define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
+#define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
+#define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
+#define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
+#define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
+#define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE7  7
+#define PORTE6  6
+#define PORTE5  5
+#define PORTE4  4
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
+#define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
+#define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
+#define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
+#define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
+#define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
+#define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
+#define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PORTF7  7
+#define PORTF6  6
+#define PORTF5  5
+#define PORTF4  4
+#define PORTF3  3
+#define PORTF2  2
+#define PORTF1  1
+#define PORTF0  0
+
+#define PING    _SFR_IO8(0x12)
+#define PING7   7
+#define PING6   6
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDRG7   7
+// Inserted "DDG7" from "DDRG7" due to compatibility
+#define DDG7    7
+#define DDRG6   6
+// Inserted "DDG6" from "DDRG6" due to compatibility
+#define DDG6    6
+#define DDRG5   5
+// Inserted "DDG5" from "DDRG5" due to compatibility
+#define DDG5    5
+#define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
+#define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
+#define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
+#define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
+#define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PORTG7  7
+#define PORTG6  6
+#define PORTG5  5
+#define PORTG4  4
+#define PORTG3  3
+#define PORTG2  2
+#define PORTG1  1
+#define PORTG0  0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define OCF1C   3
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+#define Res0    3
+#define Res1    4
+#define Res2    5
+#define Res3    6
+#define Res4    7
+
+#define TIFR3   _SFR_IO8(0x18)
+#define TOV3    0
+#define OCF3A   1
+#define OCF3B   2
+#define OCF3C   3
+#define ICF3    5
+
+#define TIFR4   _SFR_IO8(0x19)
+#define TOV4    0
+#define OCF4A   1
+#define OCF4B   2
+#define OCF4C   3
+#define ICF4    5
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define TOV5    0
+#define OCF5A   1
+#define OCF5B   2
+#define OCF5C   3
+#define ICF5    5
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+#define INTF2   2
+#define INTF3   3
+#define INTF4   4
+#define INTF5   5
+#define INTF6   6
+#define INTF7   7
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+#define INT2    2
+#define INT3    3
+#define INT4    4
+#define INT5    5
+#define INT6    6
+#define INT7    7
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define PSRASY  1
+#define TSM     7
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define OCDR    _SFR_IO8(0x31)
+#define OCDR0   0
+#define OCDR1   1
+#define OCDR2   2
+#define OCDR3   3
+#define OCDR4   4
+#define OCDR5   5
+#define OCDR6   6
+#define OCDR7   7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62] */
+
+#define PRR2    _SFR_MEM8(0x63)
+#define PRRAM0  0
+#define PRRAM1  1
+#define PRRAM2  2
+#define PRRAM3  3
 
 #define __AVR_HAVE_PRR2	((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3))
 #define __AVR_HAVE_PRR2_PRRAM0
@@ -1219,36 +607,15 @@
 #define __AVR_HAVE_PRR2_PRRAM2
 #define __AVR_HAVE_PRR2_PRRAM3
 
-/* Power Reduction Register0 */
-#define PRR0                            _SFR_MEM8(0x64)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR0 {
-        unsigned int pradc : 1;	/* Power Reduction ADC */
-        unsigned int prusart0 : 1;	/* Power Reduction USART */
-        unsigned int prspi : 1;	/* Power Reduction Serial Peripheral Interface */
-        unsigned int prtim1 : 1;	/* Power Reduction Timer/Counter1 */
-        unsigned int prpga : 1;	/* Power Reduction PGA */
-        unsigned int prtim0 : 1;	/* Power Reduction Timer/Counter0 */
-        unsigned int prtim2 : 1;	/* Power Reduction Timer/Counter2 */
-        unsigned int prtwi : 1;	/* Power Reduction TWI */
-};
-
-#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR0 */
-
-#define PRADC                           0
-#define PRUSART0                        1
-#define PRSPI                           2
-#define PRTIM1                          3
-#define PRPGA                           4
-#define PRTIM0                          5
-#define PRTIM2                          6
-#define PRTWI                           7
+#define PRR0    _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRPGA   4
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
 
 #define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
 #define __AVR_HAVE_PRR0_PRADC
@@ -1260,32 +627,13 @@
 #define __AVR_HAVE_PRR0_PRTIM2
 #define __AVR_HAVE_PRR0_PRTWI
 
-/* Power Reduction Register 1 */
-#define PRR1                            _SFR_MEM8(0x65)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR1 {
-        unsigned int prusart1 : 1;	/* Power Reduction USART1 */
-        unsigned int : 2;
-        unsigned int prtim3 : 1;	/* Power Reduction Timer/Counter3 */
-        unsigned int prtim4 : 1;	/* Power Reduction Timer/Counter4 */
-        unsigned int prtim5 : 1;	/* Power Reduction Timer/Counter5 */
-        unsigned int prtrx24 : 1;	/* Power Reduction Transceiver */
-        unsigned int : 1;
-};
-
-#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR1 */
-
-#define PRUSART1                        0
-#define PRTIM3                          3
-#define PRTIM4                          4
-#define PRTIM5                          5
-#define PRTRX24                         6
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSART1 0
+#define PRTIM3  3
+#define PRTIM4  4
+#define PRTIM5  5
+#define PRTRX24 6
+#define Res     7
 
 #define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24))
 #define __AVR_HAVE_PRR1_PRUSART1
@@ -1294,4975 +642,2062 @@
 #define __AVR_HAVE_PRR1_PRTIM5
 #define __AVR_HAVE_PRR1_PRTRX24
 
-/* Oscillator Calibration Value */
-#define OSCCAL                          _SFR_MEM8(0x66)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OSCCAL {
-        unsigned int cal : 8;	/* Oscillator Calibration Tuning Value */
-};
-
-#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OSCCAL */
-
-#define CAL0                            0
-#define CAL1                            1
-#define CAL2                            2
-#define CAL3                            3
-#define CAL4                            4
-#define CAL5                            5
-#define CAL6                            6
-#define CAL7                            7
-
-/* Reference Voltage Calibration Register */
-#define BGCR                            _SFR_MEM8(0x67)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BGCR {
-        unsigned int bgcal : 3;	/* Coarse Calibration Bits */
-        unsigned int bgcal_fine : 4;	/* Fine Calibration Bits */
-        unsigned int : 1;
-};
-
-#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* BGCR */
-
-#define BGCAL0                          0
-#define BGCAL1                          1
-#define BGCAL2                          2
-#define BGCAL_FINE0                     3
-#define BGCAL_FINE1                     4
-#define BGCAL_FINE2                     5
-#define BGCAL_FINE3                     6
-
-/* Pin Change Interrupt Control Register */
-#define PCICR                           _SFR_MEM8(0x68)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCICR {
-        unsigned int pcie : 3;	/* Pin Change Interrupt Enables */
-        unsigned int : 5;
-};
-
-#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCICR */
-
-#define PCIE0                           0
-#define PCIE1                           1
-#define PCIE2                           2
-
-/* External Interrupt Control Register A */
-#define EICRA                           _SFR_MEM8(0x69)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRA {
-        unsigned int isc0 : 2;	/* External Interrupt 0 Sense Control Bit */
-        unsigned int isc1 : 2;	/* External Interrupt 1 Sense Control Bit */
-        unsigned int isc2 : 2;	/* External Interrupt 2 Sense Control Bit */
-        unsigned int isc3 : 2;	/* External Interrupt 3 Sense Control Bit */
-};
-
-#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRA */
-
-#define ISC00                           0
-#define ISC01                           1
-#define ISC10                           2
-#define ISC11                           3
-#define ISC20                           4
-#define ISC21                           5
-#define ISC30                           6
-#define ISC31                           7
-
-/* External Interrupt Control Register B */
-#define EICRB                           _SFR_MEM8(0x6A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRB {
-        unsigned int isc4 : 2;	/* External Interrupt 4 Sense Control Bit */
-        unsigned int isc5 : 2;	/* External Interrupt 5 Sense Control Bit */
-        unsigned int isc6 : 2;	/* External Interrupt 6 Sense Control Bit */
-        unsigned int isc7 : 2;	/* External Interrupt 7 Sense Control Bit */
-};
-
-#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRB */
-
-#define ISC40                           0
-#define ISC41                           1
-#define ISC50                           2
-#define ISC51                           3
-#define ISC60                           4
-#define ISC61                           5
-#define ISC70                           6
-#define ISC71                           7
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0                          _SFR_MEM8(0x6B)
-
-  /* PCMSK0 */
-
-#define PCINT0                          0
-#define PCINT1                          1
-#define PCINT2                          2
-#define PCINT3                          3
-#define PCINT4                          4
-#define PCINT5                          5
-#define PCINT6                          6
-#define PCINT7                          7
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1                          _SFR_MEM8(0x6C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK1 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK1 */
-
-#define PCINT8                          0
-#define PCINT9                          1
-#define PCINT10                         2
-#define PCINT11                         3
-#define PCINT12                         4
-#define PCINT13                         5
-#define PCINT14                         6
-#define PCINT15                         7
-
-/* Pin Change Mask Register 2 */
-#define PCMSK2                          _SFR_MEM8(0x6D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK2 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK2 */
-
-#define PCINT16                         0
-#define PCINT17                         1
-#define PCINT18                         2
-#define PCINT19                         3
-#define PCINT20                         4
-#define PCINT21                         5
-#define PCINT22                         6
-#define PCINT23                         7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0                          _SFR_MEM8(0x6E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK0 {
-        unsigned int toie0 : 1;	/* Timer/Counter0 Overflow Interrupt Enable */
-        unsigned int ocie0a : 1;	/* Timer/Counter0 Output Compare Match A Interrupt Enable */
-        unsigned int ocie0b : 1;	/* Timer/Counter0 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK0 */
-
-#define TOIE0                           0
-#define OCIE0A                          1
-#define OCIE0B                          2
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1                          _SFR_MEM8(0x6F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK1 {
-        unsigned int toie1 : 1;	/* Timer/Counter1 Overflow Interrupt Enable */
-        unsigned int ocie1a : 1;	/* Timer/Counter1 Output Compare A Match Interrupt Enable */
-        unsigned int ocie1b : 1;	/* Timer/Counter1 Output Compare B Match Interrupt Enable */
-        unsigned int ocie1c : 1;	/* Timer/Counter1 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie1 : 1;	/* Timer/Counter1 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK1 */
-
-#define TOIE1                           0
-#define OCIE1A                          1
-#define OCIE1B                          2
-#define OCIE1C                          3
-#define ICIE1                           5
-
-/* Timer/Counter Interrupt Mask register */
-#define TIMSK2                          _SFR_MEM8(0x70)
+#define OSCCAL  _SFR_MEM8(0x66)
+#define CAL0    0
+#define CAL1    1
+#define CAL2    2
+#define CAL3    3
+#define CAL4    4
+#define CAL5    5
+#define CAL6    6
+#define CAL7    7
+
+#define BGCR    _SFR_MEM8(0x67)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL_FINE0 3
+#define BGCAL_FINE1 4
+#define BGCAL_FINE2 5
+#define BGCAL_FINE3 6
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+#define ISC20   4
+#define ISC21   5
+#define ISC30   6
+#define ISC31   7
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC40   0
+#define ISC41   1
+#define ISC50   2
+#define ISC51   3
+#define ISC60   4
+#define ISC61   5
+#define ISC70   6
+#define ISC71   7
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define OCIE1C  3
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define TOIE3   0
+#define OCIE3A  1
+#define OCIE3B  2
+#define OCIE3C  3
+#define ICIE3   5
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define TOIE4   0
+#define OCIE4A  1
+#define OCIE4B  2
+#define OCIE4C  3
+#define ICIE4   5
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define TOIE5   0
+#define OCIE5A  1
+#define OCIE5B  2
+#define OCIE5C  3
+#define ICIE5   5
+
+/* Reserved [0x74] */
+
+#define NEMCR   _SFR_MEM8(0x75)
+#define AEAM0   4
+#define AEAM1   5
+#define ENEAM   6
+
+/* Reserved [0x76] */
+
+#define ADCSRC  _SFR_MEM8(0x77)
+#define ADSUT0  0
+#define ADSUT1  1
+#define ADSUT2  2
+#define ADSUT3  3
+#define ADSUT4  4
+#define ADTHT0  6
+#define ADTHT1  7
 
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK2 {
-        unsigned int toie2 : 1;	/* Timer/Counter2 Overflow Interrupt Enable */
-        unsigned int ocie2a : 1;	/* Timer/Counter2 Output Compare Match A Interrupt Enable */
-        unsigned int ocie2b : 1;	/* Timer/Counter2 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK2 */
-
-#define TOIE2                           0
-#define TOIE2A                          0
-#define OCIE2A                          1
-#define OCIE2B                          2
-
-/* Timer/Counter3 Interrupt Mask Register */
-#define TIMSK3                          _SFR_MEM8(0x71)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK3 {
-        unsigned int toie3 : 1;	/* Timer/Counter3 Overflow Interrupt Enable */
-        unsigned int ocie3a : 1;	/* Timer/Counter3 Output Compare A Match Interrupt Enable */
-        unsigned int ocie3b : 1;	/* Timer/Counter3 Output Compare B Match Interrupt Enable */
-        unsigned int ocie3c : 1;	/* Timer/Counter3 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie3 : 1;	/* Timer/Counter3 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK3 */
-
-#define TOIE3                           0
-#define OCIE3A                          1
-#define OCIE3B                          2
-#define OCIE3C                          3
-#define ICIE3                           5
-
-/* Timer/Counter4 Interrupt Mask Register */
-#define TIMSK4                          _SFR_MEM8(0x72)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK4 {
-        unsigned int toie4 : 1;	/* Timer/Counter4 Overflow Interrupt Enable */
-        unsigned int ocie4a : 1;	/* Timer/Counter4 Output Compare A Match Interrupt Enable */
-        unsigned int ocie4b : 1;	/* Timer/Counter4 Output Compare B Match Interrupt Enable */
-        unsigned int ocie4c : 1;	/* Timer/Counter4 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie4 : 1;	/* Timer/Counter4 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK4 */
-
-#define TOIE4                           0
-#define OCIE4A                          1
-#define OCIE4B                          2
-#define OCIE4C                          3
-#define ICIE4                           5
-
-/* Timer/Counter5 Interrupt Mask Register */
-#define TIMSK5                          _SFR_MEM8(0x73)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK5 {
-        unsigned int toie5 : 1;	/* Timer/Counter5 Overflow Interrupt Enable */
-        unsigned int ocie5a : 1;	/* Timer/Counter5 Output Compare A Match Interrupt Enable */
-        unsigned int ocie5b : 1;	/* Timer/Counter5 Output Compare B Match Interrupt Enable */
-        unsigned int ocie5c : 1;	/* Timer/Counter5 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie5 : 1;	/* Timer/Counter5 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK5 */
-
-#define TOIE5                           0
-#define OCIE5A                          1
-#define OCIE5B                          2
-#define OCIE5C                          3
-#define ICIE5                           5
-
-/* Flash Extended-Mode Control-Register */
-#define NEMCR                           _SFR_MEM8(0x75)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_NEMCR {
-        unsigned int : 4;
-        unsigned int aeam : 2;	/* Address for Extended Address Mode of Extra Rows */
-        unsigned int eneam : 1;	/* Enable Extended Address Mode for Extra Rows */
-        unsigned int : 1;
-};
-
-#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* NEMCR */
-
-#define AEAM0                           4
-#define AEAM1                           5
-#define ENEAM                           6
-
-/* The ADC Control and Status Register C */
-#define ADCSRC                          _SFR_MEM8(0x77)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRC {
-        unsigned int adsut : 5;	/* ADC Start-up Time */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int adtht : 2;	/* ADC Track-and-Hold Time */
-};
-
-#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRC */
-
-#define ADSUT0                          0
-#define ADSUT1                          1
-#define ADSUT2                          2
-#define ADSUT3                          3
-#define ADSUT4                          4
-#define ADTHT0                          6
-#define ADTHT1                          7
-
-/* ADC Data Register  Bytes */
+/* Combine ADCL and ADCH */
 #ifndef __ASSEMBLER__
-#define ADC                             _SFR_MEM16(0x78)
-#define ADCL                            _SFR_MEM8(0x78)
-#define ADCH                            _SFR_MEM8(0x79)
-#endif /* __ASSEMBLER__ */
-#define ADCW                            _SFR_MEM16(0x78)
-#define ADCWL                           _SFR_MEM8(0x78)
-#define ADCWH                           _SFR_MEM8(0x79)
-
-/* The ADC Control and Status Register A */
-#define ADCSRA                          _SFR_MEM8(0x7A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRA {
-        unsigned int adps : 3;	/* ADC  Prescaler Select Bits */
-        unsigned int adie : 1;	/* ADC Interrupt Enable */
-        unsigned int adif : 1;	/* ADC Interrupt Flag */
-        unsigned int adate : 1;	/* ADC Auto Trigger Enable */
-        unsigned int adsc : 1;	/* ADC Start Conversion */
-        unsigned int aden : 1;	/* ADC Enable */
-};
-
-#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRA */
-
-#define ADPS0                           0
-#define ADPS1                           1
-#define ADPS2                           2
-#define ADIE                            3
-#define ADIF                            4
-#define ADATE                           5
-#define ADSC                            6
-#define ADEN                            7
-
-/* ADC Control and Status Register B */
-#define ADCSRB                          _SFR_MEM8(0x7B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRB {
-        unsigned int adts : 3;	/* ADC Auto Trigger Source */
-        unsigned int mux5 : 1;	/* Analog Channel and Gain Selection Bits */
-        unsigned int acch : 1;	/* Analog Channel Change */
-        unsigned int refok : 1;	/* Reference Voltage OK */
-        unsigned int acme : 1;	/* Analog Comparator Multiplexer Enable */
-        unsigned int avddok : 1;	/* AVDD Supply Voltage OK */
-};
-
-#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRB */
-
-#define ADTS0                           0
-#define ADTS1                           1
-#define ADTS2                           2
-#define MUX5                            3
-#define ACCH                            4
-#define REFOK                           5
-#define ACME                            6
-#define AVDDOK                          7
-
-/* The ADC Multiplexer Selection Register */
-#define ADMUX                           _SFR_MEM8(0x7C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADMUX {
-        unsigned int mux : 5;	/* Analog Channel and Gain Selection Bits */
-        unsigned int adlar : 1;	/* ADC Left Adjust Result */
-        unsigned int refs : 2;	/* Reference Selection Bits */
-};
-
-#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADMUX */
-
-#define MUX0                            0
-#define MUX1                            1
-#define MUX2                            2
-#define MUX3                            3
-#define MUX4                            4
-#define ADLAR                           5
-#define REFS0                           6
-#define REFS1                           7
-
-/* Digital Input Disable Register 2 */
-#define DIDR2                           _SFR_MEM8(0x7D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR2 {
-        unsigned int adc8d : 1;	/* Reserved Bits */
-        unsigned int adc9d : 1;	/* Reserved Bits */
-        unsigned int adc10d : 1;	/* Reserved Bits */
-        unsigned int adc11d : 1;	/* Reserved Bits */
-        unsigned int adc12d : 1;	/* Reserved Bits */
-        unsigned int adc13d : 1;	/* Reserved Bits */
-        unsigned int adc14d : 1;	/* Reserved Bits */
-        unsigned int adc15d : 1;	/* Reserved Bits */
-};
-
-#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR2 */
-
-#define ADC8D                           0
-#define ADC9D                           1
-#define ADC10D                          2
-#define ADC11D                          3
-#define ADC12D                          4
-#define ADC13D                          5
-#define ADC14D                          6
-#define ADC15D                          7
-
-/* Digital Input Disable Register 0 */
-#define DIDR0                           _SFR_MEM8(0x7E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR0 {
-        unsigned int adc0d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc1d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc2d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc3d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc4d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc5d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc6d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc7d : 1;	/* Disable ADC7:0 Digital Input */
-};
-
-#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR0 */
-
-#define ADC0D                           0
-#define ADC1D                           1
-#define ADC2D                           2
-#define ADC3D                           3
-#define ADC4D                           4
-#define ADC5D                           5
-#define ADC6D                           6
-#define ADC7D                           7
-
-/* Digital Input Disable Register 1 */
-#define DIDR1                           _SFR_MEM8(0x7F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR1 {
-        unsigned int ain0d : 1;	/* AIN0 Digital Input Disable */
-        unsigned int ain1d : 1;	/* AIN1 Digital Input Disable */
-        unsigned int : 6;
-};
-
-#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR1 */
-
-#define AIN0D                           0
-#define AIN1D                           1
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A                          _SFR_MEM8(0x80)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1A {
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int com1c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com1b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com1a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1A */
-
-#define WGM10                           0
-#define WGM11                           1
-#define COM1C0                          2
-#define COM1C1                          3
-#define COM1B0                          4
-#define COM1B1                          5
-#define COM1A0                          6
-#define COM1A1                          7
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B                          _SFR_MEM8(0x81)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1B {
-        unsigned int cs1 : 3;	/* Clock Select */
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices1 : 1;	/* Input Capture 1 Edge Select */
-        unsigned int icnc1 : 1;	/* Input Capture 1 Noise Canceller */
-};
-
-#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1B */
-
-#define CS10                            0
-#define CS11                            1
-#define CS12                            2
-#define WGM12                           3
-#define WGM13                           4
-#define ICES1                           6
-#define ICNC1                           7
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C                          _SFR_MEM8(0x82)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1C {
-        unsigned int : 5;
-        unsigned int foc1c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc1b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc1a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1C */
-
-#define FOC1C                           5
-#define FOC1B                           6
-#define FOC1A                           7
-
-/* Timer/Counter1  Bytes */
-#define TCNT1                           _SFR_MEM16(0x84)
-#define TCNT1L                          _SFR_MEM8(0x84)
-#define TCNT1H                          _SFR_MEM8(0x85)
-
-/* Timer/Counter1 Input Capture Register  Bytes */
-#define ICR1                            _SFR_MEM16(0x86)
-#define ICR1L                           _SFR_MEM8(0x86)
-#define ICR1H                           _SFR_MEM8(0x87)
-
-/* Timer/Counter1 Output Compare Register A  Bytes */
-#define OCR1A                           _SFR_MEM16(0x88)
-#define OCR1AL                          _SFR_MEM8(0x88)
-#define OCR1AH                          _SFR_MEM8(0x89)
-
-/* Timer/Counter1 Output Compare Register B  Bytes */
-#define OCR1B                           _SFR_MEM16(0x8A)
-#define OCR1BL                          _SFR_MEM8(0x8A)
-#define OCR1BH                          _SFR_MEM8(0x8B)
-
-/* Timer/Counter1 Output Compare Register C  Bytes */
-#define OCR1C                           _SFR_MEM16(0x8C)
-#define OCR1CL                          _SFR_MEM8(0x8C)
-#define OCR1CH                          _SFR_MEM8(0x8D)
-
-/* Timer/Counter3 Control Register A */
-#define TCCR3A                          _SFR_MEM8(0x90)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3A {
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int com3c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com3b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com3a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3A */
-
-#define WGM30                           0
-#define WGM31                           1
-#define COM3C0                          2
-#define COM3C1                          3
-#define COM3B0                          4
-#define COM3B1                          5
-#define COM3A0                          6
-#define COM3A1                          7
-
-/* Timer/Counter3 Control Register B */
-#define TCCR3B                          _SFR_MEM8(0x91)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3B {
-        unsigned int cs3 : 3;	/* Clock Select */
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices3 : 1;	/* Input Capture 3 Edge Select */
-        unsigned int icnc3 : 1;	/* Input Capture 3 Noise Canceller */
-};
-
-#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3B */
-
-#define CS30                            0
-#define CS31                            1
-#define CS32                            2
-#define WGM32                           3
-#define WGM33                           4
-#define ICES3                           6
-#define ICNC3                           7
-
-/* Timer/Counter3 Control Register C */
-#define TCCR3C                          _SFR_MEM8(0x92)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3C {
-        unsigned int : 5;
-        unsigned int foc3c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc3b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc3a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3C */
-
-#define FOC3C                           5
-#define FOC3B                           6
-#define FOC3A                           7
-
-/* Timer/Counter3  Bytes */
-#define TCNT3                           _SFR_MEM16(0x94)
-#define TCNT3L                          _SFR_MEM8(0x94)
-#define TCNT3H                          _SFR_MEM8(0x95)
-
-/* Timer/Counter3 Input Capture Register  Bytes */
-#define ICR3                            _SFR_MEM16(0x96)
-#define ICR3L                           _SFR_MEM8(0x96)
-#define ICR3H                           _SFR_MEM8(0x97)
-
-/* Timer/Counter3 Output Compare Register A  Bytes */
-#define OCR3A                           _SFR_MEM16(0x98)
-#define OCR3AL                          _SFR_MEM8(0x98)
-#define OCR3AH                          _SFR_MEM8(0x99)
-
-/* Timer/Counter3 Output Compare Register B  Bytes */
-#define OCR3B                           _SFR_MEM16(0x9A)
-#define OCR3BL                          _SFR_MEM8(0x9A)
-#define OCR3BH                          _SFR_MEM8(0x9B)
-
-/* Timer/Counter3 Output Compare Register C  Bytes */
-#define OCR3C                           _SFR_MEM16(0x9C)
-#define OCR3CL                          _SFR_MEM8(0x9C)
-#define OCR3CH                          _SFR_MEM8(0x9D)
-
-/* Timer/Counter4 Control Register A */
-#define TCCR4A                          _SFR_MEM8(0xA0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4A {
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int com4c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com4b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com4a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4A */
-
-#define WGM40                           0
-#define WGM41                           1
-#define COM4C0                          2
-#define COM4C1                          3
-#define COM4B0                          4
-#define COM4B1                          5
-#define COM4A0                          6
-#define COM4A1                          7
-
-/* Timer/Counter4 Control Register B */
-#define TCCR4B                          _SFR_MEM8(0xA1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4B {
-        unsigned int cs4 : 3;	/* Clock Select */
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices4 : 1;	/* Input Capture 4 Edge Select */
-        unsigned int icnc4 : 1;	/* Input Capture 4 Noise Canceller */
-};
-
-#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4B */
-
-#define CS40                            0
-#define CS41                            1
-#define CS42                            2
-#define WGM42                           3
-#define WGM43                           4
-#define ICES4                           6
-#define ICNC4                           7
-
-/* Timer/Counter4 Control Register C */
-#define TCCR4C                          _SFR_MEM8(0xA2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4C {
-        unsigned int : 5;
-        unsigned int foc4c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc4b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc4a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4C */
-
-#define FOC4C                           5
-#define FOC4B                           6
-#define FOC4A                           7
-
-/* Timer/Counter4  Bytes */
-#define TCNT4                           _SFR_MEM16(0xA4)
-#define TCNT4L                          _SFR_MEM8(0xA4)
-#define TCNT4H                          _SFR_MEM8(0xA5)
-
-/* Timer/Counter4 Input Capture Register  Bytes */
-#define ICR4                            _SFR_MEM16(0xA6)
-#define ICR4L                           _SFR_MEM8(0xA6)
-#define ICR4H                           _SFR_MEM8(0xA7)
-
-/* Timer/Counter4 Output Compare Register A  Bytes */
-#define OCR4A                           _SFR_MEM16(0xA8)
-#define OCR4AL                          _SFR_MEM8(0xA8)
-#define OCR4AH                          _SFR_MEM8(0xA9)
-
-/* Timer/Counter4 Output Compare Register B  Bytes */
-#define OCR4B                           _SFR_MEM16(0xAA)
-#define OCR4BL                          _SFR_MEM8(0xAA)
-#define OCR4BH                          _SFR_MEM8(0xAB)
-
-/* Timer/Counter4 Output Compare Register C  Bytes */
-#define OCR4C                           _SFR_MEM16(0xAC)
-#define OCR4CL                          _SFR_MEM8(0xAC)
-#define OCR4CH                          _SFR_MEM8(0xAD)
-
-/* Timer/Counter2 Control Register A */
-#define TCCR2A                          _SFR_MEM8(0xB0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2A {
-        unsigned int wgm2 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com2b : 2;	/* Compare Match Output B Mode */
-        unsigned int com2a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2A */
-
-#define WGM20                           0
-#define WGM21                           1
-#define COM2B0                          4
-#define COM2B1                          5
-#define COM2A0                          6
-#define COM2A1                          7
-
-/* Timer/Counter2 Control Register B */
-#define TCCR2B                          _SFR_MEM8(0xB1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2B {
-        unsigned int cs2 : 3;	/* Clock Select */
-        unsigned int wgm22 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc2b : 1;	/* Force Output Compare B */
-        unsigned int foc2a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2B */
-
-#define CS20                            0
-#define CS21                            1
-#define CS22                            2
-#define WGM22                           3
-#define FOC2B                           6
-#define FOC2A                           7
-
-/* Timer/Counter2 */
-#define TCNT2                           _SFR_MEM8(0xB2)
-
-  /* TCNT2 */
-
-#define TCNT20                          0
-#define TCNT21                          1
-#define TCNT22                          2
-#define TCNT23                          3
-#define TCNT24                          4
-#define TCNT25                          5
-#define TCNT26                          6
-#define TCNT27                          7
-
-/* Timer/Counter2 Output Compare Register A */
-#define OCR2A                           _SFR_MEM8(0xB3)
-
-  /* OCR2A */
-
-#define OCR2A0                          0
-#define OCR2A1                          1
-#define OCR2A2                          2
-#define OCR2A3                          3
-#define OCR2A4                          4
-#define OCR2A5                          5
-#define OCR2A6                          6
-#define OCR2A7                          7
-
-/* Timer/Counter2 Output Compare Register B */
-#define OCR2B                           _SFR_MEM8(0xB4)
-
-  /* OCR2B */
-
-#define OCR2B0                          0
-#define OCR2B1                          1
-#define OCR2B2                          2
-#define OCR2B3                          3
-#define OCR2B4                          4
-#define OCR2B5                          5
-#define OCR2B6                          6
-#define OCR2B7                          7
-
-/* Asynchronous Status Register */
-#define ASSR                            _SFR_MEM8(0xB6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ASSR {
-        unsigned int tcr2bub : 1;	/* Timer/Counter2 Control Register B Update Busy */
-        unsigned int tcr2aub : 1;	/* Timer/Counter2 Control Register A Update Busy */
-        unsigned int ocr2bub : 1;	/* Timer/Counter2 Output Compare Register B Update Busy */
-        unsigned int ocr2aub : 1;	/* Timer/Counter2 Output Compare Register A Update Busy */
-        unsigned int tcn2ub : 1;	/* Timer/Counter2 Update Busy */
-        unsigned int as2 : 1;	/* Timer/Counter2 Asynchronous Mode */
-        unsigned int exclk : 1;	/* Enable External Clock Input */
-        unsigned int exclkamr : 1;	/* Enable External Clock Input for AMR */
-};
-
-#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ASSR */
-
-#define TCR2BUB                         0
-#define TCR2AUB                         1
-#define OCR2BUB                         2
-#define OCR2AUB                         3
-#define TCN2UB                          4
-#define AS2                             5
-#define EXCLK                           6
-#define EXCLKAMR                        7
-
-/* TWI Bit Rate Register */
-#define TWBR                            _SFR_MEM8(0xB8)
-
-  /* TWBR */
-
-#define TWBR0                           0
-#define TWBR1                           1
-#define TWBR2                           2
-#define TWBR3                           3
-#define TWBR4                           4
-#define TWBR5                           5
-#define TWBR6                           6
-#define TWBR7                           7
-
-/* TWI Status Register */
-#define TWSR                            _SFR_MEM8(0xB9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWSR {
-        unsigned int twps : 2;	/* TWI Prescaler Bits */
-        unsigned int : 1;
-        unsigned int tws : 5;	/* TWI Status */
-};
-
-#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWSR */
-
-#define TWPS0                           0
-#define TWPS1                           1
-#define TWS3                            3
-#define TWS4                            4
-#define TWS5                            5
-#define TWS6                            6
-#define TWS7                            7
-
-/* TWI (Slave) Address Register */
-#define TWAR                            _SFR_MEM8(0xBA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAR {
-        unsigned int twgce : 1;	/* TWI General Call Recognition Enable Bit */
-        unsigned int twa : 7;	/* TWI (Slave) Address */
-};
-
-#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAR */
-
-#define TWGCE                           0
-#define TWA0                            1
-#define TWA1                            2
-#define TWA2                            3
-#define TWA3                            4
-#define TWA4                            5
-#define TWA5                            6
-#define TWA6                            7
-
-/* TWI Data Register */
-#define TWDR                            _SFR_MEM8(0xBB)
-
-  /* TWDR */
-
-#define TWD0                            0
-#define TWD1                            1
-#define TWD2                            2
-#define TWD3                            3
-#define TWD4                            4
-#define TWD5                            5
-#define TWD6                            6
-#define TWD7                            7
-
-/* TWI Control Register */
-#define TWCR                            _SFR_MEM8(0xBC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWCR {
-        unsigned int twie : 1;	/* TWI Interrupt Enable */
-        unsigned int : 1;
-        unsigned int twen : 1;	/* TWI Enable Bit */
-        unsigned int twwc : 1;	/* TWI Write Collision Flag */
-        unsigned int twsto : 1;	/* TWI STOP Condition Bit */
-        unsigned int twsta : 1;	/* TWI START Condition Bit */
-        unsigned int twea : 1;	/* TWI Enable Acknowledge Bit */
-        unsigned int twint : 1;	/* TWI Interrupt Flag */
-};
-
-#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWCR */
-
-#define TWIE                            0
-#define TWEN                            2
-#define TWWC                            3
-#define TWSTO                           4
-#define TWSTA                           5
-#define TWEA                            6
-#define TWINT                           7
-
-/* TWI (Slave) Address Mask Register */
-#define TWAMR                           _SFR_MEM8(0xBD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAMR {
-        unsigned int : 1;
-        unsigned int twam : 7;	/* TWI Address Mask */
-};
-
-#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAMR */
-
-#define TWAM0                           1
-#define TWAMR0                          1
-#define TWAM1                           2
-#define TWAMR1                          2
-#define TWAM2                           3
-#define TWAMR2                          3
-#define TWAM3                           4
-#define TWAMR3                          4
-#define TWAM4                           5
-#define TWAMR4                          5
-#define TWAM5                           6
-#define TWAMR5                          6
-#define TWAM6                           7
-#define TWAMR6                          7
-
-/* Transceiver Interrupt Enable Register 1 */
-#define IRQ_MASK1                       _SFR_MEM8(0xBE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK1 {
-        unsigned int tx_start_en : 1;	/* Transmit Start Interrupt enable */
-        unsigned int maf_0_ami_en : 1;	/* Address Match Interrupt enable Address filter 0 */
-        unsigned int maf_1_ami_en : 1;	/* Address Match Interrupt enable Address filter 1 */
-        unsigned int maf_2_ami_en : 1;	/* Address Match Interrupt enable Address filter 2 */
-        unsigned int maf_3_ami_en : 1;	/* Address Match Interrupt enable Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_MASK1_struct _SFR_MEM8_STRUCT(0xbe, struct __reg_IRQ_MASK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK1 */
-
-#define TX_START_EN                     0
-#define MAF_0_AMI_EN                    1
-#define MAF_1_AMI_EN                    2
-#define MAF_2_AMI_EN                    3
-#define MAF_3_AMI_EN                    4
-
-/* Transceiver Interrupt Status Register 1 */
-#define IRQ_STATUS1                     _SFR_MEM8(0xBF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS1 {
-        unsigned int tx_start : 1;	/* Transmit Start Interrupt Status */
-        unsigned int maf_0_ami : 1;	/* Address Match Interrupt Status Address filter 0 */
-        unsigned int maf_1_ami : 1;	/* Address Match Interrupt Status Address filter 1 */
-        unsigned int maf_2_ami : 1;	/* Address Match Interrupt Status Address filter 2 */
-        unsigned int maf_3_ami : 1;	/* Address Match Interrupt Status Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_STATUS1_struct _SFR_MEM8_STRUCT(0xbf, struct __reg_IRQ_STATUS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS1 */
-
-#define TX_START                        0
-#define MAF_0_AMI                       1
-#define MAF_1_AMI                       2
-#define MAF_2_AMI                       3
-#define MAF_3_AMI                       4
-
-/* USART0 Control and Status Register A */
-#define UCSR0A                          _SFR_MEM8(0xC0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0A {
-        unsigned int mpcm0 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x0 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe0 : 1;	/* USART Parity Error */
-        unsigned int dor0 : 1;	/* Data OverRun */
-        unsigned int fe0 : 1;	/* Frame Error */
-        unsigned int udre0 : 1;	/* USART Data Register Empty */
-        unsigned int txc0 : 1;	/* USART Transmit Complete */
-        unsigned int rxc0 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0A */
-
-#define MPCM0                           0
-#define U2X0                            1
-#define UPE0                            2
-#define DOR0                            3
-#define FE0                             4
-#define UDRE0                           5
-#define TXC0                            6
-#define RXC0                            7
-
-/* USART0 Control and Status Register B */
-#define UCSR0B                          _SFR_MEM8(0xC1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0B {
-        unsigned int txb80 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb80 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz02 : 1;	/* Character Size */
-        unsigned int txen0 : 1;	/* Transmitter Enable */
-        unsigned int rxen0 : 1;	/* Receiver Enable */
-        unsigned int udrie0 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie0 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie0 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0B */
-
-#define TXB80                           0
-#define RXB80                           1
-#define UCSZ02                          2
-#define TXEN0                           3
-#define RXEN0                           4
-#define UDRIE0                          5
-#define TXCIE0                          6
-#define RXCIE0                          7
-
-/* USART0 Control and Status Register C */
-#define UCSR0C                          _SFR_MEM8(0xC2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0C {
-        unsigned int ucpol0 : 1;	/* Clock Polarity */
-        unsigned int ucsz0 : 2;	/* Character Size */
-        unsigned int ucpha0 : 1;	/* Clock Phase */
-        unsigned int udord0 : 1;	/* Data Order */
-        unsigned int usbs0 : 1;	/* Stop Bit Select */
-        unsigned int upm0 : 2;	/* Parity Mode */
-        unsigned int umsel0 : 2;	/* USART Mode Select */
-};
-
-#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0C */
-
-#define UCPOL0                          0
-#define UCPHA0                          1
-#define UCPHA0                          1
-#define UCSZ00                          1
-#define UDORD0                          2
-#define UDORD0                          2
-#define UCSZ01                          2
-#define USBS0                           3
-#define UPM00                           4
-#define UPM01                           5
-#define UMSEL00                         6
-#define UMSEL0                          6
-#define UMSEL01                         7
-#define UMSEL1                          7
-
-/* USART0 Baud Rate Register  Bytes */
-#define UBRR0                           _SFR_MEM16(0xC4)
-#define UBRR0L                          _SFR_MEM8(0xC4)
-#define UBRR0H                          _SFR_MEM8(0xC5)
-
-/* USART0 I/O Data Register */
-#define UDR0                            _SFR_MEM8(0xC6)
-
-  /* UDR0 */
-
-#define UDR00                           0
-#define UDR01                           1
-#define UDR02                           2
-#define UDR03                           3
-#define UDR04                           4
-#define UDR05                           5
-#define UDR06                           6
-#define UDR07                           7
-
-/* USART1 Control and Status Register A */
-#define UCSR1A                          _SFR_MEM8(0xC8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1A {
-        unsigned int mpcm1 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x1 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe1 : 1;	/* USART Parity Error */
-        unsigned int dor1 : 1;	/* Data OverRun */
-        unsigned int fe1 : 1;	/* Frame Error */
-        unsigned int udre1 : 1;	/* USART Data Register Empty */
-        unsigned int txc1 : 1;	/* USART Transmit Complete */
-        unsigned int rxc1 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1A */
-
-#define MPCM1                           0
-#define U2X1                            1
-#define UPE1                            2
-#define DOR1                            3
-#define FE1                             4
-#define UDRE1                           5
-#define TXC1                            6
-#define RXC1                            7
-
-/* USART1 Control and Status Register B */
-#define UCSR1B                          _SFR_MEM8(0xC9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1B {
-        unsigned int txb81 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb81 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz12 : 1;	/* Character Size */
-        unsigned int txen1 : 1;	/* Transmitter Enable */
-        unsigned int rxen1 : 1;	/* Receiver Enable */
-        unsigned int udrie1 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie1 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie1 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1B */
-
-#define TXB81                           0
-#define RXB81                           1
-#define UCSZ12                          2
-#define TXEN1                           3
-#define RXEN1                           4
-#define UDRIE1                          5
-#define TXCIE1                          6
-#define RXCIE1                          7
-
-/* USART1 Control and Status Register C */
-#define UCSR1C                          _SFR_MEM8(0xCA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1C {
-        unsigned int ucpol1 : 1;	/* Clock Polarity */
-        unsigned int ucsz1 : 2;	/* Character Size */
-        unsigned int ucpha1 : 1;	/* Clock Phase */
-        unsigned int udord1 : 1;	/* Data Order */
-        unsigned int usbs1 : 1;	/* Stop Bit Select */
-        unsigned int upm1 : 2;	/* Parity Mode */
-        unsigned int umsel1 : 2;	/* USART Mode Select */
-};
-
-#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1C */
-
-#define UCPOL1                          0
-#define UCPHA1                          1
-#define UCPHA1                          1
-#define UCSZ10                          1
-#define UDORD1                          2
-#define UDORD1                          2
-#define UCSZ11                          2
-#define USBS1                           3
-#define UPM10                           4
-#define UPM11                           5
-#define UMSEL10                         6
-#define UMSEL11                         7
-
-/* USART1 Baud Rate Register  Bytes */
-#define UBRR1                           _SFR_MEM16(0xCC)
-#define UBRR1L                          _SFR_MEM8(0xCC)
-#define UBRR1H                          _SFR_MEM8(0xCD)
-
-/* USART1 I/O Data Register */
-#define UDR1                            _SFR_MEM8(0xCE)
-
-  /* UDR1 */
-
-#define UDR10                           0
-#define UDR11                           1
-#define UDR12                           2
-#define UDR13                           3
-#define UDR14                           4
-#define UDR15                           5
-#define UDR16                           6
-#define UDR17                           7
-
-/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-#define SCRSTRLL                        _SFR_MEM8(0xD7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLL {
-        unsigned int scrstrll : 8;	/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-};
-
-#define SCRSTRLL_struct _SFR_MEM8_STRUCT(0xd7, struct __reg_SCRSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLL */
-
-#define SCRSTRLL0                       0
-#define SCRSTRLL1                       1
-#define SCRSTRLL2                       2
-#define SCRSTRLL3                       3
-#define SCRSTRLL4                       4
-#define SCRSTRLL5                       5
-#define SCRSTRLL6                       6
-#define SCRSTRLL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-#define SCRSTRLH                        _SFR_MEM8(0xD8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLH {
-        unsigned int scrstrlh : 8;	/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-};
-
-#define SCRSTRLH_struct _SFR_MEM8_STRUCT(0xd8, struct __reg_SCRSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLH */
-
-#define SCRSTRLH0                       0
-#define SCRSTRLH1                       1
-#define SCRSTRLH2                       2
-#define SCRSTRLH3                       3
-#define SCRSTRLH4                       4
-#define SCRSTRLH5                       5
-#define SCRSTRLH6                       6
-#define SCRSTRLH7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-#define SCRSTRHL                        _SFR_MEM8(0xD9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHL {
-        unsigned int scrstrhl : 8;	/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-};
-
-#define SCRSTRHL_struct _SFR_MEM8_STRUCT(0xd9, struct __reg_SCRSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHL */
-
-#define SCRSTRHL0                       0
-#define SCRSTRHL1                       1
-#define SCRSTRHL2                       2
-#define SCRSTRHL3                       3
-#define SCRSTRHL4                       4
-#define SCRSTRHL5                       5
-#define SCRSTRHL6                       6
-#define SCRSTRHL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-#define SCRSTRHH                        _SFR_MEM8(0xDA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHH {
-        unsigned int scrstrhh : 8;	/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-};
-
-#define SCRSTRHH_struct _SFR_MEM8_STRUCT(0xda, struct __reg_SCRSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHH */
-
-#define SCRSTRHH0                       0
-#define SCRSTRHH1                       1
-#define SCRSTRHH2                       2
-#define SCRSTRHH3                       3
-#define SCRSTRHH4                       4
-#define SCRSTRHH5                       5
-#define SCRSTRHH6                       6
-#define SCRSTRHH7                       7
-
-/* Symbol Counter Compare Source Register */
-#define SCCSR                           _SFR_MEM8(0xDB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCSR {
-        unsigned int sccs1 : 2;	/* Symbol Counter Compare Source select register for Compare Units */
-        unsigned int sccs2 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 2 */
-        unsigned int sccs3 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 3 */
-        unsigned int : 2;
-};
-
-#define SCCSR_struct _SFR_MEM8_STRUCT(0xdb, struct __reg_SCCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCSR */
-
-#define SCCS10                          0
-#define SCCS11                          1
-#define SCCS20                          2
-#define SCCS21                          3
-#define SCCS30                          4
-#define SCCS31                          5
-
-/* Symbol Counter Control Register 0 */
-#define SCCR0                           _SFR_MEM8(0xDC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR0 {
-        unsigned int sccmp : 3;	/* Symbol Counter Compare Unit 3 Mode select */
-        unsigned int sctse : 1;	/* Symbol Counter Automatic Timestamping enable */
-        unsigned int sccksel : 1;	/* Symbol Counter Clock Source select */
-        unsigned int scen : 1;	/* Symbol Counter enable */
-        unsigned int scmbts : 1;	/* Manual Beacon Timestamp */
-        unsigned int scres : 1;	/* Symbol Counter Synchronization */
-};
-
-#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR0 */
-
-#define SCCMP1                          0
-#define SCCMP2                          1
-#define SCCMP3                          2
-#define SCTSE                           3
-#define SCCKSEL                         4
-#define SCEN                            5
-#define SCMBTS                          6
-#define SCRES                           7
-
-/* Symbol Counter Control Register 1 */
-#define SCCR1                           _SFR_MEM8(0xDD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR1 {
-        unsigned int scenbo : 1;	/* Backoff Slot Counter enable */
-        unsigned int sceeclk : 1;	/* Enable External Clock Source on PG2 */
-        unsigned int scckdiv : 3;	/* Clock divider for synchronous clock source (16MHz Transceiver Clock) */
-        unsigned int scbtsm : 1;	/* Symbol Counter Beacon Timestamp Mask Register */
-        unsigned int : 2;
-};
-
-#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR1 */
-
-#define SCENBO                          0
-#define SCEECLK                         1
-#define SCCKDIV0                        2
-#define SCCKDIV1                        3
-#define SCCKDIV2                        4
-#define SCBTSM                          5
-
-/* Symbol Counter Status Register */
-#define SCSR                            _SFR_MEM8(0xDE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCSR {
-        unsigned int scbsy : 1;	/* Symbol Counter busy */
-        unsigned int : 7;
-};
-
-#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCSR */
-
-#define SCBSY                           0
-
-/* Symbol Counter Interrupt Mask Register */
-#define SCIRQM                          _SFR_MEM8(0xDF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQM {
-        unsigned int irqmcp : 3;	/* Symbol Counter Compare Match 3 IRQ enable */
-        unsigned int irqmof : 1;	/* Symbol Counter Overflow IRQ enable */
-        unsigned int irqmbo : 1;	/* Backoff Slot Counter IRQ enable */
-        unsigned int : 3;
-};
-
-#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQM */
-
-#define IRQMCP1                         0
-#define IRQMCP2                         1
-#define IRQMCP3                         2
-#define IRQMOF                          3
-#define IRQMBO                          4
-
-/* Symbol Counter Interrupt Status Register */
-#define SCIRQS                          _SFR_MEM8(0xE0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQS {
-        unsigned int irqscp : 3;	/* Compare Unit 3 Compare Match IRQ */
-        unsigned int irqsof : 1;	/* Symbol Counter Overflow IRQ */
-        unsigned int irqsbo : 1;	/* Backoff Slot Counter IRQ */
-        unsigned int : 3;
-};
-
-#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQS */
-
-#define IRQSCP1                         0
-#define IRQSCP2                         1
-#define IRQSCP3                         2
-#define IRQSOF                          3
-#define IRQSBO                          4
-
-/* Symbol Counter Register LL-Byte */
-#define SCCNTLL                         _SFR_MEM8(0xE1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLL {
-        unsigned int sccntll : 8;	/* Symbol Counter Register LL-Byte */
-};
-
-#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLL */
-
-#define SCCNTLL0                        0
-#define SCCNTLL1                        1
-#define SCCNTLL2                        2
-#define SCCNTLL3                        3
-#define SCCNTLL4                        4
-#define SCCNTLL5                        5
-#define SCCNTLL6                        6
-#define SCCNTLL7                        7
-
-/* Symbol Counter Register LH-Byte */
-#define SCCNTLH                         _SFR_MEM8(0xE2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLH {
-        unsigned int sccntlh : 8;	/* Symbol Counter Register LH-Byte */
-};
-
-#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLH */
-
-#define SCCNTLH0                        0
-#define SCCNTLH1                        1
-#define SCCNTLH2                        2
-#define SCCNTLH3                        3
-#define SCCNTLH4                        4
-#define SCCNTLH5                        5
-#define SCCNTLH6                        6
-#define SCCNTLH7                        7
-
-/* Symbol Counter Register HL-Byte */
-#define SCCNTHL                         _SFR_MEM8(0xE3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHL {
-        unsigned int sccnthl : 8;	/* Symbol Counter Register HL-Byte */
-};
-
-#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHL */
-
-#define SCCNTHL0                        0
-#define SCCNTHL1                        1
-#define SCCNTHL2                        2
-#define SCCNTHL3                        3
-#define SCCNTHL4                        4
-#define SCCNTHL5                        5
-#define SCCNTHL6                        6
-#define SCCNTHL7                        7
-
-/* Symbol Counter Register HH-Byte */
-#define SCCNTHH                         _SFR_MEM8(0xE4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHH {
-        unsigned int sccnthh : 8;	/* Symbol Counter Register HH-Byte */
-};
-
-#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHH */
-
-#define SCCNTHH0                        0
-#define SCCNTHH1                        1
-#define SCCNTHH2                        2
-#define SCCNTHH3                        3
-#define SCCNTHH4                        4
-#define SCCNTHH5                        5
-#define SCCNTHH6                        6
-#define SCCNTHH7                        7
-
-/* Symbol Counter Beacon Timestamp Register LL-Byte */
-#define SCBTSRLL                        _SFR_MEM8(0xE5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLL {
-        unsigned int scbtsrll : 8;	/* Symbol Counter Beacon Timestamp Register LL-Byte */
-};
-
-#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLL */
-
-#define SCBTSRLL0                       0
-#define SCBTSRLL1                       1
-#define SCBTSRLL2                       2
-#define SCBTSRLL3                       3
-#define SCBTSRLL4                       4
-#define SCBTSRLL5                       5
-#define SCBTSRLL6                       6
-#define SCBTSRLL7                       7
-
-/* Symbol Counter Beacon Timestamp Register LH-Byte */
-#define SCBTSRLH                        _SFR_MEM8(0xE6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLH {
-        unsigned int scbtsrlh : 8;	/* Symbol Counter Beacon Timestamp Register LH-Byte */
-};
-
-#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLH */
-
-#define SCBTSRLH0                       0
-#define SCBTSRLH1                       1
-#define SCBTSRLH2                       2
-#define SCBTSRLH3                       3
-#define SCBTSRLH4                       4
-#define SCBTSRLH5                       5
-#define SCBTSRLH6                       6
-#define SCBTSRLH7                       7
-
-/* Symbol Counter Beacon Timestamp Register HL-Byte */
-#define SCBTSRHL                        _SFR_MEM8(0xE7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHL {
-        unsigned int scbtsrhl : 8;	/* Symbol Counter Beacon Timestamp Register HL-Byte */
-};
-
-#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHL */
-
-#define SCBTSRHL0                       0
-#define SCBTSRHL1                       1
-#define SCBTSRHL2                       2
-#define SCBTSRHL3                       3
-#define SCBTSRHL4                       4
-#define SCBTSRHL5                       5
-#define SCBTSRHL6                       6
-#define SCBTSRHL7                       7
-
-/* Symbol Counter Beacon Timestamp Register HH-Byte */
-#define SCBTSRHH                        _SFR_MEM8(0xE8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHH {
-        unsigned int scbtsrhh : 8;	/* Symbol Counter Beacon Timestamp Register HH-Byte */
-};
-
-#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHH */
-
-#define SCBTSRHH0                       0
-#define SCBTSRHH1                       1
-#define SCBTSRHH2                       2
-#define SCBTSRHH3                       3
-#define SCBTSRHH4                       4
-#define SCBTSRHH5                       5
-#define SCBTSRHH6                       6
-#define SCBTSRHH7                       7
-
-/* Symbol Counter Frame Timestamp Register LL-Byte */
-#define SCTSRLL                         _SFR_MEM8(0xE9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLL {
-        unsigned int sctsrll : 8;	/* Symbol Counter Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLL */
-
-#define SCTSRLL0                        0
-#define SCTSRLL1                        1
-#define SCTSRLL2                        2
-#define SCTSRLL3                        3
-#define SCTSRLL4                        4
-#define SCTSRLL5                        5
-#define SCTSRLL6                        6
-#define SCTSRLL7                        7
-
-/* Symbol Counter Frame Timestamp Register LH-Byte */
-#define SCTSRLH                         _SFR_MEM8(0xEA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLH {
-        unsigned int sctsrlh : 8;	/* Symbol Counter Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLH */
-
-#define SCTSRLH0                        0
-#define SCTSRLH1                        1
-#define SCTSRLH2                        2
-#define SCTSRLH3                        3
-#define SCTSRLH4                        4
-#define SCTSRLH5                        5
-#define SCTSRLH6                        6
-#define SCTSRLH7                        7
-
-/* Symbol Counter Frame Timestamp Register HL-Byte */
-#define SCTSRHL                         _SFR_MEM8(0xEB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHL {
-        unsigned int sctsrhl : 8;	/* Symbol Counter Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHL */
-
-#define SCTSRHL0                        0
-#define SCTSRHL1                        1
-#define SCTSRHL2                        2
-#define SCTSRHL3                        3
-#define SCTSRHL4                        4
-#define SCTSRHL5                        5
-#define SCTSRHL6                        6
-#define SCTSRHL7                        7
-
-/* Symbol Counter Frame Timestamp Register HH-Byte */
-#define SCTSRHH                         _SFR_MEM8(0xEC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHH {
-        unsigned int sctsrhh : 8;	/* Symbol Counter Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHH */
-
-#define SCTSRHH0                        0
-#define SCTSRHH1                        1
-#define SCTSRHH2                        2
-#define SCTSRHH3                        3
-#define SCTSRHH4                        4
-#define SCTSRHH5                        5
-#define SCTSRHH6                        6
-#define SCTSRHH7                        7
-
-/* Symbol Counter Output Compare Register 3 LL-Byte */
-#define SCOCR3LL                        _SFR_MEM8(0xED)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LL {
-        unsigned int scocr3ll : 8;	/* Symbol Counter Output Compare Register 3 LL-Byte */
-};
-
-#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LL */
-
-#define SCOCR3LL0                       0
-#define SCOCR3LL1                       1
-#define SCOCR3LL2                       2
-#define SCOCR3LL3                       3
-#define SCOCR3LL4                       4
-#define SCOCR3LL5                       5
-#define SCOCR3LL6                       6
-#define SCOCR3LL7                       7
-
-/* Symbol Counter Output Compare Register 3 LH-Byte */
-#define SCOCR3LH                        _SFR_MEM8(0xEE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LH {
-        unsigned int scocr3lh : 8;	/* Symbol Counter Output Compare Register 3 LH-Byte */
-};
-
-#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LH */
-
-#define SCOCR3LH0                       0
-#define SCOCR3LH1                       1
-#define SCOCR3LH2                       2
-#define SCOCR3LH3                       3
-#define SCOCR3LH4                       4
-#define SCOCR3LH5                       5
-#define SCOCR3LH6                       6
-#define SCOCR3LH7                       7
-
-/* Symbol Counter Output Compare Register 3 HL-Byte */
-#define SCOCR3HL                        _SFR_MEM8(0xEF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HL {
-        unsigned int scocr3hl : 8;	/* Symbol Counter Output Compare Register 3 HL-Byte */
-};
-
-#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HL */
-
-#define SCOCR3HL0                       0
-#define SCOCR3HL1                       1
-#define SCOCR3HL2                       2
-#define SCOCR3HL3                       3
-#define SCOCR3HL4                       4
-#define SCOCR3HL5                       5
-#define SCOCR3HL6                       6
-#define SCOCR3HL7                       7
-
-/* Symbol Counter Output Compare Register 3 HH-Byte */
-#define SCOCR3HH                        _SFR_MEM8(0xF0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HH {
-        unsigned int scocr3hh : 8;	/* Symbol Counter Output Compare Register 3 HH-Byte */
-};
-
-#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HH */
-
-#define SCOCR3HH0                       0
-#define SCOCR3HH1                       1
-#define SCOCR3HH2                       2
-#define SCOCR3HH3                       3
-#define SCOCR3HH4                       4
-#define SCOCR3HH5                       5
-#define SCOCR3HH6                       6
-#define SCOCR3HH7                       7
-
-/* Symbol Counter Output Compare Register 2 LL-Byte */
-#define SCOCR2LL                        _SFR_MEM8(0xF1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LL {
-        unsigned int scocr2ll : 8;	/* Symbol Counter Output Compare Register 2 LL-Byte */
-};
-
-#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LL */
-
-#define SCOCR2LL0                       0
-#define SCOCR2LL1                       1
-#define SCOCR2LL2                       2
-#define SCOCR2LL3                       3
-#define SCOCR2LL4                       4
-#define SCOCR2LL5                       5
-#define SCOCR2LL6                       6
-#define SCOCR2LL7                       7
-
-/* Symbol Counter Output Compare Register 2 LH-Byte */
-#define SCOCR2LH                        _SFR_MEM8(0xF2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LH {
-        unsigned int scocr2lh : 8;	/* Symbol Counter Output Compare Register 2 LH-Byte */
-};
-
-#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LH */
-
-#define SCOCR2LH0                       0
-#define SCOCR2LH1                       1
-#define SCOCR2LH2                       2
-#define SCOCR2LH3                       3
-#define SCOCR2LH4                       4
-#define SCOCR2LH5                       5
-#define SCOCR2LH6                       6
-#define SCOCR2LH7                       7
-
-/* Symbol Counter Output Compare Register 2 HL-Byte */
-#define SCOCR2HL                        _SFR_MEM8(0xF3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HL {
-        unsigned int scocr2hl : 8;	/* Symbol Counter Output Compare Register 2 HL-Byte */
-};
-
-#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HL */
-
-#define SCOCR2HL0                       0
-#define SCOCR2HL1                       1
-#define SCOCR2HL2                       2
-#define SCOCR2HL3                       3
-#define SCOCR2HL4                       4
-#define SCOCR2HL5                       5
-#define SCOCR2HL6                       6
-#define SCOCR2HL7                       7
-
-/* Symbol Counter Output Compare Register 2 HH-Byte */
-#define SCOCR2HH                        _SFR_MEM8(0xF4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HH {
-        unsigned int scocr2hh : 8;	/* Symbol Counter Output Compare Register 2 HH-Byte */
-};
-
-#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HH */
-
-#define SCOCR2HH0                       0
-#define SCOCR2HH1                       1
-#define SCOCR2HH2                       2
-#define SCOCR2HH3                       3
-#define SCOCR2HH4                       4
-#define SCOCR2HH5                       5
-#define SCOCR2HH6                       6
-#define SCOCR2HH7                       7
-
-/* Symbol Counter Output Compare Register 1 LL-Byte */
-#define SCOCR1LL                        _SFR_MEM8(0xF5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LL {
-        unsigned int scocr1ll : 8;	/* Symbol Counter Output Compare Register 1 LL-Byte */
-};
-
-#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LL */
-
-#define SCOCR1LL0                       0
-#define SCOCR1LL1                       1
-#define SCOCR1LL2                       2
-#define SCOCR1LL3                       3
-#define SCOCR1LL4                       4
-#define SCOCR1LL5                       5
-#define SCOCR1LL6                       6
-#define SCOCR1LL7                       7
-
-/* Symbol Counter Output Compare Register 1 LH-Byte */
-#define SCOCR1LH                        _SFR_MEM8(0xF6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LH {
-        unsigned int scocr1lh : 8;	/* Symbol Counter Output Compare Register 1 LH-Byte */
-};
-
-#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LH */
-
-#define SCOCR1LH0                       0
-#define SCOCR1LH1                       1
-#define SCOCR1LH2                       2
-#define SCOCR1LH3                       3
-#define SCOCR1LH4                       4
-#define SCOCR1LH5                       5
-#define SCOCR1LH6                       6
-#define SCOCR1LH7                       7
-
-/* Symbol Counter Output Compare Register 1 HL-Byte */
-#define SCOCR1HL                        _SFR_MEM8(0xF7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HL {
-        unsigned int scocr1hl : 8;	/* Symbol Counter Output Compare Register 1 HL-Byte */
-};
-
-#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HL */
-
-#define SCOCR1HL0                       0
-#define SCOCR1HL1                       1
-#define SCOCR1HL2                       2
-#define SCOCR1HL3                       3
-#define SCOCR1HL4                       4
-#define SCOCR1HL5                       5
-#define SCOCR1HL6                       6
-#define SCOCR1HL7                       7
-
-/* Symbol Counter Output Compare Register 1 HH-Byte */
-#define SCOCR1HH                        _SFR_MEM8(0xF8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HH {
-        unsigned int scocr1hh : 8;	/* Symbol Counter Output Compare Register 1 HH-Byte */
-};
-
-#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HH */
-
-#define SCOCR1HH0                       0
-#define SCOCR1HH1                       1
-#define SCOCR1HH2                       2
-#define SCOCR1HH3                       3
-#define SCOCR1HH4                       4
-#define SCOCR1HH5                       5
-#define SCOCR1HH6                       6
-#define SCOCR1HH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-#define SCTSTRLL                        _SFR_MEM8(0xF9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLL {
-        unsigned int sctstrll : 8;	/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSTRLL_struct _SFR_MEM8_STRUCT(0xf9, struct __reg_SCTSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLL */
-
-#define SCTSTRLL0                       0
-#define SCTSTRLL1                       1
-#define SCTSTRLL2                       2
-#define SCTSTRLL3                       3
-#define SCTSTRLL4                       4
-#define SCTSTRLL5                       5
-#define SCTSTRLL6                       6
-#define SCTSTRLL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-#define SCTSTRLH                        _SFR_MEM8(0xFA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLH {
-        unsigned int sctstrlh : 8;	/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSTRLH_struct _SFR_MEM8_STRUCT(0xfa, struct __reg_SCTSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLH */
-
-#define SCTSTRLH0                       0
-#define SCTSTRLH1                       1
-#define SCTSTRLH2                       2
-#define SCTSTRLH3                       3
-#define SCTSTRLH4                       4
-#define SCTSTRLH5                       5
-#define SCTSTRLH6                       6
-#define SCTSTRLH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-#define SCTSTRHL                        _SFR_MEM8(0xFB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHL {
-        unsigned int sctstrhl : 8;	/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSTRHL_struct _SFR_MEM8_STRUCT(0xfb, struct __reg_SCTSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHL */
-
-#define SCTSTRHL0                       0
-#define SCTSTRHL1                       1
-#define SCTSTRHL2                       2
-#define SCTSTRHL3                       3
-#define SCTSTRHL4                       4
-#define SCTSTRHL5                       5
-#define SCTSTRHL6                       6
-#define SCTSTRHL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-#define SCTSTRHH                        _SFR_MEM8(0xFC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHH {
-        unsigned int sctstrhh : 8;	/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSTRHH_struct _SFR_MEM8_STRUCT(0xfc, struct __reg_SCTSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHH */
-
-#define SCTSTRHH0                       0
-#define SCTSTRHH1                       1
-#define SCTSTRHH2                       2
-#define SCTSTRHH3                       3
-#define SCTSTRHH4                       4
-#define SCTSTRHH5                       5
-#define SCTSTRHH6                       6
-#define SCTSTRHH7                       7
-
-/* Multiple Address Filter Configuration Register 0 */
-#define MAFCR0                          _SFR_MEM8(0x10C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR0 {
-        unsigned int maf0en : 1;	/* Multiple Address Filter 0 Enable */
-        unsigned int maf1en : 1;	/* Multiple Address Filter 1 Enable */
-        unsigned int maf2en : 1;	/* Multiple Address Filter 2 Enable */
-        unsigned int maf3en : 1;	/* Multiple Address Filter 3 Enable */
-        unsigned int : 4;
-};
-
-#define MAFCR0_struct _SFR_MEM8_STRUCT(0x10c, struct __reg_MAFCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR0 */
-
-#define MAF0EN                          0
-#define MAF1EN                          1
-#define MAF2EN                          2
-#define MAF3EN                          3
-
-/* Multiple Address Filter Configuration Register 1 */
-#define MAFCR1                          _SFR_MEM8(0x10D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR1 {
-        unsigned int aack_0_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 0. */
-        unsigned int aack_0_set_pd : 1;	/* Set Data Pending bit for address filter 0. */
-        unsigned int aack_1_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 1. */
-        unsigned int aack_1_set_pd : 1;	/* Set Data Pending bit for address filter 1. */
-        unsigned int aack_2_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 2. */
-        unsigned int aack_2_set_pd : 1;	/* Set Data Pending bit for address filter 2. */
-        unsigned int aack_3_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 3. */
-        unsigned int aack_3_set_pd : 1;	/* Set Data Pending bit for address filter 3. */
-};
-
-#define MAFCR1_struct _SFR_MEM8_STRUCT(0x10d, struct __reg_MAFCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR1 */
-
-#define AACK_0_I_AM_COORD               0
-#define AACK_0_SET_PD                   1
-#define AACK_1_I_AM_COORD               2
-#define AACK_1_SET_PD                   3
-#define AACK_2_I_AM_COORD               4
-#define AACK_2_SET_PD                   5
-#define AACK_3_I_AM_COORD               6
-#define AACK_3_SET_PD                   7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) */
-#define MAFSA0L                         _SFR_MEM8(0x10E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0L {
-        unsigned int mafsa0l : 8;	/* MAC Short Address low Byte for Frame Filter 0 */
-};
-
-#define MAFSA0L_struct _SFR_MEM8_STRUCT(0x10e, struct __reg_MAFSA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0L */
-
-#define MAFSA0L0                        0
-#define MAFSA0L1                        1
-#define MAFSA0L2                        2
-#define MAFSA0L3                        3
-#define MAFSA0L4                        4
-#define MAFSA0L5                        5
-#define MAFSA0L6                        6
-#define MAFSA0L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) */
-#define MAFSA0H                         _SFR_MEM8(0x10F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0H {
-        unsigned int mafsa0h : 8;	/* MAC Short Address high Byte for Frame Filter 0 */
-};
-
-#define MAFSA0H_struct _SFR_MEM8_STRUCT(0x10f, struct __reg_MAFSA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0H */
-
-#define MAFSA0H0                        0
-#define MAFSA0H1                        1
-#define MAFSA0H2                        2
-#define MAFSA0H3                        3
-#define MAFSA0H4                        4
-#define MAFSA0H5                        5
-#define MAFSA0H6                        6
-#define MAFSA0H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) */
-#define MAFPA0L                         _SFR_MEM8(0x110)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0L {
-        unsigned int mafpa0l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 0 */
-};
-
-#define MAFPA0L_struct _SFR_MEM8_STRUCT(0x110, struct __reg_MAFPA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0L */
-
-#define MAFPA0L0                        0
-#define MAFPA0L1                        1
-#define MAFPA0L2                        2
-#define MAFPA0L3                        3
-#define MAFPA0L4                        4
-#define MAFPA0L5                        5
-#define MAFPA0L6                        6
-#define MAFPA0L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) */
-#define MAFPA0H                         _SFR_MEM8(0x111)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0H {
-        unsigned int mafpa0h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 0 */
-};
-
-#define MAFPA0H_struct _SFR_MEM8_STRUCT(0x111, struct __reg_MAFPA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0H */
-
-#define MAFPA0H0                        0
-#define MAFPA0H1                        1
-#define MAFPA0H2                        2
-#define MAFPA0H3                        3
-#define MAFPA0H4                        4
-#define MAFPA0H5                        5
-#define MAFPA0H6                        6
-#define MAFPA0H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) */
-#define MAFSA1L                         _SFR_MEM8(0x112)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1L {
-        unsigned int mafsa1l : 8;	/* MAC Short Address low Byte for Frame Filter 1 */
-};
-
-#define MAFSA1L_struct _SFR_MEM8_STRUCT(0x112, struct __reg_MAFSA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1L */
-
-#define MAFSA1L0                        0
-#define MAFSA1L1                        1
-#define MAFSA1L2                        2
-#define MAFSA1L3                        3
-#define MAFSA1L4                        4
-#define MAFSA1L5                        5
-#define MAFSA1L6                        6
-#define MAFSA1L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) */
-#define MAFSA1H                         _SFR_MEM8(0x113)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1H {
-        unsigned int mafsa1h : 8;	/* MAC Short Address high Byte for Frame Filter 1 */
-};
-
-#define MAFSA1H_struct _SFR_MEM8_STRUCT(0x113, struct __reg_MAFSA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1H */
-
-#define MAFSA1H0                        0
-#define MAFSA1H1                        1
-#define MAFSA1H2                        2
-#define MAFSA1H3                        3
-#define MAFSA1H4                        4
-#define MAFSA1H5                        5
-#define MAFSA1H6                        6
-#define MAFSA1H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) */
-#define MAFPA1L                         _SFR_MEM8(0x114)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1L {
-        unsigned int mafpa1l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 1 */
-};
-
-#define MAFPA1L_struct _SFR_MEM8_STRUCT(0x114, struct __reg_MAFPA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1L */
-
-#define MAFPA1L0                        0
-#define MAFPA1L1                        1
-#define MAFPA1L2                        2
-#define MAFPA1L3                        3
-#define MAFPA1L4                        4
-#define MAFPA1L5                        5
-#define MAFPA1L6                        6
-#define MAFPA1L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) */
-#define MAFPA1H                         _SFR_MEM8(0x115)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1H {
-        unsigned int mafpa1h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 1 */
-};
-
-#define MAFPA1H_struct _SFR_MEM8_STRUCT(0x115, struct __reg_MAFPA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1H */
-
-#define MAFPA1H0                        0
-#define MAFPA1H1                        1
-#define MAFPA1H2                        2
-#define MAFPA1H3                        3
-#define MAFPA1H4                        4
-#define MAFPA1H5                        5
-#define MAFPA1H6                        6
-#define MAFPA1H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) */
-#define MAFSA2L                         _SFR_MEM8(0x116)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2L {
-        unsigned int mafsa2l : 8;	/* MAC Short Address low Byte for Frame Filter 2 */
-};
-
-#define MAFSA2L_struct _SFR_MEM8_STRUCT(0x116, struct __reg_MAFSA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2L */
-
-#define MAFSA2L0                        0
-#define MAFSA2L1                        1
-#define MAFSA2L2                        2
-#define MAFSA2L3                        3
-#define MAFSA2L4                        4
-#define MAFSA2L5                        5
-#define MAFSA2L6                        6
-#define MAFSA2L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) */
-#define MAFSA2H                         _SFR_MEM8(0x117)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2H {
-        unsigned int mafsa2h : 8;	/* MAC Short Address high Byte for Frame Filter 2 */
-};
-
-#define MAFSA2H_struct _SFR_MEM8_STRUCT(0x117, struct __reg_MAFSA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2H */
-
-#define MAFSA2H0                        0
-#define MAFSA2H1                        1
-#define MAFSA2H2                        2
-#define MAFSA2H3                        3
-#define MAFSA2H4                        4
-#define MAFSA2H5                        5
-#define MAFSA2H6                        6
-#define MAFSA2H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) */
-#define MAFPA2L                         _SFR_MEM8(0x118)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2L {
-        unsigned int mafpa2l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 2 */
-};
-
-#define MAFPA2L_struct _SFR_MEM8_STRUCT(0x118, struct __reg_MAFPA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2L */
-
-#define MAFPA2L0                        0
-#define MAFPA2L1                        1
-#define MAFPA2L2                        2
-#define MAFPA2L3                        3
-#define MAFPA2L4                        4
-#define MAFPA2L5                        5
-#define MAFPA2L6                        6
-#define MAFPA2L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) */
-#define MAFPA2H                         _SFR_MEM8(0x119)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2H {
-        unsigned int mafpa2h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 2 */
-};
-
-#define MAFPA2H_struct _SFR_MEM8_STRUCT(0x119, struct __reg_MAFPA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2H */
-
-#define MAFPA2H0                        0
-#define MAFPA2H1                        1
-#define MAFPA2H2                        2
-#define MAFPA2H3                        3
-#define MAFPA2H4                        4
-#define MAFPA2H5                        5
-#define MAFPA2H6                        6
-#define MAFPA2H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) */
-#define MAFSA3L                         _SFR_MEM8(0x11A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3L {
-        unsigned int mafsa3l : 8;	/* MAC Short Address low Byte for Frame Filter 3 */
-};
-
-#define MAFSA3L_struct _SFR_MEM8_STRUCT(0x11a, struct __reg_MAFSA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3L */
-
-#define MAFSA3L0                        0
-#define MAFSA3L1                        1
-#define MAFSA3L2                        2
-#define MAFSA3L3                        3
-#define MAFSA3L4                        4
-#define MAFSA3L5                        5
-#define MAFSA3L6                        6
-#define MAFSA3L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) */
-#define MAFSA3H                         _SFR_MEM8(0x11B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3H {
-        unsigned int mafsa3h : 8;	/* MAC Short Address high Byte for Frame Filter 3 */
-};
-
-#define MAFSA3H_struct _SFR_MEM8_STRUCT(0x11b, struct __reg_MAFSA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3H */
-
-#define MAFSA3H0                        0
-#define MAFSA3H1                        1
-#define MAFSA3H2                        2
-#define MAFSA3H3                        3
-#define MAFSA3H4                        4
-#define MAFSA3H5                        5
-#define MAFSA3H6                        6
-#define MAFSA3H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) */
-#define MAFPA3L                         _SFR_MEM8(0x11C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3L {
-        unsigned int mafpa3l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 3 */
-};
-
-#define MAFPA3L_struct _SFR_MEM8_STRUCT(0x11c, struct __reg_MAFPA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3L */
-
-#define MAFPA3L0                        0
-#define MAFPA3L1                        1
-#define MAFPA3L2                        2
-#define MAFPA3L3                        3
-#define MAFPA3L4                        4
-#define MAFPA3L5                        5
-#define MAFPA3L6                        6
-#define MAFPA3L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) */
-#define MAFPA3H                         _SFR_MEM8(0x11D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3H {
-        unsigned int mafpa3h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 3 */
-};
-
-#define MAFPA3H_struct _SFR_MEM8_STRUCT(0x11d, struct __reg_MAFPA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3H */
-
-#define MAFPA3H0                        0
-#define MAFPA3H1                        1
-#define MAFPA3H2                        2
-#define MAFPA3H3                        3
-#define MAFPA3H4                        4
-#define MAFPA3H5                        5
-#define MAFPA3H6                        6
-#define MAFPA3H7                        7
-
-/* Timer/Counter5 Control Register A */
-#define TCCR5A                          _SFR_MEM8(0x120)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5A {
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int com5c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com5b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com5a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5A */
-
-#define WGM50                           0
-#define WGM51                           1
-#define COM5C0                          2
-#define COM5C1                          3
-#define COM5B0                          4
-#define COM5B1                          5
-#define COM5A0                          6
-#define COM5A1                          7
-
-/* Timer/Counter5 Control Register B */
-#define TCCR5B                          _SFR_MEM8(0x121)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5B {
-        unsigned int cs5 : 3;	/* Clock Select */
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices5 : 1;	/* Input Capture 5 Edge Select */
-        unsigned int icnc5 : 1;	/* Input Capture 5 Noise Canceller */
-};
-
-#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5B */
-
-#define CS50                            0
-#define CS51                            1
-#define CS52                            2
-#define WGM52                           3
-#define WGM53                           4
-#define ICES5                           6
-#define ICNC5                           7
-
-/* Timer/Counter5 Control Register C */
-#define TCCR5C                          _SFR_MEM8(0x122)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5C {
-        unsigned int : 5;
-        unsigned int foc5c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc5b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc5a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5C */
-
-#define FOC5C                           5
-#define FOC5B                           6
-#define FOC5A                           7
-
-/* Timer/Counter5  Bytes */
-#define TCNT5                           _SFR_MEM16(0x124)
-#define TCNT5L                          _SFR_MEM8(0x124)
-#define TCNT5H                          _SFR_MEM8(0x125)
-
-/* Timer/Counter5 Input Capture Register  Bytes */
-#define ICR5                            _SFR_MEM16(0x126)
-#define ICR5L                           _SFR_MEM8(0x126)
-#define ICR5H                           _SFR_MEM8(0x127)
-
-/* Timer/Counter5 Output Compare Register A  Bytes */
-#define OCR5A                           _SFR_MEM16(0x128)
-#define OCR5AL                          _SFR_MEM8(0x128)
-#define OCR5AH                          _SFR_MEM8(0x129)
-
-/* Timer/Counter5 Output Compare Register B  Bytes */
-#define OCR5B                           _SFR_MEM16(0x12A)
-#define OCR5BL                          _SFR_MEM8(0x12A)
-#define OCR5BH                          _SFR_MEM8(0x12B)
-
-/* Timer/Counter5 Output Compare Register C  Bytes */
-#define OCR5C                           _SFR_MEM16(0x12C)
-#define OCR5CL                          _SFR_MEM8(0x12C)
-#define OCR5CH                          _SFR_MEM8(0x12D)
-
-/* Low Leakage Voltage Regulator Control Register */
-#define LLCR                            _SFR_MEM8(0x12F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLCR {
-        unsigned int llencal : 1;	/* Enable Automatic Calibration */
-        unsigned int llshort : 1;	/* Short Lower Calibration Circuit */
-        unsigned int lltco : 1;	/* Temperature Coefficient of Current Source */
-        unsigned int llcal : 1;	/* Calibration Active */
-        unsigned int llcomp : 1;	/* Comparator Output */
-        unsigned int lldone : 1;	/* Calibration Done */
-        unsigned int : 2;
-};
-
-#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLCR */
-
-#define LLENCAL                         0
-#define LLSHORT                         1
-#define LLTCO                           2
-#define LLCAL                           3
-#define LLCOMP                          4
-#define LLDONE                          5
-
-/* Low Leakage Voltage Regulator Data Register (Low-Byte) */
-#define LLDRL                           _SFR_MEM8(0x130)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRL {
-        unsigned int lldrl : 4;	/* Low-Byte Data Register Bits */
-        unsigned int : 4;
-};
-
-#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRL */
-
-#define LLDRL0                          0
-#define LLDRL1                          1
-#define LLDRL2                          2
-#define LLDRL3                          3
-
-/* Low Leakage Voltage Regulator Data Register (High-Byte) */
-#define LLDRH                           _SFR_MEM8(0x131)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRH {
-        unsigned int lldrh : 5;	/* High-Byte Data Register Bits */
-        unsigned int : 3;
-};
-
-#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRH */
-
-#define LLDRH0                          0
-#define LLDRH1                          1
-#define LLDRH2                          2
-#define LLDRH3                          3
-#define LLDRH4                          4
-
-/* Data Retention Configuration Register #3 */
-#define DRTRAM3                         _SFR_MEM8(0x132)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM3 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM3 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #2 */
-#define DRTRAM2                         _SFR_MEM8(0x133)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM2 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM2 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #1 */
-#define DRTRAM1                         _SFR_MEM8(0x134)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM1 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM1 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #0 */
-#define DRTRAM0                         _SFR_MEM8(0x135)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM0 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM0 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Port Driver Strength Register 0 */
-#define DPDS0                           _SFR_MEM8(0x136)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS0 {
-        unsigned int pbdrv : 2;	/* Driver Strength Port B */
-        unsigned int pddrv : 2;	/* Driver Strength Port D */
-        unsigned int pedrv : 2;	/* Driver Strength Port E */
-        unsigned int pfdrv : 2;	/* Driver Strength Port F */
-};
-
-#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS0 */
-
-#define PBDRV0                          0
-#define PBDRV1                          1
-#define PDDRV0                          2
-#define PDDRV1                          3
-#define PEDRV0                          4
-#define PEDRV1                          5
-#define PFDRV0                          6
-#define PFDRV1                          7
-
-/* Port Driver Strength Register 1 */
-#define DPDS1                           _SFR_MEM8(0x137)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS1 {
-        unsigned int pgdrv : 2;	/* Driver Strength Port G */
-        unsigned int : 6;
-};
-
-#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS1 */
-
-#define PGDRV0                          0
-#define PGDRV1                          1
-
-/* Power Amplifier Ramp up/down Control Register */
-#define PARCR                           _SFR_MEM8(0x138)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PARCR {
-        unsigned int parufi : 1;	/* Power Amplifier Ramp Up Frequency Inversion */
-        unsigned int pardfi : 1;	/* Power Amplifier Ramp Down Frequency Inversion */
-        unsigned int paltu : 3;	/* ext. PA Ramp Up Lead Time */
-        unsigned int paltd : 3;	/* ext. PA Ramp Down Lead Time */
-};
-
-#define PARCR_struct _SFR_MEM8_STRUCT(0x138, struct __reg_PARCR)
-
-/* symbolic names */
-
-#define PALTU_MINUS_3US                 0
-#define PALTU_MINUS_2US                 1
-#define PALTU_MINUS_1US                 2
-#define PALTU_0US                       3
-#define PALTU_1US                       4
-#define PALTU_2US                       5
-#define PALTU_3US                       6
-#define PALTU_4US                       7
-#define PALTD_MINUS_3US                 0
-#define PALTD_MINUS_2US                 1
-#define PALTD_MINUS_1US                 2
-#define PALTD_0US                       3
-#define PALTD_1US                       4
-#define PALTD_2US                       5
-#define PALTD_3US                       6
-#define PALTD_4US                       7
-
-#endif /* __ASSEMBLER__ */
-
-  /* PARCR */
-
-#define PARUFI                          0
-#define PARDFI                          1
-#define PALTU0                          2
-#define PALTU1                          3
-#define PALTU2                          4
-#define PALTD0                          5
-#define PALTD1                          6
-#define PALTD2                          7
-
-/* Transceiver Pin Register */
-#define TRXPR                           _SFR_MEM8(0x139)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRXPR {
-        unsigned int trxrst : 1;	/* Force Transceiver Reset */
-        unsigned int slptr : 1;	/* Multi-purpose Transceiver Control Bit */
-        unsigned int : 6;
-};
-
-#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRXPR */
-
-#define TRXRST                          0
-#define SLPTR                           1
-
-/* AES Control Register */
-#define AES_CTRL                        _SFR_MEM8(0x13C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_CTRL {
-        unsigned int : 2;
-        unsigned int aes_im : 1;	/* AES Interrupt Enable */
-        unsigned int aes_dir : 1;	/* Set AES Operation Direction */
-        unsigned int : 1;
-        unsigned int aes_mode : 1;	/* Set AES Operation Mode */
-        unsigned int : 1;
-        unsigned int aes_request : 1;	/* Request AES Operation. */
-};
-
-#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL)
-
-/* symbolic names */
-
-#define AES_DIR_ENC                     0
-#define AES_DIR_DEC                     1
-#define AES_MODE_ECB                    0
-#define AES_MODE_CBC                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_CTRL */
-
-#define AES_IM                          2
-#define AES_DIR                         3
-#define AES_MODE                        5
-#define AES_REQUEST                     7
-
-/* AES Status Register */
-#define AES_STATUS                      _SFR_MEM8(0x13D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATUS {
-        unsigned int aes_done : 1;	/* AES Operation Finished with Success */
-        unsigned int : 6;
-        unsigned int aes_er : 1;	/* AES Operation Finished with Error */
-};
-
-#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATUS */
-
-#define AES_DONE                        0
-#define AES_ER                          7
-
-/* AES Plain and Cipher Text Buffer Register */
-#define AES_STATE                       _SFR_MEM8(0x13E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATE {
-        unsigned int aes_state : 8;	/* AES Plain and Cipher Text Buffer */
-};
-
-#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATE */
-
-#define AES_STATE0                      0
-#define AES_STATE1                      1
-#define AES_STATE2                      2
-#define AES_STATE3                      3
-#define AES_STATE4                      4
-#define AES_STATE5                      5
-#define AES_STATE6                      6
-#define AES_STATE7                      7
-
-/* AES Encryption and Decryption Key Buffer Register */
-#define AES_KEY                         _SFR_MEM8(0x13F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_KEY {
-        unsigned int aes_key : 8;	/* AES Encryption/Decryption Key Buffer */
-};
-
-#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_KEY */
-
-#define AES_KEY0                        0
-#define AES_KEY1                        1
-#define AES_KEY2                        2
-#define AES_KEY3                        3
-#define AES_KEY4                        4
-#define AES_KEY5                        5
-#define AES_KEY6                        6
-#define AES_KEY7                        7
-
-/* Transceiver Status Register */
-#define TRX_STATUS                      _SFR_MEM8(0x141)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATUS {
-        unsigned int trx_status : 5;	/* Transceiver Main Status */
-        unsigned int tst_status : 1;	/* Test mode status */
-        unsigned int cca_status : 1;	/* CCA Status Result */
-        unsigned int cca_done : 1;	/* CCA Algorithm Status */
-};
-
-#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS)
-
-/* symbolic names */
-
-#define BUSY_RX                         1
-#define BUSY_TX                         2
-#define RX_ON                           6
-#define TRX_OFF                         8
-#define PLL_ON                          9
-#define SLEEP                           15
-#define BUSY_RX_AACK                    17
-#define BUSY_TX_ARET                    18
-#define RX_AACK_ON                      22
-#define TX_ARET_ON                      25
-#define STATE_TRANSITION_IN_PROGRESS    31
-#define TST_DISABLED                    0
-#define TST_ENABLED                     1
-#define CCA_BUSY                        0
-#define CCA_IDLE                        1
-#define CCA_NOT_FIN                     0
-#define CCA_FIN                         1
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATUS */
-
-#define TRX_STATUS0                     0
-#define TRX_STATUS1                     1
-#define TRX_STATUS2                     2
-#define TRX_STATUS3                     3
-#define TRX_STATUS4                     4
-#define TST_STATUS                      5
-#define CCA_STATUS                      6
-#define CCA_DONE                        7
-
-/* Transceiver State Control Register */
-#define TRX_STATE                       _SFR_MEM8(0x142)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATE {
-        unsigned int trx_cmd : 5;	/* State Control Command */
-        unsigned int trac_status : 3;	/* Transaction Status */
-};
-
-#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE)
-
-/* symbolic names */
-
-#define CMD_NOP                         0
-#define CMD_TX_START                    2
-#define CMD_FORCE_TRX_OFF               3
-#define CMD_FORCE_PLL_ON                4
-#define CMD_RX_ON                       6
-#define CMD_TRX_OFF                     8
-#define CMD_PLL_ON                      9
-#define CMD_RX_AACK_ON                  22
-#define CMD_TX_ARET_ON                  25
-#define TRAC_SUCCESS                    0
-#define TRAC_SUCCESS_DATA_PENDING       1
-#define TRAC_SUCCESS_WAIT_FOR_ACK       2
-#define TRAC_CHANNEL_ACCESS_FAILURE     3
-#define TRAC_NO_ACK                     5
-#define TRAC_INVALID                    7
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATE */
-
-#define TRX_CMD0                        0
-#define TRX_CMD1                        1
-#define TRX_CMD2                        2
-#define TRX_CMD3                        3
-#define TRX_CMD4                        4
-#define TRAC_STATUS0                    5
-#define TRAC_STATUS1                    6
-#define TRAC_STATUS2                    7
-
-/* Reserved */
-#define TRX_CTRL_0                      _SFR_MEM8(0x143)
-
-/* Transceiver Control Register 1 */
-#define TRX_CTRL_1                      _SFR_MEM8(0x144)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_1 {
-        unsigned int : 4;
-        unsigned int pll_tx_flt : 1;	/* Enable PLL TX Filter */
-        unsigned int tx_auto_crc_on : 1;	/* Enable Automatic CRC Calculation */
-        unsigned int irq_2_ext_en : 1;	/* Connect Frame Start IRQ to TC1 */
-        unsigned int pa_ext_en : 1;	/* External PA support enable */
-};
-
-#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_1 */
-
-#define PLL_TX_FLT                      4
-#define TX_AUTO_CRC_ON                  5
-#define IRQ_2_EXT_EN                    6
-#define PA_EXT_EN                       7
-
-/* Transceiver Transmit Power Control Register */
-#define PHY_TX_PWR                      _SFR_MEM8(0x145)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_TX_PWR {
-        unsigned int tx_pwr : 4;	/* Transmit Power Setting */
-        unsigned int : 4;
-};
-
-#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_TX_PWR */
-
-#define TX_PWR0                         0
-#define TX_PWR1                         1
-#define TX_PWR2                         2
-#define TX_PWR3                         3
-
-/* Receiver Signal Strength Indicator Register */
-#define PHY_RSSI                        _SFR_MEM8(0x146)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_RSSI {
-        unsigned int rssi : 5;	/* Receiver Signal Strength Indicator */
-        unsigned int rnd_value : 2;	/* Random Value */
-        unsigned int rx_crc_valid : 1;	/* Received Frame CRC Status */
-};
-
-#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI)
-
-/* symbolic names */
-
-#define RSSI_MIN                        0
-#define RSSI_MIN_PLUS_3dB               1
-#define RSSI_MAX                        28
-#define CRC_INVALID                     0
-#define CRC_VALID                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_RSSI */
-
-#define RSSI0                           0
-#define RSSI1                           1
-#define RSSI2                           2
-#define RSSI3                           3
-#define RSSI4                           4
-#define RND_VALUE0                      5
-#define RND_VALUE1                      6
-#define RX_CRC_VALID                    7
-
-/* Transceiver Energy Detection Level Register */
-#define PHY_ED_LEVEL                    _SFR_MEM8(0x147)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_ED_LEVEL {
-        unsigned int ed_level : 8;	/* Energy Detection Level */
-};
-
-#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL)
-
-/* symbolic names */
-
-#define ED_MIN                          0
-#define ED_MIN_PLUS_1dB                 1
-#define ED_MAX                          83
-#define ED_RESET                        255
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_ED_LEVEL */
-
-#define ED_LEVEL0                       0
-#define ED_LEVEL1                       1
-#define ED_LEVEL2                       2
-#define ED_LEVEL3                       3
-#define ED_LEVEL4                       4
-#define ED_LEVEL5                       5
-#define ED_LEVEL6                       6
-#define ED_LEVEL7                       7
-
-/* Transceiver Clear Channel Assessment (CCA) Control Register */
-#define PHY_CC_CCA                      _SFR_MEM8(0x148)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_CC_CCA {
-        unsigned int channel : 5;	/* RX/TX Channel Selection */
-        unsigned int cca_mode : 2;	/* Select CCA Measurement Mode */
-        unsigned int cca_request : 1;	/* Manual CCA Measurement Request */
-};
-
-#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA)
-
-/* symbolic names */
-
-#define F_2405MHZ                       11
-#define F_2410MHZ                       12
-#define F_2415MHZ                       13
-#define F_2420MHZ                       14
-#define F_2425MHZ                       15
-#define F_2430MHZ                       16
-#define F_2435MHZ                       17
-#define F_2440MHZ                       18
-#define F_2445MHZ                       19
-#define F_2450MHZ                       20
-#define F_2455MHZ                       21
-#define F_2460MHZ                       22
-#define F_2465MHZ                       23
-#define F_2470MHZ                       24
-#define F_2475MHZ                       25
-#define F_2480MHZ                       26
-#define CCA_CS_OR_ED                    0
-#define CCA_ED                          1
-#define CCA_CS                          2
-#define CCA_CS_AND_ED                   3
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_CC_CCA */
-
-#define CHANNEL0                        0
-#define CHANNEL1                        1
-#define CHANNEL2                        2
-#define CHANNEL3                        3
-#define CHANNEL4                        4
-#define CCA_MODE0                       5
-#define CCA_MODE1                       6
-#define CCA_REQUEST                     7
-
-/* Transceiver CCA Threshold Setting Register */
-#define CCA_THRES                       _SFR_MEM8(0x149)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CCA_THRES {
-        unsigned int cca_ed_thres : 4;	/* ED Threshold Level for CCA Measurement */
-        unsigned int cca_cs_thres : 4;	/* CS Threshold Level for CCA Measurement */
-};
-
-#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CCA_THRES */
-
-#define CCA_ED_THRES0                   0
-#define CCA_ED_THRES1                   1
-#define CCA_ED_THRES2                   2
-#define CCA_ED_THRES3                   3
-#define CCA_CS_THRES0                   4
-#define CCA_CS_THRES1                   5
-#define CCA_CS_THRES2                   6
-#define CCA_CS_THRES3                   7
-
-/* Transceiver Receive Control Register */
-#define RX_CTRL                         _SFR_MEM8(0x14A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_CTRL {
-        unsigned int pdt_thres : 4;	/* Receiver Sensitivity Control */
-        unsigned int : 4;
-};
-
-#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL)
-
-/* symbolic names */
-
-#define PDT_THRES_ANT_DIV_OFF           7
-#define PDT_THRES_ANT_DIV_ON            3
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_CTRL */
-
-#define PDT_THRES0                      0
-#define PDT_THRES1                      1
-#define PDT_THRES2                      2
-#define PDT_THRES3                      3
-
-/* Start of Frame Delimiter Value Register */
-#define SFD_VALUE                       _SFR_MEM8(0x14B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SFD_VALUE {
-        unsigned int sfd_value : 8;	/* Start of Frame Delimiter Value */
-};
-
-#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE)
-
-/* symbolic names */
-
-#define IEEE_SFD                        167
-
-#endif /* __ASSEMBLER__ */
-
-  /* SFD_VALUE */
-
-#define SFD_VALUE0                      0
-#define SFD_VALUE1                      1
-#define SFD_VALUE2                      2
-#define SFD_VALUE3                      3
-#define SFD_VALUE4                      4
-#define SFD_VALUE5                      5
-#define SFD_VALUE6                      6
-#define SFD_VALUE7                      7
-
-/* Transceiver Control Register 2 */
-#define TRX_CTRL_2                      _SFR_MEM8(0x14C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_2 {
-        unsigned int oqpsk_data_rate : 2;	/* Data Rate Selection */
-        unsigned int : 5;
-        unsigned int rx_safe_mode : 1;	/* RX Safe Mode */
-};
-
-#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2)
-
-/* symbolic names */
-
-#define RATE_250KB                      0
-#define RATE_500KB                      1
-#define RATE_1000KB                     2
-#define RATE_2000KB                     3
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_2 */
-
-#define OQPSK_DATA_RATE0                0
-#define OQPSK_DATA_RATE1                1
-#define RX_SAFE_MODE                    7
-
-/* Antenna Diversity Control Register */
-#define ANT_DIV                         _SFR_MEM8(0x14D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ANT_DIV {
-        unsigned int ant_ctrl : 2;	/* Static Antenna Diversity Switch Control */
-        unsigned int ant_ext_sw_en : 1;	/* Enable External Antenna Switch Control */
-        unsigned int ant_div_en : 1;	/* Enable Antenna Diversity */
-        unsigned int : 3;
-        unsigned int ant_sel : 1;	/* Antenna Diversity Antenna Status */
-};
-
-#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV)
-
-/* symbolic names */
-
-#define ANT_1                           1
-#define ANT_0                           2
-#define ANT_RESET                       3
-#define ANT_DIV_EXT_SW_DIS              0
-#define ANT_DIV_EXT_SW_EN               1
-#define ANTENNA_0                       0
-#define ANTENNA_1                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* ANT_DIV */
-
-#define ANT_CTRL0                       0
-#define ANT_CTRL1                       1
-#define ANT_EXT_SW_EN                   2
-#define ANT_DIV_EN                      3
-#define ANT_SEL                         7
-
-/* Transceiver Interrupt Enable Register */
-#define IRQ_MASK                        _SFR_MEM8(0x14E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK {
-        unsigned int pll_lock_en : 1;	/* PLL Lock Interrupt Enable */
-        unsigned int pll_unlock_en : 1;	/* PLL Unlock Interrupt Enable */
-        unsigned int rx_start_en : 1;	/* RX_START Interrupt Enable */
-        unsigned int rx_end_en : 1;	/* RX_END Interrupt Enable */
-        unsigned int cca_ed_done_en : 1;	/* End of ED Measurement Interrupt Enable */
-        unsigned int ami_en : 1;	/* Address Match Interrupt Enable */
-        unsigned int tx_end_en : 1;	/* TX_END Interrupt Enable */
-        unsigned int awake_en : 1;	/* Awake Interrupt Enable */
-};
-
-#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK */
-
-#define PLL_LOCK_EN                     0
-#define PLL_UNLOCK_EN                   1
-#define RX_START_EN                     2
-#define RX_END_EN                       3
-#define CCA_ED_DONE_EN                  4
-#define AMI_EN                          5
-#define TX_END_EN                       6
-#define AWAKE_EN                        7
-
-/* Transceiver Interrupt Status Register */
-#define IRQ_STATUS                      _SFR_MEM8(0x14F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS {
-        unsigned int pll_lock : 1;	/* PLL Lock Interrupt Status */
-        unsigned int pll_unlock : 1;	/* PLL Unlock Interrupt Status */
-        unsigned int rx_start : 1;	/* RX_START Interrupt Status */
-        unsigned int rx_end : 1;	/* RX_END Interrupt Status */
-        unsigned int cca_ed_done : 1;	/* End of ED Measurement Interrupt Status */
-        unsigned int ami : 1;	/* Address Match Interrupt Status */
-        unsigned int tx_end : 1;	/* TX_END Interrupt Status */
-        unsigned int awake : 1;	/* Awake Interrupt Status */
-};
-
-#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS */
-
-#define PLL_LOCK                        0
-#define PLL_UNLOCK                      1
-#define RX_START                        2
-#define RX_END                          3
-#define CCA_ED_DONE                     4
-#define AMI                             5
-#define TX_END                          6
-#define AWAKE                           7
-
-/* Voltage Regulator Control and Status Register */
-#define VREG_CTRL                       _SFR_MEM8(0x150)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VREG_CTRL {
-        unsigned int : 2;
-        unsigned int dvdd_ok : 1;	/* DVDD Supply Voltage Valid */
-        unsigned int dvreg_ext : 1;	/* Use External DVDD Regulator */
-        unsigned int : 2;
-        unsigned int avdd_ok : 1;	/* AVDD Supply Voltage Valid */
-        unsigned int avreg_ext : 1;	/* Use External AVDD Regulator */
-};
-
-#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL)
-
-/* symbolic names */
-
-#define DVDD_INT                        0
-#define DVDD_EXT                        1
-#define AVDD_INT                        0
-#define AVDD_EXT                        1
-
-#endif /* __ASSEMBLER__ */
-
-  /* VREG_CTRL */
-
-#define DVDD_OK                         2
-#define DVREG_EXT                       3
-#define AVDD_OK                         6
-#define AVREG_EXT                       7
-
-/* Battery Monitor Control and Status Register */
-#define BATMON                          _SFR_MEM8(0x151)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BATMON {
-        unsigned int batmon_vth : 4;	/* Battery Monitor Threshold Voltage */
-        unsigned int batmon_hr : 1;	/* Battery Monitor Voltage Range */
-        unsigned int batmon_ok : 1;	/* Battery Monitor Status */
-        unsigned int bat_low_en : 1;	/* Battery Monitor Interrupt Enable */
-        unsigned int bat_low : 1;	/* Battery Monitor Interrupt Status */
-};
-
-#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON)
-
-/* symbolic names */
-
-#define BATMON_HR_DIS                   0
-#define BATMON_HR_EN                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* BATMON */
-
-#define BATMON_VTH0                     0
-#define BATMON_VTH1                     1
-#define BATMON_VTH2                     2
-#define BATMON_VTH3                     3
-#define BATMON_HR                       4
-#define BATMON_OK                       5
-#define BAT_LOW_EN                      6
-#define BAT_LOW                         7
-
-/* Crystal Oscillator Control Register */
-#define XOSC_CTRL                       _SFR_MEM8(0x152)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XOSC_CTRL {
-        unsigned int xtal_trim : 4;	/* Crystal Oscillator Load Capacitance Trimming */
-        unsigned int xtal_mode : 4;	/* Crystal Oscillator Operating Mode */
-};
-
-#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL)
-
-/* symbolic names */
-
-#define XTAL_TRIM_MIN                   0
-#define XTAL_TRIM_MAX                   15
-
-#endif /* __ASSEMBLER__ */
-
-  /* XOSC_CTRL */
-
-#define XTAL_TRIM0                      0
-#define XTAL_TRIM1                      1
-#define XTAL_TRIM2                      2
-#define XTAL_TRIM3                      3
-#define XTAL_MODE0                      4
-#define XTAL_MODE1                      5
-#define XTAL_MODE2                      6
-#define XTAL_MODE3                      7
-
-/* Channel Control Register 0 */
-#define CC_CTRL_0                       _SFR_MEM8(0x153)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_0 {
-        unsigned int cc_number : 8;	/* Channel Number */
-};
-
-#define CC_CTRL_0_struct _SFR_MEM8_STRUCT(0x153, struct __reg_CC_CTRL_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_0 */
-
-#define CC_NUMBER0                      0
-#define CC_NUMBER1                      1
-#define CC_NUMBER2                      2
-#define CC_NUMBER3                      3
-#define CC_NUMBER4                      4
-#define CC_NUMBER5                      5
-#define CC_NUMBER6                      6
-#define CC_NUMBER7                      7
-
-/* Channel Control Register 1 */
-#define CC_CTRL_1                       _SFR_MEM8(0x154)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_1 {
-        unsigned int cc_band : 4;	/* Channel Band */
-        unsigned int : 4;
-};
-
-#define CC_CTRL_1_struct _SFR_MEM8_STRUCT(0x154, struct __reg_CC_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_1 */
-
-#define CC_BAND0                        0
-#define CC_BAND1                        1
-#define CC_BAND2                        2
-#define CC_BAND3                        3
-
-/* Transceiver Receiver Sensitivity Control Register */
-#define RX_SYN                          _SFR_MEM8(0x155)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_SYN {
-        unsigned int rx_pdt_level : 4;	/* Reduce Receiver Sensitivity */
-        unsigned int : 2;
-        unsigned int rx_override : 1;	/* Receiver Override Function */
-        unsigned int rx_pdt_dis : 1;	/* Prevent Frame Reception */
-};
-
-#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN)
-
-/* symbolic names */
-
-#define RX_PDT_LEVEL_MIN                0
-#define RX_PDT_LEVEL_MAX                15
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_SYN */
-
-#define RX_PDT_LEVEL0                   0
-#define RX_PDT_LEVEL1                   1
-#define RX_PDT_LEVEL2                   2
-#define RX_PDT_LEVEL3                   3
-#define RX_OVERRIDE                     6
-#define RX_PDT_DIS                      7
-
-/* Transceiver Reduced Power Consumption Control */
-#define TRX_RPC                         _SFR_MEM8(0x156)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_RPC {
-        unsigned int : 1;
-        unsigned int ipan_rpc_en : 1;	/* Smart Receiving Mode IPAN Handling Enable */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int pll_rpc_en : 1;	/* PLL Smart Receiving Mode Enable */
-        unsigned int pdt_rpc_en : 1;	/* Smart Receiving Mode Reduced Sensitivity Enable */
-        unsigned int rx_rpc_en : 1;	/* Receiver Smart Receiving Mode Enable */
-        unsigned int rx_rpc_ctrl : 2;	/* Smart Receiving Mode Timing */
-};
-
-#define TRX_RPC_struct _SFR_MEM8_STRUCT(0x156, struct __reg_TRX_RPC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_RPC */
-
-#define IPAN_RPC_EN                     1
-#define PLL_RPC_EN                      3
-#define PDT_RPC_EN                      4
-#define RX_RPC_EN                       5
-#define RX_RPC_CTRL0                    6
-#define RX_RPC_CTRL1                    7
-
-/* Transceiver Acknowledgment Frame Control Register 1 */
-#define XAH_CTRL_1                      _SFR_MEM8(0x157)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_1 {
-        unsigned int : 1;
-        unsigned int aack_prom_mode : 1;	/* Enable Promiscuous Mode */
-        unsigned int aack_ack_time : 1;	/* Reduce Acknowledgment Time */
-        unsigned int : 1;
-        unsigned int aack_upld_res_ft : 1;	/* Process Reserved Frames */
-        unsigned int aack_fltr_res_ft : 1;	/* Filter Reserved Frames */
-        unsigned int : 2;
-};
-
-#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1)
-
-/* symbolic names */
-
-#define AACK_ACK_TIME_12_SYM            0
-#define AACK_ACK_TIME_2_SYM             1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_1 */
-
-#define AACK_PROM_MODE                  1
-#define AACK_ACK_TIME                   2
-#define AACK_UPLD_RES_FT                4
-#define AACK_FLTR_RES_FT                5
-
-/* Transceiver Filter Tuning Control Register */
-#define FTN_CTRL                        _SFR_MEM8(0x158)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_FTN_CTRL {
-        unsigned int : 7;
-        unsigned int ftn_start : 1;	/* Start Calibration Loop of Filter Tuning Network */
-};
-
-#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* FTN_CTRL */
-
-#define FTN_START                       7
-
-/* Transceiver Center Frequency Calibration Control Register */
-#define PLL_CF                          _SFR_MEM8(0x15A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_CF {
-        unsigned int : 7;
-        unsigned int pll_cf_start : 1;	/* Start Center Frequency Calibration */
-};
-
-#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_CF */
-
-#define PLL_CF_START                    7
-
-/* Transceiver Delay Cell Calibration Control Register */
-#define PLL_DCU                         _SFR_MEM8(0x15B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_DCU {
-        unsigned int : 7;
-        unsigned int pll_dcu_start : 1;	/* Start Delay Cell Calibration */
-};
-
-#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_DCU */
-
-#define PLL_DCU_START                   7
-
-/* Device Identification Register (Part Number) */
-#define PART_NUM                        _SFR_MEM8(0x15C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PART_NUM {
-        unsigned int part_num : 8;	/* Part Number */
-};
-
-#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM)
-
-/* symbolic names */
-
-#define P_RFR2                          148
-
-#endif /* __ASSEMBLER__ */
-
-  /* PART_NUM */
-
-#define PART_NUM0                       0
-#define PART_NUM1                       1
-#define PART_NUM2                       2
-#define PART_NUM3                       3
-#define PART_NUM4                       4
-#define PART_NUM5                       5
-#define PART_NUM6                       6
-#define PART_NUM7                       7
-
-/* Device Identification Register (Version Number) */
-#define VERSION_NUM                     _SFR_MEM8(0x15D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VERSION_NUM {
-        unsigned int version_num : 8;	/* Version Number */
-};
-
-#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM)
-
-/* symbolic names */
-
-#define REV_A                           12
-#define REV_B                           1
-#define REV_C                           3
-#define REV_D                           4
-
-#endif /* __ASSEMBLER__ */
-
-  /* VERSION_NUM */
-
-#define VERSION_NUM0                    0
-#define VERSION_NUM1                    1
-#define VERSION_NUM2                    2
-#define VERSION_NUM3                    3
-#define VERSION_NUM4                    4
-#define VERSION_NUM5                    5
-#define VERSION_NUM6                    6
-#define VERSION_NUM7                    7
-
-/* Device Identification Register (Manufacture ID Low Byte) */
-#define MAN_ID_0                        _SFR_MEM8(0x15E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_0 {
-        unsigned int man_id_00 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_01 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_02 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_03 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_04 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_05 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_06 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_07 : 1;	/* Manufacturer ID (Low Byte) */
-};
-
-#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_0                    31
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_0 */
-
-#define MAN_ID_00                       0
-#define MAN_ID_01                       1
-#define MAN_ID_02                       2
-#define MAN_ID_03                       3
-#define MAN_ID_04                       4
-#define MAN_ID_05                       5
-#define MAN_ID_06                       6
-#define MAN_ID_07                       7
-
-/* Device Identification Register (Manufacture ID High Byte) */
-#define MAN_ID_1                        _SFR_MEM8(0x15F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_1 {
-        unsigned int man_id_ : 8;	/* Manufacturer ID (High Byte) */
-};
-
-#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_1                    0
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_1 */
-
-#define MAN_ID_10                       0
-#define MAN_ID_11                       1
-#define MAN_ID_12                       2
-#define MAN_ID_13                       3
-#define MAN_ID_14                       4
-#define MAN_ID_15                       5
-#define MAN_ID_16                       6
-#define MAN_ID_17                       7
-
-/* Transceiver MAC Short Address Register (Low Byte) */
-#define SHORT_ADDR_0                    _SFR_MEM8(0x160)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_0 {
-        unsigned int short_addr_00 : 1;	/* MAC Short Address */
-        unsigned int short_addr_01 : 1;	/* MAC Short Address */
-        unsigned int short_addr_02 : 1;	/* MAC Short Address */
-        unsigned int short_addr_03 : 1;	/* MAC Short Address */
-        unsigned int short_addr_04 : 1;	/* MAC Short Address */
-        unsigned int short_addr_05 : 1;	/* MAC Short Address */
-        unsigned int short_addr_06 : 1;	/* MAC Short Address */
-        unsigned int short_addr_07 : 1;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_0 */
-
-#define SHORT_ADDR_00                   0
-#define SHORT_ADDR_01                   1
-#define SHORT_ADDR_02                   2
-#define SHORT_ADDR_03                   3
-#define SHORT_ADDR_04                   4
-#define SHORT_ADDR_05                   5
-#define SHORT_ADDR_06                   6
-#define SHORT_ADDR_07                   7
-
-/* Transceiver MAC Short Address Register (High Byte) */
-#define SHORT_ADDR_1                    _SFR_MEM8(0x161)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_1 {
-        unsigned int short_addr_ : 8;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_1 */
-
-#define SHORT_ADDR_10                   0
-#define SHORT_ADDR_11                   1
-#define SHORT_ADDR_12                   2
-#define SHORT_ADDR_13                   3
-#define SHORT_ADDR_14                   4
-#define SHORT_ADDR_15                   5
-#define SHORT_ADDR_16                   6
-#define SHORT_ADDR_17                   7
-
-/* Transceiver Personal Area Network ID Register (Low Byte) */
-#define PAN_ID_0                        _SFR_MEM8(0x162)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_0 {
-        unsigned int pan_id_00 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_01 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_02 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_03 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_04 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_05 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_06 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_07 : 1;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_0 */
-
-#define PAN_ID_00                       0
-#define PAN_ID_01                       1
-#define PAN_ID_02                       2
-#define PAN_ID_03                       3
-#define PAN_ID_04                       4
-#define PAN_ID_05                       5
-#define PAN_ID_06                       6
-#define PAN_ID_07                       7
-
-/* Transceiver Personal Area Network ID Register (High Byte) */
-#define PAN_ID_1                        _SFR_MEM8(0x163)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_1 {
-        unsigned int pan_id_ : 8;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_1 */
-
-#define PAN_ID_10                       0
-#define PAN_ID_11                       1
-#define PAN_ID_12                       2
-#define PAN_ID_13                       3
-#define PAN_ID_14                       4
-#define PAN_ID_15                       5
-#define PAN_ID_16                       6
-#define PAN_ID_17                       7
-
-/* Transceiver MAC IEEE Address Register 0 */
-#define IEEE_ADDR_0                     _SFR_MEM8(0x164)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_0 {
-        unsigned int ieee_addr_00 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_01 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_02 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_03 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_04 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_05 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_06 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_07 : 1;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_0 */
-
-#define IEEE_ADDR_00                    0
-#define IEEE_ADDR_01                    1
-#define IEEE_ADDR_02                    2
-#define IEEE_ADDR_03                    3
-#define IEEE_ADDR_04                    4
-#define IEEE_ADDR_05                    5
-#define IEEE_ADDR_06                    6
-#define IEEE_ADDR_07                    7
-
-/* Transceiver MAC IEEE Address Register 1 */
-#define IEEE_ADDR_1                     _SFR_MEM8(0x165)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_1 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_1 */
-
-#define IEEE_ADDR_10                    0
-#define IEEE_ADDR_11                    1
-#define IEEE_ADDR_12                    2
-#define IEEE_ADDR_13                    3
-#define IEEE_ADDR_14                    4
-#define IEEE_ADDR_15                    5
-#define IEEE_ADDR_16                    6
-#define IEEE_ADDR_17                    7
-
-/* Transceiver MAC IEEE Address Register 2 */
-#define IEEE_ADDR_2                     _SFR_MEM8(0x166)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_2 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_2 */
-
-#define IEEE_ADDR_20                    0
-#define IEEE_ADDR_21                    1
-#define IEEE_ADDR_22                    2
-#define IEEE_ADDR_23                    3
-#define IEEE_ADDR_24                    4
-#define IEEE_ADDR_25                    5
-#define IEEE_ADDR_26                    6
-#define IEEE_ADDR_27                    7
-
-/* Transceiver MAC IEEE Address Register 3 */
-#define IEEE_ADDR_3                     _SFR_MEM8(0x167)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_3 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_3 */
-
-#define IEEE_ADDR_30                    0
-#define IEEE_ADDR_31                    1
-#define IEEE_ADDR_32                    2
-#define IEEE_ADDR_33                    3
-#define IEEE_ADDR_34                    4
-#define IEEE_ADDR_35                    5
-#define IEEE_ADDR_36                    6
-#define IEEE_ADDR_37                    7
-
-/* Transceiver MAC IEEE Address Register 4 */
-#define IEEE_ADDR_4                     _SFR_MEM8(0x168)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_4 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_4 */
-
-#define IEEE_ADDR_40                    0
-#define IEEE_ADDR_41                    1
-#define IEEE_ADDR_42                    2
-#define IEEE_ADDR_43                    3
-#define IEEE_ADDR_44                    4
-#define IEEE_ADDR_45                    5
-#define IEEE_ADDR_46                    6
-#define IEEE_ADDR_47                    7
-
-/* Transceiver MAC IEEE Address Register 5 */
-#define IEEE_ADDR_5                     _SFR_MEM8(0x169)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_5 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_5 */
-
-#define IEEE_ADDR_50                    0
-#define IEEE_ADDR_51                    1
-#define IEEE_ADDR_52                    2
-#define IEEE_ADDR_53                    3
-#define IEEE_ADDR_54                    4
-#define IEEE_ADDR_55                    5
-#define IEEE_ADDR_56                    6
-#define IEEE_ADDR_57                    7
-
-/* Transceiver MAC IEEE Address Register 6 */
-#define IEEE_ADDR_6                     _SFR_MEM8(0x16A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_6 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_6 */
-
-#define IEEE_ADDR_60                    0
-#define IEEE_ADDR_61                    1
-#define IEEE_ADDR_62                    2
-#define IEEE_ADDR_63                    3
-#define IEEE_ADDR_64                    4
-#define IEEE_ADDR_65                    5
-#define IEEE_ADDR_66                    6
-#define IEEE_ADDR_67                    7
-
-/* Transceiver MAC IEEE Address Register 7 */
-#define IEEE_ADDR_7                     _SFR_MEM8(0x16B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_7 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_7 */
-
-#define IEEE_ADDR_70                    0
-#define IEEE_ADDR_71                    1
-#define IEEE_ADDR_72                    2
-#define IEEE_ADDR_73                    3
-#define IEEE_ADDR_74                    4
-#define IEEE_ADDR_75                    5
-#define IEEE_ADDR_76                    6
-#define IEEE_ADDR_77                    7
-
-/* Transceiver Extended Operating Mode Control Register */
-#define XAH_CTRL_0                      _SFR_MEM8(0x16C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_0 {
-        unsigned int slotted_operation : 1;	/* Set Slotted Acknowledgment */
-        unsigned int max_csma_retries : 3;	/* Maximum Number of CSMA-CA Procedure Repetition Attempts */
-        unsigned int max_frame_retries : 4;	/* Maximum Number of Frame Re-transmission Attempts */
-};
-
-#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0)
-
-/* symbolic names */
-
-#define SLOTTED_OP_DIS                  0
-#define SLOTTED_OP_EN                   1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_0 */
-
-#define SLOTTED_OPERATION               0
-#define MAX_CSMA_RETRIES0               1
-#define MAX_CSMA_RETRIES1               2
-#define MAX_CSMA_RETRIES2               3
-#define MAX_FRAME_RETRIES0              4
-#define MAX_FRAME_RETRIES1              5
-#define MAX_FRAME_RETRIES2              6
-#define MAX_FRAME_RETRIES3              7
-
-/* Transceiver CSMA-CA Random Number Generator Seed Register */
-#define CSMA_SEED_0                     _SFR_MEM8(0x16D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_0 {
-        unsigned int csma_seed_00 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_01 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_02 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_03 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_04 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_05 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_06 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_07 : 1;	/* Seed Value for CSMA Random Number Generator */
-};
-
-#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_0 */
-
-#define CSMA_SEED_00                    0
-#define CSMA_SEED_01                    1
-#define CSMA_SEED_02                    2
-#define CSMA_SEED_03                    3
-#define CSMA_SEED_04                    4
-#define CSMA_SEED_05                    5
-#define CSMA_SEED_06                    6
-#define CSMA_SEED_07                    7
-
-/* Transceiver Acknowledgment Frame Control Register 2 */
-#define CSMA_SEED_1                     _SFR_MEM8(0x16E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_1 {
-        unsigned int csma_seed_1 : 3;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int aack_i_am_coord : 1;	/* Set Personal Area Network Coordinator */
-        unsigned int aack_dis_ack : 1;	/* Disable Acknowledgment Frame Transmission */
-        unsigned int aack_set_pd : 1;	/* Set Frame Pending Sub-field */
-        unsigned int aack_fvn_mode : 2;	/* Acknowledgment Frame Filter Mode */
-};
-
-#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_1 */
-
-#define CSMA_SEED_10                    0
-#define CSMA_SEED_11                    1
-#define CSMA_SEED_12                    2
-#define AACK_I_AM_COORD                 3
-#define AACK_DIS_ACK                    4
-#define AACK_SET_PD                     5
-#define AACK_FVN_MODE0                  6
-#define AACK_FVN_MODE1                  7
-
-/* Transceiver CSMA-CA Back-off Exponent Control Register */
-#define CSMA_BE                         _SFR_MEM8(0x16F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_BE {
-        unsigned int min_be : 4;	/* Minimum Back-off Exponent */
-        unsigned int max_be : 4;	/* Maximum Back-off Exponent */
-};
-
-#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_BE */
-
-#define MIN_BE0                         0
-#define MIN_BE1                         1
-#define MIN_BE2                         2
-#define MIN_BE3                         3
-#define MAX_BE0                         4
-#define MAX_BE1                         5
-#define MAX_BE2                         6
-#define MAX_BE3                         7
-
-/* Transceiver Digital Test Control Register */
-#define TST_CTRL_DIGI                   _SFR_MEM8(0x176)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_CTRL_DIGI {
-        unsigned int tst_ctrl_dig : 4;	/* Digital Test Controller Register */
-        unsigned int : 4;
-};
-
-#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_CTRL_DIGI */
-
-#define TST_CTRL_DIG0                   0
-#define TST_CTRL_DIG1                   1
-#define TST_CTRL_DIG2                   2
-#define TST_CTRL_DIG3                   3
-
-/* Transceiver Received Frame Length Register */
-#define TST_RX_LENGTH                   _SFR_MEM8(0x17B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_RX_LENGTH {
-        unsigned int rx_length : 8;	/* Received Frame Length */
-};
-
-#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH)
-
-#endif /* __ASSEMBLER__ */
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
 
-  /* TST_RX_LENGTH */
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
 
-#define RX_LENGTH0                      0
-#define RX_LENGTH1                      1
-#define RX_LENGTH2                      2
-#define RX_LENGTH3                      3
-#define RX_LENGTH4                      4
-#define RX_LENGTH5                      5
-#define RX_LENGTH6                      6
-#define RX_LENGTH7                      7
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define MUX5    3
+#define ACCH    4
+#define REFOK   5
+#define AVDDOK  7
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC8D   0
+#define ADC9D   1
+#define ADC10D  2
+#define ADC11D  3
+#define ADC12D  4
+#define ADC13D  5
+#define ADC14D  6
+#define ADC15D  7
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1C0  2
+#define COM1C1  3
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1C   5
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define WGM30   0
+#define WGM31   1
+#define COM3C0  2
+#define COM3C1  3
+#define COM3B0  4
+#define COM3B1  5
+#define COM3A0  6
+#define COM3A1  7
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define CS30    0
+#define CS31    1
+#define CS32    2
+#define WGM32   3
+#define WGM33   4
+#define ICES3   6
+#define ICNC3   7
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3C   5
+#define FOC3B   6
+#define FOC3A   7
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define WGM40   0
+#define WGM41   1
+#define COM4C0  2
+#define COM4C1  3
+#define COM4B0  4
+#define COM4B1  5
+#define COM4A0  6
+#define COM4A1  7
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define CS40    0
+#define CS41    1
+#define CS42    2
+#define WGM42   3
+#define WGM43   4
+#define ICES4   6
+#define ICNC4   7
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4C   5
+#define FOC4B   6
+#define FOC4A   7
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+#define EXCLKAMR 7
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+#define IRQ_MASK1 _SFR_MEM8(0xBE)
+#define TX_START_EN 0
+#define MAF_0_AMI_EN 1
+#define MAF_1_AMI_EN 2
+#define MAF_2_AMI_EN 3
+#define MAF_3_AMI_EN 4
+
+#define IRQ_STATUS1 _SFR_MEM8(0xBF)
+#define TX_START 0
+#define MAF_0_AMI 1
+#define MAF_1_AMI 2
+#define MAF_2_AMI 3
+#define MAF_3_AMI 4
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+#define UCPHA0  1
+#define UDORD0  2
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+#define UCSR1B  _SFR_MEM8(0xC9)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+#define UCPHA1  1
+#define UDORD1  2
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0xCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define SCRSTRLL _SFR_MEM8(0xD7)
+#define SCRSTRLL0 0
+#define SCRSTRLL1 1
+#define SCRSTRLL2 2
+#define SCRSTRLL3 3
+#define SCRSTRLL4 4
+#define SCRSTRLL5 5
+#define SCRSTRLL6 6
+#define SCRSTRLL7 7
+
+#define SCRSTRLH _SFR_MEM8(0xD8)
+#define SCRSTRLH0 0
+#define SCRSTRLH1 1
+#define SCRSTRLH2 2
+#define SCRSTRLH3 3
+#define SCRSTRLH4 4
+#define SCRSTRLH5 5
+#define SCRSTRLH6 6
+#define SCRSTRLH7 7
+
+#define SCRSTRHL _SFR_MEM8(0xD9)
+#define SCRSTRHL0 0
+#define SCRSTRHL1 1
+#define SCRSTRHL2 2
+#define SCRSTRHL3 3
+#define SCRSTRHL4 4
+#define SCRSTRHL5 5
+#define SCRSTRHL6 6
+#define SCRSTRHL7 7
+
+#define SCRSTRHH _SFR_MEM8(0xDA)
+#define SCRSTRHH0 0
+#define SCRSTRHH1 1
+#define SCRSTRHH2 2
+#define SCRSTRHH3 3
+#define SCRSTRHH4 4
+#define SCRSTRHH5 5
+#define SCRSTRHH6 6
+#define SCRSTRHH7 7
+
+#define SCCSR   _SFR_MEM8(0xDB)
+#define SCCS10  0
+#define SCCS11  1
+#define SCCS20  2
+#define SCCS21  3
+#define SCCS30  4
+#define SCCS31  5
+
+#define SCCR0   _SFR_MEM8(0xDC)
+#define SCCMP1  0
+#define SCCMP2  1
+#define SCCMP3  2
+#define SCTSE   3
+#define SCCKSEL 4
+#define SCEN    5
+#define SCMBTS  6
+#define SCRES   7
+
+#define SCCR1   _SFR_MEM8(0xDD)
+#define SCENBO  0
+#define SCEECLK 1
+#define SCCKDIV0 2
+#define SCCKDIV1 3
+#define SCCKDIV2 4
+#define SCBTSM  5
+#define Res5    6
+#define Res6    7
+
+#define SCSR    _SFR_MEM8(0xDE)
+#define SCBSY   0
+
+#define SCIRQM  _SFR_MEM8(0xDF)
+#define IRQMCP1 0
+#define IRQMCP2 1
+#define IRQMCP3 2
+#define IRQMOF  3
+#define IRQMBO  4
+
+#define SCIRQS  _SFR_MEM8(0xE0)
+#define IRQSCP1 0
+#define IRQSCP2 1
+#define IRQSCP3 2
+#define IRQSOF  3
+#define IRQSBO  4
+
+#define SCCNTLL _SFR_MEM8(0xE1)
+#define SCCNTLL0 0
+#define SCCNTLL1 1
+#define SCCNTLL2 2
+#define SCCNTLL3 3
+#define SCCNTLL4 4
+#define SCCNTLL5 5
+#define SCCNTLL6 6
+#define SCCNTLL7 7
+
+#define SCCNTLH _SFR_MEM8(0xE2)
+#define SCCNTLH0 0
+#define SCCNTLH1 1
+#define SCCNTLH2 2
+#define SCCNTLH3 3
+#define SCCNTLH4 4
+#define SCCNTLH5 5
+#define SCCNTLH6 6
+#define SCCNTLH7 7
+
+#define SCCNTHL _SFR_MEM8(0xE3)
+#define SCCNTHL0 0
+#define SCCNTHL1 1
+#define SCCNTHL2 2
+#define SCCNTHL3 3
+#define SCCNTHL4 4
+#define SCCNTHL5 5
+#define SCCNTHL6 6
+#define SCCNTHL7 7
+
+#define SCCNTHH _SFR_MEM8(0xE4)
+#define SCCNTHH0 0
+#define SCCNTHH1 1
+#define SCCNTHH2 2
+#define SCCNTHH3 3
+#define SCCNTHH4 4
+#define SCCNTHH5 5
+#define SCCNTHH6 6
+#define SCCNTHH7 7
+
+#define SCBTSRLL _SFR_MEM8(0xE5)
+#define SCBTSRLL0 0
+#define SCBTSRLL1 1
+#define SCBTSRLL2 2
+#define SCBTSRLL3 3
+#define SCBTSRLL4 4
+#define SCBTSRLL5 5
+#define SCBTSRLL6 6
+#define SCBTSRLL7 7
+
+#define SCBTSRLH _SFR_MEM8(0xE6)
+#define SCBTSRLH0 0
+#define SCBTSRLH1 1
+#define SCBTSRLH2 2
+#define SCBTSRLH3 3
+#define SCBTSRLH4 4
+#define SCBTSRLH5 5
+#define SCBTSRLH6 6
+#define SCBTSRLH7 7
+
+#define SCBTSRHL _SFR_MEM8(0xE7)
+#define SCBTSRHL0 0
+#define SCBTSRHL1 1
+#define SCBTSRHL2 2
+#define SCBTSRHL3 3
+#define SCBTSRHL4 4
+#define SCBTSRHL5 5
+#define SCBTSRHL6 6
+#define SCBTSRHL7 7
+
+#define SCBTSRHH _SFR_MEM8(0xE8)
+#define SCBTSRHH0 0
+#define SCBTSRHH1 1
+#define SCBTSRHH2 2
+#define SCBTSRHH3 3
+#define SCBTSRHH4 4
+#define SCBTSRHH5 5
+#define SCBTSRHH6 6
+#define SCBTSRHH7 7
+
+#define SCTSRLL _SFR_MEM8(0xE9)
+#define SCTSRLL0 0
+#define SCTSRLL1 1
+#define SCTSRLL2 2
+#define SCTSRLL3 3
+#define SCTSRLL4 4
+#define SCTSRLL5 5
+#define SCTSRLL6 6
+#define SCTSRLL7 7
+
+#define SCTSRLH _SFR_MEM8(0xEA)
+#define SCTSRLH0 0
+#define SCTSRLH1 1
+#define SCTSRLH2 2
+#define SCTSRLH3 3
+#define SCTSRLH4 4
+#define SCTSRLH5 5
+#define SCTSRLH6 6
+#define SCTSRLH7 7
+
+#define SCTSRHL _SFR_MEM8(0xEB)
+#define SCTSRHL0 0
+#define SCTSRHL1 1
+#define SCTSRHL2 2
+#define SCTSRHL3 3
+#define SCTSRHL4 4
+#define SCTSRHL5 5
+#define SCTSRHL6 6
+#define SCTSRHL7 7
+
+#define SCTSRHH _SFR_MEM8(0xEC)
+#define SCTSRHH0 0
+#define SCTSRHH1 1
+#define SCTSRHH2 2
+#define SCTSRHH3 3
+#define SCTSRHH4 4
+#define SCTSRHH5 5
+#define SCTSRHH6 6
+#define SCTSRHH7 7
+
+#define SCOCR3LL _SFR_MEM8(0xED)
+#define SCOCR3LL0 0
+#define SCOCR3LL1 1
+#define SCOCR3LL2 2
+#define SCOCR3LL3 3
+#define SCOCR3LL4 4
+#define SCOCR3LL5 5
+#define SCOCR3LL6 6
+#define SCOCR3LL7 7
+
+#define SCOCR3LH _SFR_MEM8(0xEE)
+#define SCOCR3LH0 0
+#define SCOCR3LH1 1
+#define SCOCR3LH2 2
+#define SCOCR3LH3 3
+#define SCOCR3LH4 4
+#define SCOCR3LH5 5
+#define SCOCR3LH6 6
+#define SCOCR3LH7 7
+
+#define SCOCR3HL _SFR_MEM8(0xEF)
+#define SCOCR3HL0 0
+#define SCOCR3HL1 1
+#define SCOCR3HL2 2
+#define SCOCR3HL3 3
+#define SCOCR3HL4 4
+#define SCOCR3HL5 5
+#define SCOCR3HL6 6
+#define SCOCR3HL7 7
+
+#define SCOCR3HH _SFR_MEM8(0xF0)
+#define SCOCR3HH0 0
+#define SCOCR3HH1 1
+#define SCOCR3HH2 2
+#define SCOCR3HH3 3
+#define SCOCR3HH4 4
+#define SCOCR3HH5 5
+#define SCOCR3HH6 6
+#define SCOCR3HH7 7
+
+#define SCOCR2LL _SFR_MEM8(0xF1)
+#define SCOCR2LL0 0
+#define SCOCR2LL1 1
+#define SCOCR2LL2 2
+#define SCOCR2LL3 3
+#define SCOCR2LL4 4
+#define SCOCR2LL5 5
+#define SCOCR2LL6 6
+#define SCOCR2LL7 7
+
+#define SCOCR2LH _SFR_MEM8(0xF2)
+#define SCOCR2LH0 0
+#define SCOCR2LH1 1
+#define SCOCR2LH2 2
+#define SCOCR2LH3 3
+#define SCOCR2LH4 4
+#define SCOCR2LH5 5
+#define SCOCR2LH6 6
+#define SCOCR2LH7 7
+
+#define SCOCR2HL _SFR_MEM8(0xF3)
+#define SCOCR2HL0 0
+#define SCOCR2HL1 1
+#define SCOCR2HL2 2
+#define SCOCR2HL3 3
+#define SCOCR2HL4 4
+#define SCOCR2HL5 5
+#define SCOCR2HL6 6
+#define SCOCR2HL7 7
+
+#define SCOCR2HH _SFR_MEM8(0xF4)
+#define SCOCR2HH0 0
+#define SCOCR2HH1 1
+#define SCOCR2HH2 2
+#define SCOCR2HH3 3
+#define SCOCR2HH4 4
+#define SCOCR2HH5 5
+#define SCOCR2HH6 6
+#define SCOCR2HH7 7
+
+#define SCOCR1LL _SFR_MEM8(0xF5)
+#define SCOCR1LL0 0
+#define SCOCR1LL1 1
+#define SCOCR1LL2 2
+#define SCOCR1LL3 3
+#define SCOCR1LL4 4
+#define SCOCR1LL5 5
+#define SCOCR1LL6 6
+#define SCOCR1LL7 7
+
+#define SCOCR1LH _SFR_MEM8(0xF6)
+#define SCOCR1LH0 0
+#define SCOCR1LH1 1
+#define SCOCR1LH2 2
+#define SCOCR1LH3 3
+#define SCOCR1LH4 4
+#define SCOCR1LH5 5
+#define SCOCR1LH6 6
+#define SCOCR1LH7 7
+
+#define SCOCR1HL _SFR_MEM8(0xF7)
+#define SCOCR1HL0 0
+#define SCOCR1HL1 1
+#define SCOCR1HL2 2
+#define SCOCR1HL3 3
+#define SCOCR1HL4 4
+#define SCOCR1HL5 5
+#define SCOCR1HL6 6
+#define SCOCR1HL7 7
+
+#define SCOCR1HH _SFR_MEM8(0xF8)
+#define SCOCR1HH0 0
+#define SCOCR1HH1 1
+#define SCOCR1HH2 2
+#define SCOCR1HH3 3
+#define SCOCR1HH4 4
+#define SCOCR1HH5 5
+#define SCOCR1HH6 6
+#define SCOCR1HH7 7
+
+#define SCTSTRLL _SFR_MEM8(0xF9)
+#define SCTSTRLL0 0
+#define SCTSTRLL1 1
+#define SCTSTRLL2 2
+#define SCTSTRLL3 3
+#define SCTSTRLL4 4
+#define SCTSTRLL5 5
+#define SCTSTRLL6 6
+#define SCTSTRLL7 7
+
+#define SCTSTRLH _SFR_MEM8(0xFA)
+#define SCTSTRLH0 0
+#define SCTSTRLH1 1
+#define SCTSTRLH2 2
+#define SCTSTRLH3 3
+#define SCTSTRLH4 4
+#define SCTSTRLH5 5
+#define SCTSTRLH6 6
+#define SCTSTRLH7 7
+
+#define SCTSTRHL _SFR_MEM8(0xFB)
+#define SCTSTRHL0 0
+#define SCTSTRHL1 1
+#define SCTSTRHL2 2
+#define SCTSTRHL3 3
+#define SCTSTRHL4 4
+#define SCTSTRHL5 5
+#define SCTSTRHL6 6
+#define SCTSTRHL7 7
+
+#define SCTSTRHH _SFR_MEM8(0xFC)
+#define SCTSTRHH0 0
+#define SCTSTRHH1 1
+#define SCTSTRHH2 2
+#define SCTSTRHH3 3
+#define SCTSTRHH4 4
+#define SCTSTRHH5 5
+#define SCTSTRHH6 6
+#define SCTSTRHH7 7
+
+/* Reserved [0xFD..0x10B] */
+
+#define MAFCR0  _SFR_MEM8(0x10C)
+#define MAF0EN  0
+#define MAF1EN  1
+#define MAF2EN  2
+#define MAF3EN  3
+
+#define MAFCR1  _SFR_MEM8(0x10D)
+#define AACK_0_I_AM_COORD 0
+#define AACK_0_SET_PD 1
+#define AACK_1_I_AM_COORD 2
+#define AACK_1_SET_PD 3
+#define AACK_2_I_AM_COORD 4
+#define AACK_2_SET_PD 5
+#define AACK_3_I_AM_COORD 6
+#define AACK_3_SET_PD 7
+
+#define MAFSA0L _SFR_MEM8(0x10E)
+#define MAFSA0L0 0
+#define MAFSA0L1 1
+#define MAFSA0L2 2
+#define MAFSA0L3 3
+#define MAFSA0L4 4
+#define MAFSA0L5 5
+#define MAFSA0L6 6
+#define MAFSA0L7 7
+
+#define MAFSA0H _SFR_MEM8(0x10F)
+#define MAFSA0H0 0
+#define MAFSA0H1 1
+#define MAFSA0H2 2
+#define MAFSA0H3 3
+#define MAFSA0H4 4
+#define MAFSA0H5 5
+#define MAFSA0H6 6
+#define MAFSA0H7 7
+
+#define MAFPA0L _SFR_MEM8(0x110)
+#define MAFPA0L0 0
+#define MAFPA0L1 1
+#define MAFPA0L2 2
+#define MAFPA0L3 3
+#define MAFPA0L4 4
+#define MAFPA0L5 5
+#define MAFPA0L6 6
+#define MAFPA0L7 7
+
+#define MAFPA0H _SFR_MEM8(0x111)
+#define MAFPA0H0 0
+#define MAFPA0H1 1
+#define MAFPA0H2 2
+#define MAFPA0H3 3
+#define MAFPA0H4 4
+#define MAFPA0H5 5
+#define MAFPA0H6 6
+#define MAFPA0H7 7
+
+#define MAFSA1L _SFR_MEM8(0x112)
+#define MAFSA1L0 0
+#define MAFSA1L1 1
+#define MAFSA1L2 2
+#define MAFSA1L3 3
+#define MAFSA1L4 4
+#define MAFSA1L5 5
+#define MAFSA1L6 6
+#define MAFSA1L7 7
+
+#define MAFSA1H _SFR_MEM8(0x113)
+#define MAFSA1H0 0
+#define MAFSA1H1 1
+#define MAFSA1H2 2
+#define MAFSA1H3 3
+#define MAFSA1H4 4
+#define MAFSA1H5 5
+#define MAFSA1H6 6
+#define MAFSA1H7 7
+
+#define MAFPA1L _SFR_MEM8(0x114)
+#define MAFPA1L0 0
+#define MAFPA1L1 1
+#define MAFPA1L2 2
+#define MAFPA1L3 3
+#define MAFPA1L4 4
+#define MAFPA1L5 5
+#define MAFPA1L6 6
+#define MAFPA1L7 7
+
+#define MAFPA1H _SFR_MEM8(0x115)
+#define MAFPA1H0 0
+#define MAFPA1H1 1
+#define MAFPA1H2 2
+#define MAFPA1H3 3
+#define MAFPA1H4 4
+#define MAFPA1H5 5
+#define MAFPA1H6 6
+#define MAFPA1H7 7
+
+#define MAFSA2L _SFR_MEM8(0x116)
+#define MAFSA2L0 0
+#define MAFSA2L1 1
+#define MAFSA2L2 2
+#define MAFSA2L3 3
+#define MAFSA2L4 4
+#define MAFSA2L5 5
+#define MAFSA2L6 6
+#define MAFSA2L7 7
+
+#define MAFSA2H _SFR_MEM8(0x117)
+#define MAFSA2H0 0
+#define MAFSA2H1 1
+#define MAFSA2H2 2
+#define MAFSA2H3 3
+#define MAFSA2H4 4
+#define MAFSA2H5 5
+#define MAFSA2H6 6
+#define MAFSA2H7 7
+
+#define MAFPA2L _SFR_MEM8(0x118)
+#define MAFPA2L0 0
+#define MAFPA2L1 1
+#define MAFPA2L2 2
+#define MAFPA2L3 3
+#define MAFPA2L4 4
+#define MAFPA2L5 5
+#define MAFPA2L6 6
+#define MAFPA2L7 7
+
+#define MAFPA2H _SFR_MEM8(0x119)
+#define MAFPA2H0 0
+#define MAFPA2H1 1
+#define MAFPA2H2 2
+#define MAFPA2H3 3
+#define MAFPA2H4 4
+#define MAFPA2H5 5
+#define MAFPA2H6 6
+#define MAFPA2H7 7
+
+#define MAFSA3L _SFR_MEM8(0x11A)
+#define MAFSA3L0 0
+#define MAFSA3L1 1
+#define MAFSA3L2 2
+#define MAFSA3L3 3
+#define MAFSA3L4 4
+#define MAFSA3L5 5
+#define MAFSA3L6 6
+#define MAFSA3L7 7
+
+#define MAFSA3H _SFR_MEM8(0x11B)
+#define MAFSA3H0 0
+#define MAFSA3H1 1
+#define MAFSA3H2 2
+#define MAFSA3H3 3
+#define MAFSA3H4 4
+#define MAFSA3H5 5
+#define MAFSA3H6 6
+#define MAFSA3H7 7
+
+#define MAFPA3L _SFR_MEM8(0x11C)
+#define MAFPA3L0 0
+#define MAFPA3L1 1
+#define MAFPA3L2 2
+#define MAFPA3L3 3
+#define MAFPA3L4 4
+#define MAFPA3L5 5
+#define MAFPA3L6 6
+#define MAFPA3L7 7
+
+#define MAFPA3H _SFR_MEM8(0x11D)
+#define MAFPA3H0 0
+#define MAFPA3H1 1
+#define MAFPA3H2 2
+#define MAFPA3H3 3
+#define MAFPA3H4 4
+#define MAFPA3H5 5
+#define MAFPA3H6 6
+#define MAFPA3H7 7
+
+/* Reserved [0x11E..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define WGM50   0
+#define WGM51   1
+#define COM5C0  2
+#define COM5C1  3
+#define COM5B0  4
+#define COM5B1  5
+#define COM5A0  6
+#define COM5A1  7
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define CS50    0
+#define CS51    1
+#define CS52    2
+#define WGM52   3
+#define WGM53   4
+#define ICES5   6
+#define ICNC5   7
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5C   5
+#define FOC5B   6
+#define FOC5A   7
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E] */
+
+#define LLCR    _SFR_MEM8(0x12F)
+#define LLENCAL 0
+#define LLSHORT 1
+#define LLTCO   2
+#define LLCAL   3
+#define LLCOMP  4
+#define LLDONE  5
+
+#define LLDRL   _SFR_MEM8(0x130)
+#define LLDRL0  0
+#define LLDRL1  1
+#define LLDRL2  2
+#define LLDRL3  3
+
+#define LLDRH   _SFR_MEM8(0x131)
+#define LLDRH0  0
+#define LLDRH1  1
+#define LLDRH2  2
+#define LLDRH3  3
+#define LLDRH4  4
+
+#define DRTRAM3 _SFR_MEM8(0x132)
+#define ENDRT   4
+#define DRTSWOK 5
+
+#define DRTRAM2 _SFR_MEM8(0x133)
+
+#define DRTRAM1 _SFR_MEM8(0x134)
+
+#define DRTRAM0 _SFR_MEM8(0x135)
+
+#define DPDS0   _SFR_MEM8(0x136)
+#define PBDRV0  0
+#define PBDRV1  1
+#define PDDRV0  2
+#define PDDRV1  3
+#define PEDRV0  4
+#define PEDRV1  5
+#define PFDRV0  6
+#define PFDRV1  7
+
+#define DPDS1   _SFR_MEM8(0x137)
+#define PGDRV0  0
+#define PGDRV1  1
+
+#define PARCR   _SFR_MEM8(0x138)
+#define PARUFI  0
+#define PARDFI  1
+#define PALTU0  2
+#define PALTU1  3
+#define PALTU2  4
+#define PALTD0  5
+#define PALTD1  6
+#define PALTD2  7
+
+#define TRXPR   _SFR_MEM8(0x139)
+#define TRXRST  0
+#define SLPTR   1
+
+/* Reserved [0x13A..0x13B] */
+
+#define AES_CTRL _SFR_MEM8(0x13C)
+#define AES_IM  2
+#define AES_DIR 3
+#define AES_MODE 5
+#define AES_REQUEST 7
+
+#define AES_STATUS _SFR_MEM8(0x13D)
+#define AES_DONE 0
+#define AES_ER  7
+
+#define AES_STATE _SFR_MEM8(0x13E)
+#define AES_STATE0 0
+#define AES_STATE1 1
+#define AES_STATE2 2
+#define AES_STATE3 3
+#define AES_STATE4 4
+#define AES_STATE5 5
+#define AES_STATE6 6
+#define AES_STATE7 7
+
+#define AES_KEY _SFR_MEM8(0x13F)
+#define AES_KEY0 0
+#define AES_KEY1 1
+#define AES_KEY2 2
+#define AES_KEY3 3
+#define AES_KEY4 4
+#define AES_KEY5 5
+#define AES_KEY6 6
+#define AES_KEY7 7
+
+/* Reserved [0x140] */
+
+#define TRX_STATUS _SFR_MEM8(0x141)
+#define TRX_STATUS0 0
+#define TRX_STATUS1 1
+#define TRX_STATUS2 2
+#define TRX_STATUS3 3
+#define TRX_STATUS4 4
+#define TST_STATUS 5
+#define CCA_STATUS 6
+#define CCA_DONE 7
+
+#define TRX_STATE _SFR_MEM8(0x142)
+#define TRX_CMD0 0
+#define TRX_CMD1 1
+#define TRX_CMD2 2
+#define TRX_CMD3 3
+#define TRX_CMD4 4
+#define TRAC_STATUS0 5
+#define TRAC_STATUS1 6
+#define TRAC_STATUS2 7
+
+#define TRX_CTRL_0 _SFR_MEM8(0x143)
+#define PMU_IF_INV 4
+#define PMU_START 5
+#define PMU_EN  6
+#define Res7    7
+
+#define TRX_CTRL_1 _SFR_MEM8(0x144)
+#define PLL_TX_FLT 4
+#define TX_AUTO_CRC_ON 5
+#define IRQ_2_EXT_EN 6
+#define PA_EXT_EN 7
+
+#define PHY_TX_PWR _SFR_MEM8(0x145)
+#define TX_PWR0 0
+#define TX_PWR1 1
+#define TX_PWR2 2
+#define TX_PWR3 3
+
+#define PHY_RSSI _SFR_MEM8(0x146)
+#define RSSI0   0
+#define RSSI1   1
+#define RSSI2   2
+#define RSSI3   3
+#define RSSI4   4
+#define RND_VALUE0 5
+#define RND_VALUE1 6
+#define RX_CRC_VALID 7
+
+#define PHY_ED_LEVEL _SFR_MEM8(0x147)
+#define ED_LEVEL0 0
+#define ED_LEVEL1 1
+#define ED_LEVEL2 2
+#define ED_LEVEL3 3
+#define ED_LEVEL4 4
+#define ED_LEVEL5 5
+#define ED_LEVEL6 6
+#define ED_LEVEL7 7
+
+#define PHY_CC_CCA _SFR_MEM8(0x148)
+#define CHANNEL0 0
+#define CHANNEL1 1
+#define CHANNEL2 2
+#define CHANNEL3 3
+#define CHANNEL4 4
+#define CCA_MODE0 5
+#define CCA_MODE1 6
+#define CCA_REQUEST 7
+
+#define CCA_THRES _SFR_MEM8(0x149)
+#define CCA_ED_THRES0 0
+#define CCA_ED_THRES1 1
+#define CCA_ED_THRES2 2
+#define CCA_ED_THRES3 3
+#define CCA_CS_THRES0 4
+#define CCA_CS_THRES1 5
+#define CCA_CS_THRES2 6
+#define CCA_CS_THRES3 7
+
+#define RX_CTRL _SFR_MEM8(0x14A)
+#define PDT_THRES0 0
+#define PDT_THRES1 1
+#define PDT_THRES2 2
+#define PDT_THRES3 3
+
+#define SFD_VALUE _SFR_MEM8(0x14B)
+#define SFD_VALUE0 0
+#define SFD_VALUE1 1
+#define SFD_VALUE2 2
+#define SFD_VALUE3 3
+#define SFD_VALUE4 4
+#define SFD_VALUE5 5
+#define SFD_VALUE6 6
+#define SFD_VALUE7 7
+
+#define TRX_CTRL_2 _SFR_MEM8(0x14C)
+#define OQPSK_DATA_RATE0 0
+#define OQPSK_DATA_RATE1 1
+#define RX_SAFE_MODE 7
+
+#define ANT_DIV _SFR_MEM8(0x14D)
+#define ANT_CTRL0 0
+#define ANT_CTRL1 1
+#define ANT_EXT_SW_EN 2
+#define ANT_DIV_EN 3
+#define ANT_SEL 7
+
+#define IRQ_MASK _SFR_MEM8(0x14E)
+#define PLL_LOCK_EN 0
+#define PLL_UNLOCK_EN 1
+#define RX_START_EN 2
+#define RX_END_EN 3
+#define CCA_ED_DONE_EN 4
+#define AMI_EN  5
+#define TX_END_EN 6
+#define AWAKE_EN 7
+
+#define IRQ_STATUS _SFR_MEM8(0x14F)
+#define PLL_LOCK 0
+#define PLL_UNLOCK 1
+#define RX_START 2
+#define RX_END  3
+#define CCA_ED_DONE 4
+#define AMI     5
+#define TX_END  6
+#define AWAKE   7
+
+#define VREG_CTRL _SFR_MEM8(0x150)
+#define DVDD_OK 2
+#define DVREG_EXT 3
+#define AVDD_OK 6
+#define AVREG_EXT 7
+
+#define BATMON  _SFR_MEM8(0x151)
+#define BATMON_VTH0 0
+#define BATMON_VTH1 1
+#define BATMON_VTH2 2
+#define BATMON_VTH3 3
+#define BATMON_HR 4
+#define BATMON_OK 5
+#define BAT_LOW_EN 6
+#define BAT_LOW 7
+
+#define XOSC_CTRL _SFR_MEM8(0x152)
+#define XTAL_TRIM0 0
+#define XTAL_TRIM1 1
+#define XTAL_TRIM2 2
+#define XTAL_TRIM3 3
+#define XTAL_MODE0 4
+#define XTAL_MODE1 5
+#define XTAL_MODE2 6
+#define XTAL_MODE3 7
+
+#define CC_CTRL_0 _SFR_MEM8(0x153)
+#define CC_NUMBER0 0
+#define CC_NUMBER1 1
+#define CC_NUMBER2 2
+#define CC_NUMBER3 3
+#define CC_NUMBER4 4
+#define CC_NUMBER5 5
+#define CC_NUMBER6 6
+#define CC_NUMBER7 7
+
+#define CC_CTRL_1 _SFR_MEM8(0x154)
+#define CC_BAND0 0
+#define CC_BAND1 1
+#define CC_BAND2 2
+#define CC_BAND3 3
+
+#define RX_SYN  _SFR_MEM8(0x155)
+#define RX_PDT_LEVEL0 0
+#define RX_PDT_LEVEL1 1
+#define RX_PDT_LEVEL2 2
+#define RX_PDT_LEVEL3 3
+#define RX_OVERRIDE 6
+#define RX_PDT_DIS 7
+
+#define TRX_RPC _SFR_MEM8(0x156)
+#define XAH_RPC_EN 0
+#define IPAN_RPC_EN 1
+#define PLL_RPC_EN 3
+#define PDT_RPC_EN 4
+#define RX_RPC_EN 5
+#define RX_RPC_CTRL0 6
+#define RX_RPC_CTRL1 7
+
+#define XAH_CTRL_1 _SFR_MEM8(0x157)
+#define AACK_PROM_MODE 1
+#define AACK_ACK_TIME 2
+#define AACK_UPLD_RES_FT 4
+#define AACK_FLTR_RES_FT 5
+
+#define FTN_CTRL _SFR_MEM8(0x158)
+#define FTN_START 7
+
+/* Reserved [0x159] */
+
+#define PLL_CF  _SFR_MEM8(0x15A)
+#define PLL_CF_START 7
+
+#define PLL_DCU _SFR_MEM8(0x15B)
+#define PLL_DCU_START 7
+
+#define PART_NUM _SFR_MEM8(0x15C)
+#define PART_NUM0 0
+#define PART_NUM1 1
+#define PART_NUM2 2
+#define PART_NUM3 3
+#define PART_NUM4 4
+#define PART_NUM5 5
+#define PART_NUM6 6
+#define PART_NUM7 7
+
+#define VERSION_NUM _SFR_MEM8(0x15D)
+#define VERSION_NUM0 0
+#define VERSION_NUM1 1
+#define VERSION_NUM2 2
+#define VERSION_NUM3 3
+#define VERSION_NUM4 4
+#define VERSION_NUM5 5
+#define VERSION_NUM6 6
+#define VERSION_NUM7 7
+
+#define MAN_ID_0 _SFR_MEM8(0x15E)
+#define MAN_ID_00 0
+#define MAN_ID_01 1
+#define MAN_ID_02 2
+#define MAN_ID_03 3
+#define MAN_ID_04 4
+#define MAN_ID_05 5
+#define MAN_ID_06 6
+#define MAN_ID_07 7
+
+#define MAN_ID_1 _SFR_MEM8(0x15F)
+#define MAN_ID_10 0
+#define MAN_ID_11 1
+#define MAN_ID_12 2
+#define MAN_ID_13 3
+#define MAN_ID_14 4
+#define MAN_ID_15 5
+#define MAN_ID_16 6
+#define MAN_ID_17 7
+
+#define SHORT_ADDR_0 _SFR_MEM8(0x160)
+#define SHORT_ADDR_00 0
+#define SHORT_ADDR_01 1
+#define SHORT_ADDR_02 2
+#define SHORT_ADDR_03 3
+#define SHORT_ADDR_04 4
+#define SHORT_ADDR_05 5
+#define SHORT_ADDR_06 6
+#define SHORT_ADDR_07 7
+
+#define SHORT_ADDR_1 _SFR_MEM8(0x161)
+#define SHORT_ADDR_10 0
+#define SHORT_ADDR_11 1
+#define SHORT_ADDR_12 2
+#define SHORT_ADDR_13 3
+#define SHORT_ADDR_14 4
+#define SHORT_ADDR_15 5
+#define SHORT_ADDR_16 6
+#define SHORT_ADDR_17 7
+
+#define PAN_ID_0 _SFR_MEM8(0x162)
+#define PAN_ID_00 0
+#define PAN_ID_01 1
+#define PAN_ID_02 2
+#define PAN_ID_03 3
+#define PAN_ID_04 4
+#define PAN_ID_05 5
+#define PAN_ID_06 6
+#define PAN_ID_07 7
+
+#define PAN_ID_1 _SFR_MEM8(0x163)
+#define PAN_ID_10 0
+#define PAN_ID_11 1
+#define PAN_ID_12 2
+#define PAN_ID_13 3
+#define PAN_ID_14 4
+#define PAN_ID_15 5
+#define PAN_ID_16 6
+#define PAN_ID_17 7
+
+#define IEEE_ADDR_0 _SFR_MEM8(0x164)
+#define IEEE_ADDR_00 0
+#define IEEE_ADDR_01 1
+#define IEEE_ADDR_02 2
+#define IEEE_ADDR_03 3
+#define IEEE_ADDR_04 4
+#define IEEE_ADDR_05 5
+#define IEEE_ADDR_06 6
+#define IEEE_ADDR_07 7
+
+#define IEEE_ADDR_1 _SFR_MEM8(0x165)
+#define IEEE_ADDR_10 0
+#define IEEE_ADDR_11 1
+#define IEEE_ADDR_12 2
+#define IEEE_ADDR_13 3
+#define IEEE_ADDR_14 4
+#define IEEE_ADDR_15 5
+#define IEEE_ADDR_16 6
+#define IEEE_ADDR_17 7
+
+#define IEEE_ADDR_2 _SFR_MEM8(0x166)
+#define IEEE_ADDR_20 0
+#define IEEE_ADDR_21 1
+#define IEEE_ADDR_22 2
+#define IEEE_ADDR_23 3
+#define IEEE_ADDR_24 4
+#define IEEE_ADDR_25 5
+#define IEEE_ADDR_26 6
+#define IEEE_ADDR_27 7
+
+#define IEEE_ADDR_3 _SFR_MEM8(0x167)
+#define IEEE_ADDR_30 0
+#define IEEE_ADDR_31 1
+#define IEEE_ADDR_32 2
+#define IEEE_ADDR_33 3
+#define IEEE_ADDR_34 4
+#define IEEE_ADDR_35 5
+#define IEEE_ADDR_36 6
+#define IEEE_ADDR_37 7
+
+#define IEEE_ADDR_4 _SFR_MEM8(0x168)
+#define IEEE_ADDR_40 0
+#define IEEE_ADDR_41 1
+#define IEEE_ADDR_42 2
+#define IEEE_ADDR_43 3
+#define IEEE_ADDR_44 4
+#define IEEE_ADDR_45 5
+#define IEEE_ADDR_46 6
+#define IEEE_ADDR_47 7
+
+#define IEEE_ADDR_5 _SFR_MEM8(0x169)
+#define IEEE_ADDR_50 0
+#define IEEE_ADDR_51 1
+#define IEEE_ADDR_52 2
+#define IEEE_ADDR_53 3
+#define IEEE_ADDR_54 4
+#define IEEE_ADDR_55 5
+#define IEEE_ADDR_56 6
+#define IEEE_ADDR_57 7
+
+#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
+#define IEEE_ADDR_60 0
+#define IEEE_ADDR_61 1
+#define IEEE_ADDR_62 2
+#define IEEE_ADDR_63 3
+#define IEEE_ADDR_64 4
+#define IEEE_ADDR_65 5
+#define IEEE_ADDR_66 6
+#define IEEE_ADDR_67 7
+
+#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
+#define IEEE_ADDR_70 0
+#define IEEE_ADDR_71 1
+#define IEEE_ADDR_72 2
+#define IEEE_ADDR_73 3
+#define IEEE_ADDR_74 4
+#define IEEE_ADDR_75 5
+#define IEEE_ADDR_76 6
+#define IEEE_ADDR_77 7
+
+#define XAH_CTRL_0 _SFR_MEM8(0x16C)
+#define SLOTTED_OPERATION 0
+#define MAX_CSMA_RETRIES0 1
+#define MAX_CSMA_RETRIES1 2
+#define MAX_CSMA_RETRIES2 3
+#define MAX_FRAME_RETRIES0 4
+#define MAX_FRAME_RETRIES1 5
+#define MAX_FRAME_RETRIES2 6
+#define MAX_FRAME_RETRIES3 7
+
+#define CSMA_SEED_0 _SFR_MEM8(0x16D)
+#define CSMA_SEED_00 0
+#define CSMA_SEED_01 1
+#define CSMA_SEED_02 2
+#define CSMA_SEED_03 3
+#define CSMA_SEED_04 4
+#define CSMA_SEED_05 5
+#define CSMA_SEED_06 6
+#define CSMA_SEED_07 7
+
+#define CSMA_SEED_1 _SFR_MEM8(0x16E)
+#define CSMA_SEED_10 0
+#define CSMA_SEED_11 1
+#define CSMA_SEED_12 2
+#define AACK_I_AM_COORD 3
+#define AACK_DIS_ACK 4
+#define AACK_SET_PD 5
+#define AACK_FVN_MODE0 6
+#define AACK_FVN_MODE1 7
+
+#define CSMA_BE _SFR_MEM8(0x16F)
+#define MIN_BE0 0
+#define MIN_BE1 1
+#define MIN_BE2 2
+#define MIN_BE3 3
+#define MAX_BE0 4
+#define MAX_BE1 5
+#define MAX_BE2 6
+#define MAX_BE3 7
+
+/* Reserved [0x170..0x175] */
+
+#define TST_CTRL_DIGI _SFR_MEM8(0x176)
+#define TST_CTRL_DIG0 0
+#define TST_CTRL_DIG1 1
+#define TST_CTRL_DIG2 2
+#define TST_CTRL_DIG3 3
+
+/* Reserved [0x177..0x17A] */
+
+#define TST_RX_LENGTH _SFR_MEM8(0x17B)
+#define RX_LENGTH0 0
+#define RX_LENGTH1 1
+#define RX_LENGTH2 2
+#define RX_LENGTH3 3
+#define RX_LENGTH4 4
+#define RX_LENGTH5 5
+#define RX_LENGTH6 6
+#define RX_LENGTH7 7
+
+/* Reserved [0x17C..0x17F] */
+
+#define TRXFBST _SFR_MEM8(0x180)
 
-/* Start of frame buffer */
-#define TRXFBST                         _SFR_MEM8(0x180)
+/* Reserved [0x181..0x1FE] */
 
-  /* TRXFBST */
+#define TRXFBEND _SFR_MEM8(0x1FF)
 
-#define TRXFBST0                        0
-#define TRXFBST1                        1
-#define TRXFBST2                        2
-#define TRXFBST3                        3
-#define TRXFBST4                        4
-#define TRXFBST5                        5
-#define TRXFBST6                        6
-#define TRXFBST7                        7
 
-/* End of frame buffer */
-#define TRXFBEND                        _SFR_MEM8(0x1FF)
 
-  /* TRXFBEND */
+/* Values and associated defines */
 
-#define TRXFBEND0                       0
-#define TRXFBEND1                       1
-#define TRXFBEND2                       2
-#define TRXFBEND3                       3
-#define TRXFBEND4                       4
-#define TRXFBEND5                       5
-#define TRXFBEND6                       6
-#define TRXFBEND7                       7
 
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
-
-#define _VECTORS_SIZE                  308
-
 /* External Interrupt Request 0 */
-#define INT0_vect                       _VECTOR(1)
-#define INT0_vect_num                   1
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
 
 /* External Interrupt Request 1 */
-#define INT1_vect                       _VECTOR(2)
-#define INT1_vect_num                   2
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
 
 /* External Interrupt Request 2 */
-#define INT2_vect                       _VECTOR(3)
-#define INT2_vect_num                   3
+#define INT2_vect            _VECTOR(3)
+#define INT2_vect_num        3
 
 /* External Interrupt Request 3 */
-#define INT3_vect                       _VECTOR(4)
-#define INT3_vect_num                   4
+#define INT3_vect            _VECTOR(4)
+#define INT3_vect_num        4
 
 /* External Interrupt Request 4 */
-#define INT4_vect                       _VECTOR(5)
-#define INT4_vect_num                   5
+#define INT4_vect            _VECTOR(5)
+#define INT4_vect_num        5
 
 /* External Interrupt Request 5 */
-#define INT5_vect                       _VECTOR(6)
-#define INT5_vect_num                   6
+#define INT5_vect            _VECTOR(6)
+#define INT5_vect_num        6
 
 /* External Interrupt Request 6 */
-#define INT6_vect                       _VECTOR(7)
-#define INT6_vect_num                   7
+#define INT6_vect            _VECTOR(7)
+#define INT6_vect_num        7
 
 /* External Interrupt Request 7 */
-#define INT7_vect                       _VECTOR(8)
-#define INT7_vect_num                   8
+#define INT7_vect            _VECTOR(8)
+#define INT7_vect_num        8
 
 /* Pin Change Interrupt Request 0 */
-#define PCINT0_vect                     _VECTOR(9)
-#define PCINT0_vect_num                 9
+#define PCINT0_vect            _VECTOR(9)
+#define PCINT0_vect_num        9
 
 /* Pin Change Interrupt Request 1 */
-#define PCINT1_vect                     _VECTOR(10)
-#define PCINT1_vect_num                 10
+#define PCINT1_vect            _VECTOR(10)
+#define PCINT1_vect_num        10
 
 /* Pin Change Interrupt Request 2 */
-#define PCINT2_vect                     _VECTOR(11)
-#define PCINT2_vect_num                 11
+#define PCINT2_vect            _VECTOR(11)
+#define PCINT2_vect_num        11
 
 /* Watchdog Time-out Interrupt */
-#define WDT_vect                        _VECTOR(12)
-#define WDT_vect_num                    12
+#define WDT_vect            _VECTOR(12)
+#define WDT_vect_num        12
 
 /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect               _VECTOR(13)
-#define TIMER2_COMPA_vect_num           13
+#define TIMER2_COMPA_vect            _VECTOR(13)
+#define TIMER2_COMPA_vect_num        13
 
 /* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect               _VECTOR(14)
-#define TIMER2_COMPB_vect_num           14
+#define TIMER2_COMPB_vect            _VECTOR(14)
+#define TIMER2_COMPB_vect_num        14
 
 /* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect                 _VECTOR(15)
-#define TIMER2_OVF_vect_num             15
+#define TIMER2_OVF_vect            _VECTOR(15)
+#define TIMER2_OVF_vect_num        15
 
 /* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect                _VECTOR(16)
-#define TIMER1_CAPT_vect_num            16
+#define TIMER1_CAPT_vect            _VECTOR(16)
+#define TIMER1_CAPT_vect_num        16
 
 /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect               _VECTOR(17)
-#define TIMER1_COMPA_vect_num           17
+#define TIMER1_COMPA_vect            _VECTOR(17)
+#define TIMER1_COMPA_vect_num        17
 
 /* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect               _VECTOR(18)
-#define TIMER1_COMPB_vect_num           18
+#define TIMER1_COMPB_vect            _VECTOR(18)
+#define TIMER1_COMPB_vect_num        18
 
 /* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect               _VECTOR(19)
-#define TIMER1_COMPC_vect_num           19
+#define TIMER1_COMPC_vect            _VECTOR(19)
+#define TIMER1_COMPC_vect_num        19
 
 /* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect                 _VECTOR(20)
-#define TIMER1_OVF_vect_num             20
+#define TIMER1_OVF_vect            _VECTOR(20)
+#define TIMER1_OVF_vect_num        20
 
 /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect               _VECTOR(21)
-#define TIMER0_COMPA_vect_num           21
+#define TIMER0_COMPA_vect            _VECTOR(21)
+#define TIMER0_COMPA_vect_num        21
 
 /* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect               _VECTOR(22)
-#define TIMER0_COMPB_vect_num           22
+#define TIMER0_COMPB_vect            _VECTOR(22)
+#define TIMER0_COMPB_vect_num        22
 
 /* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect                 _VECTOR(23)
-#define TIMER0_OVF_vect_num             23
+#define TIMER0_OVF_vect            _VECTOR(23)
+#define TIMER0_OVF_vect_num        23
 
 /* SPI Serial Transfer Complete */
-#define SPI_STC_vect                    _VECTOR(24)
-#define SPI_STC_vect_num                24
+#define SPI_STC_vect            _VECTOR(24)
+#define SPI_STC_vect_num        24
 
 /* USART0, Rx Complete */
-#define USART0_RX_vect                  _VECTOR(25)
-#define USART0_RX_vect_num              25
+#define USART0_RX_vect            _VECTOR(25)
+#define USART0_RX_vect_num        25
 
 /* USART0 Data register Empty */
-#define USART0_UDRE_vect                _VECTOR(26)
-#define USART0_UDRE_vect_num            26
+#define USART0_UDRE_vect            _VECTOR(26)
+#define USART0_UDRE_vect_num        26
 
 /* USART0, Tx Complete */
-#define USART0_TX_vect                  _VECTOR(27)
-#define USART0_TX_vect_num              27
+#define USART0_TX_vect            _VECTOR(27)
+#define USART0_TX_vect_num        27
 
 /* Analog Comparator */
-#define ANALOG_COMP_vect                _VECTOR(28)
-#define ANALOG_COMP_vect_num            28
+#define ANALOG_COMP_vect            _VECTOR(28)
+#define ANALOG_COMP_vect_num        28
 
 /* ADC Conversion Complete */
-#define ADC_vect                        _VECTOR(29)
-#define ADC_vect_num                    29
+#define ADC_vect            _VECTOR(29)
+#define ADC_vect_num        29
 
 /* EEPROM Ready */
-#define EE_READY_vect                   _VECTOR(30)
-#define EE_READY_vect_num               30
+#define EE_READY_vect            _VECTOR(30)
+#define EE_READY_vect_num        30
 
 /* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect                _VECTOR(31)
-#define TIMER3_CAPT_vect_num            31
+#define TIMER3_CAPT_vect            _VECTOR(31)
+#define TIMER3_CAPT_vect_num        31
 
 /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect               _VECTOR(32)
-#define TIMER3_COMPA_vect_num           32
+#define TIMER3_COMPA_vect            _VECTOR(32)
+#define TIMER3_COMPA_vect_num        32
 
 /* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect               _VECTOR(33)
-#define TIMER3_COMPB_vect_num           33
+#define TIMER3_COMPB_vect            _VECTOR(33)
+#define TIMER3_COMPB_vect_num        33
 
 /* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect               _VECTOR(34)
-#define TIMER3_COMPC_vect_num           34
+#define TIMER3_COMPC_vect            _VECTOR(34)
+#define TIMER3_COMPC_vect_num        34
 
 /* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect                 _VECTOR(35)
-#define TIMER3_OVF_vect_num             35
+#define TIMER3_OVF_vect            _VECTOR(35)
+#define TIMER3_OVF_vect_num        35
 
 /* USART1, Rx Complete */
-#define USART1_RX_vect                  _VECTOR(36)
-#define USART1_RX_vect_num              36
+#define USART1_RX_vect            _VECTOR(36)
+#define USART1_RX_vect_num        36
 
 /* USART1 Data register Empty */
-#define USART1_UDRE_vect                _VECTOR(37)
-#define USART1_UDRE_vect_num            37
+#define USART1_UDRE_vect            _VECTOR(37)
+#define USART1_UDRE_vect_num        37
 
 /* USART1, Tx Complete */
-#define USART1_TX_vect                  _VECTOR(38)
-#define USART1_TX_vect_num              38
+#define USART1_TX_vect            _VECTOR(38)
+#define USART1_TX_vect_num        38
 
 /* 2-wire Serial Interface */
-#define TWI_vect                        _VECTOR(39)
-#define TWI_vect_num                    39
+#define TWI_vect            _VECTOR(39)
+#define TWI_vect_num        39
 
 /* Store Program Memory Read */
-#define SPM_READY_vect                  _VECTOR(40)
-#define SPM_READY_vect_num              40
+#define SPM_READY_vect            _VECTOR(40)
+#define SPM_READY_vect_num        40
 
 /* Timer/Counter4 Capture Event */
-#define TIMER4_CAPT_vect                _VECTOR(41)
-#define TIMER4_CAPT_vect_num            41
+#define TIMER4_CAPT_vect            _VECTOR(41)
+#define TIMER4_CAPT_vect_num        41
 
 /* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPA_vect               _VECTOR(42)
-#define TIMER4_COMPA_vect_num           42
+#define TIMER4_COMPA_vect            _VECTOR(42)
+#define TIMER4_COMPA_vect_num        42
 
 /* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPB_vect               _VECTOR(43)
-#define TIMER4_COMPB_vect_num           43
+#define TIMER4_COMPB_vect            _VECTOR(43)
+#define TIMER4_COMPB_vect_num        43
 
 /* Timer/Counter4 Compare Match C */
-#define TIMER4_COMPC_vect               _VECTOR(44)
-#define TIMER4_COMPC_vect_num           44
+#define TIMER4_COMPC_vect            _VECTOR(44)
+#define TIMER4_COMPC_vect_num        44
 
 /* Timer/Counter4 Overflow */
-#define TIMER4_OVF_vect                 _VECTOR(45)
-#define TIMER4_OVF_vect_num             45
+#define TIMER4_OVF_vect            _VECTOR(45)
+#define TIMER4_OVF_vect_num        45
 
 /* Timer/Counter5 Capture Event */
-#define TIMER5_CAPT_vect                _VECTOR(46)
-#define TIMER5_CAPT_vect_num            46
+#define TIMER5_CAPT_vect            _VECTOR(46)
+#define TIMER5_CAPT_vect_num        46
 
 /* Timer/Counter5 Compare Match A */
-#define TIMER5_COMPA_vect               _VECTOR(47)
-#define TIMER5_COMPA_vect_num           47
+#define TIMER5_COMPA_vect            _VECTOR(47)
+#define TIMER5_COMPA_vect_num        47
 
 /* Timer/Counter5 Compare Match B */
-#define TIMER5_COMPB_vect               _VECTOR(48)
-#define TIMER5_COMPB_vect_num           48
+#define TIMER5_COMPB_vect            _VECTOR(48)
+#define TIMER5_COMPB_vect_num        48
 
 /* Timer/Counter5 Compare Match C */
-#define TIMER5_COMPC_vect               _VECTOR(49)
-#define TIMER5_COMPC_vect_num           49
+#define TIMER5_COMPC_vect            _VECTOR(49)
+#define TIMER5_COMPC_vect_num        49
 
 /* Timer/Counter5 Overflow */
-#define TIMER5_OVF_vect                 _VECTOR(50)
-#define TIMER5_OVF_vect_num             50
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_51_vect                _VECTOR(51)
-#define RESERVED_51_vect_num            51
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_52_vect                _VECTOR(52)
-#define RESERVED_52_vect_num            52
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_53_vect                _VECTOR(53)
-#define RESERVED_53_vect_num            53
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_54_vect                _VECTOR(54)
-#define RESERVED_54_vect_num            54
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_55_vect                _VECTOR(55)
-#define RESERVED_55_vect_num            55
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_56_vect                _VECTOR(56)
-#define RESERVED_56_vect_num            56
+#define TIMER5_OVF_vect            _VECTOR(50)
+#define TIMER5_OVF_vect_num        50
 
 /* TRX24 - PLL lock interrupt */
-#define TRX24_PLL_LOCK_vect             _VECTOR(57)
-#define TRX24_PLL_LOCK_vect_num         57
+#define TRX24_PLL_LOCK_vect            _VECTOR(57)
+#define TRX24_PLL_LOCK_vect_num        57
 
 /* TRX24 - PLL unlock interrupt */
-#define TRX24_PLL_UNLOCK_vect           _VECTOR(58)
-#define TRX24_PLL_UNLOCK_vect_num       58
+#define TRX24_PLL_UNLOCK_vect            _VECTOR(58)
+#define TRX24_PLL_UNLOCK_vect_num        58
 
 /* TRX24 - Receive start interrupt */
-#define TRX24_RX_START_vect             _VECTOR(59)
-#define TRX24_RX_START_vect_num         59
+#define TRX24_RX_START_vect            _VECTOR(59)
+#define TRX24_RX_START_vect_num        59
 
 /* TRX24 - RX_END interrupt */
-#define TRX24_RX_END_vect               _VECTOR(60)
-#define TRX24_RX_END_vect_num           60
+#define TRX24_RX_END_vect            _VECTOR(60)
+#define TRX24_RX_END_vect_num        60
 
 /* TRX24 - CCA/ED done interrupt */
-#define TRX24_CCA_ED_DONE_vect          _VECTOR(61)
-#define TRX24_CCA_ED_DONE_vect_num      61
+#define TRX24_CCA_ED_DONE_vect            _VECTOR(61)
+#define TRX24_CCA_ED_DONE_vect_num        61
 
 /* TRX24 - XAH - AMI */
-#define TRX24_XAH_AMI_vect              _VECTOR(62)
-#define TRX24_XAH_AMI_vect_num          62
+#define TRX24_XAH_AMI_vect            _VECTOR(62)
+#define TRX24_XAH_AMI_vect_num        62
 
 /* TRX24 - TX_END interrupt */
-#define TRX24_TX_END_vect               _VECTOR(63)
-#define TRX24_TX_END_vect_num           63
+#define TRX24_TX_END_vect            _VECTOR(63)
+#define TRX24_TX_END_vect_num        63
 
 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
-#define TRX24_AWAKE_vect                _VECTOR(64)
-#define TRX24_AWAKE_vect_num            64
+#define TRX24_AWAKE_vect            _VECTOR(64)
+#define TRX24_AWAKE_vect_num        64
 
 /* Symbol counter - compare match 1 interrupt */
-#define SCNT_CMP1_vect                  _VECTOR(65)
-#define SCNT_CMP1_vect_num              65
+#define SCNT_CMP1_vect            _VECTOR(65)
+#define SCNT_CMP1_vect_num        65
 
 /* Symbol counter - compare match 2 interrupt */
-#define SCNT_CMP2_vect                  _VECTOR(66)
-#define SCNT_CMP2_vect_num              66
+#define SCNT_CMP2_vect            _VECTOR(66)
+#define SCNT_CMP2_vect_num        66
 
 /* Symbol counter - compare match 3 interrupt */
-#define SCNT_CMP3_vect                  _VECTOR(67)
-#define SCNT_CMP3_vect_num              67
+#define SCNT_CMP3_vect            _VECTOR(67)
+#define SCNT_CMP3_vect_num        67
 
 /* Symbol counter - overflow interrupt */
-#define SCNT_OVFL_vect                  _VECTOR(68)
-#define SCNT_OVFL_vect_num              68
+#define SCNT_OVFL_vect            _VECTOR(68)
+#define SCNT_OVFL_vect_num        68
 
 /* Symbol counter - backoff interrupt */
-#define SCNT_BACKOFF_vect               _VECTOR(69)
-#define SCNT_BACKOFF_vect_num           69
+#define SCNT_BACKOFF_vect            _VECTOR(69)
+#define SCNT_BACKOFF_vect_num        69
 
 /* AES engine ready interrupt */
-#define AES_READY_vect                  _VECTOR(70)
-#define AES_READY_vect_num              70
+#define AES_READY_vect            _VECTOR(70)
+#define AES_READY_vect_num        70
 
 /* Battery monitor indicates supply voltage below threshold */
-#define BAT_LOW_vect                    _VECTOR(71)
-#define BAT_LOW_vect_num                71
+#define BAT_LOW_vect            _VECTOR(71)
+#define BAT_LOW_vect_num        71
 
 /* TRX24 TX start interrupt */
-#define TRX24_TX_START_vect             _VECTOR(72)
-#define TRX24_TX_START_vect_num         72
+#define TRX24_TX_START_vect            _VECTOR(72)
+#define TRX24_TX_START_vect_num        72
 
 /* Address match interrupt of address filter 0 */
-#define TRX24_AMI0_vect                 _VECTOR(73)
-#define TRX24_AMI0_vect_num             73
+#define TRX24_AMI0_vect            _VECTOR(73)
+#define TRX24_AMI0_vect_num        73
 
 /* Address match interrupt of address filter 1 */
-#define TRX24_AMI1_vect                 _VECTOR(74)
-#define TRX24_AMI1_vect_num             74
+#define TRX24_AMI1_vect            _VECTOR(74)
+#define TRX24_AMI1_vect_num        74
 
 /* Address match interrupt of address filter 2 */
-#define TRX24_AMI2_vect                 _VECTOR(75)
-#define TRX24_AMI2_vect_num             75
+#define TRX24_AMI2_vect            _VECTOR(75)
+#define TRX24_AMI2_vect_num        75
 
 /* Address match interrupt of address filter 3 */
-#define TRX24_AMI3_vect                 _VECTOR(76)
-#define TRX24_AMI3_vect_num             76
+#define TRX24_AMI3_vect            _VECTOR(76)
+#define TRX24_AMI3_vect_num        76
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 308
+#else
+#  define _VECTORS_SIZE 308U
+#endif
 
 
-/* memory parameters */
+/* Constants */
 
-#define SPM_PAGESIZE                    (256)
-#define RAMSTART                        (0x200)
-#define RAMSIZE                         (0x2000)
-#define RAMEND                          (0x21FF)
-#define XRAMSTART                       (0x0000)
-#define XRAMSIZE                        (0x0000)
-#define XRAMEND                         RAMEND
-#define E2END                           (0x7FF)
-#define E2PAGESIZE                      (0x08)
-#define FLASHEND                        (0xffff)
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 256
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0xFFFF
+#else
+#  define SPM_PAGESIZE 256U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0xFFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      8192
+#  define RAMEND       0x21FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      8192U
+#  define RAMEND       0x21FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      2048
+#  define E2PAGESIZE  8
+#  define E2END       0x07FF
+#else
+#  define E2START     0U
+#  define E2SIZE      2048U
+#  define E2PAGESIZE  8U
+#  define E2END       0x07FFU
+#endif
+#define XRAMEND      RAMEND
 
 
 /* Fuses */
 
 #define FUSE_MEMORY_SIZE 3
 
-/* LFUSE Byte */
-#define FUSE_CKSEL0     ~_BV(0) /* Select Clock Source */
-#define FUSE_CKSEL1     ~_BV(1) /* Select Clock Source */
-#define FUSE_CKSEL2     ~_BV(2) /* Select Clock Source */
-#define FUSE_CKSEL3     ~_BV(3) /* Select Clock Source */
-#define FUSE_SUT0       ~_BV(4) /* Select start-up time */
-#define FUSE_SUT1       ~_BV(5) /* Select start-up time */
-#define FUSE_CKOUT      ~_BV(6) /* Clock output */
-#define FUSE_CKDIV8     ~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* HFUSE Byte */
-#define FUSE_BOOTRST    ~_BV(0) /* Select Reset Vector */
-#define FUSE_BOOTSZ0    ~_BV(1) /* Select Boot Size */
-#define FUSE_BOOTSZ1    ~_BV(2) /* Select Boot Size */
-#define FUSE_EESAVE     ~_BV(3) /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      ~_BV(4) /* Watchdog timer always on */
-#define FUSE_SPIEN      ~_BV(5) /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN     ~_BV(6) /* Enable JTAG */
-#define FUSE_OCDEN      ~_BV(7) /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* EFUSE Byte */
-#define FUSE_BODLEVEL0  ~_BV(0) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  ~_BV(1) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  ~_BV(2) /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
+/* Low Fuse Byte */
+#define FUSE_CKSEL_SUT0  (unsigned char)~_BV(0)
+#define FUSE_CKSEL_SUT1  (unsigned char)~_BV(1)
+#define FUSE_CKSEL_SUT2  (unsigned char)~_BV(2)
+#define FUSE_CKSEL_SUT3  (unsigned char)~_BV(3)
+#define FUSE_CKSEL_SUT4  (unsigned char)~_BV(4)
+#define FUSE_CKSEL_SUT5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_CKSEL_SUT0 & FUSE_CKSEL_SUT2 & FUSE_CKSEL_SUT3 & FUSE_CKSEL_SUT4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BODLEVEL0)
 
 
 
 /* Lock Bits */
-
+#define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST
-#define __LOCK_BITS_EXIST
 
 
 /* Signature */
-
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0xA6
 #define SIGNATURE_2 0x03
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 
-#endif /* _AVR_IOM644RFR2_H_ */
+
+#endif /* #ifdef _AVR_ATMEGA644RFR2_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom645.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom645.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom645.h 2235 2011-03-17 04:13:14Z arcanum $ */
 
 /* avr/iom645.h - definitions for ATmega645 */
 
@@ -872,12 +872,10 @@
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM645_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom6450.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom6450.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom6450.h 2235 2011-03-17 04:13:14Z arcanum $ */
 
 /* avr/iom6450.h - definitions for ATmega6450 */
 
@@ -969,12 +969,10 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM6450_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom6450a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom6450a.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom6450.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom6450p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom6450p.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom6450.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom645a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom645a.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom645.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom645p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom645p.h
@@ -0,0 +1,38 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom645.h"
+
+// MCUCR
+#define BODS    5
+#define BODSE   6
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom649.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom649.h
@@ -31,8 +31,6 @@
 
 /* avr/iom649.h - definitions for ATmega649 */
 
-/* $Id$ */
-
 #ifndef _AVR_IOM649_H_
 #define _AVR_IOM649_H_ 1
 
@@ -1054,12 +1052,10 @@
 
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM649_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom6490.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom6490.h
@@ -31,8 +31,6 @@
 
 /* avr/iom6490.h - definitions for ATmega6490 */
 
-/* $Id$ */
-
 #ifndef _AVR_IOM6490_H_
 #define _AVR_IOM6490_H_ 1
 
@@ -1175,12 +1173,10 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x04
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM6490_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom6490a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom6490a.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom6490.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom6490p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom6490p.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom6490.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom649a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom649a.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom649.h"
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom649p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom649p.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom649p.h 2146 2010-06-09 06:38:54Z joerg_wunsch $ */
 
 /* avr/iom649p.h - definitions for ATmega649 */
 
@@ -42,7 +42,7 @@
 #  define _AVR_IOXXX_H_ "iom649p.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega649_H_
@@ -325,7 +325,8 @@
 #define EEAR10 2
 
 #define GTCCR _SFR_IO8(0x23)
-#define PSR310 0
+#define PSR310 0 /* Kept for legacy reasons */
+#define PSR10 0
 #define PSR2 1
 #define TSM 7
 
@@ -1480,7 +1481,6 @@
 #define ADC0_PIN   PINF
 #define ADC0_BIT   0
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom64a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom64a.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA64A_H_INCLUDED
 #define _AVR_ATMEGA64A_H_INCLUDED
 
@@ -72,13 +55,29 @@
 
 #define DDRE    _SFR_IO8(0x02)
 #define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
 #define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
 #define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
 #define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
 #define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
 #define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
 #define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
 #define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
 
 #define PORTE   _SFR_IO8(0x03)
 #define PORTE7  7
@@ -182,13 +181,29 @@
 
 #define DDRD    _SFR_IO8(0x11)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x12)
 #define PORTD7  7
@@ -212,13 +227,29 @@
 
 #define DDRC    _SFR_IO8(0x14)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x15)
 #define PORTC7  7
@@ -242,13 +273,29 @@
 
 #define DDRB    _SFR_IO8(0x17)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x18)
 #define PORTB7  7
@@ -272,13 +319,29 @@
 
 #define DDRA    _SFR_IO8(0x1A)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x1B)
 #define PORTA7  7
@@ -493,13 +556,29 @@
 
 #define DDRF    _SFR_MEM8(0x61)
 #define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
 #define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
 #define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
 #define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
 #define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
 #define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
 #define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
 #define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
 
 #define PORTF   _SFR_MEM8(0x62)
 #define PORTF7  7
@@ -520,10 +599,20 @@
 
 #define DDRG    _SFR_MEM8(0x64)
 #define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
 #define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
 #define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
 #define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
 #define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
 
 #define PORTG   _SFR_MEM8(0x65)
 #define PORTG4  4
@@ -763,6 +852,16 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<2)
+#define SLEEP_MODE_ADC (0x02<<2)
+#define SLEEP_MODE_PWR_DOWN (0x04<<2)
+#define SLEEP_MODE_PWR_SAVE (0x06<<2)
+#define SLEEP_MODE_STANDBY (0x05<<2)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<2)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -901,21 +1000,44 @@
 #define SPM_READY_vect            _VECTOR(34)
 #define SPM_READY_vect_num        34
 
-#define _VECTORS_SIZE 140
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 140
+#else
+#  define _VECTORS_SIZE 140U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 256
-#define FLASHSTART   0x0000
-#define FLASHEND     0xFFFF
-#define RAMSTART     0x0100
-#define RAMSIZE      4096
-#define RAMEND       0x10FF
-#define E2START     0
-#define E2SIZE      2048
-#define E2PAGESIZE  8
-#define E2END       0x07FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 256
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0xFFFF
+#else
+#  define SPM_PAGESIZE 256U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0xFFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      4096
+#  define RAMEND       0x10FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      4096U
+#  define RAMEND       0x10FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      2048
+#  define E2PAGESIZE  8
+#  define E2END       0x07FF
+#else
+#  define E2START     0U
+#  define E2SIZE      2048U
+#  define E2PAGESIZE  8U
+#  define E2END       0x07FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -932,6 +1054,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_BODEN       (unsigned char)~_BV(6)
 #define FUSE_BODLEVEL    (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -942,10 +1066,14 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_JTAGEN      (unsigned char)~_BV(6)
 #define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_WDTON       (unsigned char)~_BV(0)
-#define FUSE_CompMode    (unsigned char)~_BV(1)
+#define FUSE_M103C       (unsigned char)~_BV(1)
+#define EFUSE_DEFAULT    (FUSE_M103C)
+
 
 
 /* Lock Bits */
@@ -959,20 +1087,8 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x02
 
-#define SLEEP_MODE_IDLE (0x00<<2)
-#define SLEEP_MODE_ADC (0x02<<2)
-#define SLEEP_MODE_PWR_DOWN (0x04<<2)
-#define SLEEP_MODE_PWR_SAVE (0x06<<2)
-#define SLEEP_MODE_STANDBY (0x05<<2)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<2)
 
 
-#define SLEEP_MODE_IDLE (0x00<<2)
-#define SLEEP_MODE_ADC (0x02<<2)
-#define SLEEP_MODE_PWR_DOWN (0x04<<2)
-#define SLEEP_MODE_PWR_SAVE (0x06<<2)
-#define SLEEP_MODE_STANDBY (0x05<<2)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<2)
 
 #endif /* #ifdef _AVR_ATMEGA64A_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom64c1.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom64c1.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom64c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */
 
 /* avr/iom64c1.h - definitions for ATmega64C1 */
 
@@ -1312,7 +1312,6 @@
 #define SIGNATURE_2 0x86
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom64hve.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom64hve.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom64hve.h 2086 2009-12-15 03:24:16Z arcanum $ */
 
 /* avr/iom64hve.h - definitions for ATmega64HVE */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom64hve2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom64hve2.h
@@ -1,767 +1,777 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATMEGA64HVE2_H_INCLUDED
-#define _AVR_ATMEGA64HVE2_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom64hve2.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDRA1   1
-// Inserted "DDA1" from "DDRA1" due to compatibility
-#define DDA1    1
-#define DDRA0   0
-// Inserted "DDA0" from "DDRA0" due to compatibility
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PORTA1  1
-#define PORTA0  0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDRB7   7
-// Inserted "DDB7" from "DDRB7" due to compatibility
-#define DDB7    7
-#define DDRB6   6
-// Inserted "DDB6" from "DDRB6" due to compatibility
-#define DDB6    6
-#define DDRB5   5
-// Inserted "DDB5" from "DDRB5" due to compatibility
-#define DDB5    5
-#define DDRB4   4
-// Inserted "DDB4" from "DDRB4" due to compatibility
-#define DDB4    4
-#define DDRB3   3
-// Inserted "DDB3" from "DDRB3" due to compatibility
-#define DDB3    3
-#define DDRB2   2
-// Inserted "DDB2" from "DDRB2" due to compatibility
-#define DDB2    2
-#define DDRB1   1
-// Inserted "DDB1" from "DDRB1" due to compatibility
-#define DDB1    1
-#define DDRB0   0
-// Inserted "DDB0" from "DDRB0" due to compatibility
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-/* Reserved [0x06..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-#define OCF0B   2
-#define ICF0    3
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    3
-
-/* Reserved [0x17..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-#define PCIF1   1
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0
-#define ICS0    3
-#define ICES0   4
-#define ICNC0   5
-#define ICEN0   6
-#define TCW0    7
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-
-/* Combine TCNT0L and TCNT0H */
-#define TCNT0   _SFR_IO16(0x26)
-
-#define TCNT0L  _SFR_IO8(0x26)
-#define TCNT0H  _SFR_IO8(0x27)
-
-#define OCR0A   _SFR_IO8(0x28)
-
-#define OCR0B   _SFR_IO8(0x29)
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-/* Reserved [0x2F..0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BODRF   2
-#define WDRF    3
-#define OCDRF   4
-
-#define MCUCR   _SFR_IO8(0x35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define CKOE    5
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define LBSET   3
-#define RWWSRE  4
-#define SIGRD   5
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDE     3
-#define WDCE    4
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPCE  7
-
-#define WUTCSR  _SFR_MEM8(0x62)
-#define WUTP0   0
-#define WUTP1   1
-#define WUTP2   2
-#define WUTE    3
-#define WUTR    4
-#define WUTIE   6
-#define WUTIF   7
-
-#define WDTCLR  _SFR_MEM8(0x63)
-#define WDCLE   0
-#define WDCL0   1
-#define WDCL1   2
-
-#define PRR0    _SFR_MEM8(0x64)
-#define PRTIM0  0
-#define PRTIM1  1
-#define PRSPI   2
-#define PRLIN   3
-
-#define __AVR_HAVE_PRR0	((1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
-#define __AVR_HAVE_PRR0_PRTIM0
-#define __AVR_HAVE_PRR0_PRTIM1
-#define __AVR_HAVE_PRR0_PRSPI
-#define __AVR_HAVE_PRR0_PRLIN
-
-/* Reserved [0x65] */
-
-#define SOSCCALA _SFR_MEM8(0x66)
-
-#define SOSCCALB _SFR_MEM8(0x67)
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-#define PCIE1   1
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-#define OCIE0B  2
-#define ICIE0   3
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   3
-
-/* Reserved [0x70..0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define PA0DID  0
-#define PA1DID  1
-
-/* Reserved [0x7F] */
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0
-#define ICS1    3
-#define ICES1   4
-#define ICNC1   5
-#define ICEN1   6
-#define TCW1    7
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-
-/* Reserved [0x82..0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Reserved [0x86..0x87] */
-
-#define OCR1A   _SFR_MEM8(0x88)
-
-#define OCR1B   _SFR_MEM8(0x89)
-
-/* Reserved [0x8A..0xBF] */
-
-#define LINCR   _SFR_MEM8(0xC0)
-#define LCMD0   0
-#define LCMD1   1
-#define LCMD2   2
-#define LENA    3
-#define LCONF0  4
-#define LCONF1  5
-#define LIN13   6
-#define LSWRES  7
-
-#define LINSIR  _SFR_MEM8(0xC1)
-#define LRXOK   0
-#define LTXOK   1
-#define LIDOK   2
-#define LERR    3
-#define LBUSY   4
-#define LIDST0  5
-#define LIDST1  6
-#define LIDST2  7
-
-#define LINENIR _SFR_MEM8(0xC2)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR  3
-
-#define LINERR  _SFR_MEM8(0xC3)
-#define LBERR   0
-#define LCERR   1
-#define LPERR   2
-#define LSERR   3
-#define LFERR   4
-#define LOVERR  5
-#define LTOERR  6
-#define LABORT  7
-
-#define LINBTR  _SFR_MEM8(0xC4)
-#define LBT0    0
-#define LBT1    1
-#define LBT2    2
-#define LBT3    3
-#define LBT4    4
-#define LBT5    5
-#define LDISR   7
-
-#define LINBRRL _SFR_MEM8(0xC5)
-#define LDIV0   0
-#define LDIV1   1
-#define LDIV2   2
-#define LDIV3   3
-#define LDIV4   4
-#define LDIV5   5
-#define LDIV6   6
-#define LDIV7   7
-
-#define LINBRRH _SFR_MEM8(0xC6)
-#define LDIV8   0
-#define LDIV9   1
-#define LDIV10  2
-#define LDIV11  3
-
-#define LINDLR  _SFR_MEM8(0xC7)
-#define LRXDL0  0
-#define LRXDL1  1
-#define LRXDL2  2
-#define LRXDL3  3
-#define LTXDL0  4
-#define LTXDL1  5
-#define LTXDL2  6
-#define LTXDL3  7
-
-#define LINIDR  _SFR_MEM8(0xC8)
-#define LID0    0
-#define LID1    1
-#define LID2    2
-#define LID3    3
-#define LID4    4
-#define LID5    5
-#define LP0     6
-#define LP1     7
-
-#define LINSEL  _SFR_MEM8(0xC9)
-#define LINDX0  0
-#define LINDX1  1
-#define LINDX2  2
-#define LAINC   3
-
-#define LINDAT  _SFR_MEM8(0xCA)
-#define LDATA0  0
-#define LDATA1  1
-#define LDATA2  2
-#define LDATA3  3
-#define LDATA4  4
-#define LDATA5  5
-#define LDATA6  6
-#define LDATA7  7
-
-/* Reserved [0xCB..0xD0] */
-
-#define BGCSRA  _SFR_MEM8(0xD1)
-#define BGSC0   0
-#define BGSC1   1
-#define BGSC2   2
-
-#define BGCRB   _SFR_MEM8(0xD2)
-#define BGCL0   0
-#define BGCL1   1
-#define BGCL2   2
-#define BGCL3   3
-#define BGCL4   4
-#define BGCL5   5
-#define BGCL6   6
-#define BGCL7   7
-
-#define BGCRA   _SFR_MEM8(0xD3)
-#define BGCN0   0
-#define BGCN1   1
-#define BGCN2   2
-#define BGCN3   3
-#define BGCN4   4
-#define BGCN5   5
-#define BGCN6   6
-#define BGCN7   7
-
-#define BGLR    _SFR_MEM8(0xD4)
-#define BGPL    0
-#define BGPLE   1
-
-/* Reserved [0xD5..0xD7] */
-
-#define PLLCSR  _SFR_MEM8(0xD8)
-#define PLLCIE  0
-#define PLLCIF  1
-#define LOCK    4
-#define SWEN    5
-
-/* Reserved [0xD9..0xDB] */
-
-#define PBOV    _SFR_MEM8(0xDC)
-#define PBOE0   0
-#define PBOE3   3
-#define PBOVCE  7
-
-/* Reserved [0xDD..0xDF] */
-
-#define ADSCSRA _SFR_MEM8(0xE0)
-#define SCMD0   0
-#define SCMD1   1
-#define SBSY    2
-
-#define ADSCSRB _SFR_MEM8(0xE1)
-#define CADICRB 0
-#define CADACRB 1
-#define CADICPS 2
-#define VADICRB 4
-#define VADACRB 5
-#define VADICPS 6
-
-#define ADCRA   _SFR_MEM8(0xE2)
-#define CKSEL   0
-#define ADCMS0  1
-#define ADCMS1  2
-#define ADPSEL  3
-
-#define ADCRB   _SFR_MEM8(0xE3)
-#define ADADES0 0
-#define ADADES1 1
-#define ADADES2 2
-#define ADIDES0 3
-#define ADIDES1 4
-
-#define ADCRC   _SFR_MEM8(0xE4)
-#define CADRCT0 0
-#define CADRCT1 1
-#define CADRCT2 2
-#define CADRCT3 3
-#define CADRCM0 4
-#define CADRCM1 5
-#define CADEN   7
-
-#define ADCRD   _SFR_MEM8(0xE5)
-#define CADDSEL 0
-#define CADPDM0 1
-#define CADPDM1 2
-#define CADG0   3
-#define CADG1   4
-#define CADG2   5
-
-#define ADCRE   _SFR_MEM8(0xE6)
-#define VADMUX0 0
-#define VADMUX1 1
-#define VADMUX2 2
-#define VADPDM0 3
-#define VADPDM1 4
-#define VADREFS 5
-#define VADEN   7
-
-#define ADIFR   _SFR_MEM8(0xE7)
-#define CADICIF 0
-#define CADACIF 1
-#define CADRCIF 2
-#define VADICIF 4
-#define VADACIF 5
-
-#define ADIMR   _SFR_MEM8(0xE8)
-#define CADICIE 0
-#define CADACIE 1
-#define CADRCIE 2
-#define VADICIE 4
-#define VADACIE 5
-
-/* Combine CADRCLL and CADRCLH */
-#define CADRCL  _SFR_MEM16(0xE9)
-
-#define CADRCLL _SFR_MEM8(0xE9)
-#define CADRCLH _SFR_MEM8(0xEA)
-
-/* Combine CADICL and CADICH */
-#define CADIC   _SFR_MEM16(0xEB)
-
-#define CADICL  _SFR_MEM8(0xEB)
-#define CADICH  _SFR_MEM8(0xEC)
-
-#define CADAC0  _SFR_MEM8(0xED)
-
-#define CADAC1  _SFR_MEM8(0xEE)
-
-#define CADAC2  _SFR_MEM8(0xEF)
-
-#define CADAC3  _SFR_MEM8(0xF0)
-
-/* Combine VADICL and VADICH */
-#define VADIC   _SFR_MEM16(0xF1)
-
-#define VADICL  _SFR_MEM8(0xF1)
-#define VADICH  _SFR_MEM8(0xF2)
-
-#define VADAC0  _SFR_MEM8(0xF3)
-
-#define VADAC1  _SFR_MEM8(0xF4)
-
-#define VADAC2  _SFR_MEM8(0xF5)
-
-#define VADAC3  _SFR_MEM8(0xF6)
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* Pin Change Interrupt 0 */
-#define PCINT0_vect            _VECTOR(2)
-#define PCINT0_vect_num        2
-
-/* Pin Change Interrupt 1 */
-#define PCINT1_vect            _VECTOR(3)
-#define PCINT1_vect_num        3
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect            _VECTOR(4)
-#define WDT_vect_num        4
-
-/* Wakeup Timer Overflow */
-#define WAKEUP_vect            _VECTOR(5)
-#define WAKEUP_vect_num        5
-
-/* Timer 1 Input capture */
-#define TIMER1_IC_vect            _VECTOR(6)
-#define TIMER1_IC_vect_num        6
-
-/* Timer 1 Compare Match A */
-#define TIMER1_COMPA_vect            _VECTOR(7)
-#define TIMER1_COMPA_vect_num        7
-
-/* Timer 1 Compare Match B */
-#define TIMER1_COMPB_vect            _VECTOR(8)
-#define TIMER1_COMPB_vect_num        8
-
-/* Timer 1 overflow */
-#define TIMER1_OVF_vect            _VECTOR(9)
-#define TIMER1_OVF_vect_num        9
-
-/* Timer 0 Input Capture */
-#define TIMER0_IC_vect            _VECTOR(10)
-#define TIMER0_IC_vect_num        10
-
-/* Timer 0 Comapre Match A */
-#define TIMER0_COMPA_vect            _VECTOR(11)
-#define TIMER0_COMPA_vect_num        11
-
-/* Timer 0 Compare Match B */
-#define TIMER0_COMPB_vect            _VECTOR(12)
-#define TIMER0_COMPB_vect_num        12
-
-/* Timer 0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(13)
-#define TIMER0_OVF_vect_num        13
-
-/* LIN Status Interrupt */
-#define LIN_STATUS_vect            _VECTOR(14)
-#define LIN_STATUS_vect_num        14
-
-/* LIN Error Interrupt */
-#define LIN_ERROR_vect            _VECTOR(15)
-#define LIN_ERROR_vect_num        15
-
-/* SPI Serial transfer complete */
-#define SPI_STC_vect            _VECTOR(16)
-#define SPI_STC_vect_num        16
-
-/* Voltage ADC Instantaneous Conversion Complete */
-#define VADC_CONV_vect            _VECTOR(17)
-#define VADC_CONV_vect_num        17
-
-/* Voltage ADC Accumulated Conversion Complete */
-#define VADC_ACC_vect            _VECTOR(18)
-#define VADC_ACC_vect_num        18
-
-/* C-ADC Instantaneous Conversion Complete */
-#define CADC_CONV_vect            _VECTOR(19)
-#define CADC_CONV_vect_num        19
-
-/* C-ADC Regular Current */
-#define CADC_REG_CUR_vect            _VECTOR(20)
-#define CADC_REG_CUR_vect_num        20
-
-/* C-ADC Accumulated Conversion Complete */
-#define CADC_ACC_vect            _VECTOR(21)
-#define CADC_ACC_vect_num        21
-
-/* EEPROM Ready */
-#define EE_READY_vect            _VECTOR(22)
-#define EE_READY_vect_num        22
-
-/* SPM Ready */
-#define SPM_vect            _VECTOR(23)
-#define SPM_vect_num        23
-
-/* PLL Lock Change Interrupt */
-#define PLL_vect            _VECTOR(24)
-#define PLL_vect_num        24
-
-#define _VECTORS_SIZE 100
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 128
-#define FLASHSTART   0x0000
-#define FLASHEND     0xFFFF
-#define RAMSTART     0x0100
-#define RAMSIZE      4096
-#define RAMEND       0x10FF
-#define E2START     0
-#define E2SIZE      1024
-#define E2PAGESIZE  4
-#define E2END       0x03FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_OSCSEL0     (unsigned char)~_BV(0)
-#define FUSE_SUT0        (unsigned char)~_BV(1)
-#define FUSE_SUT1        (unsigned char)~_BV(2)
-#define FUSE_CKDIV8      (unsigned char)~_BV(3)
-#define FUSE_BODEN       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_EESAVE      (unsigned char)~_BV(6)
-#define FUSE_WDTON       (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_CKDIV8 & FUSE_SPIEN)
-
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_DWEN        (unsigned char)~_BV(3)
-#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x10
-
-
-#endif /* #ifdef _AVR_ATMEGA64HVE2_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATMEGA64HVE2_H_INCLUDED
+#define _AVR_ATMEGA64HVE2_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iom64hve2.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+/* Reserved [0x06..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+#define ICF0    3
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    3
+
+/* Reserved [0x17..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM     7
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define ICS0    3
+#define ICES0   4
+#define ICNC0   5
+#define ICEN0   6
+#define TCW0    7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+
+/* Combine TCNT0L and TCNT0H */
+#define TCNT0   _SFR_IO16(0x26)
+
+#define TCNT0L  _SFR_IO8(0x26)
+#define TCNT0H  _SFR_IO8(0x27)
+
+#define OCR0A   _SFR_IO8(0x28)
+
+#define OCR0B   _SFR_IO8(0x29)
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F..0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BODRF   2
+#define WDRF    3
+#define OCDRF   4
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+#define CKOE    5
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define LBSET   3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPCE  7
+
+#define WUTCSR  _SFR_MEM8(0x62)
+#define WUTP0   0
+#define WUTP1   1
+#define WUTP2   2
+#define WUTE    3
+#define WUTR    4
+#define WUTIE   6
+#define WUTIF   7
+
+#define WDTCLR  _SFR_MEM8(0x63)
+#define WDCLE   0
+#define WDCL0   1
+#define WDCL1   2
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTIM0  0
+#define PRTIM1  1
+#define PRSPI   2
+#define PRLIN   3
+
+#define __AVR_HAVE_PRR0	((1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRLIN
+
+/* Reserved [0x65] */
+
+#define SOSCCALA _SFR_MEM8(0x66)
+
+#define SOSCCALB _SFR_MEM8(0x67)
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+#define ICIE0   3
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   3
+
+/* Reserved [0x70..0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define PA0DID  0
+#define PA1DID  1
+
+/* Reserved [0x7F] */
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define ICS1    3
+#define ICES1   4
+#define ICNC1   5
+#define ICEN1   6
+#define TCW1    7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+
+/* Reserved [0x82..0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Reserved [0x86..0x87] */
+
+#define OCR1A   _SFR_MEM8(0x88)
+
+#define OCR1B   _SFR_MEM8(0x89)
+
+/* Reserved [0x8A..0xBF] */
+
+#define LINCR   _SFR_MEM8(0xC0)
+#define LCMD0   0
+#define LCMD1   1
+#define LCMD2   2
+#define LENA    3
+#define LCONF0  4
+#define LCONF1  5
+#define LIN13   6
+#define LSWRES  7
+
+#define LINSIR  _SFR_MEM8(0xC1)
+#define LRXOK   0
+#define LTXOK   1
+#define LIDOK   2
+#define LERR    3
+#define LBUSY   4
+#define LIDST0  5
+#define LIDST1  6
+#define LIDST2  7
+
+#define LINENIR _SFR_MEM8(0xC2)
+#define LENRXOK 0
+#define LENTXOK 1
+#define LENIDOK 2
+#define LENERR  3
+
+#define LINERR  _SFR_MEM8(0xC3)
+#define LBERR   0
+#define LCERR   1
+#define LPERR   2
+#define LSERR   3
+#define LFERR   4
+#define LOVERR  5
+#define LTOERR  6
+#define LABORT  7
+
+#define LINBTR  _SFR_MEM8(0xC4)
+#define LBT0    0
+#define LBT1    1
+#define LBT2    2
+#define LBT3    3
+#define LBT4    4
+#define LBT5    5
+#define LDISR   7
+
+#define LINBRRL _SFR_MEM8(0xC5)
+#define LDIV0   0
+#define LDIV1   1
+#define LDIV2   2
+#define LDIV3   3
+#define LDIV4   4
+#define LDIV5   5
+#define LDIV6   6
+#define LDIV7   7
+
+#define LINBRRH _SFR_MEM8(0xC6)
+#define LDIV8   0
+#define LDIV9   1
+#define LDIV10  2
+#define LDIV11  3
+
+#define LINDLR  _SFR_MEM8(0xC7)
+#define LRXDL0  0
+#define LRXDL1  1
+#define LRXDL2  2
+#define LRXDL3  3
+#define LTXDL0  4
+#define LTXDL1  5
+#define LTXDL2  6
+#define LTXDL3  7
+
+#define LINIDR  _SFR_MEM8(0xC8)
+#define LID0    0
+#define LID1    1
+#define LID2    2
+#define LID3    3
+#define LID4    4
+#define LID5    5
+#define LP0     6
+#define LP1     7
+
+#define LINSEL  _SFR_MEM8(0xC9)
+#define LINDX0  0
+#define LINDX1  1
+#define LINDX2  2
+#define LAINC   3
+
+#define LINDAT  _SFR_MEM8(0xCA)
+#define LDATA0  0
+#define LDATA1  1
+#define LDATA2  2
+#define LDATA3  3
+#define LDATA4  4
+#define LDATA5  5
+#define LDATA6  6
+#define LDATA7  7
+
+/* Reserved [0xCB..0xD0] */
+
+#define BGCSRA  _SFR_MEM8(0xD1)
+#define BGSC0   0
+#define BGSC1   1
+#define BGSC2   2
+
+#define BGCRB   _SFR_MEM8(0xD2)
+#define BGCL0   0
+#define BGCL1   1
+#define BGCL2   2
+#define BGCL3   3
+#define BGCL4   4
+#define BGCL5   5
+#define BGCL6   6
+#define BGCL7   7
+
+#define BGCRA   _SFR_MEM8(0xD3)
+#define BGCN0   0
+#define BGCN1   1
+#define BGCN2   2
+#define BGCN3   3
+#define BGCN4   4
+#define BGCN5   5
+#define BGCN6   6
+#define BGCN7   7
+
+#define BGLR    _SFR_MEM8(0xD4)
+#define BGPL    0
+#define BGPLE   1
+
+/* Reserved [0xD5..0xD7] */
+
+#define PLLCSR  _SFR_MEM8(0xD8)
+#define PLLCIE  0
+#define PLLCIF  1
+#define LOCK    4
+#define SWEN    5
+
+/* Reserved [0xD9..0xDB] */
+
+#define PBOV    _SFR_MEM8(0xDC)
+#define PBOE0   0
+#define PBOE3   3
+#define PBOVCE  7
+
+/* Reserved [0xDD..0xDF] */
+
+#define ADSCSRA _SFR_MEM8(0xE0)
+#define SCMD0   0
+#define SCMD1   1
+#define SBSY    2
+
+#define ADSCSRB _SFR_MEM8(0xE1)
+#define CADICRB 0
+#define CADACRB 1
+#define CADICPS 2
+#define VADICRB 4
+#define VADACRB 5
+#define VADICPS 6
+
+#define ADCRA   _SFR_MEM8(0xE2)
+#define CKSEL   0
+#define ADCMS0  1
+#define ADCMS1  2
+#define ADPSEL  3
+
+#define ADCRB   _SFR_MEM8(0xE3)
+#define ADADES0 0
+#define ADADES1 1
+#define ADADES2 2
+#define ADIDES0 3
+#define ADIDES1 4
+
+#define ADCRC   _SFR_MEM8(0xE4)
+#define CADRCT0 0
+#define CADRCT1 1
+#define CADRCT2 2
+#define CADRCT3 3
+#define CADRCM0 4
+#define CADRCM1 5
+#define CADEN   7
+
+#define ADCRD   _SFR_MEM8(0xE5)
+#define CADDSEL 0
+#define CADPDM0 1
+#define CADPDM1 2
+#define CADG0   3
+#define CADG1   4
+#define CADG2   5
+
+#define ADCRE   _SFR_MEM8(0xE6)
+#define VADMUX0 0
+#define VADMUX1 1
+#define VADMUX2 2
+#define VADPDM0 3
+#define VADPDM1 4
+#define VADREFS 5
+#define VADEN   7
+
+#define ADIFR   _SFR_MEM8(0xE7)
+#define CADICIF 0
+#define CADACIF 1
+#define CADRCIF 2
+#define VADICIF 4
+#define VADACIF 5
+
+#define ADIMR   _SFR_MEM8(0xE8)
+#define CADICIE 0
+#define CADACIE 1
+#define CADRCIE 2
+#define VADICIE 4
+#define VADACIE 5
+
+/* Combine CADRCLL and CADRCLH */
+#define CADRCL  _SFR_MEM16(0xE9)
+
+#define CADRCLL _SFR_MEM8(0xE9)
+#define CADRCLH _SFR_MEM8(0xEA)
+
+/* Combine CADICL and CADICH */
+#define CADIC   _SFR_MEM16(0xEB)
+
+#define CADICL  _SFR_MEM8(0xEB)
+#define CADICH  _SFR_MEM8(0xEC)
+
+#define CADAC0  _SFR_MEM8(0xED)
+
+#define CADAC1  _SFR_MEM8(0xEE)
+
+#define CADAC2  _SFR_MEM8(0xEF)
+
+#define CADAC3  _SFR_MEM8(0xF0)
+
+/* Combine VADICL and VADICH */
+#define VADIC   _SFR_MEM16(0xF1)
+
+#define VADICL  _SFR_MEM8(0xF1)
+#define VADICH  _SFR_MEM8(0xF2)
+
+#define VADAC0  _SFR_MEM8(0xF3)
+
+#define VADAC1  _SFR_MEM8(0xF4)
+
+#define VADAC2  _SFR_MEM8(0xF5)
+
+#define VADAC3  _SFR_MEM8(0xF6)
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* Pin Change Interrupt 0 */
+#define PCINT0_vect            _VECTOR(2)
+#define PCINT0_vect_num        2
+
+/* Pin Change Interrupt 1 */
+#define PCINT1_vect            _VECTOR(3)
+#define PCINT1_vect_num        3
+
+/* Watchdog Timeout Interrupt */
+#define WDT_vect            _VECTOR(4)
+#define WDT_vect_num        4
+
+/* Wakeup Timer Overflow */
+#define WAKEUP_vect            _VECTOR(5)
+#define WAKEUP_vect_num        5
+
+/* Timer 1 Input capture */
+#define TIMER1_IC_vect            _VECTOR(6)
+#define TIMER1_IC_vect_num        6
+
+/* Timer 1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(7)
+#define TIMER1_COMPA_vect_num        7
+
+/* Timer 1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(8)
+#define TIMER1_COMPB_vect_num        8
+
+/* Timer 1 overflow */
+#define TIMER1_OVF_vect            _VECTOR(9)
+#define TIMER1_OVF_vect_num        9
+
+/* Timer 0 Input Capture */
+#define TIMER0_IC_vect            _VECTOR(10)
+#define TIMER0_IC_vect_num        10
+
+/* Timer 0 Comapre Match A */
+#define TIMER0_COMPA_vect            _VECTOR(11)
+#define TIMER0_COMPA_vect_num        11
+
+/* Timer 0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(12)
+#define TIMER0_COMPB_vect_num        12
+
+/* Timer 0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(13)
+#define TIMER0_OVF_vect_num        13
+
+/* LIN Status Interrupt */
+#define LIN_STATUS_vect            _VECTOR(14)
+#define LIN_STATUS_vect_num        14
+
+/* LIN Error Interrupt */
+#define LIN_ERROR_vect            _VECTOR(15)
+#define LIN_ERROR_vect_num        15
+
+/* SPI Serial transfer complete */
+#define SPI_STC_vect            _VECTOR(16)
+#define SPI_STC_vect_num        16
+
+/* Voltage ADC Instantaneous Conversion Complete */
+#define VADC_CONV_vect            _VECTOR(17)
+#define VADC_CONV_vect_num        17
+
+/* Voltage ADC Accumulated Conversion Complete */
+#define VADC_ACC_vect            _VECTOR(18)
+#define VADC_ACC_vect_num        18
+
+/* C-ADC Instantaneous Conversion Complete */
+#define CADC_CONV_vect            _VECTOR(19)
+#define CADC_CONV_vect_num        19
+
+/* C-ADC Regular Current */
+#define CADC_REG_CUR_vect            _VECTOR(20)
+#define CADC_REG_CUR_vect_num        20
+
+/* C-ADC Accumulated Conversion Complete */
+#define CADC_ACC_vect            _VECTOR(21)
+#define CADC_ACC_vect_num        21
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(22)
+#define EE_READY_vect_num        22
+
+/* SPM Ready */
+#define SPM_vect            _VECTOR(23)
+#define SPM_vect_num        23
+
+/* PLL Lock Change Interrupt */
+#define PLL_vect            _VECTOR(24)
+#define PLL_vect_num        24
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 100
+#else
+#  define _VECTORS_SIZE 100U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 128
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0xFFFF
+#else
+#  define SPM_PAGESIZE 128U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0xFFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      4096
+#  define RAMEND       0x10FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      4096U
+#  define RAMEND       0x10FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      1024
+#  define E2PAGESIZE  4
+#  define E2END       0x03FF
+#else
+#  define E2START     0U
+#  define E2SIZE      1024U
+#  define E2PAGESIZE  4U
+#  define E2END       0x03FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 2
+
+/* Low Fuse Byte */
+#define FUSE_OSCSEL0     (unsigned char)~_BV(0)
+#define FUSE_SUT0        (unsigned char)~_BV(1)
+#define FUSE_SUT1        (unsigned char)~_BV(2)
+#define FUSE_CKDIV8      (unsigned char)~_BV(3)
+#define FUSE_BODEN       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_EESAVE      (unsigned char)~_BV(6)
+#define FUSE_WDTON       (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_CKDIV8 & FUSE_SPIEN)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_DWEN        (unsigned char)~_BV(3)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x96
+#define SIGNATURE_2 0x10
+
+
+
+
+#endif /* #ifdef _AVR_ATMEGA64HVE2_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom64m1.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom64m1.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom64m1.h 2183 2010-09-21 05:37:46Z aboyapati $ */
 
 /* avr/iom64m1.h - definitions for ATmega64M1 */
 
@@ -1563,7 +1563,6 @@
 #define SIGNATURE_2 0x84
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom64rfr2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom64rfr2.h
@@ -1,41 +1,25 @@
-/* Copyright (c) 2013 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* $Id$ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
 
-/* avr/iom64rfr2.h - definitions for ATmega64RFR2 */
 
-#ifndef _AVR_IOM64RFR2_H_
-#define _AVR_IOM64RFR2_H_ 1
+#ifndef _AVR_ATMEGA64RFR2_H_INCLUDED
+#define _AVR_ATMEGA64RFR2_H_INCLUDED
 
-/* This file should only be included from <avr/io.h>, never directly. */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -47,1171 +31,570 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif
 
-#include <avr/sfr_defs.h>
+/* Registers and associated bit numbers */
 
-#ifndef __ASSEMBLER__
-#  define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr))
-#  define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type)
-#  define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type)
-#endif /* __ASSEMBLER__ */
-
-/*
- * USAGE:
- *
- * simple register assignment:
- * TIFR1 = 0x17
- * subregister assignment:
- * TIFR1_struct.ocf1a = 1
- * (subregister names are converted to small letters)
- */
-
-
-/* Port A Input Pins Address */
-#define PINA                            _SFR_IO8(0x00)
-
-  /* PINA */
-
-#define PINA0                           0
-#define PINA1                           1
-#define PINA2                           2
-#define PINA3                           3
-#define PINA4                           4
-#define PINA5                           5
-#define PINA6                           6
-#define PINA7                           7
-
-/* Port A Data Direction Register */
-#define DDRA                            _SFR_IO8(0x01)
-
-  /* DDRA */
-
-#define DDA0                            0
-#define DDA1                            1
-#define DDA2                            2
-#define DDA3                            3
-#define DDA4                            4
-#define DDA5                            5
-#define DDA6                            6
-#define DDA7                            7
-
-/* Port A Data Register */
-#define PORTA                           _SFR_IO8(0x02)
-
-  /* PORTA */
-
-#define PORTA0                          0
-#define PA0                             0
-#define PORTA1                          1
-#define PA1                             1
-#define PORTA2                          2
-#define PA2                             2
-#define PORTA3                          3
-#define PA3                             3
-#define PORTA4                          4
-#define PA4                             4
-#define PORTA5                          5
-#define PA5                             5
-#define PORTA6                          6
-#define PA6                             6
-#define PORTA7                          7
-#define PA7                             7
-
-/* Port B Input Pins Address */
-#define PINB                            _SFR_IO8(0x03)
-
-  /* PINB */
-
-#define PINB0                           0
-#define PINB1                           1
-#define PINB2                           2
-#define PINB3                           3
-#define PINB4                           4
-#define PINB5                           5
-#define PINB6                           6
-#define PINB7                           7
-
-/* Port B Data Direction Register */
-#define DDRB                            _SFR_IO8(0x04)
-
-  /* DDRB */
-
-#define DDB0                            0
-#define DDB1                            1
-#define DDB2                            2
-#define DDB3                            3
-#define DDB4                            4
-#define DDB5                            5
-#define DDB6                            6
-#define DDB7                            7
-
-/* Port B Data Register */
-#define PORTB                           _SFR_IO8(0x05)
-
-  /* PORTB */
-
-#define PORTB0                          0
-#define PB0                             0
-#define PORTB1                          1
-#define PB1                             1
-#define PORTB2                          2
-#define PB2                             2
-#define PORTB3                          3
-#define PB3                             3
-#define PORTB4                          4
-#define PB4                             4
-#define PORTB5                          5
-#define PB5                             5
-#define PORTB6                          6
-#define PB6                             6
-#define PORTB7                          7
-#define PB7                             7
-
-/* Port C Input Pins Address */
-#define PINC                            _SFR_IO8(0x06)
-
-  /* PINC */
-
-#define PINC0                           0
-#define PINC1                           1
-#define PINC2                           2
-#define PINC3                           3
-#define PINC4                           4
-#define PINC5                           5
-#define PINC6                           6
-#define PINC7                           7
-
-/* Port C Data Direction Register */
-#define DDRC                            _SFR_IO8(0x07)
-
-  /* DDRC */
-
-#define DDC0                            0
-#define DDC1                            1
-#define DDC2                            2
-#define DDC3                            3
-#define DDC4                            4
-#define DDC5                            5
-#define DDC6                            6
-#define DDC7                            7
-
-/* Port C Data Register */
-#define PORTC                           _SFR_IO8(0x08)
-
-  /* PORTC */
-
-#define PORTC0                          0
-#define PC0                             0
-#define PORTC1                          1
-#define PC1                             1
-#define PORTC2                          2
-#define PC2                             2
-#define PORTC3                          3
-#define PC3                             3
-#define PORTC4                          4
-#define PC4                             4
-#define PORTC5                          5
-#define PC5                             5
-#define PORTC6                          6
-#define PC6                             6
-#define PORTC7                          7
-#define PC7                             7
-
-/* Port D Input Pins Address */
-#define PIND                            _SFR_IO8(0x09)
-
-  /* PIND */
-
-#define PIND0                           0
-#define PIND1                           1
-#define PIND2                           2
-#define PIND3                           3
-#define PIND4                           4
-#define PIND5                           5
-#define PIND6                           6
-#define PIND7                           7
-
-/* Port D Data Direction Register */
-#define DDRD                            _SFR_IO8(0x0A)
-
-  /* DDRD */
-
-#define DDD0                            0
-#define DDD1                            1
-#define DDD2                            2
-#define DDD3                            3
-#define DDD4                            4
-#define DDD5                            5
-#define DDD6                            6
-#define DDD7                            7
-
-/* Port D Data Register */
-#define PORTD                           _SFR_IO8(0x0B)
-
-  /* PORTD */
-
-#define PORTD0                          0
-#define PD0                             0
-#define PORTD1                          1
-#define PD1                             1
-#define PORTD2                          2
-#define PD2                             2
-#define PORTD3                          3
-#define PD3                             3
-#define PORTD4                          4
-#define PD4                             4
-#define PORTD5                          5
-#define PD5                             5
-#define PORTD6                          6
-#define PD6                             6
-#define PORTD7                          7
-#define PD7                             7
-
-/* Port E Input Pins Address */
-#define PINE                            _SFR_IO8(0x0C)
-
-  /* PINE */
-
-#define PINE0                           0
-#define PINE1                           1
-#define PINE2                           2
-#define PINE3                           3
-#define PINE4                           4
-#define PINE5                           5
-#define PINE6                           6
-#define PINE7                           7
-
-/* Port E Data Direction Register */
-#define DDRE                            _SFR_IO8(0x0D)
-
-  /* DDRE */
-
-#define DDE0                            0
-#define DDE1                            1
-#define DDE2                            2
-#define DDE3                            3
-#define DDE4                            4
-#define DDE5                            5
-#define DDE6                            6
-#define DDE7                            7
-
-/* Port E Data Register */
-#define PORTE                           _SFR_IO8(0x0E)
-
-  /* PORTE */
-
-#define PORTE0                          0
-#define PE0                             0
-#define PORTE1                          1
-#define PE1                             1
-#define PORTE2                          2
-#define PE2                             2
-#define PORTE3                          3
-#define PE3                             3
-#define PORTE4                          4
-#define PE4                             4
-#define PORTE5                          5
-#define PE5                             5
-#define PORTE6                          6
-#define PE6                             6
-#define PORTE7                          7
-#define PE7                             7
-
-/* Port F Input Pins Address */
-#define PINF                            _SFR_IO8(0x0F)
-
-  /* PINF */
-
-#define PINF0                           0
-#define PINF1                           1
-#define PINF2                           2
-#define PINF3                           3
-#define PINF4                           4
-#define PINF5                           5
-#define PINF6                           6
-#define PINF7                           7
-
-/* Port F Data Direction Register */
-#define DDRF                            _SFR_IO8(0x10)
-
-  /* DDRF */
-
-#define DDF0                            0
-#define DDF1                            1
-#define DDF2                            2
-#define DDF3                            3
-#define DDF4                            4
-#define DDF5                            5
-#define DDF6                            6
-#define DDF7                            7
-
-/* Port F Data Register */
-#define PORTF                           _SFR_IO8(0x11)
-
-  /* PORTF */
-
-#define PORTF0                          0
-#define PF0                             0
-#define PORTF1                          1
-#define PF1                             1
-#define PORTF2                          2
-#define PF2                             2
-#define PORTF3                          3
-#define PF3                             3
-#define PORTF4                          4
-#define PF4                             4
-#define PORTF5                          5
-#define PF5                             5
-#define PORTF6                          6
-#define PF6                             6
-#define PORTF7                          7
-#define PF7                             7
-
-/* Port G Input Pins Address */
-#define PING                            _SFR_IO8(0x12)
-
-  /* PING */
-
-#define PING0                           0
-#define PING1                           1
-#define PING2                           2
-#define PING3                           3
-#define PING4                           4
-#define PING5                           5
-
-/* Port G Data Direction Register */
-#define DDRG                            _SFR_IO8(0x13)
-
-  /* DDRG */
-
-#define DDG0                            0
-#define DDG1                            1
-#define DDG2                            2
-#define DDG3                            3
-#define DDG4                            4
-#define DDG5                            5
-
-/* Port G Data Register */
-#define PORTG                           _SFR_IO8(0x14)
-
-  /* PORTG */
-
-#define PORTG0                          0
-#define PG0                             0
-#define PORTG1                          1
-#define PG1                             1
-#define PORTG2                          2
-#define PG2                             2
-#define PORTG3                          3
-#define PG3                             3
-#define PORTG4                          4
-#define PG4                             4
-#define PORTG5                          5
-#define PG5                             5
-
-/* Timer/Counter0 Interrupt Flag Register */
-#define TIFR0                           _SFR_IO8(0x15)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR0 {
-        unsigned int tov0 : 1;	/* Timer/Counter0 Overflow Flag */
-        unsigned int ocf0a : 1;	/* Timer/Counter0 Output Compare A Match Flag */
-        unsigned int ocf0b : 1;	/* Timer/Counter0 Output Compare B Match Flag */
-        unsigned int : 5;
-};
-
-#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR0 */
-
-#define TOV0                            0
-#define OCF0A                           1
-#define OCF0B                           2
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1                           _SFR_IO8(0x16)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR1 {
-        unsigned int tov1 : 1;	/* Timer/Counter1 Overflow Flag */
-        unsigned int ocf1a : 1;	/* Timer/Counter1 Output Compare A Match Flag */
-        unsigned int ocf1b : 1;	/* Timer/Counter1 Output Compare B Match Flag */
-        unsigned int ocf1c : 1;	/* Timer/Counter1 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf1 : 1;	/* Timer/Counter1 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR1 */
-
-#define TOV1                            0
-#define OCF1A                           1
-#define OCF1B                           2
-#define OCF1C                           3
-#define ICF1                            5
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR2                           _SFR_IO8(0x17)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR2 {
-        unsigned int tov2 : 1;	/* Timer/Counter2 Overflow Flag */
-        unsigned int ocf2a : 1;	/* Output Compare Flag 2 A */
-        unsigned int ocf2b : 1;	/* Output Compare Flag 2 B */
-        unsigned int : 5;
-};
-
-#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR2 */
-
-#define TOV2                            0
-#define OCF2A                           1
-#define OCF2B                           2
-
-/* Timer/Counter3 Interrupt Flag Register */
-#define TIFR3                           _SFR_IO8(0x18)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR3 {
-        unsigned int tov3 : 1;	/* Timer/Counter3 Overflow Flag */
-        unsigned int ocf3a : 1;	/* Timer/Counter3 Output Compare A Match Flag */
-        unsigned int ocf3b : 1;	/* Timer/Counter3 Output Compare B Match Flag */
-        unsigned int ocf3c : 1;	/* Timer/Counter3 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf3 : 1;	/* Timer/Counter3 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR3 */
-
-#define TOV3                            0
-#define OCF3A                           1
-#define OCF3B                           2
-#define OCF3C                           3
-#define ICF3                            5
-
-/* Timer/Counter4 Interrupt Flag Register */
-#define TIFR4                           _SFR_IO8(0x19)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR4 {
-        unsigned int tov4 : 1;	/* Timer/Counter4 Overflow Flag */
-        unsigned int ocf4a : 1;	/* Timer/Counter4 Output Compare A Match Flag */
-        unsigned int ocf4b : 1;	/* Timer/Counter4 Output Compare B Match Flag */
-        unsigned int ocf4c : 1;	/* Timer/Counter4 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf4 : 1;	/* Timer/Counter4 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR4 */
-
-#define TOV4                            0
-#define OCF4A                           1
-#define OCF4B                           2
-#define OCF4C                           3
-#define ICF4                            5
-
-/* Timer/Counter5 Interrupt Flag Register */
-#define TIFR5                           _SFR_IO8(0x1A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR5 {
-        unsigned int tov5 : 1;	/* Timer/Counter5 Overflow Flag */
-        unsigned int ocf5a : 1;	/* Timer/Counter5 Output Compare A Match Flag */
-        unsigned int ocf5b : 1;	/* Timer/Counter5 Output Compare B Match Flag */
-        unsigned int ocf5c : 1;	/* Timer/Counter5 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf5 : 1;	/* Timer/Counter5 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR5 */
-
-#define TOV5                            0
-#define OCF5A                           1
-#define OCF5B                           2
-#define OCF5C                           3
-#define ICF5                            5
-
-/* Pin Change Interrupt Flag Register */
-#define PCIFR                           _SFR_IO8(0x1B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCIFR {
-        unsigned int pcif : 3;	/* Pin Change Interrupt Flags */
-        unsigned int : 5;
-};
-
-#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCIFR */
-
-#define PCIF0                           0
-#define PCIF1                           1
-#define PCIF2                           2
-
-/* External Interrupt Flag Register */
-#define EIFR                            _SFR_IO8(0x1C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIFR {
-        unsigned int intf : 8;	/* External Interrupt Flag */
-};
-
-#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIFR */
-
-#define INTF0                           0
-#define INTF1                           1
-#define INTF2                           2
-#define INTF3                           3
-#define INTF4                           4
-#define INTF5                           5
-#define INTF6                           6
-#define INTF7                           7
-
-/* External Interrupt Mask Register */
-#define EIMSK                           _SFR_IO8(0x1D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIMSK {
-        unsigned int intm : 8;	/* External Interrupt Request Enable */
-};
-
-#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIMSK */
-
-#define INT0                            0
-#define INT1                            1
-#define INT2                            2
-#define INT3                            3
-#define INT4                            4
-#define INT5                            5
-#define INT6                            6
-#define INT7                            7
-
-/* General Purpose IO Register 0 */
-#define GPIOR0                          _SFR_IO8(0x1E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR0 {
-        unsigned int gpior00 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior01 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior02 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior03 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior04 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior05 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior06 : 1;	/* General Purpose I/O Register 0 Value */
-        unsigned int gpior07 : 1;	/* General Purpose I/O Register 0 Value */
-};
-
-#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR0 */
-
-#define GPIOR00                         0
-#define GPIOR01                         1
-#define GPIOR02                         2
-#define GPIOR03                         3
-#define GPIOR04                         4
-#define GPIOR05                         5
-#define GPIOR06                         6
-#define GPIOR07                         7
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* EEPROM Control Register */
-#define EECR                            _SFR_IO8(0x1F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EECR {
-        unsigned int eere : 1;	/* EEPROM Read Enable */
-        unsigned int eepe : 1;	/* EEPROM Programming Enable */
-        unsigned int eempe : 1;	/* EEPROM Master Write Enable */
-        unsigned int eerie : 1;	/* EEPROM Ready Interrupt Enable */
-        unsigned int eepm : 2;	/* EEPROM Programming Mode */
-        unsigned int : 2;
-};
-
-#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EECR */
-
-#define EERE                            0
-#define EEPE                            1
-#define EEMPE                           2
-#define EERIE                           3
-#define EEPM0                           4
-#define EEPM1                           5
-
-/* EEPROM Data Register */
-#define EEDR                            _SFR_IO8(0x20)
-
-  /* EEDR */
-
-#define EEDR0                           0
-#define EEDR1                           1
-#define EEDR2                           2
-#define EEDR3                           3
-#define EEDR4                           4
-#define EEDR5                           5
-#define EEDR6                           6
-#define EEDR7                           7
-
-/* EEPROM Address Register  Bytes */
-#define EEAR                            _SFR_IO16(0x21)
-#define EEARL                           _SFR_IO8(0x21)
-#define EEARH                           _SFR_IO8(0x22)
-
-/* General Timer/Counter Control Register */
-#define GTCCR                           _SFR_IO8(0x23)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GTCCR {
-        unsigned int psrsync : 1;	/* Prescaler Reset for Synchronous Timer/Counters */
-        unsigned int psrasy : 1;	/* Prescaler Reset Timer/Counter2 */
-        unsigned int : 5;
-        unsigned int tsm : 1;	/* Timer/Counter Synchronization Mode */
-};
-
-#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GTCCR */
-
-#define PSRSYNC                         0
-#define PSR10                           0
-#define PSRASY                          1
-#define PSR2                            1
-#define TSM                             7
-
-/* Timer/Counter0 Control Register A */
-#define TCCR0A                          _SFR_IO8(0x24)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0A {
-        unsigned int wgm0 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com0b : 2;	/* Compare Match Output B Mode */
-        unsigned int com0a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0A */
-
-#define WGM00                           0
-#define WGM01                           1
-#define COM0B0                          4
-#define COM0B1                          5
-#define COM0A0                          6
-#define COM0A1                          7
-
-/* Timer/Counter0 Control Register B */
-#define TCCR0B                          _SFR_IO8(0x25)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0B {
-        unsigned int cs0 : 3;	/* Clock Select */
-        unsigned int wgm02 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc0b : 1;	/* Force Output Compare B */
-        unsigned int foc0a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0B */
-
-#define CS00                            0
-#define CS01                            1
-#define CS02                            2
-#define WGM02                           3
-#define FOC0B                           6
-#define FOC0A                           7
-
-/* Timer/Counter0 Register */
-#define TCNT0                           _SFR_IO8(0x26)
-
-  /* TCNT0 */
-
-#define TCNT0_0                         0
-#define TCNT0_1                         1
-#define TCNT0_2                         2
-#define TCNT0_3                         3
-#define TCNT0_4                         4
-#define TCNT0_5                         5
-#define TCNT0_6                         6
-#define TCNT0_7                         7
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0A                           _SFR_IO8(0x27)
-
-  /* OCR0A */
-
-#define OCR0A_0                         0
-#define OCR0A_1                         1
-#define OCR0A_2                         2
-#define OCR0A_3                         3
-#define OCR0A_4                         4
-#define OCR0A_5                         5
-#define OCR0A_6                         6
-#define OCR0A_7                         7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B                           _SFR_IO8(0x28)
-
-  /* OCR0B */
-
-#define OCR0B_0                         0
-#define OCR0B_1                         1
-#define OCR0B_2                         2
-#define OCR0B_3                         3
-#define OCR0B_4                         4
-#define OCR0B_5                         5
-#define OCR0B_6                         6
-#define OCR0B_7                         7
-
-/* General Purpose IO Register 1 */
-#define GPIOR1                          _SFR_IO8(0x2A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR1 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 1 Value */
-};
-
-#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR1 */
-
-#define GPIOR10                         0
-#define GPIOR11                         1
-#define GPIOR12                         2
-#define GPIOR13                         3
-#define GPIOR14                         4
-#define GPIOR15                         5
-#define GPIOR16                         6
-#define GPIOR17                         7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2                          _SFR_IO8(0x2B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR2 {
-        unsigned int gpior : 8;	/* General Purpose I/O Register 2 Value */
-};
-
-#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR2 */
-
-#define GPIOR20                         0
-#define GPIOR21                         1
-#define GPIOR22                         2
-#define GPIOR23                         3
-#define GPIOR24                         4
-#define GPIOR25                         5
-#define GPIOR26                         6
-#define GPIOR27                         7
-
-/* SPI Control Register */
-#define SPCR                            _SFR_IO8(0x2C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPCR {
-        unsigned int spr : 2;	/* SPI Clock Rate Select 1 and 0 */
-        unsigned int cpha : 1;	/* Clock Phase */
-        unsigned int cpol : 1;	/* Clock polarity */
-        unsigned int mstr : 1;	/* Master/Slave Select */
-        unsigned int dord : 1;	/* Data Order */
-        unsigned int spe : 1;	/* SPI Enable */
-        unsigned int spie : 1;	/* SPI Interrupt Enable */
-};
-
-#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPCR */
-
-#define SPR0                            0
-#define SPR1                            1
-#define CPHA                            2
-#define CPOL                            3
-#define MSTR                            4
-#define DORD                            5
-#define SPE                             6
-#define SPIE                            7
-
-/* SPI Status Register */
-#define SPSR                            _SFR_IO8(0x2D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPSR {
-        unsigned int spi2x : 1;	/* Double SPI Speed Bit */
-        unsigned int : 5;
-        unsigned int wcol : 1;	/* Write Collision Flag */
-        unsigned int spif : 1;	/* SPI Interrupt Flag */
-};
-
-#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPSR */
-
-#define SPI2X                           0
-#define WCOL                            6
-#define SPIF                            7
-
-/* SPI Data Register */
-#define SPDR                            _SFR_IO8(0x2E)
-
-  /* SPDR */
-
-#define SPDR0                           0
-#define SPDR1                           1
-#define SPDR2                           2
-#define SPDR3                           3
-#define SPDR4                           4
-#define SPDR5                           5
-#define SPDR6                           6
-#define SPDR7                           7
-
-/* Analog Comparator Control And Status Register */
-#define ACSR                            _SFR_IO8(0x30)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ACSR {
-        unsigned int acis : 2;	/* Analog Comparator Interrupt Mode Select */
-        unsigned int acic : 1;	/* Analog Comparator Input Capture Enable */
-        unsigned int acie : 1;	/* Analog Comparator Interrupt Enable */
-        unsigned int aci : 1;	/* Analog Comparator Interrupt Flag */
-        unsigned int aco : 1;	/* Analog Compare Output */
-        unsigned int acbg : 1;	/* Analog Comparator Bandgap Select */
-        unsigned int acd : 1;	/* Analog Comparator Disable */
-};
-
-#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ACSR */
-
-#define ACIS0                           0
-#define ACIS1                           1
-#define ACIC                            2
-#define ACIE                            3
-#define ACI                             4
-#define ACO                             5
-#define ACBG                            6
-#define ACD                             7
-
-/* On-Chip Debug Register */
-#define OCDR                            _SFR_IO8(0x31)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OCDR {
-        unsigned int ocdr : 8;	/* On-Chip Debug Register Data */
-};
-
-#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OCDR */
-
-#define OCDR0                           0
-#define OCDR1                           1
-#define OCDR2                           2
-#define OCDR3                           3
-#define OCDR4                           4
-#define OCDR5                           5
-#define OCDR6                           6
-#define OCDR7                           7
-#define IDRD                            7
-
-/* Sleep Mode Control Register */
-#define SMCR                            _SFR_IO8(0x33)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SMCR {
-        unsigned int se : 1;	/* Sleep Enable */
-        unsigned int sm : 3;	/* Sleep Mode Select bits */
-        unsigned int : 4;
-};
-
-#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SMCR */
-
-#define SE                              0
-#define SM0                             1
-#define SM1                             2
-#define SM2                             3
-
-/* MCU Status Register */
-#define MCUSR                           _SFR_IO8(0x34)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUSR {
-        unsigned int porf : 1;	/* Power-on Reset Flag */
-        unsigned int extrf : 1;	/* External Reset Flag */
-        unsigned int borf : 1;	/* Brown-out Reset Flag */
-        unsigned int wdrf : 1;	/* Watchdog Reset Flag */
-        unsigned int jtrf : 1;	/* JTAG Reset Flag */
-        unsigned int : 3;
-};
-
-#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUSR */
-
-#define PORF                            0
-#define EXTRF                           1
-#define BORF                            2
-#define WDRF                            3
-#define JTRF                            4
-
-/* MCU Control Register */
-#define MCUCR                           _SFR_IO8(0x35)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUCR {
-        unsigned int ivce : 1;	/* Interrupt Vector Change Enable */
-        unsigned int ivsel : 1;	/* Interrupt Vector Select */
-        unsigned int : 2;
-        unsigned int pud : 1;	/* Pull-up Disable */
-        unsigned int : 2;
-        unsigned int jtd : 1;	/* JTAG Interface Disable */
-};
-
-#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUCR */
-
-#define IVCE                            0
-#define IVSEL                           1
-#define PUD                             4
-#define JTD                             7
-
-/* Store Program Memory Control Register */
-#define SPMCSR                          _SFR_IO8(0x37)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPMCSR {
-        unsigned int spmen : 1;	/* Store Program Memory Enable */
-        unsigned int pgers : 1;	/* Page Erase */
-        unsigned int pgwrt : 1;	/* Page Write */
-        unsigned int blbset : 1;	/* Boot Lock Bit Set */
-        unsigned int rwwsre : 1;	/* Read While Write Section Read Enable */
-        unsigned int sigrd : 1;	/* Signature Row Read */
-        unsigned int rwwsb : 1;	/* Read While Write Section Busy */
-        unsigned int spmie : 1;	/* SPM Interrupt Enable */
-};
-
-#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPMCSR */
-
-#define SPMEN                           0
-#define PGERS                           1
-#define PGWRT                           2
-#define BLBSET                          3
-#define RWWSRE                          4
-#define SIGRD                           5
-#define RWWSB                           6
-#define SPMIE                           7
-
-/* Stack Pointer */
-#define SP                              _SFR_IO16(0x3D)
-#define SPL                             _SFR_IO8(0x3D)
-#define SPH                             _SFR_IO8(0x3E)
-
-/* Status Register */
-#define SREG                            _SFR_IO8(0x3F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SREG {
-        unsigned int c : 1;	/* Carry Flag */
-        unsigned int z : 1;	/* Zero Flag */
-        unsigned int n : 1;	/* Negative Flag */
-        unsigned int v : 1;	/* Two's Complement Overflow Flag */
-        unsigned int s : 1;	/* Sign Bit */
-        unsigned int h : 1;	/* Half Carry Flag */
-        unsigned int t : 1;	/* Bit Copy Storage */
-        unsigned int i : 1;	/* Global Interrupt Enable */
-};
-
-#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SREG */
-
-#define SREG_C                          0
-#define SREG_Z                          1
-#define SREG_N                          2
-#define SREG_V                          3
-#define SREG_S                          4
-#define SREG_H                          5
-#define SREG_T                          6
-#define SREG_I                          7
-
-/* Watchdog Timer Control Register */
-#define WDTCSR                          _SFR_MEM8(0x60)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_WDTCSR {
-        unsigned int wdp : 3;	/* Watchdog Timer Prescaler Bits */
-        unsigned int wde : 1;	/* Watch Dog Enable */
-        unsigned int wdce : 1;	/* Watchdog Change Enable */
-        unsigned int : 1;
-        unsigned int wdie : 1;	/* Watchdog Timeout Interrupt Enable */
-        unsigned int wdif : 1;	/* Watchdog Timeout Interrupt Flag */
-};
-
-#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* WDTCSR */
-
-#define WDP0                            0
-#define WDP1                            1
-#define WDP2                            2
-#define WDE                             3
-#define WDCE                            4
-#define WDP3                            5
-#define WDIE                            6
-#define WDIF                            7
-
-/* Clock Prescale Register */
-#define CLKPR                           _SFR_MEM8(0x61)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CLKPR {
-        unsigned int clkps : 4;	/* Clock Prescaler Select Bits */
-        unsigned int : 3;
-        unsigned int clkpce : 1;	/* Clock Prescaler Change Enable */
-};
-
-#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CLKPR */
-
-#define CLKPS0                          0
-#define CLKPS1                          1
-#define CLKPS2                          2
-#define CLKPS3                          3
-#define CLKPCE                          7
-
-/* Power Reduction Register 2 */
-#define PRR2                            _SFR_MEM8(0x63)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR2 {
-        unsigned int prram : 4;	/* Power Reduction SRAMs */
-        unsigned int : 4;
-};
-
-#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR2 */
-
-#define PRRAM0                          0
-#define PRRAM1                          1
-#define PRRAM2                          2
-#define PRRAM3                          3
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE7   7
+// Inserted "DDE7" from "DDRE7" due to compatibility
+#define DDE7    7
+#define DDRE6   6
+// Inserted "DDE6" from "DDRE6" due to compatibility
+#define DDE6    6
+#define DDRE5   5
+// Inserted "DDE5" from "DDRE5" due to compatibility
+#define DDE5    5
+#define DDRE4   4
+// Inserted "DDE4" from "DDRE4" due to compatibility
+#define DDE4    4
+#define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
+#define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
+#define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
+#define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE7  7
+#define PORTE6  6
+#define PORTE5  5
+#define PORTE4  4
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDRF7   7
+// Inserted "DDF7" from "DDRF7" due to compatibility
+#define DDF7    7
+#define DDRF6   6
+// Inserted "DDF6" from "DDRF6" due to compatibility
+#define DDF6    6
+#define DDRF5   5
+// Inserted "DDF5" from "DDRF5" due to compatibility
+#define DDF5    5
+#define DDRF4   4
+// Inserted "DDF4" from "DDRF4" due to compatibility
+#define DDF4    4
+#define DDRF3   3
+// Inserted "DDF3" from "DDRF3" due to compatibility
+#define DDF3    3
+#define DDRF2   2
+// Inserted "DDF2" from "DDRF2" due to compatibility
+#define DDF2    2
+#define DDRF1   1
+// Inserted "DDF1" from "DDRF1" due to compatibility
+#define DDF1    1
+#define DDRF0   0
+// Inserted "DDF0" from "DDRF0" due to compatibility
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PORTF7  7
+#define PORTF6  6
+#define PORTF5  5
+#define PORTF4  4
+#define PORTF3  3
+#define PORTF2  2
+#define PORTF1  1
+#define PORTF0  0
+
+#define PING    _SFR_IO8(0x12)
+#define PING7   7
+#define PING6   6
+#define PING5   5
+#define PING4   4
+#define PING3   3
+#define PING2   2
+#define PING1   1
+#define PING0   0
+
+#define DDRG    _SFR_IO8(0x13)
+#define DDRG7   7
+// Inserted "DDG7" from "DDRG7" due to compatibility
+#define DDG7    7
+#define DDRG6   6
+// Inserted "DDG6" from "DDRG6" due to compatibility
+#define DDG6    6
+#define DDRG5   5
+// Inserted "DDG5" from "DDRG5" due to compatibility
+#define DDG5    5
+#define DDRG4   4
+// Inserted "DDG4" from "DDRG4" due to compatibility
+#define DDG4    4
+#define DDRG3   3
+// Inserted "DDG3" from "DDRG3" due to compatibility
+#define DDG3    3
+#define DDRG2   2
+// Inserted "DDG2" from "DDRG2" due to compatibility
+#define DDG2    2
+#define DDRG1   1
+// Inserted "DDG1" from "DDRG1" due to compatibility
+#define DDG1    1
+#define DDRG0   0
+// Inserted "DDG0" from "DDRG0" due to compatibility
+#define DDG0    0
+
+#define PORTG   _SFR_IO8(0x14)
+#define PORTG7  7
+#define PORTG6  6
+#define PORTG5  5
+#define PORTG4  4
+#define PORTG3  3
+#define PORTG2  2
+#define PORTG1  1
+#define PORTG0  0
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define OCF1C   3
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+
+#define TIFR3   _SFR_IO8(0x18)
+#define TOV3    0
+#define OCF3A   1
+#define OCF3B   2
+#define OCF3C   3
+#define ICF3    5
+
+#define TIFR4   _SFR_IO8(0x19)
+#define TOV4    0
+#define OCF4A   1
+#define OCF4B   2
+#define OCF4C   3
+#define ICF4    5
+
+#define TIFR5   _SFR_IO8(0x1A)
+#define TOV5    0
+#define OCF5A   1
+#define OCF5B   2
+#define OCF5C   3
+#define ICF5    5
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+#define INTF2   2
+#define INTF3   3
+#define INTF4   4
+#define INTF5   5
+#define INTF6   6
+#define INTF7   7
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+#define INT2    2
+#define INT3    3
+#define INT4    4
+#define INT5    5
+#define INT6    6
+#define INT7    7
+
+#define GPIOR0  _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define PSRASY  1
+#define TSM     7
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define OCDR    _SFR_IO8(0x31)
+#define OCDR0   0
+#define OCDR1   1
+#define OCDR2   2
+#define OCDR3   3
+#define OCDR4   4
+#define OCDR5   5
+#define OCDR6   6
+#define OCDR7   7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62] */
+
+#define PRR2    _SFR_MEM8(0x63)
+#define PRRAM0  0
+#define PRRAM1  1
+#define PRRAM2  2
+#define PRRAM3  3
 
 #define __AVR_HAVE_PRR2	((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3))
 #define __AVR_HAVE_PRR2_PRRAM0
@@ -1219,36 +602,15 @@
 #define __AVR_HAVE_PRR2_PRRAM2
 #define __AVR_HAVE_PRR2_PRRAM3
 
-/* Power Reduction Register0 */
-#define PRR0                            _SFR_MEM8(0x64)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR0 {
-        unsigned int pradc : 1;	/* Power Reduction ADC */
-        unsigned int prusart0 : 1;	/* Power Reduction USART */
-        unsigned int prspi : 1;	/* Power Reduction Serial Peripheral Interface */
-        unsigned int prtim1 : 1;	/* Power Reduction Timer/Counter1 */
-        unsigned int prpga : 1;	/* Power Reduction PGA */
-        unsigned int prtim0 : 1;	/* Power Reduction Timer/Counter0 */
-        unsigned int prtim2 : 1;	/* Power Reduction Timer/Counter2 */
-        unsigned int prtwi : 1;	/* Power Reduction TWI */
-};
-
-#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR0 */
-
-#define PRADC                           0
-#define PRUSART0                        1
-#define PRSPI                           2
-#define PRTIM1                          3
-#define PRPGA                           4
-#define PRTIM0                          5
-#define PRTIM2                          6
-#define PRTWI                           7
+#define PRR0    _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRPGA   4
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
 
 #define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
 #define __AVR_HAVE_PRR0_PRADC
@@ -1260,32 +622,12 @@
 #define __AVR_HAVE_PRR0_PRTIM2
 #define __AVR_HAVE_PRR0_PRTWI
 
-/* Power Reduction Register 1 */
-#define PRR1                            _SFR_MEM8(0x65)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR1 {
-        unsigned int prusart1 : 1;	/* Power Reduction USART1 */
-        unsigned int : 2;
-        unsigned int prtim3 : 1;	/* Power Reduction Timer/Counter3 */
-        unsigned int prtim4 : 1;	/* Power Reduction Timer/Counter4 */
-        unsigned int prtim5 : 1;	/* Power Reduction Timer/Counter5 */
-        unsigned int prtrx24 : 1;	/* Power Reduction Transceiver */
-        unsigned int : 1;
-};
-
-#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR1 */
-
-#define PRUSART1                        0
-#define PRTIM3                          3
-#define PRTIM4                          4
-#define PRTIM5                          5
-#define PRTRX24                         6
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSART1 0
+#define PRTIM3  3
+#define PRTIM4  4
+#define PRTIM5  5
+#define PRTRX24 6
 
 #define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24))
 #define __AVR_HAVE_PRR1_PRUSART1
@@ -1294,5056 +636,2071 @@
 #define __AVR_HAVE_PRR1_PRTIM5
 #define __AVR_HAVE_PRR1_PRTRX24
 
-/* Oscillator Calibration Value */
-#define OSCCAL                          _SFR_MEM8(0x66)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OSCCAL {
-        unsigned int cal : 8;	/* Oscillator Calibration Tuning Value */
-};
-
-#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OSCCAL */
-
-#define CAL0                            0
-#define CAL1                            1
-#define CAL2                            2
-#define CAL3                            3
-#define CAL4                            4
-#define CAL5                            5
-#define CAL6                            6
-#define CAL7                            7
-
-/* Reference Voltage Calibration Register */
-#define BGCR                            _SFR_MEM8(0x67)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BGCR {
-        unsigned int bgcal : 3;	/* Coarse Calibration Bits */
-        unsigned int bgcal_fine : 4;	/* Fine Calibration Bits */
-        unsigned int : 1;
-};
-
-#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* BGCR */
-
-#define BGCAL0                          0
-#define BGCAL1                          1
-#define BGCAL2                          2
-#define BGCAL_FINE0                     3
-#define BGCAL_FINE1                     4
-#define BGCAL_FINE2                     5
-#define BGCAL_FINE3                     6
-
-/* Pin Change Interrupt Control Register */
-#define PCICR                           _SFR_MEM8(0x68)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCICR {
-        unsigned int pcie : 3;	/* Pin Change Interrupt Enables */
-        unsigned int : 5;
-};
-
-#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCICR */
-
-#define PCIE0                           0
-#define PCIE1                           1
-#define PCIE2                           2
-
-/* External Interrupt Control Register A */
-#define EICRA                           _SFR_MEM8(0x69)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRA {
-        unsigned int isc0 : 2;	/* External Interrupt 0 Sense Control Bit */
-        unsigned int isc1 : 2;	/* External Interrupt 1 Sense Control Bit */
-        unsigned int isc2 : 2;	/* External Interrupt 2 Sense Control Bit */
-        unsigned int isc3 : 2;	/* External Interrupt 3 Sense Control Bit */
-};
-
-#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRA */
-
-#define ISC00                           0
-#define ISC01                           1
-#define ISC10                           2
-#define ISC11                           3
-#define ISC20                           4
-#define ISC21                           5
-#define ISC30                           6
-#define ISC31                           7
-
-/* External Interrupt Control Register B */
-#define EICRB                           _SFR_MEM8(0x6A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRB {
-        unsigned int isc4 : 2;	/* External Interrupt 4 Sense Control Bit */
-        unsigned int isc5 : 2;	/* External Interrupt 5 Sense Control Bit */
-        unsigned int isc6 : 2;	/* External Interrupt 6 Sense Control Bit */
-        unsigned int isc7 : 2;	/* External Interrupt 7 Sense Control Bit */
-};
-
-#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRB */
-
-#define ISC40                           0
-#define ISC41                           1
-#define ISC50                           2
-#define ISC51                           3
-#define ISC60                           4
-#define ISC61                           5
-#define ISC70                           6
-#define ISC71                           7
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0                          _SFR_MEM8(0x6B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK0 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK0_struct _SFR_MEM8_STRUCT(0x6b, struct __reg_PCMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK0 */
-
-#define PCINT0                          0
-#define PCINT1                          1
-#define PCINT2                          2
-#define PCINT3                          3
-#define PCINT4                          4
-#define PCINT5                          5
-#define PCINT6                          6
-#define PCINT7                          7
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1                          _SFR_MEM8(0x6C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK1 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK1 */
-
-#define PCINT8                          0
-#define PCINT9                          1
-#define PCINT10                         2
-#define PCINT11                         3
-#define PCINT12                         4
-#define PCINT13                         5
-#define PCINT14                         6
-#define PCINT15                         7
-
-/* Pin Change Mask Register 2 */
-#define PCMSK2                          _SFR_MEM8(0x6D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK2 {
-        unsigned int pcint : 8;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK2 */
-
-#define PCINT16                         0
-#define PCINT17                         1
-#define PCINT18                         2
-#define PCINT19                         3
-#define PCINT20                         4
-#define PCINT21                         5
-#define PCINT22                         6
-#define PCINT23                         7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0                          _SFR_MEM8(0x6E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK0 {
-        unsigned int toie0 : 1;	/* Timer/Counter0 Overflow Interrupt Enable */
-        unsigned int ocie0a : 1;	/* Timer/Counter0 Output Compare Match A Interrupt Enable */
-        unsigned int ocie0b : 1;	/* Timer/Counter0 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK0 */
-
-#define TOIE0                           0
-#define OCIE0A                          1
-#define OCIE0B                          2
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1                          _SFR_MEM8(0x6F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK1 {
-        unsigned int toie1 : 1;	/* Timer/Counter1 Overflow Interrupt Enable */
-        unsigned int ocie1a : 1;	/* Timer/Counter1 Output Compare A Match Interrupt Enable */
-        unsigned int ocie1b : 1;	/* Timer/Counter1 Output Compare B Match Interrupt Enable */
-        unsigned int ocie1c : 1;	/* Timer/Counter1 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie1 : 1;	/* Timer/Counter1 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK1 */
+#define OSCCAL  _SFR_MEM8(0x66)
+#define CAL0    0
+#define CAL1    1
+#define CAL2    2
+#define CAL3    3
+#define CAL4    4
+#define CAL5    5
+#define CAL6    6
+#define CAL7    7
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+#define BGCR    _SFR_MEM8(0x67)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL_FINE0 3
+#define BGCAL_FINE1 4
+#define BGCAL_FINE2 5
+#define BGCAL_FINE3 6
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+#define ISC20   4
+#define ISC21   5
+#define ISC30   6
+#define ISC31   7
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC40   0
+#define ISC41   1
+#define ISC50   2
+#define ISC51   3
+#define ISC60   4
+#define ISC61   5
+#define ISC70   6
+#define ISC71   7
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define OCIE1C  3
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define TOIE3   0
+#define OCIE3A  1
+#define OCIE3B  2
+#define OCIE3C  3
+#define ICIE3   5
+
+#define TIMSK4  _SFR_MEM8(0x72)
+#define TOIE4   0
+#define OCIE4A  1
+#define OCIE4B  2
+#define OCIE4C  3
+#define ICIE4   5
+
+#define TIMSK5  _SFR_MEM8(0x73)
+#define TOIE5   0
+#define OCIE5A  1
+#define OCIE5B  2
+#define OCIE5C  3
+#define ICIE5   5
+
+/* Reserved [0x74] */
+
+#define NEMCR   _SFR_MEM8(0x75)
+#define AEAM0   4
+#define AEAM1   5
+#define ENEAM   6
+
+/* Reserved [0x76] */
+
+#define ADCSRC  _SFR_MEM8(0x77)
+#define ADSUT0  0
+#define ADSUT1  1
+#define ADSUT2  2
+#define ADSUT3  3
+#define ADSUT4  4
+#define Res0    5
+#define ADTHT0  6
+#define ADTHT1  7
 
-#define TOIE1                           0
-#define OCIE1A                          1
-#define OCIE1B                          2
-#define OCIE1C                          3
-#define ICIE1                           5
-
-/* Timer/Counter Interrupt Mask register */
-#define TIMSK2                          _SFR_MEM8(0x70)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK2 {
-        unsigned int toie2 : 1;	/* Timer/Counter2 Overflow Interrupt Enable */
-        unsigned int ocie2a : 1;	/* Timer/Counter2 Output Compare Match A Interrupt Enable */
-        unsigned int ocie2b : 1;	/* Timer/Counter2 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK2 */
-
-#define TOIE2                           0
-#define TOIE2A                          0
-#define OCIE2A                          1
-#define OCIE2B                          2
-
-/* Timer/Counter3 Interrupt Mask Register */
-#define TIMSK3                          _SFR_MEM8(0x71)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK3 {
-        unsigned int toie3 : 1;	/* Timer/Counter3 Overflow Interrupt Enable */
-        unsigned int ocie3a : 1;	/* Timer/Counter3 Output Compare A Match Interrupt Enable */
-        unsigned int ocie3b : 1;	/* Timer/Counter3 Output Compare B Match Interrupt Enable */
-        unsigned int ocie3c : 1;	/* Timer/Counter3 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie3 : 1;	/* Timer/Counter3 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK3 */
-
-#define TOIE3                           0
-#define OCIE3A                          1
-#define OCIE3B                          2
-#define OCIE3C                          3
-#define ICIE3                           5
-
-/* Timer/Counter4 Interrupt Mask Register */
-#define TIMSK4                          _SFR_MEM8(0x72)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK4 {
-        unsigned int toie4 : 1;	/* Timer/Counter4 Overflow Interrupt Enable */
-        unsigned int ocie4a : 1;	/* Timer/Counter4 Output Compare A Match Interrupt Enable */
-        unsigned int ocie4b : 1;	/* Timer/Counter4 Output Compare B Match Interrupt Enable */
-        unsigned int ocie4c : 1;	/* Timer/Counter4 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie4 : 1;	/* Timer/Counter4 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK4 */
-
-#define TOIE4                           0
-#define OCIE4A                          1
-#define OCIE4B                          2
-#define OCIE4C                          3
-#define ICIE4                           5
-
-/* Timer/Counter5 Interrupt Mask Register */
-#define TIMSK5                          _SFR_MEM8(0x73)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK5 {
-        unsigned int toie5 : 1;	/* Timer/Counter5 Overflow Interrupt Enable */
-        unsigned int ocie5a : 1;	/* Timer/Counter5 Output Compare A Match Interrupt Enable */
-        unsigned int ocie5b : 1;	/* Timer/Counter5 Output Compare B Match Interrupt Enable */
-        unsigned int ocie5c : 1;	/* Timer/Counter5 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie5 : 1;	/* Timer/Counter5 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK5 */
-
-#define TOIE5                           0
-#define OCIE5A                          1
-#define OCIE5B                          2
-#define OCIE5C                          3
-#define ICIE5                           5
-
-/* Flash Extended-Mode Control-Register */
-#define NEMCR                           _SFR_MEM8(0x75)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_NEMCR {
-        unsigned int : 4;
-        unsigned int aeam : 2;	/* Address for Extended Address Mode of Extra Rows */
-        unsigned int eneam : 1;	/* Enable Extended Address Mode for Extra Rows */
-        unsigned int : 1;
-};
-
-#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* NEMCR */
-
-#define AEAM0                           4
-#define AEAM1                           5
-#define ENEAM                           6
-
-/* The ADC Control and Status Register C */
-#define ADCSRC                          _SFR_MEM8(0x77)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRC {
-        unsigned int adsut : 5;	/* ADC Start-up Time */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int adtht : 2;	/* ADC Track-and-Hold Time */
-};
-
-#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRC */
-
-#define ADSUT0                          0
-#define ADSUT1                          1
-#define ADSUT2                          2
-#define ADSUT3                          3
-#define ADSUT4                          4
-#define ADTHT0                          6
-#define ADTHT1                          7
-
-/* ADC Data Register  Bytes */
+/* Combine ADCL and ADCH */
 #ifndef __ASSEMBLER__
-#define ADC                             _SFR_MEM16(0x78)
-#define ADCL                            _SFR_MEM8(0x78)
-#define ADCH                            _SFR_MEM8(0x79)
-#endif /* __ASSEMBLER__ */
-#define ADCW                            _SFR_MEM16(0x78)
-#define ADCWL                           _SFR_MEM8(0x78)
-#define ADCWH                           _SFR_MEM8(0x79)
-
-/* The ADC Control and Status Register A */
-#define ADCSRA                          _SFR_MEM8(0x7A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRA {
-        unsigned int adps : 3;	/* ADC  Prescaler Select Bits */
-        unsigned int adie : 1;	/* ADC Interrupt Enable */
-        unsigned int adif : 1;	/* ADC Interrupt Flag */
-        unsigned int adate : 1;	/* ADC Auto Trigger Enable */
-        unsigned int adsc : 1;	/* ADC Start Conversion */
-        unsigned int aden : 1;	/* ADC Enable */
-};
-
-#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRA */
-
-#define ADPS0                           0
-#define ADPS1                           1
-#define ADPS2                           2
-#define ADIE                            3
-#define ADIF                            4
-#define ADATE                           5
-#define ADSC                            6
-#define ADEN                            7
-
-/* ADC Control and Status Register B */
-#define ADCSRB                          _SFR_MEM8(0x7B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRB {
-        unsigned int adts : 3;	/* ADC Auto Trigger Source */
-        unsigned int mux5 : 1;	/* Analog Channel and Gain Selection Bits */
-        unsigned int acch : 1;	/* Analog Channel Change */
-        unsigned int refok : 1;	/* Reference Voltage OK */
-        unsigned int acme : 1;	/* Analog Comparator Multiplexer Enable */
-        unsigned int avddok : 1;	/* AVDD Supply Voltage OK */
-};
-
-#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRB */
-
-#define ADTS0                           0
-#define ADTS1                           1
-#define ADTS2                           2
-#define MUX5                            3
-#define ACCH                            4
-#define REFOK                           5
-#define ACME                            6
-#define AVDDOK                          7
-
-/* The ADC Multiplexer Selection Register */
-#define ADMUX                           _SFR_MEM8(0x7C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADMUX {
-        unsigned int mux : 5;	/* Analog Channel and Gain Selection Bits */
-        unsigned int adlar : 1;	/* ADC Left Adjust Result */
-        unsigned int refs : 2;	/* Reference Selection Bits */
-};
-
-#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADMUX */
-
-#define MUX0                            0
-#define MUX1                            1
-#define MUX2                            2
-#define MUX3                            3
-#define MUX4                            4
-#define ADLAR                           5
-#define REFS0                           6
-#define REFS1                           7
-
-/* Digital Input Disable Register 2 */
-#define DIDR2                           _SFR_MEM8(0x7D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR2 {
-        unsigned int adc8d : 1;	/* Reserved Bits */
-        unsigned int adc9d : 1;	/* Reserved Bits */
-        unsigned int adc10d : 1;	/* Reserved Bits */
-        unsigned int adc11d : 1;	/* Reserved Bits */
-        unsigned int adc12d : 1;	/* Reserved Bits */
-        unsigned int adc13d : 1;	/* Reserved Bits */
-        unsigned int adc14d : 1;	/* Reserved Bits */
-        unsigned int adc15d : 1;	/* Reserved Bits */
-};
-
-#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR2 */
-
-#define ADC8D                           0
-#define ADC9D                           1
-#define ADC10D                          2
-#define ADC11D                          3
-#define ADC12D                          4
-#define ADC13D                          5
-#define ADC14D                          6
-#define ADC15D                          7
-
-/* Digital Input Disable Register 0 */
-#define DIDR0                           _SFR_MEM8(0x7E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR0 {
-        unsigned int adc0d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc1d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc2d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc3d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc4d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc5d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc6d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc7d : 1;	/* Disable ADC7:0 Digital Input */
-};
-
-#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR0 */
-
-#define ADC0D                           0
-#define ADC1D                           1
-#define ADC2D                           2
-#define ADC3D                           3
-#define ADC4D                           4
-#define ADC5D                           5
-#define ADC6D                           6
-#define ADC7D                           7
-
-/* Digital Input Disable Register 1 */
-#define DIDR1                           _SFR_MEM8(0x7F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR1 {
-        unsigned int ain0d : 1;	/* AIN0 Digital Input Disable */
-        unsigned int ain1d : 1;	/* AIN1 Digital Input Disable */
-        unsigned int : 6;
-};
-
-#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR1 */
-
-#define AIN0D                           0
-#define AIN1D                           1
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A                          _SFR_MEM8(0x80)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1A {
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int com1c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com1b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com1a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1A */
-
-#define WGM10                           0
-#define WGM11                           1
-#define COM1C0                          2
-#define COM1C1                          3
-#define COM1B0                          4
-#define COM1B1                          5
-#define COM1A0                          6
-#define COM1A1                          7
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B                          _SFR_MEM8(0x81)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1B {
-        unsigned int cs1 : 3;	/* Clock Select */
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices1 : 1;	/* Input Capture 1 Edge Select */
-        unsigned int icnc1 : 1;	/* Input Capture 1 Noise Canceller */
-};
-
-#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1B */
-
-#define CS10                            0
-#define CS11                            1
-#define CS12                            2
-#define WGM12                           3
-#define WGM13                           4
-#define ICES1                           6
-#define ICNC1                           7
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C                          _SFR_MEM8(0x82)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1C {
-        unsigned int : 5;
-        unsigned int foc1c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc1b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc1a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1C */
-
-#define FOC1C                           5
-#define FOC1B                           6
-#define FOC1A                           7
-
-/* Timer/Counter1  Bytes */
-#define TCNT1                           _SFR_MEM16(0x84)
-#define TCNT1L                          _SFR_MEM8(0x84)
-#define TCNT1H                          _SFR_MEM8(0x85)
-
-/* Timer/Counter1 Input Capture Register  Bytes */
-#define ICR1                            _SFR_MEM16(0x86)
-#define ICR1L                           _SFR_MEM8(0x86)
-#define ICR1H                           _SFR_MEM8(0x87)
-
-/* Timer/Counter1 Output Compare Register A  Bytes */
-#define OCR1A                           _SFR_MEM16(0x88)
-#define OCR1AL                          _SFR_MEM8(0x88)
-#define OCR1AH                          _SFR_MEM8(0x89)
-
-/* Timer/Counter1 Output Compare Register B  Bytes */
-#define OCR1B                           _SFR_MEM16(0x8A)
-#define OCR1BL                          _SFR_MEM8(0x8A)
-#define OCR1BH                          _SFR_MEM8(0x8B)
-
-/* Timer/Counter1 Output Compare Register C  Bytes */
-#define OCR1C                           _SFR_MEM16(0x8C)
-#define OCR1CL                          _SFR_MEM8(0x8C)
-#define OCR1CH                          _SFR_MEM8(0x8D)
-
-/* Timer/Counter3 Control Register A */
-#define TCCR3A                          _SFR_MEM8(0x90)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3A {
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int com3c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com3b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com3a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3A */
-
-#define WGM30                           0
-#define WGM31                           1
-#define COM3C0                          2
-#define COM3C1                          3
-#define COM3B0                          4
-#define COM3B1                          5
-#define COM3A0                          6
-#define COM3A1                          7
-
-/* Timer/Counter3 Control Register B */
-#define TCCR3B                          _SFR_MEM8(0x91)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3B {
-        unsigned int cs3 : 3;	/* Clock Select */
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices3 : 1;	/* Input Capture 3 Edge Select */
-        unsigned int icnc3 : 1;	/* Input Capture 3 Noise Canceller */
-};
-
-#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3B */
-
-#define CS30                            0
-#define CS31                            1
-#define CS32                            2
-#define WGM32                           3
-#define WGM33                           4
-#define ICES3                           6
-#define ICNC3                           7
-
-/* Timer/Counter3 Control Register C */
-#define TCCR3C                          _SFR_MEM8(0x92)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3C {
-        unsigned int : 5;
-        unsigned int foc3c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc3b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc3a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3C */
-
-#define FOC3C                           5
-#define FOC3B                           6
-#define FOC3A                           7
-
-/* Timer/Counter3  Bytes */
-#define TCNT3                           _SFR_MEM16(0x94)
-#define TCNT3L                          _SFR_MEM8(0x94)
-#define TCNT3H                          _SFR_MEM8(0x95)
-
-/* Timer/Counter3 Input Capture Register  Bytes */
-#define ICR3                            _SFR_MEM16(0x96)
-#define ICR3L                           _SFR_MEM8(0x96)
-#define ICR3H                           _SFR_MEM8(0x97)
-
-/* Timer/Counter3 Output Compare Register A  Bytes */
-#define OCR3A                           _SFR_MEM16(0x98)
-#define OCR3AL                          _SFR_MEM8(0x98)
-#define OCR3AH                          _SFR_MEM8(0x99)
-
-/* Timer/Counter3 Output Compare Register B  Bytes */
-#define OCR3B                           _SFR_MEM16(0x9A)
-#define OCR3BL                          _SFR_MEM8(0x9A)
-#define OCR3BH                          _SFR_MEM8(0x9B)
-
-/* Timer/Counter3 Output Compare Register C  Bytes */
-#define OCR3C                           _SFR_MEM16(0x9C)
-#define OCR3CL                          _SFR_MEM8(0x9C)
-#define OCR3CH                          _SFR_MEM8(0x9D)
-
-/* Timer/Counter4 Control Register A */
-#define TCCR4A                          _SFR_MEM8(0xA0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4A {
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int com4c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com4b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com4a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4A */
-
-#define WGM40                           0
-#define WGM41                           1
-#define COM4C0                          2
-#define COM4C1                          3
-#define COM4B0                          4
-#define COM4B1                          5
-#define COM4A0                          6
-#define COM4A1                          7
-
-/* Timer/Counter4 Control Register B */
-#define TCCR4B                          _SFR_MEM8(0xA1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4B {
-        unsigned int cs4 : 3;	/* Clock Select */
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices4 : 1;	/* Input Capture 4 Edge Select */
-        unsigned int icnc4 : 1;	/* Input Capture 4 Noise Canceller */
-};
-
-#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4B */
-
-#define CS40                            0
-#define CS41                            1
-#define CS42                            2
-#define WGM42                           3
-#define WGM43                           4
-#define ICES4                           6
-#define ICNC4                           7
-
-/* Timer/Counter4 Control Register C */
-#define TCCR4C                          _SFR_MEM8(0xA2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4C {
-        unsigned int : 5;
-        unsigned int foc4c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc4b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc4a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4C */
-
-#define FOC4C                           5
-#define FOC4B                           6
-#define FOC4A                           7
-
-/* Timer/Counter4  Bytes */
-#define TCNT4                           _SFR_MEM16(0xA4)
-#define TCNT4L                          _SFR_MEM8(0xA4)
-#define TCNT4H                          _SFR_MEM8(0xA5)
-
-/* Timer/Counter4 Input Capture Register  Bytes */
-#define ICR4                            _SFR_MEM16(0xA6)
-#define ICR4L                           _SFR_MEM8(0xA6)
-#define ICR4H                           _SFR_MEM8(0xA7)
-
-/* Timer/Counter4 Output Compare Register A  Bytes */
-#define OCR4A                           _SFR_MEM16(0xA8)
-#define OCR4AL                          _SFR_MEM8(0xA8)
-#define OCR4AH                          _SFR_MEM8(0xA9)
-
-/* Timer/Counter4 Output Compare Register B  Bytes */
-#define OCR4B                           _SFR_MEM16(0xAA)
-#define OCR4BL                          _SFR_MEM8(0xAA)
-#define OCR4BH                          _SFR_MEM8(0xAB)
-
-/* Timer/Counter4 Output Compare Register C  Bytes */
-#define OCR4C                           _SFR_MEM16(0xAC)
-#define OCR4CL                          _SFR_MEM8(0xAC)
-#define OCR4CH                          _SFR_MEM8(0xAD)
-
-/* Timer/Counter2 Control Register A */
-#define TCCR2A                          _SFR_MEM8(0xB0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2A {
-        unsigned int wgm2 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com2b : 2;	/* Compare Match Output B Mode */
-        unsigned int com2a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2A */
-
-#define WGM20                           0
-#define WGM21                           1
-#define COM2B0                          4
-#define COM2B1                          5
-#define COM2A0                          6
-#define COM2A1                          7
-
-/* Timer/Counter2 Control Register B */
-#define TCCR2B                          _SFR_MEM8(0xB1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2B {
-        unsigned int cs2 : 3;	/* Clock Select */
-        unsigned int wgm22 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc2b : 1;	/* Force Output Compare B */
-        unsigned int foc2a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2B */
-
-#define CS20                            0
-#define CS21                            1
-#define CS22                            2
-#define WGM22                           3
-#define FOC2B                           6
-#define FOC2A                           7
-
-/* Timer/Counter2 */
-#define TCNT2                           _SFR_MEM8(0xB2)
-
-  /* TCNT2 */
-
-#define TCNT20                          0
-#define TCNT21                          1
-#define TCNT22                          2
-#define TCNT23                          3
-#define TCNT24                          4
-#define TCNT25                          5
-#define TCNT26                          6
-#define TCNT27                          7
-
-/* Timer/Counter2 Output Compare Register A */
-#define OCR2A                           _SFR_MEM8(0xB3)
-
-  /* OCR2A */
-
-#define OCR2A0                          0
-#define OCR2A1                          1
-#define OCR2A2                          2
-#define OCR2A3                          3
-#define OCR2A4                          4
-#define OCR2A5                          5
-#define OCR2A6                          6
-#define OCR2A7                          7
-
-/* Timer/Counter2 Output Compare Register B */
-#define OCR2B                           _SFR_MEM8(0xB4)
-
-  /* OCR2B */
-
-#define OCR2B0                          0
-#define OCR2B1                          1
-#define OCR2B2                          2
-#define OCR2B3                          3
-#define OCR2B4                          4
-#define OCR2B5                          5
-#define OCR2B6                          6
-#define OCR2B7                          7
-
-/* Asynchronous Status Register */
-#define ASSR                            _SFR_MEM8(0xB6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ASSR {
-        unsigned int tcr2bub : 1;	/* Timer/Counter2 Control Register B Update Busy */
-        unsigned int tcr2aub : 1;	/* Timer/Counter2 Control Register A Update Busy */
-        unsigned int ocr2bub : 1;	/* Timer/Counter2 Output Compare Register B Update Busy */
-        unsigned int ocr2aub : 1;	/* Timer/Counter2 Output Compare Register A Update Busy */
-        unsigned int tcn2ub : 1;	/* Timer/Counter2 Update Busy */
-        unsigned int as2 : 1;	/* Timer/Counter2 Asynchronous Mode */
-        unsigned int exclk : 1;	/* Enable External Clock Input */
-        unsigned int exclkamr : 1;	/* Enable External Clock Input for AMR */
-};
-
-#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ASSR */
-
-#define TCR2BUB                         0
-#define TCR2AUB                         1
-#define OCR2BUB                         2
-#define OCR2AUB                         3
-#define TCN2UB                          4
-#define AS2                             5
-#define EXCLK                           6
-#define EXCLKAMR                        7
-
-/* TWI Bit Rate Register */
-#define TWBR                            _SFR_MEM8(0xB8)
-
-  /* TWBR */
-
-#define TWBR0                           0
-#define TWBR1                           1
-#define TWBR2                           2
-#define TWBR3                           3
-#define TWBR4                           4
-#define TWBR5                           5
-#define TWBR6                           6
-#define TWBR7                           7
-
-/* TWI Status Register */
-#define TWSR                            _SFR_MEM8(0xB9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWSR {
-        unsigned int twps : 2;	/* TWI Prescaler Bits */
-        unsigned int : 1;
-        unsigned int tws : 5;	/* TWI Status */
-};
-
-#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWSR */
-
-#define TWPS0                           0
-#define TWPS1                           1
-#define TWS3                            3
-#define TWS4                            4
-#define TWS5                            5
-#define TWS6                            6
-#define TWS7                            7
-
-/* TWI (Slave) Address Register */
-#define TWAR                            _SFR_MEM8(0xBA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAR {
-        unsigned int twgce : 1;	/* TWI General Call Recognition Enable Bit */
-        unsigned int twa : 7;	/* TWI (Slave) Address */
-};
-
-#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAR */
-
-#define TWGCE                           0
-#define TWA0                            1
-#define TWA1                            2
-#define TWA2                            3
-#define TWA3                            4
-#define TWA4                            5
-#define TWA5                            6
-#define TWA6                            7
-
-/* TWI Data Register */
-#define TWDR                            _SFR_MEM8(0xBB)
-
-  /* TWDR */
-
-#define TWD0                            0
-#define TWD1                            1
-#define TWD2                            2
-#define TWD3                            3
-#define TWD4                            4
-#define TWD5                            5
-#define TWD6                            6
-#define TWD7                            7
-
-/* TWI Control Register */
-#define TWCR                            _SFR_MEM8(0xBC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWCR {
-        unsigned int twie : 1;	/* TWI Interrupt Enable */
-        unsigned int : 1;
-        unsigned int twen : 1;	/* TWI Enable Bit */
-        unsigned int twwc : 1;	/* TWI Write Collision Flag */
-        unsigned int twsto : 1;	/* TWI STOP Condition Bit */
-        unsigned int twsta : 1;	/* TWI START Condition Bit */
-        unsigned int twea : 1;	/* TWI Enable Acknowledge Bit */
-        unsigned int twint : 1;	/* TWI Interrupt Flag */
-};
-
-#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWCR */
-
-#define TWIE                            0
-#define TWEN                            2
-#define TWWC                            3
-#define TWSTO                           4
-#define TWSTA                           5
-#define TWEA                            6
-#define TWINT                           7
-
-/* TWI (Slave) Address Mask Register */
-#define TWAMR                           _SFR_MEM8(0xBD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAMR {
-        unsigned int : 1;
-        unsigned int twam : 7;	/* TWI Address Mask */
-};
-
-#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAMR */
-
-#define TWAM0                           1
-#define TWAMR0                          1
-#define TWAM1                           2
-#define TWAMR1                          2
-#define TWAM2                           3
-#define TWAMR2                          3
-#define TWAM3                           4
-#define TWAMR3                          4
-#define TWAM4                           5
-#define TWAMR4                          5
-#define TWAM5                           6
-#define TWAMR5                          6
-#define TWAM6                           7
-#define TWAMR6                          7
-
-/* Transceiver Interrupt Enable Register 1 */
-#define IRQ_MASK1                       _SFR_MEM8(0xBE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK1 {
-        unsigned int tx_start_en : 1;	/* Transmit Start Interrupt enable */
-        unsigned int maf_0_ami_en : 1;	/* Address Match Interrupt enable Address filter 0 */
-        unsigned int maf_1_ami_en : 1;	/* Address Match Interrupt enable Address filter 1 */
-        unsigned int maf_2_ami_en : 1;	/* Address Match Interrupt enable Address filter 2 */
-        unsigned int maf_3_ami_en : 1;	/* Address Match Interrupt enable Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_MASK1_struct _SFR_MEM8_STRUCT(0xbe, struct __reg_IRQ_MASK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK1 */
-
-#define TX_START_EN                     0
-#define MAF_0_AMI_EN                    1
-#define MAF_1_AMI_EN                    2
-#define MAF_2_AMI_EN                    3
-#define MAF_3_AMI_EN                    4
-
-/* Transceiver Interrupt Status Register 1 */
-#define IRQ_STATUS1                     _SFR_MEM8(0xBF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS1 {
-        unsigned int tx_start : 1;	/* Transmit Start Interrupt Status */
-        unsigned int maf_0_ami : 1;	/* Address Match Interrupt Status Address filter 0 */
-        unsigned int maf_1_ami : 1;	/* Address Match Interrupt Status Address filter 1 */
-        unsigned int maf_2_ami : 1;	/* Address Match Interrupt Status Address filter 2 */
-        unsigned int maf_3_ami : 1;	/* Address Match Interrupt Status Address filter 3 */
-        unsigned int : 3;
-};
-
-#define IRQ_STATUS1_struct _SFR_MEM8_STRUCT(0xbf, struct __reg_IRQ_STATUS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS1 */
-
-#define TX_START                        0
-#define MAF_0_AMI                       1
-#define MAF_1_AMI                       2
-#define MAF_2_AMI                       3
-#define MAF_3_AMI                       4
-
-/* USART0 Control and Status Register A */
-#define UCSR0A                          _SFR_MEM8(0xC0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0A {
-        unsigned int mpcm0 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x0 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe0 : 1;	/* USART Parity Error */
-        unsigned int dor0 : 1;	/* Data OverRun */
-        unsigned int fe0 : 1;	/* Frame Error */
-        unsigned int udre0 : 1;	/* USART Data Register Empty */
-        unsigned int txc0 : 1;	/* USART Transmit Complete */
-        unsigned int rxc0 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0A */
-
-#define MPCM0                           0
-#define U2X0                            1
-#define UPE0                            2
-#define DOR0                            3
-#define FE0                             4
-#define UDRE0                           5
-#define TXC0                            6
-#define RXC0                            7
-
-/* USART0 Control and Status Register B */
-#define UCSR0B                          _SFR_MEM8(0xC1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0B {
-        unsigned int txb80 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb80 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz02 : 1;	/* Character Size */
-        unsigned int txen0 : 1;	/* Transmitter Enable */
-        unsigned int rxen0 : 1;	/* Receiver Enable */
-        unsigned int udrie0 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie0 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie0 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0B */
-
-#define TXB80                           0
-#define RXB80                           1
-#define UCSZ02                          2
-#define TXEN0                           3
-#define RXEN0                           4
-#define UDRIE0                          5
-#define TXCIE0                          6
-#define RXCIE0                          7
-
-/* USART0 Control and Status Register C */
-#define UCSR0C                          _SFR_MEM8(0xC2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0C {
-        unsigned int ucpol0 : 1;	/* Clock Polarity */
-        unsigned int ucsz0 : 2;	/* Character Size */
-        unsigned int ucpha0 : 1;	/* Clock Phase */
-        unsigned int udord0 : 1;	/* Data Order */
-        unsigned int usbs0 : 1;	/* Stop Bit Select */
-        unsigned int upm0 : 2;	/* Parity Mode */
-        unsigned int umsel0 : 2;	/* USART Mode Select */
-};
-
-#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0C */
-
-#define UCPOL0                          0
-#define UCPHA0                          1
-#define UCPHA0                          1
-#define UCSZ00                          1
-#define UDORD0                          2
-#define UDORD0                          2
-#define UCSZ01                          2
-#define USBS0                           3
-#define UPM00                           4
-#define UPM01                           5
-#define UMSEL00                         6
-#define UMSEL0                          6
-#define UMSEL01                         7
-#define UMSEL1                          7
-
-/* USART0 Baud Rate Register  Bytes */
-#define UBRR0                           _SFR_MEM16(0xC4)
-#define UBRR0L                          _SFR_MEM8(0xC4)
-#define UBRR0H                          _SFR_MEM8(0xC5)
-
-/* USART0 I/O Data Register */
-#define UDR0                            _SFR_MEM8(0xC6)
-
-  /* UDR0 */
-
-#define UDR00                           0
-#define UDR01                           1
-#define UDR02                           2
-#define UDR03                           3
-#define UDR04                           4
-#define UDR05                           5
-#define UDR06                           6
-#define UDR07                           7
-
-/* USART1 Control and Status Register A */
-#define UCSR1A                          _SFR_MEM8(0xC8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1A {
-        unsigned int mpcm1 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x1 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe1 : 1;	/* USART Parity Error */
-        unsigned int dor1 : 1;	/* Data OverRun */
-        unsigned int fe1 : 1;	/* Frame Error */
-        unsigned int udre1 : 1;	/* USART Data Register Empty */
-        unsigned int txc1 : 1;	/* USART Transmit Complete */
-        unsigned int rxc1 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1A */
-
-#define MPCM1                           0
-#define U2X1                            1
-#define UPE1                            2
-#define DOR1                            3
-#define FE1                             4
-#define UDRE1                           5
-#define TXC1                            6
-#define RXC1                            7
-
-/* USART1 Control and Status Register B */
-#define UCSR1B                          _SFR_MEM8(0xC9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1B {
-        unsigned int txb81 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb81 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz12 : 1;	/* Character Size */
-        unsigned int txen1 : 1;	/* Transmitter Enable */
-        unsigned int rxen1 : 1;	/* Receiver Enable */
-        unsigned int udrie1 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie1 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie1 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1B */
-
-#define TXB81                           0
-#define RXB81                           1
-#define UCSZ12                          2
-#define TXEN1                           3
-#define RXEN1                           4
-#define UDRIE1                          5
-#define TXCIE1                          6
-#define RXCIE1                          7
-
-/* USART1 Control and Status Register C */
-#define UCSR1C                          _SFR_MEM8(0xCA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1C {
-        unsigned int ucpol1 : 1;	/* Clock Polarity */
-        unsigned int ucsz1 : 2;	/* Character Size */
-        unsigned int ucpha1 : 1;	/* Clock Phase */
-        unsigned int udord1 : 1;	/* Data Order */
-        unsigned int usbs1 : 1;	/* Stop Bit Select */
-        unsigned int upm1 : 2;	/* Parity Mode */
-        unsigned int umsel1 : 2;	/* USART Mode Select */
-};
-
-#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1C */
-
-#define UCPOL1                          0
-#define UCPHA1                          1
-#define UCPHA1                          1
-#define UCSZ10                          1
-#define UDORD1                          2
-#define UDORD1                          2
-#define UCSZ11                          2
-#define USBS1                           3
-#define UPM10                           4
-#define UPM11                           5
-#define UMSEL10                         6
-#define UMSEL11                         7
-
-/* USART1 Baud Rate Register  Bytes */
-#define UBRR1                           _SFR_MEM16(0xCC)
-#define UBRR1L                          _SFR_MEM8(0xCC)
-#define UBRR1H                          _SFR_MEM8(0xCD)
-
-/* USART1 I/O Data Register */
-#define UDR1                            _SFR_MEM8(0xCE)
-
-  /* UDR1 */
-
-#define UDR10                           0
-#define UDR11                           1
-#define UDR12                           2
-#define UDR13                           3
-#define UDR14                           4
-#define UDR15                           5
-#define UDR16                           6
-#define UDR17                           7
-
-/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-#define SCRSTRLL                        _SFR_MEM8(0xD7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLL {
-        unsigned int scrstrll : 8;	/* Symbol Counter Received Frame Timestamp Register LL-Byte */
-};
-
-#define SCRSTRLL_struct _SFR_MEM8_STRUCT(0xd7, struct __reg_SCRSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLL */
-
-#define SCRSTRLL0                       0
-#define SCRSTRLL1                       1
-#define SCRSTRLL2                       2
-#define SCRSTRLL3                       3
-#define SCRSTRLL4                       4
-#define SCRSTRLL5                       5
-#define SCRSTRLL6                       6
-#define SCRSTRLL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-#define SCRSTRLH                        _SFR_MEM8(0xD8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRLH {
-        unsigned int scrstrlh : 8;	/* Symbol Counter Received Frame Timestamp Register LH-Byte */
-};
-
-#define SCRSTRLH_struct _SFR_MEM8_STRUCT(0xd8, struct __reg_SCRSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRLH */
-
-#define SCRSTRLH0                       0
-#define SCRSTRLH1                       1
-#define SCRSTRLH2                       2
-#define SCRSTRLH3                       3
-#define SCRSTRLH4                       4
-#define SCRSTRLH5                       5
-#define SCRSTRLH6                       6
-#define SCRSTRLH7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-#define SCRSTRHL                        _SFR_MEM8(0xD9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHL {
-        unsigned int scrstrhl : 8;	/* Symbol Counter Received Frame Timestamp Register HL-Byte */
-};
-
-#define SCRSTRHL_struct _SFR_MEM8_STRUCT(0xd9, struct __reg_SCRSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHL */
-
-#define SCRSTRHL0                       0
-#define SCRSTRHL1                       1
-#define SCRSTRHL2                       2
-#define SCRSTRHL3                       3
-#define SCRSTRHL4                       4
-#define SCRSTRHL5                       5
-#define SCRSTRHL6                       6
-#define SCRSTRHL7                       7
-
-/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-#define SCRSTRHH                        _SFR_MEM8(0xDA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCRSTRHH {
-        unsigned int scrstrhh : 8;	/* Symbol Counter Received Frame Timestamp Register HH-Byte */
-};
-
-#define SCRSTRHH_struct _SFR_MEM8_STRUCT(0xda, struct __reg_SCRSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCRSTRHH */
-
-#define SCRSTRHH0                       0
-#define SCRSTRHH1                       1
-#define SCRSTRHH2                       2
-#define SCRSTRHH3                       3
-#define SCRSTRHH4                       4
-#define SCRSTRHH5                       5
-#define SCRSTRHH6                       6
-#define SCRSTRHH7                       7
-
-/* Symbol Counter Compare Source Register */
-#define SCCSR                           _SFR_MEM8(0xDB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCSR {
-        unsigned int sccs1 : 2;	/* Symbol Counter Compare Source select register for Compare Units */
-        unsigned int sccs2 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 2 */
-        unsigned int sccs3 : 2;	/* Symbol Counter Compare Source select register for Compare Unit 3 */
-        unsigned int : 2;
-};
-
-#define SCCSR_struct _SFR_MEM8_STRUCT(0xdb, struct __reg_SCCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCSR */
-
-#define SCCS10                          0
-#define SCCS11                          1
-#define SCCS20                          2
-#define SCCS21                          3
-#define SCCS30                          4
-#define SCCS31                          5
-
-/* Symbol Counter Control Register 0 */
-#define SCCR0                           _SFR_MEM8(0xDC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR0 {
-        unsigned int sccmp : 3;	/* Symbol Counter Compare Unit 3 Mode select */
-        unsigned int sctse : 1;	/* Symbol Counter Automatic Timestamping enable */
-        unsigned int sccksel : 1;	/* Symbol Counter Clock Source select */
-        unsigned int scen : 1;	/* Symbol Counter enable */
-        unsigned int scmbts : 1;	/* Manual Beacon Timestamp */
-        unsigned int scres : 1;	/* Symbol Counter Synchronization */
-};
-
-#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR0 */
-
-#define SCCMP1                          0
-#define SCCMP2                          1
-#define SCCMP3                          2
-#define SCTSE                           3
-#define SCCKSEL                         4
-#define SCEN                            5
-#define SCMBTS                          6
-#define SCRES                           7
-
-/* Symbol Counter Control Register 1 */
-#define SCCR1                           _SFR_MEM8(0xDD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR1 {
-        unsigned int scenbo : 1;	/* Backoff Slot Counter enable */
-        unsigned int sceeclk : 1;	/* Enable External Clock Source on PG2 */
-        unsigned int scckdiv : 3;	/* Clock divider for synchronous clock source (16MHz Transceiver Clock) */
-        unsigned int scbtsm : 1;	/* Symbol Counter Beacon Timestamp Mask Register */
-        unsigned int : 2;
-};
-
-#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR1 */
-
-#define SCENBO                          0
-#define SCEECLK                         1
-#define SCCKDIV0                        2
-#define SCCKDIV1                        3
-#define SCCKDIV2                        4
-#define SCBTSM                          5
-
-/* Symbol Counter Status Register */
-#define SCSR                            _SFR_MEM8(0xDE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCSR {
-        unsigned int scbsy : 1;	/* Symbol Counter busy */
-        unsigned int : 7;
-};
-
-#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCSR */
-
-#define SCBSY                           0
-
-/* Symbol Counter Interrupt Mask Register */
-#define SCIRQM                          _SFR_MEM8(0xDF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQM {
-        unsigned int irqmcp : 3;	/* Symbol Counter Compare Match 3 IRQ enable */
-        unsigned int irqmof : 1;	/* Symbol Counter Overflow IRQ enable */
-        unsigned int irqmbo : 1;	/* Backoff Slot Counter IRQ enable */
-        unsigned int : 3;
-};
-
-#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQM */
-
-#define IRQMCP1                         0
-#define IRQMCP2                         1
-#define IRQMCP3                         2
-#define IRQMOF                          3
-#define IRQMBO                          4
-
-/* Symbol Counter Interrupt Status Register */
-#define SCIRQS                          _SFR_MEM8(0xE0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQS {
-        unsigned int irqscp : 3;	/* Compare Unit 3 Compare Match IRQ */
-        unsigned int irqsof : 1;	/* Symbol Counter Overflow IRQ */
-        unsigned int irqsbo : 1;	/* Backoff Slot Counter IRQ */
-        unsigned int : 3;
-};
-
-#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQS */
-
-#define IRQSCP1                         0
-#define IRQSCP2                         1
-#define IRQSCP3                         2
-#define IRQSOF                          3
-#define IRQSBO                          4
-
-/* Symbol Counter Register LL-Byte */
-#define SCCNTLL                         _SFR_MEM8(0xE1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLL {
-        unsigned int sccntll : 8;	/* Symbol Counter Register LL-Byte */
-};
-
-#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLL */
-
-#define SCCNTLL0                        0
-#define SCCNTLL1                        1
-#define SCCNTLL2                        2
-#define SCCNTLL3                        3
-#define SCCNTLL4                        4
-#define SCCNTLL5                        5
-#define SCCNTLL6                        6
-#define SCCNTLL7                        7
-
-/* Symbol Counter Register LH-Byte */
-#define SCCNTLH                         _SFR_MEM8(0xE2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLH {
-        unsigned int sccntlh : 8;	/* Symbol Counter Register LH-Byte */
-};
-
-#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLH */
-
-#define SCCNTLH0                        0
-#define SCCNTLH1                        1
-#define SCCNTLH2                        2
-#define SCCNTLH3                        3
-#define SCCNTLH4                        4
-#define SCCNTLH5                        5
-#define SCCNTLH6                        6
-#define SCCNTLH7                        7
-
-/* Symbol Counter Register HL-Byte */
-#define SCCNTHL                         _SFR_MEM8(0xE3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHL {
-        unsigned int sccnthl : 8;	/* Symbol Counter Register HL-Byte */
-};
-
-#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHL */
-
-#define SCCNTHL0                        0
-#define SCCNTHL1                        1
-#define SCCNTHL2                        2
-#define SCCNTHL3                        3
-#define SCCNTHL4                        4
-#define SCCNTHL5                        5
-#define SCCNTHL6                        6
-#define SCCNTHL7                        7
-
-/* Symbol Counter Register HH-Byte */
-#define SCCNTHH                         _SFR_MEM8(0xE4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHH {
-        unsigned int sccnthh : 8;	/* Symbol Counter Register HH-Byte */
-};
-
-#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHH */
-
-#define SCCNTHH0                        0
-#define SCCNTHH1                        1
-#define SCCNTHH2                        2
-#define SCCNTHH3                        3
-#define SCCNTHH4                        4
-#define SCCNTHH5                        5
-#define SCCNTHH6                        6
-#define SCCNTHH7                        7
-
-/* Symbol Counter Beacon Timestamp Register LL-Byte */
-#define SCBTSRLL                        _SFR_MEM8(0xE5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLL {
-        unsigned int scbtsrll : 8;	/* Symbol Counter Beacon Timestamp Register LL-Byte */
-};
-
-#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLL */
-
-#define SCBTSRLL0                       0
-#define SCBTSRLL1                       1
-#define SCBTSRLL2                       2
-#define SCBTSRLL3                       3
-#define SCBTSRLL4                       4
-#define SCBTSRLL5                       5
-#define SCBTSRLL6                       6
-#define SCBTSRLL7                       7
-
-/* Symbol Counter Beacon Timestamp Register LH-Byte */
-#define SCBTSRLH                        _SFR_MEM8(0xE6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLH {
-        unsigned int scbtsrlh : 8;	/* Symbol Counter Beacon Timestamp Register LH-Byte */
-};
-
-#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLH */
-
-#define SCBTSRLH0                       0
-#define SCBTSRLH1                       1
-#define SCBTSRLH2                       2
-#define SCBTSRLH3                       3
-#define SCBTSRLH4                       4
-#define SCBTSRLH5                       5
-#define SCBTSRLH6                       6
-#define SCBTSRLH7                       7
-
-/* Symbol Counter Beacon Timestamp Register HL-Byte */
-#define SCBTSRHL                        _SFR_MEM8(0xE7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHL {
-        unsigned int scbtsrhl : 8;	/* Symbol Counter Beacon Timestamp Register HL-Byte */
-};
-
-#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHL */
-
-#define SCBTSRHL0                       0
-#define SCBTSRHL1                       1
-#define SCBTSRHL2                       2
-#define SCBTSRHL3                       3
-#define SCBTSRHL4                       4
-#define SCBTSRHL5                       5
-#define SCBTSRHL6                       6
-#define SCBTSRHL7                       7
-
-/* Symbol Counter Beacon Timestamp Register HH-Byte */
-#define SCBTSRHH                        _SFR_MEM8(0xE8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHH {
-        unsigned int scbtsrhh : 8;	/* Symbol Counter Beacon Timestamp Register HH-Byte */
-};
-
-#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHH */
-
-#define SCBTSRHH0                       0
-#define SCBTSRHH1                       1
-#define SCBTSRHH2                       2
-#define SCBTSRHH3                       3
-#define SCBTSRHH4                       4
-#define SCBTSRHH5                       5
-#define SCBTSRHH6                       6
-#define SCBTSRHH7                       7
-
-/* Symbol Counter Frame Timestamp Register LL-Byte */
-#define SCTSRLL                         _SFR_MEM8(0xE9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLL {
-        unsigned int sctsrll : 8;	/* Symbol Counter Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLL */
-
-#define SCTSRLL0                        0
-#define SCTSRLL1                        1
-#define SCTSRLL2                        2
-#define SCTSRLL3                        3
-#define SCTSRLL4                        4
-#define SCTSRLL5                        5
-#define SCTSRLL6                        6
-#define SCTSRLL7                        7
-
-/* Symbol Counter Frame Timestamp Register LH-Byte */
-#define SCTSRLH                         _SFR_MEM8(0xEA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLH {
-        unsigned int sctsrlh : 8;	/* Symbol Counter Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLH */
-
-#define SCTSRLH0                        0
-#define SCTSRLH1                        1
-#define SCTSRLH2                        2
-#define SCTSRLH3                        3
-#define SCTSRLH4                        4
-#define SCTSRLH5                        5
-#define SCTSRLH6                        6
-#define SCTSRLH7                        7
-
-/* Symbol Counter Frame Timestamp Register HL-Byte */
-#define SCTSRHL                         _SFR_MEM8(0xEB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHL {
-        unsigned int sctsrhl : 8;	/* Symbol Counter Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHL */
-
-#define SCTSRHL0                        0
-#define SCTSRHL1                        1
-#define SCTSRHL2                        2
-#define SCTSRHL3                        3
-#define SCTSRHL4                        4
-#define SCTSRHL5                        5
-#define SCTSRHL6                        6
-#define SCTSRHL7                        7
-
-/* Symbol Counter Frame Timestamp Register HH-Byte */
-#define SCTSRHH                         _SFR_MEM8(0xEC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHH {
-        unsigned int sctsrhh : 8;	/* Symbol Counter Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHH */
-
-#define SCTSRHH0                        0
-#define SCTSRHH1                        1
-#define SCTSRHH2                        2
-#define SCTSRHH3                        3
-#define SCTSRHH4                        4
-#define SCTSRHH5                        5
-#define SCTSRHH6                        6
-#define SCTSRHH7                        7
-
-/* Symbol Counter Output Compare Register 3 LL-Byte */
-#define SCOCR3LL                        _SFR_MEM8(0xED)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LL {
-        unsigned int scocr3ll : 8;	/* Symbol Counter Output Compare Register 3 LL-Byte */
-};
-
-#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LL */
-
-#define SCOCR3LL0                       0
-#define SCOCR3LL1                       1
-#define SCOCR3LL2                       2
-#define SCOCR3LL3                       3
-#define SCOCR3LL4                       4
-#define SCOCR3LL5                       5
-#define SCOCR3LL6                       6
-#define SCOCR3LL7                       7
-
-/* Symbol Counter Output Compare Register 3 LH-Byte */
-#define SCOCR3LH                        _SFR_MEM8(0xEE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LH {
-        unsigned int scocr3lh : 8;	/* Symbol Counter Output Compare Register 3 LH-Byte */
-};
-
-#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LH */
-
-#define SCOCR3LH0                       0
-#define SCOCR3LH1                       1
-#define SCOCR3LH2                       2
-#define SCOCR3LH3                       3
-#define SCOCR3LH4                       4
-#define SCOCR3LH5                       5
-#define SCOCR3LH6                       6
-#define SCOCR3LH7                       7
-
-/* Symbol Counter Output Compare Register 3 HL-Byte */
-#define SCOCR3HL                        _SFR_MEM8(0xEF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HL {
-        unsigned int scocr3hl : 8;	/* Symbol Counter Output Compare Register 3 HL-Byte */
-};
-
-#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HL */
-
-#define SCOCR3HL0                       0
-#define SCOCR3HL1                       1
-#define SCOCR3HL2                       2
-#define SCOCR3HL3                       3
-#define SCOCR3HL4                       4
-#define SCOCR3HL5                       5
-#define SCOCR3HL6                       6
-#define SCOCR3HL7                       7
-
-/* Symbol Counter Output Compare Register 3 HH-Byte */
-#define SCOCR3HH                        _SFR_MEM8(0xF0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HH {
-        unsigned int scocr3hh : 8;	/* Symbol Counter Output Compare Register 3 HH-Byte */
-};
-
-#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HH */
-
-#define SCOCR3HH0                       0
-#define SCOCR3HH1                       1
-#define SCOCR3HH2                       2
-#define SCOCR3HH3                       3
-#define SCOCR3HH4                       4
-#define SCOCR3HH5                       5
-#define SCOCR3HH6                       6
-#define SCOCR3HH7                       7
-
-/* Symbol Counter Output Compare Register 2 LL-Byte */
-#define SCOCR2LL                        _SFR_MEM8(0xF1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LL {
-        unsigned int scocr2ll : 8;	/* Symbol Counter Output Compare Register 2 LL-Byte */
-};
-
-#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LL */
-
-#define SCOCR2LL0                       0
-#define SCOCR2LL1                       1
-#define SCOCR2LL2                       2
-#define SCOCR2LL3                       3
-#define SCOCR2LL4                       4
-#define SCOCR2LL5                       5
-#define SCOCR2LL6                       6
-#define SCOCR2LL7                       7
-
-/* Symbol Counter Output Compare Register 2 LH-Byte */
-#define SCOCR2LH                        _SFR_MEM8(0xF2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LH {
-        unsigned int scocr2lh : 8;	/* Symbol Counter Output Compare Register 2 LH-Byte */
-};
-
-#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LH */
-
-#define SCOCR2LH0                       0
-#define SCOCR2LH1                       1
-#define SCOCR2LH2                       2
-#define SCOCR2LH3                       3
-#define SCOCR2LH4                       4
-#define SCOCR2LH5                       5
-#define SCOCR2LH6                       6
-#define SCOCR2LH7                       7
-
-/* Symbol Counter Output Compare Register 2 HL-Byte */
-#define SCOCR2HL                        _SFR_MEM8(0xF3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HL {
-        unsigned int scocr2hl : 8;	/* Symbol Counter Output Compare Register 2 HL-Byte */
-};
-
-#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HL */
-
-#define SCOCR2HL0                       0
-#define SCOCR2HL1                       1
-#define SCOCR2HL2                       2
-#define SCOCR2HL3                       3
-#define SCOCR2HL4                       4
-#define SCOCR2HL5                       5
-#define SCOCR2HL6                       6
-#define SCOCR2HL7                       7
-
-/* Symbol Counter Output Compare Register 2 HH-Byte */
-#define SCOCR2HH                        _SFR_MEM8(0xF4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HH {
-        unsigned int scocr2hh : 8;	/* Symbol Counter Output Compare Register 2 HH-Byte */
-};
-
-#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HH */
-
-#define SCOCR2HH0                       0
-#define SCOCR2HH1                       1
-#define SCOCR2HH2                       2
-#define SCOCR2HH3                       3
-#define SCOCR2HH4                       4
-#define SCOCR2HH5                       5
-#define SCOCR2HH6                       6
-#define SCOCR2HH7                       7
-
-/* Symbol Counter Output Compare Register 1 LL-Byte */
-#define SCOCR1LL                        _SFR_MEM8(0xF5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LL {
-        unsigned int scocr1ll : 8;	/* Symbol Counter Output Compare Register 1 LL-Byte */
-};
-
-#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LL */
-
-#define SCOCR1LL0                       0
-#define SCOCR1LL1                       1
-#define SCOCR1LL2                       2
-#define SCOCR1LL3                       3
-#define SCOCR1LL4                       4
-#define SCOCR1LL5                       5
-#define SCOCR1LL6                       6
-#define SCOCR1LL7                       7
-
-/* Symbol Counter Output Compare Register 1 LH-Byte */
-#define SCOCR1LH                        _SFR_MEM8(0xF6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LH {
-        unsigned int scocr1lh : 8;	/* Symbol Counter Output Compare Register 1 LH-Byte */
-};
-
-#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LH */
-
-#define SCOCR1LH0                       0
-#define SCOCR1LH1                       1
-#define SCOCR1LH2                       2
-#define SCOCR1LH3                       3
-#define SCOCR1LH4                       4
-#define SCOCR1LH5                       5
-#define SCOCR1LH6                       6
-#define SCOCR1LH7                       7
-
-/* Symbol Counter Output Compare Register 1 HL-Byte */
-#define SCOCR1HL                        _SFR_MEM8(0xF7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HL {
-        unsigned int scocr1hl : 8;	/* Symbol Counter Output Compare Register 1 HL-Byte */
-};
-
-#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HL */
-
-#define SCOCR1HL0                       0
-#define SCOCR1HL1                       1
-#define SCOCR1HL2                       2
-#define SCOCR1HL3                       3
-#define SCOCR1HL4                       4
-#define SCOCR1HL5                       5
-#define SCOCR1HL6                       6
-#define SCOCR1HL7                       7
-
-/* Symbol Counter Output Compare Register 1 HH-Byte */
-#define SCOCR1HH                        _SFR_MEM8(0xF8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HH {
-        unsigned int scocr1hh : 8;	/* Symbol Counter Output Compare Register 1 HH-Byte */
-};
-
-#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HH */
-
-#define SCOCR1HH0                       0
-#define SCOCR1HH1                       1
-#define SCOCR1HH2                       2
-#define SCOCR1HH3                       3
-#define SCOCR1HH4                       4
-#define SCOCR1HH5                       5
-#define SCOCR1HH6                       6
-#define SCOCR1HH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-#define SCTSTRLL                        _SFR_MEM8(0xF9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLL {
-        unsigned int sctstrll : 8;	/* Symbol Counter Transmit Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSTRLL_struct _SFR_MEM8_STRUCT(0xf9, struct __reg_SCTSTRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLL */
-
-#define SCTSTRLL0                       0
-#define SCTSTRLL1                       1
-#define SCTSTRLL2                       2
-#define SCTSTRLL3                       3
-#define SCTSTRLL4                       4
-#define SCTSTRLL5                       5
-#define SCTSTRLL6                       6
-#define SCTSTRLL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-#define SCTSTRLH                        _SFR_MEM8(0xFA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRLH {
-        unsigned int sctstrlh : 8;	/* Symbol Counter Transmit Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSTRLH_struct _SFR_MEM8_STRUCT(0xfa, struct __reg_SCTSTRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRLH */
-
-#define SCTSTRLH0                       0
-#define SCTSTRLH1                       1
-#define SCTSTRLH2                       2
-#define SCTSTRLH3                       3
-#define SCTSTRLH4                       4
-#define SCTSTRLH5                       5
-#define SCTSTRLH6                       6
-#define SCTSTRLH7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-#define SCTSTRHL                        _SFR_MEM8(0xFB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHL {
-        unsigned int sctstrhl : 8;	/* Symbol Counter Transmit Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSTRHL_struct _SFR_MEM8_STRUCT(0xfb, struct __reg_SCTSTRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHL */
-
-#define SCTSTRHL0                       0
-#define SCTSTRHL1                       1
-#define SCTSTRHL2                       2
-#define SCTSTRHL3                       3
-#define SCTSTRHL4                       4
-#define SCTSTRHL5                       5
-#define SCTSTRHL6                       6
-#define SCTSTRHL7                       7
-
-/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-#define SCTSTRHH                        _SFR_MEM8(0xFC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSTRHH {
-        unsigned int sctstrhh : 8;	/* Symbol Counter Transmit Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSTRHH_struct _SFR_MEM8_STRUCT(0xfc, struct __reg_SCTSTRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSTRHH */
-
-#define SCTSTRHH0                       0
-#define SCTSTRHH1                       1
-#define SCTSTRHH2                       2
-#define SCTSTRHH3                       3
-#define SCTSTRHH4                       4
-#define SCTSTRHH5                       5
-#define SCTSTRHH6                       6
-#define SCTSTRHH7                       7
-
-/* Multiple Address Filter Configuration Register 0 */
-#define MAFCR0                          _SFR_MEM8(0x10C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR0 {
-        unsigned int maf0en : 1;	/* Multiple Address Filter 0 Enable */
-        unsigned int maf1en : 1;	/* Multiple Address Filter 1 Enable */
-        unsigned int maf2en : 1;	/* Multiple Address Filter 2 Enable */
-        unsigned int maf3en : 1;	/* Multiple Address Filter 3 Enable */
-        unsigned int : 4;
-};
-
-#define MAFCR0_struct _SFR_MEM8_STRUCT(0x10c, struct __reg_MAFCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR0 */
-
-#define MAF0EN                          0
-#define MAF1EN                          1
-#define MAF2EN                          2
-#define MAF3EN                          3
-
-/* Multiple Address Filter Configuration Register 1 */
-#define MAFCR1                          _SFR_MEM8(0x10D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFCR1 {
-        unsigned int aack_0_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 0. */
-        unsigned int aack_0_set_pd : 1;	/* Set Data Pending bit for address filter 0. */
-        unsigned int aack_1_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 1. */
-        unsigned int aack_1_set_pd : 1;	/* Set Data Pending bit for address filter 1. */
-        unsigned int aack_2_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 2. */
-        unsigned int aack_2_set_pd : 1;	/* Set Data Pending bit for address filter 2. */
-        unsigned int aack_3_i_am_coord : 1;	/* Enable PAN Coordinator mode for address filter 3. */
-        unsigned int aack_3_set_pd : 1;	/* Set Data Pending bit for address filter 3. */
-};
-
-#define MAFCR1_struct _SFR_MEM8_STRUCT(0x10d, struct __reg_MAFCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFCR1 */
-
-#define AACK_0_I_AM_COORD               0
-#define AACK_0_SET_PD                   1
-#define AACK_1_I_AM_COORD               2
-#define AACK_1_SET_PD                   3
-#define AACK_2_I_AM_COORD               4
-#define AACK_2_SET_PD                   5
-#define AACK_3_I_AM_COORD               6
-#define AACK_3_SET_PD                   7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) */
-#define MAFSA0L                         _SFR_MEM8(0x10E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0L {
-        unsigned int mafsa0l : 8;	/* MAC Short Address low Byte for Frame Filter 0 */
-};
-
-#define MAFSA0L_struct _SFR_MEM8_STRUCT(0x10e, struct __reg_MAFSA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0L */
-
-#define MAFSA0L0                        0
-#define MAFSA0L1                        1
-#define MAFSA0L2                        2
-#define MAFSA0L3                        3
-#define MAFSA0L4                        4
-#define MAFSA0L5                        5
-#define MAFSA0L6                        6
-#define MAFSA0L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) */
-#define MAFSA0H                         _SFR_MEM8(0x10F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA0H {
-        unsigned int mafsa0h : 8;	/* MAC Short Address high Byte for Frame Filter 0 */
-};
-
-#define MAFSA0H_struct _SFR_MEM8_STRUCT(0x10f, struct __reg_MAFSA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA0H */
-
-#define MAFSA0H0                        0
-#define MAFSA0H1                        1
-#define MAFSA0H2                        2
-#define MAFSA0H3                        3
-#define MAFSA0H4                        4
-#define MAFSA0H5                        5
-#define MAFSA0H6                        6
-#define MAFSA0H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) */
-#define MAFPA0L                         _SFR_MEM8(0x110)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0L {
-        unsigned int mafpa0l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 0 */
-};
-
-#define MAFPA0L_struct _SFR_MEM8_STRUCT(0x110, struct __reg_MAFPA0L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0L */
-
-#define MAFPA0L0                        0
-#define MAFPA0L1                        1
-#define MAFPA0L2                        2
-#define MAFPA0L3                        3
-#define MAFPA0L4                        4
-#define MAFPA0L5                        5
-#define MAFPA0L6                        6
-#define MAFPA0L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) */
-#define MAFPA0H                         _SFR_MEM8(0x111)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA0H {
-        unsigned int mafpa0h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 0 */
-};
-
-#define MAFPA0H_struct _SFR_MEM8_STRUCT(0x111, struct __reg_MAFPA0H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA0H */
-
-#define MAFPA0H0                        0
-#define MAFPA0H1                        1
-#define MAFPA0H2                        2
-#define MAFPA0H3                        3
-#define MAFPA0H4                        4
-#define MAFPA0H5                        5
-#define MAFPA0H6                        6
-#define MAFPA0H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) */
-#define MAFSA1L                         _SFR_MEM8(0x112)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1L {
-        unsigned int mafsa1l : 8;	/* MAC Short Address low Byte for Frame Filter 1 */
-};
-
-#define MAFSA1L_struct _SFR_MEM8_STRUCT(0x112, struct __reg_MAFSA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1L */
-
-#define MAFSA1L0                        0
-#define MAFSA1L1                        1
-#define MAFSA1L2                        2
-#define MAFSA1L3                        3
-#define MAFSA1L4                        4
-#define MAFSA1L5                        5
-#define MAFSA1L6                        6
-#define MAFSA1L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) */
-#define MAFSA1H                         _SFR_MEM8(0x113)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA1H {
-        unsigned int mafsa1h : 8;	/* MAC Short Address high Byte for Frame Filter 1 */
-};
-
-#define MAFSA1H_struct _SFR_MEM8_STRUCT(0x113, struct __reg_MAFSA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA1H */
-
-#define MAFSA1H0                        0
-#define MAFSA1H1                        1
-#define MAFSA1H2                        2
-#define MAFSA1H3                        3
-#define MAFSA1H4                        4
-#define MAFSA1H5                        5
-#define MAFSA1H6                        6
-#define MAFSA1H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) */
-#define MAFPA1L                         _SFR_MEM8(0x114)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1L {
-        unsigned int mafpa1l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 1 */
-};
-
-#define MAFPA1L_struct _SFR_MEM8_STRUCT(0x114, struct __reg_MAFPA1L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1L */
-
-#define MAFPA1L0                        0
-#define MAFPA1L1                        1
-#define MAFPA1L2                        2
-#define MAFPA1L3                        3
-#define MAFPA1L4                        4
-#define MAFPA1L5                        5
-#define MAFPA1L6                        6
-#define MAFPA1L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) */
-#define MAFPA1H                         _SFR_MEM8(0x115)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA1H {
-        unsigned int mafpa1h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 1 */
-};
-
-#define MAFPA1H_struct _SFR_MEM8_STRUCT(0x115, struct __reg_MAFPA1H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA1H */
-
-#define MAFPA1H0                        0
-#define MAFPA1H1                        1
-#define MAFPA1H2                        2
-#define MAFPA1H3                        3
-#define MAFPA1H4                        4
-#define MAFPA1H5                        5
-#define MAFPA1H6                        6
-#define MAFPA1H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) */
-#define MAFSA2L                         _SFR_MEM8(0x116)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2L {
-        unsigned int mafsa2l : 8;	/* MAC Short Address low Byte for Frame Filter 2 */
-};
-
-#define MAFSA2L_struct _SFR_MEM8_STRUCT(0x116, struct __reg_MAFSA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2L */
-
-#define MAFSA2L0                        0
-#define MAFSA2L1                        1
-#define MAFSA2L2                        2
-#define MAFSA2L3                        3
-#define MAFSA2L4                        4
-#define MAFSA2L5                        5
-#define MAFSA2L6                        6
-#define MAFSA2L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) */
-#define MAFSA2H                         _SFR_MEM8(0x117)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA2H {
-        unsigned int mafsa2h : 8;	/* MAC Short Address high Byte for Frame Filter 2 */
-};
-
-#define MAFSA2H_struct _SFR_MEM8_STRUCT(0x117, struct __reg_MAFSA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA2H */
-
-#define MAFSA2H0                        0
-#define MAFSA2H1                        1
-#define MAFSA2H2                        2
-#define MAFSA2H3                        3
-#define MAFSA2H4                        4
-#define MAFSA2H5                        5
-#define MAFSA2H6                        6
-#define MAFSA2H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) */
-#define MAFPA2L                         _SFR_MEM8(0x118)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2L {
-        unsigned int mafpa2l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 2 */
-};
-
-#define MAFPA2L_struct _SFR_MEM8_STRUCT(0x118, struct __reg_MAFPA2L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2L */
-
-#define MAFPA2L0                        0
-#define MAFPA2L1                        1
-#define MAFPA2L2                        2
-#define MAFPA2L3                        3
-#define MAFPA2L4                        4
-#define MAFPA2L5                        5
-#define MAFPA2L6                        6
-#define MAFPA2L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) */
-#define MAFPA2H                         _SFR_MEM8(0x119)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA2H {
-        unsigned int mafpa2h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 2 */
-};
-
-#define MAFPA2H_struct _SFR_MEM8_STRUCT(0x119, struct __reg_MAFPA2H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA2H */
-
-#define MAFPA2H0                        0
-#define MAFPA2H1                        1
-#define MAFPA2H2                        2
-#define MAFPA2H3                        3
-#define MAFPA2H4                        4
-#define MAFPA2H5                        5
-#define MAFPA2H6                        6
-#define MAFPA2H7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) */
-#define MAFSA3L                         _SFR_MEM8(0x11A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3L {
-        unsigned int mafsa3l : 8;	/* MAC Short Address low Byte for Frame Filter 3 */
-};
-
-#define MAFSA3L_struct _SFR_MEM8_STRUCT(0x11a, struct __reg_MAFSA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3L */
-
-#define MAFSA3L0                        0
-#define MAFSA3L1                        1
-#define MAFSA3L2                        2
-#define MAFSA3L3                        3
-#define MAFSA3L4                        4
-#define MAFSA3L5                        5
-#define MAFSA3L6                        6
-#define MAFSA3L7                        7
-
-/* Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) */
-#define MAFSA3H                         _SFR_MEM8(0x11B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFSA3H {
-        unsigned int mafsa3h : 8;	/* MAC Short Address high Byte for Frame Filter 3 */
-};
-
-#define MAFSA3H_struct _SFR_MEM8_STRUCT(0x11b, struct __reg_MAFSA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFSA3H */
-
-#define MAFSA3H0                        0
-#define MAFSA3H1                        1
-#define MAFSA3H2                        2
-#define MAFSA3H3                        3
-#define MAFSA3H4                        4
-#define MAFSA3H5                        5
-#define MAFSA3H6                        6
-#define MAFSA3H7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) */
-#define MAFPA3L                         _SFR_MEM8(0x11C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3L {
-        unsigned int mafpa3l : 8;	/* MAC Personal Area Network ID low Byte for Frame Filter 3 */
-};
-
-#define MAFPA3L_struct _SFR_MEM8_STRUCT(0x11c, struct __reg_MAFPA3L)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3L */
-
-#define MAFPA3L0                        0
-#define MAFPA3L1                        1
-#define MAFPA3L2                        2
-#define MAFPA3L3                        3
-#define MAFPA3L4                        4
-#define MAFPA3L5                        5
-#define MAFPA3L6                        6
-#define MAFPA3L7                        7
-
-/* Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) */
-#define MAFPA3H                         _SFR_MEM8(0x11D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAFPA3H {
-        unsigned int mafpa3h : 8;	/* MAC Personal Area Network ID high Byte for Frame Filter 3 */
-};
-
-#define MAFPA3H_struct _SFR_MEM8_STRUCT(0x11d, struct __reg_MAFPA3H)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAFPA3H */
-
-#define MAFPA3H0                        0
-#define MAFPA3H1                        1
-#define MAFPA3H2                        2
-#define MAFPA3H3                        3
-#define MAFPA3H4                        4
-#define MAFPA3H5                        5
-#define MAFPA3H6                        6
-#define MAFPA3H7                        7
-
-/* Timer/Counter5 Control Register A */
-#define TCCR5A                          _SFR_MEM8(0x120)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5A {
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int com5c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com5b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com5a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5A */
-
-#define WGM50                           0
-#define WGM51                           1
-#define COM5C0                          2
-#define COM5C1                          3
-#define COM5B0                          4
-#define COM5B1                          5
-#define COM5A0                          6
-#define COM5A1                          7
-
-/* Timer/Counter5 Control Register B */
-#define TCCR5B                          _SFR_MEM8(0x121)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5B {
-        unsigned int cs5 : 3;	/* Clock Select */
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices5 : 1;	/* Input Capture 5 Edge Select */
-        unsigned int icnc5 : 1;	/* Input Capture 5 Noise Canceller */
-};
-
-#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5B */
-
-#define CS50                            0
-#define CS51                            1
-#define CS52                            2
-#define WGM52                           3
-#define WGM53                           4
-#define ICES5                           6
-#define ICNC5                           7
-
-/* Timer/Counter5 Control Register C */
-#define TCCR5C                          _SFR_MEM8(0x122)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5C {
-        unsigned int : 5;
-        unsigned int foc5c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc5b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc5a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5C */
-
-#define FOC5C                           5
-#define FOC5B                           6
-#define FOC5A                           7
-
-/* Timer/Counter5  Bytes */
-#define TCNT5                           _SFR_MEM16(0x124)
-#define TCNT5L                          _SFR_MEM8(0x124)
-#define TCNT5H                          _SFR_MEM8(0x125)
-
-/* Timer/Counter5 Input Capture Register  Bytes */
-#define ICR5                            _SFR_MEM16(0x126)
-#define ICR5L                           _SFR_MEM8(0x126)
-#define ICR5H                           _SFR_MEM8(0x127)
-
-/* Timer/Counter5 Output Compare Register A  Bytes */
-#define OCR5A                           _SFR_MEM16(0x128)
-#define OCR5AL                          _SFR_MEM8(0x128)
-#define OCR5AH                          _SFR_MEM8(0x129)
-
-/* Timer/Counter5 Output Compare Register B  Bytes */
-#define OCR5B                           _SFR_MEM16(0x12A)
-#define OCR5BL                          _SFR_MEM8(0x12A)
-#define OCR5BH                          _SFR_MEM8(0x12B)
-
-/* Timer/Counter5 Output Compare Register C  Bytes */
-#define OCR5C                           _SFR_MEM16(0x12C)
-#define OCR5CL                          _SFR_MEM8(0x12C)
-#define OCR5CH                          _SFR_MEM8(0x12D)
-
-/* Low Leakage Voltage Regulator Control Register */
-#define LLCR                            _SFR_MEM8(0x12F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLCR {
-        unsigned int llencal : 1;	/* Enable Automatic Calibration */
-        unsigned int llshort : 1;	/* Short Lower Calibration Circuit */
-        unsigned int lltco : 1;	/* Temperature Coefficient of Current Source */
-        unsigned int llcal : 1;	/* Calibration Active */
-        unsigned int llcomp : 1;	/* Comparator Output */
-        unsigned int lldone : 1;	/* Calibration Done */
-        unsigned int : 2;
-};
-
-#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLCR */
-
-#define LLENCAL                         0
-#define LLSHORT                         1
-#define LLTCO                           2
-#define LLCAL                           3
-#define LLCOMP                          4
-#define LLDONE                          5
-
-/* Low Leakage Voltage Regulator Data Register (Low-Byte) */
-#define LLDRL                           _SFR_MEM8(0x130)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRL {
-        unsigned int lldrl : 4;	/* Low-Byte Data Register Bits */
-        unsigned int : 4;
-};
-
-#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRL */
-
-#define LLDRL0                          0
-#define LLDRL1                          1
-#define LLDRL2                          2
-#define LLDRL3                          3
-
-/* Low Leakage Voltage Regulator Data Register (High-Byte) */
-#define LLDRH                           _SFR_MEM8(0x131)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRH {
-        unsigned int lldrh : 5;	/* High-Byte Data Register Bits */
-        unsigned int : 3;
-};
-
-#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRH */
-
-#define LLDRH0                          0
-#define LLDRH1                          1
-#define LLDRH2                          2
-#define LLDRH3                          3
-#define LLDRH4                          4
-
-/* Data Retention Configuration Register #3 */
-#define DRTRAM3                         _SFR_MEM8(0x132)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM3 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM3 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #2 */
-#define DRTRAM2                         _SFR_MEM8(0x133)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM2 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM2 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #1 */
-#define DRTRAM1                         _SFR_MEM8(0x134)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM1 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM1 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register #0 */
-#define DRTRAM0                         _SFR_MEM8(0x135)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM0 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM0 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Port Driver Strength Register 0 */
-#define DPDS0                           _SFR_MEM8(0x136)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS0 {
-        unsigned int pbdrv : 2;	/* Driver Strength Port B */
-        unsigned int pddrv : 2;	/* Driver Strength Port D */
-        unsigned int pedrv : 2;	/* Driver Strength Port E */
-        unsigned int pfdrv : 2;	/* Driver Strength Port F */
-};
-
-#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS0 */
-
-#define PBDRV0                          0
-#define PBDRV1                          1
-#define PDDRV0                          2
-#define PDDRV1                          3
-#define PEDRV0                          4
-#define PEDRV1                          5
-#define PFDRV0                          6
-#define PFDRV1                          7
-
-/* Port Driver Strength Register 1 */
-#define DPDS1                           _SFR_MEM8(0x137)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS1 {
-        unsigned int pgdrv : 2;	/* Driver Strength Port G */
-        unsigned int : 6;
-};
-
-#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS1 */
-
-#define PGDRV0                          0
-#define PGDRV1                          1
-
-/* Power Amplifier Ramp up/down Control Register */
-#define PARCR                           _SFR_MEM8(0x138)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PARCR {
-        unsigned int parufi : 1;	/* Power Amplifier Ramp Up Frequency Inversion */
-        unsigned int pardfi : 1;	/* Power Amplifier Ramp Down Frequency Inversion */
-        unsigned int paltu : 3;	/* ext. PA Ramp Up Lead Time */
-        unsigned int paltd : 3;	/* ext. PA Ramp Down Lead Time */
-};
-
-#define PARCR_struct _SFR_MEM8_STRUCT(0x138, struct __reg_PARCR)
-
-/* symbolic names */
-
-#define PALTU_MINUS_3US                 0
-#define PALTU_MINUS_2US                 1
-#define PALTU_MINUS_1US                 2
-#define PALTU_0US                       3
-#define PALTU_1US                       4
-#define PALTU_2US                       5
-#define PALTU_3US                       6
-#define PALTU_4US                       7
-#define PALTD_MINUS_3US                 0
-#define PALTD_MINUS_2US                 1
-#define PALTD_MINUS_1US                 2
-#define PALTD_0US                       3
-#define PALTD_1US                       4
-#define PALTD_2US                       5
-#define PALTD_3US                       6
-#define PALTD_4US                       7
-
-#endif /* __ASSEMBLER__ */
-
-  /* PARCR */
-
-#define PARUFI                          0
-#define PARDFI                          1
-#define PALTU0                          2
-#define PALTU1                          3
-#define PALTU2                          4
-#define PALTD0                          5
-#define PALTD1                          6
-#define PALTD2                          7
-
-/* Transceiver Pin Register */
-#define TRXPR                           _SFR_MEM8(0x139)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRXPR {
-        unsigned int trxrst : 1;	/* Force Transceiver Reset */
-        unsigned int slptr : 1;	/* Multi-purpose Transceiver Control Bit */
-        unsigned int : 6;
-};
-
-#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRXPR */
-
-#define TRXRST                          0
-#define SLPTR                           1
-
-/* AES Control Register */
-#define AES_CTRL                        _SFR_MEM8(0x13C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_CTRL {
-        unsigned int : 2;
-        unsigned int aes_im : 1;	/* AES Interrupt Enable */
-        unsigned int aes_dir : 1;	/* Set AES Operation Direction */
-        unsigned int : 1;
-        unsigned int aes_mode : 1;	/* Set AES Operation Mode */
-        unsigned int : 1;
-        unsigned int aes_request : 1;	/* Request AES Operation. */
-};
-
-#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL)
-
-/* symbolic names */
-
-#define AES_DIR_ENC                     0
-#define AES_DIR_DEC                     1
-#define AES_MODE_ECB                    0
-#define AES_MODE_CBC                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_CTRL */
-
-#define AES_IM                          2
-#define AES_DIR                         3
-#define AES_MODE                        5
-#define AES_REQUEST                     7
-
-/* AES Status Register */
-#define AES_STATUS                      _SFR_MEM8(0x13D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATUS {
-        unsigned int aes_done : 1;	/* AES Operation Finished with Success */
-        unsigned int : 6;
-        unsigned int aes_er : 1;	/* AES Operation Finished with Error */
-};
-
-#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATUS */
-
-#define AES_DONE                        0
-#define AES_ER                          7
-
-/* AES Plain and Cipher Text Buffer Register */
-#define AES_STATE                       _SFR_MEM8(0x13E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATE {
-        unsigned int aes_state : 8;	/* AES Plain and Cipher Text Buffer */
-};
-
-#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATE */
-
-#define AES_STATE0                      0
-#define AES_STATE1                      1
-#define AES_STATE2                      2
-#define AES_STATE3                      3
-#define AES_STATE4                      4
-#define AES_STATE5                      5
-#define AES_STATE6                      6
-#define AES_STATE7                      7
-
-/* AES Encryption and Decryption Key Buffer Register */
-#define AES_KEY                         _SFR_MEM8(0x13F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_KEY {
-        unsigned int aes_key : 8;	/* AES Encryption/Decryption Key Buffer */
-};
-
-#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_KEY */
-
-#define AES_KEY0                        0
-#define AES_KEY1                        1
-#define AES_KEY2                        2
-#define AES_KEY3                        3
-#define AES_KEY4                        4
-#define AES_KEY5                        5
-#define AES_KEY6                        6
-#define AES_KEY7                        7
-
-/* Transceiver Status Register */
-#define TRX_STATUS                      _SFR_MEM8(0x141)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATUS {
-        unsigned int trx_status : 5;	/* Transceiver Main Status */
-        unsigned int tst_status : 1;	/* Test mode status */
-        unsigned int cca_status : 1;	/* CCA Status Result */
-        unsigned int cca_done : 1;	/* CCA Algorithm Status */
-};
-
-#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS)
-
-/* symbolic names */
-
-#define BUSY_RX                         1
-#define BUSY_TX                         2
-#define RX_ON                           6
-#define TRX_OFF                         8
-#define PLL_ON                          9
-#define SLEEP                           15
-#define BUSY_RX_AACK                    17
-#define BUSY_TX_ARET                    18
-#define RX_AACK_ON                      22
-#define TX_ARET_ON                      25
-#define STATE_TRANSITION_IN_PROGRESS    31
-#define TST_DISABLED                    0
-#define TST_ENABLED                     1
-#define CCA_BUSY                        0
-#define CCA_IDLE                        1
-#define CCA_NOT_FIN                     0
-#define CCA_FIN                         1
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATUS */
-
-#define TRX_STATUS0                     0
-#define TRX_STATUS1                     1
-#define TRX_STATUS2                     2
-#define TRX_STATUS3                     3
-#define TRX_STATUS4                     4
-#define TST_STATUS                      5
-#define CCA_STATUS                      6
-#define CCA_DONE                        7
-
-/* Transceiver State Control Register */
-#define TRX_STATE                       _SFR_MEM8(0x142)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATE {
-        unsigned int trx_cmd : 5;	/* State Control Command */
-        unsigned int trac_status : 3;	/* Transaction Status */
-};
-
-#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE)
-
-/* symbolic names */
-
-#define CMD_NOP                         0
-#define CMD_TX_START                    2
-#define CMD_FORCE_TRX_OFF               3
-#define CMD_FORCE_PLL_ON                4
-#define CMD_RX_ON                       6
-#define CMD_TRX_OFF                     8
-#define CMD_PLL_ON                      9
-#define CMD_RX_AACK_ON                  22
-#define CMD_TX_ARET_ON                  25
-#define TRAC_SUCCESS                    0
-#define TRAC_SUCCESS_DATA_PENDING       1
-#define TRAC_SUCCESS_WAIT_FOR_ACK       2
-#define TRAC_CHANNEL_ACCESS_FAILURE     3
-#define TRAC_NO_ACK                     5
-#define TRAC_INVALID                    7
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATE */
-
-#define TRX_CMD0                        0
-#define TRX_CMD1                        1
-#define TRX_CMD2                        2
-#define TRX_CMD3                        3
-#define TRX_CMD4                        4
-#define TRAC_STATUS0                    5
-#define TRAC_STATUS1                    6
-#define TRAC_STATUS2                    7
-
-/* Tranceiver Control Register 0 */
-#define TRX_CTRL_0                      _SFR_MEM8(0x143)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_0 {
-        unsigned int : 4;
-        unsigned int pmu_if_inv : 1;	/* PMU IF Inverse */
-        unsigned int pmu_start : 1;	/* Start of Phase Measurement Unit */
-        unsigned int pmu_en : 1;	/* Enable Phase Measurement Unit */
-        unsigned int res7 : 1;	/* Reserved */
-};
-
-#define TRX_CTRL_0_struct _SFR_MEM8_STRUCT(0x143, struct __reg_TRX_CTRL_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_0 */
-
-#define PMU_IF_INV                      4
-#define PMU_START                       5
-#define PMU_EN                          6
-
-/* Transceiver Control Register 1 */
-#define TRX_CTRL_1                      _SFR_MEM8(0x144)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_1 {
-        unsigned int : 4;
-        unsigned int pll_tx_flt : 1;	/* Enable PLL TX Filter */
-        unsigned int tx_auto_crc_on : 1;	/* Enable Automatic CRC Calculation */
-        unsigned int irq_2_ext_en : 1;	/* Connect Frame Start IRQ to TC1 */
-        unsigned int pa_ext_en : 1;	/* External PA support enable */
-};
-
-#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_1 */
-
-#define PLL_TX_FLT                      4
-#define TX_AUTO_CRC_ON                  5
-#define IRQ_2_EXT_EN                    6
-#define PA_EXT_EN                       7
-
-/* Transceiver Transmit Power Control Register */
-#define PHY_TX_PWR                      _SFR_MEM8(0x145)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_TX_PWR {
-        unsigned int tx_pwr : 4;	/* Transmit Power Setting */
-        unsigned int : 4;
-};
-
-#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_TX_PWR */
-
-#define TX_PWR0                         0
-#define TX_PWR1                         1
-#define TX_PWR2                         2
-#define TX_PWR3                         3
-
-/* Receiver Signal Strength Indicator Register */
-#define PHY_RSSI                        _SFR_MEM8(0x146)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_RSSI {
-        unsigned int rssi : 5;	/* Receiver Signal Strength Indicator */
-        unsigned int rnd_value : 2;	/* Random Value */
-        unsigned int rx_crc_valid : 1;	/* Received Frame CRC Status */
-};
-
-#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI)
-
-/* symbolic names */
-
-#define RSSI_MIN                        0
-#define RSSI_MIN_PLUS_3dB               1
-#define RSSI_MAX                        28
-#define CRC_INVALID                     0
-#define CRC_VALID                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_RSSI */
-
-#define RSSI0                           0
-#define RSSI1                           1
-#define RSSI2                           2
-#define RSSI3                           3
-#define RSSI4                           4
-#define RND_VALUE0                      5
-#define RND_VALUE1                      6
-#define RX_CRC_VALID                    7
-
-/* Transceiver Energy Detection Level Register */
-#define PHY_ED_LEVEL                    _SFR_MEM8(0x147)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_ED_LEVEL {
-        unsigned int ed_level : 8;	/* Energy Detection Level */
-};
-
-#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL)
-
-/* symbolic names */
-
-#define ED_MIN                          0
-#define ED_MIN_PLUS_1dB                 1
-#define ED_MAX                          83
-#define ED_RESET                        255
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_ED_LEVEL */
-
-#define ED_LEVEL0                       0
-#define ED_LEVEL1                       1
-#define ED_LEVEL2                       2
-#define ED_LEVEL3                       3
-#define ED_LEVEL4                       4
-#define ED_LEVEL5                       5
-#define ED_LEVEL6                       6
-#define ED_LEVEL7                       7
-
-/* Transceiver Clear Channel Assessment (CCA) Control Register */
-#define PHY_CC_CCA                      _SFR_MEM8(0x148)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_CC_CCA {
-        unsigned int channel : 5;	/* RX/TX Channel Selection */
-        unsigned int cca_mode : 2;	/* Select CCA Measurement Mode */
-        unsigned int cca_request : 1;	/* Manual CCA Measurement Request */
-};
-
-#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA)
-
-/* symbolic names */
-
-#define F_2405MHZ                       11
-#define F_2410MHZ                       12
-#define F_2415MHZ                       13
-#define F_2420MHZ                       14
-#define F_2425MHZ                       15
-#define F_2430MHZ                       16
-#define F_2435MHZ                       17
-#define F_2440MHZ                       18
-#define F_2445MHZ                       19
-#define F_2450MHZ                       20
-#define F_2455MHZ                       21
-#define F_2460MHZ                       22
-#define F_2465MHZ                       23
-#define F_2470MHZ                       24
-#define F_2475MHZ                       25
-#define F_2480MHZ                       26
-#define CCA_CS_OR_ED                    0
-#define CCA_ED                          1
-#define CCA_CS                          2
-#define CCA_CS_AND_ED                   3
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_CC_CCA */
-
-#define CHANNEL0                        0
-#define CHANNEL1                        1
-#define CHANNEL2                        2
-#define CHANNEL3                        3
-#define CHANNEL4                        4
-#define CCA_MODE0                       5
-#define CCA_MODE1                       6
-#define CCA_REQUEST                     7
-
-/* Transceiver CCA Threshold Setting Register */
-#define CCA_THRES                       _SFR_MEM8(0x149)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CCA_THRES {
-        unsigned int cca_ed_thres : 4;	/* ED Threshold Level for CCA Measurement */
-        unsigned int cca_cs_thres : 4;	/* CS Threshold Level for CCA Measurement */
-};
-
-#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CCA_THRES */
-
-#define CCA_ED_THRES0                   0
-#define CCA_ED_THRES1                   1
-#define CCA_ED_THRES2                   2
-#define CCA_ED_THRES3                   3
-#define CCA_CS_THRES0                   4
-#define CCA_CS_THRES1                   5
-#define CCA_CS_THRES2                   6
-#define CCA_CS_THRES3                   7
-
-/* Transceiver Receive Control Register */
-#define RX_CTRL                         _SFR_MEM8(0x14A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_CTRL {
-        unsigned int pdt_thres : 4;	/* Receiver Sensitivity Control */
-        unsigned int : 4;
-};
-
-#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL)
-
-/* symbolic names */
-
-#define PDT_THRES_ANT_DIV_OFF           7
-#define PDT_THRES_ANT_DIV_ON            3
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_CTRL */
-
-#define PDT_THRES0                      0
-#define PDT_THRES1                      1
-#define PDT_THRES2                      2
-#define PDT_THRES3                      3
-
-/* Start of Frame Delimiter Value Register */
-#define SFD_VALUE                       _SFR_MEM8(0x14B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SFD_VALUE {
-        unsigned int sfd_value : 8;	/* Start of Frame Delimiter Value */
-};
-
-#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE)
-
-/* symbolic names */
-
-#define IEEE_SFD                        167
-
-#endif /* __ASSEMBLER__ */
-
-  /* SFD_VALUE */
-
-#define SFD_VALUE0                      0
-#define SFD_VALUE1                      1
-#define SFD_VALUE2                      2
-#define SFD_VALUE3                      3
-#define SFD_VALUE4                      4
-#define SFD_VALUE5                      5
-#define SFD_VALUE6                      6
-#define SFD_VALUE7                      7
-
-/* Transceiver Control Register 2 */
-#define TRX_CTRL_2                      _SFR_MEM8(0x14C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_2 {
-        unsigned int oqpsk_data_rate : 2;	/* Data Rate Selection */
-        unsigned int : 5;
-        unsigned int rx_safe_mode : 1;	/* RX Safe Mode */
-};
-
-#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2)
-
-/* symbolic names */
-
-#define RATE_250KB                      0
-#define RATE_500KB                      1
-#define RATE_1000KB                     2
-#define RATE_2000KB                     3
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_2 */
-
-#define OQPSK_DATA_RATE0                0
-#define OQPSK_DATA_RATE1                1
-#define RX_SAFE_MODE                    7
-
-/* Antenna Diversity Control Register */
-#define ANT_DIV                         _SFR_MEM8(0x14D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ANT_DIV {
-        unsigned int ant_ctrl : 2;	/* Static Antenna Diversity Switch Control */
-        unsigned int ant_ext_sw_en : 1;	/* Enable External Antenna Switch Control */
-        unsigned int ant_div_en : 1;	/* Enable Antenna Diversity */
-        unsigned int : 3;
-        unsigned int ant_sel : 1;	/* Antenna Diversity Antenna Status */
-};
-
-#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV)
-
-/* symbolic names */
-
-#define ANT_1                           1
-#define ANT_0                           2
-#define ANT_RESET                       3
-#define ANT_DIV_EXT_SW_DIS              0
-#define ANT_DIV_EXT_SW_EN               1
-#define ANTENNA_0                       0
-#define ANTENNA_1                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* ANT_DIV */
-
-#define ANT_CTRL0                       0
-#define ANT_CTRL1                       1
-#define ANT_EXT_SW_EN                   2
-#define ANT_DIV_EN                      3
-#define ANT_SEL                         7
-
-/* Transceiver Interrupt Enable Register */
-#define IRQ_MASK                        _SFR_MEM8(0x14E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK {
-        unsigned int pll_lock_en : 1;	/* PLL Lock Interrupt Enable */
-        unsigned int pll_unlock_en : 1;	/* PLL Unlock Interrupt Enable */
-        unsigned int rx_start_en : 1;	/* RX_START Interrupt Enable */
-        unsigned int rx_end_en : 1;	/* RX_END Interrupt Enable */
-        unsigned int cca_ed_done_en : 1;	/* End of ED Measurement Interrupt Enable */
-        unsigned int ami_en : 1;	/* Address Match Interrupt Enable */
-        unsigned int tx_end_en : 1;	/* TX_END Interrupt Enable */
-        unsigned int awake_en : 1;	/* Awake Interrupt Enable */
-};
-
-#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK */
-
-#define PLL_LOCK_EN                     0
-#define PLL_UNLOCK_EN                   1
-#define RX_START_EN                     2
-#define RX_END_EN                       3
-#define CCA_ED_DONE_EN                  4
-#define AMI_EN                          5
-#define TX_END_EN                       6
-#define AWAKE_EN                        7
-
-/* Transceiver Interrupt Status Register */
-#define IRQ_STATUS                      _SFR_MEM8(0x14F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS {
-        unsigned int pll_lock : 1;	/* PLL Lock Interrupt Status */
-        unsigned int pll_unlock : 1;	/* PLL Unlock Interrupt Status */
-        unsigned int rx_start : 1;	/* RX_START Interrupt Status */
-        unsigned int rx_end : 1;	/* RX_END Interrupt Status */
-        unsigned int cca_ed_done : 1;	/* End of ED Measurement Interrupt Status */
-        unsigned int ami : 1;	/* Address Match Interrupt Status */
-        unsigned int tx_end : 1;	/* TX_END Interrupt Status */
-        unsigned int awake : 1;	/* Awake Interrupt Status */
-};
-
-#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS */
-
-#define PLL_LOCK                        0
-#define PLL_UNLOCK                      1
-#define RX_START                        2
-#define RX_END                          3
-#define CCA_ED_DONE                     4
-#define AMI                             5
-#define TX_END                          6
-#define AWAKE                           7
-
-/* Voltage Regulator Control and Status Register */
-#define VREG_CTRL                       _SFR_MEM8(0x150)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VREG_CTRL {
-        unsigned int : 2;
-        unsigned int dvdd_ok : 1;	/* DVDD Supply Voltage Valid */
-        unsigned int dvreg_ext : 1;	/* Use External DVDD Regulator */
-        unsigned int : 2;
-        unsigned int avdd_ok : 1;	/* AVDD Supply Voltage Valid */
-        unsigned int avreg_ext : 1;	/* Use External AVDD Regulator */
-};
-
-#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL)
-
-/* symbolic names */
-
-#define DVDD_INT                        0
-#define DVDD_EXT                        1
-#define AVDD_INT                        0
-#define AVDD_EXT                        1
-
-#endif /* __ASSEMBLER__ */
-
-  /* VREG_CTRL */
-
-#define DVDD_OK                         2
-#define DVREG_EXT                       3
-#define AVDD_OK                         6
-#define AVREG_EXT                       7
-
-/* Battery Monitor Control and Status Register */
-#define BATMON                          _SFR_MEM8(0x151)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BATMON {
-        unsigned int batmon_vth : 4;	/* Battery Monitor Threshold Voltage */
-        unsigned int batmon_hr : 1;	/* Battery Monitor Voltage Range */
-        unsigned int batmon_ok : 1;	/* Battery Monitor Status */
-        unsigned int bat_low_en : 1;	/* Battery Monitor Interrupt Enable */
-        unsigned int bat_low : 1;	/* Battery Monitor Interrupt Status */
-};
-
-#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON)
-
-/* symbolic names */
-
-#define BATMON_HR_DIS                   0
-#define BATMON_HR_EN                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* BATMON */
-
-#define BATMON_VTH0                     0
-#define BATMON_VTH1                     1
-#define BATMON_VTH2                     2
-#define BATMON_VTH3                     3
-#define BATMON_HR                       4
-#define BATMON_OK                       5
-#define BAT_LOW_EN                      6
-#define BAT_LOW                         7
-
-/* Crystal Oscillator Control Register */
-#define XOSC_CTRL                       _SFR_MEM8(0x152)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XOSC_CTRL {
-        unsigned int xtal_trim : 4;	/* Crystal Oscillator Load Capacitance Trimming */
-        unsigned int xtal_mode : 4;	/* Crystal Oscillator Operating Mode */
-};
-
-#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL)
-
-/* symbolic names */
-
-#define XTAL_TRIM_MIN                   0
-#define XTAL_TRIM_MAX                   15
-
-#endif /* __ASSEMBLER__ */
-
-  /* XOSC_CTRL */
-
-#define XTAL_TRIM0                      0
-#define XTAL_TRIM1                      1
-#define XTAL_TRIM2                      2
-#define XTAL_TRIM3                      3
-#define XTAL_MODE0                      4
-#define XTAL_MODE1                      5
-#define XTAL_MODE2                      6
-#define XTAL_MODE3                      7
-
-/* Channel Control Register 0 */
-#define CC_CTRL_0                       _SFR_MEM8(0x153)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_0 {
-        unsigned int cc_number : 8;	/* Channel Number */
-};
-
-#define CC_CTRL_0_struct _SFR_MEM8_STRUCT(0x153, struct __reg_CC_CTRL_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_0 */
-
-#define CC_NUMBER0                      0
-#define CC_NUMBER1                      1
-#define CC_NUMBER2                      2
-#define CC_NUMBER3                      3
-#define CC_NUMBER4                      4
-#define CC_NUMBER5                      5
-#define CC_NUMBER6                      6
-#define CC_NUMBER7                      7
-
-/* Channel Control Register 1 */
-#define CC_CTRL_1                       _SFR_MEM8(0x154)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CC_CTRL_1 {
-        unsigned int cc_band : 4;	/* Channel Band */
-        unsigned int : 4;
-};
-
-#define CC_CTRL_1_struct _SFR_MEM8_STRUCT(0x154, struct __reg_CC_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CC_CTRL_1 */
-
-#define CC_BAND0                        0
-#define CC_BAND1                        1
-#define CC_BAND2                        2
-#define CC_BAND3                        3
-
-/* Transceiver Receiver Sensitivity Control Register */
-#define RX_SYN                          _SFR_MEM8(0x155)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_SYN {
-        unsigned int rx_pdt_level : 4;	/* Reduce Receiver Sensitivity */
-        unsigned int : 2;
-        unsigned int rx_override : 1;	/* Receiver Override Function */
-        unsigned int rx_pdt_dis : 1;	/* Prevent Frame Reception */
-};
-
-#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN)
-
-/* symbolic names */
-
-#define RX_PDT_LEVEL_MIN                0
-#define RX_PDT_LEVEL_MAX                15
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_SYN */
-
-#define RX_PDT_LEVEL0                   0
-#define RX_PDT_LEVEL1                   1
-#define RX_PDT_LEVEL2                   2
-#define RX_PDT_LEVEL3                   3
-#define RX_OVERRIDE                     6
-#define RX_PDT_DIS                      7
-
-/* Transceiver Reduced Power Consumption Control */
-#define TRX_RPC                         _SFR_MEM8(0x156)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_RPC {
-        unsigned int : 1;
-        unsigned int ipan_rpc_en : 1;	/* Smart Receiving Mode IPAN Handling Enable */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int pll_rpc_en : 1;	/* PLL Smart Receiving Mode Enable */
-        unsigned int pdt_rpc_en : 1;	/* Smart Receiving Mode Reduced Sensitivity Enable */
-        unsigned int rx_rpc_en : 1;	/* Receiver Smart Receiving Mode Enable */
-        unsigned int rx_rpc_ctrl : 2;	/* Smart Receiving Mode Timing */
-};
-
-#define TRX_RPC_struct _SFR_MEM8_STRUCT(0x156, struct __reg_TRX_RPC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_RPC */
-
-#define IPAN_RPC_EN                     1
-#define PLL_RPC_EN                      3
-#define PDT_RPC_EN                      4
-#define RX_RPC_EN                       5
-#define RX_RPC_CTRL0                    6
-#define RX_RPC_CTRL1                    7
-
-/* Transceiver Acknowledgment Frame Control Register 1 */
-#define XAH_CTRL_1                      _SFR_MEM8(0x157)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_1 {
-        unsigned int : 1;
-        unsigned int aack_prom_mode : 1;	/* Enable Promiscuous Mode */
-        unsigned int aack_ack_time : 1;	/* Reduce Acknowledgment Time */
-        unsigned int : 1;
-        unsigned int aack_upld_res_ft : 1;	/* Process Reserved Frames */
-        unsigned int aack_fltr_res_ft : 1;	/* Filter Reserved Frames */
-        unsigned int : 2;
-};
-
-#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1)
-
-/* symbolic names */
-
-#define AACK_ACK_TIME_12_SYM            0
-#define AACK_ACK_TIME_2_SYM             1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_1 */
-
-#define AACK_PROM_MODE                  1
-#define AACK_ACK_TIME                   2
-#define AACK_UPLD_RES_FT                4
-#define AACK_FLTR_RES_FT                5
-
-/* Transceiver Filter Tuning Control Register */
-#define FTN_CTRL                        _SFR_MEM8(0x158)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_FTN_CTRL {
-        unsigned int : 7;
-        unsigned int ftn_start : 1;	/* Start Calibration Loop of Filter Tuning Network */
-};
-
-#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* FTN_CTRL */
-
-#define FTN_START                       7
-
-/* Transceiver Center Frequency Calibration Control Register */
-#define PLL_CF                          _SFR_MEM8(0x15A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_CF {
-        unsigned int : 7;
-        unsigned int pll_cf_start : 1;	/* Start Center Frequency Calibration */
-};
-
-#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_CF */
-
-#define PLL_CF_START                    7
-
-/* Transceiver Delay Cell Calibration Control Register */
-#define PLL_DCU                         _SFR_MEM8(0x15B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_DCU {
-        unsigned int : 7;
-        unsigned int pll_dcu_start : 1;	/* Start Delay Cell Calibration */
-};
-
-#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_DCU */
-
-#define PLL_DCU_START                   7
-
-/* Device Identification Register (Part Number) */
-#define PART_NUM                        _SFR_MEM8(0x15C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PART_NUM {
-        unsigned int part_num : 8;	/* Part Number */
-};
-
-#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM)
-
-/* symbolic names */
-
-#define P_RFR2                          148
-
-#endif /* __ASSEMBLER__ */
-
-  /* PART_NUM */
-
-#define PART_NUM0                       0
-#define PART_NUM1                       1
-#define PART_NUM2                       2
-#define PART_NUM3                       3
-#define PART_NUM4                       4
-#define PART_NUM5                       5
-#define PART_NUM6                       6
-#define PART_NUM7                       7
-
-/* Device Identification Register (Version Number) */
-#define VERSION_NUM                     _SFR_MEM8(0x15D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VERSION_NUM {
-        unsigned int version_num : 8;	/* Version Number */
-};
-
-#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM)
-
-/* symbolic names */
-
-#define REV_A                           12
-#define REV_B                           1
-#define REV_C                           3
-#define REV_D                           4
-
-#endif /* __ASSEMBLER__ */
-
-  /* VERSION_NUM */
-
-#define VERSION_NUM0                    0
-#define VERSION_NUM1                    1
-#define VERSION_NUM2                    2
-#define VERSION_NUM3                    3
-#define VERSION_NUM4                    4
-#define VERSION_NUM5                    5
-#define VERSION_NUM6                    6
-#define VERSION_NUM7                    7
-
-/* Device Identification Register (Manufacture ID Low Byte) */
-#define MAN_ID_0                        _SFR_MEM8(0x15E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_0 {
-        unsigned int man_id_00 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_01 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_02 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_03 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_04 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_05 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_06 : 1;	/* Manufacturer ID (Low Byte) */
-        unsigned int man_id_07 : 1;	/* Manufacturer ID (Low Byte) */
-};
-
-#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_0                    31
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_0 */
-
-#define MAN_ID_00                       0
-#define MAN_ID_01                       1
-#define MAN_ID_02                       2
-#define MAN_ID_03                       3
-#define MAN_ID_04                       4
-#define MAN_ID_05                       5
-#define MAN_ID_06                       6
-#define MAN_ID_07                       7
-
-/* Device Identification Register (Manufacture ID High Byte) */
-#define MAN_ID_1                        _SFR_MEM8(0x15F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_1 {
-        unsigned int man_id_ : 8;	/* Manufacturer ID (High Byte) */
-};
-
-#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_1                    0
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_1 */
-
-#define MAN_ID_10                       0
-#define MAN_ID_11                       1
-#define MAN_ID_12                       2
-#define MAN_ID_13                       3
-#define MAN_ID_14                       4
-#define MAN_ID_15                       5
-#define MAN_ID_16                       6
-#define MAN_ID_17                       7
-
-/* Transceiver MAC Short Address Register (Low Byte) */
-#define SHORT_ADDR_0                    _SFR_MEM8(0x160)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_0 {
-        unsigned int short_addr_00 : 1;	/* MAC Short Address */
-        unsigned int short_addr_01 : 1;	/* MAC Short Address */
-        unsigned int short_addr_02 : 1;	/* MAC Short Address */
-        unsigned int short_addr_03 : 1;	/* MAC Short Address */
-        unsigned int short_addr_04 : 1;	/* MAC Short Address */
-        unsigned int short_addr_05 : 1;	/* MAC Short Address */
-        unsigned int short_addr_06 : 1;	/* MAC Short Address */
-        unsigned int short_addr_07 : 1;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_0 */
-
-#define SHORT_ADDR_00                   0
-#define SHORT_ADDR_01                   1
-#define SHORT_ADDR_02                   2
-#define SHORT_ADDR_03                   3
-#define SHORT_ADDR_04                   4
-#define SHORT_ADDR_05                   5
-#define SHORT_ADDR_06                   6
-#define SHORT_ADDR_07                   7
-
-/* Transceiver MAC Short Address Register (High Byte) */
-#define SHORT_ADDR_1                    _SFR_MEM8(0x161)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_1 {
-        unsigned int short_addr_ : 8;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_1 */
-
-#define SHORT_ADDR_10                   0
-#define SHORT_ADDR_11                   1
-#define SHORT_ADDR_12                   2
-#define SHORT_ADDR_13                   3
-#define SHORT_ADDR_14                   4
-#define SHORT_ADDR_15                   5
-#define SHORT_ADDR_16                   6
-#define SHORT_ADDR_17                   7
-
-/* Transceiver Personal Area Network ID Register (Low Byte) */
-#define PAN_ID_0                        _SFR_MEM8(0x162)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_0 {
-        unsigned int pan_id_00 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_01 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_02 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_03 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_04 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_05 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_06 : 1;	/* MAC Personal Area Network ID */
-        unsigned int pan_id_07 : 1;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_0 */
-
-#define PAN_ID_00                       0
-#define PAN_ID_01                       1
-#define PAN_ID_02                       2
-#define PAN_ID_03                       3
-#define PAN_ID_04                       4
-#define PAN_ID_05                       5
-#define PAN_ID_06                       6
-#define PAN_ID_07                       7
-
-/* Transceiver Personal Area Network ID Register (High Byte) */
-#define PAN_ID_1                        _SFR_MEM8(0x163)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_1 {
-        unsigned int pan_id_ : 8;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_1 */
-
-#define PAN_ID_10                       0
-#define PAN_ID_11                       1
-#define PAN_ID_12                       2
-#define PAN_ID_13                       3
-#define PAN_ID_14                       4
-#define PAN_ID_15                       5
-#define PAN_ID_16                       6
-#define PAN_ID_17                       7
-
-/* Transceiver MAC IEEE Address Register 0 */
-#define IEEE_ADDR_0                     _SFR_MEM8(0x164)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_0 {
-        unsigned int ieee_addr_00 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_01 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_02 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_03 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_04 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_05 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_06 : 1;	/* MAC IEEE Address */
-        unsigned int ieee_addr_07 : 1;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_0 */
-
-#define IEEE_ADDR_00                    0
-#define IEEE_ADDR_01                    1
-#define IEEE_ADDR_02                    2
-#define IEEE_ADDR_03                    3
-#define IEEE_ADDR_04                    4
-#define IEEE_ADDR_05                    5
-#define IEEE_ADDR_06                    6
-#define IEEE_ADDR_07                    7
-
-/* Transceiver MAC IEEE Address Register 1 */
-#define IEEE_ADDR_1                     _SFR_MEM8(0x165)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_1 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_1 */
-
-#define IEEE_ADDR_10                    0
-#define IEEE_ADDR_11                    1
-#define IEEE_ADDR_12                    2
-#define IEEE_ADDR_13                    3
-#define IEEE_ADDR_14                    4
-#define IEEE_ADDR_15                    5
-#define IEEE_ADDR_16                    6
-#define IEEE_ADDR_17                    7
-
-/* Transceiver MAC IEEE Address Register 2 */
-#define IEEE_ADDR_2                     _SFR_MEM8(0x166)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_2 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_2 */
-
-#define IEEE_ADDR_20                    0
-#define IEEE_ADDR_21                    1
-#define IEEE_ADDR_22                    2
-#define IEEE_ADDR_23                    3
-#define IEEE_ADDR_24                    4
-#define IEEE_ADDR_25                    5
-#define IEEE_ADDR_26                    6
-#define IEEE_ADDR_27                    7
-
-/* Transceiver MAC IEEE Address Register 3 */
-#define IEEE_ADDR_3                     _SFR_MEM8(0x167)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_3 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_3 */
-
-#define IEEE_ADDR_30                    0
-#define IEEE_ADDR_31                    1
-#define IEEE_ADDR_32                    2
-#define IEEE_ADDR_33                    3
-#define IEEE_ADDR_34                    4
-#define IEEE_ADDR_35                    5
-#define IEEE_ADDR_36                    6
-#define IEEE_ADDR_37                    7
-
-/* Transceiver MAC IEEE Address Register 4 */
-#define IEEE_ADDR_4                     _SFR_MEM8(0x168)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_4 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_4 */
-
-#define IEEE_ADDR_40                    0
-#define IEEE_ADDR_41                    1
-#define IEEE_ADDR_42                    2
-#define IEEE_ADDR_43                    3
-#define IEEE_ADDR_44                    4
-#define IEEE_ADDR_45                    5
-#define IEEE_ADDR_46                    6
-#define IEEE_ADDR_47                    7
-
-/* Transceiver MAC IEEE Address Register 5 */
-#define IEEE_ADDR_5                     _SFR_MEM8(0x169)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_5 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_5 */
-
-#define IEEE_ADDR_50                    0
-#define IEEE_ADDR_51                    1
-#define IEEE_ADDR_52                    2
-#define IEEE_ADDR_53                    3
-#define IEEE_ADDR_54                    4
-#define IEEE_ADDR_55                    5
-#define IEEE_ADDR_56                    6
-#define IEEE_ADDR_57                    7
-
-/* Transceiver MAC IEEE Address Register 6 */
-#define IEEE_ADDR_6                     _SFR_MEM8(0x16A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_6 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_6 */
-
-#define IEEE_ADDR_60                    0
-#define IEEE_ADDR_61                    1
-#define IEEE_ADDR_62                    2
-#define IEEE_ADDR_63                    3
-#define IEEE_ADDR_64                    4
-#define IEEE_ADDR_65                    5
-#define IEEE_ADDR_66                    6
-#define IEEE_ADDR_67                    7
-
-/* Transceiver MAC IEEE Address Register 7 */
-#define IEEE_ADDR_7                     _SFR_MEM8(0x16B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_7 {
-        unsigned int ieee_addr_ : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_7 */
-
-#define IEEE_ADDR_70                    0
-#define IEEE_ADDR_71                    1
-#define IEEE_ADDR_72                    2
-#define IEEE_ADDR_73                    3
-#define IEEE_ADDR_74                    4
-#define IEEE_ADDR_75                    5
-#define IEEE_ADDR_76                    6
-#define IEEE_ADDR_77                    7
-
-/* Transceiver Extended Operating Mode Control Register */
-#define XAH_CTRL_0                      _SFR_MEM8(0x16C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_0 {
-        unsigned int slotted_operation : 1;	/* Set Slotted Acknowledgment */
-        unsigned int max_csma_retries : 3;	/* Maximum Number of CSMA-CA Procedure Repetition Attempts */
-        unsigned int max_frame_retries : 4;	/* Maximum Number of Frame Re-transmission Attempts */
-};
-
-#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0)
-
-/* symbolic names */
-
-#define SLOTTED_OP_DIS                  0
-#define SLOTTED_OP_EN                   1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_0 */
-
-#define SLOTTED_OPERATION               0
-#define MAX_CSMA_RETRIES0               1
-#define MAX_CSMA_RETRIES1               2
-#define MAX_CSMA_RETRIES2               3
-#define MAX_FRAME_RETRIES0              4
-#define MAX_FRAME_RETRIES1              5
-#define MAX_FRAME_RETRIES2              6
-#define MAX_FRAME_RETRIES3              7
-
-/* Transceiver CSMA-CA Random Number Generator Seed Register */
-#define CSMA_SEED_0                     _SFR_MEM8(0x16D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_0 {
-        unsigned int csma_seed_00 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_01 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_02 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_03 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_04 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_05 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_06 : 1;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int csma_seed_07 : 1;	/* Seed Value for CSMA Random Number Generator */
-};
-
-#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_0 */
-
-#define CSMA_SEED_00                    0
-#define CSMA_SEED_01                    1
-#define CSMA_SEED_02                    2
-#define CSMA_SEED_03                    3
-#define CSMA_SEED_04                    4
-#define CSMA_SEED_05                    5
-#define CSMA_SEED_06                    6
-#define CSMA_SEED_07                    7
-
-/* Transceiver Acknowledgment Frame Control Register 2 */
-#define CSMA_SEED_1                     _SFR_MEM8(0x16E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_1 {
-        unsigned int csma_seed_1 : 3;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int aack_i_am_coord : 1;	/* Set Personal Area Network Coordinator */
-        unsigned int aack_dis_ack : 1;	/* Disable Acknowledgment Frame Transmission */
-        unsigned int aack_set_pd : 1;	/* Set Frame Pending Sub-field */
-        unsigned int aack_fvn_mode : 2;	/* Acknowledgment Frame Filter Mode */
-};
-
-#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_1 */
-
-#define CSMA_SEED_10                    0
-#define CSMA_SEED_11                    1
-#define CSMA_SEED_12                    2
-#define AACK_I_AM_COORD                 3
-#define AACK_DIS_ACK                    4
-#define AACK_SET_PD                     5
-#define AACK_FVN_MODE0                  6
-#define AACK_FVN_MODE1                  7
-
-/* Transceiver CSMA-CA Back-off Exponent Control Register */
-#define CSMA_BE                         _SFR_MEM8(0x16F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_BE {
-        unsigned int min_be : 4;	/* Minimum Back-off Exponent */
-        unsigned int max_be : 4;	/* Maximum Back-off Exponent */
-};
-
-#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_BE */
-
-#define MIN_BE0                         0
-#define MIN_BE1                         1
-#define MIN_BE2                         2
-#define MIN_BE3                         3
-#define MAX_BE0                         4
-#define MAX_BE1                         5
-#define MAX_BE2                         6
-#define MAX_BE3                         7
-
-/* Transceiver Digital Test Control Register */
-#define TST_CTRL_DIGI                   _SFR_MEM8(0x176)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_CTRL_DIGI {
-        unsigned int tst_ctrl_dig : 4;	/* Digital Test Controller Register */
-        unsigned int : 4;
-};
-
-#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_CTRL_DIGI */
-
-#define TST_CTRL_DIG0                   0
-#define TST_CTRL_DIG1                   1
-#define TST_CTRL_DIG2                   2
-#define TST_CTRL_DIG3                   3
-
-/* Transceiver Received Frame Length Register */
-#define TST_RX_LENGTH                   _SFR_MEM8(0x17B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_RX_LENGTH {
-        unsigned int rx_length : 8;	/* Received Frame Length */
-};
-
-#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_RX_LENGTH */
-
-#define RX_LENGTH0                      0
-#define RX_LENGTH1                      1
-#define RX_LENGTH2                      2
-#define RX_LENGTH3                      3
-#define RX_LENGTH4                      4
-#define RX_LENGTH5                      5
-#define RX_LENGTH6                      6
-#define RX_LENGTH7                      7
-
-/* Transceiver Automatic Gain Control and Test Register */
-#define TST_AGC                         _SFR_MEM8(0x17C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_AGC {
-        unsigned int gc : 2;	/* Receiver Gain Control Word */
-        unsigned int agc_hold : 1;	/* Select AGC Hold Function */
-        unsigned int agc_off : 1;	/* Disable AGC Regulation */
-        unsigned int agc_rst : 1;	/* Reset AGC Gain */
-        unsigned int agc_hold_sel : 1;	/* Enable AGC Hold Function */
-        unsigned int : 2;
-};
-
-#define TST_AGC_struct _SFR_MEM8_STRUCT(0x17c, struct __reg_TST_AGC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_AGC */
-
-#define GC0                             0
-#define GC1                             1
-#define AGC_HOLD                        2
-#define AGC_OFF                         3
-#define AGC_RST                         4
-#define AGC_HOLD_SEL                    5
-
-/* Transceiver Sigma-Delta Modulator Control and Test Register */
-#define TST_SDM                         _SFR_MEM8(0x17D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_SDM {
-        unsigned int : 4;
-        unsigned int tx_rx_sel : 1;	/* Select Transmit/Receive Control Signal */
-        unsigned int tx_rx : 1;	/* Switch between Transmit and Receive */
-        unsigned int mod : 1;	/* Select Modulation Signal Type */
-        unsigned int mod_sel : 1;	/* Select Modulation Data Source */
-};
-
-#define TST_SDM_struct _SFR_MEM8_STRUCT(0x17d, struct __reg_TST_SDM)
-
-#endif /* __ASSEMBLER__ */
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
 
-  /* TST_SDM */
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
 
-#define TX_RX_SEL                       4
-#define TX_RX                           5
-#define MOD                             6
-#define MOD_SEL                         7
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ACME    6
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define MUX5    3
+#define ACCH    4
+#define REFOK   5
+#define AVDDOK  7
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define DIDR2   _SFR_MEM8(0x7D)
+#define ADC8D   0
+#define ADC9D   1
+#define ADC10D  2
+#define ADC11D  3
+#define ADC12D  4
+#define ADC13D  5
+#define ADC14D  6
+#define ADC15D  7
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1C0  2
+#define COM1C1  3
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1C   5
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define WGM30   0
+#define WGM31   1
+#define COM3C0  2
+#define COM3C1  3
+#define COM3B0  4
+#define COM3B1  5
+#define COM3A0  6
+#define COM3A1  7
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define CS30    0
+#define CS31    1
+#define CS32    2
+#define WGM32   3
+#define WGM33   4
+#define ICES3   6
+#define ICNC3   7
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3C   5
+#define FOC3B   6
+#define FOC3A   7
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+/* Reserved [0x9E..0x9F] */
+
+#define TCCR4A  _SFR_MEM8(0xA0)
+#define WGM40   0
+#define WGM41   1
+#define COM4C0  2
+#define COM4C1  3
+#define COM4B0  4
+#define COM4B1  5
+#define COM4A0  6
+#define COM4A1  7
+
+#define TCCR4B  _SFR_MEM8(0xA1)
+#define CS40    0
+#define CS41    1
+#define CS42    2
+#define WGM42   3
+#define WGM43   4
+#define ICES4   6
+#define ICNC4   7
+
+#define TCCR4C  _SFR_MEM8(0xA2)
+#define FOC4C   5
+#define FOC4B   6
+#define FOC4A   7
+
+/* Reserved [0xA3] */
+
+/* Combine TCNT4L and TCNT4H */
+#define TCNT4   _SFR_MEM16(0xA4)
+
+#define TCNT4L  _SFR_MEM8(0xA4)
+#define TCNT4H  _SFR_MEM8(0xA5)
+
+/* Combine ICR4L and ICR4H */
+#define ICR4    _SFR_MEM16(0xA6)
+
+#define ICR4L   _SFR_MEM8(0xA6)
+#define ICR4H   _SFR_MEM8(0xA7)
+
+/* Combine OCR4AL and OCR4AH */
+#define OCR4A   _SFR_MEM16(0xA8)
+
+#define OCR4AL  _SFR_MEM8(0xA8)
+#define OCR4AH  _SFR_MEM8(0xA9)
+
+/* Combine OCR4BL and OCR4BH */
+#define OCR4B   _SFR_MEM16(0xAA)
+
+#define OCR4BL  _SFR_MEM8(0xAA)
+#define OCR4BH  _SFR_MEM8(0xAB)
+
+/* Combine OCR4CL and OCR4CH */
+#define OCR4C   _SFR_MEM16(0xAC)
+
+#define OCR4CL  _SFR_MEM8(0xAC)
+#define OCR4CH  _SFR_MEM8(0xAD)
+
+/* Reserved [0xAE..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+#define EXCLKAMR 7
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+#define IRQ_MASK1 _SFR_MEM8(0xBE)
+#define TX_START_EN 0
+#define MAF_0_AMI_EN 1
+#define MAF_1_AMI_EN 2
+#define MAF_2_AMI_EN 3
+#define MAF_3_AMI_EN 4
+
+#define IRQ_STATUS1 _SFR_MEM8(0xBF)
+#define TX_START 0
+#define MAF_0_AMI 1
+#define MAF_1_AMI 2
+#define MAF_2_AMI 3
+#define MAF_3_AMI 4
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+#define UCPHA0  1
+#define UDORD0  2
+
+/* Reserved [0xC3] */
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+#define UCSR1B  _SFR_MEM8(0xC9)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+#define UCPHA1  1
+#define UDORD1  2
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0xCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define SCRSTRLL _SFR_MEM8(0xD7)
+#define SCRSTRLL0 0
+#define SCRSTRLL1 1
+#define SCRSTRLL2 2
+#define SCRSTRLL3 3
+#define SCRSTRLL4 4
+#define SCRSTRLL5 5
+#define SCRSTRLL6 6
+#define SCRSTRLL7 7
+
+#define SCRSTRLH _SFR_MEM8(0xD8)
+#define SCRSTRLH0 0
+#define SCRSTRLH1 1
+#define SCRSTRLH2 2
+#define SCRSTRLH3 3
+#define SCRSTRLH4 4
+#define SCRSTRLH5 5
+#define SCRSTRLH6 6
+#define SCRSTRLH7 7
+
+#define SCRSTRHL _SFR_MEM8(0xD9)
+#define SCRSTRHL0 0
+#define SCRSTRHL1 1
+#define SCRSTRHL2 2
+#define SCRSTRHL3 3
+#define SCRSTRHL4 4
+#define SCRSTRHL5 5
+#define SCRSTRHL6 6
+#define SCRSTRHL7 7
+
+#define SCRSTRHH _SFR_MEM8(0xDA)
+#define SCRSTRHH0 0
+#define SCRSTRHH1 1
+#define SCRSTRHH2 2
+#define SCRSTRHH3 3
+#define SCRSTRHH4 4
+#define SCRSTRHH5 5
+#define SCRSTRHH6 6
+#define SCRSTRHH7 7
+
+#define SCCSR   _SFR_MEM8(0xDB)
+#define SCCS10  0
+#define SCCS11  1
+#define SCCS20  2
+#define SCCS21  3
+#define SCCS30  4
+#define SCCS31  5
+
+#define SCCR0   _SFR_MEM8(0xDC)
+#define SCCMP1  0
+#define SCCMP2  1
+#define SCCMP3  2
+#define SCTSE   3
+#define SCCKSEL 4
+#define SCEN    5
+#define SCMBTS  6
+#define SCRES   7
+
+#define SCCR1   _SFR_MEM8(0xDD)
+#define SCENBO  0
+#define SCEECLK 1
+#define SCCKDIV0 2
+#define SCCKDIV1 3
+#define SCCKDIV2 4
+#define SCBTSM  5
+#define Res5    6
+#define Res6    7
+
+#define SCSR    _SFR_MEM8(0xDE)
+#define SCBSY   0
+
+#define SCIRQM  _SFR_MEM8(0xDF)
+#define IRQMCP1 0
+#define IRQMCP2 1
+#define IRQMCP3 2
+#define IRQMOF  3
+#define IRQMBO  4
+
+#define SCIRQS  _SFR_MEM8(0xE0)
+#define IRQSCP1 0
+#define IRQSCP2 1
+#define IRQSCP3 2
+#define IRQSOF  3
+#define IRQSBO  4
+
+#define SCCNTLL _SFR_MEM8(0xE1)
+#define SCCNTLL0 0
+#define SCCNTLL1 1
+#define SCCNTLL2 2
+#define SCCNTLL3 3
+#define SCCNTLL4 4
+#define SCCNTLL5 5
+#define SCCNTLL6 6
+#define SCCNTLL7 7
+
+#define SCCNTLH _SFR_MEM8(0xE2)
+#define SCCNTLH0 0
+#define SCCNTLH1 1
+#define SCCNTLH2 2
+#define SCCNTLH3 3
+#define SCCNTLH4 4
+#define SCCNTLH5 5
+#define SCCNTLH6 6
+#define SCCNTLH7 7
+
+#define SCCNTHL _SFR_MEM8(0xE3)
+#define SCCNTHL0 0
+#define SCCNTHL1 1
+#define SCCNTHL2 2
+#define SCCNTHL3 3
+#define SCCNTHL4 4
+#define SCCNTHL5 5
+#define SCCNTHL6 6
+#define SCCNTHL7 7
+
+#define SCCNTHH _SFR_MEM8(0xE4)
+#define SCCNTHH0 0
+#define SCCNTHH1 1
+#define SCCNTHH2 2
+#define SCCNTHH3 3
+#define SCCNTHH4 4
+#define SCCNTHH5 5
+#define SCCNTHH6 6
+#define SCCNTHH7 7
+
+#define SCBTSRLL _SFR_MEM8(0xE5)
+#define SCBTSRLL0 0
+#define SCBTSRLL1 1
+#define SCBTSRLL2 2
+#define SCBTSRLL3 3
+#define SCBTSRLL4 4
+#define SCBTSRLL5 5
+#define SCBTSRLL6 6
+#define SCBTSRLL7 7
+
+#define SCBTSRLH _SFR_MEM8(0xE6)
+#define SCBTSRLH0 0
+#define SCBTSRLH1 1
+#define SCBTSRLH2 2
+#define SCBTSRLH3 3
+#define SCBTSRLH4 4
+#define SCBTSRLH5 5
+#define SCBTSRLH6 6
+#define SCBTSRLH7 7
+
+#define SCBTSRHL _SFR_MEM8(0xE7)
+#define SCBTSRHL0 0
+#define SCBTSRHL1 1
+#define SCBTSRHL2 2
+#define SCBTSRHL3 3
+#define SCBTSRHL4 4
+#define SCBTSRHL5 5
+#define SCBTSRHL6 6
+#define SCBTSRHL7 7
+
+#define SCBTSRHH _SFR_MEM8(0xE8)
+#define SCBTSRHH0 0
+#define SCBTSRHH1 1
+#define SCBTSRHH2 2
+#define SCBTSRHH3 3
+#define SCBTSRHH4 4
+#define SCBTSRHH5 5
+#define SCBTSRHH6 6
+#define SCBTSRHH7 7
+
+#define SCTSRLL _SFR_MEM8(0xE9)
+#define SCTSRLL0 0
+#define SCTSRLL1 1
+#define SCTSRLL2 2
+#define SCTSRLL3 3
+#define SCTSRLL4 4
+#define SCTSRLL5 5
+#define SCTSRLL6 6
+#define SCTSRLL7 7
+
+#define SCTSRLH _SFR_MEM8(0xEA)
+#define SCTSRLH0 0
+#define SCTSRLH1 1
+#define SCTSRLH2 2
+#define SCTSRLH3 3
+#define SCTSRLH4 4
+#define SCTSRLH5 5
+#define SCTSRLH6 6
+#define SCTSRLH7 7
+
+#define SCTSRHL _SFR_MEM8(0xEB)
+#define SCTSRHL0 0
+#define SCTSRHL1 1
+#define SCTSRHL2 2
+#define SCTSRHL3 3
+#define SCTSRHL4 4
+#define SCTSRHL5 5
+#define SCTSRHL6 6
+#define SCTSRHL7 7
+
+#define SCTSRHH _SFR_MEM8(0xEC)
+#define SCTSRHH0 0
+#define SCTSRHH1 1
+#define SCTSRHH2 2
+#define SCTSRHH3 3
+#define SCTSRHH4 4
+#define SCTSRHH5 5
+#define SCTSRHH6 6
+#define SCTSRHH7 7
+
+#define SCOCR3LL _SFR_MEM8(0xED)
+#define SCOCR3LL0 0
+#define SCOCR3LL1 1
+#define SCOCR3LL2 2
+#define SCOCR3LL3 3
+#define SCOCR3LL4 4
+#define SCOCR3LL5 5
+#define SCOCR3LL6 6
+#define SCOCR3LL7 7
+
+#define SCOCR3LH _SFR_MEM8(0xEE)
+#define SCOCR3LH0 0
+#define SCOCR3LH1 1
+#define SCOCR3LH2 2
+#define SCOCR3LH3 3
+#define SCOCR3LH4 4
+#define SCOCR3LH5 5
+#define SCOCR3LH6 6
+#define SCOCR3LH7 7
+
+#define SCOCR3HL _SFR_MEM8(0xEF)
+#define SCOCR3HL0 0
+#define SCOCR3HL1 1
+#define SCOCR3HL2 2
+#define SCOCR3HL3 3
+#define SCOCR3HL4 4
+#define SCOCR3HL5 5
+#define SCOCR3HL6 6
+#define SCOCR3HL7 7
+
+#define SCOCR3HH _SFR_MEM8(0xF0)
+#define SCOCR3HH0 0
+#define SCOCR3HH1 1
+#define SCOCR3HH2 2
+#define SCOCR3HH3 3
+#define SCOCR3HH4 4
+#define SCOCR3HH5 5
+#define SCOCR3HH6 6
+#define SCOCR3HH7 7
+
+#define SCOCR2LL _SFR_MEM8(0xF1)
+#define SCOCR2LL0 0
+#define SCOCR2LL1 1
+#define SCOCR2LL2 2
+#define SCOCR2LL3 3
+#define SCOCR2LL4 4
+#define SCOCR2LL5 5
+#define SCOCR2LL6 6
+#define SCOCR2LL7 7
+
+#define SCOCR2LH _SFR_MEM8(0xF2)
+#define SCOCR2LH0 0
+#define SCOCR2LH1 1
+#define SCOCR2LH2 2
+#define SCOCR2LH3 3
+#define SCOCR2LH4 4
+#define SCOCR2LH5 5
+#define SCOCR2LH6 6
+#define SCOCR2LH7 7
+
+#define SCOCR2HL _SFR_MEM8(0xF3)
+#define SCOCR2HL0 0
+#define SCOCR2HL1 1
+#define SCOCR2HL2 2
+#define SCOCR2HL3 3
+#define SCOCR2HL4 4
+#define SCOCR2HL5 5
+#define SCOCR2HL6 6
+#define SCOCR2HL7 7
+
+#define SCOCR2HH _SFR_MEM8(0xF4)
+#define SCOCR2HH0 0
+#define SCOCR2HH1 1
+#define SCOCR2HH2 2
+#define SCOCR2HH3 3
+#define SCOCR2HH4 4
+#define SCOCR2HH5 5
+#define SCOCR2HH6 6
+#define SCOCR2HH7 7
+
+#define SCOCR1LL _SFR_MEM8(0xF5)
+#define SCOCR1LL0 0
+#define SCOCR1LL1 1
+#define SCOCR1LL2 2
+#define SCOCR1LL3 3
+#define SCOCR1LL4 4
+#define SCOCR1LL5 5
+#define SCOCR1LL6 6
+#define SCOCR1LL7 7
+
+#define SCOCR1LH _SFR_MEM8(0xF6)
+#define SCOCR1LH0 0
+#define SCOCR1LH1 1
+#define SCOCR1LH2 2
+#define SCOCR1LH3 3
+#define SCOCR1LH4 4
+#define SCOCR1LH5 5
+#define SCOCR1LH6 6
+#define SCOCR1LH7 7
+
+#define SCOCR1HL _SFR_MEM8(0xF7)
+#define SCOCR1HL0 0
+#define SCOCR1HL1 1
+#define SCOCR1HL2 2
+#define SCOCR1HL3 3
+#define SCOCR1HL4 4
+#define SCOCR1HL5 5
+#define SCOCR1HL6 6
+#define SCOCR1HL7 7
+
+#define SCOCR1HH _SFR_MEM8(0xF8)
+#define SCOCR1HH0 0
+#define SCOCR1HH1 1
+#define SCOCR1HH2 2
+#define SCOCR1HH3 3
+#define SCOCR1HH4 4
+#define SCOCR1HH5 5
+#define SCOCR1HH6 6
+#define SCOCR1HH7 7
+
+#define SCTSTRLL _SFR_MEM8(0xF9)
+#define SCTSTRLL0 0
+#define SCTSTRLL1 1
+#define SCTSTRLL2 2
+#define SCTSTRLL3 3
+#define SCTSTRLL4 4
+#define SCTSTRLL5 5
+#define SCTSTRLL6 6
+#define SCTSTRLL7 7
+
+#define SCTSTRLH _SFR_MEM8(0xFA)
+#define SCTSTRLH0 0
+#define SCTSTRLH1 1
+#define SCTSTRLH2 2
+#define SCTSTRLH3 3
+#define SCTSTRLH4 4
+#define SCTSTRLH5 5
+#define SCTSTRLH6 6
+#define SCTSTRLH7 7
+
+#define SCTSTRHL _SFR_MEM8(0xFB)
+#define SCTSTRHL0 0
+#define SCTSTRHL1 1
+#define SCTSTRHL2 2
+#define SCTSTRHL3 3
+#define SCTSTRHL4 4
+#define SCTSTRHL5 5
+#define SCTSTRHL6 6
+#define SCTSTRHL7 7
+
+#define SCTSTRHH _SFR_MEM8(0xFC)
+#define SCTSTRHH0 0
+#define SCTSTRHH1 1
+#define SCTSTRHH2 2
+#define SCTSTRHH3 3
+#define SCTSTRHH4 4
+#define SCTSTRHH5 5
+#define SCTSTRHH6 6
+#define SCTSTRHH7 7
+
+/* Reserved [0xFD..0x10B] */
+
+#define MAFCR0  _SFR_MEM8(0x10C)
+#define MAF0EN  0
+#define MAF1EN  1
+#define MAF2EN  2
+#define MAF3EN  3
+
+#define MAFCR1  _SFR_MEM8(0x10D)
+#define AACK_0_I_AM_COORD 0
+#define AACK_0_SET_PD 1
+#define AACK_1_I_AM_COORD 2
+#define AACK_1_SET_PD 3
+#define AACK_2_I_AM_COORD 4
+#define AACK_2_SET_PD 5
+#define AACK_3_I_AM_COORD 6
+#define AACK_3_SET_PD 7
+
+#define MAFSA0L _SFR_MEM8(0x10E)
+#define MAFSA0L0 0
+#define MAFSA0L1 1
+#define MAFSA0L2 2
+#define MAFSA0L3 3
+#define MAFSA0L4 4
+#define MAFSA0L5 5
+#define MAFSA0L6 6
+#define MAFSA0L7 7
+
+#define MAFSA0H _SFR_MEM8(0x10F)
+#define MAFSA0H0 0
+#define MAFSA0H1 1
+#define MAFSA0H2 2
+#define MAFSA0H3 3
+#define MAFSA0H4 4
+#define MAFSA0H5 5
+#define MAFSA0H6 6
+#define MAFSA0H7 7
+
+#define MAFPA0L _SFR_MEM8(0x110)
+#define MAFPA0L0 0
+#define MAFPA0L1 1
+#define MAFPA0L2 2
+#define MAFPA0L3 3
+#define MAFPA0L4 4
+#define MAFPA0L5 5
+#define MAFPA0L6 6
+#define MAFPA0L7 7
+
+#define MAFPA0H _SFR_MEM8(0x111)
+#define MAFPA0H0 0
+#define MAFPA0H1 1
+#define MAFPA0H2 2
+#define MAFPA0H3 3
+#define MAFPA0H4 4
+#define MAFPA0H5 5
+#define MAFPA0H6 6
+#define MAFPA0H7 7
+
+#define MAFSA1L _SFR_MEM8(0x112)
+#define MAFSA1L0 0
+#define MAFSA1L1 1
+#define MAFSA1L2 2
+#define MAFSA1L3 3
+#define MAFSA1L4 4
+#define MAFSA1L5 5
+#define MAFSA1L6 6
+#define MAFSA1L7 7
+
+#define MAFSA1H _SFR_MEM8(0x113)
+#define MAFSA1H0 0
+#define MAFSA1H1 1
+#define MAFSA1H2 2
+#define MAFSA1H3 3
+#define MAFSA1H4 4
+#define MAFSA1H5 5
+#define MAFSA1H6 6
+#define MAFSA1H7 7
+
+#define MAFPA1L _SFR_MEM8(0x114)
+#define MAFPA1L0 0
+#define MAFPA1L1 1
+#define MAFPA1L2 2
+#define MAFPA1L3 3
+#define MAFPA1L4 4
+#define MAFPA1L5 5
+#define MAFPA1L6 6
+#define MAFPA1L7 7
+
+#define MAFPA1H _SFR_MEM8(0x115)
+#define MAFPA1H0 0
+#define MAFPA1H1 1
+#define MAFPA1H2 2
+#define MAFPA1H3 3
+#define MAFPA1H4 4
+#define MAFPA1H5 5
+#define MAFPA1H6 6
+#define MAFPA1H7 7
+
+#define MAFSA2L _SFR_MEM8(0x116)
+#define MAFSA2L0 0
+#define MAFSA2L1 1
+#define MAFSA2L2 2
+#define MAFSA2L3 3
+#define MAFSA2L4 4
+#define MAFSA2L5 5
+#define MAFSA2L6 6
+#define MAFSA2L7 7
+
+#define MAFSA2H _SFR_MEM8(0x117)
+#define MAFSA2H0 0
+#define MAFSA2H1 1
+#define MAFSA2H2 2
+#define MAFSA2H3 3
+#define MAFSA2H4 4
+#define MAFSA2H5 5
+#define MAFSA2H6 6
+#define MAFSA2H7 7
+
+#define MAFPA2L _SFR_MEM8(0x118)
+#define MAFPA2L0 0
+#define MAFPA2L1 1
+#define MAFPA2L2 2
+#define MAFPA2L3 3
+#define MAFPA2L4 4
+#define MAFPA2L5 5
+#define MAFPA2L6 6
+#define MAFPA2L7 7
+
+#define MAFPA2H _SFR_MEM8(0x119)
+#define MAFPA2H0 0
+#define MAFPA2H1 1
+#define MAFPA2H2 2
+#define MAFPA2H3 3
+#define MAFPA2H4 4
+#define MAFPA2H5 5
+#define MAFPA2H6 6
+#define MAFPA2H7 7
+
+#define MAFSA3L _SFR_MEM8(0x11A)
+#define MAFSA3L0 0
+#define MAFSA3L1 1
+#define MAFSA3L2 2
+#define MAFSA3L3 3
+#define MAFSA3L4 4
+#define MAFSA3L5 5
+#define MAFSA3L6 6
+#define MAFSA3L7 7
+
+#define MAFSA3H _SFR_MEM8(0x11B)
+#define MAFSA3H0 0
+#define MAFSA3H1 1
+#define MAFSA3H2 2
+#define MAFSA3H3 3
+#define MAFSA3H4 4
+#define MAFSA3H5 5
+#define MAFSA3H6 6
+#define MAFSA3H7 7
+
+#define MAFPA3L _SFR_MEM8(0x11C)
+#define MAFPA3L0 0
+#define MAFPA3L1 1
+#define MAFPA3L2 2
+#define MAFPA3L3 3
+#define MAFPA3L4 4
+#define MAFPA3L5 5
+#define MAFPA3L6 6
+#define MAFPA3L7 7
+
+#define MAFPA3H _SFR_MEM8(0x11D)
+#define MAFPA3H0 0
+#define MAFPA3H1 1
+#define MAFPA3H2 2
+#define MAFPA3H3 3
+#define MAFPA3H4 4
+#define MAFPA3H5 5
+#define MAFPA3H6 6
+#define MAFPA3H7 7
+
+/* Reserved [0x11E..0x11F] */
+
+#define TCCR5A  _SFR_MEM8(0x120)
+#define WGM50   0
+#define WGM51   1
+#define COM5C0  2
+#define COM5C1  3
+#define COM5B0  4
+#define COM5B1  5
+#define COM5A0  6
+#define COM5A1  7
+
+#define TCCR5B  _SFR_MEM8(0x121)
+#define CS50    0
+#define CS51    1
+#define CS52    2
+#define WGM52   3
+#define WGM53   4
+#define ICES5   6
+#define ICNC5   7
+
+#define TCCR5C  _SFR_MEM8(0x122)
+#define FOC5C   5
+#define FOC5B   6
+#define FOC5A   7
+
+/* Reserved [0x123] */
+
+/* Combine TCNT5L and TCNT5H */
+#define TCNT5   _SFR_MEM16(0x124)
+
+#define TCNT5L  _SFR_MEM8(0x124)
+#define TCNT5H  _SFR_MEM8(0x125)
+
+/* Combine ICR5L and ICR5H */
+#define ICR5    _SFR_MEM16(0x126)
+
+#define ICR5L   _SFR_MEM8(0x126)
+#define ICR5H   _SFR_MEM8(0x127)
+
+/* Combine OCR5AL and OCR5AH */
+#define OCR5A   _SFR_MEM16(0x128)
+
+#define OCR5AL  _SFR_MEM8(0x128)
+#define OCR5AH  _SFR_MEM8(0x129)
+
+/* Combine OCR5BL and OCR5BH */
+#define OCR5B   _SFR_MEM16(0x12A)
+
+#define OCR5BL  _SFR_MEM8(0x12A)
+#define OCR5BH  _SFR_MEM8(0x12B)
+
+/* Combine OCR5CL and OCR5CH */
+#define OCR5C   _SFR_MEM16(0x12C)
+
+#define OCR5CL  _SFR_MEM8(0x12C)
+#define OCR5CH  _SFR_MEM8(0x12D)
+
+/* Reserved [0x12E] */
+
+#define LLCR    _SFR_MEM8(0x12F)
+#define LLENCAL 0
+#define LLSHORT 1
+#define LLTCO   2
+#define LLCAL   3
+#define LLCOMP  4
+#define LLDONE  5
+
+#define LLDRL   _SFR_MEM8(0x130)
+#define LLDRL0  0
+#define LLDRL1  1
+#define LLDRL2  2
+#define LLDRL3  3
+
+#define LLDRH   _SFR_MEM8(0x131)
+#define LLDRH0  0
+#define LLDRH1  1
+#define LLDRH2  2
+#define LLDRH3  3
+#define LLDRH4  4
+
+#define DRTRAM3 _SFR_MEM8(0x132)
+#define ENDRT   4
+#define DRTSWOK 5
+
+#define DRTRAM2 _SFR_MEM8(0x133)
+
+#define DRTRAM1 _SFR_MEM8(0x134)
+
+#define DRTRAM0 _SFR_MEM8(0x135)
+
+#define DPDS0   _SFR_MEM8(0x136)
+#define PBDRV0  0
+#define PBDRV1  1
+#define PDDRV0  2
+#define PDDRV1  3
+#define PEDRV0  4
+#define PEDRV1  5
+#define PFDRV0  6
+#define PFDRV1  7
+
+#define DPDS1   _SFR_MEM8(0x137)
+#define PGDRV0  0
+#define PGDRV1  1
+
+#define PARCR   _SFR_MEM8(0x138)
+#define PARUFI  0
+#define PARDFI  1
+#define PALTU0  2
+#define PALTU1  3
+#define PALTU2  4
+#define PALTD0  5
+#define PALTD1  6
+#define PALTD2  7
+
+#define TRXPR   _SFR_MEM8(0x139)
+#define TRXRST  0
+#define SLPTR   1
+
+/* Reserved [0x13A..0x13B] */
+
+#define AES_CTRL _SFR_MEM8(0x13C)
+#define AES_IM  2
+#define AES_DIR 3
+#define AES_MODE 5
+#define AES_REQUEST 7
+
+#define AES_STATUS _SFR_MEM8(0x13D)
+#define AES_DONE 0
+#define AES_ER  7
+
+#define AES_STATE _SFR_MEM8(0x13E)
+#define AES_STATE0 0
+#define AES_STATE1 1
+#define AES_STATE2 2
+#define AES_STATE3 3
+#define AES_STATE4 4
+#define AES_STATE5 5
+#define AES_STATE6 6
+#define AES_STATE7 7
+
+#define AES_KEY _SFR_MEM8(0x13F)
+#define AES_KEY0 0
+#define AES_KEY1 1
+#define AES_KEY2 2
+#define AES_KEY3 3
+#define AES_KEY4 4
+#define AES_KEY5 5
+#define AES_KEY6 6
+#define AES_KEY7 7
+
+/* Reserved [0x140] */
+
+#define TRX_STATUS _SFR_MEM8(0x141)
+#define TRX_STATUS0 0
+#define TRX_STATUS1 1
+#define TRX_STATUS2 2
+#define TRX_STATUS3 3
+#define TRX_STATUS4 4
+#define TST_STATUS 5
+#define CCA_STATUS 6
+#define CCA_DONE 7
+
+#define TRX_STATE _SFR_MEM8(0x142)
+#define TRX_CMD0 0
+#define TRX_CMD1 1
+#define TRX_CMD2 2
+#define TRX_CMD3 3
+#define TRX_CMD4 4
+#define TRAC_STATUS0 5
+#define TRAC_STATUS1 6
+#define TRAC_STATUS2 7
+
+#define TRX_CTRL_0 _SFR_MEM8(0x143)
+#define PMU_IF_INV 4
+#define PMU_START 5
+#define PMU_EN  6
+#define Res7    7
+
+#define TRX_CTRL_1 _SFR_MEM8(0x144)
+#define PLL_TX_FLT 4
+#define TX_AUTO_CRC_ON 5
+#define IRQ_2_EXT_EN 6
+#define PA_EXT_EN 7
+
+#define PHY_TX_PWR _SFR_MEM8(0x145)
+#define TX_PWR0 0
+#define TX_PWR1 1
+#define TX_PWR2 2
+#define TX_PWR3 3
+
+#define PHY_RSSI _SFR_MEM8(0x146)
+#define RSSI0   0
+#define RSSI1   1
+#define RSSI2   2
+#define RSSI3   3
+#define RSSI4   4
+#define RND_VALUE0 5
+#define RND_VALUE1 6
+#define RX_CRC_VALID 7
+
+#define PHY_ED_LEVEL _SFR_MEM8(0x147)
+#define ED_LEVEL0 0
+#define ED_LEVEL1 1
+#define ED_LEVEL2 2
+#define ED_LEVEL3 3
+#define ED_LEVEL4 4
+#define ED_LEVEL5 5
+#define ED_LEVEL6 6
+#define ED_LEVEL7 7
+
+#define PHY_CC_CCA _SFR_MEM8(0x148)
+#define CHANNEL0 0
+#define CHANNEL1 1
+#define CHANNEL2 2
+#define CHANNEL3 3
+#define CHANNEL4 4
+#define CCA_MODE0 5
+#define CCA_MODE1 6
+#define CCA_REQUEST 7
+
+#define CCA_THRES _SFR_MEM8(0x149)
+#define CCA_ED_THRES0 0
+#define CCA_ED_THRES1 1
+#define CCA_ED_THRES2 2
+#define CCA_ED_THRES3 3
+#define CCA_CS_THRES0 4
+#define CCA_CS_THRES1 5
+#define CCA_CS_THRES2 6
+#define CCA_CS_THRES3 7
+
+#define RX_CTRL _SFR_MEM8(0x14A)
+#define PDT_THRES0 0
+#define PDT_THRES1 1
+#define PDT_THRES2 2
+#define PDT_THRES3 3
+
+#define SFD_VALUE _SFR_MEM8(0x14B)
+#define SFD_VALUE0 0
+#define SFD_VALUE1 1
+#define SFD_VALUE2 2
+#define SFD_VALUE3 3
+#define SFD_VALUE4 4
+#define SFD_VALUE5 5
+#define SFD_VALUE6 6
+#define SFD_VALUE7 7
+
+#define TRX_CTRL_2 _SFR_MEM8(0x14C)
+#define OQPSK_DATA_RATE0 0
+#define OQPSK_DATA_RATE1 1
+#define RX_SAFE_MODE 7
+
+#define ANT_DIV _SFR_MEM8(0x14D)
+#define ANT_CTRL0 0
+#define ANT_CTRL1 1
+#define ANT_EXT_SW_EN 2
+#define ANT_DIV_EN 3
+#define ANT_SEL 7
+
+#define IRQ_MASK _SFR_MEM8(0x14E)
+#define PLL_LOCK_EN 0
+#define PLL_UNLOCK_EN 1
+#define RX_START_EN 2
+#define RX_END_EN 3
+#define CCA_ED_DONE_EN 4
+#define AMI_EN  5
+#define TX_END_EN 6
+#define AWAKE_EN 7
+
+#define IRQ_STATUS _SFR_MEM8(0x14F)
+#define PLL_LOCK 0
+#define PLL_UNLOCK 1
+#define RX_START 2
+#define RX_END  3
+#define CCA_ED_DONE 4
+#define AMI     5
+#define TX_END  6
+#define AWAKE   7
+
+#define VREG_CTRL _SFR_MEM8(0x150)
+#define DVDD_OK 2
+#define DVREG_EXT 3
+#define AVDD_OK 6
+#define AVREG_EXT 7
+
+#define BATMON  _SFR_MEM8(0x151)
+#define BATMON_VTH0 0
+#define BATMON_VTH1 1
+#define BATMON_VTH2 2
+#define BATMON_VTH3 3
+#define BATMON_HR 4
+#define BATMON_OK 5
+#define BAT_LOW_EN 6
+#define BAT_LOW 7
+
+#define XOSC_CTRL _SFR_MEM8(0x152)
+#define XTAL_TRIM0 0
+#define XTAL_TRIM1 1
+#define XTAL_TRIM2 2
+#define XTAL_TRIM3 3
+#define XTAL_MODE0 4
+#define XTAL_MODE1 5
+#define XTAL_MODE2 6
+#define XTAL_MODE3 7
+
+#define CC_CTRL_0 _SFR_MEM8(0x153)
+#define CC_NUMBER0 0
+#define CC_NUMBER1 1
+#define CC_NUMBER2 2
+#define CC_NUMBER3 3
+#define CC_NUMBER4 4
+#define CC_NUMBER5 5
+#define CC_NUMBER6 6
+#define CC_NUMBER7 7
+
+#define CC_CTRL_1 _SFR_MEM8(0x154)
+#define CC_BAND0 0
+#define CC_BAND1 1
+#define CC_BAND2 2
+#define CC_BAND3 3
+
+#define RX_SYN  _SFR_MEM8(0x155)
+#define RX_PDT_LEVEL0 0
+#define RX_PDT_LEVEL1 1
+#define RX_PDT_LEVEL2 2
+#define RX_PDT_LEVEL3 3
+#define RX_OVERRIDE 6
+#define RX_PDT_DIS 7
+
+#define TRX_RPC _SFR_MEM8(0x156)
+#define XAH_RPC_EN 0
+#define IPAN_RPC_EN 1
+#define PLL_RPC_EN 3
+#define PDT_RPC_EN 4
+#define RX_RPC_EN 5
+#define RX_RPC_CTRL0 6
+#define RX_RPC_CTRL1 7
+
+#define XAH_CTRL_1 _SFR_MEM8(0x157)
+#define AACK_PROM_MODE 1
+#define AACK_ACK_TIME 2
+#define AACK_UPLD_RES_FT 4
+#define AACK_FLTR_RES_FT 5
+
+#define FTN_CTRL _SFR_MEM8(0x158)
+#define FTN_START 7
+
+/* Reserved [0x159] */
+
+#define PLL_CF  _SFR_MEM8(0x15A)
+#define PLL_CF_START 7
+
+#define PLL_DCU _SFR_MEM8(0x15B)
+#define PLL_DCU_START 7
+
+#define PART_NUM _SFR_MEM8(0x15C)
+#define PART_NUM0 0
+#define PART_NUM1 1
+#define PART_NUM2 2
+#define PART_NUM3 3
+#define PART_NUM4 4
+#define PART_NUM5 5
+#define PART_NUM6 6
+#define PART_NUM7 7
+
+#define VERSION_NUM _SFR_MEM8(0x15D)
+#define VERSION_NUM0 0
+#define VERSION_NUM1 1
+#define VERSION_NUM2 2
+#define VERSION_NUM3 3
+#define VERSION_NUM4 4
+#define VERSION_NUM5 5
+#define VERSION_NUM6 6
+#define VERSION_NUM7 7
+
+#define MAN_ID_0 _SFR_MEM8(0x15E)
+#define MAN_ID_00 0
+#define MAN_ID_01 1
+#define MAN_ID_02 2
+#define MAN_ID_03 3
+#define MAN_ID_04 4
+#define MAN_ID_05 5
+#define MAN_ID_06 6
+#define MAN_ID_07 7
+
+#define MAN_ID_1 _SFR_MEM8(0x15F)
+#define MAN_ID_10 0
+#define MAN_ID_11 1
+#define MAN_ID_12 2
+#define MAN_ID_13 3
+#define MAN_ID_14 4
+#define MAN_ID_15 5
+#define MAN_ID_16 6
+#define MAN_ID_17 7
+
+#define SHORT_ADDR_0 _SFR_MEM8(0x160)
+#define SHORT_ADDR_00 0
+#define SHORT_ADDR_01 1
+#define SHORT_ADDR_02 2
+#define SHORT_ADDR_03 3
+#define SHORT_ADDR_04 4
+#define SHORT_ADDR_05 5
+#define SHORT_ADDR_06 6
+#define SHORT_ADDR_07 7
+
+#define SHORT_ADDR_1 _SFR_MEM8(0x161)
+#define SHORT_ADDR_10 0
+#define SHORT_ADDR_11 1
+#define SHORT_ADDR_12 2
+#define SHORT_ADDR_13 3
+#define SHORT_ADDR_14 4
+#define SHORT_ADDR_15 5
+#define SHORT_ADDR_16 6
+#define SHORT_ADDR_17 7
+
+#define PAN_ID_0 _SFR_MEM8(0x162)
+#define PAN_ID_00 0
+#define PAN_ID_01 1
+#define PAN_ID_02 2
+#define PAN_ID_03 3
+#define PAN_ID_04 4
+#define PAN_ID_05 5
+#define PAN_ID_06 6
+#define PAN_ID_07 7
+
+#define PAN_ID_1 _SFR_MEM8(0x163)
+#define PAN_ID_10 0
+#define PAN_ID_11 1
+#define PAN_ID_12 2
+#define PAN_ID_13 3
+#define PAN_ID_14 4
+#define PAN_ID_15 5
+#define PAN_ID_16 6
+#define PAN_ID_17 7
+
+#define IEEE_ADDR_0 _SFR_MEM8(0x164)
+#define IEEE_ADDR_00 0
+#define IEEE_ADDR_01 1
+#define IEEE_ADDR_02 2
+#define IEEE_ADDR_03 3
+#define IEEE_ADDR_04 4
+#define IEEE_ADDR_05 5
+#define IEEE_ADDR_06 6
+#define IEEE_ADDR_07 7
+
+#define IEEE_ADDR_1 _SFR_MEM8(0x165)
+#define IEEE_ADDR_10 0
+#define IEEE_ADDR_11 1
+#define IEEE_ADDR_12 2
+#define IEEE_ADDR_13 3
+#define IEEE_ADDR_14 4
+#define IEEE_ADDR_15 5
+#define IEEE_ADDR_16 6
+#define IEEE_ADDR_17 7
+
+#define IEEE_ADDR_2 _SFR_MEM8(0x166)
+#define IEEE_ADDR_20 0
+#define IEEE_ADDR_21 1
+#define IEEE_ADDR_22 2
+#define IEEE_ADDR_23 3
+#define IEEE_ADDR_24 4
+#define IEEE_ADDR_25 5
+#define IEEE_ADDR_26 6
+#define IEEE_ADDR_27 7
+
+#define IEEE_ADDR_3 _SFR_MEM8(0x167)
+#define IEEE_ADDR_30 0
+#define IEEE_ADDR_31 1
+#define IEEE_ADDR_32 2
+#define IEEE_ADDR_33 3
+#define IEEE_ADDR_34 4
+#define IEEE_ADDR_35 5
+#define IEEE_ADDR_36 6
+#define IEEE_ADDR_37 7
+
+#define IEEE_ADDR_4 _SFR_MEM8(0x168)
+#define IEEE_ADDR_40 0
+#define IEEE_ADDR_41 1
+#define IEEE_ADDR_42 2
+#define IEEE_ADDR_43 3
+#define IEEE_ADDR_44 4
+#define IEEE_ADDR_45 5
+#define IEEE_ADDR_46 6
+#define IEEE_ADDR_47 7
+
+#define IEEE_ADDR_5 _SFR_MEM8(0x169)
+#define IEEE_ADDR_50 0
+#define IEEE_ADDR_51 1
+#define IEEE_ADDR_52 2
+#define IEEE_ADDR_53 3
+#define IEEE_ADDR_54 4
+#define IEEE_ADDR_55 5
+#define IEEE_ADDR_56 6
+#define IEEE_ADDR_57 7
+
+#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
+#define IEEE_ADDR_60 0
+#define IEEE_ADDR_61 1
+#define IEEE_ADDR_62 2
+#define IEEE_ADDR_63 3
+#define IEEE_ADDR_64 4
+#define IEEE_ADDR_65 5
+#define IEEE_ADDR_66 6
+#define IEEE_ADDR_67 7
+
+#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
+#define IEEE_ADDR_70 0
+#define IEEE_ADDR_71 1
+#define IEEE_ADDR_72 2
+#define IEEE_ADDR_73 3
+#define IEEE_ADDR_74 4
+#define IEEE_ADDR_75 5
+#define IEEE_ADDR_76 6
+#define IEEE_ADDR_77 7
+
+#define XAH_CTRL_0 _SFR_MEM8(0x16C)
+#define SLOTTED_OPERATION 0
+#define MAX_CSMA_RETRIES0 1
+#define MAX_CSMA_RETRIES1 2
+#define MAX_CSMA_RETRIES2 3
+#define MAX_FRAME_RETRIES0 4
+#define MAX_FRAME_RETRIES1 5
+#define MAX_FRAME_RETRIES2 6
+#define MAX_FRAME_RETRIES3 7
+
+#define CSMA_SEED_0 _SFR_MEM8(0x16D)
+#define CSMA_SEED_00 0
+#define CSMA_SEED_01 1
+#define CSMA_SEED_02 2
+#define CSMA_SEED_03 3
+#define CSMA_SEED_04 4
+#define CSMA_SEED_05 5
+#define CSMA_SEED_06 6
+#define CSMA_SEED_07 7
+
+#define CSMA_SEED_1 _SFR_MEM8(0x16E)
+#define CSMA_SEED_10 0
+#define CSMA_SEED_11 1
+#define CSMA_SEED_12 2
+#define AACK_I_AM_COORD 3
+#define AACK_DIS_ACK 4
+#define AACK_SET_PD 5
+#define AACK_FVN_MODE0 6
+#define AACK_FVN_MODE1 7
+
+#define CSMA_BE _SFR_MEM8(0x16F)
+#define MIN_BE0 0
+#define MIN_BE1 1
+#define MIN_BE2 2
+#define MIN_BE3 3
+#define MAX_BE0 4
+#define MAX_BE1 5
+#define MAX_BE2 6
+#define MAX_BE3 7
+
+/* Reserved [0x170..0x175] */
+
+#define TST_CTRL_DIGI _SFR_MEM8(0x176)
+#define TST_CTRL_DIG0 0
+#define TST_CTRL_DIG1 1
+#define TST_CTRL_DIG2 2
+#define TST_CTRL_DIG3 3
+
+/* Reserved [0x177..0x17A] */
+
+#define TST_RX_LENGTH _SFR_MEM8(0x17B)
+#define RX_LENGTH0 0
+#define RX_LENGTH1 1
+#define RX_LENGTH2 2
+#define RX_LENGTH3 3
+#define RX_LENGTH4 4
+#define RX_LENGTH5 5
+#define RX_LENGTH6 6
+#define RX_LENGTH7 7
+
+/* Reserved [0x17C..0x17F] */
+
+#define TRXFBST _SFR_MEM8(0x180)
 
-/* Start of frame buffer */
-#define TRXFBST                         _SFR_MEM8(0x180)
+/* Reserved [0x181..0x1FE] */
 
-  /* TRXFBST */
+#define TRXFBEND _SFR_MEM8(0x1FF)
 
-#define TRXFBST0                        0
-#define TRXFBST1                        1
-#define TRXFBST2                        2
-#define TRXFBST3                        3
-#define TRXFBST4                        4
-#define TRXFBST5                        5
-#define TRXFBST6                        6
-#define TRXFBST7                        7
 
-/* End of frame buffer */
-#define TRXFBEND                        _SFR_MEM8(0x1FF)
 
-  /* TRXFBEND */
+/* Values and associated defines */
 
-#define TRXFBEND0                       0
-#define TRXFBEND1                       1
-#define TRXFBEND2                       2
-#define TRXFBEND3                       3
-#define TRXFBEND4                       4
-#define TRXFBEND5                       5
-#define TRXFBEND6                       6
-#define TRXFBEND7                       7
 
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
-
-#define _VECTORS_SIZE                  308
-
 /* External Interrupt Request 0 */
-#define INT0_vect                       _VECTOR(1)
-#define INT0_vect_num                   1
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
 
 /* External Interrupt Request 1 */
-#define INT1_vect                       _VECTOR(2)
-#define INT1_vect_num                   2
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
 
 /* External Interrupt Request 2 */
-#define INT2_vect                       _VECTOR(3)
-#define INT2_vect_num                   3
+#define INT2_vect            _VECTOR(3)
+#define INT2_vect_num        3
 
 /* External Interrupt Request 3 */
-#define INT3_vect                       _VECTOR(4)
-#define INT3_vect_num                   4
+#define INT3_vect            _VECTOR(4)
+#define INT3_vect_num        4
 
 /* External Interrupt Request 4 */
-#define INT4_vect                       _VECTOR(5)
-#define INT4_vect_num                   5
+#define INT4_vect            _VECTOR(5)
+#define INT4_vect_num        5
 
 /* External Interrupt Request 5 */
-#define INT5_vect                       _VECTOR(6)
-#define INT5_vect_num                   6
+#define INT5_vect            _VECTOR(6)
+#define INT5_vect_num        6
 
 /* External Interrupt Request 6 */
-#define INT6_vect                       _VECTOR(7)
-#define INT6_vect_num                   7
+#define INT6_vect            _VECTOR(7)
+#define INT6_vect_num        7
 
 /* External Interrupt Request 7 */
-#define INT7_vect                       _VECTOR(8)
-#define INT7_vect_num                   8
+#define INT7_vect            _VECTOR(8)
+#define INT7_vect_num        8
 
 /* Pin Change Interrupt Request 0 */
-#define PCINT0_vect                     _VECTOR(9)
-#define PCINT0_vect_num                 9
+#define PCINT0_vect            _VECTOR(9)
+#define PCINT0_vect_num        9
 
 /* Pin Change Interrupt Request 1 */
-#define PCINT1_vect                     _VECTOR(10)
-#define PCINT1_vect_num                 10
+#define PCINT1_vect            _VECTOR(10)
+#define PCINT1_vect_num        10
 
 /* Pin Change Interrupt Request 2 */
-#define PCINT2_vect                     _VECTOR(11)
-#define PCINT2_vect_num                 11
+#define PCINT2_vect            _VECTOR(11)
+#define PCINT2_vect_num        11
 
 /* Watchdog Time-out Interrupt */
-#define WDT_vect                        _VECTOR(12)
-#define WDT_vect_num                    12
+#define WDT_vect            _VECTOR(12)
+#define WDT_vect_num        12
 
 /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect               _VECTOR(13)
-#define TIMER2_COMPA_vect_num           13
+#define TIMER2_COMPA_vect            _VECTOR(13)
+#define TIMER2_COMPA_vect_num        13
 
 /* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect               _VECTOR(14)
-#define TIMER2_COMPB_vect_num           14
+#define TIMER2_COMPB_vect            _VECTOR(14)
+#define TIMER2_COMPB_vect_num        14
 
 /* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect                 _VECTOR(15)
-#define TIMER2_OVF_vect_num             15
+#define TIMER2_OVF_vect            _VECTOR(15)
+#define TIMER2_OVF_vect_num        15
 
 /* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect                _VECTOR(16)
-#define TIMER1_CAPT_vect_num            16
+#define TIMER1_CAPT_vect            _VECTOR(16)
+#define TIMER1_CAPT_vect_num        16
 
 /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect               _VECTOR(17)
-#define TIMER1_COMPA_vect_num           17
+#define TIMER1_COMPA_vect            _VECTOR(17)
+#define TIMER1_COMPA_vect_num        17
 
 /* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect               _VECTOR(18)
-#define TIMER1_COMPB_vect_num           18
+#define TIMER1_COMPB_vect            _VECTOR(18)
+#define TIMER1_COMPB_vect_num        18
 
 /* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect               _VECTOR(19)
-#define TIMER1_COMPC_vect_num           19
+#define TIMER1_COMPC_vect            _VECTOR(19)
+#define TIMER1_COMPC_vect_num        19
 
 /* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect                 _VECTOR(20)
-#define TIMER1_OVF_vect_num             20
+#define TIMER1_OVF_vect            _VECTOR(20)
+#define TIMER1_OVF_vect_num        20
 
 /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect               _VECTOR(21)
-#define TIMER0_COMPA_vect_num           21
+#define TIMER0_COMPA_vect            _VECTOR(21)
+#define TIMER0_COMPA_vect_num        21
 
 /* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect               _VECTOR(22)
-#define TIMER0_COMPB_vect_num           22
+#define TIMER0_COMPB_vect            _VECTOR(22)
+#define TIMER0_COMPB_vect_num        22
 
 /* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect                 _VECTOR(23)
-#define TIMER0_OVF_vect_num             23
+#define TIMER0_OVF_vect            _VECTOR(23)
+#define TIMER0_OVF_vect_num        23
 
 /* SPI Serial Transfer Complete */
-#define SPI_STC_vect                    _VECTOR(24)
-#define SPI_STC_vect_num                24
+#define SPI_STC_vect            _VECTOR(24)
+#define SPI_STC_vect_num        24
 
 /* USART0, Rx Complete */
-#define USART0_RX_vect                  _VECTOR(25)
-#define USART0_RX_vect_num              25
+#define USART0_RX_vect            _VECTOR(25)
+#define USART0_RX_vect_num        25
 
 /* USART0 Data register Empty */
-#define USART0_UDRE_vect                _VECTOR(26)
-#define USART0_UDRE_vect_num            26
+#define USART0_UDRE_vect            _VECTOR(26)
+#define USART0_UDRE_vect_num        26
 
 /* USART0, Tx Complete */
-#define USART0_TX_vect                  _VECTOR(27)
-#define USART0_TX_vect_num              27
+#define USART0_TX_vect            _VECTOR(27)
+#define USART0_TX_vect_num        27
 
 /* Analog Comparator */
-#define ANALOG_COMP_vect                _VECTOR(28)
-#define ANALOG_COMP_vect_num            28
+#define ANALOG_COMP_vect            _VECTOR(28)
+#define ANALOG_COMP_vect_num        28
 
 /* ADC Conversion Complete */
-#define ADC_vect                        _VECTOR(29)
-#define ADC_vect_num                    29
+#define ADC_vect            _VECTOR(29)
+#define ADC_vect_num        29
 
 /* EEPROM Ready */
-#define EE_READY_vect                   _VECTOR(30)
-#define EE_READY_vect_num               30
+#define EE_READY_vect            _VECTOR(30)
+#define EE_READY_vect_num        30
 
 /* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect                _VECTOR(31)
-#define TIMER3_CAPT_vect_num            31
+#define TIMER3_CAPT_vect            _VECTOR(31)
+#define TIMER3_CAPT_vect_num        31
 
 /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect               _VECTOR(32)
-#define TIMER3_COMPA_vect_num           32
+#define TIMER3_COMPA_vect            _VECTOR(32)
+#define TIMER3_COMPA_vect_num        32
 
 /* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect               _VECTOR(33)
-#define TIMER3_COMPB_vect_num           33
+#define TIMER3_COMPB_vect            _VECTOR(33)
+#define TIMER3_COMPB_vect_num        33
 
 /* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect               _VECTOR(34)
-#define TIMER3_COMPC_vect_num           34
+#define TIMER3_COMPC_vect            _VECTOR(34)
+#define TIMER3_COMPC_vect_num        34
 
 /* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect                 _VECTOR(35)
-#define TIMER3_OVF_vect_num             35
+#define TIMER3_OVF_vect            _VECTOR(35)
+#define TIMER3_OVF_vect_num        35
 
 /* USART1, Rx Complete */
-#define USART1_RX_vect                  _VECTOR(36)
-#define USART1_RX_vect_num              36
+#define USART1_RX_vect            _VECTOR(36)
+#define USART1_RX_vect_num        36
 
 /* USART1 Data register Empty */
-#define USART1_UDRE_vect                _VECTOR(37)
-#define USART1_UDRE_vect_num            37
+#define USART1_UDRE_vect            _VECTOR(37)
+#define USART1_UDRE_vect_num        37
 
 /* USART1, Tx Complete */
-#define USART1_TX_vect                  _VECTOR(38)
-#define USART1_TX_vect_num              38
+#define USART1_TX_vect            _VECTOR(38)
+#define USART1_TX_vect_num        38
 
 /* 2-wire Serial Interface */
-#define TWI_vect                        _VECTOR(39)
-#define TWI_vect_num                    39
+#define TWI_vect            _VECTOR(39)
+#define TWI_vect_num        39
 
 /* Store Program Memory Read */
-#define SPM_READY_vect                  _VECTOR(40)
-#define SPM_READY_vect_num              40
+#define SPM_READY_vect            _VECTOR(40)
+#define SPM_READY_vect_num        40
 
 /* Timer/Counter4 Capture Event */
-#define TIMER4_CAPT_vect                _VECTOR(41)
-#define TIMER4_CAPT_vect_num            41
+#define TIMER4_CAPT_vect            _VECTOR(41)
+#define TIMER4_CAPT_vect_num        41
 
 /* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPA_vect               _VECTOR(42)
-#define TIMER4_COMPA_vect_num           42
+#define TIMER4_COMPA_vect            _VECTOR(42)
+#define TIMER4_COMPA_vect_num        42
 
 /* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPB_vect               _VECTOR(43)
-#define TIMER4_COMPB_vect_num           43
+#define TIMER4_COMPB_vect            _VECTOR(43)
+#define TIMER4_COMPB_vect_num        43
 
 /* Timer/Counter4 Compare Match C */
-#define TIMER4_COMPC_vect               _VECTOR(44)
-#define TIMER4_COMPC_vect_num           44
+#define TIMER4_COMPC_vect            _VECTOR(44)
+#define TIMER4_COMPC_vect_num        44
 
 /* Timer/Counter4 Overflow */
-#define TIMER4_OVF_vect                 _VECTOR(45)
-#define TIMER4_OVF_vect_num             45
+#define TIMER4_OVF_vect            _VECTOR(45)
+#define TIMER4_OVF_vect_num        45
 
 /* Timer/Counter5 Capture Event */
-#define TIMER5_CAPT_vect                _VECTOR(46)
-#define TIMER5_CAPT_vect_num            46
+#define TIMER5_CAPT_vect            _VECTOR(46)
+#define TIMER5_CAPT_vect_num        46
 
 /* Timer/Counter5 Compare Match A */
-#define TIMER5_COMPA_vect               _VECTOR(47)
-#define TIMER5_COMPA_vect_num           47
+#define TIMER5_COMPA_vect            _VECTOR(47)
+#define TIMER5_COMPA_vect_num        47
 
 /* Timer/Counter5 Compare Match B */
-#define TIMER5_COMPB_vect               _VECTOR(48)
-#define TIMER5_COMPB_vect_num           48
+#define TIMER5_COMPB_vect            _VECTOR(48)
+#define TIMER5_COMPB_vect_num        48
 
 /* Timer/Counter5 Compare Match C */
-#define TIMER5_COMPC_vect               _VECTOR(49)
-#define TIMER5_COMPC_vect_num           49
+#define TIMER5_COMPC_vect            _VECTOR(49)
+#define TIMER5_COMPC_vect_num        49
 
 /* Timer/Counter5 Overflow */
-#define TIMER5_OVF_vect                 _VECTOR(50)
-#define TIMER5_OVF_vect_num             50
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_51_vect                _VECTOR(51)
-#define RESERVED_51_vect_num            51
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_52_vect                _VECTOR(52)
-#define RESERVED_52_vect_num            52
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_53_vect                _VECTOR(53)
-#define RESERVED_53_vect_num            53
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_54_vect                _VECTOR(54)
-#define RESERVED_54_vect_num            54
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_55_vect                _VECTOR(55)
-#define RESERVED_55_vect_num            55
-
-/* Reserved, vector numbers above has to be kept unchanged */
-#define RESERVED_56_vect                _VECTOR(56)
-#define RESERVED_56_vect_num            56
+#define TIMER5_OVF_vect            _VECTOR(50)
+#define TIMER5_OVF_vect_num        50
 
 /* TRX24 - PLL lock interrupt */
-#define TRX24_PLL_LOCK_vect             _VECTOR(57)
-#define TRX24_PLL_LOCK_vect_num         57
+#define TRX24_PLL_LOCK_vect            _VECTOR(57)
+#define TRX24_PLL_LOCK_vect_num        57
 
 /* TRX24 - PLL unlock interrupt */
-#define TRX24_PLL_UNLOCK_vect           _VECTOR(58)
-#define TRX24_PLL_UNLOCK_vect_num       58
+#define TRX24_PLL_UNLOCK_vect            _VECTOR(58)
+#define TRX24_PLL_UNLOCK_vect_num        58
 
 /* TRX24 - Receive start interrupt */
-#define TRX24_RX_START_vect             _VECTOR(59)
-#define TRX24_RX_START_vect_num         59
+#define TRX24_RX_START_vect            _VECTOR(59)
+#define TRX24_RX_START_vect_num        59
 
 /* TRX24 - RX_END interrupt */
-#define TRX24_RX_END_vect               _VECTOR(60)
-#define TRX24_RX_END_vect_num           60
+#define TRX24_RX_END_vect            _VECTOR(60)
+#define TRX24_RX_END_vect_num        60
 
 /* TRX24 - CCA/ED done interrupt */
-#define TRX24_CCA_ED_DONE_vect          _VECTOR(61)
-#define TRX24_CCA_ED_DONE_vect_num      61
+#define TRX24_CCA_ED_DONE_vect            _VECTOR(61)
+#define TRX24_CCA_ED_DONE_vect_num        61
 
 /* TRX24 - XAH - AMI */
-#define TRX24_XAH_AMI_vect              _VECTOR(62)
-#define TRX24_XAH_AMI_vect_num          62
+#define TRX24_XAH_AMI_vect            _VECTOR(62)
+#define TRX24_XAH_AMI_vect_num        62
 
 /* TRX24 - TX_END interrupt */
-#define TRX24_TX_END_vect               _VECTOR(63)
-#define TRX24_TX_END_vect_num           63
+#define TRX24_TX_END_vect            _VECTOR(63)
+#define TRX24_TX_END_vect_num        63
 
 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
-#define TRX24_AWAKE_vect                _VECTOR(64)
-#define TRX24_AWAKE_vect_num            64
+#define TRX24_AWAKE_vect            _VECTOR(64)
+#define TRX24_AWAKE_vect_num        64
 
 /* Symbol counter - compare match 1 interrupt */
-#define SCNT_CMP1_vect                  _VECTOR(65)
-#define SCNT_CMP1_vect_num              65
+#define SCNT_CMP1_vect            _VECTOR(65)
+#define SCNT_CMP1_vect_num        65
 
 /* Symbol counter - compare match 2 interrupt */
-#define SCNT_CMP2_vect                  _VECTOR(66)
-#define SCNT_CMP2_vect_num              66
+#define SCNT_CMP2_vect            _VECTOR(66)
+#define SCNT_CMP2_vect_num        66
 
 /* Symbol counter - compare match 3 interrupt */
-#define SCNT_CMP3_vect                  _VECTOR(67)
-#define SCNT_CMP3_vect_num              67
+#define SCNT_CMP3_vect            _VECTOR(67)
+#define SCNT_CMP3_vect_num        67
 
 /* Symbol counter - overflow interrupt */
-#define SCNT_OVFL_vect                  _VECTOR(68)
-#define SCNT_OVFL_vect_num              68
+#define SCNT_OVFL_vect            _VECTOR(68)
+#define SCNT_OVFL_vect_num        68
 
 /* Symbol counter - backoff interrupt */
-#define SCNT_BACKOFF_vect               _VECTOR(69)
-#define SCNT_BACKOFF_vect_num           69
+#define SCNT_BACKOFF_vect            _VECTOR(69)
+#define SCNT_BACKOFF_vect_num        69
 
 /* AES engine ready interrupt */
-#define AES_READY_vect                  _VECTOR(70)
-#define AES_READY_vect_num              70
+#define AES_READY_vect            _VECTOR(70)
+#define AES_READY_vect_num        70
 
 /* Battery monitor indicates supply voltage below threshold */
-#define BAT_LOW_vect                    _VECTOR(71)
-#define BAT_LOW_vect_num                71
+#define BAT_LOW_vect            _VECTOR(71)
+#define BAT_LOW_vect_num        71
 
 /* TRX24 TX start interrupt */
-#define TRX24_TX_START_vect             _VECTOR(72)
-#define TRX24_TX_START_vect_num         72
+#define TRX24_TX_START_vect            _VECTOR(72)
+#define TRX24_TX_START_vect_num        72
 
 /* Address match interrupt of address filter 0 */
-#define TRX24_AMI0_vect                 _VECTOR(73)
-#define TRX24_AMI0_vect_num             73
+#define TRX24_AMI0_vect            _VECTOR(73)
+#define TRX24_AMI0_vect_num        73
 
 /* Address match interrupt of address filter 1 */
-#define TRX24_AMI1_vect                 _VECTOR(74)
-#define TRX24_AMI1_vect_num             74
+#define TRX24_AMI1_vect            _VECTOR(74)
+#define TRX24_AMI1_vect_num        74
 
 /* Address match interrupt of address filter 2 */
-#define TRX24_AMI2_vect                 _VECTOR(75)
-#define TRX24_AMI2_vect_num             75
+#define TRX24_AMI2_vect            _VECTOR(75)
+#define TRX24_AMI2_vect_num        75
 
 /* Address match interrupt of address filter 3 */
-#define TRX24_AMI3_vect                 _VECTOR(76)
-#define TRX24_AMI3_vect_num             76
+#define TRX24_AMI3_vect            _VECTOR(76)
+#define TRX24_AMI3_vect_num        76
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 308
+#else
+#  define _VECTORS_SIZE 308U
+#endif
 
 
-/* memory parameters */
+/* Constants */
 
-#define SPM_PAGESIZE                    (256)
-#define RAMSTART                        (0x200)
-#define RAMSIZE                         (0x2000)
-#define RAMEND                          (0x21FF)
-#define XRAMSTART                       (0x0000)
-#define XRAMSIZE                        (0x0000)
-#define XRAMEND                         RAMEND
-#define E2END                           (0x7FF)
-#define E2PAGESIZE                      (0x08)
-#define FLASHEND                        (0xffff)
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 256
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0xFFFF
+#else
+#  define SPM_PAGESIZE 256U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0xFFFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0200
+#  define RAMSIZE      8192
+#  define RAMEND       0x21FF
+#else
+#  define RAMSTART     0x0200U
+#  define RAMSIZE      8192U
+#  define RAMEND       0x21FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      2048
+#  define E2PAGESIZE  8
+#  define E2END       0x07FF
+#else
+#  define E2START     0U
+#  define E2SIZE      2048U
+#  define E2PAGESIZE  8U
+#  define E2END       0x07FFU
+#endif
+#define XRAMEND      RAMEND
 
 
 /* Fuses */
 
 #define FUSE_MEMORY_SIZE 3
 
-/* LFUSE Byte */
-#define FUSE_CKSEL0     ~_BV(0) /* Select Clock Source */
-#define FUSE_CKSEL1     ~_BV(1) /* Select Clock Source */
-#define FUSE_CKSEL2     ~_BV(2) /* Select Clock Source */
-#define FUSE_CKSEL3     ~_BV(3) /* Select Clock Source */
-#define FUSE_SUT0       ~_BV(4) /* Select start-up time */
-#define FUSE_SUT1       ~_BV(5) /* Select start-up time */
-#define FUSE_CKOUT      ~_BV(6) /* Clock output */
-#define FUSE_CKDIV8     ~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* HFUSE Byte */
-#define FUSE_BOOTRST    ~_BV(0) /* Select Reset Vector */
-#define FUSE_BOOTSZ0    ~_BV(1) /* Select Boot Size */
-#define FUSE_BOOTSZ1    ~_BV(2) /* Select Boot Size */
-#define FUSE_EESAVE     ~_BV(3) /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      ~_BV(4) /* Watchdog timer always on */
-#define FUSE_SPIEN      ~_BV(5) /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN     ~_BV(6) /* Enable JTAG */
-#define FUSE_OCDEN      ~_BV(7) /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* EFUSE Byte */
-#define FUSE_BODLEVEL0  ~_BV(0) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  ~_BV(1) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  ~_BV(2) /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
+/* Low Fuse Byte */
+#define FUSE_CKSEL_SUT0  (unsigned char)~_BV(0)
+#define FUSE_CKSEL_SUT1  (unsigned char)~_BV(1)
+#define FUSE_CKSEL_SUT2  (unsigned char)~_BV(2)
+#define FUSE_CKSEL_SUT3  (unsigned char)~_BV(3)
+#define FUSE_CKSEL_SUT4  (unsigned char)~_BV(4)
+#define FUSE_CKSEL_SUT5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_CKSEL_SUT0 & FUSE_CKSEL_SUT2 & FUSE_CKSEL_SUT3 & FUSE_CKSEL_SUT4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BODLEVEL0)
 
 
 
 /* Lock Bits */
-
+#define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST
-#define __LOCK_BITS_EXIST
 
 
 /* Signature */
-
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0xA6
 #define SIGNATURE_2 0x02
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
 
-#endif /* _AVR_IOM64RFR2_H_ */
+
+#endif /* #ifdef _AVR_ATMEGA64RFR2_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom8.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom8.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom8.h 2235 2011-03-17 04:13:14Z arcanum $ */
 
 /* avr/iom8.h - definitions for ATmega8 */
 
@@ -656,12 +656,10 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_ADC (0x01<<4)
 #define SLEEP_MODE_PWR_DOWN (0x02<<4)
 #define SLEEP_MODE_PWR_SAVE (0x03<<4)
 #define SLEEP_MODE_STANDBY (0x06<<4)
 
-
 #endif /* _AVR_IOM8_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom8515.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom8515.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom8515.h 2235 2011-03-17 04:13:14Z arcanum $ */
 
 /* avr/iom8515.h - definitions for ATmega8515 */
 
@@ -677,7 +677,6 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE         0
 #define SLEEP_MODE_PWR_DOWN     1
 #define SLEEP_MODE_PWR_SAVE     2
@@ -685,5 +684,4 @@
 #define SLEEP_MODE_STANDBY      4
 #define SLEEP_MODE_EXT_STANDBY  5
 
-
 #endif /* _AVR_IOM8515_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom8535.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom8535.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom8535.h 2235 2011-03-17 04:13:14Z arcanum $ */
 
 /* avr/iom8535.h - definitions for ATmega8535 */
 
@@ -762,7 +762,6 @@
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_ADC (0x01<<4)
 #define SLEEP_MODE_PWR_DOWN (0x02<<4)
@@ -770,5 +769,4 @@
 #define SLEEP_MODE_STANDBY (0x0A<<4)
 #define SLEEP_MODE_EXT_STANDBY (0x0B<<4)
 
-
 #endif /* _AVR_IOM8535_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom88.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom88.h
@@ -28,12 +28,769 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom88.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 #ifndef _AVR_IOM88_H_
 #define _AVR_IOM88_H_ 1
 
-#include <avr/iomx8.h>
+/* I/O registers */
+
+/* Port B */
+
+#define PINB    _SFR_IO8 (0x03)
+/* PINB */
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8 (0x04)
+/* DDRB */
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8 (0x05)
+/* PORTB */
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+/* Port C */
+
+#define PINC    _SFR_IO8 (0x06)
+/* PINC */
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8 (0x07)
+/* DDRC */
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8 (0x08)
+/* PORTC */
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC3     3
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+/* Port D */
+
+#define PIND    _SFR_IO8 (0x09)
+/* PIND */
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8 (0x0A)
+/* DDRD */
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8 (0x0B)
+/* PORTD */
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+#define TIFR0   _SFR_IO8 (0x15)
+/* TIFR0 */
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8 (0x16)
+/* TIFR1 */
+#define ICF1    5
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8 (0x17)
+/* TIFR2 */
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define PCIFR   _SFR_IO8 (0x1B)
+/* PCIFR */
+#define PCIF2   2
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8 (0x1C)
+/* EIFR */
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8 (0x1D)
+/* EIMSK */
+#define INT1    1
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8 (0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+/* EECT - EEPROM Control Register */
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0X20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0X22)
+/* 
+Even though EEARH is not used by the mega48, the EEAR8 bit in the register
+must be written to 0, according to the datasheet, hence the EEARH register
+must be defined for the mega48.
+*/
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+
+#define GTCCR   _SFR_IO8 (0x23)
+/* GTCCR */
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8 (0x24)
+/* TCCR0A */
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8 (0x25)
+/* TCCR0A */
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8 (0x26)
+#define OCR0A   _SFR_IO8 (0x27)
+#define OCR0B   _SFR_IO8 (0x28)
+
+#define GPIOR1  _SFR_IO8 (0x2A)
+#define GPIOR2  _SFR_IO8 (0x2B)
+
+#define SPCR    _SFR_IO8 (0x2C)
+/* SPCR */
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8 (0x2D)
+/* SPSR */
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8 (0x2E)
+
+#define ACSR    _SFR_IO8 (0x30)
+/* ACSR */
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8 (0x31)
+
+#define SMCR    _SFR_IO8 (0x33)
+/* SMCR */
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8 (0x34)
+/* MCUSR */
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8 (0x35)
+/* MCUCR */
+#define PUD     4
+#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)  || defined (__AVR_ATmega48A__) || defined(__AVR_ATmega48PA__)
+#define IVSEL   1
+#define IVCE    0
+#endif
+
+#define SPMCSR  _SFR_IO8 (0x37)
+/* SPMCSR */
+#define SPMIE     7
+#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || (__AVR_ATmega88P__) || defined (__AVR_ATmega168P__) || (__AVR_ATmega88A__) || defined (__AVR_ATmega168A__) || (__AVR_ATmega88PA__) || defined (__AVR_ATmega168PA__)
+#  define RWWSB   6
+#  define RWWSRE  4
+#endif
+#if defined(__AVR_ATmega48A) || defined(__AVR_ATmega48PA) || defined(__AVR_ATmega88A) || defined(__AVR_ATmega88PA) || defined(__AVR_ATmega168A) || defined(__AVR_ATmega168PA)
+	#define SIGRD 5
+#endif
+#define BLBSET    3
+#define PGWRT     2
+#define PGERS     1
+#define SELFPRGEN 0
+#define SPMEN     0
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+#define WDTCSR  _SFR_MEM8 (0x60)
+/* WDTCSR */
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8 (0x61)
+/* CLKPR */
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define PRR     _SFR_MEM8 (0x64)
+/* PRR */
+#define PRTWI    7
+#define PRTIM2   6
+#define PRTIM0   5
+#define PRTIM1   3
+#define PRSPI    2
+#define PRUSART0 1
+#define PRADC    0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRTWI
+
+#define OSCCAL  _SFR_MEM8 (0x66)
+
+#define PCICR   _SFR_MEM8 (0x68)
+/* PCICR */
+#define PCIE2   2
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8 (0x69)
+/* EICRA */
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define PCMSK0  _SFR_MEM8 (0x6B)
+/* PCMSK0 */
+#define PCINT7    7
+#define PCINT6    6
+#define PCINT5    5
+#define PCINT4    4
+#define PCINT3    3
+#define PCINT2    2
+#define PCINT1    1
+#define PCINT0    0
+
+#define PCMSK1  _SFR_MEM8 (0x6C)
+/* PCMSK1 */
+#define PCINT14   6
+#define PCINT13   5
+#define PCINT12   4
+#define PCINT11   3
+#define PCINT10   2
+#define PCINT9    1
+#define PCINT8    0
+
+#define PCMSK2  _SFR_MEM8 (0x6D)
+/* PCMSK2 */
+#define PCINT23   7
+#define PCINT22   6
+#define PCINT21   5
+#define PCINT20   4
+#define PCINT19   3
+#define PCINT18   2
+#define PCINT17   1
+#define PCINT16   0
+
+#define TIMSK0  _SFR_MEM8 (0x6E)
+/* TIMSK0 */
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8 (0x6F)
+/* TIMSK1 */
+#define ICIE1   5
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8 (0x70)
+/* TIMSK2 */
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16 (0x78)
+#endif
+#define ADCW    _SFR_MEM16 (0x78)
+#define ADCL    _SFR_MEM8 (0x78)
+#define ADCH    _SFR_MEM8 (0x79)
+
+#define ADCSRA  _SFR_MEM8 (0x7A)
+/* ADCSRA */
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8 (0x7B)
+/* ADCSRB */
+#define ACME    6
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8 (0x7C)
+/* ADMUX */
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define DIDR0   _SFR_MEM8 (0x7E)
+/* DIDR0 */
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8 (0x7F)
+/* DIDR1 */
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8 (0x80)
+/* TCCR1A */
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8 (0x81)
+/* TCCR1B */
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8 (0x82)
+/* TCCR1C */
+#define FOC1A   7
+#define FOC1B   6
+
+#define TCNT1   _SFR_MEM16 (0x84)
+#define TCNT1L  _SFR_MEM8 (0x84)
+#define TCNT1H  _SFR_MEM8 (0x85)
+
+#define ICR1    _SFR_MEM16 (0x86)
+#define ICR1L   _SFR_MEM8 (0x86)
+#define ICR1H   _SFR_MEM8 (0x87)
+
+#define OCR1A   _SFR_MEM16 (0x88)
+#define OCR1AL  _SFR_MEM8 (0x88)
+#define OCR1AH  _SFR_MEM8 (0x89)
+
+#define OCR1B   _SFR_MEM16 (0x8A)
+#define OCR1BL  _SFR_MEM8 (0x8A)
+#define OCR1BH  _SFR_MEM8 (0x8B)
+
+#define TCCR2A  _SFR_MEM8 (0xB0)
+/* TCCR2A */
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8 (0xB1)
+/* TCCR2B */
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8 (0xB2)
+#define OCR2A   _SFR_MEM8 (0xB3)
+#define OCR2B   _SFR_MEM8 (0xB4)
+
+#define ASSR    _SFR_MEM8 (0xB6)
+/* ASSR */
+#define EXCLK    6
+#define AS2      5
+#define TCN2UB   4
+#define OCR2AUB  3
+#define OCR2BUB  2
+#define TCR2AUB  1
+#define TCR2BUB  0
+
+#define TWBR    _SFR_MEM8 (0xB8)
+
+#define TWSR    _SFR_MEM8 (0xB9)
+/* TWSR */
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8 (0xBA)
+/* TWAR */
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8 (0xBB)
+
+#define TWCR    _SFR_MEM8 (0xBC)
+/* TWCR */
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8 (0xBD)
+/* TWAMR */
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+#define UCSR0A  _SFR_MEM8 (0xC0)
+/* UCSR0A */
+#define RXC0    7
+#define TXC0    6
+#define UDRE0   5
+#define FE0     4
+#define DOR0    3
+#define UPE0    2
+#define U2X0    1
+#define MPCM0   0
+
+#define UCSR0B  _SFR_MEM8 (0xC1)
+/* UCSR0B */
+#define RXCIE0  7
+#define TXCIE0  6
+#define UDRIE0  5
+#define RXEN0   4
+#define TXEN0   3
+#define UCSZ02  2
+#define RXB80   1
+#define TXB80   0
+
+#define UCSR0C  _SFR_MEM8 (0xC2)
+/* UCSR0C */
+#define UMSEL01  7
+#define UMSEL00  6
+#define UPM01    5
+#define UPM00    4
+#define USBS0    3
+#define UCSZ01   2
+#define UDORD0   2
+#define UCSZ00   1
+#define UCPHA0   1
+#define UCPOL0   0
+
+#define UBRR0   _SFR_MEM16 (0xC4)
+#define UBRR0L  _SFR_MEM8 (0xC4)
+#define UBRR0H  _SFR_MEM8 (0xC5)
+#define UDR0    _SFR_MEM8 (0xC6)
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+#define SIG_INTERRUPT1			_VECTOR(2)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		3
+#define PCINT0_vect			_VECTOR(3)
+#define SIG_PIN_CHANGE0			_VECTOR(3)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num		4
+#define PCINT1_vect			_VECTOR(4)
+#define SIG_PIN_CHANGE1			_VECTOR(4)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT2_vect_num		5
+#define PCINT2_vect			_VECTOR(5)
+#define SIG_PIN_CHANGE2			_VECTOR(5)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		6
+#define WDT_vect			_VECTOR(6)
+#define SIG_WATCHDOG_TIMEOUT		_VECTOR(6)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	7
+#define TIMER2_COMPA_vect		_VECTOR(7)
+#define SIG_OUTPUT_COMPARE2A		_VECTOR(7)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect_num	8
+#define TIMER2_COMPB_vect		_VECTOR(8)
+#define SIG_OUTPUT_COMPARE2B		_VECTOR(8)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		9
+#define TIMER2_OVF_vect			_VECTOR(9)
+#define SIG_OVERFLOW2			_VECTOR(9)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	10
+#define TIMER1_CAPT_vect		_VECTOR(10)
+#define SIG_INPUT_CAPTURE1		_VECTOR(10)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	11
+#define TIMER1_COMPA_vect		_VECTOR(11)
+#define SIG_OUTPUT_COMPARE1A		_VECTOR(11)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	12
+#define TIMER1_COMPB_vect		_VECTOR(12)
+#define SIG_OUTPUT_COMPARE1B		_VECTOR(12)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		13
+#define TIMER1_OVF_vect			_VECTOR(13)
+#define SIG_OVERFLOW1			_VECTOR(13)
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	14
+#define TIMER0_COMPA_vect		_VECTOR(14)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(14)
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	15
+#define TIMER0_COMPB_vect		_VECTOR(15)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(15)
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect_num		16
+#define TIMER0_OVF_vect			_VECTOR(16)
+#define SIG_OVERFLOW0			_VECTOR(16)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		17
+#define SPI_STC_vect			_VECTOR(17)
+#define SIG_SPI				_VECTOR(17)
+
+/* USART Rx Complete */
+#define USART_RX_vect_num		18
+#define USART_RX_vect			_VECTOR(18)
+#define SIG_USART_RECV			_VECTOR(18)
+
+/* USART, Data Register Empty */
+#define USART_UDRE_vect_num		19
+#define USART_UDRE_vect			_VECTOR(19)
+#define SIG_USART_DATA			_VECTOR(19)
+
+/* USART Tx Complete */
+#define USART_TX_vect_num		20
+#define USART_TX_vect			_VECTOR(20)
+#define SIG_USART_TRANS			_VECTOR(20)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		21
+#define ADC_vect			_VECTOR(21)
+#define SIG_ADC				_VECTOR(21)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		22
+#define EE_READY_vect			_VECTOR(22)
+#define SIG_EEPROM_READY		_VECTOR(22)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	23
+#define ANALOG_COMP_vect		_VECTOR(23)
+#define SIG_COMPARATOR			_VECTOR(23)
+
+/* Two-wire Serial Interface */
+#define TWI_vect_num		24
+#define TWI_vect			_VECTOR(24)
+#define SIG_TWI				_VECTOR(24)
+#define SIG_2WIRE_SERIAL		_VECTOR(24)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		25
+#define SPM_READY_vect			_VECTOR(25)
+#define SIG_SPM_READY			_VECTOR(25)
+
+/* The mega48 and mega88 vector tables are single instruction entries (16 bits
+   per entry for an RJMP) while the mega168 table has double instruction
+   entries (32 bits per entry for a JMP). */
+
+#if defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__)
+#  define _VECTORS_SIZE 104
+#else
+#  define _VECTORS_SIZE 52
+#endif
+
+
+/* Deprecated items */
+#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
+
+#pragma GCC system_header
+
+#pragma GCC poison SIG_INTERRUPT0
+#pragma GCC poison SIG_INTERRUPT1
+#pragma GCC poison SIG_PIN_CHANGE0
+#pragma GCC poison SIG_PIN_CHANGE1
+#pragma GCC poison SIG_PIN_CHANGE2
+#pragma GCC poison SIG_WATCHDOG_TIMEOUT
+#pragma GCC poison SIG_OUTPUT_COMPARE2A
+#pragma GCC poison SIG_OUTPUT_COMPARE2B
+#pragma GCC poison SIG_OVERFLOW2
+#pragma GCC poison SIG_INPUT_CAPTURE1
+#pragma GCC poison SIG_OUTPUT_COMPARE1A
+#pragma GCC poison SIG_OUTPUT_COMPARE1B
+#pragma GCC poison SIG_OVERFLOW1
+#pragma GCC poison SIG_OUTPUT_COMPARE0A
+#pragma GCC poison SIG_OUTPUT_COMPARE0B
+#pragma GCC poison SIG_OVERFLOW0
+#pragma GCC poison SIG_SPI
+#pragma GCC poison SIG_USART_RECV
+#pragma GCC poison SIG_USART_DATA
+#pragma GCC poison SIG_USART_TRANS
+#pragma GCC poison SIG_ADC
+#pragma GCC poison SIG_EEPROM_READY
+#pragma GCC poison SIG_COMPARATOR
+#pragma GCC poison SIG_TWI
+#pragma GCC poison SIG_2WIRE_SERIAL
+#pragma GCC poison SIG_SPM_READY
+
+#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
+
+
 
 /* Constants */
 #define SPM_PAGESIZE 64
@@ -88,12 +845,10 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x0A
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 
-
 #endif /* _AVR_IOM88_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom88a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom88a.h
@@ -1,35 +1,35 @@
-/*****************************************************************************
- *
- * Copyright (C) 2011 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-#include "iom88.h"
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+/*****************************************************************************
+ *
+ * Copyright (C) 2011 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+#include "iom88.h"
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom88p.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom88p.h
@@ -29,7 +29,7 @@
   POSSIBILITY OF SUCH DAMAGE. 
 */
 
-/* $Id$ */
+/* $Id: iom88p.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/iom88p.h - definitions for ATmega88P. */
 
@@ -931,7 +931,6 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x0F
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -939,5 +938,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif  /* _AVR_IOM88P_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom88pa.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom88pa.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom88pa.h 2035 2009-11-02 02:44:17Z arcanum $ */
 
 /* avr/iom88pa.h - definitions for ATmega88PA */
 
@@ -1174,7 +1174,6 @@
 #define PCINT18_PIN   PIND
 #define PCINT18_BIT   2
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom88pb.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom88pb.h
@@ -1,899 +1,907 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATMEGA88PB_H_INCLUDED
-#define _AVR_ATMEGA88PB_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom88pb.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDRB7   7
-// Inserted "DDB7" from "DDRB7" due to compatibility
-#define DDB7    7
-#define DDRB6   6
-// Inserted "DDB6" from "DDRB6" due to compatibility
-#define DDB6    6
-#define DDRB5   5
-// Inserted "DDB5" from "DDRB5" due to compatibility
-#define DDB5    5
-#define DDRB4   4
-// Inserted "DDB4" from "DDRB4" due to compatibility
-#define DDB4    4
-#define DDRB3   3
-// Inserted "DDB3" from "DDRB3" due to compatibility
-#define DDB3    3
-#define DDRB2   2
-// Inserted "DDB2" from "DDRB2" due to compatibility
-#define DDB2    2
-#define DDRB1   1
-// Inserted "DDB1" from "DDRB1" due to compatibility
-#define DDB1    1
-#define DDRB0   0
-// Inserted "DDB0" from "DDRB0" due to compatibility
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PORTB7  7
-#define PORTB6  6
-#define PORTB5  5
-#define PORTB4  4
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDRC6   6
-// Inserted "DDC6" from "DDRC6" due to compatibility
-#define DDC6    6
-#define DDRC5   5
-// Inserted "DDC5" from "DDRC5" due to compatibility
-#define DDC5    5
-#define DDRC4   4
-// Inserted "DDC4" from "DDRC4" due to compatibility
-#define DDC4    4
-#define DDRC3   3
-// Inserted "DDC3" from "DDRC3" due to compatibility
-#define DDC3    3
-#define DDRC2   2
-// Inserted "DDC2" from "DDRC2" due to compatibility
-#define DDC2    2
-#define DDRC1   1
-// Inserted "DDC1" from "DDRC1" due to compatibility
-#define DDC1    1
-#define DDRC0   0
-// Inserted "DDC0" from "DDRC0" due to compatibility
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PORTC6  6
-#define PORTC5  5
-#define PORTC4  4
-#define PORTC3  3
-#define PORTC2  2
-#define PORTC1  1
-#define PORTC0  0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDRD7   7
-// Inserted "DDD7" from "DDRD7" due to compatibility
-#define DDD7    7
-#define DDRD6   6
-// Inserted "DDD6" from "DDRD6" due to compatibility
-#define DDD6    6
-#define DDRD5   5
-// Inserted "DDD5" from "DDRD5" due to compatibility
-#define DDD5    5
-#define DDRD4   4
-// Inserted "DDD4" from "DDRD4" due to compatibility
-#define DDD4    4
-#define DDRD3   3
-// Inserted "DDD3" from "DDRD3" due to compatibility
-#define DDD3    3
-#define DDRD2   2
-// Inserted "DDD2" from "DDRD2" due to compatibility
-#define DDD2    2
-#define DDRD1   1
-// Inserted "DDD1" from "DDRD1" due to compatibility
-#define DDD1    1
-#define DDRD0   0
-// Inserted "DDD0" from "DDRD0" due to compatibility
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PORTD7  7
-#define PORTD6  6
-#define PORTD5  5
-#define PORTD4  4
-#define PORTD3  3
-#define PORTD2  2
-#define PORTD1  1
-#define PORTD0  0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDRE3   3
-// Inserted "DDE3" from "DDRE3" due to compatibility
-#define DDE3    3
-#define DDRE2   2
-// Inserted "DDE2" from "DDRE2" due to compatibility
-#define DDE2    2
-#define DDRE1   1
-// Inserted "DDE1" from "DDRE1" due to compatibility
-#define DDE1    1
-#define DDRE0   0
-// Inserted "DDE0" from "DDRE0" due to compatibility
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PORTE3  3
-#define PORTE2  2
-#define PORTE1  1
-#define PORTE0  0
-
-#define ACSRB   _SFR_IO8(0x0F)
-#define ACOE    0
-
-/* Reserved [0x10..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-#define OCF0B   2
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-#define OCF2B   2
-
-/* Reserved [0x18..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-#define PCIF1   1
-#define PCIF2   2
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define INT1    1
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM     7
-#define PSRASY  1
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0
-#define WGM01   1
-#define COM0B0  4
-#define COM0B1  5
-#define COM0A0  6
-#define COM0A1  7
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM02   3
-#define FOC0B   6
-#define FOC0A   7
-
-#define TCNT0   _SFR_IO8(0x26)
-
-#define OCR0A   _SFR_IO8(0x27)
-
-#define OCR0B   _SFR_IO8(0x28)
-
-/* Reserved [0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-/* Reserved [0x31..0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define BODSE   5
-#define BODS    6
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define SIGRD   5
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDE     3
-#define WDCE    4
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0
-#define PRUSART0 1
-#define PRSPI   2
-#define PRTIM1  3
-#define PRTIM0  5
-#define PRTIM2  6
-#define PRTWI   7
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRUSART0
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRTIM1
-#define __AVR_HAVE_PRR_PRTIM0
-#define __AVR_HAVE_PRR_PRTIM2
-#define __AVR_HAVE_PRR_PRTWI
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-#define OSCCAL0 0
-#define OSCCAL1 1
-#define OSCCAL2 2
-#define OSCCAL3 3
-#define OSCCAL4 4
-#define OSCCAL5 5
-#define OSCCAL6 6
-#define OSCCAL7 7
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-#define PCIE1   1
-#define PCIE2   2
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2  _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-#define OCIE0B  2
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-#define OCIE2B  2
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define WGM20   0
-#define WGM21   1
-#define COM2B0  4
-#define COM2B1  5
-#define COM2A0  6
-#define COM2A1  7
-
-#define TCCR2B  _SFR_MEM8(0xB1)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM22   3
-#define FOC2B   6
-#define FOC2A   7
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-#define OCR2B   _SFR_MEM8(0xB4)
-
-/* Reserved [0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB  4
-#define AS2     5
-#define EXCLK   6
-
-/* Reserved [0xB7] */
-
-#define TWBR    _SFR_MEM8(0xB8)
-
-#define TWSR    _SFR_MEM8(0xB9)
-#define TWPS0   0
-#define TWPS1   1
-#define TWS3    3
-#define TWS4    4
-#define TWS5    5
-#define TWS6    6
-#define TWS7    7
-
-#define TWAR    _SFR_MEM8(0xBA)
-#define TWGCE   0
-#define TWA0    1
-#define TWA1    2
-#define TWA2    3
-#define TWA3    4
-#define TWA4    5
-#define TWA5    6
-#define TWA6    7
-
-#define TWDR    _SFR_MEM8(0xBB)
-
-#define TWCR    _SFR_MEM8(0xBC)
-#define TWIE    0
-#define TWEN    2
-#define TWWC    3
-#define TWSTO   4
-#define TWSTA   5
-#define TWEA    6
-#define TWINT   7
-
-#define TWAMR   _SFR_MEM8(0xBD)
-#define TWAM0   1
-#define TWAM1   2
-#define TWAM2   3
-#define TWAM3   4
-#define TWAM4   5
-#define TWAM5   6
-#define TWAM6   7
-
-/* Reserved [0xBE..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0xC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UCSR0D  _SFR_MEM8(0xC3)
-#define SFDE    5
-#define RXS     6
-#define RXSIE   7
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0xC6)
-
-/* Reserved [0xC7..0xEF] */
-
-#define DEVID0  _SFR_MEM8(0xF0)
-
-#define DEVID1  _SFR_MEM8(0xF1)
-
-#define DEVID2  _SFR_MEM8(0xF2)
-
-#define DEVID3  _SFR_MEM8(0xF3)
-
-#define DEVID4  _SFR_MEM8(0xF4)
-
-#define DEVID5  _SFR_MEM8(0xF5)
-
-#define DEVID6  _SFR_MEM8(0xF6)
-
-#define DEVID7  _SFR_MEM8(0xF7)
-
-#define DEVID8  _SFR_MEM8(0xF8)
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* External Interrupt Request 1 */
-#define INT1_vect            _VECTOR(2)
-#define INT1_vect_num        2
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(3)
-#define PCINT0_vect_num        3
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT1_vect            _VECTOR(4)
-#define PCINT1_vect_num        4
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT2_vect            _VECTOR(5)
-#define PCINT2_vect_num        5
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect            _VECTOR(6)
-#define WDT_vect_num        6
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect            _VECTOR(7)
-#define TIMER2_COMPA_vect_num        7
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect            _VECTOR(8)
-#define TIMER2_COMPB_vect_num        8
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect            _VECTOR(9)
-#define TIMER2_OVF_vect_num        9
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(10)
-#define TIMER1_CAPT_vect_num        10
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect            _VECTOR(11)
-#define TIMER1_COMPA_vect_num        11
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect            _VECTOR(12)
-#define TIMER1_COMPB_vect_num        12
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(13)
-#define TIMER1_OVF_vect_num        13
-
-/* TimerCounter0 Compare Match A */
-#define TIMER0_COMPA_vect            _VECTOR(14)
-#define TIMER0_COMPA_vect_num        14
-
-/* TimerCounter0 Compare Match B */
-#define TIMER0_COMPB_vect            _VECTOR(15)
-#define TIMER0_COMPB_vect_num        15
-
-/* Timer/Couner0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(16)
-#define TIMER0_OVF_vect_num        16
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect            _VECTOR(17)
-#define SPI_STC_vect_num        17
-
-/* USART Rx Complete */
-#define USART_RX_vect            _VECTOR(18)
-#define USART_RX_vect_num        18
-
-/* USART, Data Register Empty */
-#define USART_UDRE_vect            _VECTOR(19)
-#define USART_UDRE_vect_num        19
-
-/* USART Tx Complete */
-#define USART_TX_vect            _VECTOR(20)
-#define USART_TX_vect_num        20
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(21)
-#define ADC_vect_num        21
-
-/* EEPROM Ready */
-#define EE_READY_vect            _VECTOR(22)
-#define EE_READY_vect_num        22
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect            _VECTOR(23)
-#define ANALOG_COMP_vect_num        23
-
-/* Two-wire Serial Interface */
-#define TWI_vect            _VECTOR(24)
-#define TWI_vect_num        24
-
-/* Store Program Memory Read */
-#define SPM_Ready_vect            _VECTOR(25)
-#define SPM_Ready_vect_num        25
-
-/* USART Start Edge Interrupt */
-#define USART_START_vect            _VECTOR(26)
-#define USART_START_vect_num        26
-
-#define _VECTORS_SIZE 54
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      1024
-#define RAMEND       0x04FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x16
-
-
-#endif /* #ifdef _AVR_ATMEGA88PB_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATMEGA88PB_H_INCLUDED
+#define _AVR_ATMEGA88PB_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iom88pb.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
+#define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
+#define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
+#define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE3   3
+// Inserted "DDE3" from "DDRE3" due to compatibility
+#define DDE3    3
+#define DDRE2   2
+// Inserted "DDE2" from "DDRE2" due to compatibility
+#define DDE2    2
+#define DDRE1   1
+// Inserted "DDE1" from "DDRE1" due to compatibility
+#define DDE1    1
+#define DDRE0   0
+// Inserted "DDE0" from "DDRE0" due to compatibility
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+/* Reserved [0x0F..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIFR2   _SFR_IO8(0x17)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+
+/* Reserved [0x18..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM     7
+#define PSRASY  1
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define ACSRB   _SFR_IO8(0x2F)
+#define ACOE    0
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+/* Reserved [0x31..0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+#define BODSE   5
+#define BODS    6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+/* Reserved [0x62..0x63] */
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRTIM0  5
+#define PRTIM2  6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+#define OSCCAL0 0
+#define OSCCAL1 1
+#define OSCCAL2 2
+#define OSCCAL3 3
+#define OSCCAL4 4
+#define OSCCAL5 5
+#define OSCCAL6 6
+#define OSCCAL7 7
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+
+/* Reserved [0x71..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN0D   0
+#define AIN1D   1
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xAF] */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB  4
+#define AS2     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWPS0   0
+#define TWPS1   1
+#define TWS3    3
+#define TWS4    4
+#define TWS5    5
+#define TWS6    6
+#define TWS7    7
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWGCE   0
+#define TWA0    1
+#define TWA1    2
+#define TWA2    3
+#define TWA3    4
+#define TWA4    5
+#define TWA5    6
+#define TWA6    7
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWIE    0
+#define TWEN    2
+#define TWWC    3
+#define TWSTO   4
+#define TWSTA   5
+#define TWEA    6
+#define TWINT   7
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM0   1
+#define TWAM1   2
+#define TWAM2   3
+#define TWAM3   4
+#define TWAM4   5
+#define TWAM5   6
+#define TWAM6   7
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSR0A  _SFR_MEM8(0xC0)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+#define UCSR0B  _SFR_MEM8(0xC1)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0C  _SFR_MEM8(0xC2)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+#define UCSR0D  _SFR_MEM8(0xC3)
+#define SFDE    5
+#define RXS     6
+#define RXSIE   7
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0xC4)
+
+#define UBRR0L  _SFR_MEM8(0xC4)
+#define UBRR0H  _SFR_MEM8(0xC5)
+
+#define UDR0    _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7..0xEF] */
+
+#define DEVID0  _SFR_MEM8(0xF0)
+
+#define DEVID1  _SFR_MEM8(0xF1)
+
+#define DEVID2  _SFR_MEM8(0xF2)
+
+#define DEVID3  _SFR_MEM8(0xF3)
+
+#define DEVID4  _SFR_MEM8(0xF4)
+
+#define DEVID5  _SFR_MEM8(0xF5)
+
+#define DEVID6  _SFR_MEM8(0xF6)
+
+#define DEVID7  _SFR_MEM8(0xF7)
+
+#define DEVID8  _SFR_MEM8(0xF8)
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT2_vect            _VECTOR(5)
+#define PCINT2_vect_num        5
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(6)
+#define WDT_vect_num        6
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(7)
+#define TIMER2_COMPA_vect_num        7
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect            _VECTOR(8)
+#define TIMER2_COMPB_vect_num        8
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(9)
+#define TIMER2_OVF_vect_num        9
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(10)
+#define TIMER1_CAPT_vect_num        10
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(11)
+#define TIMER1_COMPA_vect_num        11
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(12)
+#define TIMER1_COMPB_vect_num        12
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(13)
+#define TIMER1_OVF_vect_num        13
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(14)
+#define TIMER0_COMPA_vect_num        14
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(15)
+#define TIMER0_COMPB_vect_num        15
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(16)
+#define TIMER0_OVF_vect_num        16
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(17)
+#define SPI_STC_vect_num        17
+
+/* USART Rx Complete */
+#define USART_RX_vect            _VECTOR(18)
+#define USART_RX_vect_num        18
+
+/* USART, Data Register Empty */
+#define USART_UDRE_vect            _VECTOR(19)
+#define USART_UDRE_vect_num        19
+
+/* USART Tx Complete */
+#define USART_TX_vect            _VECTOR(20)
+#define USART_TX_vect_num        20
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(21)
+#define ADC_vect_num        21
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(22)
+#define EE_READY_vect_num        22
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect            _VECTOR(23)
+#define ANALOG_COMP_vect_num        23
+
+/* Two-wire Serial Interface */
+#define TWI_vect            _VECTOR(24)
+#define TWI_vect_num        24
+
+/* Store Program Memory Read */
+#define SPM_Ready_vect            _VECTOR(25)
+#define SPM_Ready_vect_num        25
+
+/* USART Start Edge Interrupt */
+#define USART_START_vect            _VECTOR(26)
+#define USART_START_vect_num        26
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 54
+#else
+#  define _VECTORS_SIZE 54U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      1024
+#  define RAMEND       0x04FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x04FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x16
+
+
+
+
+#endif /* #ifdef _AVR_ATMEGA88PB_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom8a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom8a.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATMEGA8A_H_INCLUDED
 #define _AVR_ATMEGA8A_H_INCLUDED
 
@@ -164,13 +147,29 @@
 
 #define DDRD    _SFR_IO8(0x11)
 #define DDRD7   7
+// Inserted "DDD7" from "DDRD7" due to compatibility
+#define DDD7    7
 #define DDRD6   6
+// Inserted "DDD6" from "DDRD6" due to compatibility
+#define DDD6    6
 #define DDRD5   5
+// Inserted "DDD5" from "DDRD5" due to compatibility
+#define DDD5    5
 #define DDRD4   4
+// Inserted "DDD4" from "DDRD4" due to compatibility
+#define DDD4    4
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x12)
 #define PORTD7  7
@@ -193,12 +192,26 @@
 
 #define DDRC    _SFR_IO8(0x14)
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x15)
 #define PORTC6  6
@@ -221,13 +234,29 @@
 
 #define DDRB    _SFR_IO8(0x17)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x18)
 #define PORTB7  7
@@ -431,6 +460,15 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<4)
+#define SLEEP_MODE_ADC (0x01<<4)
+#define SLEEP_MODE_PWR_DOWN (0x02<<4)
+#define SLEEP_MODE_PWR_SAVE (0x03<<4)
+#define SLEEP_MODE_STANDBY (0x06<<4)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -505,21 +543,44 @@
 #define SPM_RDY_vect            _VECTOR(18)
 #define SPM_RDY_vect_num        18
 
-#define _VECTORS_SIZE 38
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 38
+#else
+#  define _VECTORS_SIZE 38U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFF
-#define RAMSTART     0x0060
-#define RAMSIZE      1024
-#define RAMEND       0x045F
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0060
+#  define RAMSIZE      1024
+#  define RAMEND       0x045F
+#else
+#  define RAMSTART     0x0060U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x045FU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -536,6 +597,8 @@
 #define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
 #define FUSE_BODEN       (unsigned char)~_BV(6)
 #define FUSE_BODLEVEL    (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4)
+
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -544,8 +607,10 @@
 #define FUSE_EESAVE      (unsigned char)~_BV(3)
 #define FUSE_CKOPT       (unsigned char)~_BV(4)
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_WTDON       (unsigned char)~_BV(6)
+#define FUSE_WDTON       (unsigned char)~_BV(6)
 #define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
+
 
 
 /* Lock Bits */
@@ -561,11 +626,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<4)
-#define SLEEP_MODE_ADC (0x01<<4)
-#define SLEEP_MODE_PWR_DOWN (0x02<<4)
-#define SLEEP_MODE_PWR_SAVE (0x03<<4)
-#define SLEEP_MODE_STANDBY (0x06<<4)
 
 #endif /* #ifdef _AVR_ATMEGA8A_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom8hva.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom8hva.h
@@ -28,14 +28,507 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom8hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* iom8hva.h - definitions for ATmega8HVA.  */
 
 #ifndef _AVR_IOM8HVA_H_
 #define _AVR_IOM8HVA_H_ 1
 
-#include <avr/iomxxhva.h>
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PA1     1
+#define PA0     0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC0   0
+
+/* Reserved [0x7] */
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC0     0
+
+/* Reserved [0x9..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define ICF0    3
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define OSICSR  _SFR_IO8(0x17)
+#define OSISEL0 4
+#define OSIST   1
+#define OSIEN   0
+
+/* Reserved [0x18..0x1B] */
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO8(0x21)
+#define EEARL   _SFR_IO8(0x21)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+/* Reserved [0x22] */
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define TCW0    7
+#define ICEN0   6
+#define ICNC0   5
+#define ICES0   4
+#define ICS0    3
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO16(0X26)
+#define TCNT0L  _SFR_IO8(0X26)
+#define TCNT0H  _SFR_IO8(0X27)
+
+#define OCR0A   _SFR_IO8(0x28)
+
+#define OCR0B   _SFR_IO8(0X29)
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F..0x30] */
+
+#define DWDR    _SFR_IO8(0x31)
+#define IDRD    7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define OCDRF   4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define CKOE    5
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SIGRD   5
+#define CTPB    4
+#define RFLB    3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRVRM   5
+#define PRSPI   3
+#define PRTIM1  2
+#define PRTIM0  1
+#define PRVADC  0
+
+#define __AVR_HAVE_PRR0	((1<<PRVADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRVRM))
+#define __AVR_HAVE_PRR0_PRVADC
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRVRM
+
+/* Reserved [0x65] */
+
+#define FOSCCAL _SFR_MEM8(0x66)
+
+/* Reserved [0x67..0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+/* Reserved [0x6A..0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define ICIE0   3
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+/* Reserved [0x70..0x77] */
+
+#define VADC	_SFR_MEM16(0x78)
+#define VADCL	_SFR_MEM8(0x78)
+#define VADCH	_SFR_MEM8(0x79)
+
+#define VADCSR	_SFR_MEM8(0x7A)
+#define VADEN   3
+#define VADSC   2
+#define VADCCIF 1
+#define VADCCIE 0
+
+/* Reserved [0x7B] */
+
+#define VADMUX	_SFR_MEM8(0x7C)
+#define VADMUX3 3
+#define VADMUX2 2
+#define VADMUX1 1
+#define VADMUX0 0
+
+/* Reserved [0x7D] */
+
+#define DIDR0	_SFR_MEM8(0x7E)
+#define PA1DID  1
+#define PA0DID  0
+
+/* Reserved [0x7F] */
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define TCW1    7
+#define ICEN1   6
+#define ICNC1   5
+#define ICES1   4
+#define ICS1    3
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+/* Reserved [0x82..0x83] */
+
+#define TCNT1   _SFR_MEM16(0x84)
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Reserved [0x86..0x87] */
+
+#define OCR1A   _SFR_MEM8(0x88)
+
+#define OCR1B   _SFR_MEM8(0x89)
+
+/* Reserved [0x8A..0xC7] */
+
+#define ROCR    _SFR_MEM8(0xC8)
+#define ROCS    7
+#define ROCWIF  1
+#define ROCWIE  0
+
+/* Reserved [0xC9..0xCF] */
+
+#define BGCCR   _SFR_MEM8(0xD0)
+#define BGD     7
+#define BGCC5   5
+#define BGCC4   4
+#define BGCC3   3
+#define BGCC2   2
+#define BGCC1   1
+#define BGCC0   0
+
+#define BGCRR   _SFR_MEM8(0xD1)
+#define BGCR7   7
+#define BGCR6   6
+#define BGCR5   5
+#define BGCR4   4
+#define BGCR3   3
+#define BGCR2   2
+#define BGCR1   1
+#define BGCR0   0
+
+/* Reserved [0xD2..0xDF] */
+
+/* CC-ADC Accumulate Current */
+/* TODO: Add _SFR_MEM32 */
+/* #define CADAC   _SFR_MEM32(0xE0) */
+#define CADAC0  _SFR_MEM8(0xE0)
+#define CADAC1  _SFR_MEM8(0xE1)
+#define CADAC2  _SFR_MEM8(0xE2)
+#define CADAC3  _SFR_MEM8(0xE3)
+
+#define CADCSRA _SFR_MEM8(0xE4)
+#define CADEN   7
+#define CADPOL  6
+#define CADUB   5
+#define CADAS1  4
+#define CADAS0  3
+#define CADSI1  2
+#define CADSI0  1
+#define CADSE   0
+
+#define CADCSRB _SFR_MEM8(0xE5)
+#define CADACIE 6
+#define CADRCIE 5
+#define CADICIE 4
+#define CADACIF 2
+#define CADRCIF 1
+#define CADICIF 0
+
+#define CADRC   _SFR_MEM8(0xE6)
+
+/* Reserved [0xE7] */
+
+#define CADIC   _SFR_MEM16(0xE8)
+#define CADICL  _SFR_MEM8(0xE8)
+#define CADICH  _SFR_MEM8(0xE9)
+
+/* Reserved [0xEA..0xEF] */
+
+#define FCSR    _SFR_MEM8(0xF0)
+#define DUVRD   3
+#define CPS     2
+#define DFE     1
+#define CFE     0
+
+/* Reserved [0xF1] */
+
+#define BPIMSK  _SFR_MEM8(0xF2)
+#define SCIE    4
+#define DOCIE   3
+#define COCIE   2
+#define DHCIE   1
+#define CHCIE   0
+
+#define BPIFR   _SFR_MEM8(0xF3)
+#define SCIF    4
+#define DOCIF   3
+#define COCIF   2
+#define DHCIF   1
+#define CHCIF   0
+
+/* Reserved [0xF4] */
+
+#define BPSCD   _SFR_MEM8(0xF5)
+
+#define BPDOCD  _SFR_MEM8(0xF6)
+
+#define BPCOCD  _SFR_MEM8(0xF7)
+
+#define BPDHCD  _SFR_MEM8(0xF8)
+
+#define BPCHCD  _SFR_MEM8(0xF9)
+
+#define BPSCTR  _SFR_MEM8(0xFA)
+
+#define BPOCTR  _SFR_MEM8(0xFB)
+
+#define BPHCTR  _SFR_MEM8(0xFC)
+
+#define BPCR    _SFR_MEM8(0xFD)
+#define SCD     4
+#define DOCD    3
+#define COCD    2
+#define DHCD    1
+#define CHCD    0
+
+#define BPPLR   _SFR_MEM8(0xFE)
+#define BPPLE   1
+#define BPPL    0
+
+/* Reserved [0xFF] */
+
+/* Interrupt vectors */
+/* Battery Protection Interrupt */
+#define BPINT_vect_num		1
+#define BPINT_vect			_VECTOR(1)
+
+/* Voltage Regulator Monitor Interrupt */
+#define VREGMON_vect_num		2
+#define VREGMON_vect			_VECTOR(2)
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		3
+#define INT0_vect			_VECTOR(3)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		4
+#define INT1_vect			_VECTOR(4)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		5
+#define INT2_vect			_VECTOR(5)
+
+/* Watchdog Timeout Interrupt */
+#define WDT_vect_num		6
+#define WDT_vect			_VECTOR(6)
+
+/* Timer/Counter 1 Input Capture */
+#define TIMER1_IC_vect_num		7
+#define TIMER1_IC_vect			_VECTOR(7)
+
+/* Timer/Counter 1 Compare A Match */
+#define TIMER1_COMPA_vect_num	8
+#define TIMER1_COMPA_vect		_VECTOR(8)
+
+/* Timer/Counter 1 Compare B Match */
+#define TIMER1_COMPB_vect_num	9
+#define TIMER1_COMPB_vect		_VECTOR(9)
+
+/* Timer/Counter 1 Overflow */
+#define TIMER1_OVF_vect_num		10
+#define TIMER1_OVF_vect			_VECTOR(10)
+
+/* Timer/Counter 0 Input Capture */
+#define TIMER0_IC_vect_num		11
+#define TIMER0_IC_vect			_VECTOR(11)
+
+/* Timer/Counter0 Compare A Match */
+#define TIMER0_COMPA_vect_num	12
+#define TIMER0_COMPA_vect		_VECTOR(12)
+
+/* Timer/Counter0 Compare B Match */
+#define TIMER0_COMPB_vect_num	13
+#define TIMER0_COMPB_vect		_VECTOR(13)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		14
+#define TIMER0_OVF_vect			_VECTOR(14)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		15
+#define SPI_STC_vect			_VECTOR(15)
+
+/* Voltage ADC Conversion Complete */
+#define VADC_vect_num		16
+#define VADC_vect			_VECTOR(16)
+
+/* Coulomb Counter ADC Conversion Complete */
+#define CCADC_CONV_vect_num		17
+#define CCADC_CONV_vect			_VECTOR(17)
+
+/* Coloumb Counter ADC Regular Current */
+#define CCADC_REG_CUR_vect_num	18
+#define CCADC_REG_CUR_vect		_VECTOR(18)
+
+/* Coloumb Counter ADC Accumulator */
+#define CCADC_ACC_vect_num		19
+#define CCADC_ACC_vect			_VECTOR(19)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		20
+#define EE_READY_vect			_VECTOR(20)
+
+#define _VECTORS_SIZE 42
 
 /* Constants */
 #define SPM_PAGESIZE 128
@@ -67,7 +560,6 @@
 #define __LOCK_BITS_EXIST
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iom8u2.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iom8u2.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iom8u2.h 2245 2011-05-12 22:42:21Z arcanum $ */
 
 /* avr/iom8u2.h - definitions for ATmega8U2 */
 
@@ -987,8 +987,6 @@
 #define SIGNATURE_2 0x89
 
 
-/* Device Pin Definitions */
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn10.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn10.h
@@ -503,7 +503,6 @@
 #define PB3_PIN   PINRESET
 #define PB3_BIT   RESET
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn11.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn11.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn11.h 2236 2011-03-17 21:53:39Z arcanum $ */
 
 /* avr/iotn11.h - definitions for ATtiny10/11 */
 
@@ -249,9 +249,7 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_PWR_DOWN (0x01<<4)
 
-
 #endif /* _AVR_IOTN11_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn12.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn12.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn12.h 2236 2011-03-17 21:53:39Z arcanum $ */
 
 /* avr/iotn12.h - definitions for ATtiny12 */
 
@@ -282,9 +282,7 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_PWR_DOWN (0x01<<4)
 
-
 #endif /* _AVR_IOTN12_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn13.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn13.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn13.h 2236 2011-03-17 21:53:39Z arcanum $ */
 
 /* avr/iotn13.h - definitions for ATtiny13 */
 
@@ -388,10 +388,8 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 
-
 #endif /* _AVR_IOTN13_H_*/
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn13a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn13a.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn13a.h 1955 2009-04-28 08:51:16Z arcanum $ */
 
 /* avr/iotn13a.h - definitions for ATtiny13 */
 
@@ -386,7 +386,6 @@
 #define SIGNATURE_2 0x07
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn15.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn15.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn15.h 2236 2011-03-17 21:53:39Z arcanum $ */
 
 /* avr/iotn15.h - definitions for ATtiny15 */
 
@@ -356,10 +356,8 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 
-
 #endif /* _AVR_IOTN15_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn1634.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn1634.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATTINY1634_H_INCLUDED
 #define _AVR_ATTINY1634_H_INCLUDED
 
@@ -116,11 +99,23 @@
 
 #define DDRC    _SFR_IO8(0x08)
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x09)
 #define PORTC5  5
@@ -146,9 +141,17 @@
 
 #define DDRB    _SFR_IO8(0x0C)
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x0D)
 #define PORTB3  3
@@ -174,13 +177,29 @@
 
 #define DDRA    _SFR_IO8(0x10)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x11)
 #define PORTA7  7
@@ -617,6 +636,14 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<5)
+#define SLEEP_MODE_ADC (0x01<<5)
+#define SLEEP_MODE_PWR_DOWN (0x02<<5)
+#define SLEEP_MODE_STANDBY (0x03<<5)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -803,21 +830,44 @@
 #define QTRIP_vect            _VECTOR(27)
 #define QTRIP_vect_num        27
 
-#define _VECTORS_SIZE 112
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 112
+#else
+#  define _VECTORS_SIZE 112U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 32
-#define FLASHSTART   0x0000
-#define FLASHEND     0x3FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      1024
-#define RAMEND       0x04FF
-#define E2START     0
-#define E2SIZE      256
-#define E2PAGESIZE  4
-#define E2END       0x00FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 32
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x3FFF
+#else
+#  define SPM_PAGESIZE 32U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x3FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      1024
+#  define RAMEND       0x04FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      1024U
+#  define RAMEND       0x04FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      256
+#  define E2PAGESIZE  4
+#  define E2END       0x00FF
+#else
+#  define E2START     0U
+#  define E2SIZE      256U
+#  define E2PAGESIZE  4U
+#  define E2END       0x00FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -833,6 +883,8 @@
 #define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
@@ -843,6 +895,8 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_DWEN        (unsigned char)~_BV(6)
 #define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
@@ -850,6 +904,8 @@
 #define FUSE_BODACT1     (unsigned char)~_BV(2)
 #define FUSE_BODPD0      (unsigned char)~_BV(3)
 #define FUSE_BODPD1      (unsigned char)~_BV(4)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -863,10 +919,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<5)
-#define SLEEP_MODE_ADC (0x01<<5)
-#define SLEEP_MODE_PWR_DOWN (0x02<<5)
-#define SLEEP_MODE_STANDBY (0x03<<5)
 
 #endif /* #ifdef _AVR_ATTINY1634_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn167.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn167.h
@@ -29,7 +29,7 @@
   POSSIBILITY OF SUCH DAMAGE. 
 */
 
-/* $Id$ */
+/* $Id: iotn167.h 2253 2011-09-26 14:53:41Z arcanum $ */
 
 /* avr/iotn167.h - definitions for ATtiny167. */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn20.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn20.h
@@ -767,7 +767,6 @@
 #define PCINT5_PIN   PINADC
 #define PCINT5_BIT   ADC5
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn22.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn22.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn22.h 2236 2011-03-17 21:53:39Z arcanum $ */
 
 /* avr/iotn22.h - definitions for ATtiny22 */
 
@@ -215,9 +215,7 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_PWR_DOWN (0x01<<4)
 
-
 #endif /* _AVR_IOTN22_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn2313.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn2313.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn2313.h 2236 2011-03-17 21:53:39Z arcanum $ */
 
 /* iotn2313.h derived from io2313.h by Bob Paddock.
 
@@ -699,5 +699,4 @@
 #define SLEEP_MODE_STANDBY (0x04<<4)
 #define SLEEP_MODE_PWR_DOWN (0x05<<4)
 
-
 #endif  /* _AVR_IOTN2313_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn2313a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn2313a.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn2313a.h 2412 2014-03-20 11:21:20Z pitchumani $ */
 
 /* avr/iotn2313a.h - definitions for ATtiny2313A */
 
@@ -42,7 +42,7 @@
 #  define _AVR_IOXXX_H_ "iotn2313a.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATtiny2313A_H_
@@ -316,6 +316,7 @@
 #define EEDR7 7
 
 #define EEAR _SFR_IO8(0x01E)
+#define EEARL _SFR_IO8(0x01E)
 #define EEAR0 0
 #define EEAR1 1
 #define EEAR2 2
@@ -804,7 +805,6 @@
 #define SCL_PIN   PINB
 #define SCL_BIT   7
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_STANDBY (0x04<<4)
 #define SLEEP_MODE_PWR_DOWN (0x05<<4)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn24.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn24.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005, Anatoly Sokolov
+/* Copyright (c) 2005, 2007 Anatoly Sokolov
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,14 +28,457 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn24.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 /* avr/iotn24.h - definitions for ATtiny24 */
 
 #ifndef _AVR_IOTN24_H_
 #define _AVR_IOTN24_H_ 1
 
-#include <avr/iotnx4.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx4.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* I/O registers */
+
+#define PRR     _SFR_IO8 (0x00)
+#define PRTIM1  3
+#define PRTIM0  2
+#define PRUSI   1
+#define PRADC   0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define DIDR0    _SFR_IO8(0x01)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1 
+#define ADC0D   0
+
+/* Reserved [0x02] */
+
+#define ADCSRB  _SFR_IO8 (0x03)
+#define BIN     7
+#define ACME    6
+#define ADLAR   4
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+#define ADCW    _SFR_IO16(0x04)
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8 (0x06)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADMUX   _SFR_IO8(0x07)
+#define REFS1   7
+#define REFS0   6
+#define MUX5    5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define ACSR    _SFR_IO8(0x08)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+/* Reserved [0x09..0x0A] */
+
+#define TIFR1   _SFR_IO8(0x0B)
+#define ICF1    5
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIMSK1   _SFR_IO8(0x0C)
+#define ICIE1   5
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define USICR   _SFR_IO8(0x0D)
+#define USISIE  7
+#define USIOIE  6
+#define USIWM1  5
+#define USIWM0  4
+#define USICS1  3
+#define USICS0  2
+#define USICLK  1
+#define USITC   0
+
+#define USISR   _SFR_IO8(0x0E)
+#define USISIF  7 
+#define USIOIF  6
+#define USIPF   5
+#define USIDC   4
+#define USICNT3 3
+#define USICNT2 2
+#define USICNT1 1
+#define USICNT0 0
+
+#define USIDR   _SFR_IO8(0x0F)
+
+#define USIBR   _SFR_IO8(0x10)
+
+/* Reserved [0x11] */
+
+#define PCMSK0  _SFR_IO8(0x12)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define GPIOR0  _SFR_IO8(0x13)
+
+#define GPIOR1  _SFR_IO8(0x14)
+
+#define GPIOR2  _SFR_IO8(0x15)
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PA7     7
+#define PA6     6
+#define PA5     5
+#define PA4     4
+#define PA3     3
+#define PA2     2
+#define PA1     1
+#define PA0     0
+
+/* EEPROM Control Register EECR */
+#define EECR	_SFR_IO8(0x1C)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define PCMSK1  _SFR_IO8(0x20)
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+#define WDTCSR _SFR_IO8(0x21)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define TCCR1C  _SFR_IO8(0x22)
+#define FOC1A   7
+#define FOC1B   6
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSR10   0
+
+#define ICR1    _SFR_IO16(0x24)
+#define ICR1L   _SFR_IO8(0x24)
+#define ICR1H   _SFR_IO8(0x25)
+
+#define CLKPR   _SFR_IO8(0x26)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define DWDR    _SFR_IO8(0x27)
+
+#define OCR1B   _SFR_IO16(0x28)
+#define OCR1BL  _SFR_IO8(0x28)
+#define OCR1BH  _SFR_IO8(0x29)
+
+#define OCR1A   _SFR_IO16(0x2A)
+#define OCR1AL  _SFR_IO8(0x2A)
+#define OCR1AH  _SFR_IO8(0x2B)
+
+/* keep misspelled names from avr-libc 1.4.[0..1] for compatibility */
+#define OCRB1   _SFR_IO16(0x28)
+#define OCRB1L  _SFR_IO8(0x28)
+#define OCRB1H  _SFR_IO8(0x29)
+
+#define OCRA1   _SFR_IO16(0x2A)
+#define OCRA1L  _SFR_IO8(0x2A)
+#define OCRA1H  _SFR_IO8(0x2B)
+
+#define TCNT1   _SFR_IO16(0x2C)
+#define TCNT1L  _SFR_IO8(0x2C)
+#define TCNT1H  _SFR_IO8(0x2D)
+
+#define TCCR1B  _SFR_IO8(0x2E)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1A  _SFR_IO8(0x2F)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR0A  _SFR_IO8(0x30)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define BODS    7
+#define PUD     6
+#define SE      5
+#define SM1     4
+#define SM0     3
+#define BODSE   2
+#define ISC01   1
+#define ISC00   0
+
+#define OCR0A   _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define RSIG    5
+#define CTPB    4
+#define RFLB    3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+#define TIFR0   _SFR_IO8(0x38)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIMSK0  _SFR_IO8(0x39)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define GIFR    _SFR_IO8(0x3A)
+#define INTF0   6
+#define PCIF1   5
+#define PCIF0   4
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define INT0    6
+#define PCIE1   5
+#define PCIE0   4
+
+#define OCR0B   _SFR_IO8(0x3C)
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+///---
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt Request 0 */
+#define INT0_vect_num		    1
+#define INT0_vect			    _VECTOR(1)
+#define EXT_INT0_vect_num    	1
+#define EXT_INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		    2
+#define PCINT0_vect			    _VECTOR(2)
+#define SIG_PIN_CHANGE0			_VECTOR(2)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		    3
+#define PCINT1_vect			    _VECTOR(3)
+#define SIG_PIN_CHANGE1			_VECTOR(3)
+
+/* Watchdog Time-out */
+#define WDT_vect_num			4
+#define WDT_vect			    _VECTOR(4)
+#define WATCHDOG_vect_num		4
+#define WATCHDOG_vect			_VECTOR(4)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(4)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	5
+#define TIMER1_CAPT_vect		_VECTOR(5)
+#define TIM1_CAPT_vect_num		5
+#define TIM1_CAPT_vect			_VECTOR(5)
+#define SIG_INPUT_CAPTURE1		_VECTOR(5)
+
+/* Timer/Counter1 Compare Match A */
+#define TIM1_COMPA_vect_num		6
+#define TIM1_COMPA_vect			_VECTOR(6)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(6)
+
+/* Timer/Counter1 Compare Match B */
+#define TIM1_COMPB_vect_num		7
+#define TIM1_COMPB_vect			_VECTOR(7)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(7)
+
+/* Timer/Counter1 Overflow */
+#define TIM1_OVF_vect_num		8
+#define TIM1_OVF_vect			_VECTOR(8)
+#define SIG_OVERFLOW1			_VECTOR(8)
+
+/* Timer/Counter0 Compare Match A */
+#define TIM0_COMPA_vect_num		9
+#define TIM0_COMPA_vect			_VECTOR(9)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(9)
+
+/* Timer/Counter0 Compare Match B */
+#define TIM0_COMPB_vect_num		10
+#define TIM0_COMPB_vect			_VECTOR(10)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(10)
+
+/* Timer/Counter0 Overflow */
+#define TIM0_OVF_vect_num		11
+#define TIM0_OVF_vect			_VECTOR(11)
+#define SIG_OVERFLOW0			_VECTOR(11)
+
+/* Analog Comparator */
+#define ANA_COMP_vect_num		12
+#define ANA_COMP_vect			_VECTOR(12)
+#define SIG_COMPARATOR			_VECTOR(12)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		    13
+#define ADC_vect			    _VECTOR(13)
+#define SIG_ADC				    _VECTOR(13)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num		    14
+#define EE_RDY_vect			    _VECTOR(14)
+#define SIG_EEPROM_READY		_VECTOR(14)
+
+/* USI START */
+#define USI_START_vect_num		15
+#define USI_START_vect			_VECTOR(15)
+#define USI_STR_vect_num		15
+#define USI_STR_vect			_VECTOR(15)
+#define SIG_USI_START			_VECTOR(15)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		16
+#define USI_OVF_vect			_VECTOR(16)
+#define SIG_USI_OVERFLOW		_VECTOR(16)
+
+#define _VECTORS_SIZE 34
+
 
 #define SPM_PAGESIZE 32
 #define RAMSTART     (0x60)
@@ -86,11 +529,9 @@
 #define SIGNATURE_1 0x91
 #define SIGNATURE_2 0x0B
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 #define SLEEP_MODE_STANDBY (0x03<<3)
 
-
 #endif /* _AVR_IOTN24_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn24a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn24a.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn24a.h 2414 2014-03-21 16:04:00Z pitchumani $ */
 
 /* avr/iotn24a.h - definitions for ATtiny24A */
 
@@ -837,7 +837,6 @@
 #define PCINT5_PIN   PINA
 #define PCINT5_BIT   5
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn25.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn25.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005, Joerg Wunsch
+/* Copyright (c) 2005, Joerg Wunsch, 2005,2007 Anatoly Sokolov
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,14 +28,417 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn25.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 /* avr/iotn25.h - definitions for ATtiny25 */
 
 #ifndef _AVR_IOTN25_H_
 #define _AVR_IOTN25_H_ 1
 
-#include <avr/iotnx5.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx5.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* I/O registers */
+
+/* Reserved [0x00..0x02] */
+
+#define ADCSRB  _SFR_IO8 (0x03)
+#define BIN     7
+#define ACME    6
+#define IPR     5
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+#define ADCW    _SFR_IO16(0x04)
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8 (0x06)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADMUX   _SFR_IO8(0x07)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define REFS2   4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define ACSR    _SFR_IO8(0x08)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIS1   1
+#define ACIS0   0
+
+/* Reserved [0x09..0x0C] */
+
+#define USICR   _SFR_IO8(0x0D)
+#define USISIE  7
+#define USIOIE  6
+#define USIWM1  5
+#define USIWM0  4
+#define USICS1  3
+#define USICS0  2
+#define USICLK  1
+#define USITC   0
+
+#define USISR   _SFR_IO8(0x0E)
+#define USISIF  7 
+#define USIOIF  6
+#define USIPF   5
+#define USIDC   4
+#define USICNT3 3
+#define USICNT2 2
+#define USICNT1 1
+#define USICNT0 0
+
+#define USIDR   _SFR_IO8(0x0F)
+#define USIBR   _SFR_IO8(0x10)
+
+#define GPIOR0  _SFR_IO8(0x11)
+#define GPIOR1  _SFR_IO8(0x12)
+#define GPIOR2  _SFR_IO8(0x13)
+
+#define DIDR0    _SFR_IO8(0x14)
+#define ADC0D   5
+#define ADC2D   4
+#define ADC3D   3
+#define ADC1D   2
+#define AIN1D   1 
+#define AIN0D   0
+
+#define PCMSK   _SFR_IO8(0x15)
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+/* Reserved [0x19..0x1B] */
+
+/* EEPROM Control Register EECR */
+#define EECR	_SFR_IO8(0x1C)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define PRR     _SFR_IO8(0x20)
+#define PRTIM1  3
+#define PRTIM0  2
+#define PRUSI   1
+#define PRADC   0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define WDTCR   _SFR_IO8(0x21)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define DWDR    _SFR_IO8(0x22)
+
+#define DTPS1   _SFR_IO8(0x23)
+#define DTPS11   1
+#define DTPS10   0
+
+#define DT1B    _SFR_IO8(0x24)
+#define DT1BH3  7
+#define DT1BH2  6
+#define DT1BH1  5
+#define DT1BH0  4
+#define DT1BL3  3
+#define DT1BL2  2
+#define DT1BL1  1
+#define DT1BL0  0
+
+#define DT1A    _SFR_IO8(0x25)
+#define DT1AH3  7
+#define DT1AH2  6
+#define DT1AH1  5
+#define DT1AH0  4
+#define DT1AL3  3
+#define DT1AL2  2
+#define DT1AL1  1
+#define DT1AL0  0
+
+#define CLKPR   _SFR_IO8(0x26)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define PLLCSR  _SFR_IO8(0x27)
+#define LSM     7
+#define PCKE    2
+#define PLLE    1
+#define PLOCK   0
+
+#define OCR0B   _SFR_IO8(0x28)
+
+#define OCR0A   _SFR_IO8(0x29)
+
+#define TCCR0A  _SFR_IO8(0x2A)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define OCR1B   _SFR_IO8(0x2B)
+
+#define GTCCR   _SFR_IO8(0x2C)
+#define TSM     7
+#define PWM1B   6
+#define COM1B1  5
+#define COM1B0  4
+#define FOC1B   3
+#define FOC1A   2
+#define PSR1    1
+#define PSR0    0
+
+#define OCR1C   _SFR_IO8(0x2D)
+
+#define OCR1A   _SFR_IO8(0x2E)
+
+#define TCNT1   _SFR_IO8(0x2F)
+
+#define TCCR1   _SFR_IO8(0x30)
+#define CTC1    7
+#define PWM1A   6
+#define COM1A1  5
+#define COM1A0  4
+#define CS13    3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define BODS    7
+#define PUD     6
+#define SE      5
+#define SM1     4
+#define SM0     3
+#define BODSE   2
+#define ISC01   1
+#define ISC00   0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define RSIG    5
+#define CTPB    4
+#define RFLB    3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+#define TIFR    _SFR_IO8(0x38)
+#define OCF1A   6
+#define OCF1B   5
+#define OCF0A   4
+#define OCF0B   3
+#define TOV1    2
+#define TOV0    1
+
+#define TIMSK   _SFR_IO8(0x39)
+#define OCIE1A  6
+#define OCIE1B  5
+#define OCIE0A  4
+#define OCIE0B  3
+#define TOIE1   2
+#define TOIE0   1
+
+#define GIFR    _SFR_IO8(0x3A)
+#define INTF0   6
+#define PCIF    5
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define INT0    6
+#define PCIE    5
+
+/* Reserved [0x3C] */
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+///---
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt 0 */
+#define INT0_vect_num	        1
+#define INT0_vect			    _VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin change Interrupt Request 0 */
+#define PCINT0_vect_num			2
+#define PCINT0_vect			    _VECTOR(2)
+#define SIG_PIN_CHANGE			_VECTOR(2)
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIM1_COMPA_vect_num		3
+#define TIM1_COMPA_vect			_VECTOR(3)
+#define TIMER1_COMPA_vect_num	3
+#define TIMER1_COMPA_vect		_VECTOR(3)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(3)
+
+/* Timer/Counter1 Overflow */
+#define TIM1_OVF_vect_num		4
+#define TIM1_OVF_vect			_VECTOR(4)
+#define TIMER1_OVF_vect_num		4
+#define TIMER1_OVF_vect			_VECTOR(4)
+#define SIG_OVERFLOW1			_VECTOR(4)
+
+/* Timer/Counter0 Overflow */
+#define TIM0_OVF_vect_num		5
+#define TIM0_OVF_vect			_VECTOR(5)
+#define TIMER0_OVF_vect_num		5
+#define TIMER0_OVF_vect			_VECTOR(5)
+#define SIG_OVERFLOW0			_VECTOR(5)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num			6
+#define EE_RDY_vect		    	_VECTOR(6)
+#define SIG_EEPROM_READY		_VECTOR(6)
+
+/* Analog comparator */
+#define ANA_COMP_vect_num		7
+#define ANA_COMP_vect			_VECTOR(7)
+#define SIG_COMPARATOR			_VECTOR(7)
+
+/* ADC Conversion ready */
+#define ADC_vect_num    		8
+#define ADC_vect		    	_VECTOR(8)
+#define SIG_ADC				    _VECTOR(8)
+
+/* Timer/Counter1 Compare Match B */
+#define TIM1_COMPB_vect_num  	9
+#define TIM1_COMPB_vect			_VECTOR(9)
+#define TIMER1_COMPB_vect_num	9
+#define TIMER1_COMPB_vect   	_VECTOR(9)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(9)
+
+/* Timer/Counter0 Compare Match A */
+#define TIM0_COMPA_vect_num		10
+#define TIM0_COMPA_vect			_VECTOR(10)
+#define TIMER0_COMPA_vect_num	10
+#define TIMER0_COMPA_vect		_VECTOR(10)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(10)
+
+/* Timer/Counter0 Compare Match B */
+#define TIM0_COMPB_vect_num		11
+#define TIM0_COMPB_vect			_VECTOR(11)
+#define TIMER0_COMPB_vect_num	11
+#define TIMER0_COMPB_vect		_VECTOR(11)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(11)
+
+/* Watchdog Time-out */
+#define WDT_vect_num			12
+#define WDT_vect				_VECTOR(12)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(12)
+
+/* USI START */
+#define USI_START_vect_num		13
+#define USI_START_vect			_VECTOR(13)
+#define SIG_USI_START			_VECTOR(13)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		14
+#define USI_OVF_vect			_VECTOR(14)
+#define SIG_USI_OVERFLOW		_VECTOR(14)
+
+#define _VECTORS_SIZE 30
+
 
 #define SPM_PAGESIZE 32
 #define RAMSTART     (0x60)
@@ -86,10 +489,8 @@
 #define SIGNATURE_1 0x91
 #define SIGNATURE_2 0x08
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 
-
 #endif /* _AVR_IOTN25_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn26.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn26.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn26.h 2236 2011-03-17 21:53:39Z arcanum $ */
 
 /* avr/iotn26.h - definitions for ATtiny26 */
 
@@ -414,11 +414,9 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 #define SLEEP_MODE_STANDBY (0x03<<3)
 
-
 #endif  /* _AVR_IOTN26_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn261.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn261.h
@@ -28,14 +28,516 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn261.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 /* avr/iotn261.h - definitions for ATtiny261 */
 
 #ifndef _AVR_IOTN261_H_
 #define _AVR_IOTN261_H_ 1
 
-#include <avr/iotnx61.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx61.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define TCCR1E  _SFR_IO8(0x00)
+#define OC1OE0  0
+#define OC1OE1  1
+#define OC1OE2  2
+#define OC1OE3  3
+#define OC1OE4  4
+#define OC1OE5  5
+
+#define DIDR0   _SFR_IO8(0x01)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define AREFD   3
+#define ADC3D   4
+#define ADC4D   5
+#define ADC5D   6
+#define ADC6D   7
+
+#define DIDR1   _SFR_IO8(0x02)
+#define ADC7D   4
+#define ADC8D   5
+#define ADC9D   6
+#define ADC10D  7
+
+#define ADCSRB  _SFR_IO8(0x03)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define MUX5    3
+#define REFS2   4
+#define IRP     5
+#define GSEL    6
+#define BIN     7
+
+#define ADCW    _SFR_IO16(0x04)
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8(0x06)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADMUX   _SFR_IO8(0x07)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define ACSRA   _SFR_IO8(0x08)
+#define ACIS0   0
+#define ACIS1   1
+#define ACME    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define ACSRB   _SFR_IO8(0x09)
+#define ACM0    0
+#define ACM1    1
+#define ACM2    2
+#define HLEV    6
+#define HSEL    7
+
+#define GPIOR0  _SFR_IO8(0x0A)
+
+#define GPIOR1  _SFR_IO8(0x0B)
+
+#define GPIOR2  _SFR_IO8(0x0C)
+
+#define USICR   _SFR_IO8(0x0D)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_IO8(0x0F)
+
+#define USIBR   _SFR_IO8(0x10)
+
+#define USIPP   _SFR_IO8(0x11)
+#define USIPOS  0
+
+#define OCR0B   _SFR_IO8(0x12)
+
+#define OCR0A   _SFR_IO8(0x13)
+
+#define TCNT0H  _SFR_IO8(0x14)
+
+#define TCCR0A  _SFR_IO8(0x15)
+#define WGM00   0		/* up to at least datasheet rev. B */
+#define CTC0    0		/* newer revisions; change not mentioned
+				 * in revision history */
+#define ACIC0   3
+#define ICES0   4
+#define ICNC0   5
+#define ICEN0   6
+#define TCW0    7
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB0   0
+#define PINB1   1
+#define PINB2   2
+#define PINB3   3
+#define PINB4   4
+#define PINB5   5
+#define PINB6   6
+#define PINB7   7
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB0    0
+#define DDB1    1
+#define DDB2    2
+#define DDB3    3
+#define DDB4    4
+#define DDB5    5
+#define DDB6    6
+#define DDB7    7
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB0     0
+#define PB1     1
+#define PB2     2
+#define PB3     3
+#define PB4     4
+#define PB5     5
+#define PB6     6
+#define PB7     7
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA0   0
+#define PINA1   1
+#define PINA2   2
+#define PINA3   3
+#define PINA4   4
+#define PINA5   5
+#define PINA6   6
+#define PINA7   7
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDA0    0
+#define DDA1    1
+#define DDA2    2
+#define DDA3    3
+#define DDA4    4
+#define DDA5    5
+#define DDA6    6
+#define DDA7    7
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PA0     0
+#define PA1     1
+#define PA2     2
+#define PA3     3
+#define PA4     4
+#define PA5     5
+#define PA6     6
+#define PA7     7
+
+/* EEPROM Control Register */
+#define EECR	_SFR_IO8(0x1C)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define DWDR    _SFR_IO8(0x20)
+
+#define WDTCR   _SFR_IO8(0x21)
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDE     3
+#define WDCE    4
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define PCMSK1  _SFR_IO8(0x22)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK0  _SFR_IO8(0x23)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define DT1     _SFR_IO8(0x24)
+#define DT1L0   0
+#define DT1L1   1
+#define DT1L2   2
+#define DT1L3   3
+#define DT1H0   4
+#define DT1H1   5
+#define DT1H2   6
+#define DT1H3   7
+
+#define TC1H    _SFR_IO8(0x25)
+#define TC18    0
+#define TC19    1
+
+#define TCCR1D  _SFR_IO8(0x26)
+#define WGM10   0
+#define WGM11   1
+#define FPF1    2
+#define FPAC1   3
+#define FPES1   4
+#define FPNC1   5
+#define FPEN1   6
+#define FPIE1   7
+
+#define TCCR1C  _SFR_IO8(0x27)
+#define PWM1D   0
+#define FOC1D   1
+#define COM1D0  2
+#define COM1D1  3
+#define COM1B0S 4
+#define COM1B1S 5
+#define COM1A0S 6
+#define COM1A1S 7
+
+#define CLKPR   _SFR_IO8(0x28)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLOCK   0
+#define PLLE    1
+#define PCKE    2
+#define LSM     7
+
+#define OCR1D   _SFR_IO8(0x2A)
+
+#define OCR1C   _SFR_IO8(0x2B)
+
+#define OCR1B   _SFR_IO8(0x2C)
+
+#define OCR1A   _SFR_IO8(0x2D)
+
+#define TCNT1   _SFR_IO8(0x2E)
+
+#define TCCR1B  _SFR_IO8(0x2F)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define CS13    3
+#define DTPS10  4
+#define DTPS11  5
+#define PSR1    6
+#define PWM1X   7
+
+#define TCCR1A  _SFR_IO8(0x30)
+#define PWM1B   0
+#define PWM1A   1
+#define FOC1B   2
+#define FOC1A   3
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0L  _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define PSR0    3
+#define TSM     4
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define ISC00   0
+#define ISC01   1
+#define SM0     3
+#define SM1     4
+#define SE      5
+#define PUD     6
+
+#define PRR     _SFR_IO8(0x36)
+#define PRADC   0
+#define PRUSI   1
+#define PRTIM0  2
+#define PRTIM1  3
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR    _SFR_IO8(0x38)
+#define ICF0    0
+#define TOV0    1
+#define TOV1    2
+#define OCF0B   3
+#define OCF0A   4
+#define OCF1B   5
+#define OCF1A   6
+#define OCF1D   7
+
+#define TIMSK   _SFR_IO8(0x39)
+#define TICIE0  0
+#define TOIE0   1
+#define TOIE1   2
+#define OCIE0B  3
+#define OCIE0A  4
+#define OCIE1B  5
+#define OCIE1A  6
+#define OCIE1D  7
+
+#define GIFR    _SFR_IO8(0x3A)
+#define PCIF    5
+#define INTF0   6
+#define INTF1   7
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define PCIE0   4
+#define PCIE1   5
+#define INT0    6
+#define INT1    7
+
+/* Reserved [0x3C] */
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt 0 */
+#define INT0_vect_num			1
+#define INT0_vect	    		_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin Change Interrupt */
+#define PCINT_vect_num			2
+#define PCINT_vect		    	_VECTOR(2)
+#define SIG_PIN_CHANGE			_VECTOR(2)
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPA_vect_num	3
+#define TIMER1_COMPA_vect		_VECTOR(3)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(3)
+
+/* Timer/Counter1 Compare Match 1B */
+#define TIMER1_COMPB_vect_num	4
+#define TIMER1_COMPB_vect	    _VECTOR(4)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(4)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		5
+#define TIMER1_OVF_vect			_VECTOR(5)
+#define SIG_OVERFLOW1			_VECTOR(5)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num 	6
+#define TIMER0_OVF_vect			_VECTOR(6)
+#define SIG_OVERFLOW0			_VECTOR(6)
+
+/* USI Start */
+#define USI_START_vect_num		7
+#define USI_START_vect			_VECTOR(7)
+#define SIG_USI_START			_VECTOR(7)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		8
+#define USI_OVF_vect			_VECTOR(8)
+#define SIG_USI_OVERFLOW		_VECTOR(8)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num			9
+#define EE_RDY_vect		    	_VECTOR(9)
+#define SIG_EEPROM_READY		_VECTOR(9)
+
+/* Analog Comparator */
+#define ANA_COMP_vect_num   	10
+#define ANA_COMP_vect			_VECTOR(10)
+#define SIG_ANA_COMP			_VECTOR(10)
+#define SIG_COMPARATOR			_VECTOR(10)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			11
+#define ADC_vect	    		_VECTOR(11)
+#define SIG_ADC			    	_VECTOR(11)
+
+/* Watchdog Time-Out */
+#define WDT_vect_num			12
+#define WDT_vect	    		_VECTOR(12)
+#define SIG_WDT			    	_VECTOR(12)
+
+/* External Interrupt 1 */
+#define INT1_vect_num			13
+#define INT1_vect	    		_VECTOR(13)
+#define SIG_INTERRUPT1			_VECTOR(13)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num		14
+#define TIMER0_COMPA_vect	    	_VECTOR(14)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(14)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num		15
+#define TIMER0_COMPB_vect	    	_VECTOR(15)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(15)
+
+/* ADC Conversion Complete */
+#define TIMER0_CAPT_vect_num		16
+#define TIMER0_CAPT_vect	    	_VECTOR(16)
+#define SIG_INPUT_CAPTURE0		    _VECTOR(16)
+
+/* Timer/Counter1 Compare Match D */
+#define TIMER1_COMPD_vect_num       17
+#define TIMER1_COMPD_vect		    _VECTOR(17)
+#define SIG_OUTPUT_COMPARE0D		_VECTOR(17)
+
+/* Timer/Counter1 Fault Protection */
+#define FAULT_PROTECTION_vect_num	18
+#define FAULT_PROTECTION_vect		_VECTOR(18)
+
+#define _VECTORS_SIZE 38
+
 
 #define SPM_PAGESIZE 32
 #define RAMSTART     (0x60)
@@ -85,11 +587,9 @@
 #define SIGNATURE_1 0x91
 #define SIGNATURE_2 0x0C
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 #define SLEEP_MODE_STANDBY (0x03<<3)
 
-
 #endif /* _AVR_IOTN261_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn261a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn261a.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn261a.h 2063 2009-11-18 22:06:28Z arcanum $ */
 
 /* avr/iotn261a.h - definitions for ATtiny261A */
 
@@ -496,6 +496,7 @@
 #define DTPS10 4
 #define DTPS11 5
 #define PSR1 6
+#define PWM1X 7
 
 #define TCCR1A _SFR_IO8(0x30)
 #define PWM1B 0
@@ -978,7 +979,6 @@
 #define PA0_PIN   PINADC
 #define PA0_BIT   ADC0
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn28.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn28.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn28.h 2236 2011-03-17 21:53:39Z arcanum $ */
 
 /* avr/iotn28.h - definitions for ATtiny28 */
 
@@ -291,9 +291,7 @@
 
 #endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
 
-
 #define SLEEP_MODE_IDLE (0x00<<4)
 #define SLEEP_MODE_PWR_DOWN (0x01<<4)
 
-
 #endif /* _AVR_IOTN28_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn4.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn4.h
@@ -468,7 +468,6 @@
 #define PB3_PIN   PINRESET
 #define PB3_BIT   RESET
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn40.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn40.h
@@ -599,7 +599,7 @@
 
 
 /* Fuses */
-#define FUSE_MEMORY_SIZE 1 
+#define FUSE_MEMORY_SIZE 1
 
 
 /* Lock Bits */
@@ -758,7 +758,6 @@
 #define PCINT7_PIN   PINADC
 #define PCINT7_BIT   ADC7
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn4313.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn4313.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn4313.h 2412 2014-03-20 11:21:20Z pitchumani $ */
 
 /* avr/iotn4313.h - definitions for ATtiny4313 */
 
@@ -42,7 +42,7 @@
 #  define _AVR_IOXXX_H_ "iotn4313.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATtiny4313_H_
@@ -316,6 +316,7 @@
 #define EEDR7 7
 
 #define EEAR _SFR_IO8(0x01E)
+#define EEARL _SFR_IO8(0x01E)
 #define EEAR0 0
 #define EEAR1 1
 #define EEAR2 2
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn43u.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn43u.h
@@ -29,7 +29,7 @@
   POSSIBILITY OF SUCH DAMAGE. 
 */
 
-/* $Id$ */
+/* $Id: iotn43u.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/iotn43u.h - definitions for ATtiny43U */
 
@@ -596,11 +596,9 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x0C
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 #define SLEEP_MODE_STANDBY (0x03<<3)
 
-
 #endif /* _AVR_IOTN43U_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn44.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn44.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005, Anatoly Sokolov
+/* Copyright (c) 2005, 2007 Anatoly Sokolov
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,14 +28,457 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn44.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 /* avr/iotn44.h - definitions for ATtiny44 */
 
 #ifndef _AVR_IOTN44_H_
 #define _AVR_IOTN44_H_ 1
 
-#include <avr/iotnx4.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx4.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* I/O registers */
+
+#define PRR     _SFR_IO8 (0x00)
+#define PRTIM1  3
+#define PRTIM0  2
+#define PRUSI   1
+#define PRADC   0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define DIDR0    _SFR_IO8(0x01)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1 
+#define ADC0D   0
+
+/* Reserved [0x02] */
+
+#define ADCSRB  _SFR_IO8 (0x03)
+#define BIN     7
+#define ACME    6
+#define ADLAR   4
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+#define ADCW    _SFR_IO16(0x04)
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8 (0x06)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADMUX   _SFR_IO8(0x07)
+#define REFS1   7
+#define REFS0   6
+#define MUX5    5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define ACSR    _SFR_IO8(0x08)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+/* Reserved [0x09..0x0A] */
+
+#define TIFR1   _SFR_IO8(0x0B)
+#define ICF1    5
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIMSK1   _SFR_IO8(0x0C)
+#define ICIE1   5
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define USICR   _SFR_IO8(0x0D)
+#define USISIE  7
+#define USIOIE  6
+#define USIWM1  5
+#define USIWM0  4
+#define USICS1  3
+#define USICS0  2
+#define USICLK  1
+#define USITC   0
+
+#define USISR   _SFR_IO8(0x0E)
+#define USISIF  7 
+#define USIOIF  6
+#define USIPF   5
+#define USIDC   4
+#define USICNT3 3
+#define USICNT2 2
+#define USICNT1 1
+#define USICNT0 0
+
+#define USIDR   _SFR_IO8(0x0F)
+
+#define USIBR   _SFR_IO8(0x10)
+
+/* Reserved [0x11] */
+
+#define PCMSK0  _SFR_IO8(0x12)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define GPIOR0  _SFR_IO8(0x13)
+
+#define GPIOR1  _SFR_IO8(0x14)
+
+#define GPIOR2  _SFR_IO8(0x15)
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PA7     7
+#define PA6     6
+#define PA5     5
+#define PA4     4
+#define PA3     3
+#define PA2     2
+#define PA1     1
+#define PA0     0
+
+/* EEPROM Control Register EECR */
+#define EECR	_SFR_IO8(0x1C)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define PCMSK1  _SFR_IO8(0x20)
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+#define WDTCSR _SFR_IO8(0x21)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define TCCR1C  _SFR_IO8(0x22)
+#define FOC1A   7
+#define FOC1B   6
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSR10   0
+
+#define ICR1    _SFR_IO16(0x24)
+#define ICR1L   _SFR_IO8(0x24)
+#define ICR1H   _SFR_IO8(0x25)
+
+#define CLKPR   _SFR_IO8(0x26)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define DWDR    _SFR_IO8(0x27)
+
+#define OCR1B   _SFR_IO16(0x28)
+#define OCR1BL  _SFR_IO8(0x28)
+#define OCR1BH  _SFR_IO8(0x29)
+
+#define OCR1A   _SFR_IO16(0x2A)
+#define OCR1AL  _SFR_IO8(0x2A)
+#define OCR1AH  _SFR_IO8(0x2B)
+
+/* keep misspelled names from avr-libc 1.4.[0..1] for compatibility */
+#define OCRB1   _SFR_IO16(0x28)
+#define OCRB1L  _SFR_IO8(0x28)
+#define OCRB1H  _SFR_IO8(0x29)
+
+#define OCRA1   _SFR_IO16(0x2A)
+#define OCRA1L  _SFR_IO8(0x2A)
+#define OCRA1H  _SFR_IO8(0x2B)
+
+#define TCNT1   _SFR_IO16(0x2C)
+#define TCNT1L  _SFR_IO8(0x2C)
+#define TCNT1H  _SFR_IO8(0x2D)
+
+#define TCCR1B  _SFR_IO8(0x2E)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1A  _SFR_IO8(0x2F)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR0A  _SFR_IO8(0x30)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define BODS    7
+#define PUD     6
+#define SE      5
+#define SM1     4
+#define SM0     3
+#define BODSE   2
+#define ISC01   1
+#define ISC00   0
+
+#define OCR0A   _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define RSIG    5
+#define CTPB    4
+#define RFLB    3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+#define TIFR0   _SFR_IO8(0x38)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIMSK0  _SFR_IO8(0x39)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define GIFR    _SFR_IO8(0x3A)
+#define INTF0   6
+#define PCIF1   5
+#define PCIF0   4
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define INT0    6
+#define PCIE1   5
+#define PCIE0   4
+
+#define OCR0B   _SFR_IO8(0x3C)
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+///---
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt Request 0 */
+#define INT0_vect_num		    1
+#define INT0_vect			    _VECTOR(1)
+#define EXT_INT0_vect_num    	1
+#define EXT_INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		    2
+#define PCINT0_vect			    _VECTOR(2)
+#define SIG_PIN_CHANGE0			_VECTOR(2)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		    3
+#define PCINT1_vect			    _VECTOR(3)
+#define SIG_PIN_CHANGE1			_VECTOR(3)
+
+/* Watchdog Time-out */
+#define WDT_vect_num			4
+#define WDT_vect			    _VECTOR(4)
+#define WATCHDOG_vect_num		4
+#define WATCHDOG_vect			_VECTOR(4)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(4)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	5
+#define TIMER1_CAPT_vect		_VECTOR(5)
+#define TIM1_CAPT_vect_num		5
+#define TIM1_CAPT_vect			_VECTOR(5)
+#define SIG_INPUT_CAPTURE1		_VECTOR(5)
+
+/* Timer/Counter1 Compare Match A */
+#define TIM1_COMPA_vect_num		6
+#define TIM1_COMPA_vect			_VECTOR(6)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(6)
+
+/* Timer/Counter1 Compare Match B */
+#define TIM1_COMPB_vect_num		7
+#define TIM1_COMPB_vect			_VECTOR(7)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(7)
+
+/* Timer/Counter1 Overflow */
+#define TIM1_OVF_vect_num		8
+#define TIM1_OVF_vect			_VECTOR(8)
+#define SIG_OVERFLOW1			_VECTOR(8)
+
+/* Timer/Counter0 Compare Match A */
+#define TIM0_COMPA_vect_num		9
+#define TIM0_COMPA_vect			_VECTOR(9)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(9)
+
+/* Timer/Counter0 Compare Match B */
+#define TIM0_COMPB_vect_num		10
+#define TIM0_COMPB_vect			_VECTOR(10)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(10)
+
+/* Timer/Counter0 Overflow */
+#define TIM0_OVF_vect_num		11
+#define TIM0_OVF_vect			_VECTOR(11)
+#define SIG_OVERFLOW0			_VECTOR(11)
+
+/* Analog Comparator */
+#define ANA_COMP_vect_num		12
+#define ANA_COMP_vect			_VECTOR(12)
+#define SIG_COMPARATOR			_VECTOR(12)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		    13
+#define ADC_vect			    _VECTOR(13)
+#define SIG_ADC				    _VECTOR(13)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num		    14
+#define EE_RDY_vect			    _VECTOR(14)
+#define SIG_EEPROM_READY		_VECTOR(14)
+
+/* USI START */
+#define USI_START_vect_num		15
+#define USI_START_vect			_VECTOR(15)
+#define USI_STR_vect_num		15
+#define USI_STR_vect			_VECTOR(15)
+#define SIG_USI_START			_VECTOR(15)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		16
+#define USI_OVF_vect			_VECTOR(16)
+#define SIG_USI_OVERFLOW		_VECTOR(16)
+
+#define _VECTORS_SIZE 34
+
 
 /* Constants */
 #define SPM_PAGESIZE 64
@@ -86,11 +529,9 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x07
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 #define SLEEP_MODE_STANDBY (0x03<<3)
 
-
 #endif /* _AVR_IOTN44_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn441.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn441.h
@@ -1,903 +1,925 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATTINY441_H_INCLUDED
-#define _AVR_ATTINY441_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn441.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define ADCSRB  _SFR_IO8(0x04)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ADLAR   3
-
-#define ADCSRA  _SFR_IO8(0x05)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_IO16(0x06)
-#endif
-#define ADCW    _SFR_IO16(0x06)
-
-#define ADCL    _SFR_IO8(0x06)
-#define ADCH    _SFR_IO8(0x07)
-
-#define ADMUXB  _SFR_IO8(0x08)
-#define GSEL0   0
-#define GSEL1   1
-#define REFS0   5
-#define REFS1   6
-#define REFS2   7
-
-#define ADMUXA  _SFR_IO8(0x09)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define MUX5    5
-
-#define ACSR0A  _SFR_IO8(0x0A)
-#define ACIS00  0
-#define ACIS01  1
-#define ACIC0   2
-#define ACIE0   3
-#define ACI0    4
-#define ACO0    5
-#define ACPMUX2 6
-#define ACD0    7
-
-#define ACSR0B  _SFR_IO8(0x0B)
-#define ACPMUX0 0
-#define ACPMUX1 1
-#define ACNMUX0 2
-#define ACNMUX1 3
-#define ACOE0   4
-#define HLEV0   6
-#define HSEL0   7
-
-#define ACSR1A  _SFR_IO8(0x0C)
-#define ACIS10  0
-#define ACIS11  1
-#define ACIC1   2
-#define ACIE1   3
-#define ACI1    4
-#define ACO1    5
-#define ACBG1   6
-#define ACD1    7
-
-#define ACSR1B  _SFR_IO8(0x0D)
-#define ACME1   2
-#define ACOE1   4
-#define HLEV1   6
-#define HSEL1   7
-
-#define TIFR1   _SFR_IO8(0x0E)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIMSK1  _SFR_IO8(0x0F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIFR2   _SFR_IO8(0x10)
-#define TOV2    0
-#define OCF2A   1
-#define OCF2B   2
-#define ICF2    5
-
-#define TIMSK2  _SFR_IO8(0x11)
-#define TOIE2   0
-#define OCIE2A  1
-#define OCIE2B  2
-#define ICIE2   5
-
-#define PCMSK0  _SFR_IO8(0x12)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define GPIOR0  _SFR_IO8(0x13)
-
-#define GPIOR1  _SFR_IO8(0x14)
-
-#define GPIOR2  _SFR_IO8(0x15)
-
-#define PINB    _SFR_IO8(0x16)
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x17)
-#define DDRB3   3
-// Inserted "DDB3" from "DDRB3" due to compatibility
-#define DDB3    3
-#define DDRB2   2
-// Inserted "DDB2" from "DDRB2" due to compatibility
-#define DDB2    2
-#define DDRB1   1
-// Inserted "DDB1" from "DDRB1" due to compatibility
-#define DDB1    1
-#define DDRB0   0
-// Inserted "DDB0" from "DDRB0" due to compatibility
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x18)
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINA    _SFR_IO8(0x19)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x1A)
-#define DDRA7   7
-// Inserted "DDA7" from "DDRA7" due to compatibility
-#define DDA7    7
-#define DDRA6   6
-// Inserted "DDA6" from "DDRA6" due to compatibility
-#define DDA6    6
-#define DDRA5   5
-// Inserted "DDA5" from "DDRA5" due to compatibility
-#define DDA5    5
-#define DDRA4   4
-// Inserted "DDA4" from "DDRA4" due to compatibility
-#define DDA4    4
-#define DDRA3   3
-// Inserted "DDA3" from "DDRA3" due to compatibility
-#define DDA3    3
-#define DDRA2   2
-// Inserted "DDA2" from "DDRA2" due to compatibility
-#define DDA2    2
-#define DDRA1   1
-// Inserted "DDA1" from "DDRA1" due to compatibility
-#define DDA1    1
-#define DDRA0   0
-// Inserted "DDA0" from "DDRA0" due to compatibility
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x1B)
-#define PORTA7  7
-#define PORTA6  6
-#define PORTA5  5
-#define PORTA4  4
-#define PORTA3  3
-#define PORTA2  2
-#define PORTA1  1
-#define PORTA0  0
-
-#define EECR    _SFR_IO8(0x1C)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x1D)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x1E)
-
-#define EEARL   _SFR_IO8(0x1E)
-#define EEARH   _SFR_IO8(0x1F)
-
-#define PCMSK1  _SFR_IO8(0x20)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-
-#define WDTCSR  _SFR_IO8(0x21)
-#define WDE     3
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define TCCR1C  _SFR_IO8(0x22)
-#define FOC1B   6
-#define FOC1A   7
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR     0
-#define TSM     7
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_IO16(0x24)
-
-#define ICR1L   _SFR_IO8(0x24)
-#define ICR1H   _SFR_IO8(0x25)
-
-/* Reserved [0x26..0x27] */
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_IO16(0x28)
-
-#define OCR1BL  _SFR_IO8(0x28)
-#define OCR1BH  _SFR_IO8(0x29)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_IO16(0x2A)
-
-#define OCR1AL  _SFR_IO8(0x2A)
-#define OCR1AH  _SFR_IO8(0x2B)
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_IO16(0x2C)
-
-#define TCNT1L  _SFR_IO8(0x2C)
-#define TCNT1H  _SFR_IO8(0x2D)
-
-#define TCCR1B  _SFR_IO8(0x2E)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1A  _SFR_IO8(0x2F)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR0A  _SFR_IO8(0x30)
-#define WGM00   0
-#define WGM01   1
-#define COM0B0  4
-#define COM0B1  5
-#define COM0A0  6
-#define COM0A1  7
-
-/* Reserved [0x31] */
-
-#define TCNT0   _SFR_IO8(0x32)
-
-#define TCCR0B  _SFR_IO8(0x33)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM02   3
-#define FOC0B   6
-#define FOC0A   7
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define ISC00   0
-#define ISC01   1
-#define SM0     3
-#define SM1     4
-#define SE      5
-
-#define OCR0A   _SFR_IO8(0x36)
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define RFLB    3
-#define CTPB    4
-#define RSIG    5
-
-#define TIFR0   _SFR_IO8(0x38)
-#define TOV0    0
-#define OCF0A   1
-#define OCF0B   2
-
-#define TIMSK0  _SFR_IO8(0x39)
-#define TOIE0   0
-#define OCIE0A  1
-#define OCIE0B  2
-
-#define GIFR    _SFR_IO8(0x3A)
-#define PCIF0   4
-#define PCIF1   5
-#define INTF0   6
-
-#define GIMSK   _SFR_IO8(0x3B)
-#define PCIE0   4
-#define PCIE1   5
-#define INT0    6
-
-#define OCR0B   _SFR_IO8(0x3C)
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define DIDR0   _SFR_MEM8(0x60)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x61)
-#define ADC11D  0
-#define ADC10D  1
-#define ADC8D   2
-#define ADC9D   3
-
-#define PUEB    _SFR_MEM8(0x62)
-
-#define PUEA    _SFR_MEM8(0x63)
-
-#define PORTCR  _SFR_MEM8(0x64)
-#define BBMB    1
-#define BBMA    0
-
-#define REMAP   _SFR_MEM8(0x65)
-#define U0MAP   0
-#define SPIMAP  1
-
-#define TOCPMCOE _SFR_MEM8(0x66)
-#define TOCC0OE 0
-#define TOCC1OE 1
-#define TOCC2OE 2
-#define TOCC3OE 3
-#define TOCC4OE 4
-#define TOCC5OE 5
-#define TOCC6OE 6
-#define TOCC7OE 7
-
-#define TOCPMSA0 _SFR_MEM8(0x67)
-#define TOCC0S0 0
-#define TOCC0S1 1
-#define TOCC1S0 2
-#define TOCC1S1 3
-#define TOCC2S0 4
-#define TOCC2S1 5
-#define TOCC3S0 6
-#define TOCC3S1 7
-
-#define TOCPMSA1 _SFR_MEM8(0x68)
-#define TOCC4S0 0
-#define TOCC4S1 1
-#define TOCC5S0 2
-#define TOCC5S1 3
-#define TOCC6S0 4
-#define TOCC6S1 5
-#define TOCC7S0 6
-#define TOCC7S1 7
-
-/* Reserved [0x69] */
-
-#define PHDE    _SFR_MEM8(0x6A)
-#define PHDEA0  0
-#define PHDEA1  1
-
-/* Reserved [0x6B..0x6F] */
-
-#define PRR     _SFR_MEM8(0x70)
-#define PRADC   0
-#define PRTIM0  1
-#define PRTIM1  2
-#define PRTIM2  3
-#define PRSPI   4
-#define PRUSART0 5
-#define PRUSART1 6
-#define PRTWI   7
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTWI))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRTIM0
-#define __AVR_HAVE_PRR_PRTIM1
-#define __AVR_HAVE_PRR_PRTIM2
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRUSART0
-#define __AVR_HAVE_PRR_PRUSART1
-#define __AVR_HAVE_PRR_PRTWI
-
-#define CCP     _SFR_MEM8(0x71)
-
-#define CLKCR   _SFR_MEM8(0x72)
-#define CKSEL0  0
-#define CKSEL1  1
-#define CKSEL2  2
-#define CKSEL3  3
-#define SUT     4
-#define CKOUTC  5
-#define CSTR    6
-#define OSCRDY  7
-
-#define CLKPR   _SFR_MEM8(0x73)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-
-#define OSCCAL0 _SFR_MEM8(0x74)
-
-#define OSCTCAL0A _SFR_MEM8(0x75)
-
-#define OSCTCAL0B _SFR_MEM8(0x76)
-
-#define OSCCAL1 _SFR_MEM8(0x77)
-
-/* Reserved [0x78..0x7F] */
-
-#define UDR0    _SFR_MEM8(0x80)
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0x81)
-
-#define UBRR0L  _SFR_MEM8(0x81)
-#define UBRR0H  _SFR_MEM8(0x82)
-
-#define UCSR0D  _SFR_MEM8(0x83)
-#define SFDE0   5
-#define RXS0    6
-#define RXSIE0  7
-
-#define UCSR0C  _SFR_MEM8(0x84)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UCSR0B  _SFR_MEM8(0x85)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0A  _SFR_MEM8(0x86)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-/* Reserved [0x87..0x8F] */
-
-#define UDR1    _SFR_MEM8(0x90)
-
-/* Combine UBRR1L and UBRR1H */
-#define UBRR1   _SFR_MEM16(0x91)
-
-#define UBRR1L  _SFR_MEM8(0x91)
-#define UBRR1H  _SFR_MEM8(0x92)
-
-#define UCSR1D  _SFR_MEM8(0x93)
-#define SFDE1   5
-#define RXS1    6
-#define RXSIE1  7
-
-#define UCSR1C  _SFR_MEM8(0x94)
-#define UCPOL1  0
-#define UCSZ10  1
-#define UCSZ11  2
-#define USBS1   3
-#define UPM10   4
-#define UPM11   5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UCSR1B  _SFR_MEM8(0x95)
-#define TXB81   0
-#define RXB81   1
-#define UCSZ12  2
-#define TXEN1   3
-#define RXEN1   4
-#define UDRIE1  5
-#define TXCIE1  6
-#define RXCIE1  7
-
-#define UCSR1A  _SFR_MEM8(0x96)
-#define MPCM1   0
-#define U2X1    1
-#define UPE1    2
-#define DOR1    3
-#define FE1     4
-#define UDRE1   5
-#define TXC1    6
-#define RXC1    7
-
-/* Reserved [0x97..0x9F] */
-
-#define TWSD    _SFR_MEM8(0xA0)
-#define TWSD0   0
-#define TWSD1   1
-#define TWSD2   2
-#define TWSD3   3
-#define TWSD4   4
-#define TWSD5   5
-#define TWSD6   6
-#define TWSD7   7
-
-#define TWSAM   _SFR_MEM8(0xA1)
-#define TWAE    0
-#define TWSAM1  1
-#define TWSAM2  2
-#define TWSAM3  3
-#define TWSAM4  4
-#define TWSAM5  5
-#define TWSAM6  6
-#define TWSAM7  7
-
-#define TWSA    _SFR_MEM8(0xA2)
-
-#define TWSSRA  _SFR_MEM8(0xA3)
-#define TWAS    0
-#define TWDIR   1
-#define TWBE    2
-#define TWC     3
-#define TWRA    4
-#define TWCH    5
-#define TWASIF  6
-#define TWDIF   7
-
-#define TWSCRB  _SFR_MEM8(0xA4)
-#define TWCMD0  0
-#define TWCMD1  1
-#define TWAA    2
-#define TWHNM   3
-
-#define TWSCRA  _SFR_MEM8(0xA5)
-#define TWSME   0
-#define TWPME   1
-#define TWSIE   2
-#define TWEN    3
-#define TWASIE  4
-#define TWDIE   5
-#define TWSHE   7
-
-/* Reserved [0xA6..0xAF] */
-
-#define SPDR    _SFR_MEM8(0xB0)
-
-#define SPSR    _SFR_MEM8(0xB1)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPCR    _SFR_MEM8(0xB2)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-/* Reserved [0xB3..0xBF] */
-
-/* Combine ICR2L and ICR2H */
-#define ICR2    _SFR_MEM16(0xC0)
-
-#define ICR2L   _SFR_MEM8(0xC0)
-#define ICR2H   _SFR_MEM8(0xC1)
-
-/* Combine OCR2BL and OCR2BH */
-#define OCR2B   _SFR_MEM16(0xC2)
-
-#define OCR2BL  _SFR_MEM8(0xC2)
-#define OCR2BH  _SFR_MEM8(0xC3)
-
-/* Combine OCR2AL and OCR2AH */
-#define OCR2A   _SFR_MEM16(0xC4)
-
-#define OCR2AL  _SFR_MEM8(0xC4)
-#define OCR2AH  _SFR_MEM8(0xC5)
-
-/* Combine TCNT2L and TCNT2H */
-#define TCNT2   _SFR_MEM16(0xC6)
-
-#define TCNT2L  _SFR_MEM8(0xC6)
-#define TCNT2H  _SFR_MEM8(0xC7)
-
-#define TCCR2C  _SFR_MEM8(0xC8)
-#define FOC2B   6
-#define FOC2A   7
-
-#define TCCR2B  _SFR_MEM8(0xC9)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM22   3
-#define WGM23   4
-#define ICES2   6
-#define ICNC2   7
-
-#define TCCR2A  _SFR_MEM8(0xCA)
-#define WGM20   0
-#define WGM21   1
-#define COM2B0  4
-#define COM2B1  5
-#define COM2A0  6
-#define COM2A1  7
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<3)
-#define SLEEP_MODE_ADC (0x01<<3)
-#define SLEEP_MODE_PWR_DOWN (0x02<<3)
-#define SLEEP_MODE_STANDBY (0x03<<3)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(2)
-#define PCINT0_vect_num        2
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect            _VECTOR(3)
-#define PCINT1_vect_num        3
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect            _VECTOR(4)
-#define WDT_vect_num        4
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(5)
-#define TIMER1_CAPT_vect_num        5
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect            _VECTOR(6)
-#define TIMER1_COMPA_vect_num        6
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect            _VECTOR(7)
-#define TIMER1_COMPB_vect_num        7
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(8)
-#define TIMER1_OVF_vect_num        8
-
-/* TimerCounter0 Compare Match A */
-#define TIMER0_COMPA_vect            _VECTOR(9)
-#define TIMER0_COMPA_vect_num        9
-
-/* TimerCounter0 Compare Match B */
-#define TIMER0_COMPB_vect            _VECTOR(10)
-#define TIMER0_COMPB_vect_num        10
-
-/* Timer/Couner0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(11)
-#define TIMER0_OVF_vect_num        11
-
-/* Analog Comparator 0 */
-#define ANA_COMP0_vect            _VECTOR(12)
-#define ANA_COMP0_vect_num        12
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(13)
-#define ADC_vect_num        13
-
-/* EEPROM Ready */
-#define EE_RDY_vect            _VECTOR(14)
-#define EE_RDY_vect_num        14
-
-/* Analog Comparator 1 */
-#define ANA_COMP1_vect            _VECTOR(15)
-#define ANA_COMP1_vect_num        15
-
-/* Timer/Counter2 Capture Event */
-#define TIMER2_CAPT_vect            _VECTOR(16)
-#define TIMER2_CAPT_vect_num        16
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect            _VECTOR(17)
-#define TIMER2_COMPA_vect_num        17
-
-/* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect            _VECTOR(18)
-#define TIMER2_COMPB_vect_num        18
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect            _VECTOR(19)
-#define TIMER2_OVF_vect_num        19
-
-/* Serial Peripheral Interface */
-#define SPI_vect            _VECTOR(20)
-#define SPI_vect_num        20
-
-/* USART0, Start */
-#define USART0_START_vect            _VECTOR(21)
-#define USART0_START_vect_num        21
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect            _VECTOR(22)
-#define USART0_RX_vect_num        22
-
-/* USART0 Data Register Empty */
-#define USART0_UDRE_vect            _VECTOR(23)
-#define USART0_UDRE_vect_num        23
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect            _VECTOR(24)
-#define USART0_TX_vect_num        24
-
-/* USART1, Start */
-#define USART1_START_vect            _VECTOR(25)
-#define USART1_START_vect_num        25
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect            _VECTOR(26)
-#define USART1_RX_vect_num        26
-
-/* USART1 Data Register Empty */
-#define USART1_UDRE_vect            _VECTOR(27)
-#define USART1_UDRE_vect_num        27
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect            _VECTOR(28)
-#define USART1_TX_vect_num        28
-
-/* Two-wire Serial Interface */
-#define TWI_SLAVE_vect            _VECTOR(29)
-#define TWI_SLAVE_vect_num        29
-
-#define _VECTORS_SIZE 60
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 16
-#define FLASHSTART   0x0000
-#define FLASHEND     0x0FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      256
-#define RAMEND       0x01FF
-#define E2START     0
-#define E2SIZE      256
-#define E2PAGESIZE  4
-#define E2END       0x00FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define FUSE_BODACT0     (unsigned char)~_BV(1)
-#define FUSE_BODACT1     (unsigned char)~_BV(2)
-#define FUSE_BODPD0      (unsigned char)~_BV(3)
-#define FUSE_BODPD1      (unsigned char)~_BV(4)
-#define FUSE_ULPOSCSEL0  (unsigned char)~_BV(5)
-#define FUSE_ULPOSCSEL1  (unsigned char)~_BV(6)
-#define FUSE_ULPOSCSEL2  (unsigned char)~_BV(7)
-#define EFUSE_DEFAULT    (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x15
-
-
-#endif /* #ifdef _AVR_ATTINY441_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATTINY441_H_INCLUDED
+#define _AVR_ATTINY441_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotn441.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define ADCSRB  _SFR_IO8(0x04)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ADLAR   3
+
+#define ADCSRA  _SFR_IO8(0x05)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x06)
+#endif
+#define ADCW    _SFR_IO16(0x06)
+
+#define ADCL    _SFR_IO8(0x06)
+#define ADCH    _SFR_IO8(0x07)
+
+#define ADMUXB  _SFR_IO8(0x08)
+#define GSEL0   0
+#define GSEL1   1
+#define REFS0   5
+#define REFS1   6
+#define REFS2   7
+
+#define ADMUXA  _SFR_IO8(0x09)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define MUX5    5
+
+#define ACSR0A  _SFR_IO8(0x0A)
+#define ACIS00  0
+#define ACIS01  1
+#define ACIC0   2
+#define ACIE0   3
+#define ACI0    4
+#define ACO0    5
+#define ACPMUX2 6
+#define ACD0    7
+
+#define ACSR0B  _SFR_IO8(0x0B)
+#define ACPMUX0 0
+#define ACPMUX1 1
+#define ACNMUX0 2
+#define ACNMUX1 3
+#define ACOE0   4
+#define HLEV0   6
+#define HSEL0   7
+
+#define ACSR1A  _SFR_IO8(0x0C)
+#define ACIS10  0
+#define ACIS11  1
+#define ACIC1   2
+#define ACIE1   3
+#define ACI1    4
+#define ACO1    5
+#define ACBG1   6
+#define ACD1    7
+
+#define ACSR1B  _SFR_IO8(0x0D)
+#define ACME1   2
+#define ACOE1   4
+#define HLEV1   6
+#define HSEL1   7
+
+#define TIFR1   _SFR_IO8(0x0E)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIMSK1  _SFR_IO8(0x0F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIFR2   _SFR_IO8(0x10)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+#define ICF2    5
+
+#define TIMSK2  _SFR_IO8(0x11)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+#define ICIE2   5
+
+#define PCMSK0  _SFR_IO8(0x12)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define GPIOR0  _SFR_IO8(0x13)
+
+#define GPIOR1  _SFR_IO8(0x14)
+
+#define GPIOR2  _SFR_IO8(0x15)
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define EECR    _SFR_IO8(0x1C)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x1D)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x1E)
+
+#define EEARL   _SFR_IO8(0x1E)
+#define EEARH   _SFR_IO8(0x1F)
+
+#define PCMSK1  _SFR_IO8(0x20)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+
+#define WDTCSR  _SFR_IO8(0x21)
+#define WDE     3
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define TCCR1C  _SFR_IO8(0x22)
+#define FOC1B   6
+#define FOC1A   7
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSR     0
+#define TSM     7
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_IO16(0x24)
+
+#define ICR1L   _SFR_IO8(0x24)
+#define ICR1H   _SFR_IO8(0x25)
+
+/* Reserved [0x26..0x27] */
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_IO16(0x28)
+
+#define OCR1BL  _SFR_IO8(0x28)
+#define OCR1BH  _SFR_IO8(0x29)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_IO16(0x2A)
+
+#define OCR1AL  _SFR_IO8(0x2A)
+#define OCR1AH  _SFR_IO8(0x2B)
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_IO16(0x2C)
+
+#define TCNT1L  _SFR_IO8(0x2C)
+#define TCNT1H  _SFR_IO8(0x2D)
+
+#define TCCR1B  _SFR_IO8(0x2E)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1A  _SFR_IO8(0x2F)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR0A  _SFR_IO8(0x30)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+/* Reserved [0x31] */
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define ISC00   0
+#define ISC01   1
+#define SM0     3
+#define SM1     4
+#define SE      5
+
+#define OCR0A   _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define RFLB    3
+#define CTPB    4
+#define RSIG    5
+
+#define TIFR0   _SFR_IO8(0x38)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIMSK0  _SFR_IO8(0x39)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define GIFR    _SFR_IO8(0x3A)
+#define PCIF0   4
+#define PCIF1   5
+#define INTF0   6
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define PCIE0   4
+#define PCIE1   5
+#define INT0    6
+
+#define OCR0B   _SFR_IO8(0x3C)
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define DIDR0   _SFR_MEM8(0x60)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x61)
+#define ADC11D  0
+#define ADC10D  1
+#define ADC8D   2
+#define ADC9D   3
+
+#define PUEB    _SFR_MEM8(0x62)
+#define PUEB3   3
+#define PUEB2   2
+#define PUEB1   1
+#define PUEB0   0
+
+#define PUEA    _SFR_MEM8(0x63)
+#define PUEA7   7
+#define PUEA6   6
+#define PUEA5   5
+#define PUEA4   4
+#define PUEA3   3
+#define PUEA2   2
+#define PUEA1   1
+#define PUEA0   0
+
+#define PORTCR  _SFR_MEM8(0x64)
+#define BBMB    1
+#define BBMA    0
+
+#define REMAP   _SFR_MEM8(0x65)
+#define U0MAP   0
+#define SPIMAP  1
+
+#define TOCPMCOE _SFR_MEM8(0x66)
+#define TOCC0OE 0
+#define TOCC1OE 1
+#define TOCC2OE 2
+#define TOCC3OE 3
+#define TOCC4OE 4
+#define TOCC5OE 5
+#define TOCC6OE 6
+#define TOCC7OE 7
+
+#define TOCPMSA0 _SFR_MEM8(0x67)
+#define TOCC0S0 0
+#define TOCC0S1 1
+#define TOCC1S0 2
+#define TOCC1S1 3
+#define TOCC2S0 4
+#define TOCC2S1 5
+#define TOCC3S0 6
+#define TOCC3S1 7
+
+#define TOCPMSA1 _SFR_MEM8(0x68)
+#define TOCC4S0 0
+#define TOCC4S1 1
+#define TOCC5S0 2
+#define TOCC5S1 3
+#define TOCC6S0 4
+#define TOCC6S1 5
+#define TOCC7S0 6
+#define TOCC7S1 7
+
+/* Reserved [0x69] */
+
+#define PHDE    _SFR_MEM8(0x6A)
+#define PHDEA0  0
+#define PHDEA1  1
+
+/* Reserved [0x6B..0x6F] */
+
+#define PRR     _SFR_MEM8(0x70)
+#define PRADC   0
+#define PRTIM0  1
+#define PRTIM1  2
+#define PRTIM2  3
+#define PRSPI   4
+#define PRUSART0 5
+#define PRUSART1 6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRUSART1
+#define __AVR_HAVE_PRR_PRTWI
+
+#define CCP     _SFR_MEM8(0x71)
+
+#define CLKCR   _SFR_MEM8(0x72)
+#define CKSEL0  0
+#define CKSEL1  1
+#define CKSEL2  2
+#define CKSEL3  3
+#define SUT     4
+#define CKOUTC  5
+#define CSTR    6
+#define OSCRDY  7
+
+#define CLKPR   _SFR_MEM8(0x73)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+
+#define OSCCAL0 _SFR_MEM8(0x74)
+
+#define OSCTCAL0A _SFR_MEM8(0x75)
+
+#define OSCTCAL0B _SFR_MEM8(0x76)
+
+#define OSCCAL1 _SFR_MEM8(0x77)
+
+/* Reserved [0x78..0x7F] */
+
+#define UDR0    _SFR_MEM8(0x80)
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0x81)
+
+#define UBRR0L  _SFR_MEM8(0x81)
+#define UBRR0H  _SFR_MEM8(0x82)
+
+#define UCSR0D  _SFR_MEM8(0x83)
+#define SFDE0   5
+#define RXS0    6
+#define RXSIE0  7
+
+#define UCSR0C  _SFR_MEM8(0x84)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+#define UCSR0B  _SFR_MEM8(0x85)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0A  _SFR_MEM8(0x86)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+/* Reserved [0x87..0x8F] */
+
+#define UDR1    _SFR_MEM8(0x90)
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0x91)
+
+#define UBRR1L  _SFR_MEM8(0x91)
+#define UBRR1H  _SFR_MEM8(0x92)
+
+#define UCSR1D  _SFR_MEM8(0x93)
+#define SFDE1   5
+#define RXS1    6
+#define RXSIE1  7
+
+#define UCSR1C  _SFR_MEM8(0x94)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+
+#define UCSR1B  _SFR_MEM8(0x95)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1A  _SFR_MEM8(0x96)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+/* Reserved [0x97..0x9F] */
+
+#define TWSD    _SFR_MEM8(0xA0)
+#define TWSD0   0
+#define TWSD1   1
+#define TWSD2   2
+#define TWSD3   3
+#define TWSD4   4
+#define TWSD5   5
+#define TWSD6   6
+#define TWSD7   7
+
+#define TWSAM   _SFR_MEM8(0xA1)
+#define TWAE    0
+#define TWSAM1  1
+#define TWSAM2  2
+#define TWSAM3  3
+#define TWSAM4  4
+#define TWSAM5  5
+#define TWSAM6  6
+#define TWSAM7  7
+
+#define TWSA    _SFR_MEM8(0xA2)
+
+#define TWSSRA  _SFR_MEM8(0xA3)
+#define TWAS    0
+#define TWDIR   1
+#define TWBE    2
+#define TWC     3
+#define TWRA    4
+#define TWCH    5
+#define TWASIF  6
+#define TWDIF   7
+
+#define TWSCRB  _SFR_MEM8(0xA4)
+#define TWCMD0  0
+#define TWCMD1  1
+#define TWAA    2
+#define TWHNM   3
+
+#define TWSCRA  _SFR_MEM8(0xA5)
+#define TWSME   0
+#define TWPME   1
+#define TWSIE   2
+#define TWEN    3
+#define TWASIE  4
+#define TWDIE   5
+#define TWSHE   7
+
+/* Reserved [0xA6..0xAF] */
+
+#define SPDR    _SFR_MEM8(0xB0)
+
+#define SPSR    _SFR_MEM8(0xB1)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPCR    _SFR_MEM8(0xB2)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+/* Reserved [0xB3..0xBF] */
+
+/* Combine ICR2L and ICR2H */
+#define ICR2    _SFR_MEM16(0xC0)
+
+#define ICR2L   _SFR_MEM8(0xC0)
+#define ICR2H   _SFR_MEM8(0xC1)
+
+/* Combine OCR2BL and OCR2BH */
+#define OCR2B   _SFR_MEM16(0xC2)
+
+#define OCR2BL  _SFR_MEM8(0xC2)
+#define OCR2BH  _SFR_MEM8(0xC3)
+
+/* Combine OCR2AL and OCR2AH */
+#define OCR2A   _SFR_MEM16(0xC4)
+
+#define OCR2AL  _SFR_MEM8(0xC4)
+#define OCR2AH  _SFR_MEM8(0xC5)
+
+/* Combine TCNT2L and TCNT2H */
+#define TCNT2   _SFR_MEM16(0xC6)
+
+#define TCNT2L  _SFR_MEM8(0xC6)
+#define TCNT2H  _SFR_MEM8(0xC7)
+
+#define TCCR2C  _SFR_MEM8(0xC8)
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCCR2B  _SFR_MEM8(0xC9)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define WGM23   4
+#define ICES2   6
+#define ICNC2   7
+
+#define TCCR2A  _SFR_MEM8(0xCA)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<3)
+#define SLEEP_MODE_ADC (0x01<<3)
+#define SLEEP_MODE_PWR_DOWN (0x02<<3)
+#define SLEEP_MODE_STANDBY (0x03<<3)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(2)
+#define PCINT0_vect_num        2
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(3)
+#define PCINT1_vect_num        3
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(4)
+#define WDT_vect_num        4
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(5)
+#define TIMER1_CAPT_vect_num        5
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(6)
+#define TIMER1_COMPA_vect_num        6
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(7)
+#define TIMER1_COMPB_vect_num        7
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(8)
+#define TIMER1_OVF_vect_num        8
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(9)
+#define TIMER0_COMPA_vect_num        9
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(10)
+#define TIMER0_COMPB_vect_num        10
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(11)
+#define TIMER0_OVF_vect_num        11
+
+/* Analog Comparator 0 */
+#define ANA_COMP0_vect            _VECTOR(12)
+#define ANA_COMP0_vect_num        12
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(13)
+#define ADC_vect_num        13
+
+/* EEPROM Ready */
+#define EE_RDY_vect            _VECTOR(14)
+#define EE_RDY_vect_num        14
+
+/* Analog Comparator 1 */
+#define ANA_COMP1_vect            _VECTOR(15)
+#define ANA_COMP1_vect_num        15
+
+/* Timer/Counter2 Capture Event */
+#define TIMER2_CAPT_vect            _VECTOR(16)
+#define TIMER2_CAPT_vect_num        16
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(17)
+#define TIMER2_COMPA_vect_num        17
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect            _VECTOR(18)
+#define TIMER2_COMPB_vect_num        18
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(19)
+#define TIMER2_OVF_vect_num        19
+
+/* Serial Peripheral Interface */
+#define SPI_vect            _VECTOR(20)
+#define SPI_vect_num        20
+
+/* USART0, Start */
+#define USART0_START_vect            _VECTOR(21)
+#define USART0_START_vect_num        21
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect            _VECTOR(22)
+#define USART0_RX_vect_num        22
+
+/* USART0 Data Register Empty */
+#define USART0_UDRE_vect            _VECTOR(23)
+#define USART0_UDRE_vect_num        23
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect            _VECTOR(24)
+#define USART0_TX_vect_num        24
+
+/* USART1, Start */
+#define USART1_START_vect            _VECTOR(25)
+#define USART1_START_vect_num        25
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect            _VECTOR(26)
+#define USART1_RX_vect_num        26
+
+/* USART1 Data Register Empty */
+#define USART1_UDRE_vect            _VECTOR(27)
+#define USART1_UDRE_vect_num        27
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect            _VECTOR(28)
+#define USART1_TX_vect_num        28
+
+/* Two-wire Serial Interface */
+#define TWI_SLAVE_vect            _VECTOR(29)
+#define TWI_SLAVE_vect_num        29
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 60
+#else
+#  define _VECTORS_SIZE 60U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 16
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x0FFF
+#else
+#  define SPM_PAGESIZE 16U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x0FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      256
+#  define RAMEND       0x01FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      256U
+#  define RAMEND       0x01FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      256
+#  define E2PAGESIZE  4
+#  define E2END       0x00FF
+#else
+#  define E2START     0U
+#  define E2SIZE      256U
+#  define E2PAGESIZE  4U
+#  define E2END       0x00FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define FUSE_BODACT0     (unsigned char)~_BV(1)
+#define FUSE_BODACT1     (unsigned char)~_BV(2)
+#define FUSE_BODPD0      (unsigned char)~_BV(3)
+#define FUSE_BODPD1      (unsigned char)~_BV(4)
+#define FUSE_ULPOSCSEL0  (unsigned char)~_BV(5)
+#define FUSE_ULPOSCSEL1  (unsigned char)~_BV(6)
+#define FUSE_ULPOSCSEL2  (unsigned char)~_BV(7)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x92
+#define SIGNATURE_2 0x15
+
+
+
+
+#endif /* #ifdef _AVR_ATTINY441_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn44a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn44a.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn44a.h 2035 2009-11-02 02:44:17Z arcanum $ */
 
 /* avr/iotn44a.h - definitions for ATtiny44A */
 
@@ -835,7 +835,6 @@
 #define PCINT5_PIN   PINA
 #define PCINT5_BIT   5
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn45.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn45.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005, Joerg Wunsch
+/* Copyright (c) 2005, Joerg Wunsch, 2005,2007 Anatoly Sokolov
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,14 +28,417 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn45.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 /* avr/iotn45.h - definitions for ATtiny45 */
 
 #ifndef _AVR_IOTN45_H_
 #define _AVR_IOTN45_H_ 1
 
-#include <avr/iotnx5.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx5.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* I/O registers */
+
+/* Reserved [0x00..0x02] */
+
+#define ADCSRB  _SFR_IO8 (0x03)
+#define BIN     7
+#define ACME    6
+#define IPR     5
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+#define ADCW    _SFR_IO16(0x04)
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8 (0x06)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADMUX   _SFR_IO8(0x07)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define REFS2   4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define ACSR    _SFR_IO8(0x08)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIS1   1
+#define ACIS0   0
+
+/* Reserved [0x09..0x0C] */
+
+#define USICR   _SFR_IO8(0x0D)
+#define USISIE  7
+#define USIOIE  6
+#define USIWM1  5
+#define USIWM0  4
+#define USICS1  3
+#define USICS0  2
+#define USICLK  1
+#define USITC   0
+
+#define USISR   _SFR_IO8(0x0E)
+#define USISIF  7 
+#define USIOIF  6
+#define USIPF   5
+#define USIDC   4
+#define USICNT3 3
+#define USICNT2 2
+#define USICNT1 1
+#define USICNT0 0
+
+#define USIDR   _SFR_IO8(0x0F)
+#define USIBR   _SFR_IO8(0x10)
+
+#define GPIOR0  _SFR_IO8(0x11)
+#define GPIOR1  _SFR_IO8(0x12)
+#define GPIOR2  _SFR_IO8(0x13)
+
+#define DIDR0    _SFR_IO8(0x14)
+#define ADC0D   5
+#define ADC2D   4
+#define ADC3D   3
+#define ADC1D   2
+#define AIN1D   1 
+#define AIN0D   0
+
+#define PCMSK   _SFR_IO8(0x15)
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+/* Reserved [0x19..0x1B] */
+
+/* EEPROM Control Register EECR */
+#define EECR	_SFR_IO8(0x1C)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define PRR     _SFR_IO8(0x20)
+#define PRTIM1  3
+#define PRTIM0  2
+#define PRUSI   1
+#define PRADC   0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define WDTCR   _SFR_IO8(0x21)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define DWDR    _SFR_IO8(0x22)
+
+#define DTPS1   _SFR_IO8(0x23)
+#define DTPS11   1
+#define DTPS10   0
+
+#define DT1B    _SFR_IO8(0x24)
+#define DT1BH3  7
+#define DT1BH2  6
+#define DT1BH1  5
+#define DT1BH0  4
+#define DT1BL3  3
+#define DT1BL2  2
+#define DT1BL1  1
+#define DT1BL0  0
+
+#define DT1A    _SFR_IO8(0x25)
+#define DT1AH3  7
+#define DT1AH2  6
+#define DT1AH1  5
+#define DT1AH0  4
+#define DT1AL3  3
+#define DT1AL2  2
+#define DT1AL1  1
+#define DT1AL0  0
+
+#define CLKPR   _SFR_IO8(0x26)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define PLLCSR  _SFR_IO8(0x27)
+#define LSM     7
+#define PCKE    2
+#define PLLE    1
+#define PLOCK   0
+
+#define OCR0B   _SFR_IO8(0x28)
+
+#define OCR0A   _SFR_IO8(0x29)
+
+#define TCCR0A  _SFR_IO8(0x2A)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define OCR1B   _SFR_IO8(0x2B)
+
+#define GTCCR   _SFR_IO8(0x2C)
+#define TSM     7
+#define PWM1B   6
+#define COM1B1  5
+#define COM1B0  4
+#define FOC1B   3
+#define FOC1A   2
+#define PSR1    1
+#define PSR0    0
+
+#define OCR1C   _SFR_IO8(0x2D)
+
+#define OCR1A   _SFR_IO8(0x2E)
+
+#define TCNT1   _SFR_IO8(0x2F)
+
+#define TCCR1   _SFR_IO8(0x30)
+#define CTC1    7
+#define PWM1A   6
+#define COM1A1  5
+#define COM1A0  4
+#define CS13    3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define BODS    7
+#define PUD     6
+#define SE      5
+#define SM1     4
+#define SM0     3
+#define BODSE   2
+#define ISC01   1
+#define ISC00   0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define RSIG    5
+#define CTPB    4
+#define RFLB    3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+#define TIFR    _SFR_IO8(0x38)
+#define OCF1A   6
+#define OCF1B   5
+#define OCF0A   4
+#define OCF0B   3
+#define TOV1    2
+#define TOV0    1
+
+#define TIMSK   _SFR_IO8(0x39)
+#define OCIE1A  6
+#define OCIE1B  5
+#define OCIE0A  4
+#define OCIE0B  3
+#define TOIE1   2
+#define TOIE0   1
+
+#define GIFR    _SFR_IO8(0x3A)
+#define INTF0   6
+#define PCIF    5
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define INT0    6
+#define PCIE    5
+
+/* Reserved [0x3C] */
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+///---
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt 0 */
+#define INT0_vect_num	        1
+#define INT0_vect			    _VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin change Interrupt Request 0 */
+#define PCINT0_vect_num			2
+#define PCINT0_vect			    _VECTOR(2)
+#define SIG_PIN_CHANGE			_VECTOR(2)
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIM1_COMPA_vect_num		3
+#define TIM1_COMPA_vect			_VECTOR(3)
+#define TIMER1_COMPA_vect_num	3
+#define TIMER1_COMPA_vect		_VECTOR(3)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(3)
+
+/* Timer/Counter1 Overflow */
+#define TIM1_OVF_vect_num		4
+#define TIM1_OVF_vect			_VECTOR(4)
+#define TIMER1_OVF_vect_num		4
+#define TIMER1_OVF_vect			_VECTOR(4)
+#define SIG_OVERFLOW1			_VECTOR(4)
+
+/* Timer/Counter0 Overflow */
+#define TIM0_OVF_vect_num		5
+#define TIM0_OVF_vect			_VECTOR(5)
+#define TIMER0_OVF_vect_num		5
+#define TIMER0_OVF_vect			_VECTOR(5)
+#define SIG_OVERFLOW0			_VECTOR(5)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num			6
+#define EE_RDY_vect		    	_VECTOR(6)
+#define SIG_EEPROM_READY		_VECTOR(6)
+
+/* Analog comparator */
+#define ANA_COMP_vect_num		7
+#define ANA_COMP_vect			_VECTOR(7)
+#define SIG_COMPARATOR			_VECTOR(7)
+
+/* ADC Conversion ready */
+#define ADC_vect_num    		8
+#define ADC_vect		    	_VECTOR(8)
+#define SIG_ADC				    _VECTOR(8)
+
+/* Timer/Counter1 Compare Match B */
+#define TIM1_COMPB_vect_num  	9
+#define TIM1_COMPB_vect			_VECTOR(9)
+#define TIMER1_COMPB_vect_num	9
+#define TIMER1_COMPB_vect   	_VECTOR(9)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(9)
+
+/* Timer/Counter0 Compare Match A */
+#define TIM0_COMPA_vect_num		10
+#define TIM0_COMPA_vect			_VECTOR(10)
+#define TIMER0_COMPA_vect_num	10
+#define TIMER0_COMPA_vect		_VECTOR(10)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(10)
+
+/* Timer/Counter0 Compare Match B */
+#define TIM0_COMPB_vect_num		11
+#define TIM0_COMPB_vect			_VECTOR(11)
+#define TIMER0_COMPB_vect_num	11
+#define TIMER0_COMPB_vect		_VECTOR(11)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(11)
+
+/* Watchdog Time-out */
+#define WDT_vect_num			12
+#define WDT_vect				_VECTOR(12)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(12)
+
+/* USI START */
+#define USI_START_vect_num		13
+#define USI_START_vect			_VECTOR(13)
+#define SIG_USI_START			_VECTOR(13)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		14
+#define USI_OVF_vect			_VECTOR(14)
+#define SIG_USI_OVERFLOW		_VECTOR(14)
+
+#define _VECTORS_SIZE 30
+
 
 /* Constants */
 #define SPM_PAGESIZE 64
@@ -86,10 +489,8 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x06
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 
-
 #endif /* _AVR_IOTN45_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn461.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn461.h
@@ -28,14 +28,516 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn461.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 /* avr/iotn461.h - definitions for ATtiny461 */
 
 #ifndef _AVR_IOTN461_H_
 #define _AVR_IOTN461_H_ 1
 
-#include <avr/iotnx61.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx61.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define TCCR1E  _SFR_IO8(0x00)
+#define OC1OE0  0
+#define OC1OE1  1
+#define OC1OE2  2
+#define OC1OE3  3
+#define OC1OE4  4
+#define OC1OE5  5
+
+#define DIDR0   _SFR_IO8(0x01)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define AREFD   3
+#define ADC3D   4
+#define ADC4D   5
+#define ADC5D   6
+#define ADC6D   7
+
+#define DIDR1   _SFR_IO8(0x02)
+#define ADC7D   4
+#define ADC8D   5
+#define ADC9D   6
+#define ADC10D  7
+
+#define ADCSRB  _SFR_IO8(0x03)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define MUX5    3
+#define REFS2   4
+#define IRP     5
+#define GSEL    6
+#define BIN     7
+
+#define ADCW    _SFR_IO16(0x04)
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8(0x06)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADMUX   _SFR_IO8(0x07)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define ACSRA   _SFR_IO8(0x08)
+#define ACIS0   0
+#define ACIS1   1
+#define ACME    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define ACSRB   _SFR_IO8(0x09)
+#define ACM0    0
+#define ACM1    1
+#define ACM2    2
+#define HLEV    6
+#define HSEL    7
+
+#define GPIOR0  _SFR_IO8(0x0A)
+
+#define GPIOR1  _SFR_IO8(0x0B)
+
+#define GPIOR2  _SFR_IO8(0x0C)
+
+#define USICR   _SFR_IO8(0x0D)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_IO8(0x0F)
+
+#define USIBR   _SFR_IO8(0x10)
+
+#define USIPP   _SFR_IO8(0x11)
+#define USIPOS  0
+
+#define OCR0B   _SFR_IO8(0x12)
+
+#define OCR0A   _SFR_IO8(0x13)
+
+#define TCNT0H  _SFR_IO8(0x14)
+
+#define TCCR0A  _SFR_IO8(0x15)
+#define WGM00   0		/* up to at least datasheet rev. B */
+#define CTC0    0		/* newer revisions; change not mentioned
+				 * in revision history */
+#define ACIC0   3
+#define ICES0   4
+#define ICNC0   5
+#define ICEN0   6
+#define TCW0    7
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB0   0
+#define PINB1   1
+#define PINB2   2
+#define PINB3   3
+#define PINB4   4
+#define PINB5   5
+#define PINB6   6
+#define PINB7   7
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB0    0
+#define DDB1    1
+#define DDB2    2
+#define DDB3    3
+#define DDB4    4
+#define DDB5    5
+#define DDB6    6
+#define DDB7    7
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB0     0
+#define PB1     1
+#define PB2     2
+#define PB3     3
+#define PB4     4
+#define PB5     5
+#define PB6     6
+#define PB7     7
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA0   0
+#define PINA1   1
+#define PINA2   2
+#define PINA3   3
+#define PINA4   4
+#define PINA5   5
+#define PINA6   6
+#define PINA7   7
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDA0    0
+#define DDA1    1
+#define DDA2    2
+#define DDA3    3
+#define DDA4    4
+#define DDA5    5
+#define DDA6    6
+#define DDA7    7
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PA0     0
+#define PA1     1
+#define PA2     2
+#define PA3     3
+#define PA4     4
+#define PA5     5
+#define PA6     6
+#define PA7     7
+
+/* EEPROM Control Register */
+#define EECR	_SFR_IO8(0x1C)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define DWDR    _SFR_IO8(0x20)
+
+#define WDTCR   _SFR_IO8(0x21)
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDE     3
+#define WDCE    4
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define PCMSK1  _SFR_IO8(0x22)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK0  _SFR_IO8(0x23)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define DT1     _SFR_IO8(0x24)
+#define DT1L0   0
+#define DT1L1   1
+#define DT1L2   2
+#define DT1L3   3
+#define DT1H0   4
+#define DT1H1   5
+#define DT1H2   6
+#define DT1H3   7
+
+#define TC1H    _SFR_IO8(0x25)
+#define TC18    0
+#define TC19    1
+
+#define TCCR1D  _SFR_IO8(0x26)
+#define WGM10   0
+#define WGM11   1
+#define FPF1    2
+#define FPAC1   3
+#define FPES1   4
+#define FPNC1   5
+#define FPEN1   6
+#define FPIE1   7
+
+#define TCCR1C  _SFR_IO8(0x27)
+#define PWM1D   0
+#define FOC1D   1
+#define COM1D0  2
+#define COM1D1  3
+#define COM1B0S 4
+#define COM1B1S 5
+#define COM1A0S 6
+#define COM1A1S 7
+
+#define CLKPR   _SFR_IO8(0x28)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLOCK   0
+#define PLLE    1
+#define PCKE    2
+#define LSM     7
+
+#define OCR1D   _SFR_IO8(0x2A)
+
+#define OCR1C   _SFR_IO8(0x2B)
+
+#define OCR1B   _SFR_IO8(0x2C)
+
+#define OCR1A   _SFR_IO8(0x2D)
+
+#define TCNT1   _SFR_IO8(0x2E)
+
+#define TCCR1B  _SFR_IO8(0x2F)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define CS13    3
+#define DTPS10  4
+#define DTPS11  5
+#define PSR1    6
+#define PWM1X   7
+
+#define TCCR1A  _SFR_IO8(0x30)
+#define PWM1B   0
+#define PWM1A   1
+#define FOC1B   2
+#define FOC1A   3
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0L  _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define PSR0    3
+#define TSM     4
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define ISC00   0
+#define ISC01   1
+#define SM0     3
+#define SM1     4
+#define SE      5
+#define PUD     6
+
+#define PRR     _SFR_IO8(0x36)
+#define PRADC   0
+#define PRUSI   1
+#define PRTIM0  2
+#define PRTIM1  3
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR    _SFR_IO8(0x38)
+#define ICF0    0
+#define TOV0    1
+#define TOV1    2
+#define OCF0B   3
+#define OCF0A   4
+#define OCF1B   5
+#define OCF1A   6
+#define OCF1D   7
+
+#define TIMSK   _SFR_IO8(0x39)
+#define TICIE0  0
+#define TOIE0   1
+#define TOIE1   2
+#define OCIE0B  3
+#define OCIE0A  4
+#define OCIE1B  5
+#define OCIE1A  6
+#define OCIE1D  7
+
+#define GIFR    _SFR_IO8(0x3A)
+#define PCIF    5
+#define INTF0   6
+#define INTF1   7
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define PCIE0   4
+#define PCIE1   5
+#define INT0    6
+#define INT1    7
+
+/* Reserved [0x3C] */
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt 0 */
+#define INT0_vect_num			1
+#define INT0_vect	    		_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin Change Interrupt */
+#define PCINT_vect_num			2
+#define PCINT_vect		    	_VECTOR(2)
+#define SIG_PIN_CHANGE			_VECTOR(2)
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPA_vect_num	3
+#define TIMER1_COMPA_vect		_VECTOR(3)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(3)
+
+/* Timer/Counter1 Compare Match 1B */
+#define TIMER1_COMPB_vect_num	4
+#define TIMER1_COMPB_vect	    _VECTOR(4)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(4)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		5
+#define TIMER1_OVF_vect			_VECTOR(5)
+#define SIG_OVERFLOW1			_VECTOR(5)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num 	6
+#define TIMER0_OVF_vect			_VECTOR(6)
+#define SIG_OVERFLOW0			_VECTOR(6)
+
+/* USI Start */
+#define USI_START_vect_num		7
+#define USI_START_vect			_VECTOR(7)
+#define SIG_USI_START			_VECTOR(7)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		8
+#define USI_OVF_vect			_VECTOR(8)
+#define SIG_USI_OVERFLOW		_VECTOR(8)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num			9
+#define EE_RDY_vect		    	_VECTOR(9)
+#define SIG_EEPROM_READY		_VECTOR(9)
+
+/* Analog Comparator */
+#define ANA_COMP_vect_num   	10
+#define ANA_COMP_vect			_VECTOR(10)
+#define SIG_ANA_COMP			_VECTOR(10)
+#define SIG_COMPARATOR			_VECTOR(10)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			11
+#define ADC_vect	    		_VECTOR(11)
+#define SIG_ADC			    	_VECTOR(11)
+
+/* Watchdog Time-Out */
+#define WDT_vect_num			12
+#define WDT_vect	    		_VECTOR(12)
+#define SIG_WDT			    	_VECTOR(12)
+
+/* External Interrupt 1 */
+#define INT1_vect_num			13
+#define INT1_vect	    		_VECTOR(13)
+#define SIG_INTERRUPT1			_VECTOR(13)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num		14
+#define TIMER0_COMPA_vect	    	_VECTOR(14)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(14)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num		15
+#define TIMER0_COMPB_vect	    	_VECTOR(15)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(15)
+
+/* ADC Conversion Complete */
+#define TIMER0_CAPT_vect_num		16
+#define TIMER0_CAPT_vect	    	_VECTOR(16)
+#define SIG_INPUT_CAPTURE0		    _VECTOR(16)
+
+/* Timer/Counter1 Compare Match D */
+#define TIMER1_COMPD_vect_num       17
+#define TIMER1_COMPD_vect		    _VECTOR(17)
+#define SIG_OUTPUT_COMPARE0D		_VECTOR(17)
+
+/* Timer/Counter1 Fault Protection */
+#define FAULT_PROTECTION_vect_num	18
+#define FAULT_PROTECTION_vect		_VECTOR(18)
+
+#define _VECTORS_SIZE 38
+
 
 /* Constants */
 #define SPM_PAGESIZE 64
@@ -86,11 +588,9 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x08
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 #define SLEEP_MODE_STANDBY (0x03<<3)
 
-
 #endif /* _AVR_IOTN461_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn461a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn461a.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn461a.h 2063 2009-11-18 22:06:28Z arcanum $ */
 
 /* avr/iotn461a.h - definitions for ATtiny461A */
 
@@ -496,6 +496,7 @@
 #define DTPS10 4
 #define DTPS11 5
 #define PSR1 6
+#define PWM1X 7
 
 #define TCCR1A _SFR_IO8(0x30)
 #define PWM1B 0
@@ -978,7 +979,6 @@
 #define PA0_PIN   PINADC
 #define PA0_BIT   ADC0
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn48.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn48.h
@@ -29,7 +29,7 @@
   POSSIBILITY OF SUCH DAMAGE. 
 */
 
-/* $Id$ */
+/* $Id: iotn48.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/iotn48.h - definitions for ATtiny48 */
 
@@ -798,11 +798,9 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x09
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 
-
 #endif /* _AVR_IOTN48_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn5.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn5.h
@@ -503,7 +503,6 @@
 #define PB3_PIN   PINRESET
 #define PB3_BIT   RESET
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn828.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn828.h
@@ -1,39 +1,22 @@
 /*****************************************************************************
  *
- * Copyright (C) 2014 Atmel Corporation
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
+ *   http://www.apache.org/licenses/LICENSE-2.0
  *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ****************************************************************************/
 
 
-/* $Id$ */
-
 #ifndef _AVR_ATTINY828_H_INCLUDED
 #define _AVR_ATTINY828_H_INCLUDED
 
@@ -62,13 +45,29 @@
 
 #define DDRA    _SFR_IO8(0x01)
 #define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
 #define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
 #define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
 #define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
 #define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
 #define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
 #define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
 #define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
 
 #define PORTA   _SFR_IO8(0x02)
 #define PORTA7  7
@@ -81,6 +80,14 @@
 #define PORTA0  0
 
 #define PUEA    _SFR_IO8(0x03)
+#define PUEA7   7
+#define PUEA6   6
+#define PUEA5   5
+#define PUEA4   4
+#define PUEA3   3
+#define PUEA2   2
+#define PUEA1   1
+#define PUEA0   0
 
 #define PINB    _SFR_IO8(0x04)
 #define PINB7   7
@@ -94,13 +101,29 @@
 
 #define DDRB    _SFR_IO8(0x05)
 #define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
 #define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
 #define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
 #define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
 #define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
 #define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
 #define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
 #define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
 
 #define PORTB   _SFR_IO8(0x06)
 #define PORTB7  7
@@ -113,6 +136,14 @@
 #define PORTB0  0
 
 #define PUEB    _SFR_IO8(0x07)
+#define PUEB7   7
+#define PUEB6   6
+#define PUEB5   5
+#define PUEB4   4
+#define PUEB3   3
+#define PUEB2   2
+#define PUEB1   1
+#define PUEB0   0
 
 #define PINC    _SFR_IO8(0x08)
 #define PINC7   7
@@ -126,13 +157,29 @@
 
 #define DDRC    _SFR_IO8(0x09)
 #define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
 #define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
 #define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
 #define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
 #define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
 #define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
 #define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
 #define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
 
 #define PORTC   _SFR_IO8(0x0A)
 #define PORTC7  7
@@ -145,6 +192,14 @@
 #define PORTC0  0
 
 #define PUEC    _SFR_IO8(0x0B)
+#define PUEC7   7
+#define PUEC6   6
+#define PUEC5   5
+#define PUEC4   4
+#define PUEC3   3
+#define PUEC2   2
+#define PUEC1   1
+#define PUEC0   0
 
 #define PIND    _SFR_IO8(0x0C)
 #define PIND3   3
@@ -154,9 +209,17 @@
 
 #define DDRD    _SFR_IO8(0x0D)
 #define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
 #define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
 #define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
 #define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
 
 #define PORTD   _SFR_IO8(0x0E)
 #define PORTD3  3
@@ -165,6 +228,10 @@
 #define PORTD0  0
 
 #define PUED    _SFR_IO8(0x0F)
+#define PUED3   3
+#define PUED2   2
+#define PUED1   1
+#define PUED0   0
 
 /* Reserved [0x10..0x13] */
 
@@ -676,6 +743,13 @@
 
 
 
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
@@ -778,21 +852,44 @@
 #define QTRIP_vect            _VECTOR(25)
 #define QTRIP_vect_num        25
 
-#define _VECTORS_SIZE 52
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 52
+#else
+#  define _VECTORS_SIZE 52U
+#endif
 
 
 /* Constants */
 
-#define SPM_PAGESIZE 64
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      256
-#define E2PAGESIZE  4
-#define E2END       0x00FF
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 64
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFF
+#else
+#  define SPM_PAGESIZE 64U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      256
+#  define E2PAGESIZE  4
+#  define E2END       0x00FF
+#else
+#  define E2START     0U
+#  define E2SIZE      256U
+#  define E2PAGESIZE  4U
+#  define E2END       0x00FFU
+#endif
 #define XRAMEND      RAMEND
 
 
@@ -803,8 +900,12 @@
 /* Low Fuse Byte */
 #define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
 #define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_CKDIV8)
+
 
 /* High Fuse Byte */
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
@@ -815,6 +916,8 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_DWEN        (unsigned char)~_BV(6)
 #define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
 
 /* Extended Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -824,6 +927,8 @@
 #define FUSE_BODACT1     (unsigned char)~_BV(5)
 #define FUSE_BODPD0      (unsigned char)~_BV(6)
 #define FUSE_BODPD1      (unsigned char)~_BV(7)
+#define EFUSE_DEFAULT    (0xFF)
+
 
 
 /* Lock Bits */
@@ -839,9 +944,6 @@
 
 
 
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_ADC (0x01<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
 
 #endif /* #ifdef _AVR_ATTINY828_H_INCLUDED */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn84.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn84.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005, Anatoly Sokolov
+/* Copyright (c) 2005, 2007 Anatoly Sokolov
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,14 +28,457 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn84.h 2417 2014-04-16 11:34:47Z pitchumani $ */
 
 /* avr/iotn84.h - definitions for ATtiny84 */
 
 #ifndef _AVR_IOTN84_H_
 #define _AVR_IOTN84_H_ 1
 
-#include <avr/iotnx4.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx4.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* I/O registers */
+
+#define PRR     _SFR_IO8 (0x00)
+#define PRTIM1  3
+#define PRTIM0  2
+#define PRUSI   1
+#define PRADC   0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define DIDR0    _SFR_IO8(0x01)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1 
+#define ADC0D   0
+
+/* Reserved [0x02] */
+
+#define ADCSRB  _SFR_IO8 (0x03)
+#define BIN     7
+#define ACME    6
+#define ADLAR   4
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+#define ADCW    _SFR_IO16(0x04)
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8 (0x06)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADMUX   _SFR_IO8(0x07)
+#define REFS1   7
+#define REFS0   6
+#define MUX5    5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define ACSR    _SFR_IO8(0x08)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+/* Reserved [0x09..0x0A] */
+
+#define TIFR1   _SFR_IO8(0x0B)
+#define ICF1    5
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIMSK1   _SFR_IO8(0x0C)
+#define ICIE1   5
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define USICR   _SFR_IO8(0x0D)
+#define USISIE  7
+#define USIOIE  6
+#define USIWM1  5
+#define USIWM0  4
+#define USICS1  3
+#define USICS0  2
+#define USICLK  1
+#define USITC   0
+
+#define USISR   _SFR_IO8(0x0E)
+#define USISIF  7 
+#define USIOIF  6
+#define USIPF   5
+#define USIDC   4
+#define USICNT3 3
+#define USICNT2 2
+#define USICNT1 1
+#define USICNT0 0
+
+#define USIDR   _SFR_IO8(0x0F)
+
+#define USIBR   _SFR_IO8(0x10)
+
+/* Reserved [0x11] */
+
+#define PCMSK0  _SFR_IO8(0x12)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define GPIOR0  _SFR_IO8(0x13)
+
+#define GPIOR1  _SFR_IO8(0x14)
+
+#define GPIOR2  _SFR_IO8(0x15)
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PA7     7
+#define PA6     6
+#define PA5     5
+#define PA4     4
+#define PA3     3
+#define PA2     2
+#define PA1     1
+#define PA0     0
+
+/* EEPROM Control Register EECR */
+#define EECR	_SFR_IO8(0x1C)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define PCMSK1  _SFR_IO8(0x20)
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+#define WDTCSR _SFR_IO8(0x21)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define TCCR1C  _SFR_IO8(0x22)
+#define FOC1A   7
+#define FOC1B   6
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSR10   0
+
+#define ICR1    _SFR_IO16(0x24)
+#define ICR1L   _SFR_IO8(0x24)
+#define ICR1H   _SFR_IO8(0x25)
+
+#define CLKPR   _SFR_IO8(0x26)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define DWDR    _SFR_IO8(0x27)
+
+#define OCR1B   _SFR_IO16(0x28)
+#define OCR1BL  _SFR_IO8(0x28)
+#define OCR1BH  _SFR_IO8(0x29)
+
+#define OCR1A   _SFR_IO16(0x2A)
+#define OCR1AL  _SFR_IO8(0x2A)
+#define OCR1AH  _SFR_IO8(0x2B)
+
+/* keep misspelled names from avr-libc 1.4.[0..1] for compatibility */
+#define OCRB1   _SFR_IO16(0x28)
+#define OCRB1L  _SFR_IO8(0x28)
+#define OCRB1H  _SFR_IO8(0x29)
+
+#define OCRA1   _SFR_IO16(0x2A)
+#define OCRA1L  _SFR_IO8(0x2A)
+#define OCRA1H  _SFR_IO8(0x2B)
+
+#define TCNT1   _SFR_IO16(0x2C)
+#define TCNT1L  _SFR_IO8(0x2C)
+#define TCNT1H  _SFR_IO8(0x2D)
+
+#define TCCR1B  _SFR_IO8(0x2E)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1A  _SFR_IO8(0x2F)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR0A  _SFR_IO8(0x30)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define BODS    7
+#define PUD     6
+#define SE      5
+#define SM1     4
+#define SM0     3
+#define BODSE   2
+#define ISC01   1
+#define ISC00   0
+
+#define OCR0A   _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define RSIG    5
+#define CTPB    4
+#define RFLB    3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+#define TIFR0   _SFR_IO8(0x38)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIMSK0  _SFR_IO8(0x39)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define GIFR    _SFR_IO8(0x3A)
+#define INTF0   6
+#define PCIF1   5
+#define PCIF0   4
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define INT0    6
+#define PCIE1   5
+#define PCIE0   4
+
+#define OCR0B   _SFR_IO8(0x3C)
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+///---
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt Request 0 */
+#define INT0_vect_num		    1
+#define INT0_vect			    _VECTOR(1)
+#define EXT_INT0_vect_num    	1
+#define EXT_INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		    2
+#define PCINT0_vect			    _VECTOR(2)
+#define SIG_PIN_CHANGE0			_VECTOR(2)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		    3
+#define PCINT1_vect			    _VECTOR(3)
+#define SIG_PIN_CHANGE1			_VECTOR(3)
+
+/* Watchdog Time-out */
+#define WDT_vect_num			4
+#define WDT_vect			    _VECTOR(4)
+#define WATCHDOG_vect_num		4
+#define WATCHDOG_vect			_VECTOR(4)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(4)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	5
+#define TIMER1_CAPT_vect		_VECTOR(5)
+#define TIM1_CAPT_vect_num		5
+#define TIM1_CAPT_vect			_VECTOR(5)
+#define SIG_INPUT_CAPTURE1		_VECTOR(5)
+
+/* Timer/Counter1 Compare Match A */
+#define TIM1_COMPA_vect_num		6
+#define TIM1_COMPA_vect			_VECTOR(6)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(6)
+
+/* Timer/Counter1 Compare Match B */
+#define TIM1_COMPB_vect_num		7
+#define TIM1_COMPB_vect			_VECTOR(7)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(7)
+
+/* Timer/Counter1 Overflow */
+#define TIM1_OVF_vect_num		8
+#define TIM1_OVF_vect			_VECTOR(8)
+#define SIG_OVERFLOW1			_VECTOR(8)
+
+/* Timer/Counter0 Compare Match A */
+#define TIM0_COMPA_vect_num		9
+#define TIM0_COMPA_vect			_VECTOR(9)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(9)
+
+/* Timer/Counter0 Compare Match B */
+#define TIM0_COMPB_vect_num		10
+#define TIM0_COMPB_vect			_VECTOR(10)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(10)
+
+/* Timer/Counter0 Overflow */
+#define TIM0_OVF_vect_num		11
+#define TIM0_OVF_vect			_VECTOR(11)
+#define SIG_OVERFLOW0			_VECTOR(11)
+
+/* Analog Comparator */
+#define ANA_COMP_vect_num		12
+#define ANA_COMP_vect			_VECTOR(12)
+#define SIG_COMPARATOR			_VECTOR(12)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		    13
+#define ADC_vect			    _VECTOR(13)
+#define SIG_ADC				    _VECTOR(13)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num		    14
+#define EE_RDY_vect			    _VECTOR(14)
+#define SIG_EEPROM_READY		_VECTOR(14)
+
+/* USI START */
+#define USI_START_vect_num		15
+#define USI_START_vect			_VECTOR(15)
+#define USI_STR_vect_num		15
+#define USI_STR_vect			_VECTOR(15)
+#define SIG_USI_START			_VECTOR(15)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		16
+#define USI_OVF_vect			_VECTOR(16)
+#define SIG_USI_OVERFLOW		_VECTOR(16)
+
+#define _VECTORS_SIZE 34
+
 
 /* Constants */
 #define SPM_PAGESIZE 64
@@ -86,11 +529,9 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x0C
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 #define SLEEP_MODE_STANDBY (0x03<<3)
 
-
 #endif /* _AVR_IOTN84_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn841.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn841.h
@@ -1,903 +1,925 @@
-/*****************************************************************************
- *
- * Copyright (C) 2016 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-#ifndef _AVR_ATTINY841_H_INCLUDED
-#define _AVR_ATTINY841_H_INCLUDED
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn841.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define ADCSRB  _SFR_IO8(0x04)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ADLAR   3
-
-#define ADCSRA  _SFR_IO8(0x05)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_IO16(0x06)
-#endif
-#define ADCW    _SFR_IO16(0x06)
-
-#define ADCL    _SFR_IO8(0x06)
-#define ADCH    _SFR_IO8(0x07)
-
-#define ADMUXB  _SFR_IO8(0x08)
-#define GSEL0   0
-#define GSEL1   1
-#define REFS0   5
-#define REFS1   6
-#define REFS2   7
-
-#define ADMUXA  _SFR_IO8(0x09)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define MUX5    5
-
-#define ACSR0A  _SFR_IO8(0x0A)
-#define ACIS00  0
-#define ACIS01  1
-#define ACIC0   2
-#define ACIE0   3
-#define ACI0    4
-#define ACO0    5
-#define ACPMUX2 6
-#define ACD0    7
-
-#define ACSR0B  _SFR_IO8(0x0B)
-#define ACPMUX0 0
-#define ACPMUX1 1
-#define ACNMUX0 2
-#define ACNMUX1 3
-#define ACOE0   4
-#define HLEV0   6
-#define HSEL0   7
-
-#define ACSR1A  _SFR_IO8(0x0C)
-#define ACIS10  0
-#define ACIS11  1
-#define ACIC1   2
-#define ACIE1   3
-#define ACI1    4
-#define ACO1    5
-#define ACBG1   6
-#define ACD1    7
-
-#define ACSR1B  _SFR_IO8(0x0D)
-#define ACME1   2
-#define ACOE1   4
-#define HLEV1   6
-#define HSEL1   7
-
-#define TIFR1   _SFR_IO8(0x0E)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIMSK1  _SFR_IO8(0x0F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIFR2   _SFR_IO8(0x10)
-#define TOV2    0
-#define OCF2A   1
-#define OCF2B   2
-#define ICF2    5
-
-#define TIMSK2  _SFR_IO8(0x11)
-#define TOIE2   0
-#define OCIE2A  1
-#define OCIE2B  2
-#define ICIE2   5
-
-#define PCMSK0  _SFR_IO8(0x12)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define GPIOR0  _SFR_IO8(0x13)
-
-#define GPIOR1  _SFR_IO8(0x14)
-
-#define GPIOR2  _SFR_IO8(0x15)
-
-#define PINB    _SFR_IO8(0x16)
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x17)
-#define DDRB3   3
-// Inserted "DDB3" from "DDRB3" due to compatibility
-#define DDB3    3
-#define DDRB2   2
-// Inserted "DDB2" from "DDRB2" due to compatibility
-#define DDB2    2
-#define DDRB1   1
-// Inserted "DDB1" from "DDRB1" due to compatibility
-#define DDB1    1
-#define DDRB0   0
-// Inserted "DDB0" from "DDRB0" due to compatibility
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x18)
-#define PORTB3  3
-#define PORTB2  2
-#define PORTB1  1
-#define PORTB0  0
-
-#define PINA    _SFR_IO8(0x19)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x1A)
-#define DDRA7   7
-// Inserted "DDA7" from "DDRA7" due to compatibility
-#define DDA7    7
-#define DDRA6   6
-// Inserted "DDA6" from "DDRA6" due to compatibility
-#define DDA6    6
-#define DDRA5   5
-// Inserted "DDA5" from "DDRA5" due to compatibility
-#define DDA5    5
-#define DDRA4   4
-// Inserted "DDA4" from "DDRA4" due to compatibility
-#define DDA4    4
-#define DDRA3   3
-// Inserted "DDA3" from "DDRA3" due to compatibility
-#define DDA3    3
-#define DDRA2   2
-// Inserted "DDA2" from "DDRA2" due to compatibility
-#define DDA2    2
-#define DDRA1   1
-// Inserted "DDA1" from "DDRA1" due to compatibility
-#define DDA1    1
-#define DDRA0   0
-// Inserted "DDA0" from "DDRA0" due to compatibility
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x1B)
-#define PORTA7  7
-#define PORTA6  6
-#define PORTA5  5
-#define PORTA4  4
-#define PORTA3  3
-#define PORTA2  2
-#define PORTA1  1
-#define PORTA0  0
-
-#define EECR    _SFR_IO8(0x1C)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-#define EEDR    _SFR_IO8(0x1D)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x1E)
-
-#define EEARL   _SFR_IO8(0x1E)
-#define EEARH   _SFR_IO8(0x1F)
-
-#define PCMSK1  _SFR_IO8(0x20)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-
-#define WDTCSR  _SFR_IO8(0x21)
-#define WDE     3
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define TCCR1C  _SFR_IO8(0x22)
-#define FOC1B   6
-#define FOC1A   7
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR     0
-#define TSM     7
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_IO16(0x24)
-
-#define ICR1L   _SFR_IO8(0x24)
-#define ICR1H   _SFR_IO8(0x25)
-
-/* Reserved [0x26..0x27] */
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_IO16(0x28)
-
-#define OCR1BL  _SFR_IO8(0x28)
-#define OCR1BH  _SFR_IO8(0x29)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_IO16(0x2A)
-
-#define OCR1AL  _SFR_IO8(0x2A)
-#define OCR1AH  _SFR_IO8(0x2B)
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_IO16(0x2C)
-
-#define TCNT1L  _SFR_IO8(0x2C)
-#define TCNT1H  _SFR_IO8(0x2D)
-
-#define TCCR1B  _SFR_IO8(0x2E)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1A  _SFR_IO8(0x2F)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR0A  _SFR_IO8(0x30)
-#define WGM00   0
-#define WGM01   1
-#define COM0B0  4
-#define COM0B1  5
-#define COM0A0  6
-#define COM0A1  7
-
-/* Reserved [0x31] */
-
-#define TCNT0   _SFR_IO8(0x32)
-
-#define TCCR0B  _SFR_IO8(0x33)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM02   3
-#define FOC0B   6
-#define FOC0A   7
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define ISC00   0
-#define ISC01   1
-#define SM0     3
-#define SM1     4
-#define SE      5
-
-#define OCR0A   _SFR_IO8(0x36)
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define RFLB    3
-#define CTPB    4
-#define RSIG    5
-
-#define TIFR0   _SFR_IO8(0x38)
-#define TOV0    0
-#define OCF0A   1
-#define OCF0B   2
-
-#define TIMSK0  _SFR_IO8(0x39)
-#define TOIE0   0
-#define OCIE0A  1
-#define OCIE0B  2
-
-#define GIFR    _SFR_IO8(0x3A)
-#define PCIF0   4
-#define PCIF1   5
-#define INTF0   6
-
-#define GIMSK   _SFR_IO8(0x3B)
-#define PCIE0   4
-#define PCIE1   5
-#define INT0    6
-
-#define OCR0B   _SFR_IO8(0x3C)
-
-/* SP [0x3D..0x3E] */
-
-/* SREG [0x3F] */
-
-#define DIDR0   _SFR_MEM8(0x60)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x61)
-#define ADC11D  0
-#define ADC10D  1
-#define ADC8D   2
-#define ADC9D   3
-
-#define PUEB    _SFR_MEM8(0x62)
-
-#define PUEA    _SFR_MEM8(0x63)
-
-#define PORTCR  _SFR_MEM8(0x64)
-#define BBMB    1
-#define BBMA    0
-
-#define REMAP   _SFR_MEM8(0x65)
-#define U0MAP   0
-#define SPIMAP  1
-
-#define TOCPMCOE _SFR_MEM8(0x66)
-#define TOCC0OE 0
-#define TOCC1OE 1
-#define TOCC2OE 2
-#define TOCC3OE 3
-#define TOCC4OE 4
-#define TOCC5OE 5
-#define TOCC6OE 6
-#define TOCC7OE 7
-
-#define TOCPMSA0 _SFR_MEM8(0x67)
-#define TOCC0S0 0
-#define TOCC0S1 1
-#define TOCC1S0 2
-#define TOCC1S1 3
-#define TOCC2S0 4
-#define TOCC2S1 5
-#define TOCC3S0 6
-#define TOCC3S1 7
-
-#define TOCPMSA1 _SFR_MEM8(0x68)
-#define TOCC4S0 0
-#define TOCC4S1 1
-#define TOCC5S0 2
-#define TOCC5S1 3
-#define TOCC6S0 4
-#define TOCC6S1 5
-#define TOCC7S0 6
-#define TOCC7S1 7
-
-/* Reserved [0x69] */
-
-#define PHDE    _SFR_MEM8(0x6A)
-#define PHDEA0  0
-#define PHDEA1  1
-
-/* Reserved [0x6B..0x6F] */
-
-#define PRR     _SFR_MEM8(0x70)
-#define PRADC   0
-#define PRTIM0  1
-#define PRTIM1  2
-#define PRTIM2  3
-#define PRSPI   4
-#define PRUSART0 5
-#define PRUSART1 6
-#define PRTWI   7
-
-#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTWI))
-#define __AVR_HAVE_PRR_PRADC
-#define __AVR_HAVE_PRR_PRTIM0
-#define __AVR_HAVE_PRR_PRTIM1
-#define __AVR_HAVE_PRR_PRTIM2
-#define __AVR_HAVE_PRR_PRSPI
-#define __AVR_HAVE_PRR_PRUSART0
-#define __AVR_HAVE_PRR_PRUSART1
-#define __AVR_HAVE_PRR_PRTWI
-
-#define CCP     _SFR_MEM8(0x71)
-
-#define CLKCR   _SFR_MEM8(0x72)
-#define CKSEL0  0
-#define CKSEL1  1
-#define CKSEL2  2
-#define CKSEL3  3
-#define SUT     4
-#define CKOUTC  5
-#define CSTR    6
-#define OSCRDY  7
-
-#define CLKPR   _SFR_MEM8(0x73)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-
-#define OSCCAL0 _SFR_MEM8(0x74)
-
-#define OSCTCAL0A _SFR_MEM8(0x75)
-
-#define OSCTCAL0B _SFR_MEM8(0x76)
-
-#define OSCCAL1 _SFR_MEM8(0x77)
-
-/* Reserved [0x78..0x7F] */
-
-#define UDR0    _SFR_MEM8(0x80)
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0x81)
-
-#define UBRR0L  _SFR_MEM8(0x81)
-#define UBRR0H  _SFR_MEM8(0x82)
-
-#define UCSR0D  _SFR_MEM8(0x83)
-#define SFDE0   5
-#define RXS0    6
-#define RXSIE0  7
-
-#define UCSR0C  _SFR_MEM8(0x84)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UCSR0B  _SFR_MEM8(0x85)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0A  _SFR_MEM8(0x86)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-/* Reserved [0x87..0x8F] */
-
-#define UDR1    _SFR_MEM8(0x90)
-
-/* Combine UBRR1L and UBRR1H */
-#define UBRR1   _SFR_MEM16(0x91)
-
-#define UBRR1L  _SFR_MEM8(0x91)
-#define UBRR1H  _SFR_MEM8(0x92)
-
-#define UCSR1D  _SFR_MEM8(0x93)
-#define SFDE1   5
-#define RXS1    6
-#define RXSIE1  7
-
-#define UCSR1C  _SFR_MEM8(0x94)
-#define UCPOL1  0
-#define UCSZ10  1
-#define UCSZ11  2
-#define USBS1   3
-#define UPM10   4
-#define UPM11   5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UCSR1B  _SFR_MEM8(0x95)
-#define TXB81   0
-#define RXB81   1
-#define UCSZ12  2
-#define TXEN1   3
-#define RXEN1   4
-#define UDRIE1  5
-#define TXCIE1  6
-#define RXCIE1  7
-
-#define UCSR1A  _SFR_MEM8(0x96)
-#define MPCM1   0
-#define U2X1    1
-#define UPE1    2
-#define DOR1    3
-#define FE1     4
-#define UDRE1   5
-#define TXC1    6
-#define RXC1    7
-
-/* Reserved [0x97..0x9F] */
-
-#define TWSD    _SFR_MEM8(0xA0)
-#define TWSD0   0
-#define TWSD1   1
-#define TWSD2   2
-#define TWSD3   3
-#define TWSD4   4
-#define TWSD5   5
-#define TWSD6   6
-#define TWSD7   7
-
-#define TWSAM   _SFR_MEM8(0xA1)
-#define TWAE    0
-#define TWSAM1  1
-#define TWSAM2  2
-#define TWSAM3  3
-#define TWSAM4  4
-#define TWSAM5  5
-#define TWSAM6  6
-#define TWSAM7  7
-
-#define TWSA    _SFR_MEM8(0xA2)
-
-#define TWSSRA  _SFR_MEM8(0xA3)
-#define TWAS    0
-#define TWDIR   1
-#define TWBE    2
-#define TWC     3
-#define TWRA    4
-#define TWCH    5
-#define TWASIF  6
-#define TWDIF   7
-
-#define TWSCRB  _SFR_MEM8(0xA4)
-#define TWCMD0  0
-#define TWCMD1  1
-#define TWAA    2
-#define TWHNM   3
-
-#define TWSCRA  _SFR_MEM8(0xA5)
-#define TWSME   0
-#define TWPME   1
-#define TWSIE   2
-#define TWEN    3
-#define TWASIE  4
-#define TWDIE   5
-#define TWSHE   7
-
-/* Reserved [0xA6..0xAF] */
-
-#define SPDR    _SFR_MEM8(0xB0)
-
-#define SPSR    _SFR_MEM8(0xB1)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPCR    _SFR_MEM8(0xB2)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-/* Reserved [0xB3..0xBF] */
-
-/* Combine ICR2L and ICR2H */
-#define ICR2    _SFR_MEM16(0xC0)
-
-#define ICR2L   _SFR_MEM8(0xC0)
-#define ICR2H   _SFR_MEM8(0xC1)
-
-/* Combine OCR2BL and OCR2BH */
-#define OCR2B   _SFR_MEM16(0xC2)
-
-#define OCR2BL  _SFR_MEM8(0xC2)
-#define OCR2BH  _SFR_MEM8(0xC3)
-
-/* Combine OCR2AL and OCR2AH */
-#define OCR2A   _SFR_MEM16(0xC4)
-
-#define OCR2AL  _SFR_MEM8(0xC4)
-#define OCR2AH  _SFR_MEM8(0xC5)
-
-/* Combine TCNT2L and TCNT2H */
-#define TCNT2   _SFR_MEM16(0xC6)
-
-#define TCNT2L  _SFR_MEM8(0xC6)
-#define TCNT2H  _SFR_MEM8(0xC7)
-
-#define TCCR2C  _SFR_MEM8(0xC8)
-#define FOC2B   6
-#define FOC2A   7
-
-#define TCCR2B  _SFR_MEM8(0xC9)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM22   3
-#define WGM23   4
-#define ICES2   6
-#define ICNC2   7
-
-#define TCCR2A  _SFR_MEM8(0xCA)
-#define WGM20   0
-#define WGM21   1
-#define COM2B0  4
-#define COM2B1  5
-#define COM2A0  6
-#define COM2A1  7
-
-
-
-/* Values and associated defines */
-
-
-#define SLEEP_MODE_IDLE (0x00<<3)
-#define SLEEP_MODE_ADC (0x01<<3)
-#define SLEEP_MODE_PWR_DOWN (0x02<<3)
-#define SLEEP_MODE_STANDBY (0x03<<3)
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect            _VECTOR(1)
-#define INT0_vect_num        1
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect            _VECTOR(2)
-#define PCINT0_vect_num        2
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect            _VECTOR(3)
-#define PCINT1_vect_num        3
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect            _VECTOR(4)
-#define WDT_vect_num        4
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect            _VECTOR(5)
-#define TIMER1_CAPT_vect_num        5
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect            _VECTOR(6)
-#define TIMER1_COMPA_vect_num        6
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect            _VECTOR(7)
-#define TIMER1_COMPB_vect_num        7
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect            _VECTOR(8)
-#define TIMER1_OVF_vect_num        8
-
-/* TimerCounter0 Compare Match A */
-#define TIMER0_COMPA_vect            _VECTOR(9)
-#define TIMER0_COMPA_vect_num        9
-
-/* TimerCounter0 Compare Match B */
-#define TIMER0_COMPB_vect            _VECTOR(10)
-#define TIMER0_COMPB_vect_num        10
-
-/* Timer/Couner0 Overflow */
-#define TIMER0_OVF_vect            _VECTOR(11)
-#define TIMER0_OVF_vect_num        11
-
-/* Analog Comparator 0 */
-#define ANA_COMP0_vect            _VECTOR(12)
-#define ANA_COMP0_vect_num        12
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(13)
-#define ADC_vect_num        13
-
-/* EEPROM Ready */
-#define EE_RDY_vect            _VECTOR(14)
-#define EE_RDY_vect_num        14
-
-/* Analog Comparator 1 */
-#define ANA_COMP1_vect            _VECTOR(15)
-#define ANA_COMP1_vect_num        15
-
-/* Timer/Counter2 Capture Event */
-#define TIMER2_CAPT_vect            _VECTOR(16)
-#define TIMER2_CAPT_vect_num        16
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect            _VECTOR(17)
-#define TIMER2_COMPA_vect_num        17
-
-/* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect            _VECTOR(18)
-#define TIMER2_COMPB_vect_num        18
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect            _VECTOR(19)
-#define TIMER2_OVF_vect_num        19
-
-/* Serial Peripheral Interface */
-#define SPI_vect            _VECTOR(20)
-#define SPI_vect_num        20
-
-/* USART0, Start */
-#define USART0_START_vect            _VECTOR(21)
-#define USART0_START_vect_num        21
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect            _VECTOR(22)
-#define USART0_RX_vect_num        22
-
-/* USART0 Data Register Empty */
-#define USART0_UDRE_vect            _VECTOR(23)
-#define USART0_UDRE_vect_num        23
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect            _VECTOR(24)
-#define USART0_TX_vect_num        24
-
-/* USART1, Start */
-#define USART1_START_vect            _VECTOR(25)
-#define USART1_START_vect_num        25
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect            _VECTOR(26)
-#define USART1_RX_vect_num        26
-
-/* USART1 Data Register Empty */
-#define USART1_UDRE_vect            _VECTOR(27)
-#define USART1_UDRE_vect_num        27
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect            _VECTOR(28)
-#define USART1_TX_vect_num        28
-
-/* Two-wire Serial Interface */
-#define TWI_SLAVE_vect            _VECTOR(29)
-#define TWI_SLAVE_vect_num        29
-
-#define _VECTORS_SIZE 60
-
-
-/* Constants */
-
-#define SPM_PAGESIZE 16
-#define FLASHSTART   0x0000
-#define FLASHEND     0x1FFF
-#define RAMSTART     0x0100
-#define RAMSIZE      512
-#define RAMEND       0x02FF
-#define E2START     0
-#define E2SIZE      512
-#define E2PAGESIZE  4
-#define E2END       0x01FF
-#define XRAMEND      RAMEND
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT    (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define FUSE_BODACT0     (unsigned char)~_BV(1)
-#define FUSE_BODACT1     (unsigned char)~_BV(2)
-#define FUSE_BODPD0      (unsigned char)~_BV(3)
-#define FUSE_BODPD1      (unsigned char)~_BV(4)
-#define FUSE_ULPOSCSEL0  (unsigned char)~_BV(5)
-#define FUSE_ULPOSCSEL1  (unsigned char)~_BV(6)
-#define FUSE_ULPOSCSEL2  (unsigned char)~_BV(7)
-#define EFUSE_DEFAULT    (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x15
-
-
-#endif /* #ifdef _AVR_ATTINY841_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATTINY841_H_INCLUDED
+#define _AVR_ATTINY841_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotn841.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define ADCSRB  _SFR_IO8(0x04)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ADLAR   3
+
+#define ADCSRA  _SFR_IO8(0x05)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x06)
+#endif
+#define ADCW    _SFR_IO16(0x06)
+
+#define ADCL    _SFR_IO8(0x06)
+#define ADCH    _SFR_IO8(0x07)
+
+#define ADMUXB  _SFR_IO8(0x08)
+#define GSEL0   0
+#define GSEL1   1
+#define REFS0   5
+#define REFS1   6
+#define REFS2   7
+
+#define ADMUXA  _SFR_IO8(0x09)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define MUX5    5
+
+#define ACSR0A  _SFR_IO8(0x0A)
+#define ACIS00  0
+#define ACIS01  1
+#define ACIC0   2
+#define ACIE0   3
+#define ACI0    4
+#define ACO0    5
+#define ACPMUX2 6
+#define ACD0    7
+
+#define ACSR0B  _SFR_IO8(0x0B)
+#define ACPMUX0 0
+#define ACPMUX1 1
+#define ACNMUX0 2
+#define ACNMUX1 3
+#define ACOE0   4
+#define HLEV0   6
+#define HSEL0   7
+
+#define ACSR1A  _SFR_IO8(0x0C)
+#define ACIS10  0
+#define ACIS11  1
+#define ACIC1   2
+#define ACIE1   3
+#define ACI1    4
+#define ACO1    5
+#define ACBG1   6
+#define ACD1    7
+
+#define ACSR1B  _SFR_IO8(0x0D)
+#define ACME1   2
+#define ACOE1   4
+#define HLEV1   6
+#define HSEL1   7
+
+#define TIFR1   _SFR_IO8(0x0E)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIMSK1  _SFR_IO8(0x0F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIFR2   _SFR_IO8(0x10)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+#define ICF2    5
+
+#define TIMSK2  _SFR_IO8(0x11)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+#define ICIE2   5
+
+#define PCMSK0  _SFR_IO8(0x12)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define GPIOR0  _SFR_IO8(0x13)
+
+#define GPIOR1  _SFR_IO8(0x14)
+
+#define GPIOR2  _SFR_IO8(0x15)
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define EECR    _SFR_IO8(0x1C)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x1D)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x1E)
+
+#define EEARL   _SFR_IO8(0x1E)
+#define EEARH   _SFR_IO8(0x1F)
+
+#define PCMSK1  _SFR_IO8(0x20)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+
+#define WDTCSR  _SFR_IO8(0x21)
+#define WDE     3
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define TCCR1C  _SFR_IO8(0x22)
+#define FOC1B   6
+#define FOC1A   7
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSR     0
+#define TSM     7
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_IO16(0x24)
+
+#define ICR1L   _SFR_IO8(0x24)
+#define ICR1H   _SFR_IO8(0x25)
+
+/* Reserved [0x26..0x27] */
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_IO16(0x28)
+
+#define OCR1BL  _SFR_IO8(0x28)
+#define OCR1BH  _SFR_IO8(0x29)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_IO16(0x2A)
+
+#define OCR1AL  _SFR_IO8(0x2A)
+#define OCR1AH  _SFR_IO8(0x2B)
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_IO16(0x2C)
+
+#define TCNT1L  _SFR_IO8(0x2C)
+#define TCNT1H  _SFR_IO8(0x2D)
+
+#define TCCR1B  _SFR_IO8(0x2E)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1A  _SFR_IO8(0x2F)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR0A  _SFR_IO8(0x30)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+/* Reserved [0x31] */
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define ISC00   0
+#define ISC01   1
+#define SM0     3
+#define SM1     4
+#define SE      5
+
+#define OCR0A   _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define RFLB    3
+#define CTPB    4
+#define RSIG    5
+
+#define TIFR0   _SFR_IO8(0x38)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIMSK0  _SFR_IO8(0x39)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define GIFR    _SFR_IO8(0x3A)
+#define PCIF0   4
+#define PCIF1   5
+#define INTF0   6
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define PCIE0   4
+#define PCIE1   5
+#define INT0    6
+
+#define OCR0B   _SFR_IO8(0x3C)
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define DIDR0   _SFR_MEM8(0x60)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x61)
+#define ADC11D  0
+#define ADC10D  1
+#define ADC8D   2
+#define ADC9D   3
+
+#define PUEB    _SFR_MEM8(0x62)
+#define PUEB3   3
+#define PUEB2   2
+#define PUEB1   1
+#define PUEB0   0
+
+#define PUEA    _SFR_MEM8(0x63)
+#define PUEA7   7
+#define PUEA6   6
+#define PUEA5   5
+#define PUEA4   4
+#define PUEA3   3
+#define PUEA2   2
+#define PUEA1   1
+#define PUEA0   0
+
+#define PORTCR  _SFR_MEM8(0x64)
+#define BBMB    1
+#define BBMA    0
+
+#define REMAP   _SFR_MEM8(0x65)
+#define U0MAP   0
+#define SPIMAP  1
+
+#define TOCPMCOE _SFR_MEM8(0x66)
+#define TOCC0OE 0
+#define TOCC1OE 1
+#define TOCC2OE 2
+#define TOCC3OE 3
+#define TOCC4OE 4
+#define TOCC5OE 5
+#define TOCC6OE 6
+#define TOCC7OE 7
+
+#define TOCPMSA0 _SFR_MEM8(0x67)
+#define TOCC0S0 0
+#define TOCC0S1 1
+#define TOCC1S0 2
+#define TOCC1S1 3
+#define TOCC2S0 4
+#define TOCC2S1 5
+#define TOCC3S0 6
+#define TOCC3S1 7
+
+#define TOCPMSA1 _SFR_MEM8(0x68)
+#define TOCC4S0 0
+#define TOCC4S1 1
+#define TOCC5S0 2
+#define TOCC5S1 3
+#define TOCC6S0 4
+#define TOCC6S1 5
+#define TOCC7S0 6
+#define TOCC7S1 7
+
+/* Reserved [0x69] */
+
+#define PHDE    _SFR_MEM8(0x6A)
+#define PHDEA0  0
+#define PHDEA1  1
+
+/* Reserved [0x6B..0x6F] */
+
+#define PRR     _SFR_MEM8(0x70)
+#define PRADC   0
+#define PRTIM0  1
+#define PRTIM1  2
+#define PRTIM2  3
+#define PRSPI   4
+#define PRUSART0 5
+#define PRUSART1 6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRUSART1
+#define __AVR_HAVE_PRR_PRTWI
+
+#define CCP     _SFR_MEM8(0x71)
+
+#define CLKCR   _SFR_MEM8(0x72)
+#define CKSEL0  0
+#define CKSEL1  1
+#define CKSEL2  2
+#define CKSEL3  3
+#define SUT     4
+#define CKOUTC  5
+#define CSTR    6
+#define OSCRDY  7
+
+#define CLKPR   _SFR_MEM8(0x73)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+
+#define OSCCAL0 _SFR_MEM8(0x74)
+
+#define OSCTCAL0A _SFR_MEM8(0x75)
+
+#define OSCTCAL0B _SFR_MEM8(0x76)
+
+#define OSCCAL1 _SFR_MEM8(0x77)
+
+/* Reserved [0x78..0x7F] */
+
+#define UDR0    _SFR_MEM8(0x80)
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0x81)
+
+#define UBRR0L  _SFR_MEM8(0x81)
+#define UBRR0H  _SFR_MEM8(0x82)
+
+#define UCSR0D  _SFR_MEM8(0x83)
+#define SFDE0   5
+#define RXS0    6
+#define RXSIE0  7
+
+#define UCSR0C  _SFR_MEM8(0x84)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+#define UCSR0B  _SFR_MEM8(0x85)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0A  _SFR_MEM8(0x86)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+/* Reserved [0x87..0x8F] */
+
+#define UDR1    _SFR_MEM8(0x90)
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0x91)
+
+#define UBRR1L  _SFR_MEM8(0x91)
+#define UBRR1H  _SFR_MEM8(0x92)
+
+#define UCSR1D  _SFR_MEM8(0x93)
+#define SFDE1   5
+#define RXS1    6
+#define RXSIE1  7
+
+#define UCSR1C  _SFR_MEM8(0x94)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+
+#define UCSR1B  _SFR_MEM8(0x95)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1A  _SFR_MEM8(0x96)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+/* Reserved [0x97..0x9F] */
+
+#define TWSD    _SFR_MEM8(0xA0)
+#define TWSD0   0
+#define TWSD1   1
+#define TWSD2   2
+#define TWSD3   3
+#define TWSD4   4
+#define TWSD5   5
+#define TWSD6   6
+#define TWSD7   7
+
+#define TWSAM   _SFR_MEM8(0xA1)
+#define TWAE    0
+#define TWSAM1  1
+#define TWSAM2  2
+#define TWSAM3  3
+#define TWSAM4  4
+#define TWSAM5  5
+#define TWSAM6  6
+#define TWSAM7  7
+
+#define TWSA    _SFR_MEM8(0xA2)
+
+#define TWSSRA  _SFR_MEM8(0xA3)
+#define TWAS    0
+#define TWDIR   1
+#define TWBE    2
+#define TWC     3
+#define TWRA    4
+#define TWCH    5
+#define TWASIF  6
+#define TWDIF   7
+
+#define TWSCRB  _SFR_MEM8(0xA4)
+#define TWCMD0  0
+#define TWCMD1  1
+#define TWAA    2
+#define TWHNM   3
+
+#define TWSCRA  _SFR_MEM8(0xA5)
+#define TWSME   0
+#define TWPME   1
+#define TWSIE   2
+#define TWEN    3
+#define TWASIE  4
+#define TWDIE   5
+#define TWSHE   7
+
+/* Reserved [0xA6..0xAF] */
+
+#define SPDR    _SFR_MEM8(0xB0)
+
+#define SPSR    _SFR_MEM8(0xB1)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPCR    _SFR_MEM8(0xB2)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+/* Reserved [0xB3..0xBF] */
+
+/* Combine ICR2L and ICR2H */
+#define ICR2    _SFR_MEM16(0xC0)
+
+#define ICR2L   _SFR_MEM8(0xC0)
+#define ICR2H   _SFR_MEM8(0xC1)
+
+/* Combine OCR2BL and OCR2BH */
+#define OCR2B   _SFR_MEM16(0xC2)
+
+#define OCR2BL  _SFR_MEM8(0xC2)
+#define OCR2BH  _SFR_MEM8(0xC3)
+
+/* Combine OCR2AL and OCR2AH */
+#define OCR2A   _SFR_MEM16(0xC4)
+
+#define OCR2AL  _SFR_MEM8(0xC4)
+#define OCR2AH  _SFR_MEM8(0xC5)
+
+/* Combine TCNT2L and TCNT2H */
+#define TCNT2   _SFR_MEM16(0xC6)
+
+#define TCNT2L  _SFR_MEM8(0xC6)
+#define TCNT2H  _SFR_MEM8(0xC7)
+
+#define TCCR2C  _SFR_MEM8(0xC8)
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCCR2B  _SFR_MEM8(0xC9)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define WGM23   4
+#define ICES2   6
+#define ICNC2   7
+
+#define TCCR2A  _SFR_MEM8(0xCA)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<3)
+#define SLEEP_MODE_ADC (0x01<<3)
+#define SLEEP_MODE_PWR_DOWN (0x02<<3)
+#define SLEEP_MODE_STANDBY (0x03<<3)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(2)
+#define PCINT0_vect_num        2
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(3)
+#define PCINT1_vect_num        3
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(4)
+#define WDT_vect_num        4
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(5)
+#define TIMER1_CAPT_vect_num        5
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(6)
+#define TIMER1_COMPA_vect_num        6
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(7)
+#define TIMER1_COMPB_vect_num        7
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(8)
+#define TIMER1_OVF_vect_num        8
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(9)
+#define TIMER0_COMPA_vect_num        9
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(10)
+#define TIMER0_COMPB_vect_num        10
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(11)
+#define TIMER0_OVF_vect_num        11
+
+/* Analog Comparator 0 */
+#define ANA_COMP0_vect            _VECTOR(12)
+#define ANA_COMP0_vect_num        12
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(13)
+#define ADC_vect_num        13
+
+/* EEPROM Ready */
+#define EE_RDY_vect            _VECTOR(14)
+#define EE_RDY_vect_num        14
+
+/* Analog Comparator 1 */
+#define ANA_COMP1_vect            _VECTOR(15)
+#define ANA_COMP1_vect_num        15
+
+/* Timer/Counter2 Capture Event */
+#define TIMER2_CAPT_vect            _VECTOR(16)
+#define TIMER2_CAPT_vect_num        16
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(17)
+#define TIMER2_COMPA_vect_num        17
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect            _VECTOR(18)
+#define TIMER2_COMPB_vect_num        18
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(19)
+#define TIMER2_OVF_vect_num        19
+
+/* Serial Peripheral Interface */
+#define SPI_vect            _VECTOR(20)
+#define SPI_vect_num        20
+
+/* USART0, Start */
+#define USART0_START_vect            _VECTOR(21)
+#define USART0_START_vect_num        21
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect            _VECTOR(22)
+#define USART0_RX_vect_num        22
+
+/* USART0 Data Register Empty */
+#define USART0_UDRE_vect            _VECTOR(23)
+#define USART0_UDRE_vect_num        23
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect            _VECTOR(24)
+#define USART0_TX_vect_num        24
+
+/* USART1, Start */
+#define USART1_START_vect            _VECTOR(25)
+#define USART1_START_vect_num        25
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect            _VECTOR(26)
+#define USART1_RX_vect_num        26
+
+/* USART1 Data Register Empty */
+#define USART1_UDRE_vect            _VECTOR(27)
+#define USART1_UDRE_vect_num        27
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect            _VECTOR(28)
+#define USART1_TX_vect_num        28
+
+/* Two-wire Serial Interface */
+#define TWI_SLAVE_vect            _VECTOR(29)
+#define TWI_SLAVE_vect_num        29
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define _VECTORS_SIZE 60
+#else
+#  define _VECTORS_SIZE 60U
+#endif
+
+
+/* Constants */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 16
+#  define FLASHSTART   0x0000
+#  define FLASHEND     0x1FFF
+#else
+#  define SPM_PAGESIZE 16U
+#  define FLASHSTART   0x0000U
+#  define FLASHEND     0x1FFFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define RAMSTART     0x0100
+#  define RAMSIZE      512
+#  define RAMEND       0x02FF
+#else
+#  define RAMSTART     0x0100U
+#  define RAMSIZE      512U
+#  define RAMEND       0x02FFU
+#endif
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define E2START     0
+#  define E2SIZE      512
+#  define E2PAGESIZE  4
+#  define E2END       0x01FF
+#else
+#  define E2START     0U
+#  define E2SIZE      512U
+#  define E2PAGESIZE  4U
+#  define E2END       0x01FFU
+#endif
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define FUSE_BODACT0     (unsigned char)~_BV(1)
+#define FUSE_BODACT1     (unsigned char)~_BV(2)
+#define FUSE_BODPD0      (unsigned char)~_BV(3)
+#define FUSE_BODPD1      (unsigned char)~_BV(4)
+#define FUSE_ULPOSCSEL0  (unsigned char)~_BV(5)
+#define FUSE_ULPOSCSEL1  (unsigned char)~_BV(6)
+#define FUSE_ULPOSCSEL2  (unsigned char)~_BV(7)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x15
+
+
+
+
+#endif /* #ifdef _AVR_ATTINY841_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn84a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn84a.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn84a.h 2435 2014-08-11 10:31:52Z joerg_wunsch $ */
 
 /* avr/iotn84a.h - definitions for ATtiny84A */
 
@@ -835,7 +835,6 @@
 #define PCINT5_PIN   PINA
 #define PCINT5_BIT   5
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn85.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn85.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005, Joerg Wunsch
+/* Copyright (c) 2005, Joerg Wunsch, 2005,2007 Anatoly Sokolov
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,14 +28,417 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn85.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 /* avr/iotn85.h - definitions for ATtiny85 */
 
 #ifndef _AVR_IOTN85_H_
 #define _AVR_IOTN85_H_ 1
 
-#include <avr/iotnx5.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx5.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* I/O registers */
+
+/* Reserved [0x00..0x02] */
+
+#define ADCSRB  _SFR_IO8 (0x03)
+#define BIN     7
+#define ACME    6
+#define IPR     5
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+#define ADCW    _SFR_IO16(0x04)
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8 (0x06)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADMUX   _SFR_IO8(0x07)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define REFS2   4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define ACSR    _SFR_IO8(0x08)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIS1   1
+#define ACIS0   0
+
+/* Reserved [0x09..0x0C] */
+
+#define USICR   _SFR_IO8(0x0D)
+#define USISIE  7
+#define USIOIE  6
+#define USIWM1  5
+#define USIWM0  4
+#define USICS1  3
+#define USICS0  2
+#define USICLK  1
+#define USITC   0
+
+#define USISR   _SFR_IO8(0x0E)
+#define USISIF  7 
+#define USIOIF  6
+#define USIPF   5
+#define USIDC   4
+#define USICNT3 3
+#define USICNT2 2
+#define USICNT1 1
+#define USICNT0 0
+
+#define USIDR   _SFR_IO8(0x0F)
+#define USIBR   _SFR_IO8(0x10)
+
+#define GPIOR0  _SFR_IO8(0x11)
+#define GPIOR1  _SFR_IO8(0x12)
+#define GPIOR2  _SFR_IO8(0x13)
+
+#define DIDR0    _SFR_IO8(0x14)
+#define ADC0D   5
+#define ADC2D   4
+#define ADC3D   3
+#define ADC1D   2
+#define AIN1D   1 
+#define AIN0D   0
+
+#define PCMSK   _SFR_IO8(0x15)
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+/* Reserved [0x19..0x1B] */
+
+/* EEPROM Control Register EECR */
+#define EECR	_SFR_IO8(0x1C)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define PRR     _SFR_IO8(0x20)
+#define PRTIM1  3
+#define PRTIM0  2
+#define PRUSI   1
+#define PRADC   0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define WDTCR   _SFR_IO8(0x21)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define DWDR    _SFR_IO8(0x22)
+
+#define DTPS1   _SFR_IO8(0x23)
+#define DTPS11   1
+#define DTPS10   0
+
+#define DT1B    _SFR_IO8(0x24)
+#define DT1BH3  7
+#define DT1BH2  6
+#define DT1BH1  5
+#define DT1BH0  4
+#define DT1BL3  3
+#define DT1BL2  2
+#define DT1BL1  1
+#define DT1BL0  0
+
+#define DT1A    _SFR_IO8(0x25)
+#define DT1AH3  7
+#define DT1AH2  6
+#define DT1AH1  5
+#define DT1AH0  4
+#define DT1AL3  3
+#define DT1AL2  2
+#define DT1AL1  1
+#define DT1AL0  0
+
+#define CLKPR   _SFR_IO8(0x26)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define PLLCSR  _SFR_IO8(0x27)
+#define LSM     7
+#define PCKE    2
+#define PLLE    1
+#define PLOCK   0
+
+#define OCR0B   _SFR_IO8(0x28)
+
+#define OCR0A   _SFR_IO8(0x29)
+
+#define TCCR0A  _SFR_IO8(0x2A)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define OCR1B   _SFR_IO8(0x2B)
+
+#define GTCCR   _SFR_IO8(0x2C)
+#define TSM     7
+#define PWM1B   6
+#define COM1B1  5
+#define COM1B0  4
+#define FOC1B   3
+#define FOC1A   2
+#define PSR1    1
+#define PSR0    0
+
+#define OCR1C   _SFR_IO8(0x2D)
+
+#define OCR1A   _SFR_IO8(0x2E)
+
+#define TCNT1   _SFR_IO8(0x2F)
+
+#define TCCR1   _SFR_IO8(0x30)
+#define CTC1    7
+#define PWM1A   6
+#define COM1A1  5
+#define COM1A0  4
+#define CS13    3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define BODS    7
+#define PUD     6
+#define SE      5
+#define SM1     4
+#define SM0     3
+#define BODSE   2
+#define ISC01   1
+#define ISC00   0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define RSIG    5
+#define CTPB    4
+#define RFLB    3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+#define TIFR    _SFR_IO8(0x38)
+#define OCF1A   6
+#define OCF1B   5
+#define OCF0A   4
+#define OCF0B   3
+#define TOV1    2
+#define TOV0    1
+
+#define TIMSK   _SFR_IO8(0x39)
+#define OCIE1A  6
+#define OCIE1B  5
+#define OCIE0A  4
+#define OCIE0B  3
+#define TOIE1   2
+#define TOIE0   1
+
+#define GIFR    _SFR_IO8(0x3A)
+#define INTF0   6
+#define PCIF    5
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define INT0    6
+#define PCIE    5
+
+/* Reserved [0x3C] */
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+///---
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt 0 */
+#define INT0_vect_num	        1
+#define INT0_vect			    _VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin change Interrupt Request 0 */
+#define PCINT0_vect_num			2
+#define PCINT0_vect			    _VECTOR(2)
+#define SIG_PIN_CHANGE			_VECTOR(2)
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIM1_COMPA_vect_num		3
+#define TIM1_COMPA_vect			_VECTOR(3)
+#define TIMER1_COMPA_vect_num	3
+#define TIMER1_COMPA_vect		_VECTOR(3)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(3)
+
+/* Timer/Counter1 Overflow */
+#define TIM1_OVF_vect_num		4
+#define TIM1_OVF_vect			_VECTOR(4)
+#define TIMER1_OVF_vect_num		4
+#define TIMER1_OVF_vect			_VECTOR(4)
+#define SIG_OVERFLOW1			_VECTOR(4)
+
+/* Timer/Counter0 Overflow */
+#define TIM0_OVF_vect_num		5
+#define TIM0_OVF_vect			_VECTOR(5)
+#define TIMER0_OVF_vect_num		5
+#define TIMER0_OVF_vect			_VECTOR(5)
+#define SIG_OVERFLOW0			_VECTOR(5)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num			6
+#define EE_RDY_vect		    	_VECTOR(6)
+#define SIG_EEPROM_READY		_VECTOR(6)
+
+/* Analog comparator */
+#define ANA_COMP_vect_num		7
+#define ANA_COMP_vect			_VECTOR(7)
+#define SIG_COMPARATOR			_VECTOR(7)
+
+/* ADC Conversion ready */
+#define ADC_vect_num    		8
+#define ADC_vect		    	_VECTOR(8)
+#define SIG_ADC				    _VECTOR(8)
+
+/* Timer/Counter1 Compare Match B */
+#define TIM1_COMPB_vect_num  	9
+#define TIM1_COMPB_vect			_VECTOR(9)
+#define TIMER1_COMPB_vect_num	9
+#define TIMER1_COMPB_vect   	_VECTOR(9)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(9)
+
+/* Timer/Counter0 Compare Match A */
+#define TIM0_COMPA_vect_num		10
+#define TIM0_COMPA_vect			_VECTOR(10)
+#define TIMER0_COMPA_vect_num	10
+#define TIMER0_COMPA_vect		_VECTOR(10)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(10)
+
+/* Timer/Counter0 Compare Match B */
+#define TIM0_COMPB_vect_num		11
+#define TIM0_COMPB_vect			_VECTOR(11)
+#define TIMER0_COMPB_vect_num	11
+#define TIMER0_COMPB_vect		_VECTOR(11)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(11)
+
+/* Watchdog Time-out */
+#define WDT_vect_num			12
+#define WDT_vect				_VECTOR(12)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(12)
+
+/* USI START */
+#define USI_START_vect_num		13
+#define USI_START_vect			_VECTOR(13)
+#define SIG_USI_START			_VECTOR(13)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		14
+#define USI_OVF_vect			_VECTOR(14)
+#define SIG_USI_OVERFLOW		_VECTOR(14)
+
+#define _VECTORS_SIZE 30
+
 
 /* Constants */
 #define SPM_PAGESIZE 64
@@ -86,10 +489,8 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x0B
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 
-
 #endif /* _AVR_IOTN85_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn861.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn861.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2006, Anatoly Sokolov
+/* Copyright (c) 2006, 2007 Anatoly Sokolov
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -28,14 +28,516 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn861.h 2115 2010-04-05 23:19:53Z arcanum $ */
 
 /* avr/iotn861.h - definitions for ATtiny861 */
 
 #ifndef _AVR_IOTN861_H_
 #define _AVR_IOTN861_H_ 1
 
-#include <avr/iotnx61.h>
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx61.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define TCCR1E  _SFR_IO8(0x00)
+#define OC1OE0  0
+#define OC1OE1  1
+#define OC1OE2  2
+#define OC1OE3  3
+#define OC1OE4  4
+#define OC1OE5  5
+
+#define DIDR0   _SFR_IO8(0x01)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define AREFD   3
+#define ADC3D   4
+#define ADC4D   5
+#define ADC5D   6
+#define ADC6D   7
+
+#define DIDR1   _SFR_IO8(0x02)
+#define ADC7D   4
+#define ADC8D   5
+#define ADC9D   6
+#define ADC10D  7
+
+#define ADCSRB  _SFR_IO8(0x03)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define MUX5    3
+#define REFS2   4
+#define IRP     5
+#define GSEL    6
+#define BIN     7
+
+#define ADCW    _SFR_IO16(0x04)
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8(0x06)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADMUX   _SFR_IO8(0x07)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define ACSRA   _SFR_IO8(0x08)
+#define ACIS0   0
+#define ACIS1   1
+#define ACME    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define ACSRB   _SFR_IO8(0x09)
+#define ACM0    0
+#define ACM1    1
+#define ACM2    2
+#define HLEV    6
+#define HSEL    7
+
+#define GPIOR0  _SFR_IO8(0x0A)
+
+#define GPIOR1  _SFR_IO8(0x0B)
+
+#define GPIOR2  _SFR_IO8(0x0C)
+
+#define USICR   _SFR_IO8(0x0D)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_IO8(0x0F)
+
+#define USIBR   _SFR_IO8(0x10)
+
+#define USIPP   _SFR_IO8(0x11)
+#define USIPOS  0
+
+#define OCR0B   _SFR_IO8(0x12)
+
+#define OCR0A   _SFR_IO8(0x13)
+
+#define TCNT0H  _SFR_IO8(0x14)
+
+#define TCCR0A  _SFR_IO8(0x15)
+#define WGM00   0		/* up to at least datasheet rev. B */
+#define CTC0    0		/* newer revisions; change not mentioned
+				 * in revision history */
+#define ACIC0   3
+#define ICES0   4
+#define ICNC0   5
+#define ICEN0   6
+#define TCW0    7
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB0   0
+#define PINB1   1
+#define PINB2   2
+#define PINB3   3
+#define PINB4   4
+#define PINB5   5
+#define PINB6   6
+#define PINB7   7
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB0    0
+#define DDB1    1
+#define DDB2    2
+#define DDB3    3
+#define DDB4    4
+#define DDB5    5
+#define DDB6    6
+#define DDB7    7
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB0     0
+#define PB1     1
+#define PB2     2
+#define PB3     3
+#define PB4     4
+#define PB5     5
+#define PB6     6
+#define PB7     7
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA0   0
+#define PINA1   1
+#define PINA2   2
+#define PINA3   3
+#define PINA4   4
+#define PINA5   5
+#define PINA6   6
+#define PINA7   7
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDA0    0
+#define DDA1    1
+#define DDA2    2
+#define DDA3    3
+#define DDA4    4
+#define DDA5    5
+#define DDA6    6
+#define DDA7    7
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PA0     0
+#define PA1     1
+#define PA2     2
+#define PA3     3
+#define PA4     4
+#define PA5     5
+#define PA6     6
+#define PA7     7
+
+/* EEPROM Control Register */
+#define EECR	_SFR_IO8(0x1C)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define DWDR    _SFR_IO8(0x20)
+
+#define WDTCR   _SFR_IO8(0x21)
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDE     3
+#define WDCE    4
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define PCMSK1  _SFR_IO8(0x22)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK0  _SFR_IO8(0x23)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define DT1     _SFR_IO8(0x24)
+#define DT1L0   0
+#define DT1L1   1
+#define DT1L2   2
+#define DT1L3   3
+#define DT1H0   4
+#define DT1H1   5
+#define DT1H2   6
+#define DT1H3   7
+
+#define TC1H    _SFR_IO8(0x25)
+#define TC18    0
+#define TC19    1
+
+#define TCCR1D  _SFR_IO8(0x26)
+#define WGM10   0
+#define WGM11   1
+#define FPF1    2
+#define FPAC1   3
+#define FPES1   4
+#define FPNC1   5
+#define FPEN1   6
+#define FPIE1   7
+
+#define TCCR1C  _SFR_IO8(0x27)
+#define PWM1D   0
+#define FOC1D   1
+#define COM1D0  2
+#define COM1D1  3
+#define COM1B0S 4
+#define COM1B1S 5
+#define COM1A0S 6
+#define COM1A1S 7
+
+#define CLKPR   _SFR_IO8(0x28)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLOCK   0
+#define PLLE    1
+#define PCKE    2
+#define LSM     7
+
+#define OCR1D   _SFR_IO8(0x2A)
+
+#define OCR1C   _SFR_IO8(0x2B)
+
+#define OCR1B   _SFR_IO8(0x2C)
+
+#define OCR1A   _SFR_IO8(0x2D)
+
+#define TCNT1   _SFR_IO8(0x2E)
+
+#define TCCR1B  _SFR_IO8(0x2F)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define CS13    3
+#define DTPS10  4
+#define DTPS11  5
+#define PSR1    6
+#define PWM1X   7
+
+#define TCCR1A  _SFR_IO8(0x30)
+#define PWM1B   0
+#define PWM1A   1
+#define FOC1B   2
+#define FOC1A   3
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0L  _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define PSR0    3
+#define TSM     4
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define ISC00   0
+#define ISC01   1
+#define SM0     3
+#define SM1     4
+#define SE      5
+#define PUD     6
+
+#define PRR     _SFR_IO8(0x36)
+#define PRADC   0
+#define PRUSI   1
+#define PRTIM0  2
+#define PRTIM1  3
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR    _SFR_IO8(0x38)
+#define ICF0    0
+#define TOV0    1
+#define TOV1    2
+#define OCF0B   3
+#define OCF0A   4
+#define OCF1B   5
+#define OCF1A   6
+#define OCF1D   7
+
+#define TIMSK   _SFR_IO8(0x39)
+#define TICIE0  0
+#define TOIE0   1
+#define TOIE1   2
+#define OCIE0B  3
+#define OCIE0A  4
+#define OCIE1B  5
+#define OCIE1A  6
+#define OCIE1D  7
+
+#define GIFR    _SFR_IO8(0x3A)
+#define PCIF    5
+#define INTF0   6
+#define INTF1   7
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define PCIE0   4
+#define PCIE1   5
+#define INT0    6
+#define INT1    7
+
+/* Reserved [0x3C] */
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt 0 */
+#define INT0_vect_num			1
+#define INT0_vect	    		_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin Change Interrupt */
+#define PCINT_vect_num			2
+#define PCINT_vect		    	_VECTOR(2)
+#define SIG_PIN_CHANGE			_VECTOR(2)
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPA_vect_num	3
+#define TIMER1_COMPA_vect		_VECTOR(3)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(3)
+
+/* Timer/Counter1 Compare Match 1B */
+#define TIMER1_COMPB_vect_num	4
+#define TIMER1_COMPB_vect	    _VECTOR(4)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(4)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		5
+#define TIMER1_OVF_vect			_VECTOR(5)
+#define SIG_OVERFLOW1			_VECTOR(5)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num 	6
+#define TIMER0_OVF_vect			_VECTOR(6)
+#define SIG_OVERFLOW0			_VECTOR(6)
+
+/* USI Start */
+#define USI_START_vect_num		7
+#define USI_START_vect			_VECTOR(7)
+#define SIG_USI_START			_VECTOR(7)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		8
+#define USI_OVF_vect			_VECTOR(8)
+#define SIG_USI_OVERFLOW		_VECTOR(8)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num			9
+#define EE_RDY_vect		    	_VECTOR(9)
+#define SIG_EEPROM_READY		_VECTOR(9)
+
+/* Analog Comparator */
+#define ANA_COMP_vect_num   	10
+#define ANA_COMP_vect			_VECTOR(10)
+#define SIG_ANA_COMP			_VECTOR(10)
+#define SIG_COMPARATOR			_VECTOR(10)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			11
+#define ADC_vect	    		_VECTOR(11)
+#define SIG_ADC			    	_VECTOR(11)
+
+/* Watchdog Time-Out */
+#define WDT_vect_num			12
+#define WDT_vect	    		_VECTOR(12)
+#define SIG_WDT			    	_VECTOR(12)
+
+/* External Interrupt 1 */
+#define INT1_vect_num			13
+#define INT1_vect	    		_VECTOR(13)
+#define SIG_INTERRUPT1			_VECTOR(13)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num		14
+#define TIMER0_COMPA_vect	    	_VECTOR(14)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(14)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num		15
+#define TIMER0_COMPB_vect	    	_VECTOR(15)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(15)
+
+/* ADC Conversion Complete */
+#define TIMER0_CAPT_vect_num		16
+#define TIMER0_CAPT_vect	    	_VECTOR(16)
+#define SIG_INPUT_CAPTURE0		    _VECTOR(16)
+
+/* Timer/Counter1 Compare Match D */
+#define TIMER1_COMPD_vect_num       17
+#define TIMER1_COMPD_vect		    _VECTOR(17)
+#define SIG_OUTPUT_COMPARE0D		_VECTOR(17)
+
+/* Timer/Counter1 Fault Protection */
+#define FAULT_PROTECTION_vect_num	18
+#define FAULT_PROTECTION_vect		_VECTOR(18)
+
+#define _VECTORS_SIZE 38
+
 
 /* Constants */
 #define SPM_PAGESIZE 64
@@ -86,11 +588,9 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x0D
 
-
 #define SLEEP_MODE_IDLE (0x00<<3)
 #define SLEEP_MODE_ADC (0x01<<3)
 #define SLEEP_MODE_PWR_DOWN (0x02<<3)
 #define SLEEP_MODE_STANDBY (0x03<<3)
 
-
 #endif /* _AVR_IOTN861_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn861a.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn861a.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn861a.h 2063 2009-11-18 22:06:28Z arcanum $ */
 
 /* avr/iotn861a.h - definitions for ATtiny861A */
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn87.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn87.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iotn87.h 2181 2010-08-23 03:46:23Z arcanum $ */
 
 /* avr/iotn87.h - definitions for ATtiny87 */
 
@@ -851,7 +851,6 @@
 #define SIGNATURE_2 0x87
 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn88.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn88.h
@@ -29,7 +29,7 @@
   POSSIBILITY OF SUCH DAMAGE. 
 */
 
-/* $Id$ */
+/* $Id: iotn88.h 2225 2011-03-02 16:27:26Z arcanum $ */
 
 /* avr/iotn88.h - definitions for ATtiny88 */
 
@@ -798,11 +798,9 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x11
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 
-
 #endif /* _AVR_IOTN88_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iotn9.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iotn9.h
@@ -468,7 +468,6 @@
 #define PB3_PIN   PINRESET
 #define PB3_BIT   RESET
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iousb1286.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iousb1286.h
@@ -28,14 +28,1127 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iousb1286.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* avr/iousb1286.h - definitions for AT90USB1286 */
 
 #ifndef _AVR_AT90USB1286_H_
 #define _AVR_AT90USB1286_H_ 1
 
-#include <avr/iousbxx6_7.h>
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iousbxx6_7.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0X01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0X02)
+#define PA7  7
+#define PA6  6
+#define PA5  5
+#define PA4  4
+#define PA3  3
+#define PA2  2
+#define PA1  1
+#define PA0  0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7  7
+#define PB6  6
+#define PB5  5
+#define PB4  4
+#define PB3  3
+#define PB2  2
+#define PB1  1
+#define PB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7  7
+#define PC6  6
+#define PC5  5
+#define PC4  4
+#define PC3  3
+#define PC2  2
+#define PC1  1
+#define PC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7  7
+#define PD6  6
+#define PD5  5
+#define PD4  4
+#define PD3  3
+#define PD2  2
+#define PD1  1
+#define PD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7  7
+#define PE6  6
+#define PE5  5
+#define PE4  4
+#define PE3  3
+#define PE2  2
+#define PE1  1
+#define PE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7  7
+#define PF6  6
+#define PF5  5
+#define PF4  4
+#define PF3  3
+#define PF2  2
+#define PF1  1
+#define PF0  0
+
+/* Reserved [0x12..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8(0x17)
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define TIFR3   _SFR_IO8(0x18)
+#define ICF3    5
+#define OCF3C   3
+#define OCF3B   2
+#define OCF3A   1
+#define TOV3    0
+
+/* Reserved [0x19..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLLP2   4
+#define PLLP1   3
+#define PLLP0   2
+#define PLLE    1
+#define PLOCK   0
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8(0x31)
+#define OCDR    _SFR_IO8(0x31)
+#define IDRD    7
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0x3B)
+
+
+/* Reserved [0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTWI   7
+#define PRTIM2  6
+#define PRTIM0  5
+#define PRTIM1  3
+#define PRSPI   2
+#define PRADC   0
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSB   7
+#define PRTIM3  3
+#define PRUSART1 0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRUSB))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRUSB
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+/* Reserved [0x6C..0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define ICIE3   5
+#define OCIE3C  3
+#define OCIE3B  2
+#define OCIE3A  1
+#define TOIE3   0
+
+/* Reserved [0x72..0x73] */
+
+#define XMCRA   _SFR_MEM8(0x74)
+#define SRE     7
+#define SRL2    6
+#define SRL1    5
+#define SRL0    4
+#define SRW11   3
+#define SRW10   2
+#define SRW01   1
+#define SRW00   0
+
+#define XMCRB   _SFR_MEM8(0x75)
+#define XMBK    7
+#define XMM2    2
+#define XMM1    1
+#define XMM0    0
+
+/* Reserved [0x76..0x77] */
+
+/* RegDef:  ADC Data Register */
+#ifndef __ASSEMBLER__
+#define ADC    _SFR_MEM16(0x78)
+#endif
+#define ADCW   _SFR_MEM16(0x78)
+#define ADCL   _SFR_MEM8(0x78)
+#define ADCH   _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADHSM  7
+#define ACME    6
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define COM3A1  7
+#define COM3A0  6
+#define COM3B1  5
+#define COM3B0  4
+#define COM3C1  3
+#define COM3C0  2
+#define WGM31   1
+#define WGM30   0
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define ICNC3   7
+#define ICES3   6
+#define WGM33   4
+#define WGM32   3
+#define CS32    2
+#define CS31    1
+#define CS30    0
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3A   7
+#define FOC3B   6
+#define FOC3C   5
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define EXCLK   6
+#define AS2     5
+#define TCN2UB  4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+/* Reserved [0xBE..0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define UHWCON  _SFR_MEM8(0XD7)
+#define UIMOD   7
+#define UIDE    6
+#define UVCONE  4
+#define UVREGE  0
+
+#define USBCON  _SFR_MEM8(0XD8)
+#define USBE    7
+#define HOST    6
+#define FRZCLK  5
+#define OTGPADE 4
+#define IDTE    1
+#define VBUSTE  0
+
+#define USBSTA  _SFR_MEM8(0XD9)
+#define SPEED   3
+#define ID      1
+#define VBUS    0
+
+#define USBINT  _SFR_MEM8(0XDA)
+#define IDTI    1
+#define VBUSTI  0
+
+/* Combine UDPADDL and UDPADDH */
+#define UDPADD  _SFR_MEM16(0xDB)
+
+#define UDPADDL _SFR_MEM8(0xDB)
+#define UDPADDH _SFR_MEM8(0xDC)
+#define DPACC   7
+
+#define UDCON   _SFR_MEM8(0XE0)
+#define LSM     2
+#define RMWKUP  1
+#define DETACH  0
+
+#define UDINT   _SFR_MEM8(0XE1)
+#define UPRSMI  6
+#define EORSMI  5
+#define WAKEUPI 4
+#define EORSTI  3
+#define SOFI    2
+/* #define MSOFI   1 */ /* Reserved */
+#define SUSPI   0
+
+#define UDIEN   _SFR_MEM8(0XE2)
+#define UPRSME  6
+#define EORSME  5
+#define WAKEUPE 4
+#define EORSTE  3
+#define SOFE    2
+/* #define MSOFE   1 */ /* Reserved */
+#define SUSPE   0
+
+#define UDADDR  _SFR_MEM8(0XE3)
+#define ADDEN   7
+
+/* Combine UDFNUML and UDFNUMH */
+#define UDFNUM  _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define UDFNUMH _SFR_MEM8(0xE5)
+
+#define UDMFN   _SFR_MEM8(0XE6)
+#define FNCERR  4
+
+#define UDTST   _SFR_MEM8(0XE7)
+#define OPMODE2 5
+#define TSTPCKT 4
+#define TSTK    3
+#define TSTJ    2
+
+#define UEINTX  _SFR_MEM8(0XE8)
+#define FIFOCON 7
+#define NAKINI  6
+#define RWAL    5
+#define NAKOUTI 4
+#define RXSTPI  3
+#define RXOUTI  2
+#define STALLEDI 1
+#define TXINI   0
+
+#define UENUM   _SFR_MEM8(0XE9)
+
+#define UERST   _SFR_MEM8(0XEA)
+#define EPRST6  6
+#define EPRST5  5
+#define EPRST4  4
+#define EPRST3  3
+#define EPRST2  2
+#define EPRST1  1
+#define EPRST0  0
+
+#define UECONX  _SFR_MEM8(0XEB)
+#define STALLRQ 5
+#define STALLRQC 4
+#define RSTDT   3
+#define EPEN    0
+
+#define UECFG0X _SFR_MEM8(0XEC)
+#define EPTYPE1 7
+#define EPTYPE0 6
+/* #define ISOSW   3 */ /* Reserved */
+/* #define AUTOSW  2 */ /* Reserved */
+/* #define NYETSDIS 1 */ /* Reserved */
+#define EPDIR   0
+
+#define UECFG1X  _SFR_MEM8(0XED)
+#define EPSIZE2 6
+#define EPSIZE1 5
+#define EPSIZE0 4
+#define EPBK1   3
+#define EPBK0   2
+#define ALLOC   1
+
+#define UESTA0X _SFR_MEM8(0XEE)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define ZLPSEEN 4
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UESTA1X _SFR_MEM8(0XEF)
+#define CTRLDIR 2
+#define CURRBK1 1
+#define CURRBK0 0
+
+#define UEIENX  _SFR_MEM8(0XF0)
+#define FLERRE  7
+#define NAKINE  6
+#define NAKOUTE 4
+#define RXSTPE  3
+#define RXOUTE  2
+#define STALLEDE 1
+#define TXINE   0
+
+#define UEDATX  _SFR_MEM8(0XF1)
+
+/* Combine UEBCLX and UEBCHX */
+#define UEBCX   _SFR_MEM16(0xF2)
+
+#define UEBCLX  _SFR_MEM8(0xF2)
+#define UEBCHX  _SFR_MEM8(0xF3)
+
+#define UEINT   _SFR_MEM8(0XF4)
+#define EPINT6  6
+#define EPINT5  5
+#define EPINT4  4
+#define EPINT3  3
+#define EPINT2  2
+#define EPINT1  1
+#define EPINT0  0
+
+/* Reserved [0xFA..0xFF] */
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num			1
+#define INT0_vect	    		_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num			2
+#define INT1_vect	    		_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num			3
+#define INT2_vect	    		_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num			4
+#define INT3_vect	    		_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num			5
+#define INT4_vect	    		_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num			6
+#define INT5_vect	    		_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num			7
+#define INT6_vect	    		_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num			8
+#define INT7_vect	    		_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num			9
+#define PCINT0_vect		    	_VECTOR(9)
+
+/* USB General Interrupt Request */
+#define USB_GEN_vect_num		10
+#define USB_GEN_vect			_VECTOR(10)
+
+/* USB Endpoint/Pipe Interrupt Communication Request */
+#define USB_COM_vect_num		11
+#define USB_COM_vect			_VECTOR(11)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num			12
+#define WDT_vect	    		_VECTOR(12)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	13
+#define TIMER2_COMPA_vect		_VECTOR(13)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	14
+#define TIMER2_COMPB_vect		_VECTOR(14)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		15
+#define TIMER2_OVF_vect			_VECTOR(15)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	16
+#define TIMER1_CAPT_vect		_VECTOR(16)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	17
+#define TIMER1_COMPA_vect		_VECTOR(17)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	18
+#define TIMER1_COMPB_vect		_VECTOR(18)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	19
+#define TIMER1_COMPC_vect		_VECTOR(19)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		20
+#define TIMER1_OVF_vect			_VECTOR(20)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	21
+#define TIMER0_COMPA_vect		_VECTOR(21)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	22
+#define TIMER0_COMPB_vect		_VECTOR(22)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		23
+#define TIMER0_OVF_vect			_VECTOR(23)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		24
+#define SPI_STC_vect			_VECTOR(24)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		25
+#define USART1_RX_vect			_VECTOR(25)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num    26
+#define USART1_UDRE_vect		_VECTOR(26)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		27
+#define USART1_TX_vect			_VECTOR(27)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	28
+#define ANALOG_COMP_vect		_VECTOR(28)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			29
+#define ADC_vect	    		_VECTOR(29)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		30
+#define EE_READY_vect			_VECTOR(30)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	31
+#define TIMER3_CAPT_vect		_VECTOR(31)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	32
+#define TIMER3_COMPA_vect		_VECTOR(32)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	33
+#define TIMER3_COMPB_vect		_VECTOR(33)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	34
+#define TIMER3_COMPC_vect		_VECTOR(34)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		35
+#define TIMER3_OVF_vect			_VECTOR(35)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num			36
+#define TWI_vect			    _VECTOR(36)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		37
+#define SPM_READY_vect			_VECTOR(37)
+
+#define _VECTORS_SIZE 152
+
 
 /* Constants */
 #define SPM_PAGESIZE 256
@@ -91,7 +1204,6 @@
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x82
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -99,5 +1211,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_AT90USB1286_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iousb1287.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iousb1287.h
@@ -28,14 +28,1282 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iousb1287.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* avr/iousb1287.h - definitions for AT90USB1287 */
 
 #ifndef _AVR_AT90USB1287_H_
 #define _AVR_AT90USB1287_H_ 1
 
-#include <avr/iousbxx6_7.h>
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iousbxx6_7.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0X01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0X02)
+#define PA7  7
+#define PA6  6
+#define PA5  5
+#define PA4  4
+#define PA3  3
+#define PA2  2
+#define PA1  1
+#define PA0  0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7  7
+#define PB6  6
+#define PB5  5
+#define PB4  4
+#define PB3  3
+#define PB2  2
+#define PB1  1
+#define PB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7  7
+#define PC6  6
+#define PC5  5
+#define PC4  4
+#define PC3  3
+#define PC2  2
+#define PC1  1
+#define PC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7  7
+#define PD6  6
+#define PD5  5
+#define PD4  4
+#define PD3  3
+#define PD2  2
+#define PD1  1
+#define PD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7  7
+#define PE6  6
+#define PE5  5
+#define PE4  4
+#define PE3  3
+#define PE2  2
+#define PE1  1
+#define PE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7  7
+#define PF6  6
+#define PF5  5
+#define PF4  4
+#define PF3  3
+#define PF2  2
+#define PF1  1
+#define PF0  0
+
+/* Reserved [0x12..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8(0x17)
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define TIFR3   _SFR_IO8(0x18)
+#define ICF3    5
+#define OCF3C   3
+#define OCF3B   2
+#define OCF3A   1
+#define TOV3    0
+
+/* Reserved [0x19..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLLP2   4
+#define PLLP1   3
+#define PLLP0   2
+#define PLLE    1
+#define PLOCK   0
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8(0x31)
+#define OCDR    _SFR_IO8(0x31)
+#define IDRD    7
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3A] */
+
+#define RAMPZ   _SFR_IO8(0x3B)
+
+/* Reserved [0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTWI   7
+#define PRTIM2  6
+#define PRTIM0  5
+#define PRTIM1  3
+#define PRSPI   2
+#define PRADC   0
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSB   7
+#define PRTIM3  3
+#define PRUSART1 0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRUSB))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRUSB
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+/* Reserved [0x6C..0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define ICIE3   5
+#define OCIE3C  3
+#define OCIE3B  2
+#define OCIE3A  1
+#define TOIE3   0
+
+/* Reserved [0x72..0x73] */
+
+#define XMCRA   _SFR_MEM8(0x74)
+#define SRE     7
+#define SRL2    6
+#define SRL1    5
+#define SRL0    4
+#define SRW11   3
+#define SRW10   2
+#define SRW01   1
+#define SRW00   0
+
+#define XMCRB   _SFR_MEM8(0x75)
+#define XMBK    7
+#define XMM2    2
+#define XMM1    1
+#define XMM0    0
+
+/* Reserved [0x76..0x77] */
+
+/* RegDef:  ADC Data Register */
+#ifndef __ASSEMBLER__
+#define ADC    _SFR_MEM16(0x78)
+#endif
+#define ADCW   _SFR_MEM16(0x78)
+#define ADCL   _SFR_MEM8(0x78)
+#define ADCH   _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADHSM  7
+#define ACME    6
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define COM3A1  7
+#define COM3A0  6
+#define COM3B1  5
+#define COM3B0  4
+#define COM3C1  3
+#define COM3C0  2
+#define WGM31   1
+#define WGM30   0
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define ICNC3   7
+#define ICES3   6
+#define WGM33   4
+#define WGM32   3
+#define CS32    2
+#define CS31    1
+#define CS30    0
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3A   7
+#define FOC3B   6
+#define FOC3C   5
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+#define UHCON   _SFR_MEM8(0x9E)
+#define RESUME  2
+#define RESET   1
+#define SOFEN   0
+
+#define UHINT   _SFR_MEM8(0x9F)
+#define HWUPI   6
+#define HSOFI   5
+#define RXRSMI  4
+#define RSMEDI  3
+#define RSTI    2
+#define DDISCI  1
+#define DCONNI  0
+
+#define UHIEN   _SFR_MEM8(0xA0)
+#define HWUPE   6
+#define HSOFE   5
+#define RXRSME  4
+#define RSMEDE  3
+#define RSTE    2
+#define DDISCE  1
+#define DCONNE  0
+
+#define UHADDR  _SFR_MEM8(0xA1)
+
+/* Combine UHFNUML and UHFNUMH */
+#define UHFNUM  _SFR_MEM16(0xA2)
+
+#define UHFNUML _SFR_MEM8(0xA2)
+#define UHFNUMH _SFR_MEM8(0xA3)
+
+#define UHFLEN  _SFR_MEM8(0xA4)
+
+#define UPINRQX _SFR_MEM8(0xA5)
+
+#define UPINTX  _SFR_MEM8(0xA6)
+#define FIFOCON 7
+#define NAKEDI  6
+#define RWAL    5
+#define PERRI   4
+#define TXSTPI  3
+#define TXOUTI  2
+#define RXSTALLI 1
+#define RXINI   0
+
+#define UPNUM   _SFR_MEM8(0xA7)
+
+#define UPRST   _SFR_MEM8(0xA8)
+#define PRST6   6
+#define PRST5   5
+#define PRST4   4
+#define PRST3   3
+#define PRST2   2
+#define PRST1   1
+#define PRST0   0
+
+#define UPCONX  _SFR_MEM8(0xA9)
+#define PFREEZE 6
+#define INMODE  5
+/* #define AUTOSW  4 */ /* Reserved */
+#define RSTDT   3
+#define PEN     0
+
+#define UPCFG0X _SFR_MEM8(0XAA)
+#define PTYPE1  7
+#define PTYPE0  6
+#define PTOKEN1 5
+#define PTOKEN0 4
+#define PEPNUM3 3
+#define PEPNUM2 2
+#define PEPNUM1 1
+#define PEPNUM0 0
+
+#define UPCFG1X _SFR_MEM8(0XAB)
+#define PSIZE2  6
+#define PSIZE1  5
+#define PSIZE0  4
+#define PBK1    3
+#define PBK0    2
+#define ALLOC   1
+
+#define UPSTAX  _SFR_MEM8(0XAC)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UPCFG2X _SFR_MEM8(0XAD)
+
+#define UPIENX  _SFR_MEM8(0XAE)
+#define FLERRE  7
+#define NAKEDE  6
+#define PERRE   4
+#define TXSTPE  3
+#define TXOUTE  2
+#define RXSTALLE 1
+#define RXINE   0
+
+#define UPDATX  _SFR_MEM8(0XAF)
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define EXCLK   6
+#define AS2     5
+#define TCN2UB  4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+/* Reserved [0xBE..0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define UHWCON  _SFR_MEM8(0XD7)
+#define UIMOD   7
+#define UIDE    6
+#define UVCONE  4
+#define UVREGE  0
+
+#define USBCON  _SFR_MEM8(0XD8)
+#define USBE    7
+#define HOST    6
+#define FRZCLK  5
+#define OTGPADE 4
+#define IDTE    1
+#define VBUSTE  0
+
+#define USBSTA  _SFR_MEM8(0XD9)
+#define SPEED   3
+#define ID      1
+#define VBUS    0
+
+#define USBINT  _SFR_MEM8(0XDA)
+#define IDTI    1
+#define VBUSTI  0
+
+/* Combine UDPADDL and UDPADDH */
+#define UDPADD  _SFR_MEM16(0xDB)
+
+#define UDPADDL _SFR_MEM8(0xDB)
+#define UDPADDH _SFR_MEM8(0xDC)
+#define DPACC   7
+
+#define OTGCON  _SFR_MEM8(0XDD)
+#define HNPREQ  5
+#define SRPREQ  4
+#define SRPSEL  3
+#define VBUSHWC 2
+#define VBUSREQ 1
+#define VBUSRQC 0
+
+#define OTGIEN  _SFR_MEM8(0XDE)
+#define STOE    5
+#define HNPERRE 4
+#define ROLEEXE 3
+#define BCERRE  2
+#define VBERRE  1
+#define SRPE    0
+
+#define OTGINT  _SFR_MEM8(0XDF)
+#define STOI    5
+#define HNPERRI 4
+#define ROLEEXI 3
+#define BCERRI  2
+#define VBERRI  1
+#define SRPI    0
+
+#define UDCON   _SFR_MEM8(0XE0)
+#define LSM     2
+#define RMWKUP  1
+#define DETACH  0
+
+#define UDINT   _SFR_MEM8(0XE1)
+#define UPRSMI  6
+#define EORSMI  5
+#define WAKEUPI 4
+#define EORSTI  3
+#define SOFI    2
+/* #define MSOFI   1 */ /* Reserved */
+#define SUSPI   0
+
+#define UDIEN   _SFR_MEM8(0XE2)
+#define UPRSME  6
+#define EORSME  5
+#define WAKEUPE 4
+#define EORSTE  3
+#define SOFE    2
+/* #define MSOFE   1 */ /* Reserved */
+#define SUSPE   0
+
+#define UDADDR  _SFR_MEM8(0XE3)
+#define ADDEN   7
+
+/* Combine UDFNUML and UDFNUMH */
+#define UDFNUM  _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define UDFNUMH _SFR_MEM8(0xE5)
+
+#define UDMFN   _SFR_MEM8(0XE6)
+#define FNCERR  4
+
+#define UDTST   _SFR_MEM8(0XE7)
+#define OPMODE2 5
+#define TSTPCKT 4
+#define TSTK    3
+#define TSTJ    2
+
+#define UEINTX  _SFR_MEM8(0XE8)
+#define FIFOCON 7
+#define NAKINI  6
+#define RWAL    5
+#define NAKOUTI 4
+#define RXSTPI  3
+#define RXOUTI  2
+#define STALLEDI 1
+#define TXINI   0
+
+#define UENUM   _SFR_MEM8(0XE9)
+
+#define UERST   _SFR_MEM8(0XEA)
+#define EPRST6  6
+#define EPRST5  5
+#define EPRST4  4
+#define EPRST3  3
+#define EPRST2  2
+#define EPRST1  1
+#define EPRST0  0
+
+#define UECONX  _SFR_MEM8(0XEB)
+#define STALLRQ 5
+#define STALLRQC 4
+#define RSTDT   3
+#define EPEN    0
+
+#define UECFG0X _SFR_MEM8(0XEC)
+#define EPTYPE1 7
+#define EPTYPE0 6
+/* #define ISOSW   3 */ /* Reserved */
+/* #define AUTOSW  2 */ /* Reserved */
+/* #define NYETSDIS 1 */ /* Reserved */
+#define EPDIR   0
+
+#define UECFG1X  _SFR_MEM8(0XED)
+#define EPSIZE2 6
+#define EPSIZE1 5
+#define EPSIZE0 4
+#define EPBK1   3
+#define EPBK0   2
+#define ALLOC   1
+
+#define UESTA0X _SFR_MEM8(0XEE)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define ZLPSEEN 4
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UESTA1X _SFR_MEM8(0XEF)
+#define CTRLDIR 2
+#define CURRBK1 1
+#define CURRBK0 0
+
+#define UEIENX  _SFR_MEM8(0XF0)
+#define FLERRE  7
+#define NAKINE  6
+#define NAKOUTE 4
+#define RXSTPE  3
+#define RXOUTE  2
+#define STALLEDE 1
+#define TXINE   0
+
+#define UEDATX  _SFR_MEM8(0XF1)
+
+/* Combine UEBCLX and UEBCHX */
+#define UEBCX   _SFR_MEM16(0xF2)
+
+#define UEBCLX  _SFR_MEM8(0xF2)
+#define UEBCHX  _SFR_MEM8(0xF3)
+
+#define UEINT   _SFR_MEM8(0XF4)
+#define EPINT6  6
+#define EPINT5  5
+#define EPINT4  4
+#define EPINT3  3
+#define EPINT2  2
+#define EPINT1  1
+#define EPINT0  0
+
+#define UPERRX  _SFR_MEM8(0XF5)
+#define COUNTER1 6
+#define COUNTER0 5
+#define CRC16    4
+#define TIMEOUT  3
+#define PID      2
+#define DATAPID  1
+#define DATATGL  0
+
+/* Combine UPBCLX and UPBCHX */
+#define UPBCX   _SFR_MEM16(0xF6)
+
+#define UPBCLX  _SFR_MEM8(0xF6)
+#define UPBCHX  _SFR_MEM8(0xF7)
+
+#define UPINT   _SFR_MEM8(0XF8)
+#define PINT6   6
+#define PINT5   5
+#define PINT4   4
+#define PINT3   3
+#define PINT2   2
+#define PINT1   1
+#define PINT0   0
+
+#define OTGTCON _SFR_MEM8(0XF9)
+#define PAGE1   6
+#define PAGE0   5
+#define VALUE1  1
+#define VALUE0  0
+
+/* Reserved [0xFA..0xFF] */
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num			1
+#define INT0_vect	    		_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num			2
+#define INT1_vect	    		_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num			3
+#define INT2_vect	    		_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num			4
+#define INT3_vect	    		_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num			5
+#define INT4_vect	    		_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num			6
+#define INT5_vect	    		_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num			7
+#define INT6_vect	    		_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num			8
+#define INT7_vect	    		_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num			9
+#define PCINT0_vect		    	_VECTOR(9)
+
+/* USB General Interrupt Request */
+#define USB_GEN_vect_num		10
+#define USB_GEN_vect			_VECTOR(10)
+
+/* USB Endpoint/Pipe Interrupt Communication Request */
+#define USB_COM_vect_num		11
+#define USB_COM_vect			_VECTOR(11)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num			12
+#define WDT_vect	    		_VECTOR(12)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	13
+#define TIMER2_COMPA_vect		_VECTOR(13)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	14
+#define TIMER2_COMPB_vect		_VECTOR(14)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		15
+#define TIMER2_OVF_vect			_VECTOR(15)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	16
+#define TIMER1_CAPT_vect		_VECTOR(16)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	17
+#define TIMER1_COMPA_vect		_VECTOR(17)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	18
+#define TIMER1_COMPB_vect		_VECTOR(18)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	19
+#define TIMER1_COMPC_vect		_VECTOR(19)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		20
+#define TIMER1_OVF_vect			_VECTOR(20)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	21
+#define TIMER0_COMPA_vect		_VECTOR(21)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	22
+#define TIMER0_COMPB_vect		_VECTOR(22)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		23
+#define TIMER0_OVF_vect			_VECTOR(23)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		24
+#define SPI_STC_vect			_VECTOR(24)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		25
+#define USART1_RX_vect			_VECTOR(25)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num    26
+#define USART1_UDRE_vect		_VECTOR(26)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		27
+#define USART1_TX_vect			_VECTOR(27)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	28
+#define ANALOG_COMP_vect		_VECTOR(28)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			29
+#define ADC_vect	    		_VECTOR(29)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		30
+#define EE_READY_vect			_VECTOR(30)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	31
+#define TIMER3_CAPT_vect		_VECTOR(31)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	32
+#define TIMER3_COMPA_vect		_VECTOR(32)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	33
+#define TIMER3_COMPB_vect		_VECTOR(33)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	34
+#define TIMER3_COMPC_vect		_VECTOR(34)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		35
+#define TIMER3_OVF_vect			_VECTOR(35)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num			36
+#define TWI_vect			    _VECTOR(36)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		37
+#define SPM_READY_vect			_VECTOR(37)
+
+#define _VECTORS_SIZE 152
 
 /* Constants */
 #define SPM_PAGESIZE 256
@@ -91,7 +1359,6 @@
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x82
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -99,5 +1366,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_AT90USB1287_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iousb162.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iousb162.h
@@ -29,14 +29,783 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iousb162.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* avr/iousb162.h - definitions for AT90USB162 */
 
 #ifndef _AVR_AT90USB162_H_
 #define _AVR_AT90USB162_H_ 1
 
-#include <avr/iousbxx2.h>
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iousbxx2.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+/* Reserved [0x00..0x02] */
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7     7
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+/* Reserved [0xC..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+/* Reserved [0x17..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLLP2   4
+#define PLLP1   3
+#define PLLP0   2
+#define PLLE    1
+#define PLOCK   0
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define DWDR    _SFR_IO8(0x31)
+#define IDRD    7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define USBRF   5
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define WDTCKD  _SFR_MEM8(0x62)
+#define WDEWIF  3
+#define WDEWIE  2
+#define WCLKD1  1
+#define WCLKD0  0
+
+#define REGCR   _SFR_MEM8(0x63)
+#define REGDIS  0
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTIM0  5
+#define PRTIM1  3
+#define PRSPI   2
+
+#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0))
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSB   7
+#define PRUSART1 0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRUSB))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRUSB
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+/* Reserved [0x70..0x7F] */
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+#define UCSR1D  _SFR_MEM8(0xCB)
+#define CTSEN   1
+#define RTSEN   0
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF] */
+
+#define CKSEL0  _SFR_MEM8(0XD0)	/* old name; up to AVR Studio v 4.13 */
+#define CLKSEL0 _SFR_MEM8(0XD0)	/* since AVR Studio v 4.14 */
+#define RCSUT1  7
+#define RCSUT0  6
+#define EXSUT1  5
+#define EXSUT0  4
+#define RCE     3
+#define EXTE    2
+#define CLKS    0
+
+#define CKSEL1  _SFR_MEM8(0XD1)	/* old name */
+#define CLKSEL1 _SFR_MEM8(0XD1)
+#define RCCKSEL3 7
+#define RCCKSEL2 6
+#define RCCKSEL1 5
+#define RCCKSEL0 4
+#define EXCKSEL3 3
+#define EXCKSEL2 2
+#define EXCKSEL1 1
+#define EXCKSEL0 0
+
+#define CKSTA   _SFR_MEM8(0XD2)	/* old name */
+#define CLKSTA  _SFR_MEM8(0XD2)
+#define RCON    1
+#define EXTON   0
+
+/* Reserved [0xD3..0xD7] */
+
+#define USBCON  _SFR_MEM8(0XD8)
+#define USBE    7
+#define FRZCLK  5
+
+/* Reserved [0xD9..0xDA] */
+
+/* Combine UDPADDL and UDPADDH */
+#define UDPADD  _SFR_MEM16(0xDB)
+
+#define UDPADDL _SFR_MEM8(0xDB)
+#define UDPADDH _SFR_MEM8(0xDC)
+#define DPACC   7
+
+/* Reserved [0xDD..0xDF] */
+
+#define UDCON   _SFR_MEM8(0XE0)
+#define RSTCPU  2
+#define RMWKUP  1
+#define DETACH  0
+
+#define UDINT   _SFR_MEM8(0XE1)
+#define UPRSMI  6
+#define EORSMI  5
+#define WAKEUPI 4
+#define EORSTI  3
+#define SOFI    2
+#define SUSPI   0
+
+#define UDIEN   _SFR_MEM8(0XE2)
+#define UPRSME  6
+#define EORSME  5
+#define WAKEUPE 4
+#define EORSTE  3
+#define SOFE    2
+#define SUSPE   0
+
+#define UDADDR  _SFR_MEM8(0XE3)
+#define ADDEN   7
+
+/* Combine UDFNUML and UDFNUMH */
+#define UDFNUM  _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define UDFNUMH _SFR_MEM8(0xE5)
+
+#define UDMFN   _SFR_MEM8(0XE6)
+#define FNCERR  4
+
+/* Reserved [0xE7] */
+
+#define UEINTX  _SFR_MEM8(0XE8)
+#define FIFOCON 7
+#define NAKINI  6
+#define RWAL    5
+#define NAKOUTI 4
+#define RXSTPI  3
+#define RXOUTI  2
+#define STALLEDI 1
+#define TXINI   0
+
+#define UENUM   _SFR_MEM8(0XE9)
+#define EPNUM2  2
+#define EPNUM1  1
+#define EPNUM0  0
+
+#define UERST   _SFR_MEM8(0XEA)
+#define EPRST4  4
+#define EPRST3  3
+#define EPRST2  2
+#define EPRST1  1
+#define EPRST0  0
+
+#define UECONX  _SFR_MEM8(0XEB)
+#define STALLRQ 5
+#define STALLRQC 4
+#define RSTDT   3
+#define EPEN    0
+
+#define UECFG0X _SFR_MEM8(0XEC)
+#define EPTYPE1 7
+#define EPTYPE0 6
+#define EPDIR   0
+
+#define UECFG1X  _SFR_MEM8(0XED)
+#define EPSIZE2 6
+#define EPSIZE1 5
+#define EPSIZE0 4
+#define EPBK1   3
+#define EPBK0   2
+#define ALLOC   1
+
+#define UESTA0X _SFR_MEM8(0XEE)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UESTA1X _SFR_MEM8(0XEF)
+#define CTRLDIR 2
+#define CURRBK1 1
+#define CURRBK0 0
+
+#define UEIENX  _SFR_MEM8(0XF0)
+#define FLERRE  7
+#define NAKINE  6
+#define NAKOUTE 4
+#define RXSTPE  3
+#define RXOUTE  2
+#define STALLEDE 1
+#define TXINE   0
+
+#define UEDATX  _SFR_MEM8(0XF1)
+
+#define UEBCLX  _SFR_MEM8(0xF2)
+
+/* Reserved [0xF3] */
+
+#define UEINT   _SFR_MEM8(0XF4)
+#define EPINT4  4
+#define EPINT3  3
+#define EPINT2  2
+#define EPINT1  1
+#define EPINT0  0
+
+/* Reserved [0xF5..0xF9] */
+
+#define PS2CON  _SFR_MEM8(0XFA)
+#define PS2EN   0
+
+#define UPOE    _SFR_MEM8(0XFB)
+#define UPWE1   7
+#define UPWE0   6
+#define UPDRV1  5
+#define UPDRV0  4
+#define SCKI    3
+#define DATAI   2
+#define DPI     1
+#define DMI     0
+
+/* Reserved [0xFC..0xFF] */
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num   	7
+#define INT6_vect			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		9
+#define PCINT0_vect			_VECTOR(9)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		10
+#define PCINT1_vect			_VECTOR(10)
+
+/* USB General Interrupt Request */
+#define USB_GEN_vect_num    	11
+#define USB_GEN_vect			_VECTOR(11)
+
+/* USB Endpoint/Pipe Interrupt Communication Request */
+#define USB_COM_vect_num		12
+#define USB_COM_vect			_VECTOR(12)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		13
+#define WDT_vect			_VECTOR(13)
+
+/* Timer/Counter2 Capture Event */
+#define TIMER1_CAPT_vect_num	14
+#define TIMER1_CAPT_vect		_VECTOR(14)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPA_vect_num	15
+#define TIMER1_COMPA_vect		_VECTOR(15)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPB_vect_num	16
+#define TIMER1_COMPB_vect		_VECTOR(16)
+
+/* Timer/Counter2 Compare Match C */
+#define TIMER1_COMPC_vect_num	17
+#define TIMER1_COMPC_vect		_VECTOR(17)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		18
+#define TIMER1_OVF_vect			_VECTOR(18)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	19
+#define TIMER0_COMPA_vect		_VECTOR(19)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	20
+#define TIMER0_COMPB_vect		_VECTOR(20)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		21
+#define TIMER0_OVF_vect			_VECTOR(21)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		22
+#define SPI_STC_vect			_VECTOR(22)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		23
+#define USART1_RX_vect			_VECTOR(23)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num	24
+#define USART1_UDRE_vect		_VECTOR(24)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		25
+#define USART1_TX_vect			_VECTOR(25)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	26
+#define ANALOG_COMP_vect		_VECTOR(26)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		27
+#define EE_READY_vect			_VECTOR(27)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num   	28
+#define SPM_READY_vect			_VECTOR(28)
+
+#define _VECTORS_SIZE 116
+
 
 /* Constants */
 #define SPM_PAGESIZE 128
@@ -92,12 +861,10 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x82
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_AT90USB162_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iousb646.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iousb646.h
@@ -29,14 +29,1122 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iousb646.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* avr/iousb646.h - definitions for AT90USB646 */
 
 #ifndef _AVR_AT90USB646_H_
 #define _AVR_AT90USB646_H_ 1
 
-#include <avr/iousbxx6_7.h>
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iousbxx6_7.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0X01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0X02)
+#define PA7  7
+#define PA6  6
+#define PA5  5
+#define PA4  4
+#define PA3  3
+#define PA2  2
+#define PA1  1
+#define PA0  0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7  7
+#define PB6  6
+#define PB5  5
+#define PB4  4
+#define PB3  3
+#define PB2  2
+#define PB1  1
+#define PB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7  7
+#define PC6  6
+#define PC5  5
+#define PC4  4
+#define PC3  3
+#define PC2  2
+#define PC1  1
+#define PC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7  7
+#define PD6  6
+#define PD5  5
+#define PD4  4
+#define PD3  3
+#define PD2  2
+#define PD1  1
+#define PD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7  7
+#define PE6  6
+#define PE5  5
+#define PE4  4
+#define PE3  3
+#define PE2  2
+#define PE1  1
+#define PE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7  7
+#define PF6  6
+#define PF5  5
+#define PF4  4
+#define PF3  3
+#define PF2  2
+#define PF1  1
+#define PF0  0
+
+/* Reserved [0x12..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8(0x17)
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define TIFR3   _SFR_IO8(0x18)
+#define ICF3    5
+#define OCF3C   3
+#define OCF3B   2
+#define OCF3A   1
+#define TOV3    0
+
+/* Reserved [0x19..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLLP2   4
+#define PLLP1   3
+#define PLLP0   2
+#define PLLE    1
+#define PLOCK   0
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8(0x31)
+#define OCDR    _SFR_IO8(0x31)
+#define IDRD    7
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3A] */
+/* Reserved [0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTWI   7
+#define PRTIM2  6
+#define PRTIM0  5
+#define PRTIM1  3
+#define PRSPI   2
+#define PRADC   0
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSB   7
+#define PRTIM3  3
+#define PRUSART1 0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRUSB))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRUSB
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+/* Reserved [0x6C..0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define ICIE3   5
+#define OCIE3C  3
+#define OCIE3B  2
+#define OCIE3A  1
+#define TOIE3   0
+
+/* Reserved [0x72..0x73] */
+
+#define XMCRA   _SFR_MEM8(0x74)
+#define SRE     7
+#define SRL2    6
+#define SRL1    5
+#define SRL0    4
+#define SRW11   3
+#define SRW10   2
+#define SRW01   1
+#define SRW00   0
+
+#define XMCRB   _SFR_MEM8(0x75)
+#define XMBK    7
+#define XMM2    2
+#define XMM1    1
+#define XMM0    0
+
+/* Reserved [0x76..0x77] */
+
+/* RegDef:  ADC Data Register */
+#ifndef __ASSEMBLER__
+#define ADC    _SFR_MEM16(0x78)
+#endif
+#define ADCW   _SFR_MEM16(0x78)
+#define ADCL   _SFR_MEM8(0x78)
+#define ADCH   _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADHSM  7
+#define ACME    6
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define COM3A1  7
+#define COM3A0  6
+#define COM3B1  5
+#define COM3B0  4
+#define COM3C1  3
+#define COM3C0  2
+#define WGM31   1
+#define WGM30   0
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define ICNC3   7
+#define ICES3   6
+#define WGM33   4
+#define WGM32   3
+#define CS32    2
+#define CS31    1
+#define CS30    0
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3A   7
+#define FOC3B   6
+#define FOC3C   5
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define EXCLK   6
+#define AS2     5
+#define TCN2UB  4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+/* Reserved [0xBE..0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define UHWCON  _SFR_MEM8(0XD7)
+#define UIMOD   7
+#define UIDE    6
+#define UVCONE  4
+#define UVREGE  0
+
+#define USBCON  _SFR_MEM8(0XD8)
+#define USBE    7
+#define HOST    6
+#define FRZCLK  5
+#define OTGPADE 4
+#define IDTE    1
+#define VBUSTE  0
+
+#define USBSTA  _SFR_MEM8(0XD9)
+#define SPEED   3
+#define ID      1
+#define VBUS    0
+
+#define USBINT  _SFR_MEM8(0XDA)
+#define IDTI    1
+#define VBUSTI  0
+
+/* Combine UDPADDL and UDPADDH */
+#define UDPADD  _SFR_MEM16(0xDB)
+
+#define UDPADDL _SFR_MEM8(0xDB)
+#define UDPADDH _SFR_MEM8(0xDC)
+#define DPACC   7
+
+#define UDCON   _SFR_MEM8(0XE0)
+#define LSM     2
+#define RMWKUP  1
+#define DETACH  0
+
+#define UDINT   _SFR_MEM8(0XE1)
+#define UPRSMI  6
+#define EORSMI  5
+#define WAKEUPI 4
+#define EORSTI  3
+#define SOFI    2
+/* #define MSOFI   1 */ /* Reserved */
+#define SUSPI   0
+
+#define UDIEN   _SFR_MEM8(0XE2)
+#define UPRSME  6
+#define EORSME  5
+#define WAKEUPE 4
+#define EORSTE  3
+#define SOFE    2
+/* #define MSOFE   1 */ /* Reserved */
+#define SUSPE   0
+
+#define UDADDR  _SFR_MEM8(0XE3)
+#define ADDEN   7
+
+/* Combine UDFNUML and UDFNUMH */
+#define UDFNUM  _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define UDFNUMH _SFR_MEM8(0xE5)
+
+#define UDMFN   _SFR_MEM8(0XE6)
+#define FNCERR  4
+
+#define UDTST   _SFR_MEM8(0XE7)
+#define OPMODE2 5
+#define TSTPCKT 4
+#define TSTK    3
+#define TSTJ    2
+
+#define UEINTX  _SFR_MEM8(0XE8)
+#define FIFOCON 7
+#define NAKINI  6
+#define RWAL    5
+#define NAKOUTI 4
+#define RXSTPI  3
+#define RXOUTI  2
+#define STALLEDI 1
+#define TXINI   0
+
+#define UENUM   _SFR_MEM8(0XE9)
+
+#define UERST   _SFR_MEM8(0XEA)
+#define EPRST6  6
+#define EPRST5  5
+#define EPRST4  4
+#define EPRST3  3
+#define EPRST2  2
+#define EPRST1  1
+#define EPRST0  0
+
+#define UECONX  _SFR_MEM8(0XEB)
+#define STALLRQ 5
+#define STALLRQC 4
+#define RSTDT   3
+#define EPEN    0
+
+#define UECFG0X _SFR_MEM8(0XEC)
+#define EPTYPE1 7
+#define EPTYPE0 6
+/* #define ISOSW   3 */ /* Reserved */
+/* #define AUTOSW  2 */ /* Reserved */
+/* #define NYETSDIS 1 */ /* Reserved */
+#define EPDIR   0
+
+#define UECFG1X  _SFR_MEM8(0XED)
+#define EPSIZE2 6
+#define EPSIZE1 5
+#define EPSIZE0 4
+#define EPBK1   3
+#define EPBK0   2
+#define ALLOC   1
+
+#define UESTA0X _SFR_MEM8(0XEE)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define ZLPSEEN 4
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UESTA1X _SFR_MEM8(0XEF)
+#define CTRLDIR 2
+#define CURRBK1 1
+#define CURRBK0 0
+
+#define UEIENX  _SFR_MEM8(0XF0)
+#define FLERRE  7
+#define NAKINE  6
+#define NAKOUTE 4
+#define RXSTPE  3
+#define RXOUTE  2
+#define STALLEDE 1
+#define TXINE   0
+
+#define UEDATX  _SFR_MEM8(0XF1)
+
+/* Combine UEBCLX and UEBCHX */
+#define UEBCX   _SFR_MEM16(0xF2)
+
+#define UEBCLX  _SFR_MEM8(0xF2)
+#define UEBCHX  _SFR_MEM8(0xF3)
+
+#define UEINT   _SFR_MEM8(0XF4)
+#define EPINT6  6
+#define EPINT5  5
+#define EPINT4  4
+#define EPINT3  3
+#define EPINT2  2
+#define EPINT1  1
+#define EPINT0  0
+
+/* Reserved [0xFA..0xFF] */
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num			1
+#define INT0_vect	    		_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num			2
+#define INT1_vect	    		_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num			3
+#define INT2_vect	    		_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num			4
+#define INT3_vect	    		_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num			5
+#define INT4_vect	    		_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num			6
+#define INT5_vect	    		_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num			7
+#define INT6_vect	    		_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num			8
+#define INT7_vect	    		_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num			9
+#define PCINT0_vect		    	_VECTOR(9)
+
+/* USB General Interrupt Request */
+#define USB_GEN_vect_num		10
+#define USB_GEN_vect			_VECTOR(10)
+
+/* USB Endpoint/Pipe Interrupt Communication Request */
+#define USB_COM_vect_num		11
+#define USB_COM_vect			_VECTOR(11)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num			12
+#define WDT_vect	    		_VECTOR(12)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	13
+#define TIMER2_COMPA_vect		_VECTOR(13)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	14
+#define TIMER2_COMPB_vect		_VECTOR(14)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		15
+#define TIMER2_OVF_vect			_VECTOR(15)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	16
+#define TIMER1_CAPT_vect		_VECTOR(16)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	17
+#define TIMER1_COMPA_vect		_VECTOR(17)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	18
+#define TIMER1_COMPB_vect		_VECTOR(18)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	19
+#define TIMER1_COMPC_vect		_VECTOR(19)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		20
+#define TIMER1_OVF_vect			_VECTOR(20)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	21
+#define TIMER0_COMPA_vect		_VECTOR(21)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	22
+#define TIMER0_COMPB_vect		_VECTOR(22)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		23
+#define TIMER0_OVF_vect			_VECTOR(23)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		24
+#define SPI_STC_vect			_VECTOR(24)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		25
+#define USART1_RX_vect			_VECTOR(25)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num    26
+#define USART1_UDRE_vect		_VECTOR(26)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		27
+#define USART1_TX_vect			_VECTOR(27)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	28
+#define ANALOG_COMP_vect		_VECTOR(28)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			29
+#define ADC_vect	    		_VECTOR(29)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		30
+#define EE_READY_vect			_VECTOR(30)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	31
+#define TIMER3_CAPT_vect		_VECTOR(31)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	32
+#define TIMER3_COMPA_vect		_VECTOR(32)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	33
+#define TIMER3_COMPB_vect		_VECTOR(33)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	34
+#define TIMER3_COMPC_vect		_VECTOR(34)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		35
+#define TIMER3_OVF_vect			_VECTOR(35)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num			36
+#define TWI_vect			    _VECTOR(36)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		37
+#define SPM_READY_vect			_VECTOR(37)
+
+#define _VECTORS_SIZE 152
 
 /* Constants */
 #define SPM_PAGESIZE 256
@@ -92,7 +1200,6 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x82
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -100,5 +1207,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_AT90USB646_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iousb647.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iousb647.h
@@ -29,14 +29,1279 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iousb647.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* avr/iousb647.h - definitions for AT90USB647 */
 
 #ifndef _AVR_AT90USB647_H_
 #define _AVR_AT90USB647_H_ 1
 
-#include <avr/iousbxx6_7.h>
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iousbxx6_7.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0X01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0X02)
+#define PA7  7
+#define PA6  6
+#define PA5  5
+#define PA4  4
+#define PA3  3
+#define PA2  2
+#define PA1  1
+#define PA0  0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7  7
+#define PB6  6
+#define PB5  5
+#define PB4  4
+#define PB3  3
+#define PB2  2
+#define PB1  1
+#define PB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7  7
+#define PC6  6
+#define PC5  5
+#define PC4  4
+#define PC3  3
+#define PC2  2
+#define PC1  1
+#define PC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7  7
+#define PD6  6
+#define PD5  5
+#define PD4  4
+#define PD3  3
+#define PD2  2
+#define PD1  1
+#define PD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7  7
+#define PE6  6
+#define PE5  5
+#define PE4  4
+#define PE3  3
+#define PE2  2
+#define PE1  1
+#define PE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7  7
+#define PF6  6
+#define PF5  5
+#define PF4  4
+#define PF3  3
+#define PF2  2
+#define PF1  1
+#define PF0  0
+
+/* Reserved [0x12..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8(0x17)
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define TIFR3   _SFR_IO8(0x18)
+#define ICF3    5
+#define OCF3C   3
+#define OCF3B   2
+#define OCF3A   1
+#define TOV3    0
+
+/* Reserved [0x19..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLLP2   4
+#define PLLP1   3
+#define PLLP0   2
+#define PLLE    1
+#define PLOCK   0
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8(0x31)
+#define OCDR    _SFR_IO8(0x31)
+#define IDRD    7
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3A] */
+/* Reserved [0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTWI   7
+#define PRTIM2  6
+#define PRTIM0  5
+#define PRTIM1  3
+#define PRSPI   2
+#define PRADC   0
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSB   7
+#define PRTIM3  3
+#define PRUSART1 0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRUSB))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRUSB
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+/* Reserved [0x6C..0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define ICIE3   5
+#define OCIE3C  3
+#define OCIE3B  2
+#define OCIE3A  1
+#define TOIE3   0
+
+/* Reserved [0x72..0x73] */
+
+#define XMCRA   _SFR_MEM8(0x74)
+#define SRE     7
+#define SRL2    6
+#define SRL1    5
+#define SRL0    4
+#define SRW11   3
+#define SRW10   2
+#define SRW01   1
+#define SRW00   0
+
+#define XMCRB   _SFR_MEM8(0x75)
+#define XMBK    7
+#define XMM2    2
+#define XMM1    1
+#define XMM0    0
+
+/* Reserved [0x76..0x77] */
+
+/* RegDef:  ADC Data Register */
+#ifndef __ASSEMBLER__
+#define ADC    _SFR_MEM16(0x78)
+#endif
+#define ADCW   _SFR_MEM16(0x78)
+#define ADCL   _SFR_MEM8(0x78)
+#define ADCH   _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADHSM  7
+#define ACME    6
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define COM3A1  7
+#define COM3A0  6
+#define COM3B1  5
+#define COM3B0  4
+#define COM3C1  3
+#define COM3C0  2
+#define WGM31   1
+#define WGM30   0
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define ICNC3   7
+#define ICES3   6
+#define WGM33   4
+#define WGM32   3
+#define CS32    2
+#define CS31    1
+#define CS30    0
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3A   7
+#define FOC3B   6
+#define FOC3C   5
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+#define UHCON   _SFR_MEM8(0x9E)
+#define RESUME  2
+#define RESET   1
+#define SOFEN   0
+
+#define UHINT   _SFR_MEM8(0x9F)
+#define HWUPI   6
+#define HSOFI   5
+#define RXRSMI  4
+#define RSMEDI  3
+#define RSTI    2
+#define DDISCI  1
+#define DCONNI  0
+
+#define UHIEN   _SFR_MEM8(0xA0)
+#define HWUPE   6
+#define HSOFE   5
+#define RXRSME  4
+#define RSMEDE  3
+#define RSTE    2
+#define DDISCE  1
+#define DCONNE  0
+
+#define UHADDR  _SFR_MEM8(0xA1)
+
+/* Combine UHFNUML and UHFNUMH */
+#define UHFNUM  _SFR_MEM16(0xA2)
+
+#define UHFNUML _SFR_MEM8(0xA2)
+#define UHFNUMH _SFR_MEM8(0xA3)
+
+#define UHFLEN  _SFR_MEM8(0xA4)
+
+#define UPINRQX _SFR_MEM8(0xA5)
+
+#define UPINTX  _SFR_MEM8(0xA6)
+#define FIFOCON 7
+#define NAKEDI  6
+#define RWAL    5
+#define PERRI   4
+#define TXSTPI  3
+#define TXOUTI  2
+#define RXSTALLI 1
+#define RXINI   0
+
+#define UPNUM   _SFR_MEM8(0xA7)
+
+#define UPRST   _SFR_MEM8(0xA8)
+#define PRST6   6
+#define PRST5   5
+#define PRST4   4
+#define PRST3   3
+#define PRST2   2
+#define PRST1   1
+#define PRST0   0
+
+#define UPCONX  _SFR_MEM8(0xA9)
+#define PFREEZE 6
+#define INMODE  5
+/* #define AUTOSW  4 */ /* Reserved */
+#define RSTDT   3
+#define PEN     0
+
+#define UPCFG0X _SFR_MEM8(0XAA)
+#define PTYPE1  7
+#define PTYPE0  6
+#define PTOKEN1 5
+#define PTOKEN0 4
+#define PEPNUM3 3
+#define PEPNUM2 2
+#define PEPNUM1 1
+#define PEPNUM0 0
+
+#define UPCFG1X _SFR_MEM8(0XAB)
+#define PSIZE2  6
+#define PSIZE1  5
+#define PSIZE0  4
+#define PBK1    3
+#define PBK0    2
+#define ALLOC   1
+
+#define UPSTAX  _SFR_MEM8(0XAC)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UPCFG2X _SFR_MEM8(0XAD)
+
+#define UPIENX  _SFR_MEM8(0XAE)
+#define FLERRE  7
+#define NAKEDE  6
+#define PERRE   4
+#define TXSTPE  3
+#define TXOUTE  2
+#define RXSTALLE 1
+#define RXINE   0
+
+#define UPDATX  _SFR_MEM8(0XAF)
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define EXCLK   6
+#define AS2     5
+#define TCN2UB  4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+/* Reserved [0xBE..0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define UHWCON  _SFR_MEM8(0XD7)
+#define UIMOD   7
+#define UIDE    6
+#define UVCONE  4
+#define UVREGE  0
+
+#define USBCON  _SFR_MEM8(0XD8)
+#define USBE    7
+#define HOST    6
+#define FRZCLK  5
+#define OTGPADE 4
+#define IDTE    1
+#define VBUSTE  0
+
+#define USBSTA  _SFR_MEM8(0XD9)
+#define SPEED   3
+#define ID      1
+#define VBUS    0
+
+#define USBINT  _SFR_MEM8(0XDA)
+#define IDTI    1
+#define VBUSTI  0
+
+/* Combine UDPADDL and UDPADDH */
+#define UDPADD  _SFR_MEM16(0xDB)
+
+#define UDPADDL _SFR_MEM8(0xDB)
+#define UDPADDH _SFR_MEM8(0xDC)
+#define DPACC   7
+
+#define OTGCON  _SFR_MEM8(0XDD)
+#define HNPREQ  5
+#define SRPREQ  4
+#define SRPSEL  3
+#define VBUSHWC 2
+#define VBUSREQ 1
+#define VBUSRQC 0
+
+#define OTGIEN  _SFR_MEM8(0XDE)
+#define STOE    5
+#define HNPERRE 4
+#define ROLEEXE 3
+#define BCERRE  2
+#define VBERRE  1
+#define SRPE    0
+
+#define OTGINT  _SFR_MEM8(0XDF)
+#define STOI    5
+#define HNPERRI 4
+#define ROLEEXI 3
+#define BCERRI  2
+#define VBERRI  1
+#define SRPI    0
+
+#define UDCON   _SFR_MEM8(0XE0)
+#define LSM     2
+#define RMWKUP  1
+#define DETACH  0
+
+#define UDINT   _SFR_MEM8(0XE1)
+#define UPRSMI  6
+#define EORSMI  5
+#define WAKEUPI 4
+#define EORSTI  3
+#define SOFI    2
+/* #define MSOFI   1 */ /* Reserved */
+#define SUSPI   0
+
+#define UDIEN   _SFR_MEM8(0XE2)
+#define UPRSME  6
+#define EORSME  5
+#define WAKEUPE 4
+#define EORSTE  3
+#define SOFE    2
+/* #define MSOFE   1 */ /* Reserved */
+#define SUSPE   0
+
+#define UDADDR  _SFR_MEM8(0XE3)
+#define ADDEN   7
+
+/* Combine UDFNUML and UDFNUMH */
+#define UDFNUM  _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define UDFNUMH _SFR_MEM8(0xE5)
+
+#define UDMFN   _SFR_MEM8(0XE6)
+#define FNCERR  4
+
+#define UDTST   _SFR_MEM8(0XE7)
+#define OPMODE2 5
+#define TSTPCKT 4
+#define TSTK    3
+#define TSTJ    2
+
+#define UEINTX  _SFR_MEM8(0XE8)
+#define FIFOCON 7
+#define NAKINI  6
+#define RWAL    5
+#define NAKOUTI 4
+#define RXSTPI  3
+#define RXOUTI  2
+#define STALLEDI 1
+#define TXINI   0
+
+#define UENUM   _SFR_MEM8(0XE9)
+
+#define UERST   _SFR_MEM8(0XEA)
+#define EPRST6  6
+#define EPRST5  5
+#define EPRST4  4
+#define EPRST3  3
+#define EPRST2  2
+#define EPRST1  1
+#define EPRST0  0
+
+#define UECONX  _SFR_MEM8(0XEB)
+#define STALLRQ 5
+#define STALLRQC 4
+#define RSTDT   3
+#define EPEN    0
+
+#define UECFG0X _SFR_MEM8(0XEC)
+#define EPTYPE1 7
+#define EPTYPE0 6
+/* #define ISOSW   3 */ /* Reserved */
+/* #define AUTOSW  2 */ /* Reserved */
+/* #define NYETSDIS 1 */ /* Reserved */
+#define EPDIR   0
+
+#define UECFG1X  _SFR_MEM8(0XED)
+#define EPSIZE2 6
+#define EPSIZE1 5
+#define EPSIZE0 4
+#define EPBK1   3
+#define EPBK0   2
+#define ALLOC   1
+
+#define UESTA0X _SFR_MEM8(0XEE)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define ZLPSEEN 4
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UESTA1X _SFR_MEM8(0XEF)
+#define CTRLDIR 2
+#define CURRBK1 1
+#define CURRBK0 0
+
+#define UEIENX  _SFR_MEM8(0XF0)
+#define FLERRE  7
+#define NAKINE  6
+#define NAKOUTE 4
+#define RXSTPE  3
+#define RXOUTE  2
+#define STALLEDE 1
+#define TXINE   0
+
+#define UEDATX  _SFR_MEM8(0XF1)
+
+/* Combine UEBCLX and UEBCHX */
+#define UEBCX   _SFR_MEM16(0xF2)
+
+#define UEBCLX  _SFR_MEM8(0xF2)
+#define UEBCHX  _SFR_MEM8(0xF3)
+
+#define UEINT   _SFR_MEM8(0XF4)
+#define EPINT6  6
+#define EPINT5  5
+#define EPINT4  4
+#define EPINT3  3
+#define EPINT2  2
+#define EPINT1  1
+#define EPINT0  0
+
+#define UPERRX  _SFR_MEM8(0XF5)
+#define COUNTER1 6
+#define COUNTER0 5
+#define CRC16    4
+#define TIMEOUT  3
+#define PID      2
+#define DATAPID  1
+#define DATATGL  0
+
+/* Combine UPBCLX and UPBCHX */
+#define UPBCX   _SFR_MEM16(0xF6)
+
+#define UPBCLX  _SFR_MEM8(0xF6)
+#define UPBCHX  _SFR_MEM8(0xF7)
+
+#define UPINT   _SFR_MEM8(0XF8)
+#define PINT6   6
+#define PINT5   5
+#define PINT4   4
+#define PINT3   3
+#define PINT2   2
+#define PINT1   1
+#define PINT0   0
+
+#define OTGTCON _SFR_MEM8(0XF9)
+#define PAGE1   6
+#define PAGE0   5
+#define VALUE1  1
+#define VALUE0  0
+
+/* Reserved [0xFA..0xFF] */
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num			1
+#define INT0_vect	    		_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num			2
+#define INT1_vect	    		_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num			3
+#define INT2_vect	    		_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num			4
+#define INT3_vect	    		_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num			5
+#define INT4_vect	    		_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num			6
+#define INT5_vect	    		_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num			7
+#define INT6_vect	    		_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num			8
+#define INT7_vect	    		_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num			9
+#define PCINT0_vect		    	_VECTOR(9)
+
+/* USB General Interrupt Request */
+#define USB_GEN_vect_num		10
+#define USB_GEN_vect			_VECTOR(10)
+
+/* USB Endpoint/Pipe Interrupt Communication Request */
+#define USB_COM_vect_num		11
+#define USB_COM_vect			_VECTOR(11)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num			12
+#define WDT_vect	    		_VECTOR(12)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	13
+#define TIMER2_COMPA_vect		_VECTOR(13)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	14
+#define TIMER2_COMPB_vect		_VECTOR(14)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		15
+#define TIMER2_OVF_vect			_VECTOR(15)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	16
+#define TIMER1_CAPT_vect		_VECTOR(16)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	17
+#define TIMER1_COMPA_vect		_VECTOR(17)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	18
+#define TIMER1_COMPB_vect		_VECTOR(18)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	19
+#define TIMER1_COMPC_vect		_VECTOR(19)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		20
+#define TIMER1_OVF_vect			_VECTOR(20)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	21
+#define TIMER0_COMPA_vect		_VECTOR(21)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	22
+#define TIMER0_COMPB_vect		_VECTOR(22)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		23
+#define TIMER0_OVF_vect			_VECTOR(23)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		24
+#define SPI_STC_vect			_VECTOR(24)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		25
+#define USART1_RX_vect			_VECTOR(25)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num    26
+#define USART1_UDRE_vect		_VECTOR(26)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		27
+#define USART1_TX_vect			_VECTOR(27)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	28
+#define ANALOG_COMP_vect		_VECTOR(28)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			29
+#define ADC_vect	    		_VECTOR(29)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		30
+#define EE_READY_vect			_VECTOR(30)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	31
+#define TIMER3_CAPT_vect		_VECTOR(31)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	32
+#define TIMER3_COMPA_vect		_VECTOR(32)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	33
+#define TIMER3_COMPB_vect		_VECTOR(33)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	34
+#define TIMER3_COMPC_vect		_VECTOR(34)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		35
+#define TIMER3_OVF_vect			_VECTOR(35)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num			36
+#define TWI_vect			    _VECTOR(36)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		37
+#define SPM_READY_vect			_VECTOR(37)
+
+#define _VECTORS_SIZE 152
 
 /* Constants */
 #define SPM_PAGESIZE 256
@@ -92,7 +1357,6 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x82
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_ADC (0x01<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
@@ -100,5 +1364,4 @@
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_AT90USB647_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iousb82.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iousb82.h
@@ -29,14 +29,783 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iousb82.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
 
 /* avr/iousb82.h - definitions for AT90USB82 */
 
 #ifndef _AVR_AT90USB82_H_
 #define _AVR_AT90USB82_H_ 1
 
-#include <avr/iousbxx2.h>
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iousbxx2.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+/* Reserved [0x00..0x02] */
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7     7
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+/* Reserved [0xC..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+/* Reserved [0x17..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLLP2   4
+#define PLLP1   3
+#define PLLP0   2
+#define PLLE    1
+#define PLOCK   0
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define DWDR    _SFR_IO8(0x31)
+#define IDRD    7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define USBRF   5
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define WDTCKD  _SFR_MEM8(0x62)
+#define WDEWIF  3
+#define WDEWIE  2
+#define WCLKD1  1
+#define WCLKD0  0
+
+#define REGCR   _SFR_MEM8(0x63)
+#define REGDIS  0
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTIM0  5
+#define PRTIM1  3
+#define PRSPI   2
+
+#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0))
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSB   7
+#define PRUSART1 0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRUSB))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRUSB
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+/* Reserved [0x70..0x7F] */
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+#define UCSR1D  _SFR_MEM8(0xCB)
+#define CTSEN   1
+#define RTSEN   0
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF] */
+
+#define CKSEL0  _SFR_MEM8(0XD0)	/* old name; up to AVR Studio v 4.13 */
+#define CLKSEL0 _SFR_MEM8(0XD0)	/* since AVR Studio v 4.14 */
+#define RCSUT1  7
+#define RCSUT0  6
+#define EXSUT1  5
+#define EXSUT0  4
+#define RCE     3
+#define EXTE    2
+#define CLKS    0
+
+#define CKSEL1  _SFR_MEM8(0XD1)	/* old name */
+#define CLKSEL1 _SFR_MEM8(0XD1)
+#define RCCKSEL3 7
+#define RCCKSEL2 6
+#define RCCKSEL1 5
+#define RCCKSEL0 4
+#define EXCKSEL3 3
+#define EXCKSEL2 2
+#define EXCKSEL1 1
+#define EXCKSEL0 0
+
+#define CKSTA   _SFR_MEM8(0XD2)	/* old name */
+#define CLKSTA  _SFR_MEM8(0XD2)
+#define RCON    1
+#define EXTON   0
+
+/* Reserved [0xD3..0xD7] */
+
+#define USBCON  _SFR_MEM8(0XD8)
+#define USBE    7
+#define FRZCLK  5
+
+/* Reserved [0xD9..0xDA] */
+
+/* Combine UDPADDL and UDPADDH */
+#define UDPADD  _SFR_MEM16(0xDB)
+
+#define UDPADDL _SFR_MEM8(0xDB)
+#define UDPADDH _SFR_MEM8(0xDC)
+#define DPACC   7
+
+/* Reserved [0xDD..0xDF] */
+
+#define UDCON   _SFR_MEM8(0XE0)
+#define RSTCPU  2
+#define RMWKUP  1
+#define DETACH  0
+
+#define UDINT   _SFR_MEM8(0XE1)
+#define UPRSMI  6
+#define EORSMI  5
+#define WAKEUPI 4
+#define EORSTI  3
+#define SOFI    2
+#define SUSPI   0
+
+#define UDIEN   _SFR_MEM8(0XE2)
+#define UPRSME  6
+#define EORSME  5
+#define WAKEUPE 4
+#define EORSTE  3
+#define SOFE    2
+#define SUSPE   0
+
+#define UDADDR  _SFR_MEM8(0XE3)
+#define ADDEN   7
+
+/* Combine UDFNUML and UDFNUMH */
+#define UDFNUM  _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define UDFNUMH _SFR_MEM8(0xE5)
+
+#define UDMFN   _SFR_MEM8(0XE6)
+#define FNCERR  4
+
+/* Reserved [0xE7] */
+
+#define UEINTX  _SFR_MEM8(0XE8)
+#define FIFOCON 7
+#define NAKINI  6
+#define RWAL    5
+#define NAKOUTI 4
+#define RXSTPI  3
+#define RXOUTI  2
+#define STALLEDI 1
+#define TXINI   0
+
+#define UENUM   _SFR_MEM8(0XE9)
+#define EPNUM2  2
+#define EPNUM1  1
+#define EPNUM0  0
+
+#define UERST   _SFR_MEM8(0XEA)
+#define EPRST4  4
+#define EPRST3  3
+#define EPRST2  2
+#define EPRST1  1
+#define EPRST0  0
+
+#define UECONX  _SFR_MEM8(0XEB)
+#define STALLRQ 5
+#define STALLRQC 4
+#define RSTDT   3
+#define EPEN    0
+
+#define UECFG0X _SFR_MEM8(0XEC)
+#define EPTYPE1 7
+#define EPTYPE0 6
+#define EPDIR   0
+
+#define UECFG1X  _SFR_MEM8(0XED)
+#define EPSIZE2 6
+#define EPSIZE1 5
+#define EPSIZE0 4
+#define EPBK1   3
+#define EPBK0   2
+#define ALLOC   1
+
+#define UESTA0X _SFR_MEM8(0XEE)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UESTA1X _SFR_MEM8(0XEF)
+#define CTRLDIR 2
+#define CURRBK1 1
+#define CURRBK0 0
+
+#define UEIENX  _SFR_MEM8(0XF0)
+#define FLERRE  7
+#define NAKINE  6
+#define NAKOUTE 4
+#define RXSTPE  3
+#define RXOUTE  2
+#define STALLEDE 1
+#define TXINE   0
+
+#define UEDATX  _SFR_MEM8(0XF1)
+
+#define UEBCLX  _SFR_MEM8(0xF2)
+
+/* Reserved [0xF3] */
+
+#define UEINT   _SFR_MEM8(0XF4)
+#define EPINT4  4
+#define EPINT3  3
+#define EPINT2  2
+#define EPINT1  1
+#define EPINT0  0
+
+/* Reserved [0xF5..0xF9] */
+
+#define PS2CON  _SFR_MEM8(0XFA)
+#define PS2EN   0
+
+#define UPOE    _SFR_MEM8(0XFB)
+#define UPWE1   7
+#define UPWE0   6
+#define UPDRV1  5
+#define UPDRV0  4
+#define SCKI    3
+#define DATAI   2
+#define DPI     1
+#define DMI     0
+
+/* Reserved [0xFC..0xFF] */
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num   	7
+#define INT6_vect			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		9
+#define PCINT0_vect			_VECTOR(9)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		10
+#define PCINT1_vect			_VECTOR(10)
+
+/* USB General Interrupt Request */
+#define USB_GEN_vect_num    	11
+#define USB_GEN_vect			_VECTOR(11)
+
+/* USB Endpoint/Pipe Interrupt Communication Request */
+#define USB_COM_vect_num		12
+#define USB_COM_vect			_VECTOR(12)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		13
+#define WDT_vect			_VECTOR(13)
+
+/* Timer/Counter2 Capture Event */
+#define TIMER1_CAPT_vect_num	14
+#define TIMER1_CAPT_vect		_VECTOR(14)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPA_vect_num	15
+#define TIMER1_COMPA_vect		_VECTOR(15)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPB_vect_num	16
+#define TIMER1_COMPB_vect		_VECTOR(16)
+
+/* Timer/Counter2 Compare Match C */
+#define TIMER1_COMPC_vect_num	17
+#define TIMER1_COMPC_vect		_VECTOR(17)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		18
+#define TIMER1_OVF_vect			_VECTOR(18)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	19
+#define TIMER0_COMPA_vect		_VECTOR(19)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	20
+#define TIMER0_COMPB_vect		_VECTOR(20)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		21
+#define TIMER0_OVF_vect			_VECTOR(21)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		22
+#define SPI_STC_vect			_VECTOR(22)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		23
+#define USART1_RX_vect			_VECTOR(23)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num	24
+#define USART1_UDRE_vect		_VECTOR(24)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		25
+#define USART1_TX_vect			_VECTOR(25)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	26
+#define ANALOG_COMP_vect		_VECTOR(26)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		27
+#define EE_READY_vect			_VECTOR(27)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num   	28
+#define SPM_READY_vect			_VECTOR(28)
+
+#define _VECTORS_SIZE 116
+
 
 /* Constants */
 #define SPM_PAGESIZE 128
@@ -86,12 +855,10 @@
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
 
-
 #define SLEEP_MODE_IDLE (0x00<<1)
 #define SLEEP_MODE_PWR_DOWN (0x02<<1)
 #define SLEEP_MODE_PWR_SAVE (0x03<<1)
 #define SLEEP_MODE_STANDBY (0x06<<1)
 #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
 
-
 #endif /* _AVR_AT90USB82_H_ */
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iox128a1.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iox128a1.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iox128a1.h 2200 2010-12-14 04:24:24Z arcanum $ */
 
 /* avr/iox128a1.h - definitions for ATxmega128A1 */
 
@@ -42,7 +42,7 @@
 #  define _AVR_IOXXX_H_ "iox128a1.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega128A1_H_
@@ -971,8 +971,8 @@
 typedef enum NVM_CMD_enum
 {
     NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
     NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
+    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
     NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
     NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
     NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
@@ -985,17 +985,25 @@
     NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
     NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
     NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
+    NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0),  /* Erase Flash Page */
     NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
     NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
+    NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0),  /* Write Flash Page */
+    NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0),  /* Erase-and-write Flash Page */
     NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
     NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
     NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
     NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
     NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
     NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
+    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Application section CRC */
+    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /*  Boot Section CRC */
+    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Flash Range CRC */
+    NVM_CMD_CHIP_ERASE_gc = (0x40<<0),  /* Erase Chip */
+    NVM_CMD_READ_NVM_gc = (0x43<<0),  /* Read NVM */
+    NVM_CMD_WRITE_FUSE_gc = (0x4C<<0),  /* Write Fuse byte */
+    NVM_CMD_ERASE_BOOT_gc = (0x68<<0),  /* Erase Boot Section */
+    NVM_CMD_FLASH_CRC_gc = (0x78<<0),  /* Flash CRC */
 } NVM_CMD_t;
 
 /* SPM ready interrupt level */
@@ -1284,16 +1292,34 @@
 /* Negative input multiplexer selection */
 typedef enum ADC_CH_MUXNEG_enum
 {
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
+    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN4_gc = (0x00<<0),  /* Input pin 4 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN5_gc = (0x01<<0),  /* Input pin 5 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN6_gc = (0x02<<0),  /* Input pin 6 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN7_gc = (0x03<<0),  /* Input pin 7 (Input Mode = 3) */
 } ADC_CH_MUXNEG_t;
 
+/* Negative input multiplexer selection when gain on 4 MSB pins */
+typedef enum ADC_CH_MUXNEGH_enum
+{
+    ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0),  /* Input pin 4 */
+    ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0),  /* Input pin 5 */
+    ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0),  /* Input pin 6 */
+    ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0),  /* Input pin 7 */
+} ADC_CH_MUXNEGH_t;
+
+/* Negative input multiplexer selection when gain on 4 LSB pins */
+typedef enum ADC_CH_MUXNEGL_enum
+{
+    ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0),  /* Input pin 0 */
+    ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0),  /* Input pin 1 */
+    ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0),  /* Input pin 2 */
+    ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0),  /* Input pin 3 */
+} ADC_CH_MUXNEGL_t;
+
 /* Input mode */
 typedef enum ADC_CH_INPUTMODE_enum
 {
@@ -4668,7 +4694,7 @@
 
 /* NVM - Non Volatile Memory Controller */
 /* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
+#define NVM_CMD_gm  0x7F  /* Command group mask. */
 #define NVM_CMD_gp  0  /* Command group position. */
 #define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
 #define NVM_CMD0_bp  0  /* Command bit 0 position. */
@@ -4684,8 +4710,6 @@
 #define NVM_CMD5_bp  5  /* Command bit 5 position. */
 #define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
 #define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
 
 
 /* NVM.CTRLA  bit masks and bit positions */
@@ -5368,6 +5392,35 @@
 
 
 /* EBI - External Bus Interface */
+
+/* EBI_CS.BASEADDR  bit masks and bit positions */
+#define EBI_CS_BASEADDR_gm  0xFFF0  /* Chip Select Base Address group mask. */
+#define EBI_CS_BASEADDR_gp  4  /* Chip Select Base Address group position. */
+#define EBI_CS_BASEADDR0_bm  (1<<4)  /* Chip Select Base Address bit 0 mask. */
+#define EBI_CS_BASEADDR0_bp  4  /* Chip Select Base Address bit 0 position. */
+#define EBI_CS_BASEADDR1_bm  (1<<5)  /* Chip Select Base Address bit 1 mask. */
+#define EBI_CS_BASEADDR1_bp  5  /* Chip Select Base Address bit 1 position. */
+#define EBI_CS_BASEADDR2_bm  (1<<6)  /* Chip Select Base Address bit 2 mask. */
+#define EBI_CS_BASEADDR2_bp  6  /* Chip Select Base Address bit 2 position. */
+#define EBI_CS_BASEADDR3_bm  (1<<7)  /* Chip Select Base Address bit 3 mask. */
+#define EBI_CS_BASEADDR3_bp  7  /* Chip Select Base Address bit 3 position. */
+#define EBI_CS_BASEADDR4_bm  (1<<8)  /* Chip Select Base Address bit 4 mask. */
+#define EBI_CS_BASEADDR4_bp  8  /* Chip Select Base Address bit 4 position. */
+#define EBI_CS_BASEADDR5_bm  (1<<9)  /* Chip Select Base Address bit 5 mask. */
+#define EBI_CS_BASEADDR5_bp  9  /* Chip Select Base Address bit 5 position. */
+#define EBI_CS_BASEADDR6_bm  (1<<10)  /* Chip Select Base Address bit 6 mask. */
+#define EBI_CS_BASEADDR6_bp  10  /* Chip Select Base Address bit 6 position. */
+#define EBI_CS_BASEADDR7_bm  (1<<11)  /* Chip Select Base Address bit 7 mask. */
+#define EBI_CS_BASEADDR7_bp  11  /* Chip Select Base Address bit 7 position. */
+#define EBI_CS_BASEADDR8_bm  (1<<12)  /* Chip Select Base Address bit 8 mask. */
+#define EBI_CS_BASEADDR8_bp  12  /* Chip Select Base Address bit 8 position. */
+#define EBI_CS_BASEADDR9_bm  (1<<13)  /* Chip Select Base Address bit 9 mask. */
+#define EBI_CS_BASEADDR9_bp  13  /* Chip Select Base Address bit 9 position. */
+#define EBI_CS_BASEADDR10_bm  (1<<14)  /* Chip Select Base Address bit 10 mask. */
+#define EBI_CS_BASEADDR10_bp  14  /* Chip Select Base Address bit 10 position. */
+#define EBI_CS_BASEADDR11_bm  (1<<15)  /* Chip Select Base Address bit 11 mask. */
+#define EBI_CS_BASEADDR11_bp  15  /* Chip Select Base Address bit 11 position. */
+
 /* EBI_CS.CTRLA  bit masks and bit positions */
 #define EBI_CS_ASIZE_gm  0x7C  /* Address Size group mask. */
 #define EBI_CS_ASIZE_gp  2  /* Address Size group position. */
@@ -6659,21 +6712,21 @@
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iox128a1u.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iox128a1u.h
@@ -1,7880 +1,8503 @@
-/* Copyright (c) 2010 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* $Id$ */
-
-/* avr/iox128a1u.h - definitions for ATxmega128A1U */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox128a1u.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATxmega128A1U_H_
-#define _AVR_ATxmega128A1U_H_ 1
-
-
-/* Ungrouped common registers */
-#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-    __extension__ union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-VPORT - Virtual Ports
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-    register8_t USBCTRL;  /* USB Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2 MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32 MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32.768 kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1.024 kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1.024 kHz from internal 32.768 kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC32_gc = (0x06<<1),  /* 32.768 kHz from internal 32.768 kHz RC oscillator */
-    CLK_RTCSRC_EXTCLK_gc = (0x07<<1),  /* External Clock from TOSC1 */
-} CLK_RTCSRC_t;
-
-/* USB Prescaler Division Factor */
-typedef enum CLK_USBPSDIV_enum
-{
-    CLK_USBPSDIV_1_gc = (0x00<<3),  /* Divide by 1 */
-    CLK_USBPSDIV_2_gc = (0x01<<3),  /* Divide by 2 */
-    CLK_USBPSDIV_4_gc = (0x02<<3),  /* Divide by 4 */
-    CLK_USBPSDIV_8_gc = (0x03<<3),  /* Divide by 8 */
-    CLK_USBPSDIV_16_gc = (0x04<<3),  /* Divide by 16 */
-    CLK_USBPSDIV_32_gc = (0x05<<3),  /* Divide by 32 */
-} CLK_USBPSDIV_t;
-
-/* USB Clock Source */
-typedef enum CLK_USBSRC_enum
-{
-    CLK_USBSRC_PLL_gc = (0x00<<1),  /* PLL */
-} CLK_USBSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32.768 kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32.768 kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16 MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16 MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16 MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2 MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32 MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-/* 32 MHz Calibration Reference */
-typedef enum OSC_RC32MCREF_enum
-{
-    OSC_RC32MCREF_RC32K_gc = (0x00<<1),  /* Internal 32.768 kHz RC Oscillator */
-    OSC_RC32MCREF_XOSC32_gc = (0x01<<1),  /* External 32.768 kHz Crystal Oscillator */
-} OSC_RC32MCREF_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
-    WDT_PER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
-    WDT_PER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
-    WDT_WPER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
-    WDT_WPER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t ANAINIT;  /* Analog Startup Delay */
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-PORTCFG - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/* Virtual Port Mapping */
-typedef enum PORTCFG_VP02MAP_enum
-{
-    PORTCFG_VP02MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP02MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP02MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP02MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP02MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP02MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP02MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP02MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP02MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP02MAP_t;
-
-/* Virtual Port Mapping */
-typedef enum PORTCFG_VP13MAP_enum
-{
-    PORTCFG_VP13MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP13MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP13MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP13MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP13MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP13MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP13MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP13MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP13MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP13MAP_t;
-
-/* System Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* System Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* System Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* System Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* System Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Peripheral Clock Output Select */
-typedef enum PORTCFG_CLKOUTSEL_enum
-{
-    PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2),  /* 1x Peripheral Clock Output to pin */
-    PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2),  /* 2x Peripheral Clock Output to pin */
-    PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2),  /* 4x Peripheral Clock Output to pin */
-} PORTCFG_CLKOUTSEL_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-CRC - Cyclic Redundancy Checker
---------------------------------------------------------------------------
-*/
-
-/* Cyclic Redundancy Checker */
-typedef struct CRC_struct
-{
-    register8_t CTRL;  /* CRC Control Register */
-    register8_t STATUS;  /* CRC Status Register */
-    register8_t reserved_0x02;
-    register8_t DATAIN;  /* CRC Data Input */
-    register8_t CHECKSUM0;  /* CRC Checksum byte 0 */
-    register8_t CHECKSUM1;  /* CRC Checksum byte 1 */
-    register8_t CHECKSUM2;  /* CRC Checksum byte 2 */
-    register8_t CHECKSUM3;  /* CRC Checksum byte 3 */
-} CRC_t;
-
-/* CRC Reset */
-typedef enum CRC_RESET_enum
-{
-    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
-    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
-    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
-} CRC_RESET_t;
-
-/* CRC Input Source */
-typedef enum CRC_SOURCE_enum
-{
-    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* CRC Disabled */
-    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
-    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
-    CRC_SOURCE_DMAC0_gc = (0x04<<0),  /* DMAC Channel 0 */
-    CRC_SOURCE_DMAC1_gc = (0x05<<0),  /* DMAC Channel 1 */
-    CRC_SOURCE_DMAC2_gc = (0x06<<0),  /* DMAC Channel 2 */
-    CRC_SOURCE_DMAC3_gc = (0x07<<0),  /* DMAC Channel 3 */
-} CRC_SOURCE_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_USB_gc = (0x0A<<0),  /* USB Setup, SOF, CRC error and UNF/OVF */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0),  /* Erase Flash Page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0),  /* Write Flash Page */
-    NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0),  /* Erase-and-write Flash Page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_CHIP_ERASE_gc = (0x40<<0),  /* Erase Chip */
-    NVM_CMD_READ_NVM_gc = (0x43<<0),  /* Read NVM */
-    NVM_CMD_WRITE_FUSE_gc = (0x4C<<0),  /* Write Fuse byte */
-    NVM_CMD_ERASE_BOOT_gc = (0x68<<0),  /* Erase Boot Section */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t reserved_0x05;
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-    ADC_CH_MUXPOS_PIN8_gc = (0x08<<3),  /* Input pin 8 */
-    ADC_CH_MUXPOS_PIN9_gc = (0x09<<3),  /* Input pin 9 */
-    ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3),  /* Input pin 10 */
-    ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3),  /* Input pin 11 */
-    ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3),  /* Input pin 12 */
-    ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3),  /* Input pin 13 */
-    ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3),  /* Input pin 14 */
-    ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3),  /* Input pin 15 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x00<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x01<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x02<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x03<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-    ADC_CH_GAIN_128X_gc = (0x07<<2),  /* 128x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Current Limitation Mode */
-typedef enum ADC_CURRENT_enum
-{
-    ADC_CURRENT_NO_gc = (0x00<<5),  /* No Current Reduction */
-    ADC_CURRENT_SMALL_gc = (0x01<<5),  /* 10% current reduction */
-    ADC_CURRENT_MEDIUM_gc = (0x02<<5),  /* 20% current reduction */
-    ADC_CURRENT_LARGE_gc = (0x03<<5),  /* 30% current reduction */
-} ADC_CURRENT_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC / 1.6 */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-    ADC_REFSEL_VCCDIV2_gc = (0x04<<4),  /* Internal VCC / 2 */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t TIMCTRL;  /* Timing Control */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t CH0GAINCAL;  /* Gain Calibration */
-    register8_t CH0OFFSETCAL;  /* Offset Calibration */
-    register8_t CH1GAINCAL;  /* Gain Calibration */
-    register8_t CH1OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel 0 only) */
-    DAC_CHSEL_SINGLE1_gc = (0x01<<5),  /* Single channel operation (Channel 1 only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (Channel 0 and channel 1) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-/* Conversion interval */
-typedef enum DAC_CONINTVAL_enum
-{
-    DAC_CONINTVAL_1CLK_gc = (0x00<<4),  /* 1 CLK / 2 CLK in S/H mode */
-    DAC_CONINTVAL_2CLK_gc = (0x01<<4),  /* 2 CLK / 3 CLK in S/H mode */
-    DAC_CONINTVAL_4CLK_gc = (0x02<<4),  /* 4 CLK / 6 CLK in S/H mode */
-    DAC_CONINTVAL_8CLK_gc = (0x03<<4),  /* 8 CLK / 12 CLK in S/H mode */
-    DAC_CONINTVAL_16CLK_gc = (0x04<<4),  /* 16 CLK / 24 CLK in S/H mode */
-    DAC_CONINTVAL_32CLK_gc = (0x05<<4),  /* 32 CLK / 48 CLK in S/H mode */
-    DAC_CONINTVAL_64CLK_gc = (0x06<<4),  /* 64 CLK / 96 CLK in S/H mode */
-    DAC_CONINTVAL_128CLK_gc = (0x07<<4),  /* 128 CLK / 192 CLK in S/H mode */
-} DAC_CONINTVAL_t;
-
-/* Refresh rate */
-typedef enum DAC_REFRESH_enum
-{
-    DAC_REFRESH_16CLK_gc = (0x00<<0),  /* 16 CLK */
-    DAC_REFRESH_32CLK_gc = (0x01<<0),  /* 32 CLK */
-    DAC_REFRESH_64CLK_gc = (0x02<<0),  /* 64 CLK */
-    DAC_REFRESH_128CLK_gc = (0x03<<0),  /* 128 CLK */
-    DAC_REFRESH_256CLK_gc = (0x04<<0),  /* 256 CLK */
-    DAC_REFRESH_512CLK_gc = (0x05<<0),  /* 512 CLK */
-    DAC_REFRESH_1024CLK_gc = (0x06<<0),  /* 1024 CLK */
-    DAC_REFRESH_2048CLK_gc = (0x07<<0),  /* 2048 CLK */
-    DAC_REFRESH_4086CLK_gc = (0x08<<0),  /* 4096 CLK */
-    DAC_REFRESH_8192CLK_gc = (0x09<<0),  /* 8192 CLK */
-    DAC_REFRESH_16384CLK_gc = (0x0A<<0),  /* 16384 CLK */
-    DAC_REFRESH_32768CLK_gc = (0x0B<<0),  /* 32768 CLK */
-    DAC_REFRESH_65536CLK_gc = (0x0C<<0),  /* 65536 CLK */
-    DAC_REFRESH_OFF_gc = (0x0F<<0),  /* Auto refresh OFF */
-} DAC_REFRESH_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Analog Comparator 0 Control */
-    register8_t AC1CTRL;  /* Analog Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Analog Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Analog Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASIZE_enum
-{
-    EBI_CS_ASIZE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASIZE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASIZE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASIZE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASIZE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASIZE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASIZE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASIZE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASIZE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASIZE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASIZE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASIZE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASIZE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASIZE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASIZE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASIZE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASIZE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASIZE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-USB - USB Module
---------------------------------------------------------------------------
-*/
-
-/* USB Endpoint */
-typedef struct USB_EP_struct
-{
-    register8_t STATUS;  /* Endpoint Status */
-    register8_t CTRL;  /* Endpoint Control */
-    register8_t CNTL;  /* USB Endpoint Counter Low Byte */
-    register8_t CNTH;  /* USB Endpoint Counter High Byte */
-    register8_t DATAPTRL;  /* Data Pointer Low Byte */
-    register8_t DATAPTRH;  /* Data Pointer High Byte */
-    register8_t AUXDATAL;  /* Auxiliary Data Low Byte */
-    register8_t AUXDATAH;  /* Auxiliary Data High Byte */
-} USB_EP_t;
-
-/*
---------------------------------------------------------------------------
-USB - USB Module
---------------------------------------------------------------------------
-*/
-
-/* USB Endpoint table */
-typedef struct USB_EP_TABLE_struct
-{
-    USB_EP_t EP0OUT;  /* USB Endpoint 0 Output */
-    USB_EP_t EP0IN;  /* USB Endpoint 0 Input */
-    USB_EP_t EP1OUT;  /* USB Endpoint 1 Output */
-    USB_EP_t EP1IN;  /* USB Endpoint 1 Input */
-    USB_EP_t EP2OUT;  /* USB Endpoint 2 Output */
-    USB_EP_t EP2IN;  /* USB Endpoint 2 Input */
-    USB_EP_t EP3OUT;  /* USB Endpoint 3 Output */
-    USB_EP_t EP3IN;  /* USB Endpoint 3 Input */
-    USB_EP_t EP4OUT;  /* USB Endpoint 4 Output */
-    USB_EP_t EP4IN;  /* USB Endpoint 4 Input */
-    USB_EP_t EP5OUT;  /* USB Endpoint 5 Output */
-    USB_EP_t EP5IN;  /* USB Endpoint 5 Input */
-    USB_EP_t EP6OUT;  /* USB Endpoint 6 Output */
-    USB_EP_t EP6IN;  /* USB Endpoint 6 Input */
-    USB_EP_t EP7OUT;  /* USB Endpoint 7 Output */
-    USB_EP_t EP7IN;  /* USB Endpoint 7 Input */
-    USB_EP_t EP8OUT;  /* USB Endpoint 8 Output */
-    USB_EP_t EP8IN;  /* USB Endpoint 8 Input */
-    USB_EP_t EP9OUT;  /* USB Endpoint 9 Output */
-    USB_EP_t EP9IN;  /* USB Endpoint 9 Input */
-    USB_EP_t EP10OUT;  /* USB Endpoint 10 Output */
-    USB_EP_t EP10IN;  /* USB Endpoint 10 Input */
-    USB_EP_t EP11OUT;  /* USB Endpoint 11 Output */
-    USB_EP_t EP11IN;  /* USB Endpoint 11 Input */
-    USB_EP_t EP12OUT;  /* USB Endpoint 12 Output */
-    USB_EP_t EP12IN;  /* USB Endpoint 12 Input */
-    USB_EP_t EP13OUT;  /* USB Endpoint 13 Output */
-    USB_EP_t EP13IN;  /* USB Endpoint 13 Input */
-    USB_EP_t EP14OUT;  /* USB Endpoint 14 Output */
-    USB_EP_t EP14IN;  /* USB Endpoint 14 Input */
-    USB_EP_t EP15OUT;  /* USB Endpoint 15 Output */
-    USB_EP_t EP15IN;  /* USB Endpoint 15 Input */
-    register8_t FRAMENUML;  /* Frame Number Low Byte */
-    register8_t FRAMENUMH;  /* Frame Number High Byte */
-} USB_EP_TABLE_t;
-
-/*
---------------------------------------------------------------------------
-USB - USB Module
---------------------------------------------------------------------------
-*/
-
-/* USB Module */
-typedef struct USB_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t FIFOWP;  /* FIFO Write Pointer Register */
-    register8_t FIFORP;  /* FIFO Read Pointer Register */
-    _WORDREGISTER(EPPTR);  /* Endpoint Configuration Table Pointer */
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t INTFLAGSACLR;  /* Clear Interrupt Flag Register A */
-    register8_t INTFLAGSASET;  /* Set Interrupt Flag Register A */
-    register8_t INTFLAGSBCLR;  /* Clear Interrupt Flag Register B */
-    register8_t INTFLAGSBSET;  /* Set Interrupt Flag Register B */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t reserved_0x20;
-    register8_t reserved_0x21;
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t CAL0;  /* Calibration Byte 0 */
-    register8_t CAL1;  /* Calibration Byte 1 */
-} USB_t;
-
-/* USB Endpoint Type */
-typedef enum USB_EP_TYPE_enum
-{
-    USB_EP_TYPE_DISABLE_gc = (0x00<<6),  /* Endpoint Disabled */
-    USB_EP_TYPE_CONTROL_gc = (0x01<<6),  /* Control */
-    USB_EP_TYPE_BULK_gc = (0x02<<6),  /* Bulk/Interrupt */
-    USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6),  /* Isochronous */
-} USB_EP_TYPE_t;
-
-/* USB Endpoint Buffer Size */
-typedef enum USB_EP_SIZE_enum
-{
-    USB_EP_SIZE_8_gc = (0x00<<0),  /* 8 bytes buffer size */
-    USB_EP_SIZE_16_gc = (0x01<<0),  /* 16 bytes buffer size */
-    USB_EP_SIZE_32_gc = (0x02<<0),  /* 32 bytes buffer size */
-    USB_EP_SIZE_64_gc = (0x03<<0),  /* 64 bytes buffer size */
-    USB_EP_SIZE_128_gc = (0x04<<0),  /* 128 bytes buffer size */
-    USB_EP_SIZE_256_gc = (0x05<<0),  /* 256 bytes buffer size */
-    USB_EP_SIZE_512_gc = (0x06<<0),  /* 512 bytes buffer size */
-    USB_EP_SIZE_1023_gc = (0x07<<0),  /* 1023 bytes buffer size */
-} USB_EP_SIZE_t;
-
-/* Interrupt level */
-typedef enum USB_INTLVL_enum
-{
-    USB_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    USB_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USB_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USB_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USB_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - I/O Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t REMAP;  /* I/O Port Pin Remap Register */
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-AWEX - Timer/Counter Advanced Waveform Extension
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-
-/*
---------------------------------------------------------------------------
-HIRES - Timer/Counter High-Resolution Extension
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRLA;  /* Control Register */
-} HIRES_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-PRESC - Prescaler
---------------------------------------------------------------------------
-*/
-
-/* Prescaler */
-typedef struct PRESC_struct
-{
-    register8_t PRESCALER;  /* Control Register */
-} PRESC_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define USB_EP_TABLE    (*(USB_EP_TABLE_t *) )  /* Universal Serial Bus Module */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Crypto Module */
-#define CRC    (*(CRC_t *) 0x00D0)  /* CRC Module */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ADCB    (*(ADC_t *) 0x0240)  /* Analog to Digital Converter B */
-#define DACA    (*(DAC_t *) 0x0300)  /* Digital to Analog Converter A */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define ACB    (*(AC_t *) 0x0390)  /* Analog Comparator B */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define EBI    (*(EBI_t *) 0x0440)  /* External Bus Interface */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define TWID    (*(TWI_t *) 0x0490)  /* Two-Wire Interface D */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
-#define TWIF    (*(TWI_t *) 0x04B0)  /* Two-Wire Interface F */
-#define USB    (*(USB_t *) 0x04C0)  /* Universal Serial Bus Module */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTH    (*(PORT_t *) 0x06E0)  /* Port H */
-#define PORTJ    (*(PORT_t *) 0x0700)  /* Port J */
-#define PORTK    (*(PORT_t *) 0x0720)  /* Port K */
-#define PORTQ    (*(PORT_t *) 0x07C0)  /* Port Q */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define TCE1    (*(TC1_t *) 0x0A40)  /* Timer/Counter E1 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE1    (*(USART_t *) 0x0AB0)  /* Universal Asynchronous Receiver-Transmitter E1 */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-#define TCF1    (*(TC1_t *) 0x0B40)  /* Timer/Counter F1 */
-#define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension F */
-#define USARTF0    (*(USART_t *) 0x0BA0)  /* Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF1    (*(USART_t *) 0x0BB0)  /* Universal Asynchronous Receiver-Transmitter F1 */
-#define SPIF    (*(SPI_t *) 0x0BC0)  /* Serial Peripheral Interface F */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* USB_EP_TABLE - Universal Serial Bus Module */
-#define USB_EP_TABLE_EP0OUT_STATUS  _SFR_MEM8(0x0000)
-#define USB_EP_TABLE_EP0OUT_CTRL  _SFR_MEM8(0x0001)
-#define USB_EP_TABLE_EP0OUT_CNTL  _SFR_MEM8(0x0002)
-#define USB_EP_TABLE_EP0OUT_CNTH  _SFR_MEM8(0x0003)
-#define USB_EP_TABLE_EP0OUT_DATAPTRL  _SFR_MEM8(0x0004)
-#define USB_EP_TABLE_EP0OUT_DATAPTRH  _SFR_MEM8(0x0005)
-#define USB_EP_TABLE_EP0OUT_AUXDATAL  _SFR_MEM8(0x0006)
-#define USB_EP_TABLE_EP0OUT_AUXDATAH  _SFR_MEM8(0x0007)
-#define USB_EP_TABLE_EP0IN_STATUS  _SFR_MEM8(0x0008)
-#define USB_EP_TABLE_EP0IN_CTRL  _SFR_MEM8(0x0009)
-#define USB_EP_TABLE_EP0IN_CNTL  _SFR_MEM8(0x000A)
-#define USB_EP_TABLE_EP0IN_CNTH  _SFR_MEM8(0x000B)
-#define USB_EP_TABLE_EP0IN_DATAPTRL  _SFR_MEM8(0x000C)
-#define USB_EP_TABLE_EP0IN_DATAPTRH  _SFR_MEM8(0x000D)
-#define USB_EP_TABLE_EP0IN_AUXDATAL  _SFR_MEM8(0x000E)
-#define USB_EP_TABLE_EP0IN_AUXDATAH  _SFR_MEM8(0x000F)
-#define USB_EP_TABLE_EP1OUT_STATUS  _SFR_MEM8(0x0010)
-#define USB_EP_TABLE_EP1OUT_CTRL  _SFR_MEM8(0x0011)
-#define USB_EP_TABLE_EP1OUT_CNTL  _SFR_MEM8(0x0012)
-#define USB_EP_TABLE_EP1OUT_CNTH  _SFR_MEM8(0x0013)
-#define USB_EP_TABLE_EP1OUT_DATAPTRL  _SFR_MEM8(0x0014)
-#define USB_EP_TABLE_EP1OUT_DATAPTRH  _SFR_MEM8(0x0015)
-#define USB_EP_TABLE_EP1OUT_AUXDATAL  _SFR_MEM8(0x0016)
-#define USB_EP_TABLE_EP1OUT_AUXDATAH  _SFR_MEM8(0x0017)
-#define USB_EP_TABLE_EP1IN_STATUS  _SFR_MEM8(0x0018)
-#define USB_EP_TABLE_EP1IN_CTRL  _SFR_MEM8(0x0019)
-#define USB_EP_TABLE_EP1IN_CNTL  _SFR_MEM8(0x001A)
-#define USB_EP_TABLE_EP1IN_CNTH  _SFR_MEM8(0x001B)
-#define USB_EP_TABLE_EP1IN_DATAPTRL  _SFR_MEM8(0x001C)
-#define USB_EP_TABLE_EP1IN_DATAPTRH  _SFR_MEM8(0x001D)
-#define USB_EP_TABLE_EP1IN_AUXDATAL  _SFR_MEM8(0x001E)
-#define USB_EP_TABLE_EP1IN_AUXDATAH  _SFR_MEM8(0x001F)
-#define USB_EP_TABLE_EP2OUT_STATUS  _SFR_MEM8(0x0020)
-#define USB_EP_TABLE_EP2OUT_CTRL  _SFR_MEM8(0x0021)
-#define USB_EP_TABLE_EP2OUT_CNTL  _SFR_MEM8(0x0022)
-#define USB_EP_TABLE_EP2OUT_CNTH  _SFR_MEM8(0x0023)
-#define USB_EP_TABLE_EP2OUT_DATAPTRL  _SFR_MEM8(0x0024)
-#define USB_EP_TABLE_EP2OUT_DATAPTRH  _SFR_MEM8(0x0025)
-#define USB_EP_TABLE_EP2OUT_AUXDATAL  _SFR_MEM8(0x0026)
-#define USB_EP_TABLE_EP2OUT_AUXDATAH  _SFR_MEM8(0x0027)
-#define USB_EP_TABLE_EP2IN_STATUS  _SFR_MEM8(0x0028)
-#define USB_EP_TABLE_EP2IN_CTRL  _SFR_MEM8(0x0029)
-#define USB_EP_TABLE_EP2IN_CNTL  _SFR_MEM8(0x002A)
-#define USB_EP_TABLE_EP2IN_CNTH  _SFR_MEM8(0x002B)
-#define USB_EP_TABLE_EP2IN_DATAPTRL  _SFR_MEM8(0x002C)
-#define USB_EP_TABLE_EP2IN_DATAPTRH  _SFR_MEM8(0x002D)
-#define USB_EP_TABLE_EP2IN_AUXDATAL  _SFR_MEM8(0x002E)
-#define USB_EP_TABLE_EP2IN_AUXDATAH  _SFR_MEM8(0x002F)
-#define USB_EP_TABLE_EP3OUT_STATUS  _SFR_MEM8(0x0030)
-#define USB_EP_TABLE_EP3OUT_CTRL  _SFR_MEM8(0x0031)
-#define USB_EP_TABLE_EP3OUT_CNTL  _SFR_MEM8(0x0032)
-#define USB_EP_TABLE_EP3OUT_CNTH  _SFR_MEM8(0x0033)
-#define USB_EP_TABLE_EP3OUT_DATAPTRL  _SFR_MEM8(0x0034)
-#define USB_EP_TABLE_EP3OUT_DATAPTRH  _SFR_MEM8(0x0035)
-#define USB_EP_TABLE_EP3OUT_AUXDATAL  _SFR_MEM8(0x0036)
-#define USB_EP_TABLE_EP3OUT_AUXDATAH  _SFR_MEM8(0x0037)
-#define USB_EP_TABLE_EP3IN_STATUS  _SFR_MEM8(0x0038)
-#define USB_EP_TABLE_EP3IN_CTRL  _SFR_MEM8(0x0039)
-#define USB_EP_TABLE_EP3IN_CNTL  _SFR_MEM8(0x003A)
-#define USB_EP_TABLE_EP3IN_CNTH  _SFR_MEM8(0x003B)
-#define USB_EP_TABLE_EP3IN_DATAPTRL  _SFR_MEM8(0x003C)
-#define USB_EP_TABLE_EP3IN_DATAPTRH  _SFR_MEM8(0x003D)
-#define USB_EP_TABLE_EP3IN_AUXDATAL  _SFR_MEM8(0x003E)
-#define USB_EP_TABLE_EP3IN_AUXDATAH  _SFR_MEM8(0x003F)
-#define USB_EP_TABLE_EP4OUT_STATUS  _SFR_MEM8(0x0040)
-#define USB_EP_TABLE_EP4OUT_CTRL  _SFR_MEM8(0x0041)
-#define USB_EP_TABLE_EP4OUT_CNTL  _SFR_MEM8(0x0042)
-#define USB_EP_TABLE_EP4OUT_CNTH  _SFR_MEM8(0x0043)
-#define USB_EP_TABLE_EP4OUT_DATAPTRL  _SFR_MEM8(0x0044)
-#define USB_EP_TABLE_EP4OUT_DATAPTRH  _SFR_MEM8(0x0045)
-#define USB_EP_TABLE_EP4OUT_AUXDATAL  _SFR_MEM8(0x0046)
-#define USB_EP_TABLE_EP4OUT_AUXDATAH  _SFR_MEM8(0x0047)
-#define USB_EP_TABLE_EP4IN_STATUS  _SFR_MEM8(0x0048)
-#define USB_EP_TABLE_EP4IN_CTRL  _SFR_MEM8(0x0049)
-#define USB_EP_TABLE_EP4IN_CNTL  _SFR_MEM8(0x004A)
-#define USB_EP_TABLE_EP4IN_CNTH  _SFR_MEM8(0x004B)
-#define USB_EP_TABLE_EP4IN_DATAPTRL  _SFR_MEM8(0x004C)
-#define USB_EP_TABLE_EP4IN_DATAPTRH  _SFR_MEM8(0x004D)
-#define USB_EP_TABLE_EP4IN_AUXDATAL  _SFR_MEM8(0x004E)
-#define USB_EP_TABLE_EP4IN_AUXDATAH  _SFR_MEM8(0x004F)
-#define USB_EP_TABLE_EP5OUT_STATUS  _SFR_MEM8(0x0050)
-#define USB_EP_TABLE_EP5OUT_CTRL  _SFR_MEM8(0x0051)
-#define USB_EP_TABLE_EP5OUT_CNTL  _SFR_MEM8(0x0052)
-#define USB_EP_TABLE_EP5OUT_CNTH  _SFR_MEM8(0x0053)
-#define USB_EP_TABLE_EP5OUT_DATAPTRL  _SFR_MEM8(0x0054)
-#define USB_EP_TABLE_EP5OUT_DATAPTRH  _SFR_MEM8(0x0055)
-#define USB_EP_TABLE_EP5OUT_AUXDATAL  _SFR_MEM8(0x0056)
-#define USB_EP_TABLE_EP5OUT_AUXDATAH  _SFR_MEM8(0x0057)
-#define USB_EP_TABLE_EP5IN_STATUS  _SFR_MEM8(0x0058)
-#define USB_EP_TABLE_EP5IN_CTRL  _SFR_MEM8(0x0059)
-#define USB_EP_TABLE_EP5IN_CNTL  _SFR_MEM8(0x005A)
-#define USB_EP_TABLE_EP5IN_CNTH  _SFR_MEM8(0x005B)
-#define USB_EP_TABLE_EP5IN_DATAPTRL  _SFR_MEM8(0x005C)
-#define USB_EP_TABLE_EP5IN_DATAPTRH  _SFR_MEM8(0x005D)
-#define USB_EP_TABLE_EP5IN_AUXDATAL  _SFR_MEM8(0x005E)
-#define USB_EP_TABLE_EP5IN_AUXDATAH  _SFR_MEM8(0x005F)
-#define USB_EP_TABLE_EP6OUT_STATUS  _SFR_MEM8(0x0060)
-#define USB_EP_TABLE_EP6OUT_CTRL  _SFR_MEM8(0x0061)
-#define USB_EP_TABLE_EP6OUT_CNTL  _SFR_MEM8(0x0062)
-#define USB_EP_TABLE_EP6OUT_CNTH  _SFR_MEM8(0x0063)
-#define USB_EP_TABLE_EP6OUT_DATAPTRL  _SFR_MEM8(0x0064)
-#define USB_EP_TABLE_EP6OUT_DATAPTRH  _SFR_MEM8(0x0065)
-#define USB_EP_TABLE_EP6OUT_AUXDATAL  _SFR_MEM8(0x0066)
-#define USB_EP_TABLE_EP6OUT_AUXDATAH  _SFR_MEM8(0x0067)
-#define USB_EP_TABLE_EP6IN_STATUS  _SFR_MEM8(0x0068)
-#define USB_EP_TABLE_EP6IN_CTRL  _SFR_MEM8(0x0069)
-#define USB_EP_TABLE_EP6IN_CNTL  _SFR_MEM8(0x006A)
-#define USB_EP_TABLE_EP6IN_CNTH  _SFR_MEM8(0x006B)
-#define USB_EP_TABLE_EP6IN_DATAPTRL  _SFR_MEM8(0x006C)
-#define USB_EP_TABLE_EP6IN_DATAPTRH  _SFR_MEM8(0x006D)
-#define USB_EP_TABLE_EP6IN_AUXDATAL  _SFR_MEM8(0x006E)
-#define USB_EP_TABLE_EP6IN_AUXDATAH  _SFR_MEM8(0x006F)
-#define USB_EP_TABLE_EP7OUT_STATUS  _SFR_MEM8(0x0070)
-#define USB_EP_TABLE_EP7OUT_CTRL  _SFR_MEM8(0x0071)
-#define USB_EP_TABLE_EP7OUT_CNTL  _SFR_MEM8(0x0072)
-#define USB_EP_TABLE_EP7OUT_CNTH  _SFR_MEM8(0x0073)
-#define USB_EP_TABLE_EP7OUT_DATAPTRL  _SFR_MEM8(0x0074)
-#define USB_EP_TABLE_EP7OUT_DATAPTRH  _SFR_MEM8(0x0075)
-#define USB_EP_TABLE_EP7OUT_AUXDATAL  _SFR_MEM8(0x0076)
-#define USB_EP_TABLE_EP7OUT_AUXDATAH  _SFR_MEM8(0x0077)
-#define USB_EP_TABLE_EP7IN_STATUS  _SFR_MEM8(0x0078)
-#define USB_EP_TABLE_EP7IN_CTRL  _SFR_MEM8(0x0079)
-#define USB_EP_TABLE_EP7IN_CNTL  _SFR_MEM8(0x007A)
-#define USB_EP_TABLE_EP7IN_CNTH  _SFR_MEM8(0x007B)
-#define USB_EP_TABLE_EP7IN_DATAPTRL  _SFR_MEM8(0x007C)
-#define USB_EP_TABLE_EP7IN_DATAPTRH  _SFR_MEM8(0x007D)
-#define USB_EP_TABLE_EP7IN_AUXDATAL  _SFR_MEM8(0x007E)
-#define USB_EP_TABLE_EP7IN_AUXDATAH  _SFR_MEM8(0x007F)
-#define USB_EP_TABLE_EP8OUT_STATUS  _SFR_MEM8(0x0080)
-#define USB_EP_TABLE_EP8OUT_CTRL  _SFR_MEM8(0x0081)
-#define USB_EP_TABLE_EP8OUT_CNTL  _SFR_MEM8(0x0082)
-#define USB_EP_TABLE_EP8OUT_CNTH  _SFR_MEM8(0x0083)
-#define USB_EP_TABLE_EP8OUT_DATAPTRL  _SFR_MEM8(0x0084)
-#define USB_EP_TABLE_EP8OUT_DATAPTRH  _SFR_MEM8(0x0085)
-#define USB_EP_TABLE_EP8OUT_AUXDATAL  _SFR_MEM8(0x0086)
-#define USB_EP_TABLE_EP8OUT_AUXDATAH  _SFR_MEM8(0x0087)
-#define USB_EP_TABLE_EP8IN_STATUS  _SFR_MEM8(0x0088)
-#define USB_EP_TABLE_EP8IN_CTRL  _SFR_MEM8(0x0089)
-#define USB_EP_TABLE_EP8IN_CNTL  _SFR_MEM8(0x008A)
-#define USB_EP_TABLE_EP8IN_CNTH  _SFR_MEM8(0x008B)
-#define USB_EP_TABLE_EP8IN_DATAPTRL  _SFR_MEM8(0x008C)
-#define USB_EP_TABLE_EP8IN_DATAPTRH  _SFR_MEM8(0x008D)
-#define USB_EP_TABLE_EP8IN_AUXDATAL  _SFR_MEM8(0x008E)
-#define USB_EP_TABLE_EP8IN_AUXDATAH  _SFR_MEM8(0x008F)
-#define USB_EP_TABLE_EP9OUT_STATUS  _SFR_MEM8(0x0090)
-#define USB_EP_TABLE_EP9OUT_CTRL  _SFR_MEM8(0x0091)
-#define USB_EP_TABLE_EP9OUT_CNTL  _SFR_MEM8(0x0092)
-#define USB_EP_TABLE_EP9OUT_CNTH  _SFR_MEM8(0x0093)
-#define USB_EP_TABLE_EP9OUT_DATAPTRL  _SFR_MEM8(0x0094)
-#define USB_EP_TABLE_EP9OUT_DATAPTRH  _SFR_MEM8(0x0095)
-#define USB_EP_TABLE_EP9OUT_AUXDATAL  _SFR_MEM8(0x0096)
-#define USB_EP_TABLE_EP9OUT_AUXDATAH  _SFR_MEM8(0x0097)
-#define USB_EP_TABLE_EP9IN_STATUS  _SFR_MEM8(0x0098)
-#define USB_EP_TABLE_EP9IN_CTRL  _SFR_MEM8(0x0099)
-#define USB_EP_TABLE_EP9IN_CNTL  _SFR_MEM8(0x009A)
-#define USB_EP_TABLE_EP9IN_CNTH  _SFR_MEM8(0x009B)
-#define USB_EP_TABLE_EP9IN_DATAPTRL  _SFR_MEM8(0x009C)
-#define USB_EP_TABLE_EP9IN_DATAPTRH  _SFR_MEM8(0x009D)
-#define USB_EP_TABLE_EP9IN_AUXDATAL  _SFR_MEM8(0x009E)
-#define USB_EP_TABLE_EP9IN_AUXDATAH  _SFR_MEM8(0x009F)
-#define USB_EP_TABLE_EP10OUT_STATUS  _SFR_MEM8(0x00A0)
-#define USB_EP_TABLE_EP10OUT_CTRL  _SFR_MEM8(0x00A1)
-#define USB_EP_TABLE_EP10OUT_CNTL  _SFR_MEM8(0x00A2)
-#define USB_EP_TABLE_EP10OUT_CNTH  _SFR_MEM8(0x00A3)
-#define USB_EP_TABLE_EP10OUT_DATAPTRL  _SFR_MEM8(0x00A4)
-#define USB_EP_TABLE_EP10OUT_DATAPTRH  _SFR_MEM8(0x00A5)
-#define USB_EP_TABLE_EP10OUT_AUXDATAL  _SFR_MEM8(0x00A6)
-#define USB_EP_TABLE_EP10OUT_AUXDATAH  _SFR_MEM8(0x00A7)
-#define USB_EP_TABLE_EP10IN_STATUS  _SFR_MEM8(0x00A8)
-#define USB_EP_TABLE_EP10IN_CTRL  _SFR_MEM8(0x00A9)
-#define USB_EP_TABLE_EP10IN_CNTL  _SFR_MEM8(0x00AA)
-#define USB_EP_TABLE_EP10IN_CNTH  _SFR_MEM8(0x00AB)
-#define USB_EP_TABLE_EP10IN_DATAPTRL  _SFR_MEM8(0x00AC)
-#define USB_EP_TABLE_EP10IN_DATAPTRH  _SFR_MEM8(0x00AD)
-#define USB_EP_TABLE_EP10IN_AUXDATAL  _SFR_MEM8(0x00AE)
-#define USB_EP_TABLE_EP10IN_AUXDATAH  _SFR_MEM8(0x00AF)
-#define USB_EP_TABLE_EP11OUT_STATUS  _SFR_MEM8(0x00B0)
-#define USB_EP_TABLE_EP11OUT_CTRL  _SFR_MEM8(0x00B1)
-#define USB_EP_TABLE_EP11OUT_CNTL  _SFR_MEM8(0x00B2)
-#define USB_EP_TABLE_EP11OUT_CNTH  _SFR_MEM8(0x00B3)
-#define USB_EP_TABLE_EP11OUT_DATAPTRL  _SFR_MEM8(0x00B4)
-#define USB_EP_TABLE_EP11OUT_DATAPTRH  _SFR_MEM8(0x00B5)
-#define USB_EP_TABLE_EP11OUT_AUXDATAL  _SFR_MEM8(0x00B6)
-#define USB_EP_TABLE_EP11OUT_AUXDATAH  _SFR_MEM8(0x00B7)
-#define USB_EP_TABLE_EP11IN_STATUS  _SFR_MEM8(0x00B8)
-#define USB_EP_TABLE_EP11IN_CTRL  _SFR_MEM8(0x00B9)
-#define USB_EP_TABLE_EP11IN_CNTL  _SFR_MEM8(0x00BA)
-#define USB_EP_TABLE_EP11IN_CNTH  _SFR_MEM8(0x00BB)
-#define USB_EP_TABLE_EP11IN_DATAPTRL  _SFR_MEM8(0x00BC)
-#define USB_EP_TABLE_EP11IN_DATAPTRH  _SFR_MEM8(0x00BD)
-#define USB_EP_TABLE_EP11IN_AUXDATAL  _SFR_MEM8(0x00BE)
-#define USB_EP_TABLE_EP11IN_AUXDATAH  _SFR_MEM8(0x00BF)
-#define USB_EP_TABLE_EP12OUT_STATUS  _SFR_MEM8(0x00C0)
-#define USB_EP_TABLE_EP12OUT_CTRL  _SFR_MEM8(0x00C1)
-#define USB_EP_TABLE_EP12OUT_CNTL  _SFR_MEM8(0x00C2)
-#define USB_EP_TABLE_EP12OUT_CNTH  _SFR_MEM8(0x00C3)
-#define USB_EP_TABLE_EP12OUT_DATAPTRL  _SFR_MEM8(0x00C4)
-#define USB_EP_TABLE_EP12OUT_DATAPTRH  _SFR_MEM8(0x00C5)
-#define USB_EP_TABLE_EP12OUT_AUXDATAL  _SFR_MEM8(0x00C6)
-#define USB_EP_TABLE_EP12OUT_AUXDATAH  _SFR_MEM8(0x00C7)
-#define USB_EP_TABLE_EP12IN_STATUS  _SFR_MEM8(0x00C8)
-#define USB_EP_TABLE_EP12IN_CTRL  _SFR_MEM8(0x00C9)
-#define USB_EP_TABLE_EP12IN_CNTL  _SFR_MEM8(0x00CA)
-#define USB_EP_TABLE_EP12IN_CNTH  _SFR_MEM8(0x00CB)
-#define USB_EP_TABLE_EP12IN_DATAPTRL  _SFR_MEM8(0x00CC)
-#define USB_EP_TABLE_EP12IN_DATAPTRH  _SFR_MEM8(0x00CD)
-#define USB_EP_TABLE_EP12IN_AUXDATAL  _SFR_MEM8(0x00CE)
-#define USB_EP_TABLE_EP12IN_AUXDATAH  _SFR_MEM8(0x00CF)
-#define USB_EP_TABLE_EP13OUT_STATUS  _SFR_MEM8(0x00D0)
-#define USB_EP_TABLE_EP13OUT_CTRL  _SFR_MEM8(0x00D1)
-#define USB_EP_TABLE_EP13OUT_CNTL  _SFR_MEM8(0x00D2)
-#define USB_EP_TABLE_EP13OUT_CNTH  _SFR_MEM8(0x00D3)
-#define USB_EP_TABLE_EP13OUT_DATAPTRL  _SFR_MEM8(0x00D4)
-#define USB_EP_TABLE_EP13OUT_DATAPTRH  _SFR_MEM8(0x00D5)
-#define USB_EP_TABLE_EP13OUT_AUXDATAL  _SFR_MEM8(0x00D6)
-#define USB_EP_TABLE_EP13OUT_AUXDATAH  _SFR_MEM8(0x00D7)
-#define USB_EP_TABLE_EP13IN_STATUS  _SFR_MEM8(0x00D8)
-#define USB_EP_TABLE_EP13IN_CTRL  _SFR_MEM8(0x00D9)
-#define USB_EP_TABLE_EP13IN_CNTL  _SFR_MEM8(0x00DA)
-#define USB_EP_TABLE_EP13IN_CNTH  _SFR_MEM8(0x00DB)
-#define USB_EP_TABLE_EP13IN_DATAPTRL  _SFR_MEM8(0x00DC)
-#define USB_EP_TABLE_EP13IN_DATAPTRH  _SFR_MEM8(0x00DD)
-#define USB_EP_TABLE_EP13IN_AUXDATAL  _SFR_MEM8(0x00DE)
-#define USB_EP_TABLE_EP13IN_AUXDATAH  _SFR_MEM8(0x00DF)
-#define USB_EP_TABLE_EP14OUT_STATUS  _SFR_MEM8(0x00E0)
-#define USB_EP_TABLE_EP14OUT_CTRL  _SFR_MEM8(0x00E1)
-#define USB_EP_TABLE_EP14OUT_CNTL  _SFR_MEM8(0x00E2)
-#define USB_EP_TABLE_EP14OUT_CNTH  _SFR_MEM8(0x00E3)
-#define USB_EP_TABLE_EP14OUT_DATAPTRL  _SFR_MEM8(0x00E4)
-#define USB_EP_TABLE_EP14OUT_DATAPTRH  _SFR_MEM8(0x00E5)
-#define USB_EP_TABLE_EP14OUT_AUXDATAL  _SFR_MEM8(0x00E6)
-#define USB_EP_TABLE_EP14OUT_AUXDATAH  _SFR_MEM8(0x00E7)
-#define USB_EP_TABLE_EP14IN_STATUS  _SFR_MEM8(0x00E8)
-#define USB_EP_TABLE_EP14IN_CTRL  _SFR_MEM8(0x00E9)
-#define USB_EP_TABLE_EP14IN_CNTL  _SFR_MEM8(0x00EA)
-#define USB_EP_TABLE_EP14IN_CNTH  _SFR_MEM8(0x00EB)
-#define USB_EP_TABLE_EP14IN_DATAPTRL  _SFR_MEM8(0x00EC)
-#define USB_EP_TABLE_EP14IN_DATAPTRH  _SFR_MEM8(0x00ED)
-#define USB_EP_TABLE_EP14IN_AUXDATAL  _SFR_MEM8(0x00EE)
-#define USB_EP_TABLE_EP14IN_AUXDATAH  _SFR_MEM8(0x00EF)
-#define USB_EP_TABLE_EP15OUT_STATUS  _SFR_MEM8(0x00F0)
-#define USB_EP_TABLE_EP15OUT_CTRL  _SFR_MEM8(0x00F1)
-#define USB_EP_TABLE_EP15OUT_CNTL  _SFR_MEM8(0x00F2)
-#define USB_EP_TABLE_EP15OUT_CNTH  _SFR_MEM8(0x00F3)
-#define USB_EP_TABLE_EP15OUT_DATAPTRL  _SFR_MEM8(0x00F4)
-#define USB_EP_TABLE_EP15OUT_DATAPTRH  _SFR_MEM8(0x00F5)
-#define USB_EP_TABLE_EP15OUT_AUXDATAL  _SFR_MEM8(0x00F6)
-#define USB_EP_TABLE_EP15OUT_AUXDATAH  _SFR_MEM8(0x00F7)
-#define USB_EP_TABLE_EP15IN_STATUS  _SFR_MEM8(0x00F8)
-#define USB_EP_TABLE_EP15IN_CTRL  _SFR_MEM8(0x00F9)
-#define USB_EP_TABLE_EP15IN_CNTL  _SFR_MEM8(0x00FA)
-#define USB_EP_TABLE_EP15IN_CNTH  _SFR_MEM8(0x00FB)
-#define USB_EP_TABLE_EP15IN_DATAPTRL  _SFR_MEM8(0x00FC)
-#define USB_EP_TABLE_EP15IN_DATAPTRH  _SFR_MEM8(0x00FD)
-#define USB_EP_TABLE_EP15IN_AUXDATAL  _SFR_MEM8(0x00FE)
-#define USB_EP_TABLE_EP15IN_AUXDATAH  _SFR_MEM8(0x00FF)
-#define USB_EP_TABLE_FRAMENUML  _SFR_MEM8(0x0110)
-#define USB_EP_TABLE_FRAMENUMH  _SFR_MEM8(0x0111)
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
-#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
-#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
-#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
-#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
-#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
-#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
-#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
-#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
-#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
-#define GPIO_GPIORA  _SFR_MEM8(0x000A)
-#define GPIO_GPIORB  _SFR_MEM8(0x000B)
-#define GPIO_GPIORC  _SFR_MEM8(0x000C)
-#define GPIO_GPIORD  _SFR_MEM8(0x000D)
-#define GPIO_GPIORE  _SFR_MEM8(0x000E)
-#define GPIO_GPIORF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-#define CLK_USBCTRL  _SFR_MEM8(0x0044)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x005F)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_ANAINIT  _SFR_MEM8(0x0097)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* AES - AES Crypto Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* CRC - CRC Module */
-#define CRC_CTRL  _SFR_MEM8(0x00D0)
-#define CRC_STATUS  _SFR_MEM8(0x00D1)
-#define CRC_DATAIN  _SFR_MEM8(0x00D3)
-#define CRC_CHECKSUM0  _SFR_MEM8(0x00D4)
-#define CRC_CHECKSUM1  _SFR_MEM8(0x00D5)
-#define CRC_CHECKSUM2  _SFR_MEM8(0x00D6)
-#define CRC_CHECKSUM3  _SFR_MEM8(0x00D7)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_TEMP  _SFR_MEM8(0x0207)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-
-/* ADCB - Analog to Digital Converter B */
-#define ADCB_CTRLA  _SFR_MEM8(0x0240)
-#define ADCB_CTRLB  _SFR_MEM8(0x0241)
-#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
-#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
-#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
-#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
-#define ADCB_TEMP  _SFR_MEM8(0x0247)
-#define ADCB_CAL  _SFR_MEM16(0x024C)
-#define ADCB_CH0RES  _SFR_MEM16(0x0250)
-#define ADCB_CH1RES  _SFR_MEM16(0x0252)
-#define ADCB_CH2RES  _SFR_MEM16(0x0254)
-#define ADCB_CH3RES  _SFR_MEM16(0x0256)
-#define ADCB_CMP  _SFR_MEM16(0x0258)
-#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
-#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
-#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
-#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
-#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
-#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
-#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
-#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
-#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
-#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
-#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
-#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
-#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
-#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
-#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
-#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
-#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
-#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
-#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
-#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
-
-/* DACA - Digital to Analog Converter A */
-#define DACA_CTRLA  _SFR_MEM8(0x0300)
-#define DACA_CTRLB  _SFR_MEM8(0x0301)
-#define DACA_CTRLC  _SFR_MEM8(0x0302)
-#define DACA_EVCTRL  _SFR_MEM8(0x0303)
-#define DACA_TIMCTRL  _SFR_MEM8(0x0304)
-#define DACA_STATUS  _SFR_MEM8(0x0305)
-#define DACA_CH0GAINCAL  _SFR_MEM8(0x0308)
-#define DACA_CH0OFFSETCAL  _SFR_MEM8(0x0309)
-#define DACA_CH1GAINCAL  _SFR_MEM8(0x030A)
-#define DACA_CH1OFFSETCAL  _SFR_MEM8(0x030B)
-#define DACA_CH0DATA  _SFR_MEM16(0x0318)
-#define DACA_CH1DATA  _SFR_MEM16(0x031A)
-
-/* DACB - Digital to Analog Converter B */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_TIMCTRL  _SFR_MEM8(0x0324)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_CH0GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_CH0OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH1GAINCAL  _SFR_MEM8(0x032A)
-#define DACB_CH1OFFSETCAL  _SFR_MEM8(0x032B)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* ACB - Analog Comparator B */
-#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
-#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
-#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
-#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
-#define ACB_CTRLA  _SFR_MEM8(0x0394)
-#define ACB_CTRLB  _SFR_MEM8(0x0395)
-#define ACB_WINCTRL  _SFR_MEM8(0x0396)
-#define ACB_STATUS  _SFR_MEM8(0x0397)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* EBI - External Bus Interface */
-#define EBI_CTRL  _SFR_MEM8(0x0440)
-#define EBI_SDRAMCTRLA  _SFR_MEM8(0x0441)
-#define EBI_REFRESH  _SFR_MEM16(0x0444)
-#define EBI_INITDLY  _SFR_MEM16(0x0446)
-#define EBI_SDRAMCTRLB  _SFR_MEM8(0x0448)
-#define EBI_SDRAMCTRLC  _SFR_MEM8(0x0449)
-#define EBI_CS0_CTRLA  _SFR_MEM8(0x0450)
-#define EBI_CS0_CTRLB  _SFR_MEM8(0x0451)
-#define EBI_CS0_BASEADDR  _SFR_MEM16(0x0452)
-#define EBI_CS1_CTRLA  _SFR_MEM8(0x0454)
-#define EBI_CS1_CTRLB  _SFR_MEM8(0x0455)
-#define EBI_CS1_BASEADDR  _SFR_MEM16(0x0456)
-#define EBI_CS2_CTRLA  _SFR_MEM8(0x0458)
-#define EBI_CS2_CTRLB  _SFR_MEM8(0x0459)
-#define EBI_CS2_BASEADDR  _SFR_MEM16(0x045A)
-#define EBI_CS3_CTRLA  _SFR_MEM8(0x045C)
-#define EBI_CS3_CTRLB  _SFR_MEM8(0x045D)
-#define EBI_CS3_BASEADDR  _SFR_MEM16(0x045E)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWID - Two-Wire Interface D */
-#define TWID_CTRL  _SFR_MEM8(0x0490)
-#define TWID_MASTER_CTRLA  _SFR_MEM8(0x0491)
-#define TWID_MASTER_CTRLB  _SFR_MEM8(0x0492)
-#define TWID_MASTER_CTRLC  _SFR_MEM8(0x0493)
-#define TWID_MASTER_STATUS  _SFR_MEM8(0x0494)
-#define TWID_MASTER_BAUD  _SFR_MEM8(0x0495)
-#define TWID_MASTER_ADDR  _SFR_MEM8(0x0496)
-#define TWID_MASTER_DATA  _SFR_MEM8(0x0497)
-#define TWID_SLAVE_CTRLA  _SFR_MEM8(0x0498)
-#define TWID_SLAVE_CTRLB  _SFR_MEM8(0x0499)
-#define TWID_SLAVE_STATUS  _SFR_MEM8(0x049A)
-#define TWID_SLAVE_ADDR  _SFR_MEM8(0x049B)
-#define TWID_SLAVE_DATA  _SFR_MEM8(0x049C)
-#define TWID_SLAVE_ADDRMASK  _SFR_MEM8(0x049D)
-
-/* TWIE - Two-Wire Interface E */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* TWIF - Two-Wire Interface F */
-#define TWIF_CTRL  _SFR_MEM8(0x04B0)
-#define TWIF_MASTER_CTRLA  _SFR_MEM8(0x04B1)
-#define TWIF_MASTER_CTRLB  _SFR_MEM8(0x04B2)
-#define TWIF_MASTER_CTRLC  _SFR_MEM8(0x04B3)
-#define TWIF_MASTER_STATUS  _SFR_MEM8(0x04B4)
-#define TWIF_MASTER_BAUD  _SFR_MEM8(0x04B5)
-#define TWIF_MASTER_ADDR  _SFR_MEM8(0x04B6)
-#define TWIF_MASTER_DATA  _SFR_MEM8(0x04B7)
-#define TWIF_SLAVE_CTRLA  _SFR_MEM8(0x04B8)
-#define TWIF_SLAVE_CTRLB  _SFR_MEM8(0x04B9)
-#define TWIF_SLAVE_STATUS  _SFR_MEM8(0x04BA)
-#define TWIF_SLAVE_ADDR  _SFR_MEM8(0x04BB)
-#define TWIF_SLAVE_DATA  _SFR_MEM8(0x04BC)
-#define TWIF_SLAVE_ADDRMASK  _SFR_MEM8(0x04BD)
-
-/* USB - Universal Serial Bus Module */
-#define USB_CTRLA  _SFR_MEM8(0x04C0)
-#define USB_CTRLB  _SFR_MEM8(0x04C1)
-#define USB_STATUS  _SFR_MEM8(0x04C2)
-#define USB_ADDR  _SFR_MEM8(0x04C3)
-#define USB_FIFOWP  _SFR_MEM8(0x04C4)
-#define USB_FIFORP  _SFR_MEM8(0x04C5)
-#define USB_EPPTR  _SFR_MEM16(0x04C6)
-#define USB_INTCTRLA  _SFR_MEM8(0x04C8)
-#define USB_INTCTRLB  _SFR_MEM8(0x04C9)
-#define USB_INTFLAGSACLR  _SFR_MEM8(0x04CA)
-#define USB_INTFLAGSASET  _SFR_MEM8(0x04CB)
-#define USB_INTFLAGSBCLR  _SFR_MEM8(0x04CC)
-#define USB_INTFLAGSBSET  _SFR_MEM8(0x04CD)
-#define USB_CAL0  _SFR_MEM8(0x04FA)
-#define USB_CAL1  _SFR_MEM8(0x04FB)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTH - Port H */
-#define PORTH_DIR  _SFR_MEM8(0x06E0)
-#define PORTH_DIRSET  _SFR_MEM8(0x06E1)
-#define PORTH_DIRCLR  _SFR_MEM8(0x06E2)
-#define PORTH_DIRTGL  _SFR_MEM8(0x06E3)
-#define PORTH_OUT  _SFR_MEM8(0x06E4)
-#define PORTH_OUTSET  _SFR_MEM8(0x06E5)
-#define PORTH_OUTCLR  _SFR_MEM8(0x06E6)
-#define PORTH_OUTTGL  _SFR_MEM8(0x06E7)
-#define PORTH_IN  _SFR_MEM8(0x06E8)
-#define PORTH_INTCTRL  _SFR_MEM8(0x06E9)
-#define PORTH_INT0MASK  _SFR_MEM8(0x06EA)
-#define PORTH_INT1MASK  _SFR_MEM8(0x06EB)
-#define PORTH_INTFLAGS  _SFR_MEM8(0x06EC)
-#define PORTH_PIN0CTRL  _SFR_MEM8(0x06F0)
-#define PORTH_PIN1CTRL  _SFR_MEM8(0x06F1)
-#define PORTH_PIN2CTRL  _SFR_MEM8(0x06F2)
-#define PORTH_PIN3CTRL  _SFR_MEM8(0x06F3)
-#define PORTH_PIN4CTRL  _SFR_MEM8(0x06F4)
-#define PORTH_PIN5CTRL  _SFR_MEM8(0x06F5)
-#define PORTH_PIN6CTRL  _SFR_MEM8(0x06F6)
-#define PORTH_PIN7CTRL  _SFR_MEM8(0x06F7)
-
-/* PORTJ - Port J */
-#define PORTJ_DIR  _SFR_MEM8(0x0700)
-#define PORTJ_DIRSET  _SFR_MEM8(0x0701)
-#define PORTJ_DIRCLR  _SFR_MEM8(0x0702)
-#define PORTJ_DIRTGL  _SFR_MEM8(0x0703)
-#define PORTJ_OUT  _SFR_MEM8(0x0704)
-#define PORTJ_OUTSET  _SFR_MEM8(0x0705)
-#define PORTJ_OUTCLR  _SFR_MEM8(0x0706)
-#define PORTJ_OUTTGL  _SFR_MEM8(0x0707)
-#define PORTJ_IN  _SFR_MEM8(0x0708)
-#define PORTJ_INTCTRL  _SFR_MEM8(0x0709)
-#define PORTJ_INT0MASK  _SFR_MEM8(0x070A)
-#define PORTJ_INT1MASK  _SFR_MEM8(0x070B)
-#define PORTJ_INTFLAGS  _SFR_MEM8(0x070C)
-#define PORTJ_PIN0CTRL  _SFR_MEM8(0x0710)
-#define PORTJ_PIN1CTRL  _SFR_MEM8(0x0711)
-#define PORTJ_PIN2CTRL  _SFR_MEM8(0x0712)
-#define PORTJ_PIN3CTRL  _SFR_MEM8(0x0713)
-#define PORTJ_PIN4CTRL  _SFR_MEM8(0x0714)
-#define PORTJ_PIN5CTRL  _SFR_MEM8(0x0715)
-#define PORTJ_PIN6CTRL  _SFR_MEM8(0x0716)
-#define PORTJ_PIN7CTRL  _SFR_MEM8(0x0717)
-
-/* PORTK - Port K */
-#define PORTK_DIR  _SFR_MEM8(0x0720)
-#define PORTK_DIRSET  _SFR_MEM8(0x0721)
-#define PORTK_DIRCLR  _SFR_MEM8(0x0722)
-#define PORTK_DIRTGL  _SFR_MEM8(0x0723)
-#define PORTK_OUT  _SFR_MEM8(0x0724)
-#define PORTK_OUTSET  _SFR_MEM8(0x0725)
-#define PORTK_OUTCLR  _SFR_MEM8(0x0726)
-#define PORTK_OUTTGL  _SFR_MEM8(0x0727)
-#define PORTK_IN  _SFR_MEM8(0x0728)
-#define PORTK_INTCTRL  _SFR_MEM8(0x0729)
-#define PORTK_INT0MASK  _SFR_MEM8(0x072A)
-#define PORTK_INT1MASK  _SFR_MEM8(0x072B)
-#define PORTK_INTFLAGS  _SFR_MEM8(0x072C)
-#define PORTK_PIN0CTRL  _SFR_MEM8(0x0730)
-#define PORTK_PIN1CTRL  _SFR_MEM8(0x0731)
-#define PORTK_PIN2CTRL  _SFR_MEM8(0x0732)
-#define PORTK_PIN3CTRL  _SFR_MEM8(0x0733)
-#define PORTK_PIN4CTRL  _SFR_MEM8(0x0734)
-#define PORTK_PIN5CTRL  _SFR_MEM8(0x0735)
-#define PORTK_PIN6CTRL  _SFR_MEM8(0x0736)
-#define PORTK_PIN7CTRL  _SFR_MEM8(0x0737)
-
-/* PORTQ - Port Q */
-#define PORTQ_DIR  _SFR_MEM8(0x07C0)
-#define PORTQ_DIRSET  _SFR_MEM8(0x07C1)
-#define PORTQ_DIRCLR  _SFR_MEM8(0x07C2)
-#define PORTQ_DIRTGL  _SFR_MEM8(0x07C3)
-#define PORTQ_OUT  _SFR_MEM8(0x07C4)
-#define PORTQ_OUTSET  _SFR_MEM8(0x07C5)
-#define PORTQ_OUTCLR  _SFR_MEM8(0x07C6)
-#define PORTQ_OUTTGL  _SFR_MEM8(0x07C7)
-#define PORTQ_IN  _SFR_MEM8(0x07C8)
-#define PORTQ_INTCTRL  _SFR_MEM8(0x07C9)
-#define PORTQ_INT0MASK  _SFR_MEM8(0x07CA)
-#define PORTQ_INT1MASK  _SFR_MEM8(0x07CB)
-#define PORTQ_INTFLAGS  _SFR_MEM8(0x07CC)
-#define PORTQ_PIN0CTRL  _SFR_MEM8(0x07D0)
-#define PORTQ_PIN1CTRL  _SFR_MEM8(0x07D1)
-#define PORTQ_PIN2CTRL  _SFR_MEM8(0x07D2)
-#define PORTQ_PIN3CTRL  _SFR_MEM8(0x07D3)
-#define PORTQ_PIN4CTRL  _SFR_MEM8(0x07D4)
-#define PORTQ_PIN5CTRL  _SFR_MEM8(0x07D5)
-#define PORTQ_PIN6CTRL  _SFR_MEM8(0x07D6)
-#define PORTQ_PIN7CTRL  _SFR_MEM8(0x07D7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TCD1 - Timer/Counter D1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRESD - High-Resolution Extension D */
-#define HIRESD_CTRLA  _SFR_MEM8(0x0990)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* TCE1 - Timer/Counter E1 */
-#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
-#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
-#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
-#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
-#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
-#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
-#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
-#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
-#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
-#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
-#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
-#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
-#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
-#define TCE1_CNT  _SFR_MEM16(0x0A60)
-#define TCE1_PER  _SFR_MEM16(0x0A66)
-#define TCE1_CCA  _SFR_MEM16(0x0A68)
-#define TCE1_CCB  _SFR_MEM16(0x0A6A)
-#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
-#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
-#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* HIRESE - High-Resolution Extension E */
-#define HIRESE_CTRLA  _SFR_MEM8(0x0A90)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
-#define USARTE1_DATA  _SFR_MEM8(0x0AB0)
-#define USARTE1_STATUS  _SFR_MEM8(0x0AB1)
-#define USARTE1_CTRLA  _SFR_MEM8(0x0AB3)
-#define USARTE1_CTRLB  _SFR_MEM8(0x0AB4)
-#define USARTE1_CTRLC  _SFR_MEM8(0x0AB5)
-#define USARTE1_BAUDCTRLA  _SFR_MEM8(0x0AB6)
-#define USARTE1_BAUDCTRLB  _SFR_MEM8(0x0AB7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-/* TCF1 - Timer/Counter F1 */
-#define TCF1_CTRLA  _SFR_MEM8(0x0B40)
-#define TCF1_CTRLB  _SFR_MEM8(0x0B41)
-#define TCF1_CTRLC  _SFR_MEM8(0x0B42)
-#define TCF1_CTRLD  _SFR_MEM8(0x0B43)
-#define TCF1_CTRLE  _SFR_MEM8(0x0B44)
-#define TCF1_INTCTRLA  _SFR_MEM8(0x0B46)
-#define TCF1_INTCTRLB  _SFR_MEM8(0x0B47)
-#define TCF1_CTRLFCLR  _SFR_MEM8(0x0B48)
-#define TCF1_CTRLFSET  _SFR_MEM8(0x0B49)
-#define TCF1_CTRLGCLR  _SFR_MEM8(0x0B4A)
-#define TCF1_CTRLGSET  _SFR_MEM8(0x0B4B)
-#define TCF1_INTFLAGS  _SFR_MEM8(0x0B4C)
-#define TCF1_TEMP  _SFR_MEM8(0x0B4F)
-#define TCF1_CNT  _SFR_MEM16(0x0B60)
-#define TCF1_PER  _SFR_MEM16(0x0B66)
-#define TCF1_CCA  _SFR_MEM16(0x0B68)
-#define TCF1_CCB  _SFR_MEM16(0x0B6A)
-#define TCF1_PERBUF  _SFR_MEM16(0x0B76)
-#define TCF1_CCABUF  _SFR_MEM16(0x0B78)
-#define TCF1_CCBBUF  _SFR_MEM16(0x0B7A)
-
-/* HIRESF - High-Resolution Extension F */
-#define HIRESF_CTRLA  _SFR_MEM8(0x0B90)
-
-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
-#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
-#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
-#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
-#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
-#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
-#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
-
-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
-#define USARTF1_DATA  _SFR_MEM8(0x0BB0)
-#define USARTF1_STATUS  _SFR_MEM8(0x0BB1)
-#define USARTF1_CTRLA  _SFR_MEM8(0x0BB3)
-#define USARTF1_CTRLB  _SFR_MEM8(0x0BB4)
-#define USARTF1_CTRLC  _SFR_MEM8(0x0BB5)
-#define USARTF1_BAUDCTRLA  _SFR_MEM8(0x0BB6)
-#define USARTF1_BAUDCTRLB  _SFR_MEM8(0x0BB7)
-
-/* SPIF - Serial Peripheral Interface F */
-#define SPIF_CTRL  _SFR_MEM8(0x0BC0)
-#define SPIF_INTCTRL  _SFR_MEM8(0x0BC1)
-#define SPIF_STATUS  _SFR_MEM8(0x0BC2)
-#define SPIF_DATA  _SFR_MEM8(0x0BC3)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* VPORT - Virtual Ports */
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* Clock Source Enable bit position. */
-
-
-/* CLK.USBCTRL  bit masks and bit positions */
-#define CLK_USBPSDIV_gm  0x38  /* Prescaler Division Factor group mask. */
-#define CLK_USBPSDIV_gp  3  /* Prescaler Division Factor group position. */
-#define CLK_USBPSDIV0_bm  (1<<3)  /* Prescaler Division Factor bit 0 mask. */
-#define CLK_USBPSDIV0_bp  3  /* Prescaler Division Factor bit 0 position. */
-#define CLK_USBPSDIV1_bm  (1<<4)  /* Prescaler Division Factor bit 1 mask. */
-#define CLK_USBPSDIV1_bp  4  /* Prescaler Division Factor bit 1 position. */
-#define CLK_USBPSDIV2_bm  (1<<5)  /* Prescaler Division Factor bit 2 mask. */
-#define CLK_USBPSDIV2_bp  5  /* Prescaler Division Factor bit 2 position. */
-
-#define CLK_USBSRC_gm  0x06  /* Clock Source group mask. */
-#define CLK_USBSRC_gp  1  /* Clock Source group position. */
-#define CLK_USBSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_USBSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_USBSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_USBSRC1_bp  2  /* Clock Source bit 1 position. */
-
-#define CLK_USBEN_bm  0x01  /* Clock Source Enable bit mask. */
-#define CLK_USBEN_bp  0  /* Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_USB_bm  0x40  /* USB bit mask. */
-#define PR_USB_bp  6  /* USB bit position. */
-
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32.768 kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32 MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32 MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2 MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2 MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32.768 kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32 MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32 MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2 MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2 MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_PLLFDIF_bm  0x08  /* PLL Failure Detection Interrupt Flag bit mask. */
-#define OSC_PLLFDIF_bp  3  /* PLL Failure Detection Interrupt Flag bit position. */
-
-#define OSC_PLLFDEN_bm  0x04  /* PLL Failure Detection Enable bit mask. */
-#define OSC_PLLFDEN_bp  2  /* PLL Failure Detection Enable bit position. */
-
-#define OSC_XOSCFDIF_bm  0x02  /* XOSC Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* XOSC Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* XOSC Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* XOSC Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_gm  0x06  /* 32 MHz Calibration Reference group mask. */
-#define OSC_RC32MCREF_gp  1  /* 32 MHz Calibration Reference group position. */
-#define OSC_RC32MCREF0_bm  (1<<1)  /* 32 MHz Calibration Reference bit 0 mask. */
-#define OSC_RC32MCREF0_bp  1  /* 32 MHz Calibration Reference bit 0 position. */
-#define OSC_RC32MCREF1_bm  (1<<2)  /* 32 MHz Calibration Reference bit 1 mask. */
-#define OSC_RC32MCREF1_bp  2  /* 32 MHz Calibration Reference bit 1 position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2 MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2 MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration Value A group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration Value A group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration Value A bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration Value A bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration Value A bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration Value A bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration Value A bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration Value A bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration Value A bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration Value A bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration Value A bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration Value A bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration Value A bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration Value A bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration Value A bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration Value A bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration Value B group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration Value B group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration Value B bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration Value B bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration Value B bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration Value B bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration Value B bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration Value B bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration Value B bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration Value B bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration Value B bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration Value B bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration Value B bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration Value B bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.ANAINIT  bit masks and bit positions */
-#define MCU_STARTUPDLYB_gm  0x0C  /* Analog startup delay Port A group mask. */
-#define MCU_STARTUPDLYB_gp  2  /* Analog startup delay Port A group position. */
-#define MCU_STARTUPDLYB0_bm  (1<<2)  /* Analog startup delay Port A bit 0 mask. */
-#define MCU_STARTUPDLYB0_bp  2  /* Analog startup delay Port A bit 0 position. */
-#define MCU_STARTUPDLYB1_bm  (1<<3)  /* Analog startup delay Port A bit 1 mask. */
-#define MCU_STARTUPDLYB1_bp  3  /* Analog startup delay Port A bit 1 position. */
-
-#define MCU_STARTUPDLYA_gm  0x03  /* Analog startup delay Port B group mask. */
-#define MCU_STARTUPDLYA_gp  0  /* Analog startup delay Port B group position. */
-#define MCU_STARTUPDLYA0_bm  (1<<0)  /* Analog startup delay Port B bit 0 mask. */
-#define MCU_STARTUPDLYA0_bp  0  /* Analog startup delay Port B bit 0 position. */
-#define MCU_STARTUPDLYA1_bm  (1<<1)  /* Analog startup delay Port B bit 1 mask. */
-#define MCU_STARTUPDLYA1_bp  1  /* Analog startup delay Port B bit 1 position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* PORTCFG - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Peripheral Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Peripheral Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Peripheral Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Peripheral Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Peripheral Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Peripheral Clock Output Port bit 1 position. */
-
-#define PORTCFG_CLKOUTSEL_gm  0x0C  /* Peripheral Clock Output Select group mask. */
-#define PORTCFG_CLKOUTSEL_gp  2  /* Peripheral Clock Output Select group position. */
-#define PORTCFG_CLKOUTSEL0_bm  (1<<2)  /* Peripheral Clock Output Select bit 0 mask. */
-#define PORTCFG_CLKOUTSEL0_bp  2  /* Peripheral Clock Output Select bit 0 position. */
-#define PORTCFG_CLKOUTSEL1_bm  (1<<3)  /* Peripheral Clock Output Select bit 1 mask. */
-#define PORTCFG_CLKOUTSEL1_bp  3  /* Peripheral Clock Output Select bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-#define PORTCFG_RTCOUT_bm  0x40  /* RTC Clock Output bit mask. */
-#define PORTCFG_RTCOUT_bp  6  /* RTC Clock Output bit position. */
-
-#define PORTCFG_CLKEVPIN_bm  0x80  /* Peripheral Clock and Event Output pin Select bit mask. */
-#define PORTCFG_CLKEVPIN_bp  7  /* Peripheral Clock and Event Output pin Select bit position. */
-
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* CRC - Cyclic Redundancy Checker */
-/* CRC.CTRL  bit masks and bit positions */
-#define CRC_RESET_gm  0xC0  /* CRC Reset group mask. */
-#define CRC_RESET_gp  6  /* CRC Reset group position. */
-#define CRC_RESET0_bm  (1<<6)  /* CRC Reset bit 0 mask. */
-#define CRC_RESET0_bp  6  /* CRC Reset bit 0 position. */
-#define CRC_RESET1_bm  (1<<7)  /* CRC Reset bit 1 mask. */
-#define CRC_RESET1_bp  7  /* CRC Reset bit 1 position. */
-
-#define CRC_CRC32_bm  0x20  /* CRC Mode bit mask. */
-#define CRC_CRC32_bp  5  /* CRC Mode bit position. */
-
-#define CRC_SOURCE_gm  0x0F  /* CRC Input Source group mask. */
-#define CRC_SOURCE_gp  0  /* CRC Input Source group position. */
-#define CRC_SOURCE0_bm  (1<<0)  /* CRC Input Source bit 0 mask. */
-#define CRC_SOURCE0_bp  0  /* CRC Input Source bit 0 position. */
-#define CRC_SOURCE1_bm  (1<<1)  /* CRC Input Source bit 1 mask. */
-#define CRC_SOURCE1_bp  1  /* CRC Input Source bit 1 position. */
-#define CRC_SOURCE2_bm  (1<<2)  /* CRC Input Source bit 2 mask. */
-#define CRC_SOURCE2_bp  2  /* CRC Input Source bit 2 position. */
-#define CRC_SOURCE3_bm  (1<<3)  /* CRC Input Source bit 3 mask. */
-#define CRC_SOURCE3_bp  3  /* CRC Input Source bit 3 position. */
-
-
-/* CRC.STATUS  bit masks and bit positions */
-#define CRC_ZERO_bm  0x02  /* Zero CRC detection bit mask. */
-#define CRC_ZERO_bp  1  /* Zero CRC detection bit position. */
-
-#define CRC_BUSY_bm  0x01  /* Enable bit mask. */
-#define CRC_BUSY_bp  0  /* Enable bit position. */
-
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0x7F  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAIN_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAIN_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAIN0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAIN0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAIN1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAIN1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAIN2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAIN2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* MUX selection on Positive ADC input group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* MUX selection on Positive ADC input group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* MUX selection on Positive ADC input bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* MUX selection on Positive ADC input bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* MUX selection on Positive ADC input bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* MUX selection on Positive ADC input bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* MUX selection on Positive ADC input bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* MUX selection on Positive ADC input bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* MUX selection on Positive ADC input bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* MUX selection on Positive ADC input bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* MUX selection on Internal ADC input group mask. */
-#define ADC_CH_MUXINT_gp  3  /* MUX selection on Internal ADC input group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* MUX selection on Internal ADC input bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* MUX selection on Internal ADC input bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* MUX selection on Internal ADC input bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* MUX selection on Internal ADC input bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* MUX selection on Internal ADC input bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* MUX selection on Internal ADC input bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* MUX selection on Internal ADC input bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* MUX selection on Internal ADC input bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* MUX selection on Negative ADC input group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* MUX selection on Negative ADC input group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* MUX selection on Negative ADC input bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* MUX selection on Negative ADC input bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* MUX selection on Negative ADC input bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* MUX selection on Negative ADC input bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_IMPMODE_bm  0x80  /* Gain Stage Impedance Mode bit mask. */
-#define ADC_IMPMODE_bp  7  /* Gain Stage Impedance Mode bit position. */
-
-#define ADC_CURRENT_gm  0x60  /* Current Limitation group mask. */
-#define ADC_CURRENT_gp  5  /* Current Limitation group position. */
-#define ADC_CURRENT0_bm  (1<<5)  /* Current Limitation bit 0 mask. */
-#define ADC_CURRENT0_bp  5  /* Current Limitation bit 0 position. */
-#define ADC_CURRENT1_bm  (1<<6)  /* Current Limitation bit 1 mask. */
-#define ADC_CURRENT1_bp  6  /* Current Limitation bit 1 position. */
-
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
-#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSPLIT_bm  0x08  /* Separate Event Channel Input for Channel 1 bit mask. */
-#define DAC_EVSPLIT_bp  3  /* Separate Event Channel Input for Channel 1 bit position. */
-
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-
-/* DAC.TIMCTRL  bit masks and bit positions */
-#define DAC_CONINTVAL_gm  0x70  /* Conversion Intercal group mask. */
-#define DAC_CONINTVAL_gp  4  /* Conversion Intercal group position. */
-#define DAC_CONINTVAL0_bm  (1<<4)  /* Conversion Intercal bit 0 mask. */
-#define DAC_CONINTVAL0_bp  4  /* Conversion Intercal bit 0 position. */
-#define DAC_CONINTVAL1_bm  (1<<5)  /* Conversion Intercal bit 1 mask. */
-#define DAC_CONINTVAL1_bp  5  /* Conversion Intercal bit 1 position. */
-#define DAC_CONINTVAL2_bm  (1<<6)  /* Conversion Intercal bit 2 mask. */
-#define DAC_CONINTVAL2_bp  6  /* Conversion Intercal bit 2 position. */
-
-#define DAC_REFRESH_gm  0x0F  /* Refresh Timing Control group mask. */
-#define DAC_REFRESH_gp  0  /* Refresh Timing Control group position. */
-#define DAC_REFRESH0_bm  (1<<0)  /* Refresh Timing Control bit 0 mask. */
-#define DAC_REFRESH0_bp  0  /* Refresh Timing Control bit 0 position. */
-#define DAC_REFRESH1_bm  (1<<1)  /* Refresh Timing Control bit 1 mask. */
-#define DAC_REFRESH1_bp  1  /* Refresh Timing Control bit 1 position. */
-#define DAC_REFRESH2_bm  (1<<2)  /* Refresh Timing Control bit 2 mask. */
-#define DAC_REFRESH2_bp  2  /* Refresh Timing Control bit 2 position. */
-#define DAC_REFRESH3_bm  (1<<3)  /* Refresh Timing Control bit 3 mask. */
-#define DAC_REFRESH3_bp  3  /* Refresh Timing Control bit 3 position. */
-
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-
-/* DAC.CH0GAINCAL  bit masks and bit positions */
-#define DAC_CH0GAINCAL_gm  0x7F  /* Gain Calibration group mask. */
-#define DAC_CH0GAINCAL_gp  0  /* Gain Calibration group position. */
-#define DAC_CH0GAINCAL0_bm  (1<<0)  /* Gain Calibration bit 0 mask. */
-#define DAC_CH0GAINCAL0_bp  0  /* Gain Calibration bit 0 position. */
-#define DAC_CH0GAINCAL1_bm  (1<<1)  /* Gain Calibration bit 1 mask. */
-#define DAC_CH0GAINCAL1_bp  1  /* Gain Calibration bit 1 position. */
-#define DAC_CH0GAINCAL2_bm  (1<<2)  /* Gain Calibration bit 2 mask. */
-#define DAC_CH0GAINCAL2_bp  2  /* Gain Calibration bit 2 position. */
-#define DAC_CH0GAINCAL3_bm  (1<<3)  /* Gain Calibration bit 3 mask. */
-#define DAC_CH0GAINCAL3_bp  3  /* Gain Calibration bit 3 position. */
-#define DAC_CH0GAINCAL4_bm  (1<<4)  /* Gain Calibration bit 4 mask. */
-#define DAC_CH0GAINCAL4_bp  4  /* Gain Calibration bit 4 position. */
-#define DAC_CH0GAINCAL5_bm  (1<<5)  /* Gain Calibration bit 5 mask. */
-#define DAC_CH0GAINCAL5_bp  5  /* Gain Calibration bit 5 position. */
-#define DAC_CH0GAINCAL6_bm  (1<<6)  /* Gain Calibration bit 6 mask. */
-#define DAC_CH0GAINCAL6_bp  6  /* Gain Calibration bit 6 position. */
-
-
-/* DAC.CH0OFFSETCAL  bit masks and bit positions */
-#define DAC_CH0OFFSETCAL_gm  0x7F  /* Offset Calibration group mask. */
-#define DAC_CH0OFFSETCAL_gp  0  /* Offset Calibration group position. */
-#define DAC_CH0OFFSETCAL0_bm  (1<<0)  /* Offset Calibration bit 0 mask. */
-#define DAC_CH0OFFSETCAL0_bp  0  /* Offset Calibration bit 0 position. */
-#define DAC_CH0OFFSETCAL1_bm  (1<<1)  /* Offset Calibration bit 1 mask. */
-#define DAC_CH0OFFSETCAL1_bp  1  /* Offset Calibration bit 1 position. */
-#define DAC_CH0OFFSETCAL2_bm  (1<<2)  /* Offset Calibration bit 2 mask. */
-#define DAC_CH0OFFSETCAL2_bp  2  /* Offset Calibration bit 2 position. */
-#define DAC_CH0OFFSETCAL3_bm  (1<<3)  /* Offset Calibration bit 3 mask. */
-#define DAC_CH0OFFSETCAL3_bp  3  /* Offset Calibration bit 3 position. */
-#define DAC_CH0OFFSETCAL4_bm  (1<<4)  /* Offset Calibration bit 4 mask. */
-#define DAC_CH0OFFSETCAL4_bp  4  /* Offset Calibration bit 4 position. */
-#define DAC_CH0OFFSETCAL5_bm  (1<<5)  /* Offset Calibration bit 5 mask. */
-#define DAC_CH0OFFSETCAL5_bp  5  /* Offset Calibration bit 5 position. */
-#define DAC_CH0OFFSETCAL6_bm  (1<<6)  /* Offset Calibration bit 6 mask. */
-#define DAC_CH0OFFSETCAL6_bp  6  /* Offset Calibration bit 6 position. */
-
-
-/* DAC.CH1GAINCAL  bit masks and bit positions */
-#define DAC_CH1GAINCAL_gm  0x7F  /* Gain Calibration group mask. */
-#define DAC_CH1GAINCAL_gp  0  /* Gain Calibration group position. */
-#define DAC_CH1GAINCAL0_bm  (1<<0)  /* Gain Calibration bit 0 mask. */
-#define DAC_CH1GAINCAL0_bp  0  /* Gain Calibration bit 0 position. */
-#define DAC_CH1GAINCAL1_bm  (1<<1)  /* Gain Calibration bit 1 mask. */
-#define DAC_CH1GAINCAL1_bp  1  /* Gain Calibration bit 1 position. */
-#define DAC_CH1GAINCAL2_bm  (1<<2)  /* Gain Calibration bit 2 mask. */
-#define DAC_CH1GAINCAL2_bp  2  /* Gain Calibration bit 2 position. */
-#define DAC_CH1GAINCAL3_bm  (1<<3)  /* Gain Calibration bit 3 mask. */
-#define DAC_CH1GAINCAL3_bp  3  /* Gain Calibration bit 3 position. */
-#define DAC_CH1GAINCAL4_bm  (1<<4)  /* Gain Calibration bit 4 mask. */
-#define DAC_CH1GAINCAL4_bp  4  /* Gain Calibration bit 4 position. */
-#define DAC_CH1GAINCAL5_bm  (1<<5)  /* Gain Calibration bit 5 mask. */
-#define DAC_CH1GAINCAL5_bp  5  /* Gain Calibration bit 5 position. */
-#define DAC_CH1GAINCAL6_bm  (1<<6)  /* Gain Calibration bit 6 mask. */
-#define DAC_CH1GAINCAL6_bp  6  /* Gain Calibration bit 6 position. */
-
-
-/* DAC.CH1OFFSETCAL  bit masks and bit positions */
-#define DAC_CH1OFFSETCAL_gm  0x7F  /* Offset Calibration group mask. */
-#define DAC_CH1OFFSETCAL_gp  0  /* Offset Calibration group position. */
-#define DAC_CH1OFFSETCAL0_bm  (1<<0)  /* Offset Calibration bit 0 mask. */
-#define DAC_CH1OFFSETCAL0_bp  0  /* Offset Calibration bit 0 position. */
-#define DAC_CH1OFFSETCAL1_bm  (1<<1)  /* Offset Calibration bit 1 mask. */
-#define DAC_CH1OFFSETCAL1_bp  1  /* Offset Calibration bit 1 position. */
-#define DAC_CH1OFFSETCAL2_bm  (1<<2)  /* Offset Calibration bit 2 mask. */
-#define DAC_CH1OFFSETCAL2_bp  2  /* Offset Calibration bit 2 position. */
-#define DAC_CH1OFFSETCAL3_bm  (1<<3)  /* Offset Calibration bit 3 mask. */
-#define DAC_CH1OFFSETCAL3_bp  3  /* Offset Calibration bit 3 position. */
-#define DAC_CH1OFFSETCAL4_bm  (1<<4)  /* Offset Calibration bit 4 mask. */
-#define DAC_CH1OFFSETCAL4_bp  4  /* Offset Calibration bit 4 position. */
-#define DAC_CH1OFFSETCAL5_bm  (1<<5)  /* Offset Calibration bit 5 mask. */
-#define DAC_CH1OFFSETCAL5_bp  5  /* Offset Calibration bit 5 position. */
-#define DAC_CH1OFFSETCAL6_bm  (1<<6)  /* Offset Calibration bit 6 mask. */
-#define DAC_CH1OFFSETCAL6_bp  6  /* Offset Calibration bit 6 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Analog Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Analog Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Analog Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Analog Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Analog Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Analog Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Analog Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Analog Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Analog Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Analog Comparator 0 Interrupt Flag bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASIZE_gm  0x7C  /* Address Size group mask. */
-#define EBI_CS_ASIZE_gp  2  /* Address Size group position. */
-#define EBI_CS_ASIZE0_bm  (1<<2)  /* Address Size bit 0 mask. */
-#define EBI_CS_ASIZE0_bp  2  /* Address Size bit 0 position. */
-#define EBI_CS_ASIZE1_bm  (1<<3)  /* Address Size bit 1 mask. */
-#define EBI_CS_ASIZE1_bp  3  /* Address Size bit 1 position. */
-#define EBI_CS_ASIZE2_bm  (1<<4)  /* Address Size bit 2 mask. */
-#define EBI_CS_ASIZE2_bp  4  /* Address Size bit 2 position. */
-#define EBI_CS_ASIZE3_bm  (1<<5)  /* Address Size bit 3 mask. */
-#define EBI_CS_ASIZE3_bp  5  /* Address Size bit 3 position. */
-#define EBI_CS_ASIZE4_bm  (1<<6)  /* Address Size bit 4 mask. */
-#define EBI_CS_ASIZE4_bp  6  /* Address Size bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* USB - USB Module */
-/* USB_EP.STATUS  bit masks and bit positions */
-#define USB_EP_STALL_bm  0x80  /* Endpoint Stall Flag bit mask. */
-#define USB_EP_STALL_bp  7  /* Endpoint Stall Flag bit position. */
-
-#define USB_EP_CRC_bm  0x80  /* CRC Error Flag for Isochronous Out Endpoints bit mask. */
-#define USB_EP_CRC_bp  7  /* CRC Error Flag for Isochronous Out Endpoints bit position. */
-
-#define USB_EP_UNF_bm  0x40  /* Underflow Enpoint Flag for Input Endpoints bit mask. */
-#define USB_EP_UNF_bp  6  /* Underflow Enpoint Flag for Input Endpoints bit position. */
-
-#define USB_EP_OVF_bm  0x40  /* Underflow/Overflow Enpoint Flag for Output Endpoints bit mask. */
-#define USB_EP_OVF_bp  6  /* Underflow/Overflow Enpoint Flag for Output Endpoints bit position. */
-
-#define USB_EP_TRNCOMPL0_bm  0x20  /* Transaction Complete Flag bit mask. */
-#define USB_EP_TRNCOMPL0_bp  5  /* Transaction Complete Flag bit position. */
-
-#define USB_EP_SETUP_bm  0x10  /* SETUP Transaction Complete Flag bit mask. */
-#define USB_EP_SETUP_bp  4  /* SETUP Transaction Complete Flag bit position. */
-
-#define USB_EP_BANK_bm  0x08  /* Bank Select bit mask. */
-#define USB_EP_BANK_bp  3  /* Bank Select bit position. */
-
-#define USB_EP_BUSNACK1_bm  0x04  /* Data Buffer 1 Not Acknowledge bit mask. */
-#define USB_EP_BUSNACK1_bp  2  /* Data Buffer 1 Not Acknowledge bit position. */
-
-#define USB_EP_BUSNACK0_bm  0x02  /* Data Buffer 0 Not Acknowledge bit mask. */
-#define USB_EP_BUSNACK0_bp  1  /* Data Buffer 0 Not Acknowledge bit position. */
-
-#define USB_EP_TOGGLE_bm  0x01  /* Data Toggle bit mask. */
-#define USB_EP_TOGGLE_bp  0  /* Data Toggle bit position. */
-
-
-/* USB_EP.CTRL  bit masks and bit positions */
-#define USB_EP_TYPE_gm  0xC0  /* Endpoint Type group mask. */
-#define USB_EP_TYPE_gp  6  /* Endpoint Type group position. */
-#define USB_EP_TYPE0_bm  (1<<6)  /* Endpoint Type bit 0 mask. */
-#define USB_EP_TYPE0_bp  6  /* Endpoint Type bit 0 position. */
-#define USB_EP_TYPE1_bm  (1<<7)  /* Endpoint Type bit 1 mask. */
-#define USB_EP_TYPE1_bp  7  /* Endpoint Type bit 1 position. */
-
-#define USB_EP_MULTIPKT_bm  0x20  /* Multi Packet Transfer Enable bit mask. */
-#define USB_EP_MULTIPKT_bp  5  /* Multi Packet Transfer Enable bit position. */
-
-#define USB_EP_PINGPONG_bm  0x10  /* Ping-Pong Enable bit mask. */
-#define USB_EP_PINGPONG_bp  4  /* Ping-Pong Enable bit position. */
-
-#define USB_EP_INTDSBL_bm  0x08  /* Interrupt Disable bit mask. */
-#define USB_EP_INTDSBL_bp  3  /* Interrupt Disable bit position. */
-
-/* USB_EP_STALL_bm  Predefined. */
-/* USB_EP_STALL_bp  Predefined. */
-
-#define USB_EP_SIZE_gm  0x07  /* Data Buffer Size group mask. */
-#define USB_EP_SIZE_gp  0  /* Data Buffer Size group position. */
-#define USB_EP_SIZE0_bm  (1<<0)  /* Data Buffer Size bit 0 mask. */
-#define USB_EP_SIZE0_bp  0  /* Data Buffer Size bit 0 position. */
-#define USB_EP_SIZE1_bm  (1<<1)  /* Data Buffer Size bit 1 mask. */
-#define USB_EP_SIZE1_bp  1  /* Data Buffer Size bit 1 position. */
-#define USB_EP_SIZE2_bm  (1<<2)  /* Data Buffer Size bit 2 mask. */
-#define USB_EP_SIZE2_bp  2  /* Data Buffer Size bit 2 position. */
-
-
-/* USB_EP.CNTH  bit masks and bit positions */
-#define USB_EP_ZLP_bm  0x80  /* Zero Length Packet bit mask. */
-#define USB_EP_ZLP_bp  7  /* Zero Length Packet bit position. */
-
-#define USB_EP_CNT_gm  0x03  /* Endpoint Byte Counter group mask. */
-#define USB_EP_CNT_gp  0  /* Endpoint Byte Counter group position. */
-#define USB_EP_CNT0_bm  (1<<0)  /* Endpoint Byte Counter bit 0 mask. */
-#define USB_EP_CNT0_bp  0  /* Endpoint Byte Counter bit 0 position. */
-#define USB_EP_CNT1_bm  (1<<1)  /* Endpoint Byte Counter bit 1 mask. */
-#define USB_EP_CNT1_bp  1  /* Endpoint Byte Counter bit 1 position. */
-
-
-/* USB.CTRLA  bit masks and bit positions */
-#define USB_ENABLE_bm  0x80  /* USB Enable bit mask. */
-#define USB_ENABLE_bp  7  /* USB Enable bit position. */
-
-#define USB_SPEED_bm  0x40  /* Speed Select bit mask. */
-#define USB_SPEED_bp  6  /* Speed Select bit position. */
-
-#define USB_FIFOEN_bm  0x20  /* USB FIFO Enable bit mask. */
-#define USB_FIFOEN_bp  5  /* USB FIFO Enable bit position. */
-
-#define USB_STFRNUM_bm  0x10  /* Store Frame Number Enable bit mask. */
-#define USB_STFRNUM_bp  4  /* Store Frame Number Enable bit position. */
-
-#define USB_MAXEP_gm  0x0F  /* Maximum Endpoint Addresses group mask. */
-#define USB_MAXEP_gp  0  /* Maximum Endpoint Addresses group position. */
-#define USB_MAXEP0_bm  (1<<0)  /* Maximum Endpoint Addresses bit 0 mask. */
-#define USB_MAXEP0_bp  0  /* Maximum Endpoint Addresses bit 0 position. */
-#define USB_MAXEP1_bm  (1<<1)  /* Maximum Endpoint Addresses bit 1 mask. */
-#define USB_MAXEP1_bp  1  /* Maximum Endpoint Addresses bit 1 position. */
-#define USB_MAXEP2_bm  (1<<2)  /* Maximum Endpoint Addresses bit 2 mask. */
-#define USB_MAXEP2_bp  2  /* Maximum Endpoint Addresses bit 2 position. */
-#define USB_MAXEP3_bm  (1<<3)  /* Maximum Endpoint Addresses bit 3 mask. */
-#define USB_MAXEP3_bp  3  /* Maximum Endpoint Addresses bit 3 position. */
-
-
-/* USB.CTRLB  bit masks and bit positions */
-#define USB_PULLRST_bm  0x10  /* Pull during Reset bit mask. */
-#define USB_PULLRST_bp  4  /* Pull during Reset bit position. */
-
-#define USB_RWAKEUP_bm  0x04  /* Remote Wake-up bit mask. */
-#define USB_RWAKEUP_bp  2  /* Remote Wake-up bit position. */
-
-#define USB_GNACK_bm  0x02  /* Global NACK bit mask. */
-#define USB_GNACK_bp  1  /* Global NACK bit position. */
-
-#define USB_ATTACH_bm  0x01  /* Attach bit mask. */
-#define USB_ATTACH_bp  0  /* Attach bit position. */
-
-
-/* USB.STATUS  bit masks and bit positions */
-#define USB_URESUME_bm  0x08  /* Upstream Resume bit mask. */
-#define USB_URESUME_bp  3  /* Upstream Resume bit position. */
-
-#define USB_RESUME_bm  0x04  /* Resume bit mask. */
-#define USB_RESUME_bp  2  /* Resume bit position. */
-
-#define USB_SUSPEND_bm  0x02  /* Bus Suspended bit mask. */
-#define USB_SUSPEND_bp  1  /* Bus Suspended bit position. */
-
-#define USB_BUSRST_bm  0x01  /* Bus Reset bit mask. */
-#define USB_BUSRST_bp  0  /* Bus Reset bit position. */
-
-
-/* USB.ADDR  bit masks and bit positions */
-#define USB_ADDR_gm  0x7F  /* Device Address group mask. */
-#define USB_ADDR_gp  0  /* Device Address group position. */
-#define USB_ADDR0_bm  (1<<0)  /* Device Address bit 0 mask. */
-#define USB_ADDR0_bp  0  /* Device Address bit 0 position. */
-#define USB_ADDR1_bm  (1<<1)  /* Device Address bit 1 mask. */
-#define USB_ADDR1_bp  1  /* Device Address bit 1 position. */
-#define USB_ADDR2_bm  (1<<2)  /* Device Address bit 2 mask. */
-#define USB_ADDR2_bp  2  /* Device Address bit 2 position. */
-#define USB_ADDR3_bm  (1<<3)  /* Device Address bit 3 mask. */
-#define USB_ADDR3_bp  3  /* Device Address bit 3 position. */
-#define USB_ADDR4_bm  (1<<4)  /* Device Address bit 4 mask. */
-#define USB_ADDR4_bp  4  /* Device Address bit 4 position. */
-#define USB_ADDR5_bm  (1<<5)  /* Device Address bit 5 mask. */
-#define USB_ADDR5_bp  5  /* Device Address bit 5 position. */
-#define USB_ADDR6_bm  (1<<6)  /* Device Address bit 6 mask. */
-#define USB_ADDR6_bp  6  /* Device Address bit 6 position. */
-
-
-/* USB.FIFOWP  bit masks and bit positions */
-#define USB_FIFOWP_gm  0x1F  /* FIFO Write Pointer group mask. */
-#define USB_FIFOWP_gp  0  /* FIFO Write Pointer group position. */
-#define USB_FIFOWP0_bm  (1<<0)  /* FIFO Write Pointer bit 0 mask. */
-#define USB_FIFOWP0_bp  0  /* FIFO Write Pointer bit 0 position. */
-#define USB_FIFOWP1_bm  (1<<1)  /* FIFO Write Pointer bit 1 mask. */
-#define USB_FIFOWP1_bp  1  /* FIFO Write Pointer bit 1 position. */
-#define USB_FIFOWP2_bm  (1<<2)  /* FIFO Write Pointer bit 2 mask. */
-#define USB_FIFOWP2_bp  2  /* FIFO Write Pointer bit 2 position. */
-#define USB_FIFOWP3_bm  (1<<3)  /* FIFO Write Pointer bit 3 mask. */
-#define USB_FIFOWP3_bp  3  /* FIFO Write Pointer bit 3 position. */
-#define USB_FIFOWP4_bm  (1<<4)  /* FIFO Write Pointer bit 4 mask. */
-#define USB_FIFOWP4_bp  4  /* FIFO Write Pointer bit 4 position. */
-
-
-/* USB.FIFORP  bit masks and bit positions */
-#define USB_FIFORP_gm  0x1F  /* FIFO Read Pointer group mask. */
-#define USB_FIFORP_gp  0  /* FIFO Read Pointer group position. */
-#define USB_FIFORP0_bm  (1<<0)  /* FIFO Read Pointer bit 0 mask. */
-#define USB_FIFORP0_bp  0  /* FIFO Read Pointer bit 0 position. */
-#define USB_FIFORP1_bm  (1<<1)  /* FIFO Read Pointer bit 1 mask. */
-#define USB_FIFORP1_bp  1  /* FIFO Read Pointer bit 1 position. */
-#define USB_FIFORP2_bm  (1<<2)  /* FIFO Read Pointer bit 2 mask. */
-#define USB_FIFORP2_bp  2  /* FIFO Read Pointer bit 2 position. */
-#define USB_FIFORP3_bm  (1<<3)  /* FIFO Read Pointer bit 3 mask. */
-#define USB_FIFORP3_bp  3  /* FIFO Read Pointer bit 3 position. */
-#define USB_FIFORP4_bm  (1<<4)  /* FIFO Read Pointer bit 4 mask. */
-#define USB_FIFORP4_bp  4  /* FIFO Read Pointer bit 4 position. */
-
-
-/* USB.INTCTRLA  bit masks and bit positions */
-#define USB_SOFIE_bm  0x80  /* Start Of Frame Interrupt Enable bit mask. */
-#define USB_SOFIE_bp  7  /* Start Of Frame Interrupt Enable bit position. */
-
-#define USB_BUSEVIE_bm  0x40  /* Bus Event Interrupt Enable bit mask. */
-#define USB_BUSEVIE_bp  6  /* Bus Event Interrupt Enable bit position. */
-
-#define USB_BUSERRIE_bm  0x20  /* Bus Error Interrupt Enable bit mask. */
-#define USB_BUSERRIE_bp  5  /* Bus Error Interrupt Enable bit position. */
-
-#define USB_STALLIE_bm  0x10  /* STALL Interrupt Enable bit mask. */
-#define USB_STALLIE_bp  4  /* STALL Interrupt Enable bit position. */
-
-#define USB_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define USB_INTLVL_gp  0  /* Interrupt Level group position. */
-#define USB_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define USB_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define USB_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define USB_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* USB.INTCTRLB  bit masks and bit positions */
-#define USB_TRNIE_bm  0x02  /* Transaction Complete Interrupt Enable bit mask. */
-#define USB_TRNIE_bp  1  /* Transaction Complete Interrupt Enable bit position. */
-
-#define USB_SETUPIE_bm  0x01  /* SETUP Transaction Complete Interrupt Enable bit mask. */
-#define USB_SETUPIE_bp  0  /* SETUP Transaction Complete Interrupt Enable bit position. */
-
-
-/* USB.INTFLAGSACLR  bit masks and bit positions */
-#define USB_SOFIF_bm  0x80  /* Start Of Frame Interrupt Flag bit mask. */
-#define USB_SOFIF_bp  7  /* Start Of Frame Interrupt Flag bit position. */
-
-#define USB_SUSPENDIF_bm  0x40  /* Suspend Interrupt Flag bit mask. */
-#define USB_SUSPENDIF_bp  6  /* Suspend Interrupt Flag bit position. */
-
-#define USB_RESUMEIF_bm  0x20  /* Resume Interrupt Flag bit mask. */
-#define USB_RESUMEIF_bp  5  /* Resume Interrupt Flag bit position. */
-
-#define USB_RSTIF_bm  0x10  /* Reset Interrupt Flag bit mask. */
-#define USB_RSTIF_bp  4  /* Reset Interrupt Flag bit position. */
-
-#define USB_CRCIF_bm  0x08  /* Isochronous CRC Error Interrupt Flag bit mask. */
-#define USB_CRCIF_bp  3  /* Isochronous CRC Error Interrupt Flag bit position. */
-
-#define USB_UNFIF_bm  0x04  /* Underflow Interrupt Flag bit mask. */
-#define USB_UNFIF_bp  2  /* Underflow Interrupt Flag bit position. */
-
-#define USB_OVFIF_bm  0x02  /* Overflow Interrupt Flag bit mask. */
-#define USB_OVFIF_bp  1  /* Overflow Interrupt Flag bit position. */
-
-#define USB_STALLIF_bm  0x01  /* STALL Interrupt Flag bit mask. */
-#define USB_STALLIF_bp  0  /* STALL Interrupt Flag bit position. */
-
-
-/* USB.INTFLAGSASET  bit masks and bit positions */
-/* USB_SOFIF_bm  Predefined. */
-/* USB_SOFIF_bp  Predefined. */
-
-/* USB_SUSPENDIF_bm  Predefined. */
-/* USB_SUSPENDIF_bp  Predefined. */
-
-/* USB_RESUMEIF_bm  Predefined. */
-/* USB_RESUMEIF_bp  Predefined. */
-
-/* USB_RSTIF_bm  Predefined. */
-/* USB_RSTIF_bp  Predefined. */
-
-/* USB_CRCIF_bm  Predefined. */
-/* USB_CRCIF_bp  Predefined. */
-
-/* USB_UNFIF_bm  Predefined. */
-/* USB_UNFIF_bp  Predefined. */
-
-/* USB_OVFIF_bm  Predefined. */
-/* USB_OVFIF_bp  Predefined. */
-
-/* USB_STALLIF_bm  Predefined. */
-/* USB_STALLIF_bp  Predefined. */
-
-
-/* USB.INTFLAGSBCLR  bit masks and bit positions */
-#define USB_TRNIF_bm  0x02  /* Transaction Complete Interrupt Flag bit mask. */
-#define USB_TRNIF_bp  1  /* Transaction Complete Interrupt Flag bit position. */
-
-#define USB_SETUPIF_bm  0x01  /* SETUP Transaction Complete Interrupt Flag bit mask. */
-#define USB_SETUPIF_bp  0  /* SETUP Transaction Complete Interrupt Flag bit position. */
-
-
-/* USB.INTFLAGSBSET  bit masks and bit positions */
-/* USB_TRNIF_bm  Predefined. */
-/* USB_TRNIF_bp  Predefined. */
-
-/* USB_SETUPIF_bm  Predefined. */
-/* USB_SETUPIF_bp  Predefined. */
-
-
-/* PORT - I/O Port Configuration */
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX - Timer/Counter Advanced Waveform Extension */
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES - Timer/Counter High-Resolution Extension */
-/* HIRES.CTRLA  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-/* PRESC - Prescaler */
-/* PRESC.PRESCALER  bit masks and bit positions */
-#define PRESC_RESET_bm  0x01  /* Reset bit mask. */
-#define PRESC_RESET_bp  0  /* Reset bit position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01 
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04 
-#define PIN2_bp 2
-#define PIN3_bm 0x08 
-#define PIN3_bp 3
-#define PIN4_bm 0x10 
-#define PIN4_bp 4
-#define PIN5_bm 0x20 
-#define PIN5_bp 5
-#define PIN6_bm 0x40 
-#define PIN6_bp 6
-#define PIN7_bm 0x80 
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_OSCF_vect_num  1
-#define OSC_OSCF_vect      _VECTOR(1)  /* Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* ACB interrupt vectors */
-#define ACB_AC0_vect_num  36
-#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
-#define ACB_AC1_vect_num  37
-#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
-#define ACB_ACW_vect_num  38
-#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
-
-/* ADCB interrupt vectors */
-#define ADCB_CH0_vect_num  39
-#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
-#define ADCB_CH1_vect_num  40
-#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
-#define ADCB_CH2_vect_num  41
-#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
-#define ADCB_CH3_vect_num  42
-#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* SPIE interrupt vectors */
-#define SPIE_INT_vect_num  57
-#define SPIE_INT_vect      _VECTOR(57)  /* SPI Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* USARTE1 interrupt vectors */
-#define USARTE1_RXC_vect_num  61
-#define USARTE1_RXC_vect      _VECTOR(61)  /* Reception Complete Interrupt */
-#define USARTE1_DRE_vect_num  62
-#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
-#define USARTE1_TXC_vect_num  63
-#define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TWID interrupt vectors */
-#define TWID_TWIS_vect_num  75
-#define TWID_TWIS_vect      _VECTOR(75)  /* TWI Slave Interrupt */
-#define TWID_TWIM_vect_num  76
-#define TWID_TWIM_vect      _VECTOR(76)  /* TWI Master Interrupt */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
-
-/* PORTQ interrupt vectors */
-#define PORTQ_INT0_vect_num  94
-#define PORTQ_INT0_vect      _VECTOR(94)  /* External Interrupt 0 */
-#define PORTQ_INT1_vect_num  95
-#define PORTQ_INT1_vect      _VECTOR(95)  /* External Interrupt 1 */
-
-/* PORTH interrupt vectors */
-#define PORTH_INT0_vect_num  96
-#define PORTH_INT0_vect      _VECTOR(96)  /* External Interrupt 0 */
-#define PORTH_INT1_vect_num  97
-#define PORTH_INT1_vect      _VECTOR(97)  /* External Interrupt 1 */
-
-/* PORTJ interrupt vectors */
-#define PORTJ_INT0_vect_num  98
-#define PORTJ_INT0_vect      _VECTOR(98)  /* External Interrupt 0 */
-#define PORTJ_INT1_vect_num  99
-#define PORTJ_INT1_vect      _VECTOR(99)  /* External Interrupt 1 */
-
-/* PORTK interrupt vectors */
-#define PORTK_INT0_vect_num  100
-#define PORTK_INT0_vect      _VECTOR(100)  /* External Interrupt 0 */
-#define PORTK_INT1_vect_num  101
-#define PORTK_INT1_vect      _VECTOR(101)  /* External Interrupt 1 */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TWIF interrupt vectors */
-#define TWIF_TWIS_vect_num  106
-#define TWIF_TWIS_vect      _VECTOR(106)  /* TWI Slave Interrupt */
-#define TWIF_TWIM_vect_num  107
-#define TWIF_TWIM_vect      _VECTOR(107)  /* TWI Master Interrupt */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-/* TCF1 interrupt vectors */
-#define TCF1_OVF_vect_num  114
-#define TCF1_OVF_vect      _VECTOR(114)  /* Overflow Interrupt */
-#define TCF1_ERR_vect_num  115
-#define TCF1_ERR_vect      _VECTOR(115)  /* Error Interrupt */
-#define TCF1_CCA_vect_num  116
-#define TCF1_CCA_vect      _VECTOR(116)  /* Compare or Capture A Interrupt */
-#define TCF1_CCB_vect_num  117
-#define TCF1_CCB_vect      _VECTOR(117)  /* Compare or Capture B Interrupt */
-
-/* SPIF interrupt vectors */
-#define SPIF_INT_vect_num  118
-#define SPIF_INT_vect      _VECTOR(118)  /* SPI Interrupt */
-
-/* USARTF0 interrupt vectors */
-#define USARTF0_RXC_vect_num  119
-#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
-#define USARTF0_DRE_vect_num  120
-#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
-#define USARTF0_TXC_vect_num  121
-#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
-
-/* USARTF1 interrupt vectors */
-#define USARTF1_RXC_vect_num  122
-#define USARTF1_RXC_vect      _VECTOR(122)  /* Reception Complete Interrupt */
-#define USARTF1_DRE_vect_num  123
-#define USARTF1_DRE_vect      _VECTOR(123)  /* Data Register Empty Interrupt */
-#define USARTF1_TXC_vect_num  124
-#define USARTF1_TXC_vect      _VECTOR(124)  /* Transmission Complete Interrupt */
-
-/* USB interrupt vectors */
-#define USB_BUSEVENT_vect_num  125
-#define USB_BUSEVENT_vect      _VECTOR(125)  /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
-#define USB_TRNCOMPL_vect_num  126
-#define USB_TRNCOMPL_vect      _VECTOR(126)  /* Transaction complete interrupt */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x00000)
-#define PROGMEM_SIZE      (139264)
-#define PROGMEM_PAGE_SIZE (512)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x00000)
-#define APP_SECTION_SIZE      (131072)
-#define APP_SECTION_PAGE_SIZE (512)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x1E000)
-#define APPTABLE_SECTION_SIZE      (8192)
-#define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x20000)
-#define BOOT_SECTION_SIZE      (8192)
-#define BOOT_SECTION_PAGE_SIZE (512)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (2048)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (16777216)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (2048)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (8192)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EXTERNAL_SRAM_START     (0x4000)
-#define EXTERNAL_SRAM_SIZE      (16760832)
-#define EXTERNAL_SRAM_PAGE_SIZE (0)
-#define EXTERNAL_SRAM_END       (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (512)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      EXTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 0
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x4C
-
-/* ========== Power Reduction Condition Definitions ========== */
-
-/* PR.PRGEN */
-#define __AVR_HAVE_PRGEN	(PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm)
-#define __AVR_HAVE_PRGEN_USB
-#define __AVR_HAVE_PRGEN_AES
-#define __AVR_HAVE_PRGEN_EBI
-#define __AVR_HAVE_PRGEN_RTC
-#define __AVR_HAVE_PRGEN_EVSYS
-#define __AVR_HAVE_PRGEN_DMA
-
-/* PR.PRPA */
-#define __AVR_HAVE_PRPA	(PR_DAC_bm|PR_ADC_bm|PR_AC_bm)
-#define __AVR_HAVE_PRPA_DAC
-#define __AVR_HAVE_PRPA_ADC
-#define __AVR_HAVE_PRPA_AC
-
-/* PR.PRPB */
-#define __AVR_HAVE_PRPB	(PR_DAC_bm|PR_ADC_bm|PR_AC_bm)
-#define __AVR_HAVE_PRPB_DAC
-#define __AVR_HAVE_PRPB_ADC
-#define __AVR_HAVE_PRPB_AC
-
-/* PR.PRPC */
-#define __AVR_HAVE_PRPC	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
-#define __AVR_HAVE_PRPC_TWI
-#define __AVR_HAVE_PRPC_USART1
-#define __AVR_HAVE_PRPC_USART0
-#define __AVR_HAVE_PRPC_SPI
-#define __AVR_HAVE_PRPC_HIRES
-#define __AVR_HAVE_PRPC_TC1
-#define __AVR_HAVE_PRPC_TC0
-
-/* PR.PRPD */
-#define __AVR_HAVE_PRPD	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
-#define __AVR_HAVE_PRPD_TWI
-#define __AVR_HAVE_PRPD_USART1
-#define __AVR_HAVE_PRPD_USART0
-#define __AVR_HAVE_PRPD_SPI
-#define __AVR_HAVE_PRPD_HIRES
-#define __AVR_HAVE_PRPD_TC1
-#define __AVR_HAVE_PRPD_TC0
-
-/* PR.PRPE */
-#define __AVR_HAVE_PRPE	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
-#define __AVR_HAVE_PRPE_TWI
-#define __AVR_HAVE_PRPE_USART1
-#define __AVR_HAVE_PRPE_USART0
-#define __AVR_HAVE_PRPE_SPI
-#define __AVR_HAVE_PRPE_HIRES
-#define __AVR_HAVE_PRPE_TC1
-#define __AVR_HAVE_PRPE_TC0
-
-/* PR.PRPF */
-#define __AVR_HAVE_PRPF	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
-#define __AVR_HAVE_PRPF_TWI
-#define __AVR_HAVE_PRPF_USART1
-#define __AVR_HAVE_PRPF_USART0
-#define __AVR_HAVE_PRPF_SPI
-#define __AVR_HAVE_PRPF_HIRES
-#define __AVR_HAVE_PRPF_TC1
-#define __AVR_HAVE_PRPF_TC0
-
-#endif /* _AVR_ATxmega128A1U_H_ */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iox128a1u.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+#ifndef _AVR_ATXMEGA128A1U_H_INCLUDED
+#define _AVR_ATXMEGA128A1U_H_INCLUDED
+
+/* Ungrouped common registers */
+#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
+#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
+#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
+#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
+#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
+#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
+#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
+#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
+#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
+#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
+#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
+#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
+#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
+#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
+#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
+#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
+
+/* Deprecated */
+#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
+#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
+#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
+#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
+#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
+#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
+#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
+#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
+#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
+#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
+#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
+#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
+#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
+#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
+#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
+#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
+
+#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
+#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
+#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
+#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
+#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
+#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
+#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
+#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
+#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
+
+/* C Language Only */
+#if !defined (__ASSEMBLER__)
+
+#include <stdint.h>
+
+typedef volatile uint8_t register8_t;
+typedef volatile uint16_t register16_t;
+typedef volatile uint32_t register32_t;
+
+
+#ifdef _WORDREGISTER
+#undef _WORDREGISTER
+#endif
+#define _WORDREGISTER(regname)   \
+    __extension__ union \
+    { \
+        register16_t regname; \
+        struct \
+        { \
+            register8_t regname ## L; \
+            register8_t regname ## H; \
+        }; \
+    }
+
+#ifdef _DWORDREGISTER
+#undef _DWORDREGISTER
+#endif
+#define _DWORDREGISTER(regname)  \
+    __extension__ union \
+    { \
+        register32_t regname; \
+        struct \
+        { \
+            register8_t regname ## 0; \
+            register8_t regname ## 1; \
+            register8_t regname ## 2; \
+            register8_t regname ## 3; \
+        }; \
+    }
+
+
+/*
+==========================================================================
+IO Module Structures
+==========================================================================
+*/
+
+
+/*
+--------------------------------------------------------------------------
+AC - Analog Comparator
+--------------------------------------------------------------------------
+*/
+
+/* Analog Comparator */
+typedef struct AC_struct
+{
+    register8_t AC0CTRL;  /* Analog Comparator 0 Control */
+    register8_t AC1CTRL;  /* Analog Comparator 1 Control */
+    register8_t AC0MUXCTRL;  /* Analog Comparator 0 MUX Control */
+    register8_t AC1MUXCTRL;  /* Analog Comparator 1 MUX Control */
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t WINCTRL;  /* Window Mode Control */
+    register8_t STATUS;  /* Status */
+    register8_t CURRCTRL;  /* Current Source Control */
+    register8_t CURRCALIB;  /* Current Source Calibration */
+} AC_t;
+
+/* Hysteresis mode selection */
+typedef enum AC_HYSMODE_enum
+{
+    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
+    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
+    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
+} AC_HYSMODE_t;
+
+/* Interrupt level */
+typedef enum AC_INTLVL_enum
+{
+    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
+    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
+    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
+    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
+} AC_INTLVL_t;
+
+/* Interrupt mode */
+typedef enum AC_INTMODE_enum
+{
+    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
+    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
+    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
+} AC_INTMODE_t;
+
+/* Negative input multiplexer selection */
+typedef enum AC_MUXNEG_enum
+{
+    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
+    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
+    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
+    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
+    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
+    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
+    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
+    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
+} AC_MUXNEG_t;
+
+/* Positive input multiplexer selection */
+typedef enum AC_MUXPOS_enum
+{
+    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
+    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
+    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
+    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
+    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
+    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
+    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
+    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
+} AC_MUXPOS_t;
+
+/* Window interrupt level */
+typedef enum AC_WINTLVL_enum
+{
+    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
+    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
+    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
+    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
+} AC_WINTLVL_t;
+
+/* Windows interrupt mode */
+typedef enum AC_WINTMODE_enum
+{
+    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
+    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
+    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
+    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
+} AC_WINTMODE_t;
+
+/* Window mode state */
+typedef enum AC_WSTATE_enum
+{
+    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
+    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
+    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
+} AC_WSTATE_t;
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* ADC Channel */
+typedef struct ADC_CH_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t MUXCTRL;  /* MUX Control */
+    register8_t INTCTRL;  /* Channel Interrupt Control Register */
+    register8_t INTFLAGS;  /* Interrupt Flags */
+    _WORDREGISTER(RES);  /* Channel Result */
+    register8_t SCAN;  /* Input Channel Scan */
+    register8_t reserved_0x07;
+} ADC_CH_t;
+
+
+/* Analog-to-Digital Converter */
+typedef struct ADC_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t REFCTRL;  /* Reference Control */
+    register8_t EVCTRL;  /* Event Control */
+    register8_t PRESCALER;  /* Clock Prescaler */
+    register8_t reserved_0x05;
+    register8_t INTFLAGS;  /* Interrupt Flags */
+    register8_t TEMP;  /* Temporary Register */
+    register8_t reserved_0x08;
+    register8_t reserved_0x09;
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+    _WORDREGISTER(CAL);  /* Calibration Value */
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
+    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
+    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
+    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
+    _WORDREGISTER(CMP);  /* Compare Value */
+    register8_t reserved_0x1A;
+    register8_t reserved_0x1B;
+    register8_t reserved_0x1C;
+    register8_t reserved_0x1D;
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    ADC_CH_t CH0;  /* ADC Channel 0 */
+    ADC_CH_t CH1;  /* ADC Channel 1 */
+    ADC_CH_t CH2;  /* ADC Channel 2 */
+    ADC_CH_t CH3;  /* ADC Channel 3 */
+} ADC_t;
+
+/* Gain factor */
+typedef enum ADC_CH_GAIN_enum
+{
+    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
+    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
+    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
+    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
+    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
+    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
+    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
+    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */
+} ADC_CH_GAIN_t;
+
+/* Input mode */
+typedef enum ADC_CH_INPUTMODE_enum
+{
+    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
+    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
+    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
+    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
+} ADC_CH_INPUTMODE_t;
+
+/* Interrupt level */
+typedef enum ADC_CH_INTLVL_enum
+{
+    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
+    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
+    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
+    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
+} ADC_CH_INTLVL_t;
+
+/* Interrupt mode */
+typedef enum ADC_CH_INTMODE_enum
+{
+    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
+    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
+    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
+} ADC_CH_INTMODE_t;
+
+/* Internal input multiplexer selections */
+typedef enum ADC_CH_MUXINT_enum
+{
+    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
+    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
+    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
+    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
+} ADC_CH_MUXINT_t;
+
+/* Negative input multiplexer selection */
+typedef enum ADC_CH_MUXNEG_enum
+{
+    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN4_gc = (0x00<<0),  /* Input pin 4 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN5_gc = (0x01<<0),  /* Input pin 5 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN6_gc = (0x02<<0),  /* Input pin 6 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN7_gc = (0x03<<0),  /* Input pin 7 (Input Mode = 3) */
+    ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0),  /* Internal Ground (Input Mode = 3) */
+    ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0),  /* PAD Ground (Input Mode = 2) */
+    ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0),  /* Internal Ground (Input Mode = 2) */
+    ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0),  /* PAD Ground (Input Mode = 3) */
+} ADC_CH_MUXNEG_t;
+
+/* Positive input multiplexer selection */
+typedef enum ADC_CH_MUXPOS_enum
+{
+    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
+    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
+    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
+    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
+    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
+    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
+    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
+    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
+    ADC_CH_MUXPOS_PIN8_gc = (0x08<<3),  /* Input pin 8 */
+    ADC_CH_MUXPOS_PIN9_gc = (0x09<<3),  /* Input pin 9 */
+    ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3),  /* Input pin 10 */
+    ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3),  /* Input pin 11 */
+    ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3),  /* Input pin 12 */
+    ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3),  /* Input pin 13 */
+    ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3),  /* Input pin 14 */
+    ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3),  /* Input pin 15 */
+} ADC_CH_MUXPOS_t;
+
+/* Current Limitation Mode */
+typedef enum ADC_CURRLIMIT_enum
+{
+    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No limit */
+    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit, max. sampling rate 1.5MSPS */
+    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, max. sampling rate 1MSPS */
+    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit, max. sampling rate 0.5MSPS */
+} ADC_CURRLIMIT_t;
+
+/* DMA request selection */
+typedef enum ADC_DMASEL_enum
+{
+    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
+    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
+    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
+    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
+} ADC_DMASEL_t;
+
+/* Event action selection */
+typedef enum ADC_EVACT_enum
+{
+    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
+    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
+    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
+    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
+    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
+    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
+    ADC_EVACT_SYNCSWEEP_gc = (0x06<<0),  /* The ADC is flushed and restarted for accurate timing */
+} ADC_EVACT_t;
+
+/* Event channel input selection */
+typedef enum ADC_EVSEL_enum
+{
+    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
+    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
+    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
+    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
+    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
+    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
+    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
+    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
+} ADC_EVSEL_t;
+
+/* Clock prescaler */
+typedef enum ADC_PRESCALER_enum
+{
+    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
+    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
+    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
+    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
+    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
+    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
+    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
+    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
+} ADC_PRESCALER_t;
+
+/* Voltage reference selection */
+typedef enum ADC_REFSEL_enum
+{
+    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
+    ADC_REFSEL_INTVCC_gc = (0x01<<4),  /* Internal VCC / 1.6 */
+    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
+    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
+    ADC_REFSEL_INTVCC2_gc = (0x04<<4),  /* Internal VCC / 2 */
+} ADC_REFSEL_t;
+
+/* Conversion result resolution */
+typedef enum ADC_RESOLUTION_enum
+{
+    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
+    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
+    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
+} ADC_RESOLUTION_t;
+
+/* Channel sweep selection */
+typedef enum ADC_SWEEP_enum
+{
+    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
+    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
+    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
+    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
+} ADC_SWEEP_t;
+
+/*
+--------------------------------------------------------------------------
+AES - AES Module
+--------------------------------------------------------------------------
+*/
+
+/* AES Module */
+typedef struct AES_struct
+{
+    register8_t CTRL;  /* AES Control Register */
+    register8_t STATUS;  /* AES Status Register */
+    register8_t STATE;  /* AES State Register */
+    register8_t KEY;  /* AES Key Register */
+    register8_t INTCTRL;  /* AES Interrupt Control Register */
+} AES_t;
+
+/* Interrupt level */
+typedef enum AES_INTLVL_enum
+{
+    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
+} AES_INTLVL_t;
+
+/*
+--------------------------------------------------------------------------
+AWEX - Timer/Counter Advanced Waveform Extension
+--------------------------------------------------------------------------
+*/
+
+/* Advanced Waveform Extension */
+typedef struct AWEX_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t reserved_0x01;
+    register8_t FDEMASK;  /* Fault Detection Event Mask */
+    register8_t FDCTRL;  /* Fault Detection Control Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t STATUSSET;  /* Status Set Register */
+    register8_t DTBOTH;  /* Dead Time Both Sides */
+    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
+    register8_t DTLS;  /* Dead Time Low Side */
+    register8_t DTHS;  /* Dead Time High Side */
+    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
+    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
+    register8_t OUTOVEN;  /* Output Override Enable */
+} AWEX_t;
+
+/* Fault Detect Action */
+typedef enum AWEX_FDACT_enum
+{
+    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
+    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
+    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
+} AWEX_FDACT_t;
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Clock System */
+typedef struct CLK_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t PSCTRL;  /* Prescaler Control Register */
+    register8_t LOCK;  /* Lock register */
+    register8_t RTCCTRL;  /* RTC Control Register */
+    register8_t USBCTRL;  /* USB Control Register */
+} CLK_t;
+
+/* Prescaler A Division Factor */
+typedef enum CLK_PSADIV_enum
+{
+    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
+    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
+    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
+    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
+    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
+    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
+    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
+    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
+    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
+    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
+} CLK_PSADIV_t;
+
+/* Prescaler B and C Division Factor */
+typedef enum CLK_PSBCDIV_enum
+{
+    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
+    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
+    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
+    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
+} CLK_PSBCDIV_t;
+
+/* RTC Clock Source */
+typedef enum CLK_RTCSRC_enum
+{
+    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1.024 kHz from internal 32kHz ULP */
+    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
+    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1.024 kHz from internal 32.768 kHz RC oscillator */
+    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
+    CLK_RTCSRC_RCOSC32_gc = (0x06<<1),  /* 32.768 kHz from internal 32.768 kHz RC oscillator */
+    CLK_RTCSRC_EXTCLK_gc = (0x07<<1),  /* External Clock from TOSC1 */
+} CLK_RTCSRC_t;
+
+/* System Clock Selection */
+typedef enum CLK_SCLKSEL_enum
+{
+    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2 MHz RC Oscillator */
+    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32 MHz RC Oscillator */
+    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32.768 kHz RC Oscillator */
+    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
+    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
+} CLK_SCLKSEL_t;
+
+/* USB Prescaler Division Factor */
+typedef enum CLK_USBPSDIV_enum
+{
+    CLK_USBPSDIV_1_gc = (0x00<<3),  /* Divide by 1 */
+    CLK_USBPSDIV_2_gc = (0x01<<3),  /* Divide by 2 */
+    CLK_USBPSDIV_4_gc = (0x02<<3),  /* Divide by 4 */
+    CLK_USBPSDIV_8_gc = (0x03<<3),  /* Divide by 8 */
+    CLK_USBPSDIV_16_gc = (0x04<<3),  /* Divide by 16 */
+    CLK_USBPSDIV_32_gc = (0x05<<3),  /* Divide by 32 */
+} CLK_USBPSDIV_t;
+
+/* USB Clock Source */
+typedef enum CLK_USBSRC_enum
+{
+    CLK_USBSRC_PLL_gc = (0x00<<1),  /* PLL */
+    CLK_USBSRC_RC32M_gc = (0x01<<1),  /* Internal 32 MHz RC Oscillator */
+} CLK_USBSRC_t;
+
+/*
+--------------------------------------------------------------------------
+CPU - CPU
+--------------------------------------------------------------------------
+*/
+
+/* CCP signatures */
+typedef enum CCP_enum
+{
+    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
+    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
+} CCP_t;
+
+/*
+--------------------------------------------------------------------------
+CRC - Cyclic Redundancy Checker
+--------------------------------------------------------------------------
+*/
+
+/* Cyclic Redundancy Checker */
+typedef struct CRC_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t reserved_0x02;
+    register8_t DATAIN;  /* Data Input */
+    register8_t CHECKSUM0;  /* Checksum byte 0 */
+    register8_t CHECKSUM1;  /* Checksum byte 1 */
+    register8_t CHECKSUM2;  /* Checksum byte 2 */
+    register8_t CHECKSUM3;  /* Checksum byte 3 */
+} CRC_t;
+
+/* Reset */
+typedef enum CRC_RESET_enum
+{
+    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
+    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
+    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
+} CRC_RESET_t;
+
+/* Input Source */
+typedef enum CRC_SOURCE_enum
+{
+    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
+    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
+    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
+    CRC_SOURCE_DMAC0_gc = (0x04<<0),  /* DMAC Channel 0 */
+    CRC_SOURCE_DMAC1_gc = (0x05<<0),  /* DMAC Channel 1 */
+    CRC_SOURCE_DMAC2_gc = (0x06<<0),  /* DMAC Channel 2 */
+    CRC_SOURCE_DMAC3_gc = (0x07<<0),  /* DMAC Channel 3 */
+} CRC_SOURCE_t;
+
+/*
+--------------------------------------------------------------------------
+DAC - Digital/Analog Converter
+--------------------------------------------------------------------------
+*/
+
+/* Digital-to-Analog Converter */
+typedef struct DAC_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control Register C */
+    register8_t EVCTRL;  /* Event Input Control */
+    register8_t reserved_0x04;
+    register8_t STATUS;  /* Status */
+    register8_t reserved_0x06;
+    register8_t reserved_0x07;
+    register8_t CH0GAINCAL;  /* Gain Calibration */
+    register8_t CH0OFFSETCAL;  /* Offset Calibration */
+    register8_t CH1GAINCAL;  /* Gain Calibration */
+    register8_t CH1OFFSETCAL;  /* Offset Calibration */
+    register8_t reserved_0x0C;
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    register8_t reserved_0x10;
+    register8_t reserved_0x11;
+    register8_t reserved_0x12;
+    register8_t reserved_0x13;
+    register8_t reserved_0x14;
+    register8_t reserved_0x15;
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
+    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
+} DAC_t;
+
+/* Output channel selection */
+typedef enum DAC_CHSEL_enum
+{
+    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel 0 only) */
+    DAC_CHSEL_SINGLE1_gc = (0x01<<5),  /* Single channel operation (Channel 1 only) */
+    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (Channel 0 and channel 1) */
+} DAC_CHSEL_t;
+
+/* Event channel selection */
+typedef enum DAC_EVSEL_enum
+{
+    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
+    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
+    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
+    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
+    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
+    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
+    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
+    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
+} DAC_EVSEL_t;
+
+/* Reference voltage selection */
+typedef enum DAC_REFSEL_enum
+{
+    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
+    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
+    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
+    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
+} DAC_REFSEL_t;
+
+/*
+--------------------------------------------------------------------------
+DFLL - DFLL
+--------------------------------------------------------------------------
+*/
+
+/* DFLL */
+typedef struct DFLL_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t reserved_0x01;
+    register8_t CALA;  /* Calibration Register A */
+    register8_t CALB;  /* Calibration Register B */
+    register8_t COMP0;  /* Oscillator Compare Register 0 */
+    register8_t COMP1;  /* Oscillator Compare Register 1 */
+    register8_t COMP2;  /* Oscillator Compare Register 2 */
+    register8_t reserved_0x07;
+} DFLL_t;
+
+
+/*
+--------------------------------------------------------------------------
+DMA - DMA Controller
+--------------------------------------------------------------------------
+*/
+
+/* DMA Channel */
+typedef struct DMA_CH_struct
+{
+    register8_t CTRLA;  /* Channel Control */
+    register8_t CTRLB;  /* Channel Control */
+    register8_t ADDRCTRL;  /* Address Control */
+    register8_t TRIGSRC;  /* Channel Trigger Source */
+    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
+    register8_t REPCNT;  /* Channel Repeat Count */
+    register8_t reserved_0x07;
+    register8_t SRCADDR0;  /* Channel Source Address 0 */
+    register8_t SRCADDR1;  /* Channel Source Address 1 */
+    register8_t SRCADDR2;  /* Channel Source Address 2 */
+    register8_t reserved_0x0B;
+    register8_t DESTADDR0;  /* Channel Destination Address 0 */
+    register8_t DESTADDR1;  /* Channel Destination Address 1 */
+    register8_t DESTADDR2;  /* Channel Destination Address 2 */
+    register8_t reserved_0x0F;
+} DMA_CH_t;
+
+
+/* DMA Controller */
+typedef struct DMA_struct
+{
+    register8_t CTRL;  /* Control */
+    register8_t reserved_0x01;
+    register8_t reserved_0x02;
+    register8_t INTFLAGS;  /* Transfer Interrupt Status */
+    register8_t STATUS;  /* Status */
+    register8_t reserved_0x05;
+    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
+    register8_t reserved_0x08;
+    register8_t reserved_0x09;
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+    register8_t reserved_0x0C;
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    DMA_CH_t CH0;  /* DMA Channel 0 */
+    DMA_CH_t CH1;  /* DMA Channel 1 */
+    DMA_CH_t CH2;  /* DMA Channel 2 */
+    DMA_CH_t CH3;  /* DMA Channel 3 */
+} DMA_t;
+
+/* Burst mode */
+typedef enum DMA_CH_BURSTLEN_enum
+{
+    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
+    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
+    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
+    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
+} DMA_CH_BURSTLEN_t;
+
+/* Destination addressing mode */
+typedef enum DMA_CH_DESTDIR_enum
+{
+    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
+    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
+    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
+} DMA_CH_DESTDIR_t;
+
+/* Destination address reload mode */
+typedef enum DMA_CH_DESTRELOAD_enum
+{
+    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
+    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
+    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
+    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
+} DMA_CH_DESTRELOAD_t;
+
+/* Interrupt level */
+typedef enum DMA_CH_ERRINTLVL_enum
+{
+    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
+    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
+    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
+    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
+} DMA_CH_ERRINTLVL_t;
+
+/* Source addressing mode */
+typedef enum DMA_CH_SRCDIR_enum
+{
+    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
+    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
+    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
+} DMA_CH_SRCDIR_t;
+
+/* Source address reload mode */
+typedef enum DMA_CH_SRCRELOAD_enum
+{
+    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
+    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
+    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
+    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
+} DMA_CH_SRCRELOAD_t;
+
+/* Transfer trigger source */
+typedef enum DMA_CH_TRIGSRC_enum
+{
+    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
+    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
+    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
+    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
+    DMA_CH_TRIGSRC_AES_gc = (0x04<<0),  /* AES */
+    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
+    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
+    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
+    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
+    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
+    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
+    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
+    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
+    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
+    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
+    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
+    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
+    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
+    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
+    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
+    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
+    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
+    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
+    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
+    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
+    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
+    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
+    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
+    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
+    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
+    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
+    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
+    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
+    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
+    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
+    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
+    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
+    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
+    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
+    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
+    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
+    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
+    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
+    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
+    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
+    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
+    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
+} DMA_CH_TRIGSRC_t;
+
+/* Interrupt level */
+typedef enum DMA_CH_TRNINTLVL_enum
+{
+    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
+    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
+    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
+    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
+} DMA_CH_TRNINTLVL_t;
+
+/* Double buffering mode */
+typedef enum DMA_DBUFMODE_enum
+{
+    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
+    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
+    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
+    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
+} DMA_DBUFMODE_t;
+
+/* Priority mode */
+typedef enum DMA_PRIMODE_enum
+{
+    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
+    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
+    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
+    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
+} DMA_PRIMODE_t;
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* EBI Chip Select Module */
+typedef struct EBI_CS_struct
+{
+    register8_t CTRLA;  /* Chip Select Control Register A */
+    register8_t CTRLB;  /* Chip Select Control Register B */
+    _WORDREGISTER(BASEADDR);  /* Base Address */
+} EBI_CS_t;
+
+
+/* External Bus Interface */
+typedef struct EBI_struct
+{
+    register8_t CTRL;  /* Control */
+    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
+    register8_t reserved_0x02;
+    register8_t reserved_0x03;
+    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
+    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
+    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
+    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+    register8_t reserved_0x0C;
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    EBI_CS_t CS0;  /* Chip Select 0 */
+    EBI_CS_t CS1;  /* Chip Select 1 */
+    EBI_CS_t CS2;  /* Chip Select 2 */
+    EBI_CS_t CS3;  /* Chip Select 3 */
+} EBI_t;
+
+/* Chip Select address size */
+typedef enum EBI_CS_ASIZE_enum
+{
+    EBI_CS_ASIZE_256B_gc = (0x00<<2),  /* 256 bytes */
+    EBI_CS_ASIZE_512B_gc = (0x01<<2),  /* 512 bytes */
+    EBI_CS_ASIZE_1KB_gc = (0x02<<2),  /* 1K bytes */
+    EBI_CS_ASIZE_2KB_gc = (0x03<<2),  /* 2K bytes */
+    EBI_CS_ASIZE_4KB_gc = (0x04<<2),  /* 4K bytes */
+    EBI_CS_ASIZE_8KB_gc = (0x05<<2),  /* 8K bytes */
+    EBI_CS_ASIZE_16KB_gc = (0x06<<2),  /* 16K bytes */
+    EBI_CS_ASIZE_32KB_gc = (0x07<<2),  /* 32K bytes */
+    EBI_CS_ASIZE_64KB_gc = (0x08<<2),  /* 64K bytes */
+    EBI_CS_ASIZE_128KB_gc = (0x09<<2),  /* 128K bytes */
+    EBI_CS_ASIZE_256KB_gc = (0x0A<<2),  /* 256K bytes */
+    EBI_CS_ASIZE_512KB_gc = (0x0B<<2),  /* 512K bytes */
+    EBI_CS_ASIZE_1MB_gc = (0x0C<<2),  /* 1M bytes */
+    EBI_CS_ASIZE_2MB_gc = (0x0D<<2),  /* 2M bytes */
+    EBI_CS_ASIZE_4MB_gc = (0x0E<<2),  /* 4M bytes */
+    EBI_CS_ASIZE_8MB_gc = (0x0F<<2),  /* 8M bytes */
+    EBI_CS_ASIZE_16M_gc = (0x10<<2),  /* 16M bytes */
+} EBI_CS_ASIZE_t;
+
+/* Legacy: Chip Select address space */
+typedef enum EBI_CS_ASPACE_enum
+{
+    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
+    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
+    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
+    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
+    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
+    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
+    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
+    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
+    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
+    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
+    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
+    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
+    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
+    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
+    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
+    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
+    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
+} EBI_CS_ASPACE_t;
+
+/* Chip Select address mode */
+typedef enum EBI_CS_MODE_enum
+{
+    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
+    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
+    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
+    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
+} EBI_CS_MODE_t;
+
+/* Chip Select SDRAM mode */
+typedef enum EBI_CS_SDMODE_enum
+{
+    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
+    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
+} EBI_CS_SDMODE_t;
+
+/* SRAM Wait State Selection */
+typedef enum EBI_CS_SRWS_enum
+{
+    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
+    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
+    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
+    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
+    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
+    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycles */
+    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
+    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
+} EBI_CS_SRWS_t;
+
+/* SDRAM Exit Self Refresh to Active Delay */
+typedef enum EBI_ESRDLY_enum
+{
+    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
+    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
+    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
+    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
+    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
+    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycles */
+    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
+    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
+} EBI_ESRDLY_t;
+
+/*  */
+typedef enum EBI_IFMODE_enum
+{
+    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
+    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
+    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
+    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
+} EBI_IFMODE_t;
+
+/*  */
+typedef enum EBI_LPCMODE_enum
+{
+    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
+    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
+} EBI_LPCMODE_t;
+
+/* SDRAM Load Mode to Active delay */
+typedef enum EBI_MRDLY_enum
+{
+    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
+    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
+    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
+    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
+} EBI_MRDLY_t;
+
+/* SDRAM Row to Column Delay */
+typedef enum EBI_ROWCOLDLY_enum
+{
+    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
+    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
+    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
+    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
+    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
+    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycles */
+    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
+    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
+} EBI_ROWCOLDLY_t;
+
+/* SDRAM Row Cycle Delay */
+typedef enum EBI_ROWCYCDLY_enum
+{
+    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
+    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
+    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
+    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
+    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
+    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycles */
+    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
+    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
+} EBI_ROWCYCDLY_t;
+
+/* SDRAM Row to Precharge Delay */
+typedef enum EBI_RPDLY_enum
+{
+    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
+    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
+    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
+    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
+    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
+    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycles */
+    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
+    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
+} EBI_RPDLY_t;
+
+/*  */
+typedef enum EBI_SDCOL_enum
+{
+    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
+    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
+    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
+    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
+} EBI_SDCOL_t;
+
+/*  */
+typedef enum EBI_SDDATAW_enum
+{
+    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
+    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
+} EBI_SDDATAW_t;
+
+/*  */
+typedef enum EBI_SRMODE_enum
+{
+    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
+    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
+    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
+    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
+} EBI_SRMODE_t;
+
+/* SDRAM Write Recovery Delay */
+typedef enum EBI_WRDLY_enum
+{
+    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
+    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
+    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
+    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
+} EBI_WRDLY_t;
+
+/*
+--------------------------------------------------------------------------
+EVSYS - Event System
+--------------------------------------------------------------------------
+*/
+
+/* Event System */
+typedef struct EVSYS_struct
+{
+    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
+    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
+    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
+    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
+    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
+    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
+    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
+    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
+    register8_t CH0CTRL;  /* Channel 0 Control Register */
+    register8_t CH1CTRL;  /* Channel 1 Control Register */
+    register8_t CH2CTRL;  /* Channel 2 Control Register */
+    register8_t CH3CTRL;  /* Channel 3 Control Register */
+    register8_t CH4CTRL;  /* Channel 4 Control Register */
+    register8_t CH5CTRL;  /* Channel 5 Control Register */
+    register8_t CH6CTRL;  /* Channel 6 Control Register */
+    register8_t CH7CTRL;  /* Channel 7 Control Register */
+    register8_t STROBE;  /* Event Strobe */
+    register8_t DATA;  /* Event Data */
+} EVSYS_t;
+
+/* Event Channel multiplexer input selection */
+typedef enum EVSYS_CHMUX_enum
+{
+    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
+    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
+    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
+    EVSYS_CHMUX_USB_gc = (0x0A<<0),  /* USB Setup, SOF, CRC error and UNF/OVF */
+    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
+    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
+    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
+    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
+    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
+    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
+    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
+    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
+    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
+    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
+    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
+    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
+    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
+    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
+    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
+    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
+    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
+    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
+    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
+    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
+    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
+    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
+    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
+    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
+    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
+    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
+    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
+    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
+    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
+    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
+    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
+    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
+    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
+    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
+    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
+    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
+    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
+    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
+    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
+    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
+    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
+    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
+    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
+    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
+    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
+    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
+    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
+    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
+    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
+    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
+    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
+    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
+    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
+    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
+    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
+    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
+    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
+    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
+    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
+    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
+    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
+    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
+    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
+    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
+    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
+    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
+    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
+    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
+    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
+    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
+    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
+    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
+    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
+    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
+    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
+    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
+    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
+    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
+    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
+    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
+    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
+    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
+    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
+    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
+    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
+    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
+    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
+    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
+    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
+    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
+    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
+    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
+    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
+    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
+    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
+    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
+    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
+    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
+    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
+    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
+    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
+    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
+    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
+    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
+    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
+    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
+    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
+    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
+    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
+    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
+    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
+    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
+    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
+    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
+    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
+    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
+    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
+    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
+} EVSYS_CHMUX_t;
+
+/* Digital filter coefficient */
+typedef enum EVSYS_DIGFILT_enum
+{
+    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
+    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
+    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
+    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
+    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
+    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
+    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
+    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
+} EVSYS_DIGFILT_t;
+
+/* Quadrature Decoder Index Recognition Mode */
+typedef enum EVSYS_QDIRM_enum
+{
+    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
+    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
+    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
+    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
+} EVSYS_QDIRM_t;
+
+/*
+--------------------------------------------------------------------------
+FUSE - Fuses and Lockbits
+--------------------------------------------------------------------------
+*/
+
+/* Fuses */
+typedef struct NVM_FUSES_struct
+{
+    register8_t FUSEBYTE0;  /* JTAG User ID */
+    register8_t FUSEBYTE1;  /* Watchdog Configuration */
+    register8_t FUSEBYTE2;  /* Reset Configuration */
+    register8_t reserved_0x03;
+    register8_t FUSEBYTE4;  /* Start-up Configuration */
+    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
+} NVM_FUSES_t;
+
+/* BOD operation */
+typedef enum BODACT_enum
+{
+    BODACT_SAMPLED_gc = (0x01<<4),  /* BOD enabled in sampled mode */
+    BODACT_CONTINUOUS_gc = (0x02<<4),  /* BOD enabled continuously */
+    BODACT_DISABLED_gc = (0x03<<4),  /* BOD Disabled */
+} BODACT_t;
+
+/* Brownout Detection Voltage Level */
+typedef enum BODLVL_enum
+{
+    BODLVL_3V0_gc = (0x00<<0),  /* 3.0 V */
+    BODLVL_2V8_gc = (0x01<<0),  /* 2.8 V */
+    BODLVL_2V6_gc = (0x02<<0),  /* 2.6 V */
+    BODLVL_2V4_gc = (0x03<<0),  /* 2.4 V */
+    BODLVL_2V2_gc = (0x04<<0),  /* 2.2 V */
+    BODLVL_2V0_gc = (0x05<<0),  /* 2.0 V */
+    BODLVL_1V8_gc = (0x06<<0),  /* 1.8 V */
+    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
+} BODLVL_t;
+
+/* BOD operation */
+typedef enum BODPD_enum
+{
+    BODPD_SAMPLED_gc = (0x01<<0),  /* BOD enabled in sampled mode */
+    BODPD_CONTINUOUS_gc = (0x02<<0),  /* BOD enabled continuously */
+    BODPD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
+} BODPD_t;
+
+/* Boot Loader Section Reset Vector */
+typedef enum BOOTRST_enum
+{
+    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
+    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
+} BOOTRST_t;
+
+/* Start-up Time */
+typedef enum STARTUPTIME_enum
+{
+    STARTUPTIME_64MS_gc = (0x00<<2),  /* 64 ms */
+    STARTUPTIME_4MS_gc = (0x01<<2),  /* 4 ms */
+    STARTUPTIME_0MS_gc = (0x03<<2),  /* 0 ms */
+} STARTUPTIME_t;
+
+/* Timer Oscillator pin location */
+typedef enum TOSCSEL_enum
+{
+    TOSCSEL_ALTERNATE_gc = (0x00<<5),  /* TOSC1 / TOSC2 on separate pins */
+    TOSCSEL_XTAL_gc = (0x01<<5),  /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
+} TOSCSEL_t;
+
+/* Watchdog (Window) Timeout Period */
+typedef enum WDPER_enum
+{
+    WDPER_8CLK_gc = (0x00<<0),  /* 8 cycles (8ms @ 3.3V) */
+    WDPER_16CLK_gc = (0x01<<0),  /* 16 cycles (16ms @ 3.3V) */
+    WDPER_32CLK_gc = (0x02<<0),  /* 32 cycles (32ms @ 3.3V) */
+    WDPER_64CLK_gc = (0x03<<0),  /* 64 cycles (64ms @ 3.3V) */
+    WDPER_128CLK_gc = (0x04<<0),  /* 128 cycles (0.125s @ 3.3V) */
+    WDPER_256CLK_gc = (0x05<<0),  /* 256 cycles (0.25s @ 3.3V) */
+    WDPER_512CLK_gc = (0x06<<0),  /* 512 cycles (0.5s @ 3.3V) */
+    WDPER_1KCLK_gc = (0x07<<0),  /* 1K cycles (1s @ 3.3V) */
+    WDPER_2KCLK_gc = (0x08<<0),  /* 2K cycles (2s @ 3.3V) */
+    WDPER_4KCLK_gc = (0x09<<0),  /* 4K cycles (4s @ 3.3V) */
+    WDPER_8KCLK_gc = (0x0A<<0),  /* 8K cycles (8s @ 3.3V) */
+} WDPER_t;
+
+/* Watchdog (Window) Timeout Period */
+typedef enum WDWPER_enum
+{
+    WDWPER_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
+    WDWPER_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
+    WDWPER_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
+    WDWPER_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
+    WDWPER_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
+    WDWPER_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
+    WDWPER_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
+    WDWPER_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
+    WDWPER_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
+    WDWPER_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
+    WDWPER_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
+} WDWPER_t;
+
+/*
+--------------------------------------------------------------------------
+HIRES - Timer/Counter High-Resolution Extension
+--------------------------------------------------------------------------
+*/
+
+/* High-Resolution Extension */
+typedef struct HIRES_struct
+{
+    register8_t CTRLA;  /* Control Register */
+} HIRES_t;
+
+/* High Resolution Enable */
+typedef enum HIRES_HREN_enum
+{
+    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
+    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
+    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
+    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
+} HIRES_HREN_t;
+
+/*
+--------------------------------------------------------------------------
+IRCOM - IR Communication Module
+--------------------------------------------------------------------------
+*/
+
+/* IR Communication Module */
+typedef struct IRCOM_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
+    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
+} IRCOM_t;
+
+/* Event channel selection */
+typedef enum IRCOM_EVSEL_enum
+{
+    IRCOM_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
+    IRCOM_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
+    IRCOM_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
+    IRCOM_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
+    IRCOM_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
+    IRCOM_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
+    IRCOM_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
+    IRCOM_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
+    IRCOM_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
+} IRCOM_EVSEL_t;
+
+/*
+--------------------------------------------------------------------------
+LOCKBIT - Fuses and Lockbits
+--------------------------------------------------------------------------
+*/
+
+/* Lock Bits */
+typedef struct NVM_LOCKBITS_struct
+{
+    register8_t LOCK_BITS;  /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */
+} NVM_LOCKBITS_t;
+
+/* Boot lock bits - application section */
+typedef enum BLBA_enum
+{
+    BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
+    BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
+    BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
+    BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
+} BLBA_t;
+
+/* Boot lock bits - application table section */
+typedef enum BLBAT_enum
+{
+    BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
+    BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
+    BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
+    BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
+} BLBAT_t;
+
+/* Boot lock bits - boot section */
+typedef enum BLBB_enum
+{
+    BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
+    BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
+    BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
+    BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
+} BLBB_t;
+
+/* Lock bits */
+typedef enum LB_enum
+{
+    LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
+    LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
+    LB_NOLOCK_gc = (0x03<<0),  /* No locks */
+} LB_t;
+
+/*
+--------------------------------------------------------------------------
+MCU - MCU Control
+--------------------------------------------------------------------------
+*/
+
+/* MCU Control */
+typedef struct MCU_struct
+{
+    register8_t DEVID0;  /* Device ID byte 0 */
+    register8_t DEVID1;  /* Device ID byte 1 */
+    register8_t DEVID2;  /* Device ID byte 2 */
+    register8_t REVID;  /* Revision ID */
+    register8_t JTAGUID;  /* JTAG User ID */
+    register8_t reserved_0x05;
+    register8_t MCUCR;  /* MCU Control */
+    register8_t ANAINIT;  /* Analog Startup Delay */
+    register8_t EVSYSLOCK;  /* Event System Lock */
+    register8_t AWEXLOCK;  /* AWEX Lock */
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+} MCU_t;
+
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Non-volatile Memory Controller */
+typedef struct NVM_struct
+{
+    register8_t ADDR0;  /* Address Register 0 */
+    register8_t ADDR1;  /* Address Register 1 */
+    register8_t ADDR2;  /* Address Register 2 */
+    register8_t reserved_0x03;
+    register8_t DATA0;  /* Data Register 0 */
+    register8_t DATA1;  /* Data Register 1 */
+    register8_t DATA2;  /* Data Register 2 */
+    register8_t reserved_0x07;
+    register8_t reserved_0x08;
+    register8_t reserved_0x09;
+    register8_t CMD;  /* Command */
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t INTCTRL;  /* Interrupt Control */
+    register8_t reserved_0x0E;
+    register8_t STATUS;  /* Status */
+    register8_t LOCK_BITS;  /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */
+} NVM_t;
+
+/* Boot lock bits - application section */
+typedef enum NVM_BLBA_enum
+{
+    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
+    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
+    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
+    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
+} NVM_BLBA_t;
+
+/* Boot lock bits - application table section */
+typedef enum NVM_BLBAT_enum
+{
+    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
+    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
+    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
+    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
+} NVM_BLBAT_t;
+
+/* Boot lock bits - boot section */
+typedef enum NVM_BLBB_enum
+{
+    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
+    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
+    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
+    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
+} NVM_BLBB_t;
+
+/* NVM Command */
+typedef enum NVM_CMD_enum
+{
+    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
+    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
+    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
+    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
+    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
+    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
+    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
+    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
+    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
+    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
+    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
+    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
+    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
+    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
+    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
+    NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0),  /* Erase Flash Page */
+    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
+    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
+    NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0),  /* Write Flash Page */
+    NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0),  /* Erase-and-write Flash Page */
+    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
+    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
+    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
+    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
+    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
+    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
+    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Application section CRC */
+    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /*  Boot Section CRC */
+    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Flash Range CRC */
+    NVM_CMD_CHIP_ERASE_gc = (0x40<<0),  /* Erase Chip */
+    NVM_CMD_READ_NVM_gc = (0x43<<0),  /* Read NVM */
+    NVM_CMD_WRITE_FUSE_gc = (0x4C<<0),  /* Write Fuse byte */
+    NVM_CMD_ERASE_BOOT_gc = (0x68<<0),  /* Erase Boot Section */
+    NVM_CMD_FLASH_CRC_gc = (0x78<<0),  /* Flash CRC */
+} NVM_CMD_t;
+
+/* EEPROM ready interrupt level */
+typedef enum NVM_EELVL_enum
+{
+    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
+    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
+    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
+    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
+} NVM_EELVL_t;
+
+/* Lock bits */
+typedef enum NVM_LB_enum
+{
+    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
+    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
+    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
+} NVM_LB_t;
+
+/* SPM ready interrupt level */
+typedef enum NVM_SPMLVL_enum
+{
+    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
+    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
+    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
+    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
+} NVM_SPMLVL_t;
+
+/*
+--------------------------------------------------------------------------
+OSC - Oscillator
+--------------------------------------------------------------------------
+*/
+
+/* Oscillator */
+typedef struct OSC_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t XOSCCTRL;  /* External Oscillator Control Register */
+    register8_t XOSCFAIL;  /* Oscillator Failure Detection Register */
+    register8_t RC32KCAL;  /* 32.768 kHz Internal Oscillator Calibration Register */
+    register8_t PLLCTRL;  /* PLL Control Register */
+    register8_t DFLLCTRL;  /* DFLL Control Register */
+} OSC_t;
+
+/* Oscillator Frequency Range */
+typedef enum OSC_FRQRANGE_enum
+{
+    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
+    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
+    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
+    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
+} OSC_FRQRANGE_t;
+
+/* PLL Clock Source */
+typedef enum OSC_PLLSRC_enum
+{
+    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2 MHz RC Oscillator */
+    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32 MHz RC Oscillator */
+    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
+} OSC_PLLSRC_t;
+
+/* 2 MHz DFLL Calibration Reference */
+typedef enum OSC_RC2MCREF_enum
+{
+    OSC_RC2MCREF_RC32K_gc = (0x00<<0),  /* Internal 32.768 kHz RC Oscillator */
+    OSC_RC2MCREF_XOSC32K_gc = (0x01<<0),  /* External 32.768 kHz Crystal Oscillator */
+} OSC_RC2MCREF_t;
+
+/* 32 MHz DFLL Calibration Reference */
+typedef enum OSC_RC32MCREF_enum
+{
+    OSC_RC32MCREF_RC32K_gc = (0x00<<1),  /* Internal 32.768 kHz RC Oscillator */
+    OSC_RC32MCREF_XOSC32K_gc = (0x01<<1),  /* External 32.768 kHz Crystal Oscillator */
+    OSC_RC32MCREF_USBSOF_gc = (0x02<<1),  /* USB Start of Frame */
+} OSC_RC32MCREF_t;
+
+/* External Oscillator Selection and Startup Time */
+typedef enum OSC_XOSCSEL_enum
+{
+    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
+    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32.768 kHz TOSC - 32K CLK */
+    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16 MHz XTAL - 256 CLK */
+    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16 MHz XTAL - 1K CLK */
+    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16 MHz XTAL - 16K CLK */
+} OSC_XOSCSEL_t;
+
+/*
+--------------------------------------------------------------------------
+PMIC - Programmable Multi-level Interrupt Controller
+--------------------------------------------------------------------------
+*/
+
+/* Programmable Multi-level Interrupt Controller */
+typedef struct PMIC_struct
+{
+    register8_t STATUS;  /* Status Register */
+    register8_t INTPRI;  /* Interrupt Priority */
+    register8_t CTRL;  /* Control Register */
+    register8_t reserved_0x03;
+    register8_t reserved_0x04;
+    register8_t reserved_0x05;
+    register8_t reserved_0x06;
+    register8_t reserved_0x07;
+    register8_t reserved_0x08;
+    register8_t reserved_0x09;
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+    register8_t reserved_0x0C;
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+} PMIC_t;
+
+
+/*
+--------------------------------------------------------------------------
+PORT - I/O Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O Ports */
+typedef struct PORT_struct
+{
+    register8_t DIR;  /* I/O Port Data Direction */
+    register8_t DIRSET;  /* I/O Port Data Direction Set */
+    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
+    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
+    register8_t OUT;  /* I/O Port Output */
+    register8_t OUTSET;  /* I/O Port Output Set */
+    register8_t OUTCLR;  /* I/O Port Output Clear */
+    register8_t OUTTGL;  /* I/O Port Output Toggle */
+    register8_t IN;  /* I/O port Input */
+    register8_t INTCTRL;  /* Interrupt Control Register */
+    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
+    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
+    register8_t INTFLAGS;  /* Interrupt Flag Register */
+    register8_t reserved_0x0D;
+    register8_t REMAP;  /* I/O Port Pin Remap Register */
+    register8_t reserved_0x0F;
+    register8_t PIN0CTRL;  /* Pin 0 Control Register */
+    register8_t PIN1CTRL;  /* Pin 1 Control Register */
+    register8_t PIN2CTRL;  /* Pin 2 Control Register */
+    register8_t PIN3CTRL;  /* Pin 3 Control Register */
+    register8_t PIN4CTRL;  /* Pin 4 Control Register */
+    register8_t PIN5CTRL;  /* Pin 5 Control Register */
+    register8_t PIN6CTRL;  /* Pin 6 Control Register */
+    register8_t PIN7CTRL;  /* Pin 7 Control Register */
+} PORT_t;
+
+/* Port Interrupt 0 Level */
+typedef enum PORT_INT0LVL_enum
+{
+    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
+    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
+    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
+} PORT_INT0LVL_t;
+
+/* Port Interrupt 1 Level */
+typedef enum PORT_INT1LVL_enum
+{
+    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
+    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
+    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
+} PORT_INT1LVL_t;
+
+/* Input/Sense Configuration */
+typedef enum PORT_ISC_enum
+{
+    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
+    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
+    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
+    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
+    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
+} PORT_ISC_t;
+
+/* Output/Pull Configuration */
+typedef enum PORT_OPC_enum
+{
+    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
+    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
+    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
+    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
+    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
+    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
+    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
+    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
+} PORT_OPC_t;
+
+/*
+--------------------------------------------------------------------------
+PORTCFG - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O port Configuration */
+typedef struct PORTCFG_struct
+{
+    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
+    register8_t reserved_0x01;
+    register8_t VPCTRLA;  /* Virtual Port Control Register A */
+    register8_t VPCTRLB;  /* Virtual Port Control Register B */
+    register8_t CLKEVOUT;  /* Clock and Event Out Register */
+    register8_t EBIOUT;  /* EBI Output register */
+    register8_t EVOUTSEL;  /* Event Output Select */
+} PORTCFG_t;
+
+/* Clock and Event Output Port */
+typedef enum PORTCFG_CLKEVPIN_enum
+{
+    PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7),  /* Clock and Event Output on PIN 7 */
+    PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7),  /* Clock and Event Output on PIN 4 */
+} PORTCFG_CLKEVPIN_t;
+
+/* System Clock Output Port */
+typedef enum PORTCFG_CLKOUT_enum
+{
+    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* System Clock Output Disabled */
+    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* System Clock Output on Port C pin 7 */
+    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* System Clock Output on Port D pin 7 */
+    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* System Clock Output on Port E pin 7 */
+} PORTCFG_CLKOUT_t;
+
+/* Peripheral Clock Output Select */
+typedef enum PORTCFG_CLKOUTSEL_enum
+{
+    PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2),  /* 1x Peripheral Clock Output to pin */
+    PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2),  /* 2x Peripheral Clock Output to pin */
+    PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2),  /* 4x Peripheral Clock Output to pin */
+} PORTCFG_CLKOUTSEL_t;
+
+/* EBI Address Output Port */
+typedef enum PORTCFG_EBIADROUT_enum
+{
+    PORTCFG_EBIADROUT_PF_gc = (0x00<<2),  /* EBI port 3 address output on PORTF pins 0 to 7 */
+    PORTCFG_EBIADROUT_PE_gc = (0x01<<2),  /* EBI port 3 address output on PORTE pins 0 to 7 */
+    PORTCFG_EBIADROUT_PFH_gc = (0x02<<2),  /* EBI port 3 address output on PORTF pins 4 to 7 */
+    PORTCFG_EBIADROUT_PEH_gc = (0x03<<2),  /* EBI port 3 address output on PORTE pins 4 to 7 */
+} PORTCFG_EBIADROUT_t;
+
+/* EBI Chip Select Output Port */
+typedef enum PORTCFG_EBICSOUT_enum
+{
+    PORTCFG_EBICSOUT_PH_gc = (0x00<<0),  /* EBI chip select output to PORTH pin 4 to 7 */
+    PORTCFG_EBICSOUT_PL_gc = (0x01<<0),  /* EBI chip select output to PORTL pin 4 to 7 */
+    PORTCFG_EBICSOUT_PF_gc = (0x02<<0),  /* EBI chip select output to PORTF pin 4 to 7 */
+    PORTCFG_EBICSOUT_PE_gc = (0x03<<0),  /* EBI chip select output to PORTE pin 4 to 7 */
+} PORTCFG_EBICSOUT_t;
+
+/* Event Output Port */
+typedef enum PORTCFG_EVOUT_enum
+{
+    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
+    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
+    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
+    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
+} PORTCFG_EVOUT_t;
+
+/* Event Output Select */
+typedef enum PORTCFG_EVOUTSEL_enum
+{
+    PORTCFG_EVOUTSEL_0_gc = (0x00<<0),  /* Event Channel 0 output to pin */
+    PORTCFG_EVOUTSEL_1_gc = (0x01<<0),  /* Event Channel 1 output to pin */
+    PORTCFG_EVOUTSEL_2_gc = (0x02<<0),  /* Event Channel 2 output to pin */
+    PORTCFG_EVOUTSEL_3_gc = (0x03<<0),  /* Event Channel 3 output to pin */
+    PORTCFG_EVOUTSEL_4_gc = (0x04<<0),  /* Event Channel 4 output to pin */
+    PORTCFG_EVOUTSEL_5_gc = (0x05<<0),  /* Event Channel 5 output to pin */
+    PORTCFG_EVOUTSEL_6_gc = (0x06<<0),  /* Event Channel 6 output to pin */
+    PORTCFG_EVOUTSEL_7_gc = (0x07<<0),  /* Event Channel 7 output to pin */
+} PORTCFG_EVOUTSEL_t;
+
+/* Virtual Port Mapping */
+typedef enum PORTCFG_VP0MAP_enum
+{
+    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
+    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
+    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
+    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
+    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
+    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
+    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
+    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
+    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
+    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
+    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
+    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
+    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
+    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
+    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
+    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
+
+    /* Deprecated aliases */
+    PORTCFG_VP02MAP_PORTA_gc = (0x00<<0),  /* Deprecated Mapped To PORTA */
+    PORTCFG_VP02MAP_PORTB_gc = (0x01<<0),  /* Deprecated Mapped To PORTB */
+    PORTCFG_VP02MAP_PORTC_gc = (0x02<<0),  /* Deprecated Mapped To PORTC */
+    PORTCFG_VP02MAP_PORTD_gc = (0x03<<0),  /* Deprecated Mapped To PORTD */
+    PORTCFG_VP02MAP_PORTE_gc = (0x04<<0),  /* Deprecated Mapped To PORTE */
+    PORTCFG_VP02MAP_PORTF_gc = (0x05<<0),  /* Deprecated Mapped To PORTF */
+    PORTCFG_VP02MAP_PORTG_gc = (0x06<<0),  /* Deprecated Mapped To PORTG */
+    PORTCFG_VP02MAP_PORTH_gc = (0x07<<0),  /* Deprecated Mapped To PORTH */
+    PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0),  /* Deprecated Mapped To PORTJ */
+    PORTCFG_VP02MAP_PORTK_gc = (0x09<<0),  /* Deprecated Mapped To PORTK */
+    PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0),  /* Deprecated Mapped To PORTL */
+    PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0),  /* Deprecated Mapped To PORTM */
+    PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0),  /* Deprecated Mapped To PORTN */
+    PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0),  /* Deprecated Mapped To PORTP */
+    PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0),  /* Deprecated Mapped To PORTQ */
+    PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0),  /* Deprecated Mapped To PORTR */
+} PORTCFG_VP0MAP_t;
+
+/* Deprecated type definition */
+typedef enum PORTCFG_VP0MAP_enum PORTCFG_VP02MAP_t;
+
+/* Virtual Port Mapping */
+typedef enum PORTCFG_VP1MAP_enum
+{
+    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
+    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
+    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
+    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
+    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
+    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
+    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
+    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
+    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
+    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
+    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
+    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
+    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
+    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
+    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
+    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
+
+    /* Deprecated aliases */
+    PORTCFG_VP13MAP_PORTA_gc = (0x00<<4),  /* Deprecated Mapped To PORTA */
+    PORTCFG_VP13MAP_PORTB_gc = (0x01<<4),  /* Deprecated Mapped To PORTB */
+    PORTCFG_VP13MAP_PORTC_gc = (0x02<<4),  /* Deprecated Mapped To PORTC */
+    PORTCFG_VP13MAP_PORTD_gc = (0x03<<4),  /* Deprecated Mapped To PORTD */
+    PORTCFG_VP13MAP_PORTE_gc = (0x04<<4),  /* Deprecated Mapped To PORTE */
+    PORTCFG_VP13MAP_PORTF_gc = (0x05<<4),  /* Deprecated Mapped To PORTF */
+    PORTCFG_VP13MAP_PORTG_gc = (0x06<<4),  /* Deprecated Mapped To PORTG */
+    PORTCFG_VP13MAP_PORTH_gc = (0x07<<4),  /* Deprecated Mapped To PORTH */
+    PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4),  /* Deprecated Mapped To PORTJ */
+    PORTCFG_VP13MAP_PORTK_gc = (0x09<<4),  /* Deprecated Mapped To PORTK */
+    PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4),  /* Deprecated Mapped To PORTL */
+    PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4),  /* Deprecated Mapped To PORTM */
+    PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4),  /* Deprecated Mapped To PORTN */
+    PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4),  /* Deprecated Mapped To PORTP */
+    PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4),  /* Deprecated Mapped To PORTQ */
+    PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4),  /* Deprecated Mapped To PORTR */
+} PORTCFG_VP1MAP_t;
+
+/* Deprecated type definition */
+typedef enum PORTCFG_VP1MAP_enum PORTCFG_VP13MAP_t;
+
+/* Virtual Port Mapping */
+typedef enum PORTCFG_VP2MAP_enum
+{
+    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
+    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
+    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
+    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
+    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
+    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
+    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
+    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
+    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
+    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
+    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
+    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
+    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
+    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
+    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
+    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
+} PORTCFG_VP2MAP_t;
+
+/* Virtual Port Mapping */
+typedef enum PORTCFG_VP3MAP_enum
+{
+    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
+    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
+    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
+    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
+    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
+    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
+    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
+    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
+    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
+    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
+    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
+    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
+    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
+    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
+    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
+    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
+} PORTCFG_VP3MAP_t;
+
+/*
+--------------------------------------------------------------------------
+PR - Power Reduction
+--------------------------------------------------------------------------
+*/
+
+/* Power Reduction */
+typedef struct PR_struct
+{
+    register8_t PRGEN;  /* General Power Reduction */
+    register8_t PRPA;  /* Power Reduction Port A */
+    register8_t PRPB;  /* Power Reduction Port B */
+    register8_t PRPC;  /* Power Reduction Port C */
+    register8_t PRPD;  /* Power Reduction Port D */
+    register8_t PRPE;  /* Power Reduction Port E */
+    register8_t PRPF;  /* Power Reduction Port F */
+} PR_t;
+
+
+/*
+--------------------------------------------------------------------------
+RST - Reset
+--------------------------------------------------------------------------
+*/
+
+/* Reset */
+typedef struct RST_struct
+{
+    register8_t STATUS;  /* Status Register */
+    register8_t CTRL;  /* Control Register */
+} RST_t;
+
+
+/*
+--------------------------------------------------------------------------
+RTC - Real-Time Counter
+--------------------------------------------------------------------------
+*/
+
+/* Real-Time Counter */
+typedef struct RTC_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t INTCTRL;  /* Interrupt Control Register */
+    register8_t INTFLAGS;  /* Interrupt Flags */
+    register8_t TEMP;  /* Temporary register */
+    register8_t reserved_0x05;
+    register8_t reserved_0x06;
+    register8_t reserved_0x07;
+    _WORDREGISTER(CNT);  /* Count Register */
+    _WORDREGISTER(PER);  /* Period Register */
+    _WORDREGISTER(COMP);  /* Compare Register */
+} RTC_t;
+
+/* Compare Interrupt level */
+typedef enum RTC_COMPINTLVL_enum
+{
+    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} RTC_COMPINTLVL_t;
+
+/* Overflow Interrupt level */
+typedef enum RTC_OVFINTLVL_enum
+{
+    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} RTC_OVFINTLVL_t;
+
+/* Prescaler Factor */
+typedef enum RTC_PRESCALER_enum
+{
+    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
+    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
+    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
+    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
+    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
+    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
+    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
+    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
+} RTC_PRESCALER_t;
+
+/*
+--------------------------------------------------------------------------
+SIGROW - Signature Row
+--------------------------------------------------------------------------
+*/
+
+/* Production Signatures */
+typedef struct NVM_PROD_SIGNATURES_struct
+{
+    register8_t RCOSC2M;  /* RCOSC 2 MHz Calibration Value B */
+    register8_t RCOSC2MA;  /* RCOSC 2 MHz Calibration Value A */
+    register8_t RCOSC32K;  /* RCOSC 32.768 kHz Calibration Value */
+    register8_t RCOSC32M;  /* RCOSC 32 MHz Calibration Value B */
+    register8_t RCOSC32MA;  /* RCOSC 32 MHz Calibration Value A */
+    register8_t reserved_0x05;
+    register8_t reserved_0x06;
+    register8_t reserved_0x07;
+    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
+    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
+    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
+    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
+    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
+    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    register8_t WAFNUM;  /* Wafer Number */
+    register8_t reserved_0x11;
+    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
+    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
+    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
+    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    register8_t reserved_0x18;
+    register8_t reserved_0x19;
+    register8_t USBCAL0;  /* USB Calibration Byte 0 */
+    register8_t USBCAL1;  /* USB Calibration Byte 1 */
+    register8_t USBRCOSC;  /* USB RCOSC Calibration Value B */
+    register8_t USBRCOSCA;  /* USB RCOSC Calibration Value A */
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
+    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
+    register8_t reserved_0x22;
+    register8_t reserved_0x23;
+    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
+    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
+    register8_t reserved_0x26;
+    register8_t reserved_0x27;
+    register8_t reserved_0x28;
+    register8_t reserved_0x29;
+    register8_t reserved_0x2A;
+    register8_t reserved_0x2B;
+    register8_t reserved_0x2C;
+    register8_t reserved_0x2D;
+    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
+    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 1 */
+    register8_t DACA0OFFCAL;  /* DACA0 Calibration Byte 0 */
+    register8_t DACA0GAINCAL;  /* DACA0 Calibration Byte 1 */
+    register8_t DACB0OFFCAL;  /* DACB0 Calibration Byte 0 */
+    register8_t DACB0GAINCAL;  /* DACB0 Calibration Byte 1 */
+    register8_t DACA1OFFCAL;  /* DACA1 Calibration Byte 0 */
+    register8_t DACA1GAINCAL;  /* DACA1 Calibration Byte 1 */
+    register8_t DACB1OFFCAL;  /* DACB1 Calibration Byte 0 */
+    register8_t DACB1GAINCAL;  /* DACB1 Calibration Byte 1 */
+    register8_t reserved_0x38;
+    register8_t reserved_0x39;
+    register8_t reserved_0x3A;
+    register8_t reserved_0x3B;
+    register8_t reserved_0x3C;
+    register8_t reserved_0x3D;
+    register8_t reserved_0x3E;
+    register8_t reserved_0x3F;
+    register8_t reserved_0x40;
+    register8_t reserved_0x41;
+    register8_t reserved_0x42;
+    register8_t reserved_0x43;
+    register8_t reserved_0x44;
+    register8_t reserved_0x45;
+    register8_t reserved_0x46;
+    register8_t reserved_0x47;
+} NVM_PROD_SIGNATURES_t;
+
+
+/*
+--------------------------------------------------------------------------
+SLEEP - Sleep Controller
+--------------------------------------------------------------------------
+*/
+
+/* Sleep Controller */
+typedef struct SLEEP_struct
+{
+    register8_t CTRL;  /* Control Register */
+} SLEEP_t;
+
+/* Sleep Mode */
+typedef enum SLEEP_SMODE_enum
+{
+    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
+    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
+    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
+    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
+    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
+} SLEEP_SMODE_t;
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+/*
+--------------------------------------------------------------------------
+SPI - Serial Peripheral Interface
+--------------------------------------------------------------------------
+*/
+
+/* Serial Peripheral Interface */
+typedef struct SPI_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t INTCTRL;  /* Interrupt Control Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t DATA;  /* Data Register */
+} SPI_t;
+
+/* Interrupt level */
+typedef enum SPI_INTLVL_enum
+{
+    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
+} SPI_INTLVL_t;
+
+/* SPI Mode */
+typedef enum SPI_MODE_enum
+{
+    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
+    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
+    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
+    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
+} SPI_MODE_t;
+
+/* Prescaler setting */
+typedef enum SPI_PRESCALER_enum
+{
+    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
+    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
+    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
+    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
+} SPI_PRESCALER_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 0 */
+typedef struct TC0_struct
+{
+    register8_t CTRLA;  /* Control  Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control register C */
+    register8_t CTRLD;  /* Control Register D */
+    register8_t CTRLE;  /* Control Register E */
+    register8_t reserved_0x05;
+    register8_t INTCTRLA;  /* Interrupt Control Register A */
+    register8_t INTCTRLB;  /* Interrupt Control Register B */
+    register8_t CTRLFCLR;  /* Control Register F Clear */
+    register8_t CTRLFSET;  /* Control Register F Set */
+    register8_t CTRLGCLR;  /* Control Register G Clear */
+    register8_t CTRLGSET;  /* Control Register G Set */
+    register8_t INTFLAGS;  /* Interrupt Flag Register */
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t TEMP;  /* Temporary Register For 16-bit Access */
+    register8_t reserved_0x10;
+    register8_t reserved_0x11;
+    register8_t reserved_0x12;
+    register8_t reserved_0x13;
+    register8_t reserved_0x14;
+    register8_t reserved_0x15;
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    register8_t reserved_0x18;
+    register8_t reserved_0x19;
+    register8_t reserved_0x1A;
+    register8_t reserved_0x1B;
+    register8_t reserved_0x1C;
+    register8_t reserved_0x1D;
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    _WORDREGISTER(CNT);  /* Count */
+    register8_t reserved_0x22;
+    register8_t reserved_0x23;
+    register8_t reserved_0x24;
+    register8_t reserved_0x25;
+    _WORDREGISTER(PER);  /* Period */
+    _WORDREGISTER(CCA);  /* Compare or Capture A */
+    _WORDREGISTER(CCB);  /* Compare or Capture B */
+    _WORDREGISTER(CCC);  /* Compare or Capture C */
+    _WORDREGISTER(CCD);  /* Compare or Capture D */
+    register8_t reserved_0x30;
+    register8_t reserved_0x31;
+    register8_t reserved_0x32;
+    register8_t reserved_0x33;
+    register8_t reserved_0x34;
+    register8_t reserved_0x35;
+    _WORDREGISTER(PERBUF);  /* Period Buffer */
+    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
+    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
+    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
+    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
+} TC0_t;
+
+
+/* 16-bit Timer/Counter 1 */
+typedef struct TC1_struct
+{
+    register8_t CTRLA;  /* Control  Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control register C */
+    register8_t CTRLD;  /* Control Register D */
+    register8_t CTRLE;  /* Control Register E */
+    register8_t reserved_0x05;
+    register8_t INTCTRLA;  /* Interrupt Control Register A */
+    register8_t INTCTRLB;  /* Interrupt Control Register B */
+    register8_t CTRLFCLR;  /* Control Register F Clear */
+    register8_t CTRLFSET;  /* Control Register F Set */
+    register8_t CTRLGCLR;  /* Control Register G Clear */
+    register8_t CTRLGSET;  /* Control Register G Set */
+    register8_t INTFLAGS;  /* Interrupt Flag Register */
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t TEMP;  /* Temporary Register For 16-bit Access */
+    register8_t reserved_0x10;
+    register8_t reserved_0x11;
+    register8_t reserved_0x12;
+    register8_t reserved_0x13;
+    register8_t reserved_0x14;
+    register8_t reserved_0x15;
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    register8_t reserved_0x18;
+    register8_t reserved_0x19;
+    register8_t reserved_0x1A;
+    register8_t reserved_0x1B;
+    register8_t reserved_0x1C;
+    register8_t reserved_0x1D;
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    _WORDREGISTER(CNT);  /* Count */
+    register8_t reserved_0x22;
+    register8_t reserved_0x23;
+    register8_t reserved_0x24;
+    register8_t reserved_0x25;
+    _WORDREGISTER(PER);  /* Period */
+    _WORDREGISTER(CCA);  /* Compare or Capture A */
+    _WORDREGISTER(CCB);  /* Compare or Capture B */
+    register8_t reserved_0x2C;
+    register8_t reserved_0x2D;
+    register8_t reserved_0x2E;
+    register8_t reserved_0x2F;
+    register8_t reserved_0x30;
+    register8_t reserved_0x31;
+    register8_t reserved_0x32;
+    register8_t reserved_0x33;
+    register8_t reserved_0x34;
+    register8_t reserved_0x35;
+    _WORDREGISTER(PERBUF);  /* Period Buffer */
+    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
+    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
+} TC1_t;
+
+/* Byte Mode */
+typedef enum TC_BYTEM_enum
+{
+    TC_BYTEM_NORMAL_gc = (0x00<<0),  /* 16-bit mode */
+    TC_BYTEM_BYTEMODE_gc = (0x01<<0),  /* Timer/Counter operating in byte mode only */
+    TC_BYTEM_SPLITMODE_gc = (0x02<<0),  /* Timer/Counter split into two 8-bit Counters (TC2) */
+} TC_BYTEM_t;
+
+/* Compare or Capture A Interrupt Level */
+typedef enum TC_CCAINTLVL_enum
+{
+    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} TC_CCAINTLVL_t;
+
+/* Compare or Capture B Interrupt Level */
+typedef enum TC_CCBINTLVL_enum
+{
+    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} TC_CCBINTLVL_t;
+
+/* Compare or Capture C Interrupt Level */
+typedef enum TC_CCCINTLVL_enum
+{
+    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
+    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
+    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
+    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
+} TC_CCCINTLVL_t;
+
+/* Compare or Capture D Interrupt Level */
+typedef enum TC_CCDINTLVL_enum
+{
+    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
+    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
+    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
+    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
+} TC_CCDINTLVL_t;
+
+/* Clock Selection */
+typedef enum TC_CLKSEL_enum
+{
+    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
+    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
+    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
+    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
+    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
+    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
+    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
+    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
+    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
+    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
+    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
+    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
+    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
+    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
+    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
+    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
+} TC_CLKSEL_t;
+
+/* Timer/Counter Command */
+typedef enum TC_CMD_enum
+{
+    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
+    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
+    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
+    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
+} TC_CMD_t;
+
+/* Error Interrupt Level */
+typedef enum TC_ERRINTLVL_enum
+{
+    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} TC_ERRINTLVL_t;
+
+/* Event Action */
+typedef enum TC_EVACT_enum
+{
+    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
+    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
+    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
+    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
+    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
+    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
+    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
+} TC_EVACT_t;
+
+/* Event Selection */
+typedef enum TC_EVSEL_enum
+{
+    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
+    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
+    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
+    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
+    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
+    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
+    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
+    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
+    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
+} TC_EVSEL_t;
+
+/* Overflow Interrupt Level */
+typedef enum TC_OVFINTLVL_enum
+{
+    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} TC_OVFINTLVL_t;
+
+/* Waveform Generation Mode */
+typedef enum TC_WGMODE_enum
+{
+    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
+    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
+    TC_WGMODE_SINGLESLOPE_gc = (0x03<<0),  /* Single Slope */
+    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
+    TC_WGMODE_DSTOP_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
+    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
+    TC_WGMODE_DSBOTH_gc = (0x06<<0),  /* Dual Slope, Update on both TOP and BOTTOM */
+    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on both TOP and BOTTOM */
+    TC_WGMODE_DSBOTTOM_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
+    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
+} TC_WGMODE_t;
+
+/*
+--------------------------------------------------------------------------
+TC2 - 16-bit Timer/Counter type 2
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter type 2 */
+typedef struct TC2_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control register C */
+    register8_t reserved_0x03;
+    register8_t CTRLE;  /* Control Register E */
+    register8_t reserved_0x05;
+    register8_t INTCTRLA;  /* Interrupt Control Register A */
+    register8_t INTCTRLB;  /* Interrupt Control Register B */
+    register8_t reserved_0x08;
+    register8_t CTRLF;  /* Control Register F */
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+    register8_t INTFLAGS;  /* Interrupt Flag Register */
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    register8_t reserved_0x10;
+    register8_t reserved_0x11;
+    register8_t reserved_0x12;
+    register8_t reserved_0x13;
+    register8_t reserved_0x14;
+    register8_t reserved_0x15;
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    register8_t reserved_0x18;
+    register8_t reserved_0x19;
+    register8_t reserved_0x1A;
+    register8_t reserved_0x1B;
+    register8_t reserved_0x1C;
+    register8_t reserved_0x1D;
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    register8_t LCNT;  /* Low Byte Count */
+    register8_t HCNT;  /* High Byte Count */
+    register8_t reserved_0x22;
+    register8_t reserved_0x23;
+    register8_t reserved_0x24;
+    register8_t reserved_0x25;
+    register8_t LPER;  /* Low Byte Period */
+    register8_t HPER;  /* High Byte Period */
+    register8_t LCMPA;  /* Low Byte Compare A */
+    register8_t HCMPA;  /* High Byte Compare A */
+    register8_t LCMPB;  /* Low Byte Compare B */
+    register8_t HCMPB;  /* High Byte Compare B */
+    register8_t LCMPC;  /* Low Byte Compare C */
+    register8_t HCMPC;  /* High Byte Compare C */
+    register8_t LCMPD;  /* Low Byte Compare D */
+    register8_t HCMPD;  /* High Byte Compare D */
+} TC2_t;
+
+/* Byte Mode */
+typedef enum TC2_BYTEM_enum
+{
+    TC2_BYTEM_NORMAL_gc = (0x00<<0),  /* 16-bit mode */
+    TC2_BYTEM_BYTEMODE_gc = (0x01<<0),  /* Timer/Counter operating in byte mode only (TC2) */
+    TC2_BYTEM_SPLITMODE_gc = (0x02<<0),  /* Timer/Counter split into two 8-bit Counters */
+} TC2_BYTEM_t;
+
+/* Clock Selection */
+typedef enum TC2_CLKSEL_enum
+{
+    TC2_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
+    TC2_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
+    TC2_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
+    TC2_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
+    TC2_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
+    TC2_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
+    TC2_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
+    TC2_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
+    TC2_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
+    TC2_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
+    TC2_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
+    TC2_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
+    TC2_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
+    TC2_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
+    TC2_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
+    TC2_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
+} TC2_CLKSEL_t;
+
+/* Timer/Counter Command */
+typedef enum TC2_CMD_enum
+{
+    TC2_CMD_NONE_gc = (0x00<<2),  /* No Command */
+    TC2_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
+    TC2_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
+} TC2_CMD_t;
+
+/* Timer/Counter Command */
+typedef enum TC2_CMDEN_enum
+{
+    TC2_CMDEN_LOW_gc = (0x01<<0),  /* Low Byte Timer/Counter */
+    TC2_CMDEN_HIGH_gc = (0x02<<0),  /* High Byte Timer/Counter */
+    TC2_CMDEN_BOTH_gc = (0x03<<0),  /* Both Low Byte and High Byte Timer/Counters */
+} TC2_CMDEN_t;
+
+/* High Byte Underflow Interrupt Level */
+typedef enum TC2_HUNFINTLVL_enum
+{
+    TC2_HUNFINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    TC2_HUNFINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    TC2_HUNFINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    TC2_HUNFINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} TC2_HUNFINTLVL_t;
+
+/* Low Byte Compare A Interrupt Level */
+typedef enum TC2_LCMPAINTLVL_enum
+{
+    TC2_LCMPAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    TC2_LCMPAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    TC2_LCMPAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    TC2_LCMPAINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} TC2_LCMPAINTLVL_t;
+
+/* Low Byte Compare B Interrupt Level */
+typedef enum TC2_LCMPBINTLVL_enum
+{
+    TC2_LCMPBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    TC2_LCMPBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    TC2_LCMPBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    TC2_LCMPBINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} TC2_LCMPBINTLVL_t;
+
+/* Low Byte Compare C Interrupt Level */
+typedef enum TC2_LCMPCINTLVL_enum
+{
+    TC2_LCMPCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
+    TC2_LCMPCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
+    TC2_LCMPCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
+    TC2_LCMPCINTLVL_HI_gc = (0x03<<4),  /* High Level */
+} TC2_LCMPCINTLVL_t;
+
+/* Low Byte Compare D Interrupt Level */
+typedef enum TC2_LCMPDINTLVL_enum
+{
+    TC2_LCMPDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
+    TC2_LCMPDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
+    TC2_LCMPDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
+    TC2_LCMPDINTLVL_HI_gc = (0x03<<6),  /* High Level */
+} TC2_LCMPDINTLVL_t;
+
+/* Low Byte Underflow Interrupt Level */
+typedef enum TC2_LUNFINTLVL_enum
+{
+    TC2_LUNFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    TC2_LUNFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    TC2_LUNFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    TC2_LUNFINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} TC2_LUNFINTLVL_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/*  */
+typedef struct TWI_MASTER_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control Register C */
+    register8_t STATUS;  /* Status Register */
+    register8_t BAUD;  /* Baud Rate Control Register */
+    register8_t ADDR;  /* Address Register */
+    register8_t DATA;  /* Data Register */
+} TWI_MASTER_t;
+
+
+/*  */
+typedef struct TWI_SLAVE_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t STATUS;  /* Status Register */
+    register8_t ADDR;  /* Address Register */
+    register8_t DATA;  /* Data Register */
+    register8_t ADDRMASK;  /* Address Mask Register */
+} TWI_SLAVE_t;
+
+
+/* Two-Wire Interface */
+typedef struct TWI_struct
+{
+    register8_t CTRL;  /* TWI Common Control Register */
+    TWI_MASTER_t MASTER;  /* TWI master module */
+    TWI_SLAVE_t SLAVE;  /* TWI slave module */
+} TWI_t;
+
+/* Master Bus State */
+typedef enum TWI_MASTER_BUSSTATE_enum
+{
+    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
+    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
+    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
+    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
+} TWI_MASTER_BUSSTATE_t;
+
+/* Master Command */
+typedef enum TWI_MASTER_CMD_enum
+{
+    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
+    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
+    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
+    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
+} TWI_MASTER_CMD_t;
+
+/* Master Interrupt Level */
+typedef enum TWI_MASTER_INTLVL_enum
+{
+    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
+    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
+    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
+    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
+} TWI_MASTER_INTLVL_t;
+
+/* Inactive Timeout */
+typedef enum TWI_MASTER_TIMEOUT_enum
+{
+    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
+    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
+    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
+    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
+} TWI_MASTER_TIMEOUT_t;
+
+/* Slave Command */
+typedef enum TWI_SLAVE_CMD_enum
+{
+    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
+    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
+    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
+} TWI_SLAVE_CMD_t;
+
+/* Slave Interrupt Level */
+typedef enum TWI_SLAVE_INTLVL_enum
+{
+    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
+    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
+    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
+    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
+} TWI_SLAVE_INTLVL_t;
+
+/* SDA hold time */
+typedef enum TWI_SDAHOLD_enum
+{
+    TWI_SDAHOLD_OFF_gc = (0x00<<1),  /* SDA hold time off */
+    TWI_SDAHOLD_50NS_gc = (0x01<<1),  /* Typical 50ns hold time */
+    TWI_SDAHOLD_300NS_gc = (0x02<<1),  /* Typical 300ns hold time */
+    TWI_SDAHOLD_400NS_gc = (0x03<<1),  /* Typical 400ns hold time */
+} TWI_SDAHOLD_t;
+
+/*
+--------------------------------------------------------------------------
+USART - Universal Asynchronous Receiver-Transmitter
+--------------------------------------------------------------------------
+*/
+
+/* Universal Synchronous/Asynchronous Receiver/Transmitter */
+typedef struct USART_struct
+{
+    register8_t DATA;  /* Data Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t reserved_0x02;
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control Register C */
+    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
+    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
+} USART_t;
+
+/* Character Size */
+typedef enum USART_CHSIZE_enum
+{
+    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
+    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
+    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
+    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
+    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
+} USART_CHSIZE_t;
+
+/* Communication Mode */
+typedef enum USART_CMODE_enum
+{
+    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
+    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
+    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
+    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
+} USART_CMODE_t;
+
+/* Data Register Empty Interrupt level */
+typedef enum USART_DREINTLVL_enum
+{
+    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} USART_DREINTLVL_t;
+
+/* Parity Mode */
+typedef enum USART_PMODE_enum
+{
+    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
+    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
+    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
+} USART_PMODE_t;
+
+/* Receive Complete Interrupt level */
+typedef enum USART_RXCINTLVL_enum
+{
+    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
+    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
+    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
+    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
+} USART_RXCINTLVL_t;
+
+/* Transmit Complete Interrupt level */
+typedef enum USART_TXCINTLVL_enum
+{
+    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} USART_TXCINTLVL_t;
+
+/*
+--------------------------------------------------------------------------
+USB - USB
+--------------------------------------------------------------------------
+*/
+
+/* USB Endpoint */
+typedef struct USB_EP_struct
+{
+    register8_t STATUS;  /* Endpoint Status */
+    register8_t CTRL;  /* Endpoint Control */
+    _WORDREGISTER(CNT);  /* USB Endpoint Counter */
+    _WORDREGISTER(DATAPTR);  /* Data Pointer */
+    _WORDREGISTER(AUXDATA);  /* Auxiliary Data */
+} USB_EP_t;
+
+
+/* Universal Serial Bus */
+typedef struct USB_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t STATUS;  /* Status Register */
+    register8_t ADDR;  /* Address Register */
+    register8_t FIFOWP;  /* FIFO Write Pointer Register */
+    register8_t FIFORP;  /* FIFO Read Pointer Register */
+    _WORDREGISTER(EPPTR);  /* Endpoint Configuration Table Pointer */
+    register8_t INTCTRLA;  /* Interrupt Control Register A */
+    register8_t INTCTRLB;  /* Interrupt Control Register B */
+    register8_t INTFLAGSACLR;  /* Clear Interrupt Flag Register A */
+    register8_t INTFLAGSASET;  /* Set Interrupt Flag Register A */
+    register8_t INTFLAGSBCLR;  /* Clear Interrupt Flag Register B */
+    register8_t INTFLAGSBSET;  /* Set Interrupt Flag Register B */
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    register8_t reserved_0x10;
+    register8_t reserved_0x11;
+    register8_t reserved_0x12;
+    register8_t reserved_0x13;
+    register8_t reserved_0x14;
+    register8_t reserved_0x15;
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    register8_t reserved_0x18;
+    register8_t reserved_0x19;
+    register8_t reserved_0x1A;
+    register8_t reserved_0x1B;
+    register8_t reserved_0x1C;
+    register8_t reserved_0x1D;
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    register8_t reserved_0x20;
+    register8_t reserved_0x21;
+    register8_t reserved_0x22;
+    register8_t reserved_0x23;
+    register8_t reserved_0x24;
+    register8_t reserved_0x25;
+    register8_t reserved_0x26;
+    register8_t reserved_0x27;
+    register8_t reserved_0x28;
+    register8_t reserved_0x29;
+    register8_t reserved_0x2A;
+    register8_t reserved_0x2B;
+    register8_t reserved_0x2C;
+    register8_t reserved_0x2D;
+    register8_t reserved_0x2E;
+    register8_t reserved_0x2F;
+    register8_t reserved_0x30;
+    register8_t reserved_0x31;
+    register8_t reserved_0x32;
+    register8_t reserved_0x33;
+    register8_t reserved_0x34;
+    register8_t reserved_0x35;
+    register8_t reserved_0x36;
+    register8_t reserved_0x37;
+    register8_t reserved_0x38;
+    register8_t reserved_0x39;
+    register8_t CAL0;  /* Calibration Byte 0 */
+    register8_t CAL1;  /* Calibration Byte 1 */
+} USB_t;
+
+
+/* USB Endpoint Table */
+typedef struct USB_EP_TABLE_struct
+{
+    USB_EP_t EP0OUT;  /* Endpoint 0 */
+    USB_EP_t EP0IN;  /* Endpoint 0 */
+    USB_EP_t EP1OUT;  /* Endpoint 1 */
+    USB_EP_t EP1IN;  /* Endpoint 1 */
+    USB_EP_t EP2OUT;  /* Endpoint 2 */
+    USB_EP_t EP2IN;  /* Endpoint 2 */
+    USB_EP_t EP3OUT;  /* Endpoint 3 */
+    USB_EP_t EP3IN;  /* Endpoint 3 */
+    USB_EP_t EP4OUT;  /* Endpoint 4 */
+    USB_EP_t EP4IN;  /* Endpoint 4 */
+    USB_EP_t EP5OUT;  /* Endpoint 5 */
+    USB_EP_t EP5IN;  /* Endpoint 5 */
+    USB_EP_t EP6OUT;  /* Endpoint 6 */
+    USB_EP_t EP6IN;  /* Endpoint 6 */
+    USB_EP_t EP7OUT;  /* Endpoint 7 */
+    USB_EP_t EP7IN;  /* Endpoint 7 */
+    USB_EP_t EP8OUT;  /* Endpoint 8 */
+    USB_EP_t EP8IN;  /* Endpoint 8 */
+    USB_EP_t EP9OUT;  /* Endpoint 9 */
+    USB_EP_t EP9IN;  /* Endpoint 9 */
+    USB_EP_t EP10OUT;  /* Endpoint 10 */
+    USB_EP_t EP10IN;  /* Endpoint 10 */
+    USB_EP_t EP11OUT;  /* Endpoint 11 */
+    USB_EP_t EP11IN;  /* Endpoint 11 */
+    USB_EP_t EP12OUT;  /* Endpoint 12 */
+    USB_EP_t EP12IN;  /* Endpoint 12 */
+    USB_EP_t EP13OUT;  /* Endpoint 13 */
+    USB_EP_t EP13IN;  /* Endpoint 13 */
+    USB_EP_t EP14OUT;  /* Endpoint 14 */
+    USB_EP_t EP14IN;  /* Endpoint 14 */
+    USB_EP_t EP15OUT;  /* Endpoint 15 */
+    USB_EP_t EP15IN;  /* Endpoint 15 */
+    register8_t reserved_0x100;
+    register8_t reserved_0x101;
+    register8_t reserved_0x102;
+    register8_t reserved_0x103;
+    register8_t reserved_0x104;
+    register8_t reserved_0x105;
+    register8_t reserved_0x106;
+    register8_t reserved_0x107;
+    register8_t reserved_0x108;
+    register8_t reserved_0x109;
+    register8_t reserved_0x10A;
+    register8_t reserved_0x10B;
+    register8_t reserved_0x10C;
+    register8_t reserved_0x10D;
+    register8_t reserved_0x10E;
+    register8_t reserved_0x10F;
+    register8_t FRAMENUML;  /* Frame Number Low Byte */
+    register8_t FRAMENUMH;  /* Frame Number High Byte */
+} USB_EP_TABLE_t;
+
+/* USB Endpoint Buffersize */
+typedef enum USB_EP_BUFSIZE_enum
+{
+    USB_EP_BUFSIZE_8_gc = (0x00<<0),  /* 8 bytes buffer size */
+    USB_EP_BUFSIZE_16_gc = (0x01<<0),  /* 16 bytes buffer size */
+    USB_EP_BUFSIZE_32_gc = (0x02<<0),  /* 32 bytes buffer size */
+    USB_EP_BUFSIZE_64_gc = (0x03<<0),  /* 64 bytes buffer size */
+    USB_EP_BUFSIZE_128_gc = (0x04<<0),  /* 128 bytes buffer size */
+    USB_EP_BUFSIZE_256_gc = (0x05<<0),  /* 256 bytes buffer size */
+    USB_EP_BUFSIZE_512_gc = (0x06<<0),  /* 512 bytes buffer size */
+    USB_EP_BUFSIZE_1023_gc = (0x07<<0),  /* 1023 bytes buffer size */
+} USB_EP_BUFSIZE_t;
+
+/* USB Endpoint Type */
+typedef enum USB_EP_TYPE_enum
+{
+    USB_EP_TYPE_DISABLE_gc = (0x00<<6),  /* Endpoint Disabled */
+    USB_EP_TYPE_CONTROL_gc = (0x01<<6),  /* Control */
+    USB_EP_TYPE_BULK_gc = (0x02<<6),  /* Bulk/Interrupt */
+    USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6),  /* Isochronous */
+} USB_EP_TYPE_t;
+
+/* Interrupt level */
+typedef enum USB_INTLVL_enum
+{
+    USB_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
+    USB_INTLVL_LO_gc = (0x01<<0),  /* Low level */
+    USB_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
+    USB_INTLVL_HI_gc = (0x03<<0),  /* High level */
+} USB_INTLVL_t;
+
+/*
+--------------------------------------------------------------------------
+VPORT - Virtual Ports
+--------------------------------------------------------------------------
+*/
+
+/* Virtual Port */
+typedef struct VPORT_struct
+{
+    register8_t DIR;  /* I/O Port Data Direction */
+    register8_t OUT;  /* I/O Port Output */
+    register8_t IN;  /* I/O Port Input */
+    register8_t INTFLAGS;  /* Interrupt Flag Register */
+} VPORT_t;
+
+
+/*
+--------------------------------------------------------------------------
+WDT - Watch-Dog Timer
+--------------------------------------------------------------------------
+*/
+
+/* Watch-Dog Timer */
+typedef struct WDT_struct
+{
+    register8_t CTRL;  /* Control */
+    register8_t WINCTRL;  /* Windowed Mode Control */
+    register8_t STATUS;  /* Status */
+} WDT_t;
+
+/* Period setting */
+typedef enum WDT_PER_enum
+{
+    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
+    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
+    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
+    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
+    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
+    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
+    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
+    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
+    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
+    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
+    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
+} WDT_PER_t;
+
+/* Closed window period */
+typedef enum WDT_WPER_enum
+{
+    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
+    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
+    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
+    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
+    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
+    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
+    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
+    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
+    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
+    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
+    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
+} WDT_WPER_t;
+
+/*
+--------------------------------------------------------------------------
+XOCD - On-Chip Debug System
+--------------------------------------------------------------------------
+*/
+
+/* On-Chip Debug System */
+typedef struct OCD_struct
+{
+    register8_t OCDR0;  /* OCD Register 0 */
+    register8_t OCDR1;  /* OCD Register 1 */
+} OCD_t;
+
+/*
+==========================================================================
+IO Module Instances. Mapped to memory.
+==========================================================================
+*/
+
+#define VPORT0              (*(VPORT_t *) 0x0010) /* Virtual Port */
+#define VPORT1              (*(VPORT_t *) 0x0014) /* Virtual Port */
+#define VPORT2              (*(VPORT_t *) 0x0018) /* Virtual Port */
+#define VPORT3              (*(VPORT_t *) 0x001C) /* Virtual Port */
+#define OCD                   (*(OCD_t *) 0x002E) /* On-Chip Debug System */
+#define CLK                   (*(CLK_t *) 0x0040) /* Clock System */
+#define SLEEP               (*(SLEEP_t *) 0x0048) /* Sleep Controller */
+#define OSC                   (*(OSC_t *) 0x0050) /* Oscillator */
+#define DFLLRC32M            (*(DFLL_t *) 0x0060) /* DFLL */
+#define DFLLRC2M             (*(DFLL_t *) 0x0068) /* DFLL */
+#define PR                     (*(PR_t *) 0x0070) /* Power Reduction */
+#define RST                   (*(RST_t *) 0x0078) /* Reset */
+#define WDT                   (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
+#define MCU                   (*(MCU_t *) 0x0090) /* MCU Control */
+#define PMIC                 (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
+#define PORTCFG           (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
+#define AES                   (*(AES_t *) 0x00C0) /* AES Module */
+#define CRC                   (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
+#define DMA                   (*(DMA_t *) 0x0100) /* DMA Controller */
+#define EVSYS               (*(EVSYS_t *) 0x0180) /* Event System */
+#define NVM                   (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
+#define ADCA                  (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
+#define ADCB                  (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
+#define DACA                  (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */
+#define DACB                  (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
+#define ACA                    (*(AC_t *) 0x0380) /* Analog Comparator */
+#define ACB                    (*(AC_t *) 0x0390) /* Analog Comparator */
+#define RTC                   (*(RTC_t *) 0x0400) /* Real-Time Counter */
+#define EBI                   (*(EBI_t *) 0x0440) /* External Bus Interface */
+#define TWIC                  (*(TWI_t *) 0x0480) /* Two-Wire Interface */
+#define TWID                  (*(TWI_t *) 0x0490) /* Two-Wire Interface */
+#define TWIE                  (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
+#define TWIF                  (*(TWI_t *) 0x04B0) /* Two-Wire Interface */
+#define USB                   (*(USB_t *) 0x04C0) /* Universal Serial Bus */
+#define PORTA                (*(PORT_t *) 0x0600) /* I/O Ports */
+#define PORTB                (*(PORT_t *) 0x0620) /* I/O Ports */
+#define PORTC                (*(PORT_t *) 0x0640) /* I/O Ports */
+#define PORTD                (*(PORT_t *) 0x0660) /* I/O Ports */
+#define PORTE                (*(PORT_t *) 0x0680) /* I/O Ports */
+#define PORTF                (*(PORT_t *) 0x06A0) /* I/O Ports */
+#define PORTH                (*(PORT_t *) 0x06E0) /* I/O Ports */
+#define PORTJ                (*(PORT_t *) 0x0700) /* I/O Ports */
+#define PORTK                (*(PORT_t *) 0x0720) /* I/O Ports */
+#define PORTQ                (*(PORT_t *) 0x07C0) /* I/O Ports */
+#define PORTR                (*(PORT_t *) 0x07E0) /* I/O Ports */
+#define TCC0                  (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
+#define TCC2                  (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
+#define TCC1                  (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
+#define AWEXC                (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
+#define HIRESC              (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
+#define USARTC0             (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTC1             (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define SPIC                  (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
+#define IRCOM               (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
+#define TCD0                  (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
+#define TCD2                  (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
+#define TCD1                  (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
+#define HIRESD              (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
+#define USARTD0             (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTD1             (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define SPID                  (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
+#define TCE0                  (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
+#define TCE2                  (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
+#define TCE1                  (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */
+#define AWEXE                (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */
+#define HIRESE              (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
+#define USARTE0             (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTE1             (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define SPIE                  (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */
+#define TCF0                  (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
+#define TCF2                  (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
+#define TCF1                  (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */
+#define HIRESF              (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */
+#define USARTF0             (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTF1             (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define SPIF                  (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */
+
+#endif /* !defined (__ASSEMBLER__) */
+
+
+/* ========== Flattened fully qualified IO register names ========== */
+
+
+/* GPIO - General Purpose IO Registers */
+#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
+#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
+#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
+#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
+#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
+#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
+#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
+#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
+#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
+#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
+#define GPIO_GPIORA  _SFR_MEM8(0x000A)
+#define GPIO_GPIORB  _SFR_MEM8(0x000B)
+#define GPIO_GPIORC  _SFR_MEM8(0x000C)
+#define GPIO_GPIORD  _SFR_MEM8(0x000D)
+#define GPIO_GPIORE  _SFR_MEM8(0x000E)
+#define GPIO_GPIORF  _SFR_MEM8(0x000F)
+
+
+/* Deprecated */
+#define GPIO_GPIO0  _SFR_MEM8(0x0000)
+#define GPIO_GPIO1  _SFR_MEM8(0x0001)
+#define GPIO_GPIO2  _SFR_MEM8(0x0002)
+#define GPIO_GPIO3  _SFR_MEM8(0x0003)
+#define GPIO_GPIO4  _SFR_MEM8(0x0004)
+#define GPIO_GPIO5  _SFR_MEM8(0x0005)
+#define GPIO_GPIO6  _SFR_MEM8(0x0006)
+#define GPIO_GPIO7  _SFR_MEM8(0x0007)
+#define GPIO_GPIO8  _SFR_MEM8(0x0008)
+#define GPIO_GPIO9  _SFR_MEM8(0x0009)
+#define GPIO_GPIOA  _SFR_MEM8(0x000A)
+#define GPIO_GPIOB  _SFR_MEM8(0x000B)
+#define GPIO_GPIOC  _SFR_MEM8(0x000C)
+#define GPIO_GPIOD  _SFR_MEM8(0x000D)
+#define GPIO_GPIOE  _SFR_MEM8(0x000E)
+#define GPIO_GPIOF  _SFR_MEM8(0x000F)
+
+
+/* NVM_FUSES (FUSE) - Fuses */
+#define FUSE_FUSEBYTE0  _SFR_MEM8(0x0000)
+#define FUSE_FUSEBYTE1  _SFR_MEM8(0x0001)
+#define FUSE_FUSEBYTE2  _SFR_MEM8(0x0002)
+#define FUSE_FUSEBYTE4  _SFR_MEM8(0x0004)
+#define FUSE_FUSEBYTE5  _SFR_MEM8(0x0005)
+
+
+/* NVM_LOCKBITS (LOCKBIT) - Lock Bits */
+#define LOCKBIT_LOCKBITS  _SFR_MEM8(0x0000)
+
+
+/* NVM_PROD_SIGNATURES (PROD_SIGNATURES) - Production Signatures */
+#define PRODSIGNATURES_RCOSC2M  _SFR_MEM8(0x0000)
+#define PRODSIGNATURES_RCOSC2MA  _SFR_MEM8(0x0001)
+#define PRODSIGNATURES_RCOSC32K  _SFR_MEM8(0x0002)
+#define PRODSIGNATURES_RCOSC32M  _SFR_MEM8(0x0003)
+#define PRODSIGNATURES_RCOSC32MA  _SFR_MEM8(0x0004)
+#define PRODSIGNATURES_LOTNUM0  _SFR_MEM8(0x0008)
+#define PRODSIGNATURES_LOTNUM1  _SFR_MEM8(0x0009)
+#define PRODSIGNATURES_LOTNUM2  _SFR_MEM8(0x000A)
+#define PRODSIGNATURES_LOTNUM3  _SFR_MEM8(0x000B)
+#define PRODSIGNATURES_LOTNUM4  _SFR_MEM8(0x000C)
+#define PRODSIGNATURES_LOTNUM5  _SFR_MEM8(0x000D)
+#define PRODSIGNATURES_WAFNUM  _SFR_MEM8(0x0010)
+#define PRODSIGNATURES_COORDX0  _SFR_MEM8(0x0012)
+#define PRODSIGNATURES_COORDX1  _SFR_MEM8(0x0013)
+#define PRODSIGNATURES_COORDY0  _SFR_MEM8(0x0014)
+#define PRODSIGNATURES_COORDY1  _SFR_MEM8(0x0015)
+#define PRODSIGNATURES_USBCAL0  _SFR_MEM8(0x001A)
+#define PRODSIGNATURES_USBCAL1  _SFR_MEM8(0x001B)
+#define PRODSIGNATURES_USBRCOSC  _SFR_MEM8(0x001C)
+#define PRODSIGNATURES_USBRCOSCA  _SFR_MEM8(0x001D)
+#define PRODSIGNATURES_ADCACAL0  _SFR_MEM8(0x0020)
+#define PRODSIGNATURES_ADCACAL1  _SFR_MEM8(0x0021)
+#define PRODSIGNATURES_ADCBCAL0  _SFR_MEM8(0x0024)
+#define PRODSIGNATURES_ADCBCAL1  _SFR_MEM8(0x0025)
+#define PRODSIGNATURES_TEMPSENSE0  _SFR_MEM8(0x002E)
+#define PRODSIGNATURES_TEMPSENSE1  _SFR_MEM8(0x002F)
+#define PRODSIGNATURES_DACA0OFFCAL  _SFR_MEM8(0x0030)
+#define PRODSIGNATURES_DACA0GAINCAL  _SFR_MEM8(0x0031)
+#define PRODSIGNATURES_DACB0OFFCAL  _SFR_MEM8(0x0032)
+#define PRODSIGNATURES_DACB0GAINCAL  _SFR_MEM8(0x0033)
+#define PRODSIGNATURES_DACA1OFFCAL  _SFR_MEM8(0x0034)
+#define PRODSIGNATURES_DACA1GAINCAL  _SFR_MEM8(0x0035)
+#define PRODSIGNATURES_DACB1OFFCAL  _SFR_MEM8(0x0036)
+#define PRODSIGNATURES_DACB1GAINCAL  _SFR_MEM8(0x0037)
+
+
+/* VPORT (VPORT0) - Virtual Port */
+#define VPORT0_DIR  _SFR_MEM8(0x0010)
+#define VPORT0_OUT  _SFR_MEM8(0x0011)
+#define VPORT0_IN  _SFR_MEM8(0x0012)
+#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
+
+
+/* VPORT (VPORT1) - Virtual Port */
+#define VPORT1_DIR  _SFR_MEM8(0x0014)
+#define VPORT1_OUT  _SFR_MEM8(0x0015)
+#define VPORT1_IN  _SFR_MEM8(0x0016)
+#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
+
+
+/* VPORT (VPORT2) - Virtual Port */
+#define VPORT2_DIR  _SFR_MEM8(0x0018)
+#define VPORT2_OUT  _SFR_MEM8(0x0019)
+#define VPORT2_IN  _SFR_MEM8(0x001A)
+#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
+
+
+/* VPORT (VPORT3) - Virtual Port */
+#define VPORT3_DIR  _SFR_MEM8(0x001C)
+#define VPORT3_OUT  _SFR_MEM8(0x001D)
+#define VPORT3_IN  _SFR_MEM8(0x001E)
+#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
+
+
+/* OCD - On-Chip Debug System */
+#define OCD_OCDR0  _SFR_MEM8(0x002E)
+#define OCD_OCDR1  _SFR_MEM8(0x002F)
+
+
+/* CPU - CPU registers */
+#define CPU_CCP  _SFR_MEM8(0x0034)
+#define CPU_RAMPD  _SFR_MEM8(0x0038)
+#define CPU_RAMPX  _SFR_MEM8(0x0039)
+#define CPU_RAMPY  _SFR_MEM8(0x003A)
+#define CPU_RAMPZ  _SFR_MEM8(0x003B)
+#define CPU_EIND  _SFR_MEM8(0x003C)
+#define CPU_SPL  _SFR_MEM8(0x003D)
+#define CPU_SPH  _SFR_MEM8(0x003E)
+#define CPU_SREG  _SFR_MEM8(0x003F)
+
+
+/* CLK - Clock System */
+#define CLK_CTRL  _SFR_MEM8(0x0040)
+#define CLK_PSCTRL  _SFR_MEM8(0x0041)
+#define CLK_LOCK  _SFR_MEM8(0x0042)
+#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
+#define CLK_USBCTRL  _SFR_MEM8(0x0044)
+
+
+/* SLEEP - Sleep Controller */
+#define SLEEP_CTRL  _SFR_MEM8(0x0048)
+
+
+/* OSC - Oscillator */
+#define OSC_CTRL  _SFR_MEM8(0x0050)
+#define OSC_STATUS  _SFR_MEM8(0x0051)
+#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
+#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
+#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
+#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
+#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
+
+
+/* DFLL (DFLLRC32M) - DFLL */
+#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
+#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
+#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
+#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
+#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
+#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
+
+
+/* DFLL (DFLLRC2M) - DFLL */
+#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
+#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
+#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
+#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
+#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
+#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
+
+
+/* PR - Power Reduction */
+#define PR_PRGEN  _SFR_MEM8(0x0070)
+#define PR_PRPA  _SFR_MEM8(0x0071)
+#define PR_PRPB  _SFR_MEM8(0x0072)
+#define PR_PRPC  _SFR_MEM8(0x0073)
+#define PR_PRPD  _SFR_MEM8(0x0074)
+#define PR_PRPE  _SFR_MEM8(0x0075)
+#define PR_PRPF  _SFR_MEM8(0x0076)
+
+
+/* RST - Reset */
+#define RST_STATUS  _SFR_MEM8(0x0078)
+#define RST_CTRL  _SFR_MEM8(0x0079)
+
+
+/* WDT - Watch-Dog Timer */
+#define WDT_CTRL  _SFR_MEM8(0x0080)
+#define WDT_WINCTRL  _SFR_MEM8(0x0081)
+#define WDT_STATUS  _SFR_MEM8(0x0082)
+
+
+/* MCU - MCU Control */
+#define MCU_DEVID0  _SFR_MEM8(0x0090)
+#define MCU_DEVID1  _SFR_MEM8(0x0091)
+#define MCU_DEVID2  _SFR_MEM8(0x0092)
+#define MCU_REVID  _SFR_MEM8(0x0093)
+#define MCU_JTAGUID  _SFR_MEM8(0x0094)
+#define MCU_MCUCR  _SFR_MEM8(0x0096)
+#define MCU_ANAINIT  _SFR_MEM8(0x0097)
+#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
+#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
+
+
+/* PMIC - Programmable Multi-level Interrupt Controller */
+#define PMIC_STATUS  _SFR_MEM8(0x00A0)
+#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
+#define PMIC_CTRL  _SFR_MEM8(0x00A2)
+
+
+/* PORTCFG - I/O port Configuration */
+#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
+#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
+#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
+#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
+#define PORTCFG_EBIOUT  _SFR_MEM8(0x00B5)
+#define PORTCFG_EVOUTSEL  _SFR_MEM8(0x00B6)
+
+
+/* AES - AES Module */
+#define AES_CTRL  _SFR_MEM8(0x00C0)
+#define AES_STATUS  _SFR_MEM8(0x00C1)
+#define AES_STATE  _SFR_MEM8(0x00C2)
+#define AES_KEY  _SFR_MEM8(0x00C3)
+#define AES_INTCTRL  _SFR_MEM8(0x00C4)
+
+
+/* CRC - Cyclic Redundancy Checker */
+#define CRC_CTRL  _SFR_MEM8(0x00D0)
+#define CRC_STATUS  _SFR_MEM8(0x00D1)
+#define CRC_DATAIN  _SFR_MEM8(0x00D3)
+#define CRC_CHECKSUM0  _SFR_MEM8(0x00D4)
+#define CRC_CHECKSUM1  _SFR_MEM8(0x00D5)
+#define CRC_CHECKSUM2  _SFR_MEM8(0x00D6)
+#define CRC_CHECKSUM3  _SFR_MEM8(0x00D7)
+
+
+/* DMA - DMA Controller */
+#define DMA_CTRL  _SFR_MEM8(0x0100)
+#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
+#define DMA_STATUS  _SFR_MEM8(0x0104)
+#define DMA_TEMP  _SFR_MEM16(0x0106)
+#define DMA_TEMPL  _SFR_MEM8(0x0106)
+#define DMA_TEMPH  _SFR_MEM8(0x0107)
+#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
+#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
+#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
+#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
+#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
+#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
+#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
+#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
+#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
+#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
+#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
+#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
+
+
+#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
+#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
+#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
+#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
+#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
+#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
+#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
+#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
+#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
+#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
+#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
+#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
+
+
+#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
+#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
+#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
+#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
+#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
+#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
+#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
+#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
+#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
+#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
+#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
+#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
+
+
+#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
+#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
+#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
+#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
+#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
+#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
+#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
+#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
+#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
+#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
+#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
+#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
+
+
+
+
+/* EVSYS - Event System */
+#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
+#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
+#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
+#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
+#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
+#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
+#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
+#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
+#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
+#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
+#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
+#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
+#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
+#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
+#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
+#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
+#define EVSYS_STROBE  _SFR_MEM8(0x0190)
+#define EVSYS_DATA  _SFR_MEM8(0x0191)
+
+
+/* NVM - Non-volatile Memory Controller */
+#define NVM_ADDR0  _SFR_MEM8(0x01C0)
+#define NVM_ADDR1  _SFR_MEM8(0x01C1)
+#define NVM_ADDR2  _SFR_MEM8(0x01C2)
+#define NVM_DATA0  _SFR_MEM8(0x01C4)
+#define NVM_DATA1  _SFR_MEM8(0x01C5)
+#define NVM_DATA2  _SFR_MEM8(0x01C6)
+#define NVM_CMD  _SFR_MEM8(0x01CA)
+#define NVM_CTRLA  _SFR_MEM8(0x01CB)
+#define NVM_CTRLB  _SFR_MEM8(0x01CC)
+#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
+#define NVM_STATUS  _SFR_MEM8(0x01CF)
+#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
+
+
+/* ADC (ADCA) - Analog-to-Digital Converter */
+#define ADCA_CTRLA  _SFR_MEM8(0x0200)
+#define ADCA_CTRLB  _SFR_MEM8(0x0201)
+#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
+#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
+#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
+#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
+#define ADCA_TEMP  _SFR_MEM8(0x0207)
+#define ADCA_CAL  _SFR_MEM16(0x020C)
+#define ADCA_CALL  _SFR_MEM8(0x020C)
+#define ADCA_CALH  _SFR_MEM8(0x020D)
+#define ADCA_CH0RES  _SFR_MEM16(0x0210)
+#define ADCA_CH0RESL  _SFR_MEM8(0x0210)
+#define ADCA_CH0RESH  _SFR_MEM8(0x0211)
+#define ADCA_CH1RES  _SFR_MEM16(0x0212)
+#define ADCA_CH1RESL  _SFR_MEM8(0x0212)
+#define ADCA_CH1RESH  _SFR_MEM8(0x0213)
+#define ADCA_CH2RES  _SFR_MEM16(0x0214)
+#define ADCA_CH2RESL  _SFR_MEM8(0x0214)
+#define ADCA_CH2RESH  _SFR_MEM8(0x0215)
+#define ADCA_CH3RES  _SFR_MEM16(0x0216)
+#define ADCA_CH3RESL  _SFR_MEM8(0x0216)
+#define ADCA_CH3RESH  _SFR_MEM8(0x0217)
+#define ADCA_CMP  _SFR_MEM16(0x0218)
+#define ADCA_CMPL  _SFR_MEM8(0x0218)
+#define ADCA_CMPH  _SFR_MEM8(0x0219)
+#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
+#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
+#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
+#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
+#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
+#define ADCA_CH0_SCAN  _SFR_MEM8(0x0226)
+
+
+#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
+#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
+#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
+#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
+#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
+#define ADCA_CH1_SCAN  _SFR_MEM8(0x022E)
+
+
+#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
+#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
+#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
+#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
+#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
+#define ADCA_CH2_SCAN  _SFR_MEM8(0x0236)
+
+
+#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
+#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
+#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
+#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
+#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
+#define ADCA_CH3_SCAN  _SFR_MEM8(0x023E)
+
+
+
+
+/* ADC (ADCB) - Analog-to-Digital Converter */
+#define ADCB_CTRLA  _SFR_MEM8(0x0240)
+#define ADCB_CTRLB  _SFR_MEM8(0x0241)
+#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
+#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
+#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
+#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
+#define ADCB_TEMP  _SFR_MEM8(0x0247)
+#define ADCB_CAL  _SFR_MEM16(0x024C)
+#define ADCB_CALL  _SFR_MEM8(0x024C)
+#define ADCB_CALH  _SFR_MEM8(0x024D)
+#define ADCB_CH0RES  _SFR_MEM16(0x0250)
+#define ADCB_CH0RESL  _SFR_MEM8(0x0250)
+#define ADCB_CH0RESH  _SFR_MEM8(0x0251)
+#define ADCB_CH1RES  _SFR_MEM16(0x0252)
+#define ADCB_CH1RESL  _SFR_MEM8(0x0252)
+#define ADCB_CH1RESH  _SFR_MEM8(0x0253)
+#define ADCB_CH2RES  _SFR_MEM16(0x0254)
+#define ADCB_CH2RESL  _SFR_MEM8(0x0254)
+#define ADCB_CH2RESH  _SFR_MEM8(0x0255)
+#define ADCB_CH3RES  _SFR_MEM16(0x0256)
+#define ADCB_CH3RESL  _SFR_MEM8(0x0256)
+#define ADCB_CH3RESH  _SFR_MEM8(0x0257)
+#define ADCB_CMP  _SFR_MEM16(0x0258)
+#define ADCB_CMPL  _SFR_MEM8(0x0258)
+#define ADCB_CMPH  _SFR_MEM8(0x0259)
+#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
+#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
+#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
+#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
+#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
+#define ADCB_CH0_SCAN  _SFR_MEM8(0x0266)
+
+
+#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
+#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
+#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
+#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
+#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
+#define ADCB_CH1_SCAN  _SFR_MEM8(0x026E)
+
+
+#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
+#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
+#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
+#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
+#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
+#define ADCB_CH2_SCAN  _SFR_MEM8(0x0276)
+
+
+#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
+#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
+#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
+#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
+#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
+#define ADCB_CH3_SCAN  _SFR_MEM8(0x027E)
+
+
+
+
+/* DAC (DACA) - Digital-to-Analog Converter */
+#define DACA_CTRLA  _SFR_MEM8(0x0300)
+#define DACA_CTRLB  _SFR_MEM8(0x0301)
+#define DACA_CTRLC  _SFR_MEM8(0x0302)
+#define DACA_EVCTRL  _SFR_MEM8(0x0303)
+#define DACA_STATUS  _SFR_MEM8(0x0305)
+#define DACA_CH0GAINCAL  _SFR_MEM8(0x0308)
+#define DACA_CH0OFFSETCAL  _SFR_MEM8(0x0309)
+#define DACA_CH1GAINCAL  _SFR_MEM8(0x030A)
+#define DACA_CH1OFFSETCAL  _SFR_MEM8(0x030B)
+#define DACA_CH0DATA  _SFR_MEM16(0x0318)
+#define DACA_CH0DATAL  _SFR_MEM8(0x0318)
+#define DACA_CH0DATAH  _SFR_MEM8(0x0319)
+#define DACA_CH1DATA  _SFR_MEM16(0x031A)
+#define DACA_CH1DATAL  _SFR_MEM8(0x031A)
+#define DACA_CH1DATAH  _SFR_MEM8(0x031B)
+
+
+/* DAC (DACB) - Digital-to-Analog Converter */
+#define DACB_CTRLA  _SFR_MEM8(0x0320)
+#define DACB_CTRLB  _SFR_MEM8(0x0321)
+#define DACB_CTRLC  _SFR_MEM8(0x0322)
+#define DACB_EVCTRL  _SFR_MEM8(0x0323)
+#define DACB_STATUS  _SFR_MEM8(0x0325)
+#define DACB_CH0GAINCAL  _SFR_MEM8(0x0328)
+#define DACB_CH0OFFSETCAL  _SFR_MEM8(0x0329)
+#define DACB_CH1GAINCAL  _SFR_MEM8(0x032A)
+#define DACB_CH1OFFSETCAL  _SFR_MEM8(0x032B)
+#define DACB_CH0DATA  _SFR_MEM16(0x0338)
+#define DACB_CH0DATAL  _SFR_MEM8(0x0338)
+#define DACB_CH0DATAH  _SFR_MEM8(0x0339)
+#define DACB_CH1DATA  _SFR_MEM16(0x033A)
+#define DACB_CH1DATAL  _SFR_MEM8(0x033A)
+#define DACB_CH1DATAH  _SFR_MEM8(0x033B)
+
+
+/* AC (ACA) - Analog Comparator */
+#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
+#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
+#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
+#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
+#define ACA_CTRLA  _SFR_MEM8(0x0384)
+#define ACA_CTRLB  _SFR_MEM8(0x0385)
+#define ACA_WINCTRL  _SFR_MEM8(0x0386)
+#define ACA_STATUS  _SFR_MEM8(0x0387)
+#define ACA_CURRCTRL  _SFR_MEM8(0x0388)
+#define ACA_CURRCALIB  _SFR_MEM8(0x0389)
+
+
+/* AC (ACB) - Analog Comparator */
+#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
+#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
+#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
+#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
+#define ACB_CTRLA  _SFR_MEM8(0x0394)
+#define ACB_CTRLB  _SFR_MEM8(0x0395)
+#define ACB_WINCTRL  _SFR_MEM8(0x0396)
+#define ACB_STATUS  _SFR_MEM8(0x0397)
+#define ACB_CURRCTRL  _SFR_MEM8(0x0398)
+#define ACB_CURRCALIB  _SFR_MEM8(0x0399)
+
+
+/* RTC - Real-Time Counter */
+#define RTC_CTRL  _SFR_MEM8(0x0400)
+#define RTC_STATUS  _SFR_MEM8(0x0401)
+#define RTC_INTCTRL  _SFR_MEM8(0x0402)
+#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
+#define RTC_TEMP  _SFR_MEM8(0x0404)
+#define RTC_CNT  _SFR_MEM16(0x0408)
+#define RTC_CNTL  _SFR_MEM8(0x0408)
+#define RTC_CNTH  _SFR_MEM8(0x0409)
+#define RTC_PER  _SFR_MEM16(0x040A)
+#define RTC_PERL  _SFR_MEM8(0x040A)
+#define RTC_PERH  _SFR_MEM8(0x040B)
+#define RTC_COMP  _SFR_MEM16(0x040C)
+#define RTC_COMPL  _SFR_MEM8(0x040C)
+#define RTC_COMPH  _SFR_MEM8(0x040D)
+
+
+/* EBI - External Bus Interface */
+#define EBI_CTRL  _SFR_MEM8(0x0440)
+#define EBI_SDRAMCTRLA  _SFR_MEM8(0x0441)
+#define EBI_REFRESH  _SFR_MEM16(0x0444)
+#define EBI_REFRESHL  _SFR_MEM8(0x0444)
+#define EBI_REFRESHH  _SFR_MEM8(0x0445)
+#define EBI_INITDLY  _SFR_MEM16(0x0446)
+#define EBI_INITDLYL  _SFR_MEM8(0x0446)
+#define EBI_INITDLYH  _SFR_MEM8(0x0447)
+#define EBI_SDRAMCTRLB  _SFR_MEM8(0x0448)
+#define EBI_SDRAMCTRLC  _SFR_MEM8(0x0449)
+#define EBI_CS0_CTRLA  _SFR_MEM8(0x0450)
+#define EBI_CS0_CTRLB  _SFR_MEM8(0x0451)
+#define EBI_CS0_BASEADDR  _SFR_MEM16(0x0452)
+
+
+#define EBI_CS1_CTRLA  _SFR_MEM8(0x0454)
+#define EBI_CS1_CTRLB  _SFR_MEM8(0x0455)
+#define EBI_CS1_BASEADDR  _SFR_MEM16(0x0456)
+
+
+#define EBI_CS2_CTRLA  _SFR_MEM8(0x0458)
+#define EBI_CS2_CTRLB  _SFR_MEM8(0x0459)
+#define EBI_CS2_BASEADDR  _SFR_MEM16(0x045A)
+
+
+#define EBI_CS3_CTRLA  _SFR_MEM8(0x045C)
+#define EBI_CS3_CTRLB  _SFR_MEM8(0x045D)
+#define EBI_CS3_BASEADDR  _SFR_MEM16(0x045E)
+
+
+
+
+/* TWI (TWIC) - Two-Wire Interface */
+#define TWIC_CTRL  _SFR_MEM8(0x0480)
+#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
+#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
+#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
+#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
+#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
+#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
+#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
+
+
+#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
+#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
+#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
+#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
+#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
+
+
+
+
+/* TWI (TWID) - Two-Wire Interface */
+#define TWID_CTRL  _SFR_MEM8(0x0490)
+#define TWID_MASTER_CTRLA  _SFR_MEM8(0x0491)
+#define TWID_MASTER_CTRLB  _SFR_MEM8(0x0492)
+#define TWID_MASTER_CTRLC  _SFR_MEM8(0x0493)
+#define TWID_MASTER_STATUS  _SFR_MEM8(0x0494)
+#define TWID_MASTER_BAUD  _SFR_MEM8(0x0495)
+#define TWID_MASTER_ADDR  _SFR_MEM8(0x0496)
+#define TWID_MASTER_DATA  _SFR_MEM8(0x0497)
+
+
+#define TWID_SLAVE_CTRLA  _SFR_MEM8(0x0498)
+#define TWID_SLAVE_CTRLB  _SFR_MEM8(0x0499)
+#define TWID_SLAVE_STATUS  _SFR_MEM8(0x049A)
+#define TWID_SLAVE_ADDR  _SFR_MEM8(0x049B)
+#define TWID_SLAVE_DATA  _SFR_MEM8(0x049C)
+#define TWID_SLAVE_ADDRMASK  _SFR_MEM8(0x049D)
+
+
+
+
+/* TWI (TWIE) - Two-Wire Interface */
+#define TWIE_CTRL  _SFR_MEM8(0x04A0)
+#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
+#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
+#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
+#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
+#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
+#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
+#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
+
+
+#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
+#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
+#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
+#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
+#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
+#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
+
+
+
+
+/* TWI (TWIF) - Two-Wire Interface */
+#define TWIF_CTRL  _SFR_MEM8(0x04B0)
+#define TWIF_MASTER_CTRLA  _SFR_MEM8(0x04B1)
+#define TWIF_MASTER_CTRLB  _SFR_MEM8(0x04B2)
+#define TWIF_MASTER_CTRLC  _SFR_MEM8(0x04B3)
+#define TWIF_MASTER_STATUS  _SFR_MEM8(0x04B4)
+#define TWIF_MASTER_BAUD  _SFR_MEM8(0x04B5)
+#define TWIF_MASTER_ADDR  _SFR_MEM8(0x04B6)
+#define TWIF_MASTER_DATA  _SFR_MEM8(0x04B7)
+
+
+#define TWIF_SLAVE_CTRLA  _SFR_MEM8(0x04B8)
+#define TWIF_SLAVE_CTRLB  _SFR_MEM8(0x04B9)
+#define TWIF_SLAVE_STATUS  _SFR_MEM8(0x04BA)
+#define TWIF_SLAVE_ADDR  _SFR_MEM8(0x04BB)
+#define TWIF_SLAVE_DATA  _SFR_MEM8(0x04BC)
+#define TWIF_SLAVE_ADDRMASK  _SFR_MEM8(0x04BD)
+
+
+
+
+/* USB - Universal Serial Bus */
+#define USB_CTRLA  _SFR_MEM8(0x04C0)
+#define USB_CTRLB  _SFR_MEM8(0x04C1)
+#define USB_STATUS  _SFR_MEM8(0x04C2)
+#define USB_ADDR  _SFR_MEM8(0x04C3)
+#define USB_FIFOWP  _SFR_MEM8(0x04C4)
+#define USB_FIFORP  _SFR_MEM8(0x04C5)
+#define USB_EPPTR  _SFR_MEM16(0x04C6)
+#define USB_EPPTRL  _SFR_MEM8(0x04C6)
+#define USB_EPPTRH  _SFR_MEM8(0x04C7)
+#define USB_INTCTRLA  _SFR_MEM8(0x04C8)
+#define USB_INTCTRLB  _SFR_MEM8(0x04C9)
+#define USB_INTFLAGSACLR  _SFR_MEM8(0x04CA)
+#define USB_INTFLAGSASET  _SFR_MEM8(0x04CB)
+#define USB_INTFLAGSBCLR  _SFR_MEM8(0x04CC)
+#define USB_INTFLAGSBSET  _SFR_MEM8(0x04CD)
+#define USB_CAL0  _SFR_MEM8(0x04FA)
+#define USB_CAL1  _SFR_MEM8(0x04FB)
+
+
+/* PORT (PORTA) - I/O Ports */
+#define PORTA_DIR  _SFR_MEM8(0x0600)
+#define PORTA_DIRSET  _SFR_MEM8(0x0601)
+#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
+#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
+#define PORTA_OUT  _SFR_MEM8(0x0604)
+#define PORTA_OUTSET  _SFR_MEM8(0x0605)
+#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
+#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
+#define PORTA_IN  _SFR_MEM8(0x0608)
+#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
+#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
+#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
+#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
+#define PORTA_REMAP  _SFR_MEM8(0x060E)
+#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
+#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
+#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
+#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
+#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
+#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
+#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
+#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
+
+
+/* PORT (PORTB) - I/O Ports */
+#define PORTB_DIR  _SFR_MEM8(0x0620)
+#define PORTB_DIRSET  _SFR_MEM8(0x0621)
+#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
+#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
+#define PORTB_OUT  _SFR_MEM8(0x0624)
+#define PORTB_OUTSET  _SFR_MEM8(0x0625)
+#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
+#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
+#define PORTB_IN  _SFR_MEM8(0x0628)
+#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
+#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
+#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
+#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
+#define PORTB_REMAP  _SFR_MEM8(0x062E)
+#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
+#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
+#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
+#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
+#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
+#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
+#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
+#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
+
+
+/* PORT (PORTC) - I/O Ports */
+#define PORTC_DIR  _SFR_MEM8(0x0640)
+#define PORTC_DIRSET  _SFR_MEM8(0x0641)
+#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
+#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
+#define PORTC_OUT  _SFR_MEM8(0x0644)
+#define PORTC_OUTSET  _SFR_MEM8(0x0645)
+#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
+#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
+#define PORTC_IN  _SFR_MEM8(0x0648)
+#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
+#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
+#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
+#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
+#define PORTC_REMAP  _SFR_MEM8(0x064E)
+#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
+#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
+#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
+#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
+#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
+#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
+#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
+#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
+
+
+/* PORT (PORTD) - I/O Ports */
+#define PORTD_DIR  _SFR_MEM8(0x0660)
+#define PORTD_DIRSET  _SFR_MEM8(0x0661)
+#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
+#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
+#define PORTD_OUT  _SFR_MEM8(0x0664)
+#define PORTD_OUTSET  _SFR_MEM8(0x0665)
+#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
+#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
+#define PORTD_IN  _SFR_MEM8(0x0668)
+#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
+#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
+#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
+#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
+#define PORTD_REMAP  _SFR_MEM8(0x066E)
+#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
+#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
+#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
+#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
+#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
+#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
+#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
+#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
+
+
+/* PORT (PORTE) - I/O Ports */
+#define PORTE_DIR  _SFR_MEM8(0x0680)
+#define PORTE_DIRSET  _SFR_MEM8(0x0681)
+#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
+#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
+#define PORTE_OUT  _SFR_MEM8(0x0684)
+#define PORTE_OUTSET  _SFR_MEM8(0x0685)
+#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
+#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
+#define PORTE_IN  _SFR_MEM8(0x0688)
+#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
+#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
+#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
+#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
+#define PORTE_REMAP  _SFR_MEM8(0x068E)
+#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
+#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
+#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
+#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
+#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
+#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
+#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
+#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
+
+
+/* PORT (PORTF) - I/O Ports */
+#define PORTF_DIR  _SFR_MEM8(0x06A0)
+#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
+#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
+#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
+#define PORTF_OUT  _SFR_MEM8(0x06A4)
+#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
+#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
+#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
+#define PORTF_IN  _SFR_MEM8(0x06A8)
+#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
+#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
+#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
+#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
+#define PORTF_REMAP  _SFR_MEM8(0x06AE)
+#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
+#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
+#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
+#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
+#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
+#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
+#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
+#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
+
+
+/* PORT (PORTH) - I/O Ports */
+#define PORTH_DIR  _SFR_MEM8(0x06E0)
+#define PORTH_DIRSET  _SFR_MEM8(0x06E1)
+#define PORTH_DIRCLR  _SFR_MEM8(0x06E2)
+#define PORTH_DIRTGL  _SFR_MEM8(0x06E3)
+#define PORTH_OUT  _SFR_MEM8(0x06E4)
+#define PORTH_OUTSET  _SFR_MEM8(0x06E5)
+#define PORTH_OUTCLR  _SFR_MEM8(0x06E6)
+#define PORTH_OUTTGL  _SFR_MEM8(0x06E7)
+#define PORTH_IN  _SFR_MEM8(0x06E8)
+#define PORTH_INTCTRL  _SFR_MEM8(0x06E9)
+#define PORTH_INT0MASK  _SFR_MEM8(0x06EA)
+#define PORTH_INT1MASK  _SFR_MEM8(0x06EB)
+#define PORTH_INTFLAGS  _SFR_MEM8(0x06EC)
+#define PORTH_REMAP  _SFR_MEM8(0x06EE)
+#define PORTH_PIN0CTRL  _SFR_MEM8(0x06F0)
+#define PORTH_PIN1CTRL  _SFR_MEM8(0x06F1)
+#define PORTH_PIN2CTRL  _SFR_MEM8(0x06F2)
+#define PORTH_PIN3CTRL  _SFR_MEM8(0x06F3)
+#define PORTH_PIN4CTRL  _SFR_MEM8(0x06F4)
+#define PORTH_PIN5CTRL  _SFR_MEM8(0x06F5)
+#define PORTH_PIN6CTRL  _SFR_MEM8(0x06F6)
+#define PORTH_PIN7CTRL  _SFR_MEM8(0x06F7)
+
+
+/* PORT (PORTJ) - I/O Ports */
+#define PORTJ_DIR  _SFR_MEM8(0x0700)
+#define PORTJ_DIRSET  _SFR_MEM8(0x0701)
+#define PORTJ_DIRCLR  _SFR_MEM8(0x0702)
+#define PORTJ_DIRTGL  _SFR_MEM8(0x0703)
+#define PORTJ_OUT  _SFR_MEM8(0x0704)
+#define PORTJ_OUTSET  _SFR_MEM8(0x0705)
+#define PORTJ_OUTCLR  _SFR_MEM8(0x0706)
+#define PORTJ_OUTTGL  _SFR_MEM8(0x0707)
+#define PORTJ_IN  _SFR_MEM8(0x0708)
+#define PORTJ_INTCTRL  _SFR_MEM8(0x0709)
+#define PORTJ_INT0MASK  _SFR_MEM8(0x070A)
+#define PORTJ_INT1MASK  _SFR_MEM8(0x070B)
+#define PORTJ_INTFLAGS  _SFR_MEM8(0x070C)
+#define PORTJ_REMAP  _SFR_MEM8(0x070E)
+#define PORTJ_PIN0CTRL  _SFR_MEM8(0x0710)
+#define PORTJ_PIN1CTRL  _SFR_MEM8(0x0711)
+#define PORTJ_PIN2CTRL  _SFR_MEM8(0x0712)
+#define PORTJ_PIN3CTRL  _SFR_MEM8(0x0713)
+#define PORTJ_PIN4CTRL  _SFR_MEM8(0x0714)
+#define PORTJ_PIN5CTRL  _SFR_MEM8(0x0715)
+#define PORTJ_PIN6CTRL  _SFR_MEM8(0x0716)
+#define PORTJ_PIN7CTRL  _SFR_MEM8(0x0717)
+
+
+/* PORT (PORTK) - I/O Ports */
+#define PORTK_DIR  _SFR_MEM8(0x0720)
+#define PORTK_DIRSET  _SFR_MEM8(0x0721)
+#define PORTK_DIRCLR  _SFR_MEM8(0x0722)
+#define PORTK_DIRTGL  _SFR_MEM8(0x0723)
+#define PORTK_OUT  _SFR_MEM8(0x0724)
+#define PORTK_OUTSET  _SFR_MEM8(0x0725)
+#define PORTK_OUTCLR  _SFR_MEM8(0x0726)
+#define PORTK_OUTTGL  _SFR_MEM8(0x0727)
+#define PORTK_IN  _SFR_MEM8(0x0728)
+#define PORTK_INTCTRL  _SFR_MEM8(0x0729)
+#define PORTK_INT0MASK  _SFR_MEM8(0x072A)
+#define PORTK_INT1MASK  _SFR_MEM8(0x072B)
+#define PORTK_INTFLAGS  _SFR_MEM8(0x072C)
+#define PORTK_REMAP  _SFR_MEM8(0x072E)
+#define PORTK_PIN0CTRL  _SFR_MEM8(0x0730)
+#define PORTK_PIN1CTRL  _SFR_MEM8(0x0731)
+#define PORTK_PIN2CTRL  _SFR_MEM8(0x0732)
+#define PORTK_PIN3CTRL  _SFR_MEM8(0x0733)
+#define PORTK_PIN4CTRL  _SFR_MEM8(0x0734)
+#define PORTK_PIN5CTRL  _SFR_MEM8(0x0735)
+#define PORTK_PIN6CTRL  _SFR_MEM8(0x0736)
+#define PORTK_PIN7CTRL  _SFR_MEM8(0x0737)
+
+
+/* PORT (PORTQ) - I/O Ports */
+#define PORTQ_DIR  _SFR_MEM8(0x07C0)
+#define PORTQ_DIRSET  _SFR_MEM8(0x07C1)
+#define PORTQ_DIRCLR  _SFR_MEM8(0x07C2)
+#define PORTQ_DIRTGL  _SFR_MEM8(0x07C3)
+#define PORTQ_OUT  _SFR_MEM8(0x07C4)
+#define PORTQ_OUTSET  _SFR_MEM8(0x07C5)
+#define PORTQ_OUTCLR  _SFR_MEM8(0x07C6)
+#define PORTQ_OUTTGL  _SFR_MEM8(0x07C7)
+#define PORTQ_IN  _SFR_MEM8(0x07C8)
+#define PORTQ_INTCTRL  _SFR_MEM8(0x07C9)
+#define PORTQ_INT0MASK  _SFR_MEM8(0x07CA)
+#define PORTQ_INT1MASK  _SFR_MEM8(0x07CB)
+#define PORTQ_INTFLAGS  _SFR_MEM8(0x07CC)
+#define PORTQ_REMAP  _SFR_MEM8(0x07CE)
+#define PORTQ_PIN0CTRL  _SFR_MEM8(0x07D0)
+#define PORTQ_PIN1CTRL  _SFR_MEM8(0x07D1)
+#define PORTQ_PIN2CTRL  _SFR_MEM8(0x07D2)
+#define PORTQ_PIN3CTRL  _SFR_MEM8(0x07D3)
+#define PORTQ_PIN4CTRL  _SFR_MEM8(0x07D4)
+#define PORTQ_PIN5CTRL  _SFR_MEM8(0x07D5)
+#define PORTQ_PIN6CTRL  _SFR_MEM8(0x07D6)
+#define PORTQ_PIN7CTRL  _SFR_MEM8(0x07D7)
+
+
+/* PORT (PORTR) - I/O Ports */
+#define PORTR_DIR  _SFR_MEM8(0x07E0)
+#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
+#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
+#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
+#define PORTR_OUT  _SFR_MEM8(0x07E4)
+#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
+#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
+#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
+#define PORTR_IN  _SFR_MEM8(0x07E8)
+#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
+#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
+#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
+#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
+#define PORTR_REMAP  _SFR_MEM8(0x07EE)
+#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
+#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
+#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
+#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
+#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
+#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
+#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
+#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
+
+
+/* TC0 (TCC0) - 16-bit Timer/Counter 0 */
+#define TCC0_CTRLA  _SFR_MEM8(0x0800)
+#define TCC0_CTRLB  _SFR_MEM8(0x0801)
+#define TCC0_CTRLC  _SFR_MEM8(0x0802)
+#define TCC0_CTRLD  _SFR_MEM8(0x0803)
+#define TCC0_CTRLE  _SFR_MEM8(0x0804)
+#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
+#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
+#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
+#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
+#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
+#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
+#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
+#define TCC0_TEMP  _SFR_MEM8(0x080F)
+#define TCC0_CNT  _SFR_MEM16(0x0820)
+#define TCC0_CNTL  _SFR_MEM8(0x0820)
+#define TCC0_CNTH  _SFR_MEM8(0x0821)
+#define TCC0_PER  _SFR_MEM16(0x0826)
+#define TCC0_PERL  _SFR_MEM8(0x0826)
+#define TCC0_PERH  _SFR_MEM8(0x0827)
+#define TCC0_CCA  _SFR_MEM16(0x0828)
+#define TCC0_CCAL  _SFR_MEM8(0x0828)
+#define TCC0_CCAH  _SFR_MEM8(0x0829)
+#define TCC0_CCB  _SFR_MEM16(0x082A)
+#define TCC0_CCBL  _SFR_MEM8(0x082A)
+#define TCC0_CCBH  _SFR_MEM8(0x082B)
+#define TCC0_CCC  _SFR_MEM16(0x082C)
+#define TCC0_CCCL  _SFR_MEM8(0x082C)
+#define TCC0_CCCH  _SFR_MEM8(0x082D)
+#define TCC0_CCD  _SFR_MEM16(0x082E)
+#define TCC0_CCDL  _SFR_MEM8(0x082E)
+#define TCC0_CCDH  _SFR_MEM8(0x082F)
+#define TCC0_PERBUF  _SFR_MEM16(0x0836)
+#define TCC0_PERBUFL  _SFR_MEM8(0x0836)
+#define TCC0_PERBUFH  _SFR_MEM8(0x0837)
+#define TCC0_CCABUF  _SFR_MEM16(0x0838)
+#define TCC0_CCABUFL  _SFR_MEM8(0x0838)
+#define TCC0_CCABUFH  _SFR_MEM8(0x0839)
+#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
+#define TCC0_CCBBUFL  _SFR_MEM8(0x083A)
+#define TCC0_CCBBUFH  _SFR_MEM8(0x083B)
+#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
+#define TCC0_CCCBUFL  _SFR_MEM8(0x083C)
+#define TCC0_CCCBUFH  _SFR_MEM8(0x083D)
+#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
+#define TCC0_CCDBUFL  _SFR_MEM8(0x083E)
+#define TCC0_CCDBUFH  _SFR_MEM8(0x083F)
+
+
+/* TC2 (TCC2) - 16-bit Timer/Counter type 2 */
+#define TCC2_CTRLA  _SFR_MEM8(0x0800)
+#define TCC2_CTRLB  _SFR_MEM8(0x0801)
+#define TCC2_CTRLC  _SFR_MEM8(0x0802)
+#define TCC2_CTRLE  _SFR_MEM8(0x0804)
+#define TCC2_INTCTRLA  _SFR_MEM8(0x0806)
+#define TCC2_INTCTRLB  _SFR_MEM8(0x0807)
+#define TCC2_CTRLF  _SFR_MEM8(0x0809)
+#define TCC2_INTFLAGS  _SFR_MEM8(0x080C)
+#define TCC2_LCNT  _SFR_MEM8(0x0820)
+#define TCC2_HCNT  _SFR_MEM8(0x0821)
+#define TCC2_LPER  _SFR_MEM8(0x0826)
+#define TCC2_HPER  _SFR_MEM8(0x0827)
+#define TCC2_LCMPA  _SFR_MEM8(0x0828)
+#define TCC2_HCMPA  _SFR_MEM8(0x0829)
+#define TCC2_LCMPB  _SFR_MEM8(0x082A)
+#define TCC2_HCMPB  _SFR_MEM8(0x082B)
+#define TCC2_LCMPC  _SFR_MEM8(0x082C)
+#define TCC2_HCMPC  _SFR_MEM8(0x082D)
+#define TCC2_LCMPD  _SFR_MEM8(0x082E)
+#define TCC2_HCMPD  _SFR_MEM8(0x082F)
+
+
+/* TC1 (TCC1) - 16-bit Timer/Counter 1 */
+#define TCC1_CTRLA  _SFR_MEM8(0x0840)
+#define TCC1_CTRLB  _SFR_MEM8(0x0841)
+#define TCC1_CTRLC  _SFR_MEM8(0x0842)
+#define TCC1_CTRLD  _SFR_MEM8(0x0843)
+#define TCC1_CTRLE  _SFR_MEM8(0x0844)
+#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
+#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
+#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
+#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
+#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
+#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
+#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
+#define TCC1_TEMP  _SFR_MEM8(0x084F)
+#define TCC1_CNT  _SFR_MEM16(0x0860)
+#define TCC1_CNTL  _SFR_MEM8(0x0860)
+#define TCC1_CNTH  _SFR_MEM8(0x0861)
+#define TCC1_PER  _SFR_MEM16(0x0866)
+#define TCC1_PERL  _SFR_MEM8(0x0866)
+#define TCC1_PERH  _SFR_MEM8(0x0867)
+#define TCC1_CCA  _SFR_MEM16(0x0868)
+#define TCC1_CCAL  _SFR_MEM8(0x0868)
+#define TCC1_CCAH  _SFR_MEM8(0x0869)
+#define TCC1_CCB  _SFR_MEM16(0x086A)
+#define TCC1_CCBL  _SFR_MEM8(0x086A)
+#define TCC1_CCBH  _SFR_MEM8(0x086B)
+#define TCC1_PERBUF  _SFR_MEM16(0x0876)
+#define TCC1_PERBUFL  _SFR_MEM8(0x0876)
+#define TCC1_PERBUFH  _SFR_MEM8(0x0877)
+#define TCC1_CCABUF  _SFR_MEM16(0x0878)
+#define TCC1_CCABUFL  _SFR_MEM8(0x0878)
+#define TCC1_CCABUFH  _SFR_MEM8(0x0879)
+#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
+#define TCC1_CCBBUFL  _SFR_MEM8(0x087A)
+#define TCC1_CCBBUFH  _SFR_MEM8(0x087B)
+
+
+/* AWEX (AWEXC) - Advanced Waveform Extension */
+#define AWEXC_CTRL  _SFR_MEM8(0x0880)
+#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
+#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
+#define AWEXC_STATUS  _SFR_MEM8(0x0884)
+#define AWEXC_STATUSSET  _SFR_MEM8(0x0885)
+#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
+#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
+#define AWEXC_DTLS  _SFR_MEM8(0x0888)
+#define AWEXC_DTHS  _SFR_MEM8(0x0889)
+#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
+#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
+#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
+
+
+/* HIRES (HIRESC) - High-Resolution Extension */
+#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
+
+
+/* USART (USARTC0) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTC0_DATA  _SFR_MEM8(0x08A0)
+#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
+#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
+#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
+#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
+#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
+#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
+
+
+/* USART (USARTC1) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTC1_DATA  _SFR_MEM8(0x08B0)
+#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
+#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
+#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
+#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
+#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
+#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
+
+
+/* SPI (SPIC) - Serial Peripheral Interface */
+#define SPIC_CTRL  _SFR_MEM8(0x08C0)
+#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
+#define SPIC_STATUS  _SFR_MEM8(0x08C2)
+#define SPIC_DATA  _SFR_MEM8(0x08C3)
+
+
+/* IRCOM - IR Communication Module */
+#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
+#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
+#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
+
+
+/* TC0 (TCD0) - 16-bit Timer/Counter 0 */
+#define TCD0_CTRLA  _SFR_MEM8(0x0900)
+#define TCD0_CTRLB  _SFR_MEM8(0x0901)
+#define TCD0_CTRLC  _SFR_MEM8(0x0902)
+#define TCD0_CTRLD  _SFR_MEM8(0x0903)
+#define TCD0_CTRLE  _SFR_MEM8(0x0904)
+#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
+#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
+#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
+#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
+#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
+#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
+#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
+#define TCD0_TEMP  _SFR_MEM8(0x090F)
+#define TCD0_CNT  _SFR_MEM16(0x0920)
+#define TCD0_CNTL  _SFR_MEM8(0x0920)
+#define TCD0_CNTH  _SFR_MEM8(0x0921)
+#define TCD0_PER  _SFR_MEM16(0x0926)
+#define TCD0_PERL  _SFR_MEM8(0x0926)
+#define TCD0_PERH  _SFR_MEM8(0x0927)
+#define TCD0_CCA  _SFR_MEM16(0x0928)
+#define TCD0_CCAL  _SFR_MEM8(0x0928)
+#define TCD0_CCAH  _SFR_MEM8(0x0929)
+#define TCD0_CCB  _SFR_MEM16(0x092A)
+#define TCD0_CCBL  _SFR_MEM8(0x092A)
+#define TCD0_CCBH  _SFR_MEM8(0x092B)
+#define TCD0_CCC  _SFR_MEM16(0x092C)
+#define TCD0_CCCL  _SFR_MEM8(0x092C)
+#define TCD0_CCCH  _SFR_MEM8(0x092D)
+#define TCD0_CCD  _SFR_MEM16(0x092E)
+#define TCD0_CCDL  _SFR_MEM8(0x092E)
+#define TCD0_CCDH  _SFR_MEM8(0x092F)
+#define TCD0_PERBUF  _SFR_MEM16(0x0936)
+#define TCD0_PERBUFL  _SFR_MEM8(0x0936)
+#define TCD0_PERBUFH  _SFR_MEM8(0x0937)
+#define TCD0_CCABUF  _SFR_MEM16(0x0938)
+#define TCD0_CCABUFL  _SFR_MEM8(0x0938)
+#define TCD0_CCABUFH  _SFR_MEM8(0x0939)
+#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
+#define TCD0_CCBBUFL  _SFR_MEM8(0x093A)
+#define TCD0_CCBBUFH  _SFR_MEM8(0x093B)
+#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
+#define TCD0_CCCBUFL  _SFR_MEM8(0x093C)
+#define TCD0_CCCBUFH  _SFR_MEM8(0x093D)
+#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
+#define TCD0_CCDBUFL  _SFR_MEM8(0x093E)
+#define TCD0_CCDBUFH  _SFR_MEM8(0x093F)
+
+
+/* TC2 (TCD2) - 16-bit Timer/Counter type 2 */
+#define TCD2_CTRLA  _SFR_MEM8(0x0900)
+#define TCD2_CTRLB  _SFR_MEM8(0x0901)
+#define TCD2_CTRLC  _SFR_MEM8(0x0902)
+#define TCD2_CTRLE  _SFR_MEM8(0x0904)
+#define TCD2_INTCTRLA  _SFR_MEM8(0x0906)
+#define TCD2_INTCTRLB  _SFR_MEM8(0x0907)
+#define TCD2_CTRLF  _SFR_MEM8(0x0909)
+#define TCD2_INTFLAGS  _SFR_MEM8(0x090C)
+#define TCD2_LCNT  _SFR_MEM8(0x0920)
+#define TCD2_HCNT  _SFR_MEM8(0x0921)
+#define TCD2_LPER  _SFR_MEM8(0x0926)
+#define TCD2_HPER  _SFR_MEM8(0x0927)
+#define TCD2_LCMPA  _SFR_MEM8(0x0928)
+#define TCD2_HCMPA  _SFR_MEM8(0x0929)
+#define TCD2_LCMPB  _SFR_MEM8(0x092A)
+#define TCD2_HCMPB  _SFR_MEM8(0x092B)
+#define TCD2_LCMPC  _SFR_MEM8(0x092C)
+#define TCD2_HCMPC  _SFR_MEM8(0x092D)
+#define TCD2_LCMPD  _SFR_MEM8(0x092E)
+#define TCD2_HCMPD  _SFR_MEM8(0x092F)
+
+
+/* TC1 (TCD1) - 16-bit Timer/Counter 1 */
+#define TCD1_CTRLA  _SFR_MEM8(0x0940)
+#define TCD1_CTRLB  _SFR_MEM8(0x0941)
+#define TCD1_CTRLC  _SFR_MEM8(0x0942)
+#define TCD1_CTRLD  _SFR_MEM8(0x0943)
+#define TCD1_CTRLE  _SFR_MEM8(0x0944)
+#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
+#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
+#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
+#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
+#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
+#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
+#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
+#define TCD1_TEMP  _SFR_MEM8(0x094F)
+#define TCD1_CNT  _SFR_MEM16(0x0960)
+#define TCD1_CNTL  _SFR_MEM8(0x0960)
+#define TCD1_CNTH  _SFR_MEM8(0x0961)
+#define TCD1_PER  _SFR_MEM16(0x0966)
+#define TCD1_PERL  _SFR_MEM8(0x0966)
+#define TCD1_PERH  _SFR_MEM8(0x0967)
+#define TCD1_CCA  _SFR_MEM16(0x0968)
+#define TCD1_CCAL  _SFR_MEM8(0x0968)
+#define TCD1_CCAH  _SFR_MEM8(0x0969)
+#define TCD1_CCB  _SFR_MEM16(0x096A)
+#define TCD1_CCBL  _SFR_MEM8(0x096A)
+#define TCD1_CCBH  _SFR_MEM8(0x096B)
+#define TCD1_PERBUF  _SFR_MEM16(0x0976)
+#define TCD1_PERBUFL  _SFR_MEM8(0x0976)
+#define TCD1_PERBUFH  _SFR_MEM8(0x0977)
+#define TCD1_CCABUF  _SFR_MEM16(0x0978)
+#define TCD1_CCABUFL  _SFR_MEM8(0x0978)
+#define TCD1_CCABUFH  _SFR_MEM8(0x0979)
+#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
+#define TCD1_CCBBUFL  _SFR_MEM8(0x097A)
+#define TCD1_CCBBUFH  _SFR_MEM8(0x097B)
+
+
+/* HIRES (HIRESD) - High-Resolution Extension */
+#define HIRESD_CTRLA  _SFR_MEM8(0x0990)
+
+
+/* USART (USARTD0) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTD0_DATA  _SFR_MEM8(0x09A0)
+#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
+#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
+#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
+#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
+#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
+#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
+
+
+/* USART (USARTD1) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTD1_DATA  _SFR_MEM8(0x09B0)
+#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
+#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
+#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
+#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
+#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
+#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
+
+
+/* SPI (SPID) - Serial Peripheral Interface */
+#define SPID_CTRL  _SFR_MEM8(0x09C0)
+#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
+#define SPID_STATUS  _SFR_MEM8(0x09C2)
+#define SPID_DATA  _SFR_MEM8(0x09C3)
+
+
+/* TC0 (TCE0) - 16-bit Timer/Counter 0 */
+#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
+#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
+#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
+#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
+#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
+#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
+#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
+#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
+#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
+#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
+#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
+#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
+#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
+#define TCE0_CNT  _SFR_MEM16(0x0A20)
+#define TCE0_CNTL  _SFR_MEM8(0x0A20)
+#define TCE0_CNTH  _SFR_MEM8(0x0A21)
+#define TCE0_PER  _SFR_MEM16(0x0A26)
+#define TCE0_PERL  _SFR_MEM8(0x0A26)
+#define TCE0_PERH  _SFR_MEM8(0x0A27)
+#define TCE0_CCA  _SFR_MEM16(0x0A28)
+#define TCE0_CCAL  _SFR_MEM8(0x0A28)
+#define TCE0_CCAH  _SFR_MEM8(0x0A29)
+#define TCE0_CCB  _SFR_MEM16(0x0A2A)
+#define TCE0_CCBL  _SFR_MEM8(0x0A2A)
+#define TCE0_CCBH  _SFR_MEM8(0x0A2B)
+#define TCE0_CCC  _SFR_MEM16(0x0A2C)
+#define TCE0_CCCL  _SFR_MEM8(0x0A2C)
+#define TCE0_CCCH  _SFR_MEM8(0x0A2D)
+#define TCE0_CCD  _SFR_MEM16(0x0A2E)
+#define TCE0_CCDL  _SFR_MEM8(0x0A2E)
+#define TCE0_CCDH  _SFR_MEM8(0x0A2F)
+#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
+#define TCE0_PERBUFL  _SFR_MEM8(0x0A36)
+#define TCE0_PERBUFH  _SFR_MEM8(0x0A37)
+#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
+#define TCE0_CCABUFL  _SFR_MEM8(0x0A38)
+#define TCE0_CCABUFH  _SFR_MEM8(0x0A39)
+#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
+#define TCE0_CCBBUFL  _SFR_MEM8(0x0A3A)
+#define TCE0_CCBBUFH  _SFR_MEM8(0x0A3B)
+#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
+#define TCE0_CCCBUFL  _SFR_MEM8(0x0A3C)
+#define TCE0_CCCBUFH  _SFR_MEM8(0x0A3D)
+#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
+#define TCE0_CCDBUFL  _SFR_MEM8(0x0A3E)
+#define TCE0_CCDBUFH  _SFR_MEM8(0x0A3F)
+
+
+/* TC2 (TCE2) - 16-bit Timer/Counter type 2 */
+#define TCE2_CTRLA  _SFR_MEM8(0x0A00)
+#define TCE2_CTRLB  _SFR_MEM8(0x0A01)
+#define TCE2_CTRLC  _SFR_MEM8(0x0A02)
+#define TCE2_CTRLE  _SFR_MEM8(0x0A04)
+#define TCE2_INTCTRLA  _SFR_MEM8(0x0A06)
+#define TCE2_INTCTRLB  _SFR_MEM8(0x0A07)
+#define TCE2_CTRLF  _SFR_MEM8(0x0A09)
+#define TCE2_INTFLAGS  _SFR_MEM8(0x0A0C)
+#define TCE2_LCNT  _SFR_MEM8(0x0A20)
+#define TCE2_HCNT  _SFR_MEM8(0x0A21)
+#define TCE2_LPER  _SFR_MEM8(0x0A26)
+#define TCE2_HPER  _SFR_MEM8(0x0A27)
+#define TCE2_LCMPA  _SFR_MEM8(0x0A28)
+#define TCE2_HCMPA  _SFR_MEM8(0x0A29)
+#define TCE2_LCMPB  _SFR_MEM8(0x0A2A)
+#define TCE2_HCMPB  _SFR_MEM8(0x0A2B)
+#define TCE2_LCMPC  _SFR_MEM8(0x0A2C)
+#define TCE2_HCMPC  _SFR_MEM8(0x0A2D)
+#define TCE2_LCMPD  _SFR_MEM8(0x0A2E)
+#define TCE2_HCMPD  _SFR_MEM8(0x0A2F)
+
+
+/* TC1 (TCE1) - 16-bit Timer/Counter 1 */
+#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
+#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
+#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
+#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
+#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
+#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
+#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
+#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
+#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
+#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
+#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
+#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
+#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
+#define TCE1_CNT  _SFR_MEM16(0x0A60)
+#define TCE1_CNTL  _SFR_MEM8(0x0A60)
+#define TCE1_CNTH  _SFR_MEM8(0x0A61)
+#define TCE1_PER  _SFR_MEM16(0x0A66)
+#define TCE1_PERL  _SFR_MEM8(0x0A66)
+#define TCE1_PERH  _SFR_MEM8(0x0A67)
+#define TCE1_CCA  _SFR_MEM16(0x0A68)
+#define TCE1_CCAL  _SFR_MEM8(0x0A68)
+#define TCE1_CCAH  _SFR_MEM8(0x0A69)
+#define TCE1_CCB  _SFR_MEM16(0x0A6A)
+#define TCE1_CCBL  _SFR_MEM8(0x0A6A)
+#define TCE1_CCBH  _SFR_MEM8(0x0A6B)
+#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
+#define TCE1_PERBUFL  _SFR_MEM8(0x0A76)
+#define TCE1_PERBUFH  _SFR_MEM8(0x0A77)
+#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
+#define TCE1_CCABUFL  _SFR_MEM8(0x0A78)
+#define TCE1_CCABUFH  _SFR_MEM8(0x0A79)
+#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
+#define TCE1_CCBBUFL  _SFR_MEM8(0x0A7A)
+#define TCE1_CCBBUFH  _SFR_MEM8(0x0A7B)
+
+
+/* AWEX (AWEXE) - Advanced Waveform Extension */
+#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
+#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
+#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
+#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
+#define AWEXE_STATUSSET  _SFR_MEM8(0x0A85)
+#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
+#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
+#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
+#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
+#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
+#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
+#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
+
+
+/* HIRES (HIRESE) - High-Resolution Extension */
+#define HIRESE_CTRLA  _SFR_MEM8(0x0A90)
+
+
+/* USART (USARTE0) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
+#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
+#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
+#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
+#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
+#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
+#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
+
+
+/* USART (USARTE1) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTE1_DATA  _SFR_MEM8(0x0AB0)
+#define USARTE1_STATUS  _SFR_MEM8(0x0AB1)
+#define USARTE1_CTRLA  _SFR_MEM8(0x0AB3)
+#define USARTE1_CTRLB  _SFR_MEM8(0x0AB4)
+#define USARTE1_CTRLC  _SFR_MEM8(0x0AB5)
+#define USARTE1_BAUDCTRLA  _SFR_MEM8(0x0AB6)
+#define USARTE1_BAUDCTRLB  _SFR_MEM8(0x0AB7)
+
+
+/* SPI (SPIE) - Serial Peripheral Interface */
+#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
+#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
+#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
+#define SPIE_DATA  _SFR_MEM8(0x0AC3)
+
+
+/* TC0 (TCF0) - 16-bit Timer/Counter 0 */
+#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
+#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
+#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
+#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
+#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
+#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
+#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
+#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
+#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
+#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
+#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
+#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
+#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
+#define TCF0_CNT  _SFR_MEM16(0x0B20)
+#define TCF0_CNTL  _SFR_MEM8(0x0B20)
+#define TCF0_CNTH  _SFR_MEM8(0x0B21)
+#define TCF0_PER  _SFR_MEM16(0x0B26)
+#define TCF0_PERL  _SFR_MEM8(0x0B26)
+#define TCF0_PERH  _SFR_MEM8(0x0B27)
+#define TCF0_CCA  _SFR_MEM16(0x0B28)
+#define TCF0_CCAL  _SFR_MEM8(0x0B28)
+#define TCF0_CCAH  _SFR_MEM8(0x0B29)
+#define TCF0_CCB  _SFR_MEM16(0x0B2A)
+#define TCF0_CCBL  _SFR_MEM8(0x0B2A)
+#define TCF0_CCBH  _SFR_MEM8(0x0B2B)
+#define TCF0_CCC  _SFR_MEM16(0x0B2C)
+#define TCF0_CCCL  _SFR_MEM8(0x0B2C)
+#define TCF0_CCCH  _SFR_MEM8(0x0B2D)
+#define TCF0_CCD  _SFR_MEM16(0x0B2E)
+#define TCF0_CCDL  _SFR_MEM8(0x0B2E)
+#define TCF0_CCDH  _SFR_MEM8(0x0B2F)
+#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
+#define TCF0_PERBUFL  _SFR_MEM8(0x0B36)
+#define TCF0_PERBUFH  _SFR_MEM8(0x0B37)
+#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
+#define TCF0_CCABUFL  _SFR_MEM8(0x0B38)
+#define TCF0_CCABUFH  _SFR_MEM8(0x0B39)
+#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
+#define TCF0_CCBBUFL  _SFR_MEM8(0x0B3A)
+#define TCF0_CCBBUFH  _SFR_MEM8(0x0B3B)
+#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
+#define TCF0_CCCBUFL  _SFR_MEM8(0x0B3C)
+#define TCF0_CCCBUFH  _SFR_MEM8(0x0B3D)
+#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
+#define TCF0_CCDBUFL  _SFR_MEM8(0x0B3E)
+#define TCF0_CCDBUFH  _SFR_MEM8(0x0B3F)
+
+
+/* TC2 (TCF2) - 16-bit Timer/Counter type 2 */
+#define TCF2_CTRLA  _SFR_MEM8(0x0B00)
+#define TCF2_CTRLB  _SFR_MEM8(0x0B01)
+#define TCF2_CTRLC  _SFR_MEM8(0x0B02)
+#define TCF2_CTRLE  _SFR_MEM8(0x0B04)
+#define TCF2_INTCTRLA  _SFR_MEM8(0x0B06)
+#define TCF2_INTCTRLB  _SFR_MEM8(0x0B07)
+#define TCF2_CTRLF  _SFR_MEM8(0x0B09)
+#define TCF2_INTFLAGS  _SFR_MEM8(0x0B0C)
+#define TCF2_LCNT  _SFR_MEM8(0x0B20)
+#define TCF2_HCNT  _SFR_MEM8(0x0B21)
+#define TCF2_LPER  _SFR_MEM8(0x0B26)
+#define TCF2_HPER  _SFR_MEM8(0x0B27)
+#define TCF2_LCMPA  _SFR_MEM8(0x0B28)
+#define TCF2_HCMPA  _SFR_MEM8(0x0B29)
+#define TCF2_LCMPB  _SFR_MEM8(0x0B2A)
+#define TCF2_HCMPB  _SFR_MEM8(0x0B2B)
+#define TCF2_LCMPC  _SFR_MEM8(0x0B2C)
+#define TCF2_HCMPC  _SFR_MEM8(0x0B2D)
+#define TCF2_LCMPD  _SFR_MEM8(0x0B2E)
+#define TCF2_HCMPD  _SFR_MEM8(0x0B2F)
+
+
+/* TC1 (TCF1) - 16-bit Timer/Counter 1 */
+#define TCF1_CTRLA  _SFR_MEM8(0x0B40)
+#define TCF1_CTRLB  _SFR_MEM8(0x0B41)
+#define TCF1_CTRLC  _SFR_MEM8(0x0B42)
+#define TCF1_CTRLD  _SFR_MEM8(0x0B43)
+#define TCF1_CTRLE  _SFR_MEM8(0x0B44)
+#define TCF1_INTCTRLA  _SFR_MEM8(0x0B46)
+#define TCF1_INTCTRLB  _SFR_MEM8(0x0B47)
+#define TCF1_CTRLFCLR  _SFR_MEM8(0x0B48)
+#define TCF1_CTRLFSET  _SFR_MEM8(0x0B49)
+#define TCF1_CTRLGCLR  _SFR_MEM8(0x0B4A)
+#define TCF1_CTRLGSET  _SFR_MEM8(0x0B4B)
+#define TCF1_INTFLAGS  _SFR_MEM8(0x0B4C)
+#define TCF1_TEMP  _SFR_MEM8(0x0B4F)
+#define TCF1_CNT  _SFR_MEM16(0x0B60)
+#define TCF1_CNTL  _SFR_MEM8(0x0B60)
+#define TCF1_CNTH  _SFR_MEM8(0x0B61)
+#define TCF1_PER  _SFR_MEM16(0x0B66)
+#define TCF1_PERL  _SFR_MEM8(0x0B66)
+#define TCF1_PERH  _SFR_MEM8(0x0B67)
+#define TCF1_CCA  _SFR_MEM16(0x0B68)
+#define TCF1_CCAL  _SFR_MEM8(0x0B68)
+#define TCF1_CCAH  _SFR_MEM8(0x0B69)
+#define TCF1_CCB  _SFR_MEM16(0x0B6A)
+#define TCF1_CCBL  _SFR_MEM8(0x0B6A)
+#define TCF1_CCBH  _SFR_MEM8(0x0B6B)
+#define TCF1_PERBUF  _SFR_MEM16(0x0B76)
+#define TCF1_PERBUFL  _SFR_MEM8(0x0B76)
+#define TCF1_PERBUFH  _SFR_MEM8(0x0B77)
+#define TCF1_CCABUF  _SFR_MEM16(0x0B78)
+#define TCF1_CCABUFL  _SFR_MEM8(0x0B78)
+#define TCF1_CCABUFH  _SFR_MEM8(0x0B79)
+#define TCF1_CCBBUF  _SFR_MEM16(0x0B7A)
+#define TCF1_CCBBUFL  _SFR_MEM8(0x0B7A)
+#define TCF1_CCBBUFH  _SFR_MEM8(0x0B7B)
+
+
+/* HIRES (HIRESF) - High-Resolution Extension */
+#define HIRESF_CTRLA  _SFR_MEM8(0x0B90)
+
+
+/* USART (USARTF0) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
+#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
+#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
+#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
+#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
+#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
+#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
+
+
+/* USART (USARTF1) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTF1_DATA  _SFR_MEM8(0x0BB0)
+#define USARTF1_STATUS  _SFR_MEM8(0x0BB1)
+#define USARTF1_CTRLA  _SFR_MEM8(0x0BB3)
+#define USARTF1_CTRLB  _SFR_MEM8(0x0BB4)
+#define USARTF1_CTRLC  _SFR_MEM8(0x0BB5)
+#define USARTF1_BAUDCTRLA  _SFR_MEM8(0x0BB6)
+#define USARTF1_BAUDCTRLB  _SFR_MEM8(0x0BB7)
+
+
+/* SPI (SPIF) - Serial Peripheral Interface */
+#define SPIF_CTRL  _SFR_MEM8(0x0BC0)
+#define SPIF_INTCTRL  _SFR_MEM8(0x0BC1)
+#define SPIF_STATUS  _SFR_MEM8(0x0BC2)
+#define SPIF_DATA  _SFR_MEM8(0x0BC3)
+
+
+
+/*================== Bitfield Definitions ================== */
+
+/* AC - Analog Comparator */
+/* AC.AC0CTRL  bit masks and bit positions */
+#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
+#define AC_ENABLE_bp  0  /* Enable bit position. */
+#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
+#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
+#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
+#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
+#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
+#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
+#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
+#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
+#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
+#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
+#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
+#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
+#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
+#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
+#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
+#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
+#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
+#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
+#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
+#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
+
+/* AC.AC1CTRL  bit masks and bit positions */
+/* AC_ENABLE  is already defined. */
+/* AC_HYSMODE  is already defined. */
+/* AC_HSMODE  is already defined. */
+/* AC_INTLVL  is already defined. */
+/* AC_INTMODE  is already defined. */
+
+/* AC.AC0MUXCTRL  bit masks and bit positions */
+#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
+#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
+#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
+#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
+#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
+#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
+#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
+#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
+#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
+#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
+#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
+#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
+#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
+#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
+#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
+#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
+
+/* AC.AC1MUXCTRL  bit masks and bit positions */
+/* AC_MUXNEG  is already defined. */
+/* AC_MUXPOS  is already defined. */
+
+/* AC.CTRLA  bit masks and bit positions */
+#define AC_AC0OUT_bm  0x01  /* Analog Comparator 0 Output Enable bit mask. */
+#define AC_AC0OUT_bp  0  /* Analog Comparator 0 Output Enable bit position. */
+#define AC_AC1OUT_bm  0x02  /* Analog Comparator 1 Output Enable bit mask. */
+#define AC_AC1OUT_bp  1  /* Analog Comparator 1 Output Enable bit position. */
+
+/* AC.CTRLB  bit masks and bit positions */
+#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
+#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
+#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
+#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
+#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
+#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
+#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
+#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
+#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
+#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
+#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
+#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
+#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
+#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
+
+/* AC.WINCTRL  bit masks and bit positions */
+#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
+#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
+#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
+#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
+#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
+#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
+#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
+#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
+#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
+#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
+#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
+#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
+#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
+#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
+
+/* AC.STATUS  bit masks and bit positions */
+#define AC_AC0IF_bm  0x01  /* Analog Comparator 0 Interrupt Flag bit mask. */
+#define AC_AC0IF_bp  0  /* Analog Comparator 0 Interrupt Flag bit position. */
+#define AC_AC1IF_bm  0x02  /* Analog Comparator 1 Interrupt Flag bit mask. */
+#define AC_AC1IF_bp  1  /* Analog Comparator 1 Interrupt Flag bit position. */
+#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
+#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
+#define AC_AC0STATE_bm  0x10  /* Analog Comparator 0 State bit mask. */
+#define AC_AC0STATE_bp  4  /* Analog Comparator 0 State bit position. */
+#define AC_AC1STATE_bm  0x20  /* Analog Comparator 1 State bit mask. */
+#define AC_AC1STATE_bp  5  /* Analog Comparator 1 State bit position. */
+#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
+#define AC_WSTATE_gp  6  /* Window Mode State group position. */
+#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
+#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
+#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
+#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
+
+/* AC.CURRCTRL  bit masks and bit positions */
+#define AC_AC0CURR_bm  0x01  /* AC0 Current Source Output Enable bit mask. */
+#define AC_AC0CURR_bp  0  /* AC0 Current Source Output Enable bit position. */
+#define AC_AC1CURR_bm  0x02  /* AC1 Current Source Output Enable bit mask. */
+#define AC_AC1CURR_bp  1  /* AC1 Current Source Output Enable bit position. */
+#define AC_CURRMODE_bm  0x40  /* Current Mode bit mask. */
+#define AC_CURRMODE_bp  6  /* Current Mode bit position. */
+#define AC_CURRENT_bm  0x80  /* Current Source Enable bit mask. */
+#define AC_CURRENT_bp  7  /* Current Source Enable bit position. */
+
+/* AC.CURRCALIB  bit masks and bit positions */
+#define AC_CALIB_gm  0x0F  /* Current Source Calibration group mask. */
+#define AC_CALIB_gp  0  /* Current Source Calibration group position. */
+#define AC_CALIB0_bm  (1<<0)  /* Current Source Calibration bit 0 mask. */
+#define AC_CALIB0_bp  0  /* Current Source Calibration bit 0 position. */
+#define AC_CALIB1_bm  (1<<1)  /* Current Source Calibration bit 1 mask. */
+#define AC_CALIB1_bp  1  /* Current Source Calibration bit 1 position. */
+#define AC_CALIB2_bm  (1<<2)  /* Current Source Calibration bit 2 mask. */
+#define AC_CALIB2_bp  2  /* Current Source Calibration bit 2 position. */
+#define AC_CALIB3_bm  (1<<3)  /* Current Source Calibration bit 3 mask. */
+#define AC_CALIB3_bp  3  /* Current Source Calibration bit 3 position. */
+
+/* ADC - Analog/Digital Converter */
+/* ADC_CH.CTRL  bit masks and bit positions */
+#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
+#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
+#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
+#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
+#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
+#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
+#define ADC_CH_GAIN_gm  0x1C  /* Gain Factor group mask. */
+#define ADC_CH_GAIN_gp  2  /* Gain Factor group position. */
+#define ADC_CH_GAIN0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
+#define ADC_CH_GAIN0_bp  2  /* Gain Factor bit 0 position. */
+#define ADC_CH_GAIN1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
+#define ADC_CH_GAIN1_bp  3  /* Gain Factor bit 1 position. */
+#define ADC_CH_GAIN2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
+#define ADC_CH_GAIN2_bp  4  /* Gain Factor bit 2 position. */
+#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
+#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
+
+/* ADC_CH.MUXCTRL  bit masks and bit positions */
+#define ADC_CH_MUXNEG_gm  0x07  /* MUX selection on Negative ADC input group mask. */
+#define ADC_CH_MUXNEG_gp  0  /* MUX selection on Negative ADC input group position. */
+#define ADC_CH_MUXNEG0_bm  (1<<0)  /* MUX selection on Negative ADC input bit 0 mask. */
+#define ADC_CH_MUXNEG0_bp  0  /* MUX selection on Negative ADC input bit 0 position. */
+#define ADC_CH_MUXNEG1_bm  (1<<1)  /* MUX selection on Negative ADC input bit 1 mask. */
+#define ADC_CH_MUXNEG1_bp  1  /* MUX selection on Negative ADC input bit 1 position. */
+#define ADC_CH_MUXNEG2_bm  (1<<2)  /* MUX selection on Negative ADC input bit 2 mask. */
+#define ADC_CH_MUXNEG2_bp  2  /* MUX selection on Negative ADC input bit 2 position. */
+#define ADC_CH_MUXPOS_gm  0x78  /* MUX selection on Positive ADC input group mask. */
+#define ADC_CH_MUXPOS_gp  3  /* MUX selection on Positive ADC input group position. */
+#define ADC_CH_MUXPOS0_bm  (1<<3)  /* MUX selection on Positive ADC input bit 0 mask. */
+#define ADC_CH_MUXPOS0_bp  3  /* MUX selection on Positive ADC input bit 0 position. */
+#define ADC_CH_MUXPOS1_bm  (1<<4)  /* MUX selection on Positive ADC input bit 1 mask. */
+#define ADC_CH_MUXPOS1_bp  4  /* MUX selection on Positive ADC input bit 1 position. */
+#define ADC_CH_MUXPOS2_bm  (1<<5)  /* MUX selection on Positive ADC input bit 2 mask. */
+#define ADC_CH_MUXPOS2_bp  5  /* MUX selection on Positive ADC input bit 2 position. */
+#define ADC_CH_MUXPOS3_bm  (1<<6)  /* MUX selection on Positive ADC input bit 3 mask. */
+#define ADC_CH_MUXPOS3_bp  6  /* MUX selection on Positive ADC input bit 3 position. */
+#define ADC_CH_MUXINT_gm  0x78  /* MUX selection on Internal ADC input group mask. */
+#define ADC_CH_MUXINT_gp  3  /* MUX selection on Internal ADC input group position. */
+#define ADC_CH_MUXINT0_bm  (1<<3)  /* MUX selection on Internal ADC input bit 0 mask. */
+#define ADC_CH_MUXINT0_bp  3  /* MUX selection on Internal ADC input bit 0 position. */
+#define ADC_CH_MUXINT1_bm  (1<<4)  /* MUX selection on Internal ADC input bit 1 mask. */
+#define ADC_CH_MUXINT1_bp  4  /* MUX selection on Internal ADC input bit 1 position. */
+#define ADC_CH_MUXINT2_bm  (1<<5)  /* MUX selection on Internal ADC input bit 2 mask. */
+#define ADC_CH_MUXINT2_bp  5  /* MUX selection on Internal ADC input bit 2 position. */
+#define ADC_CH_MUXINT3_bm  (1<<6)  /* MUX selection on Internal ADC input bit 3 mask. */
+#define ADC_CH_MUXINT3_bp  6  /* MUX selection on Internal ADC input bit 3 position. */
+
+/* ADC_CH.INTCTRL  bit masks and bit positions */
+#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
+#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
+#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
+#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
+#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
+#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
+#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
+#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
+#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
+#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
+#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
+#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
+
+/* ADC_CH.INTFLAGS  bit masks and bit positions */
+#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
+#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
+
+
+/* ADC_CH.SCAN  bit masks and bit positions */
+#define ADC_CH_SCANNUM_gm  0x0F  /* Number of Channels included in scan group mask. */
+#define ADC_CH_SCANNUM_gp  0  /* Number of Channels included in scan group position. */
+#define ADC_CH_SCANNUM0_bm  (1<<0)  /* Number of Channels included in scan bit 0 mask. */
+#define ADC_CH_SCANNUM0_bp  0  /* Number of Channels included in scan bit 0 position. */
+#define ADC_CH_SCANNUM1_bm  (1<<1)  /* Number of Channels included in scan bit 1 mask. */
+#define ADC_CH_SCANNUM1_bp  1  /* Number of Channels included in scan bit 1 position. */
+#define ADC_CH_SCANNUM2_bm  (1<<2)  /* Number of Channels included in scan bit 2 mask. */
+#define ADC_CH_SCANNUM2_bp  2  /* Number of Channels included in scan bit 2 position. */
+#define ADC_CH_SCANNUM3_bm  (1<<3)  /* Number of Channels included in scan bit 3 mask. */
+#define ADC_CH_SCANNUM3_bp  3  /* Number of Channels included in scan bit 3 position. */
+#define ADC_CH_OFFSET_gm  0xF0  /* Positive MUX setting offset group mask. */
+#define ADC_CH_OFFSET_gp  4  /* Positive MUX setting offset group position. */
+#define ADC_CH_OFFSET0_bm  (1<<4)  /* Positive MUX setting offset bit 0 mask. */
+#define ADC_CH_OFFSET0_bp  4  /* Positive MUX setting offset bit 0 position. */
+#define ADC_CH_OFFSET1_bm  (1<<5)  /* Positive MUX setting offset bit 1 mask. */
+#define ADC_CH_OFFSET1_bp  5  /* Positive MUX setting offset bit 1 position. */
+#define ADC_CH_OFFSET2_bm  (1<<6)  /* Positive MUX setting offset bit 2 mask. */
+#define ADC_CH_OFFSET2_bp  6  /* Positive MUX setting offset bit 2 position. */
+#define ADC_CH_OFFSET3_bm  (1<<7)  /* Positive MUX setting offset bit 3 mask. */
+#define ADC_CH_OFFSET3_bp  7  /* Positive MUX setting offset bit 3 position. */
+
+/* ADC.CTRLA  bit masks and bit positions */
+#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
+#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
+#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
+#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
+#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
+#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
+#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
+#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
+#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
+#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
+#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
+#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
+#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
+#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
+#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
+#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
+#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
+#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
+
+/* ADC.CTRLB  bit masks and bit positions */
+#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
+#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
+#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
+#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
+#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
+#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
+#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
+#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
+#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
+#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
+#define ADC_CURRLIMIT_gm  0x60  /* Current Limitation group mask. */
+#define ADC_CURRLIMIT_gp  5  /* Current Limitation group position. */
+#define ADC_CURRLIMIT0_bm  (1<<5)  /* Current Limitation bit 0 mask. */
+#define ADC_CURRLIMIT0_bp  5  /* Current Limitation bit 0 position. */
+#define ADC_CURRLIMIT1_bm  (1<<6)  /* Current Limitation bit 1 mask. */
+#define ADC_CURRLIMIT1_bp  6  /* Current Limitation bit 1 position. */
+#define ADC_IMPMODE_bm  0x80  /* Gain Stage Impedance Mode bit mask. */
+#define ADC_IMPMODE_bp  7  /* Gain Stage Impedance Mode bit position. */
+
+/* ADC.REFCTRL  bit masks and bit positions */
+#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
+#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
+#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
+#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
+#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
+#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
+#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
+#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
+#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
+#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
+#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
+#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
+
+/* ADC.EVCTRL  bit masks and bit positions */
+#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
+#define ADC_EVACT_gp  0  /* Event Action Select group position. */
+#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
+#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
+#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
+#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
+#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
+#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
+#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
+#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
+#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
+#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
+#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
+#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
+#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
+#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
+#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
+#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
+#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
+#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
+#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
+#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
+
+/* ADC.PRESCALER  bit masks and bit positions */
+#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
+#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
+#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
+#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
+#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
+#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
+#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
+#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
+
+/* ADC.INTFLAGS  bit masks and bit positions */
+#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
+#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
+#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
+#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
+#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
+#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
+#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
+#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
+
+
+
+
+
+
+
+
+/* AES - AES Module */
+/* AES.CTRL  bit masks and bit positions */
+#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
+#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
+#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
+#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
+#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
+#define AES_RESET_bp  5  /* AES Software Reset bit position. */
+#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
+#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
+#define AES_START_bm  0x80  /* Start/Run bit mask. */
+#define AES_START_bp  7  /* Start/Run bit position. */
+
+/* AES.STATUS  bit masks and bit positions */
+#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
+#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
+#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
+#define AES_ERROR_bp  7  /* AES Error bit position. */
+
+
+
+/* AES.INTCTRL  bit masks and bit positions */
+#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
+#define AES_INTLVL_gp  0  /* Interrupt level group position. */
+#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
+#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
+#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
+#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
+
+/* AWEX - Timer/Counter Advanced Waveform Extension */
+/* AWEX.CTRL  bit masks and bit positions */
+#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
+#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
+#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
+#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
+#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
+#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
+#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
+#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
+#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
+#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
+#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
+#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
+
+
+/* AWEX.FDCTRL  bit masks and bit positions */
+#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
+#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
+#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
+#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
+#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
+#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
+#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
+#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
+#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
+#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
+
+/* AWEX.STATUS  bit masks and bit positions */
+#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
+#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
+#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
+#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
+#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
+#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
+
+/* AWEX.STATUSSET  bit masks and bit positions */
+/* AWEX_DTLSBUFV  is already defined. */
+/* AWEX_DTHSBUFV  is already defined. */
+/* AWEX_FDF  is already defined. */
+
+
+
+
+
+
+
+
+/* CLK - Clock System */
+/* CLK.CTRL  bit masks and bit positions */
+#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
+#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
+#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
+#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
+#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
+#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
+#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
+#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
+
+/* CLK.PSCTRL  bit masks and bit positions */
+#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
+#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
+#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
+#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
+#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
+#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
+#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
+#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
+#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
+#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
+#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
+#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
+#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
+#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
+#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
+#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
+#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
+#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
+
+/* CLK.LOCK  bit masks and bit positions */
+#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
+#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
+
+/* CLK.RTCCTRL  bit masks and bit positions */
+#define CLK_RTCEN_bm  0x01  /* Clock Source Enable bit mask. */
+#define CLK_RTCEN_bp  0  /* Clock Source Enable bit position. */
+#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
+#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
+#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
+#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
+#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
+#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
+#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
+#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
+
+/* CLK.USBCTRL  bit masks and bit positions */
+#define CLK_USBSEN_bm  0x01  /* Clock Source Enable bit mask. */
+#define CLK_USBSEN_bp  0  /* Clock Source Enable bit position. */
+#define CLK_USBSRC_gm  0x06  /* Clock Source group mask. */
+#define CLK_USBSRC_gp  1  /* Clock Source group position. */
+#define CLK_USBSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
+#define CLK_USBSRC0_bp  1  /* Clock Source bit 0 position. */
+#define CLK_USBSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
+#define CLK_USBSRC1_bp  2  /* Clock Source bit 1 position. */
+#define CLK_USBPSDIV_gm  0x38  /* Prescaler Division Factor group mask. */
+#define CLK_USBPSDIV_gp  3  /* Prescaler Division Factor group position. */
+#define CLK_USBPSDIV0_bm  (1<<3)  /* Prescaler Division Factor bit 0 mask. */
+#define CLK_USBPSDIV0_bp  3  /* Prescaler Division Factor bit 0 position. */
+#define CLK_USBPSDIV1_bm  (1<<4)  /* Prescaler Division Factor bit 1 mask. */
+#define CLK_USBPSDIV1_bp  4  /* Prescaler Division Factor bit 1 position. */
+#define CLK_USBPSDIV2_bm  (1<<5)  /* Prescaler Division Factor bit 2 mask. */
+#define CLK_USBPSDIV2_bp  5  /* Prescaler Division Factor bit 2 position. */
+
+/* CPU - CPU */
+/* CPU.CCP  bit masks and bit positions */
+#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
+#define CPU_CCP_gp  0  /* CCP signature group position. */
+#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
+#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
+#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
+#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
+#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
+#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
+#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
+#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
+#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
+#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
+#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
+#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
+#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
+#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
+#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
+#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
+
+
+
+
+
+
+
+
+/* CPU.SREG  bit masks and bit positions */
+#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
+#define CPU_C_bp  0  /* Carry Flag bit position. */
+#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
+#define CPU_Z_bp  1  /* Zero Flag bit position. */
+#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
+#define CPU_N_bp  2  /* Negative Flag bit position. */
+#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
+#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
+#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
+#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
+#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
+#define CPU_H_bp  5  /* Half Carry Flag bit position. */
+#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
+#define CPU_T_bp  6  /* Transfer Bit bit position. */
+#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
+#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
+
+/* CRC - Cyclic Redundancy Checker */
+/* CRC.CTRL  bit masks and bit positions */
+#define CRC_SOURCE_gm  0x0F  /* Input Source group mask. */
+#define CRC_SOURCE_gp  0  /* Input Source group position. */
+#define CRC_SOURCE0_bm  (1<<0)  /* Input Source bit 0 mask. */
+#define CRC_SOURCE0_bp  0  /* Input Source bit 0 position. */
+#define CRC_SOURCE1_bm  (1<<1)  /* Input Source bit 1 mask. */
+#define CRC_SOURCE1_bp  1  /* Input Source bit 1 position. */
+#define CRC_SOURCE2_bm  (1<<2)  /* Input Source bit 2 mask. */
+#define CRC_SOURCE2_bp  2  /* Input Source bit 2 position. */
+#define CRC_SOURCE3_bm  (1<<3)  /* Input Source bit 3 mask. */
+#define CRC_SOURCE3_bp  3  /* Input Source bit 3 position. */
+#define CRC_CRC32_bm  0x20  /* CRC Mode bit mask. */
+#define CRC_CRC32_bp  5  /* CRC Mode bit position. */
+#define CRC_RESET_gm  0xC0  /* Reset group mask. */
+#define CRC_RESET_gp  6  /* Reset group position. */
+#define CRC_RESET0_bm  (1<<6)  /* Reset bit 0 mask. */
+#define CRC_RESET0_bp  6  /* Reset bit 0 position. */
+#define CRC_RESET1_bm  (1<<7)  /* Reset bit 1 mask. */
+#define CRC_RESET1_bp  7  /* Reset bit 1 position. */
+
+/* CRC.STATUS  bit masks and bit positions */
+#define CRC_BUSY_bm  0x01  /* Busy bit mask. */
+#define CRC_BUSY_bp  0  /* Busy bit position. */
+#define CRC_ZERO_bm  0x02  /* Zero detection bit mask. */
+#define CRC_ZERO_bp  1  /* Zero detection bit position. */
+
+
+
+
+
+
+/* DAC - Digital/Analog Converter */
+/* DAC.CTRLA  bit masks and bit positions */
+#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
+#define DAC_ENABLE_bp  0  /* Enable bit position. */
+#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
+#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
+#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
+#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
+#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
+#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
+#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
+#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
+
+/* DAC.CTRLB  bit masks and bit positions */
+#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
+#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
+#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
+#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
+#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
+#define DAC_CHSEL_gp  5  /* Channel Select group position. */
+#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
+#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
+#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
+#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
+
+/* DAC.CTRLC  bit masks and bit positions */
+#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
+#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
+#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
+#define DAC_REFSEL_gp  3  /* Reference Select group position. */
+#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
+#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
+#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
+#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
+
+/* DAC.EVCTRL  bit masks and bit positions */
+#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
+#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
+#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
+#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
+#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
+#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
+#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
+#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
+#define DAC_EVSPLIT_bm  0x08  /* Separate Event Channel Input for Channel 1 bit mask. */
+#define DAC_EVSPLIT_bp  3  /* Separate Event Channel Input for Channel 1 bit position. */
+
+/* DAC.STATUS  bit masks and bit positions */
+#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
+#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
+#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
+#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
+
+/* DAC.CH0GAINCAL  bit masks and bit positions */
+#define DAC_CH0GAINCAL_gm  0x7F  /* Gain Calibration group mask. */
+#define DAC_CH0GAINCAL_gp  0  /* Gain Calibration group position. */
+#define DAC_CH0GAINCAL0_bm  (1<<0)  /* Gain Calibration bit 0 mask. */
+#define DAC_CH0GAINCAL0_bp  0  /* Gain Calibration bit 0 position. */
+#define DAC_CH0GAINCAL1_bm  (1<<1)  /* Gain Calibration bit 1 mask. */
+#define DAC_CH0GAINCAL1_bp  1  /* Gain Calibration bit 1 position. */
+#define DAC_CH0GAINCAL2_bm  (1<<2)  /* Gain Calibration bit 2 mask. */
+#define DAC_CH0GAINCAL2_bp  2  /* Gain Calibration bit 2 position. */
+#define DAC_CH0GAINCAL3_bm  (1<<3)  /* Gain Calibration bit 3 mask. */
+#define DAC_CH0GAINCAL3_bp  3  /* Gain Calibration bit 3 position. */
+#define DAC_CH0GAINCAL4_bm  (1<<4)  /* Gain Calibration bit 4 mask. */
+#define DAC_CH0GAINCAL4_bp  4  /* Gain Calibration bit 4 position. */
+#define DAC_CH0GAINCAL5_bm  (1<<5)  /* Gain Calibration bit 5 mask. */
+#define DAC_CH0GAINCAL5_bp  5  /* Gain Calibration bit 5 position. */
+#define DAC_CH0GAINCAL6_bm  (1<<6)  /* Gain Calibration bit 6 mask. */
+#define DAC_CH0GAINCAL6_bp  6  /* Gain Calibration bit 6 position. */
+
+/* DAC.CH0OFFSETCAL  bit masks and bit positions */
+#define DAC_CH0OFFSETCAL_gm  0x7F  /* Offset Calibration group mask. */
+#define DAC_CH0OFFSETCAL_gp  0  /* Offset Calibration group position. */
+#define DAC_CH0OFFSETCAL0_bm  (1<<0)  /* Offset Calibration bit 0 mask. */
+#define DAC_CH0OFFSETCAL0_bp  0  /* Offset Calibration bit 0 position. */
+#define DAC_CH0OFFSETCAL1_bm  (1<<1)  /* Offset Calibration bit 1 mask. */
+#define DAC_CH0OFFSETCAL1_bp  1  /* Offset Calibration bit 1 position. */
+#define DAC_CH0OFFSETCAL2_bm  (1<<2)  /* Offset Calibration bit 2 mask. */
+#define DAC_CH0OFFSETCAL2_bp  2  /* Offset Calibration bit 2 position. */
+#define DAC_CH0OFFSETCAL3_bm  (1<<3)  /* Offset Calibration bit 3 mask. */
+#define DAC_CH0OFFSETCAL3_bp  3  /* Offset Calibration bit 3 position. */
+#define DAC_CH0OFFSETCAL4_bm  (1<<4)  /* Offset Calibration bit 4 mask. */
+#define DAC_CH0OFFSETCAL4_bp  4  /* Offset Calibration bit 4 position. */
+#define DAC_CH0OFFSETCAL5_bm  (1<<5)  /* Offset Calibration bit 5 mask. */
+#define DAC_CH0OFFSETCAL5_bp  5  /* Offset Calibration bit 5 position. */
+#define DAC_CH0OFFSETCAL6_bm  (1<<6)  /* Offset Calibration bit 6 mask. */
+#define DAC_CH0OFFSETCAL6_bp  6  /* Offset Calibration bit 6 position. */
+
+/* DAC.CH1GAINCAL  bit masks and bit positions */
+#define DAC_CH1GAINCAL_gm  0x7F  /* Gain Calibration group mask. */
+#define DAC_CH1GAINCAL_gp  0  /* Gain Calibration group position. */
+#define DAC_CH1GAINCAL0_bm  (1<<0)  /* Gain Calibration bit 0 mask. */
+#define DAC_CH1GAINCAL0_bp  0  /* Gain Calibration bit 0 position. */
+#define DAC_CH1GAINCAL1_bm  (1<<1)  /* Gain Calibration bit 1 mask. */
+#define DAC_CH1GAINCAL1_bp  1  /* Gain Calibration bit 1 position. */
+#define DAC_CH1GAINCAL2_bm  (1<<2)  /* Gain Calibration bit 2 mask. */
+#define DAC_CH1GAINCAL2_bp  2  /* Gain Calibration bit 2 position. */
+#define DAC_CH1GAINCAL3_bm  (1<<3)  /* Gain Calibration bit 3 mask. */
+#define DAC_CH1GAINCAL3_bp  3  /* Gain Calibration bit 3 position. */
+#define DAC_CH1GAINCAL4_bm  (1<<4)  /* Gain Calibration bit 4 mask. */
+#define DAC_CH1GAINCAL4_bp  4  /* Gain Calibration bit 4 position. */
+#define DAC_CH1GAINCAL5_bm  (1<<5)  /* Gain Calibration bit 5 mask. */
+#define DAC_CH1GAINCAL5_bp  5  /* Gain Calibration bit 5 position. */
+#define DAC_CH1GAINCAL6_bm  (1<<6)  /* Gain Calibration bit 6 mask. */
+#define DAC_CH1GAINCAL6_bp  6  /* Gain Calibration bit 6 position. */
+
+/* DAC.CH1OFFSETCAL  bit masks and bit positions */
+#define DAC_CH1OFFSETCAL_gm  0x7F  /* Offset Calibration group mask. */
+#define DAC_CH1OFFSETCAL_gp  0  /* Offset Calibration group position. */
+#define DAC_CH1OFFSETCAL0_bm  (1<<0)  /* Offset Calibration bit 0 mask. */
+#define DAC_CH1OFFSETCAL0_bp  0  /* Offset Calibration bit 0 position. */
+#define DAC_CH1OFFSETCAL1_bm  (1<<1)  /* Offset Calibration bit 1 mask. */
+#define DAC_CH1OFFSETCAL1_bp  1  /* Offset Calibration bit 1 position. */
+#define DAC_CH1OFFSETCAL2_bm  (1<<2)  /* Offset Calibration bit 2 mask. */
+#define DAC_CH1OFFSETCAL2_bp  2  /* Offset Calibration bit 2 position. */
+#define DAC_CH1OFFSETCAL3_bm  (1<<3)  /* Offset Calibration bit 3 mask. */
+#define DAC_CH1OFFSETCAL3_bp  3  /* Offset Calibration bit 3 position. */
+#define DAC_CH1OFFSETCAL4_bm  (1<<4)  /* Offset Calibration bit 4 mask. */
+#define DAC_CH1OFFSETCAL4_bp  4  /* Offset Calibration bit 4 position. */
+#define DAC_CH1OFFSETCAL5_bm  (1<<5)  /* Offset Calibration bit 5 mask. */
+#define DAC_CH1OFFSETCAL5_bp  5  /* Offset Calibration bit 5 position. */
+#define DAC_CH1OFFSETCAL6_bm  (1<<6)  /* Offset Calibration bit 6 mask. */
+#define DAC_CH1OFFSETCAL6_bp  6  /* Offset Calibration bit 6 position. */
+
+
+
+/* DFLL - DFLL */
+/* DFLL.CTRL  bit masks and bit positions */
+#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
+#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
+
+/* DFLL.CALA  bit masks and bit positions */
+#define DFLL_CALL_gm  0x7F  /* DFLL Calibration Value A group mask. */
+#define DFLL_CALL_gp  0  /* DFLL Calibration Value A group position. */
+#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration Value A bit 0 mask. */
+#define DFLL_CALL0_bp  0  /* DFLL Calibration Value A bit 0 position. */
+#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration Value A bit 1 mask. */
+#define DFLL_CALL1_bp  1  /* DFLL Calibration Value A bit 1 position. */
+#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration Value A bit 2 mask. */
+#define DFLL_CALL2_bp  2  /* DFLL Calibration Value A bit 2 position. */
+#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration Value A bit 3 mask. */
+#define DFLL_CALL3_bp  3  /* DFLL Calibration Value A bit 3 position. */
+#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration Value A bit 4 mask. */
+#define DFLL_CALL4_bp  4  /* DFLL Calibration Value A bit 4 position. */
+#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration Value A bit 5 mask. */
+#define DFLL_CALL5_bp  5  /* DFLL Calibration Value A bit 5 position. */
+#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration Value A bit 6 mask. */
+#define DFLL_CALL6_bp  6  /* DFLL Calibration Value A bit 6 position. */
+
+/* DFLL.CALB  bit masks and bit positions */
+#define DFLL_CALH_gm  0x3F  /* DFLL Calibration Value B group mask. */
+#define DFLL_CALH_gp  0  /* DFLL Calibration Value B group position. */
+#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration Value B bit 0 mask. */
+#define DFLL_CALH0_bp  0  /* DFLL Calibration Value B bit 0 position. */
+#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration Value B bit 1 mask. */
+#define DFLL_CALH1_bp  1  /* DFLL Calibration Value B bit 1 position. */
+#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration Value B bit 2 mask. */
+#define DFLL_CALH2_bp  2  /* DFLL Calibration Value B bit 2 position. */
+#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration Value B bit 3 mask. */
+#define DFLL_CALH3_bp  3  /* DFLL Calibration Value B bit 3 position. */
+#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration Value B bit 4 mask. */
+#define DFLL_CALH4_bp  4  /* DFLL Calibration Value B bit 4 position. */
+#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration Value B bit 5 mask. */
+#define DFLL_CALH5_bp  5  /* DFLL Calibration Value B bit 5 position. */
+
+
+
+
+/* DMA - DMA Controller */
+/* DMA_CH.CTRLA  bit masks and bit positions */
+#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
+#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
+#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
+#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
+#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
+#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
+#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
+#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
+#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
+#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
+#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
+#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
+#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
+#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
+#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
+#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
+
+/* DMA_CH.CTRLB  bit masks and bit positions */
+#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
+#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
+#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
+#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
+#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
+#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
+#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
+#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
+#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
+#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
+#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
+#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
+#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
+#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
+#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
+#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
+
+/* DMA_CH.ADDRCTRL  bit masks and bit positions */
+#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
+#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
+#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
+#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
+#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
+#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
+#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
+#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
+#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
+#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
+#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
+#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
+#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
+#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
+#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
+#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
+#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
+#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
+#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
+#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
+#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
+#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
+#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
+#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
+
+/* DMA_CH.TRIGSRC  bit masks and bit positions */
+#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
+#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
+#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
+#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
+#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
+#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
+#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
+#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
+#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
+#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
+#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
+#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
+#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
+#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
+#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
+#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
+#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
+#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
+
+
+
+
+
+
+
+
+
+/* DMA.CTRL  bit masks and bit positions */
+#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
+#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
+#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
+#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
+#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
+#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
+#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
+#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
+#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
+#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
+#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
+#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
+#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
+#define DMA_RESET_bp  6  /* Software Reset bit position. */
+#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
+#define DMA_ENABLE_bp  7  /* Enable bit position. */
+
+/* DMA.INTFLAGS  bit masks and bit positions */
+#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
+
+/* DMA.STATUS  bit masks and bit positions */
+#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
+#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
+#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
+#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
+#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
+#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
+#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
+#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
+#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
+#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
+#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
+#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
+#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
+#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
+#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
+#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
+
+
+/* EBI - External Bus Interface */
+/* EBI_CS.CTRLA  bit masks and bit positions */
+#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
+#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
+#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
+#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
+#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
+#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
+#define EBI_CS_ASIZE_gm  0x7C  /* Address Size group mask. */
+#define EBI_CS_ASIZE_gp  2  /* Address Size group position. */
+#define EBI_CS_ASIZE0_bm  (1<<2)  /* Address Size bit 0 mask. */
+#define EBI_CS_ASIZE0_bp  2  /* Address Size bit 0 position. */
+#define EBI_CS_ASIZE1_bm  (1<<3)  /* Address Size bit 1 mask. */
+#define EBI_CS_ASIZE1_bp  3  /* Address Size bit 1 position. */
+#define EBI_CS_ASIZE2_bm  (1<<4)  /* Address Size bit 2 mask. */
+#define EBI_CS_ASIZE2_bp  4  /* Address Size bit 2 position. */
+#define EBI_CS_ASIZE3_bm  (1<<5)  /* Address Size bit 3 mask. */
+#define EBI_CS_ASIZE3_bp  5  /* Address Size bit 3 position. */
+#define EBI_CS_ASIZE4_bm  (1<<6)  /* Address Size bit 4 mask. */
+#define EBI_CS_ASIZE4_bp  6  /* Address Size bit 4 position. */
+#define EBI_CS_ASPACE_gm  0x7C  /* Legacy name: Address Space group mask. */
+#define EBI_CS_ASPACE_gp  2  /* Legacy name: Address Space group position. */
+#define EBI_CS_ASPACE0_bm  (1<<2)  /* Legacy name: Address Space bit 0 mask. */
+#define EBI_CS_ASPACE0_bp  2  /* Legacy name: Address Space bit 0 position. */
+#define EBI_CS_ASPACE1_bm  (1<<3)  /* Legacy name: Address Space bit 1 mask. */
+#define EBI_CS_ASPACE1_bp  3  /* Legacy name: Address Space bit 1 position. */
+#define EBI_CS_ASPACE2_bm  (1<<4)  /* Legacy name: Address Space bit 2 mask. */
+#define EBI_CS_ASPACE2_bp  4  /* Legacy name: Address Space bit 2 position. */
+#define EBI_CS_ASPACE3_bm  (1<<5)  /* Legacy name: Address Space bit 3 mask. */
+#define EBI_CS_ASPACE3_bp  5  /* Legacy name: Address Space bit 3 position. */
+#define EBI_CS_ASPACE4_bm  (1<<6)  /* Legacy name: Address Space bit 4 mask. */
+#define EBI_CS_ASPACE4_bp  6  /* Legacy name: Address Space bit 4 position. */
+
+/* EBI_CS.CTRLB  bit masks and bit positions */
+#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
+#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
+#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
+#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
+#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
+#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
+#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
+#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
+#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
+#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
+#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
+#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
+#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
+#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
+#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
+#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
+#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
+#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
+
+/* EBI_CS.BASEADDR  bit masks and bit positions */
+#define EBI_CS_BASEADDR_gm  0xFFF0  /* Chip Select Base Address group mask. */
+#define EBI_CS_BASEADDR_gp  4  /* Chip Select Base Address group position. */
+#define EBI_CS_BASEADDR0_bm  (1<<4)  /* Chip Select Base Address bit 0 mask. */
+#define EBI_CS_BASEADDR0_bp  4  /* Chip Select Base Address bit 0 position. */
+#define EBI_CS_BASEADDR1_bm  (1<<5)  /* Chip Select Base Address bit 1 mask. */
+#define EBI_CS_BASEADDR1_bp  5  /* Chip Select Base Address bit 1 position. */
+#define EBI_CS_BASEADDR2_bm  (1<<6)  /* Chip Select Base Address bit 2 mask. */
+#define EBI_CS_BASEADDR2_bp  6  /* Chip Select Base Address bit 2 position. */
+#define EBI_CS_BASEADDR3_bm  (1<<7)  /* Chip Select Base Address bit 3 mask. */
+#define EBI_CS_BASEADDR3_bp  7  /* Chip Select Base Address bit 3 position. */
+#define EBI_CS_BASEADDR4_bm  (1<<8)  /* Chip Select Base Address bit 4 mask. */
+#define EBI_CS_BASEADDR4_bp  8  /* Chip Select Base Address bit 4 position. */
+#define EBI_CS_BASEADDR5_bm  (1<<9)  /* Chip Select Base Address bit 5 mask. */
+#define EBI_CS_BASEADDR5_bp  9  /* Chip Select Base Address bit 5 position. */
+#define EBI_CS_BASEADDR6_bm  (1<<10)  /* Chip Select Base Address bit 6 mask. */
+#define EBI_CS_BASEADDR6_bp  10  /* Chip Select Base Address bit 6 position. */
+#define EBI_CS_BASEADDR7_bm  (1<<11)  /* Chip Select Base Address bit 7 mask. */
+#define EBI_CS_BASEADDR7_bp  11  /* Chip Select Base Address bit 7 position. */
+#define EBI_CS_BASEADDR8_bm  (1<<12)  /* Chip Select Base Address bit 8 mask. */
+#define EBI_CS_BASEADDR8_bp  12  /* Chip Select Base Address bit 8 position. */
+#define EBI_CS_BASEADDR9_bm  (1<<13)  /* Chip Select Base Address bit 9 mask. */
+#define EBI_CS_BASEADDR9_bp  13  /* Chip Select Base Address bit 9 position. */
+#define EBI_CS_BASEADDR10_bm  (1<<14)  /* Chip Select Base Address bit 10 mask. */
+#define EBI_CS_BASEADDR10_bp  14  /* Chip Select Base Address bit 10 position. */
+#define EBI_CS_BASEADDR11_bm  (1<<15)  /* Chip Select Base Address bit 11 mask. */
+#define EBI_CS_BASEADDR11_bp  15  /* Chip Select Base Address bit 11 position. */
+
+/* EBI.CTRL  bit masks and bit positions */
+#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
+#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
+#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
+#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
+#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
+#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
+#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
+#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
+#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
+#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
+#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
+#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
+#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
+#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
+#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
+#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
+#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
+#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
+#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
+#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
+#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
+#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
+#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
+#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
+
+/* EBI.SDRAMCTRLA  bit masks and bit positions */
+#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
+#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
+#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
+#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
+#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
+#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
+#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
+#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
+#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
+#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
+
+
+
+/* EBI.SDRAMCTRLB  bit masks and bit positions */
+#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
+#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
+#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
+#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
+#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
+#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
+#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
+#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
+#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
+#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
+#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
+#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
+#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
+#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
+#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
+#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
+#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
+#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
+#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
+#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
+#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
+#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
+
+/* EBI.SDRAMCTRLC  bit masks and bit positions */
+#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
+#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
+#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
+#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
+#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
+#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
+#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
+#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
+#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
+#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
+#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
+#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
+#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
+#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
+#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
+#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
+#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
+#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
+#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
+#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
+#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
+#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
+
+/* EVSYS - Event System */
+/* EVSYS.CH0MUX  bit masks and bit positions */
+#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
+#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
+#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
+#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
+#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
+#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
+#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
+#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
+#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
+#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
+#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
+#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
+#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
+#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
+#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
+#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
+#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
+#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
+
+/* EVSYS.CH1MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH2MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH3MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH4MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH5MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH6MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH7MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH0CTRL  bit masks and bit positions */
+#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
+#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
+#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
+#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
+#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
+#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
+#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
+#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
+#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
+#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
+#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
+#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
+#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
+#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
+#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
+#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
+#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
+#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
+
+/* EVSYS.CH1CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+
+/* EVSYS.CH2CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+/* EVSYS_QDEN  is already defined. */
+/* EVSYS_QDIEN  is already defined. */
+/* EVSYS_QDIRM  is already defined. */
+
+/* EVSYS.CH3CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+
+/* EVSYS.CH4CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+/* EVSYS_QDEN  is already defined. */
+/* EVSYS_QDIEN  is already defined. */
+/* EVSYS_QDIRM  is already defined. */
+
+/* EVSYS.CH5CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+
+/* EVSYS.CH6CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+
+/* EVSYS.CH7CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+
+
+
+/* FUSE - Fuses and Lockbits */
+/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
+#define NVM_FUSES_JTAGUID_gm  0xFF  /* JTAG User ID group mask. */
+#define NVM_FUSES_JTAGUID_gp  0  /* JTAG User ID group position. */
+#define NVM_FUSES_JTAGUID0_bm  (1<<0)  /* JTAG User ID bit 0 mask. */
+#define NVM_FUSES_JTAGUID0_bp  0  /* JTAG User ID bit 0 position. */
+#define NVM_FUSES_JTAGUID1_bm  (1<<1)  /* JTAG User ID bit 1 mask. */
+#define NVM_FUSES_JTAGUID1_bp  1  /* JTAG User ID bit 1 position. */
+#define NVM_FUSES_JTAGUID2_bm  (1<<2)  /* JTAG User ID bit 2 mask. */
+#define NVM_FUSES_JTAGUID2_bp  2  /* JTAG User ID bit 2 position. */
+#define NVM_FUSES_JTAGUID3_bm  (1<<3)  /* JTAG User ID bit 3 mask. */
+#define NVM_FUSES_JTAGUID3_bp  3  /* JTAG User ID bit 3 position. */
+#define NVM_FUSES_JTAGUID4_bm  (1<<4)  /* JTAG User ID bit 4 mask. */
+#define NVM_FUSES_JTAGUID4_bp  4  /* JTAG User ID bit 4 position. */
+#define NVM_FUSES_JTAGUID5_bm  (1<<5)  /* JTAG User ID bit 5 mask. */
+#define NVM_FUSES_JTAGUID5_bp  5  /* JTAG User ID bit 5 position. */
+#define NVM_FUSES_JTAGUID6_bm  (1<<6)  /* JTAG User ID bit 6 mask. */
+#define NVM_FUSES_JTAGUID6_bp  6  /* JTAG User ID bit 6 position. */
+#define NVM_FUSES_JTAGUID7_bm  (1<<7)  /* JTAG User ID bit 7 mask. */
+#define NVM_FUSES_JTAGUID7_bp  7  /* JTAG User ID bit 7 position. */
+
+/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
+#define NVM_FUSES_WDPER_gm  0x0F  /* Watchdog Timeout Period group mask. */
+#define NVM_FUSES_WDPER_gp  0  /* Watchdog Timeout Period group position. */
+#define NVM_FUSES_WDPER0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDPER0_bp  0  /* Watchdog Timeout Period bit 0 position. */
+#define NVM_FUSES_WDPER1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDPER1_bp  1  /* Watchdog Timeout Period bit 1 position. */
+#define NVM_FUSES_WDPER2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDPER2_bp  2  /* Watchdog Timeout Period bit 2 position. */
+#define NVM_FUSES_WDPER3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDPER3_bp  3  /* Watchdog Timeout Period bit 3 position. */
+#define NVM_FUSES_WDWPER_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
+#define NVM_FUSES_WDWPER_gp  4  /* Watchdog Window Timeout Period group position. */
+#define NVM_FUSES_WDWPER0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDWPER0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
+#define NVM_FUSES_WDWPER1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDWPER1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
+#define NVM_FUSES_WDWPER2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDWPER2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
+#define NVM_FUSES_WDWPER3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDWPER3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
+
+/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
+#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
+#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
+#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
+#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
+#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
+#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
+#define NVM_FUSES_TOSCSEL_bm  0x20  /* Timer Oscillator pin location bit mask. */
+#define NVM_FUSES_TOSCSEL_bp  5  /* Timer Oscillator pin location bit position. */
+#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
+#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
+
+/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
+#define NVM_FUSES_JTAGEN_bm  0x01  /* JTAG Interface Enable bit mask. */
+#define NVM_FUSES_JTAGEN_bp  0  /* JTAG Interface Enable bit position. */
+#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
+#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
+#define NVM_FUSES_STARTUPTIME_gm  0x0C  /* Start-up Time group mask. */
+#define NVM_FUSES_STARTUPTIME_gp  2  /* Start-up Time group position. */
+#define NVM_FUSES_STARTUPTIME0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
+#define NVM_FUSES_STARTUPTIME0_bp  2  /* Start-up Time bit 0 position. */
+#define NVM_FUSES_STARTUPTIME1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
+#define NVM_FUSES_STARTUPTIME1_bp  3  /* Start-up Time bit 1 position. */
+#define NVM_FUSES_RSTDISBL_bm  0x10  /* External Reset Disable bit mask. */
+#define NVM_FUSES_RSTDISBL_bp  4  /* External Reset Disable bit position. */
+
+/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
+#define NVM_FUSES_BODLVL_gm  0x07  /* Brownout Detection Voltage Level group mask. */
+#define NVM_FUSES_BODLVL_gp  0  /* Brownout Detection Voltage Level group position. */
+#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brownout Detection Voltage Level bit 0 mask. */
+#define NVM_FUSES_BODLVL0_bp  0  /* Brownout Detection Voltage Level bit 0 position. */
+#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brownout Detection Voltage Level bit 1 mask. */
+#define NVM_FUSES_BODLVL1_bp  1  /* Brownout Detection Voltage Level bit 1 position. */
+#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brownout Detection Voltage Level bit 2 mask. */
+#define NVM_FUSES_BODLVL2_bp  2  /* Brownout Detection Voltage Level bit 2 position. */
+#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
+#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
+#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
+#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
+#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
+#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
+#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
+#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+/* HIRES - Timer/Counter High-Resolution Extension */
+/* HIRES.CTRLA  bit masks and bit positions */
+#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
+#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
+#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
+#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
+#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
+#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
+#define HIRES_HRPLUS_bm  0x04  /* High Resolution Plus bit mask. */
+#define HIRES_HRPLUS_bp  2  /* High Resolution Plus bit position. */
+
+/* IRCOM - IR Communication Module */
+/* IRCOM.CTRL  bit masks and bit positions */
+#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
+#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
+#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
+#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
+#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
+#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
+#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
+#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
+#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
+#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
+
+
+
+/* LOCKBIT - Fuses and Lockbits */
+/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
+#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
+#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
+#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
+#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
+#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
+#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
+#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
+#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
+#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
+#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
+#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
+#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
+#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
+#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
+
+
+
+
+
+
+/* MCU - MCU Control */
+/* MCU.MCUCR  bit masks and bit positions */
+#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
+#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
+
+/* MCU.ANAINIT  bit masks and bit positions */
+#define MCU_STARTUPDLYA_gm  0x03  /* Analog startup delay Port A group mask. */
+#define MCU_STARTUPDLYA_gp  0  /* Analog startup delay Port A group position. */
+#define MCU_STARTUPDLYA0_bm  (1<<0)  /* Analog startup delay Port A bit 0 mask. */
+#define MCU_STARTUPDLYA0_bp  0  /* Analog startup delay Port A bit 0 position. */
+#define MCU_STARTUPDLYA1_bm  (1<<1)  /* Analog startup delay Port A bit 1 mask. */
+#define MCU_STARTUPDLYA1_bp  1  /* Analog startup delay Port A bit 1 position. */
+#define MCU_STARTUPDLYB_gm  0x0C  /* Analog startup delay Port B group mask. */
+#define MCU_STARTUPDLYB_gp  2  /* Analog startup delay Port B group position. */
+#define MCU_STARTUPDLYB0_bm  (1<<2)  /* Analog startup delay Port B bit 0 mask. */
+#define MCU_STARTUPDLYB0_bp  2  /* Analog startup delay Port B bit 0 position. */
+#define MCU_STARTUPDLYB1_bm  (1<<3)  /* Analog startup delay Port B bit 1 mask. */
+#define MCU_STARTUPDLYB1_bp  3  /* Analog startup delay Port B bit 1 position. */
+
+/* MCU.EVSYSLOCK  bit masks and bit positions */
+#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
+#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
+#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
+#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
+
+/* MCU.AWEXLOCK  bit masks and bit positions */
+#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
+#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
+#define MCU_AWEXDLOCK_bm  0x02  /* AWeX on T/C D0 Lock bit mask. */
+#define MCU_AWEXDLOCK_bp  1  /* AWeX on T/C D0 Lock bit position. */
+#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
+#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
+#define MCU_AWEXFLOCK_bm  0x08  /* AWeX on T/C F0 Lock bit mask. */
+#define MCU_AWEXFLOCK_bp  3  /* AWeX on T/C F0 Lock bit position. */
+
+
+
+
+
+
+
+/* NVM - Non Volatile Memory Controller */
+/* NVM.CMD  bit masks and bit positions */
+#define NVM_CMD_gm  0x7F  /* Command group mask. */
+#define NVM_CMD_gp  0  /* Command group position. */
+#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
+#define NVM_CMD0_bp  0  /* Command bit 0 position. */
+#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
+#define NVM_CMD1_bp  1  /* Command bit 1 position. */
+#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
+#define NVM_CMD2_bp  2  /* Command bit 2 position. */
+#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
+#define NVM_CMD3_bp  3  /* Command bit 3 position. */
+#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
+#define NVM_CMD4_bp  4  /* Command bit 4 position. */
+#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
+#define NVM_CMD5_bp  5  /* Command bit 5 position. */
+#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
+#define NVM_CMD6_bp  6  /* Command bit 6 position. */
+
+/* NVM.CTRLA  bit masks and bit positions */
+#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
+#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
+
+/* NVM.CTRLB  bit masks and bit positions */
+#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
+#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
+#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
+#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
+#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
+#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
+#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
+#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
+
+/* NVM.INTCTRL  bit masks and bit positions */
+#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
+#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
+#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
+#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
+#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
+#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
+#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
+#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
+#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
+#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
+#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
+#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
+
+/* NVM.STATUS  bit masks and bit positions */
+#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
+#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
+#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
+#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
+#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
+#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
+#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
+#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
+
+/* NVM.LOCKBITS  bit masks and bit positions */
+#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
+#define NVM_LB_gp  0  /* Lock Bits group position. */
+#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
+#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
+#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
+#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
+#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
+#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
+#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
+#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
+#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
+#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
+#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
+#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
+
+/* OSC - Oscillator */
+/* OSC.CTRL  bit masks and bit positions */
+#define OSC_RC2MEN_bm  0x01  /* Internal 2 MHz RC Oscillator Enable bit mask. */
+#define OSC_RC2MEN_bp  0  /* Internal 2 MHz RC Oscillator Enable bit position. */
+#define OSC_RC32MEN_bm  0x02  /* Internal 32 MHz RC Oscillator Enable bit mask. */
+#define OSC_RC32MEN_bp  1  /* Internal 32 MHz RC Oscillator Enable bit position. */
+#define OSC_RC32KEN_bm  0x04  /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
+#define OSC_RC32KEN_bp  2  /* Internal 32.768 kHz RC Oscillator Enable bit position. */
+#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
+#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
+#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
+#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
+
+/* OSC.STATUS  bit masks and bit positions */
+#define OSC_RC2MRDY_bm  0x01  /* Internal 2 MHz RC Oscillator Ready bit mask. */
+#define OSC_RC2MRDY_bp  0  /* Internal 2 MHz RC Oscillator Ready bit position. */
+#define OSC_RC32MRDY_bm  0x02  /* Internal 32 MHz RC Oscillator Ready bit mask. */
+#define OSC_RC32MRDY_bp  1  /* Internal 32 MHz RC Oscillator Ready bit position. */
+#define OSC_RC32KRDY_bm  0x04  /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
+#define OSC_RC32KRDY_bp  2  /* Internal 32.768 kHz RC Oscillator Ready bit position. */
+#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
+#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
+#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
+#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
+
+/* OSC.XOSCCTRL  bit masks and bit positions */
+#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
+#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
+#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
+#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
+#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
+#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
+#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
+#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
+#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
+#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
+#define OSC_XOSCPWR_bm  0x10  /* 16 MHz Crystal Oscillator High Power mode bit mask. */
+#define OSC_XOSCPWR_bp  4  /* 16 MHz Crystal Oscillator High Power mode bit position. */
+#define OSC_X32KLPM_bm  0x20  /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
+#define OSC_X32KLPM_bp  5  /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
+#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
+#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
+#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
+#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
+#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
+#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
+
+/* OSC.XOSCFAIL  bit masks and bit positions */
+#define OSC_XOSCFDEN_bm  0x01  /* XOSC Failure Detection Enable bit mask. */
+#define OSC_XOSCFDEN_bp  0  /* XOSC Failure Detection Enable bit position. */
+#define OSC_XOSCFDIF_bm  0x02  /* XOSC Failure Detection Interrupt Flag bit mask. */
+#define OSC_XOSCFDIF_bp  1  /* XOSC Failure Detection Interrupt Flag bit position. */
+#define OSC_PLLFDEN_bm  0x04  /* PLL Failure Detection Enable bit mask. */
+#define OSC_PLLFDEN_bp  2  /* PLL Failure Detection Enable bit position. */
+#define OSC_PLLFDIF_bm  0x08  /* PLL Failure Detection Interrupt Flag bit mask. */
+#define OSC_PLLFDIF_bp  3  /* PLL Failure Detection Interrupt Flag bit position. */
+
+
+/* OSC.PLLCTRL  bit masks and bit positions */
+#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
+#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
+#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
+#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
+#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
+#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
+#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
+#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
+#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
+#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
+#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
+#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
+#define OSC_PLLDIV_bm  0x20  /* Divide by 2 bit mask. */
+#define OSC_PLLDIV_bp  5  /* Divide by 2 bit position. */
+#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
+#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
+#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
+#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
+#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
+#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
+
+/* OSC.DFLLCTRL  bit masks and bit positions */
+#define OSC_RC2MCREF_bm  0x01  /* 2 MHz DFLL Calibration Reference bit mask. */
+#define OSC_RC2MCREF_bp  0  /* 2 MHz DFLL Calibration Reference bit position. */
+#define OSC_RC32MCREF_gm  0x06  /* 32 MHz DFLL Calibration Reference group mask. */
+#define OSC_RC32MCREF_gp  1  /* 32 MHz DFLL Calibration Reference group position. */
+#define OSC_RC32MCREF0_bm  (1<<1)  /* 32 MHz DFLL Calibration Reference bit 0 mask. */
+#define OSC_RC32MCREF0_bp  1  /* 32 MHz DFLL Calibration Reference bit 0 position. */
+#define OSC_RC32MCREF1_bm  (1<<2)  /* 32 MHz DFLL Calibration Reference bit 1 mask. */
+#define OSC_RC32MCREF1_bp  2  /* 32 MHz DFLL Calibration Reference bit 1 position. */
+
+/* PMIC - Programmable Multi-level Interrupt Controller */
+/* PMIC.STATUS  bit masks and bit positions */
+#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
+#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
+#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
+#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
+#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
+#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
+#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
+#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
+
+/* PMIC.INTPRI  bit masks and bit positions */
+#define PMIC_INTPRI_gm  0xFF  /* Interrupt Priority group mask. */
+#define PMIC_INTPRI_gp  0  /* Interrupt Priority group position. */
+#define PMIC_INTPRI0_bm  (1<<0)  /* Interrupt Priority bit 0 mask. */
+#define PMIC_INTPRI0_bp  0  /* Interrupt Priority bit 0 position. */
+#define PMIC_INTPRI1_bm  (1<<1)  /* Interrupt Priority bit 1 mask. */
+#define PMIC_INTPRI1_bp  1  /* Interrupt Priority bit 1 position. */
+#define PMIC_INTPRI2_bm  (1<<2)  /* Interrupt Priority bit 2 mask. */
+#define PMIC_INTPRI2_bp  2  /* Interrupt Priority bit 2 position. */
+#define PMIC_INTPRI3_bm  (1<<3)  /* Interrupt Priority bit 3 mask. */
+#define PMIC_INTPRI3_bp  3  /* Interrupt Priority bit 3 position. */
+#define PMIC_INTPRI4_bm  (1<<4)  /* Interrupt Priority bit 4 mask. */
+#define PMIC_INTPRI4_bp  4  /* Interrupt Priority bit 4 position. */
+#define PMIC_INTPRI5_bm  (1<<5)  /* Interrupt Priority bit 5 mask. */
+#define PMIC_INTPRI5_bp  5  /* Interrupt Priority bit 5 position. */
+#define PMIC_INTPRI6_bm  (1<<6)  /* Interrupt Priority bit 6 mask. */
+#define PMIC_INTPRI6_bp  6  /* Interrupt Priority bit 6 position. */
+#define PMIC_INTPRI7_bm  (1<<7)  /* Interrupt Priority bit 7 mask. */
+#define PMIC_INTPRI7_bp  7  /* Interrupt Priority bit 7 position. */
+
+/* PMIC.CTRL  bit masks and bit positions */
+#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
+#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
+#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
+#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
+#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
+#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
+#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
+#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
+#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
+#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
+
+
+
+
+
+
+
+
+
+
+/* PORT - I/O Port Configuration */
+/* PORT.INTCTRL  bit masks and bit positions */
+#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
+#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
+#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
+#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
+#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
+#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
+#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
+#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
+#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
+#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
+#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
+#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
+
+
+
+/* PORT.INTFLAGS  bit masks and bit positions */
+#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
+#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
+#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
+#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
+
+/* PORT.REMAP  bit masks and bit positions */
+#define PORT_TC0A_bm  0x01  /* Timer/Counter 0 Output Compare A bit mask. */
+#define PORT_TC0A_bp  0  /* Timer/Counter 0 Output Compare A bit position. */
+#define PORT_TC0B_bm  0x02  /* Timer/Counter 0 Output Compare B bit mask. */
+#define PORT_TC0B_bp  1  /* Timer/Counter 0 Output Compare B bit position. */
+#define PORT_TC0C_bm  0x04  /* Timer/Counter 0 Output Compare C bit mask. */
+#define PORT_TC0C_bp  2  /* Timer/Counter 0 Output Compare C bit position. */
+#define PORT_TC0D_bm  0x08  /* Timer/Counter 0 Output Compare D bit mask. */
+#define PORT_TC0D_bp  3  /* Timer/Counter 0 Output Compare D bit position. */
+#define PORT_USART0_bm  0x10  /* USART0 bit mask. */
+#define PORT_USART0_bp  4  /* USART0 bit position. */
+#define PORT_SPI_bm  0x20  /* SPI bit mask. */
+#define PORT_SPI_bp  5  /* SPI bit position. */
+
+/* PORT.PIN0CTRL  bit masks and bit positions */
+#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
+#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
+#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
+#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
+#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
+#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
+#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
+#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
+#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
+#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
+#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
+#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
+#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
+#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
+#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
+#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
+#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
+#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
+#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
+#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
+
+/* PORT.PIN1CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN2CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN3CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN4CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN5CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN6CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN7CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+
+/* PORTCFG - Port Configuration */
+/* PORTCFG.VPCTRLA  bit masks and bit positions */
+#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
+#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
+#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
+#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
+#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
+#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
+#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
+#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
+#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
+#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
+#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
+#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
+#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
+#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
+#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
+#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
+#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
+#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
+#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
+#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
+
+/* PORTCFG.VPCTRLB  bit masks and bit positions */
+#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
+#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
+#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
+#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
+#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
+#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
+#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
+#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
+#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
+#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
+#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
+#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
+#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
+#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
+#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
+#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
+#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
+#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
+#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
+#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
+
+/* PORTCFG.CLKEVOUT  bit masks and bit positions */
+#define PORTCFG_CLKOUT_gm  0x03  /* Peripheral Clock Output Port group mask. */
+#define PORTCFG_CLKOUT_gp  0  /* Peripheral Clock Output Port group position. */
+#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Peripheral Clock Output Port bit 0 mask. */
+#define PORTCFG_CLKOUT0_bp  0  /* Peripheral Clock Output Port bit 0 position. */
+#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Peripheral Clock Output Port bit 1 mask. */
+#define PORTCFG_CLKOUT1_bp  1  /* Peripheral Clock Output Port bit 1 position. */
+#define PORTCFG_CLKOUTSEL_gm  0x0C  /* Peripheral Clock Output Select group mask. */
+#define PORTCFG_CLKOUTSEL_gp  2  /* Peripheral Clock Output Select group position. */
+#define PORTCFG_CLKOUTSEL0_bm  (1<<2)  /* Peripheral Clock Output Select bit 0 mask. */
+#define PORTCFG_CLKOUTSEL0_bp  2  /* Peripheral Clock Output Select bit 0 position. */
+#define PORTCFG_CLKOUTSEL1_bm  (1<<3)  /* Peripheral Clock Output Select bit 1 mask. */
+#define PORTCFG_CLKOUTSEL1_bp  3  /* Peripheral Clock Output Select bit 1 position. */
+#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
+#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
+#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
+#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
+#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
+#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
+#define PORTCFG_RTCOUT_bm  0x40  /* RTC Clock Output bit mask. */
+#define PORTCFG_RTCOUT_bp  6  /* RTC Clock Output bit position. */
+#define PORTCFG_CLKEVPIN_bm  0x80  /* Peripheral Clock and Event Output pin Select bit mask. */
+#define PORTCFG_CLKEVPIN_bp  7  /* Peripheral Clock and Event Output pin Select bit position. */
+
+/* PORTCFG.EBIOUT  bit masks and bit positions */
+#define PORTCFG_EBICSOUT_gm  0x03  /* EBI Chip Select Output group mask. */
+#define PORTCFG_EBICSOUT_gp  0  /* EBI Chip Select Output group position. */
+#define PORTCFG_EBICSOUT0_bm  (1<<0)  /* EBI Chip Select Output bit 0 mask. */
+#define PORTCFG_EBICSOUT0_bp  0  /* EBI Chip Select Output bit 0 position. */
+#define PORTCFG_EBICSOUT1_bm  (1<<1)  /* EBI Chip Select Output bit 1 mask. */
+#define PORTCFG_EBICSOUT1_bp  1  /* EBI Chip Select Output bit 1 position. */
+#define PORTCFG_EBIADROUT_gm  0x0C  /* EBI Address Output group mask. */
+#define PORTCFG_EBIADROUT_gp  2  /* EBI Address Output group position. */
+#define PORTCFG_EBIADROUT0_bm  (1<<2)  /* EBI Address Output bit 0 mask. */
+#define PORTCFG_EBIADROUT0_bp  2  /* EBI Address Output bit 0 position. */
+#define PORTCFG_EBIADROUT1_bm  (1<<3)  /* EBI Address Output bit 1 mask. */
+#define PORTCFG_EBIADROUT1_bp  3  /* EBI Address Output bit 1 position. */
+
+/* PORTCFG.EVOUTSEL  bit masks and bit positions */
+#define PORTCFG_EVOUTSEL_gm  0x07  /* Event Output Select group mask. */
+#define PORTCFG_EVOUTSEL_gp  0  /* Event Output Select group position. */
+#define PORTCFG_EVOUTSEL0_bm  (1<<0)  /* Event Output Select bit 0 mask. */
+#define PORTCFG_EVOUTSEL0_bp  0  /* Event Output Select bit 0 position. */
+#define PORTCFG_EVOUTSEL1_bm  (1<<1)  /* Event Output Select bit 1 mask. */
+#define PORTCFG_EVOUTSEL1_bp  1  /* Event Output Select bit 1 position. */
+#define PORTCFG_EVOUTSEL2_bm  (1<<2)  /* Event Output Select bit 2 mask. */
+#define PORTCFG_EVOUTSEL2_bp  2  /* Event Output Select bit 2 position. */
+
+/* PR - Power Reduction */
+/* PR.PRGEN  bit masks and bit positions */
+#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
+#define PR_DMA_bp  0  /* DMA-Controller bit position. */
+#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
+#define PR_EVSYS_bp  1  /* Event System bit position. */
+#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
+#define PR_RTC_bp  2  /* Real-time Counter bit position. */
+#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
+#define PR_EBI_bp  3  /* External Bus Interface bit position. */
+#define PR_AES_bm  0x10  /* AES bit mask. */
+#define PR_AES_bp  4  /* AES bit position. */
+#define PR_USB_bm  0x40  /* USB bit mask. */
+#define PR_USB_bp  6  /* USB bit position. */
+
+/* PR.PRPA  bit masks and bit positions */
+#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
+#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
+#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
+#define PR_ADC_bp  1  /* Port A ADC bit position. */
+#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
+#define PR_DAC_bp  2  /* Port A DAC bit position. */
+
+/* PR.PRPB  bit masks and bit positions */
+/* PR_AC  is already defined. */
+/* PR_ADC  is already defined. */
+/* PR_DAC  is already defined. */
+
+/* PR.PRPC  bit masks and bit positions */
+#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
+#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
+#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
+#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
+#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
+#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
+#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
+#define PR_SPI_bp  3  /* Port C SPI bit position. */
+#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
+#define PR_USART0_bp  4  /* Port C USART0 bit position. */
+#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
+#define PR_USART1_bp  5  /* Port C USART1 bit position. */
+#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
+#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
+
+/* PR.PRPD  bit masks and bit positions */
+/* PR_TC0  is already defined. */
+/* PR_TC1  is already defined. */
+/* PR_HIRES  is already defined. */
+/* PR_SPI  is already defined. */
+/* PR_USART0  is already defined. */
+/* PR_USART1  is already defined. */
+/* PR_TWI  is already defined. */
+
+/* PR.PRPE  bit masks and bit positions */
+/* PR_TC0  is already defined. */
+/* PR_TC1  is already defined. */
+/* PR_HIRES  is already defined. */
+/* PR_SPI  is already defined. */
+/* PR_USART0  is already defined. */
+/* PR_USART1  is already defined. */
+/* PR_TWI  is already defined. */
+
+/* PR.PRPF  bit masks and bit positions */
+/* PR_TC0  is already defined. */
+/* PR_TC1  is already defined. */
+/* PR_HIRES  is already defined. */
+/* PR_SPI  is already defined. */
+/* PR_USART0  is already defined. */
+/* PR_USART1  is already defined. */
+/* PR_TWI  is already defined. */
+
+/* RST - Reset */
+/* RST.STATUS  bit masks and bit positions */
+#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
+#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
+#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
+#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
+#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
+#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
+#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
+#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
+#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
+#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
+#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
+#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
+#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
+#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
+
+/* RST.CTRL  bit masks and bit positions */
+#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
+#define RST_SWRST_bp  0  /* Software Reset bit position. */
+
+/* RTC - Real-Time Counter */
+/* RTC.CTRL  bit masks and bit positions */
+#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
+#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
+#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
+#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
+#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
+#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
+#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
+#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
+
+/* RTC.STATUS  bit masks and bit positions */
+#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
+#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
+
+/* RTC.INTCTRL  bit masks and bit positions */
+#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
+#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
+#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
+#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
+#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
+#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
+#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
+#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
+#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
+#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
+#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
+#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
+
+/* RTC.INTFLAGS  bit masks and bit positions */
+#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
+#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
+#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
+#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+/* SLEEP - Sleep Controller */
+/* SLEEP.CTRL  bit masks and bit positions */
+#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
+#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
+#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
+#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
+#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
+#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
+#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
+#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
+#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
+#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
+
+/* SPI - Serial Peripheral Interface */
+/* SPI.CTRL  bit masks and bit positions */
+#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
+#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
+#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
+#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
+#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
+#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
+#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
+#define SPI_MODE_gp  2  /* SPI Mode group position. */
+#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
+#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
+#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
+#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
+#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
+#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
+#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
+#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
+#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
+#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
+#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
+#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
+
+/* SPI.INTCTRL  bit masks and bit positions */
+#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
+#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
+#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
+#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
+#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
+#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
+
+/* SPI.STATUS  bit masks and bit positions */
+#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
+#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
+#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
+#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
+
+
+/* TC - 16-bit Timer/Counter With PWM */
+/* TC0.CTRLA  bit masks and bit positions */
+#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
+#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
+#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
+#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
+#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
+#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
+#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
+#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
+#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
+#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
+
+/* TC0.CTRLB  bit masks and bit positions */
+#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
+#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
+#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
+#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
+#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
+#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
+#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
+#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
+#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
+#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
+#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
+#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
+#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
+#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
+#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
+#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
+
+/* TC0.CTRLC  bit masks and bit positions */
+#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
+#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
+#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
+#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
+#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
+#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
+#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
+#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
+
+/* TC0.CTRLD  bit masks and bit positions */
+#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
+#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
+#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
+#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
+#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
+#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
+#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
+#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
+#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
+#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
+#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
+#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
+#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
+#define TC0_EVACT_gp  5  /* Event Action group position. */
+#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
+#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
+#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
+#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
+#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
+#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
+
+/* TC0.CTRLE  bit masks and bit positions */
+#define TC0_BYTEM_gm  0x03  /* Byte Mode group mask. */
+#define TC0_BYTEM_gp  0  /* Byte Mode group position. */
+#define TC0_BYTEM0_bm  (1<<0)  /* Byte Mode bit 0 mask. */
+#define TC0_BYTEM0_bp  0  /* Byte Mode bit 0 position. */
+#define TC0_BYTEM1_bm  (1<<1)  /* Byte Mode bit 1 mask. */
+#define TC0_BYTEM1_bp  1  /* Byte Mode bit 1 position. */
+
+/* TC0.INTCTRLA  bit masks and bit positions */
+#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
+#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
+#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
+#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
+#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
+#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
+#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
+#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
+#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
+#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
+#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
+#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
+
+/* TC0.INTCTRLB  bit masks and bit positions */
+#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
+#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
+#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
+#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
+#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
+#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
+#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
+#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
+#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
+#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
+#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
+#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
+#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
+#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
+#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
+#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
+#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
+#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
+
+/* TC0.CTRLFCLR  bit masks and bit positions */
+#define TC0_DIR_bm  0x01  /* Direction bit mask. */
+#define TC0_DIR_bp  0  /* Direction bit position. */
+#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
+#define TC0_LUPD_bp  1  /* Lock Update bit position. */
+#define TC0_CMD_gm  0x0C  /* Command group mask. */
+#define TC0_CMD_gp  2  /* Command group position. */
+#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
+#define TC0_CMD0_bp  2  /* Command bit 0 position. */
+#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
+#define TC0_CMD1_bp  3  /* Command bit 1 position. */
+
+/* TC0.CTRLFSET  bit masks and bit positions */
+/* TC0_DIR  is already defined. */
+/* TC0_LUPD  is already defined. */
+/* TC0_CMD  is already defined. */
+
+/* TC0.CTRLGCLR  bit masks and bit positions */
+#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
+#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
+#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
+#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
+#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
+#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
+#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
+#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
+#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
+#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
+
+/* TC0.CTRLGSET  bit masks and bit positions */
+/* TC0_PERBV  is already defined. */
+/* TC0_CCABV  is already defined. */
+/* TC0_CCBBV  is already defined. */
+/* TC0_CCCBV  is already defined. */
+/* TC0_CCDBV  is already defined. */
+
+/* TC0.INTFLAGS  bit masks and bit positions */
+#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
+#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
+#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
+#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
+#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
+#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
+#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
+#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
+#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
+#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
+
+
+
+
+
+
+
+
+
+
+
+
+
+/* TC1.CTRLA  bit masks and bit positions */
+#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
+#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
+#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
+#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
+#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
+#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
+#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
+#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
+#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
+#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
+
+/* TC1.CTRLB  bit masks and bit positions */
+#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
+#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
+#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
+#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
+#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
+#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
+#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
+#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
+#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
+#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
+#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
+#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
+
+/* TC1.CTRLC  bit masks and bit positions */
+#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
+#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
+#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
+#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
+
+/* TC1.CTRLD  bit masks and bit positions */
+#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
+#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
+#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
+#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
+#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
+#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
+#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
+#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
+#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
+#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
+#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
+#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
+#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
+#define TC1_EVACT_gp  5  /* Event Action group position. */
+#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
+#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
+#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
+#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
+#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
+#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
+
+/* TC1.CTRLE  bit masks and bit positions */
+#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
+#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
+
+/* TC1.INTCTRLA  bit masks and bit positions */
+#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
+#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
+#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
+#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
+#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
+#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
+#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
+#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
+#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
+#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
+#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
+#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
+
+/* TC1.INTCTRLB  bit masks and bit positions */
+#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
+#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
+#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
+#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
+#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
+#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
+
+/* TC1.CTRLFCLR  bit masks and bit positions */
+#define TC1_DIR_bm  0x01  /* Direction bit mask. */
+#define TC1_DIR_bp  0  /* Direction bit position. */
+#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
+#define TC1_LUPD_bp  1  /* Lock Update bit position. */
+#define TC1_CMD_gm  0x0C  /* Command group mask. */
+#define TC1_CMD_gp  2  /* Command group position. */
+#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
+#define TC1_CMD0_bp  2  /* Command bit 0 position. */
+#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
+#define TC1_CMD1_bp  3  /* Command bit 1 position. */
+
+/* TC1.CTRLFSET  bit masks and bit positions */
+/* TC1_DIR  is already defined. */
+/* TC1_LUPD  is already defined. */
+/* TC1_CMD  is already defined. */
+
+/* TC1.CTRLGCLR  bit masks and bit positions */
+#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
+#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
+#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
+#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
+#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
+#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
+
+/* TC1.CTRLGSET  bit masks and bit positions */
+/* TC1_PERBV  is already defined. */
+/* TC1_CCABV  is already defined. */
+/* TC1_CCBBV  is already defined. */
+
+/* TC1.INTFLAGS  bit masks and bit positions */
+#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
+#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
+#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
+#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
+#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
+#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
+
+
+
+
+
+
+
+
+
+/* TC2 - 16-bit Timer/Counter type 2 */
+/* TC2.CTRLA  bit masks and bit positions */
+#define TC2_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
+#define TC2_CLKSEL_gp  0  /* Clock Selection group position. */
+#define TC2_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
+#define TC2_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
+#define TC2_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
+#define TC2_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
+#define TC2_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
+#define TC2_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
+#define TC2_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
+#define TC2_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
+
+/* TC2.CTRLB  bit masks and bit positions */
+#define TC2_LCMPAEN_bm  0x01  /* Low Byte Compare A Enable bit mask. */
+#define TC2_LCMPAEN_bp  0  /* Low Byte Compare A Enable bit position. */
+#define TC2_LCMPBEN_bm  0x02  /* Low Byte Compare B Enable bit mask. */
+#define TC2_LCMPBEN_bp  1  /* Low Byte Compare B Enable bit position. */
+#define TC2_LCMPCEN_bm  0x04  /* Low Byte Compare C Enable bit mask. */
+#define TC2_LCMPCEN_bp  2  /* Low Byte Compare C Enable bit position. */
+#define TC2_LCMPDEN_bm  0x08  /* Low Byte Compare D Enable bit mask. */
+#define TC2_LCMPDEN_bp  3  /* Low Byte Compare D Enable bit position. */
+#define TC2_HCMPAEN_bm  0x10  /* High Byte Compare A Enable bit mask. */
+#define TC2_HCMPAEN_bp  4  /* High Byte Compare A Enable bit position. */
+#define TC2_HCMPBEN_bm  0x20  /* High Byte Compare B Enable bit mask. */
+#define TC2_HCMPBEN_bp  5  /* High Byte Compare B Enable bit position. */
+#define TC2_HCMPCEN_bm  0x40  /* High Byte Compare C Enable bit mask. */
+#define TC2_HCMPCEN_bp  6  /* High Byte Compare C Enable bit position. */
+#define TC2_HCMPDEN_bm  0x80  /* High Byte Compare D Enable bit mask. */
+#define TC2_HCMPDEN_bp  7  /* High Byte Compare D Enable bit position. */
+
+/* TC2.CTRLC  bit masks and bit positions */
+#define TC2_LCMPA_bm  0x01  /* Low Byte Compare A Output Value bit mask. */
+#define TC2_LCMPA_bp  0  /* Low Byte Compare A Output Value bit position. */
+#define TC2_LCMPB_bm  0x02  /* Low Byte Compare B Output Value bit mask. */
+#define TC2_LCMPB_bp  1  /* Low Byte Compare B Output Value bit position. */
+#define TC2_LCMPC_bm  0x04  /* Low Byte Compare C Output Value bit mask. */
+#define TC2_LCMPC_bp  2  /* Low Byte Compare C Output Value bit position. */
+#define TC2_LCMPD_bm  0x08  /* Low Byte Compare D Output Value bit mask. */
+#define TC2_LCMPD_bp  3  /* Low Byte Compare D Output Value bit position. */
+#define TC2_HCMPA_bm  0x10  /* High Byte Compare A Output Value bit mask. */
+#define TC2_HCMPA_bp  4  /* High Byte Compare A Output Value bit position. */
+#define TC2_HCMPB_bm  0x20  /* High Byte Compare B Output Value bit mask. */
+#define TC2_HCMPB_bp  5  /* High Byte Compare B Output Value bit position. */
+#define TC2_HCMPC_bm  0x40  /* High Byte Compare C Output Value bit mask. */
+#define TC2_HCMPC_bp  6  /* High Byte Compare C Output Value bit position. */
+#define TC2_HCMPD_bm  0x80  /* High Byte Compare D Output Value bit mask. */
+#define TC2_HCMPD_bp  7  /* High Byte Compare D Output Value bit position. */
+
+/* TC2.CTRLE  bit masks and bit positions */
+#define TC2_BYTEM_gm  0x03  /* Byte Mode group mask. */
+#define TC2_BYTEM_gp  0  /* Byte Mode group position. */
+#define TC2_BYTEM0_bm  (1<<0)  /* Byte Mode bit 0 mask. */
+#define TC2_BYTEM0_bp  0  /* Byte Mode bit 0 position. */
+#define TC2_BYTEM1_bm  (1<<1)  /* Byte Mode bit 1 mask. */
+#define TC2_BYTEM1_bp  1  /* Byte Mode bit 1 position. */
+
+/* TC2.INTCTRLA  bit masks and bit positions */
+#define TC2_LUNFINTLVL_gm  0x03  /* Low Byte Underflow interrupt level group mask. */
+#define TC2_LUNFINTLVL_gp  0  /* Low Byte Underflow interrupt level group position. */
+#define TC2_LUNFINTLVL0_bm  (1<<0)  /* Low Byte Underflow interrupt level bit 0 mask. */
+#define TC2_LUNFINTLVL0_bp  0  /* Low Byte Underflow interrupt level bit 0 position. */
+#define TC2_LUNFINTLVL1_bm  (1<<1)  /* Low Byte Underflow interrupt level bit 1 mask. */
+#define TC2_LUNFINTLVL1_bp  1  /* Low Byte Underflow interrupt level bit 1 position. */
+#define TC2_HUNFINTLVL_gm  0x0C  /* High Byte Underflow Interrupt Level group mask. */
+#define TC2_HUNFINTLVL_gp  2  /* High Byte Underflow Interrupt Level group position. */
+#define TC2_HUNFINTLVL0_bm  (1<<2)  /* High Byte Underflow Interrupt Level bit 0 mask. */
+#define TC2_HUNFINTLVL0_bp  2  /* High Byte Underflow Interrupt Level bit 0 position. */
+#define TC2_HUNFINTLVL1_bm  (1<<3)  /* High Byte Underflow Interrupt Level bit 1 mask. */
+#define TC2_HUNFINTLVL1_bp  3  /* High Byte Underflow Interrupt Level bit 1 position. */
+
+/* TC2.INTCTRLB  bit masks and bit positions */
+#define TC2_LCMPAINTLVL_gm  0x03  /* Low Byte Compare A Interrupt Level group mask. */
+#define TC2_LCMPAINTLVL_gp  0  /* Low Byte Compare A Interrupt Level group position. */
+#define TC2_LCMPAINTLVL0_bm  (1<<0)  /* Low Byte Compare A Interrupt Level bit 0 mask. */
+#define TC2_LCMPAINTLVL0_bp  0  /* Low Byte Compare A Interrupt Level bit 0 position. */
+#define TC2_LCMPAINTLVL1_bm  (1<<1)  /* Low Byte Compare A Interrupt Level bit 1 mask. */
+#define TC2_LCMPAINTLVL1_bp  1  /* Low Byte Compare A Interrupt Level bit 1 position. */
+#define TC2_LCMPBINTLVL_gm  0x0C  /* Low Byte Compare B Interrupt Level group mask. */
+#define TC2_LCMPBINTLVL_gp  2  /* Low Byte Compare B Interrupt Level group position. */
+#define TC2_LCMPBINTLVL0_bm  (1<<2)  /* Low Byte Compare B Interrupt Level bit 0 mask. */
+#define TC2_LCMPBINTLVL0_bp  2  /* Low Byte Compare B Interrupt Level bit 0 position. */
+#define TC2_LCMPBINTLVL1_bm  (1<<3)  /* Low Byte Compare B Interrupt Level bit 1 mask. */
+#define TC2_LCMPBINTLVL1_bp  3  /* Low Byte Compare B Interrupt Level bit 1 position. */
+#define TC2_LCMPCINTLVL_gm  0x30  /* Low Byte Compare C Interrupt Level group mask. */
+#define TC2_LCMPCINTLVL_gp  4  /* Low Byte Compare C Interrupt Level group position. */
+#define TC2_LCMPCINTLVL0_bm  (1<<4)  /* Low Byte Compare C Interrupt Level bit 0 mask. */
+#define TC2_LCMPCINTLVL0_bp  4  /* Low Byte Compare C Interrupt Level bit 0 position. */
+#define TC2_LCMPCINTLVL1_bm  (1<<5)  /* Low Byte Compare C Interrupt Level bit 1 mask. */
+#define TC2_LCMPCINTLVL1_bp  5  /* Low Byte Compare C Interrupt Level bit 1 position. */
+#define TC2_LCMPDINTLVL_gm  0xC0  /* Low Byte Compare D Interrupt Level group mask. */
+#define TC2_LCMPDINTLVL_gp  6  /* Low Byte Compare D Interrupt Level group position. */
+#define TC2_LCMPDINTLVL0_bm  (1<<6)  /* Low Byte Compare D Interrupt Level bit 0 mask. */
+#define TC2_LCMPDINTLVL0_bp  6  /* Low Byte Compare D Interrupt Level bit 0 position. */
+#define TC2_LCMPDINTLVL1_bm  (1<<7)  /* Low Byte Compare D Interrupt Level bit 1 mask. */
+#define TC2_LCMPDINTLVL1_bp  7  /* Low Byte Compare D Interrupt Level bit 1 position. */
+
+/* TC2.CTRLF  bit masks and bit positions */
+#define TC2_CMDEN_gm  0x03  /* Command Enable group mask. */
+#define TC2_CMDEN_gp  0  /* Command Enable group position. */
+#define TC2_CMDEN0_bm  (1<<0)  /* Command Enable bit 0 mask. */
+#define TC2_CMDEN0_bp  0  /* Command Enable bit 0 position. */
+#define TC2_CMDEN1_bm  (1<<1)  /* Command Enable bit 1 mask. */
+#define TC2_CMDEN1_bp  1  /* Command Enable bit 1 position. */
+#define TC2_CMD_gm  0x0C  /* Command group mask. */
+#define TC2_CMD_gp  2  /* Command group position. */
+#define TC2_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
+#define TC2_CMD0_bp  2  /* Command bit 0 position. */
+#define TC2_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
+#define TC2_CMD1_bp  3  /* Command bit 1 position. */
+
+/* TC2.INTFLAGS  bit masks and bit positions */
+#define TC2_LUNFIF_bm  0x01  /* Low Byte Underflow Interrupt Flag bit mask. */
+#define TC2_LUNFIF_bp  0  /* Low Byte Underflow Interrupt Flag bit position. */
+#define TC2_HUNFIF_bm  0x02  /* High Byte Underflow Interrupt Flag bit mask. */
+#define TC2_HUNFIF_bp  1  /* High Byte Underflow Interrupt Flag bit position. */
+#define TC2_LCMPAIF_bm  0x10  /* Low Byte Compare A Interrupt Flag bit mask. */
+#define TC2_LCMPAIF_bp  4  /* Low Byte Compare A Interrupt Flag bit position. */
+#define TC2_LCMPBIF_bm  0x20  /* Low Byte Compare B Interrupt Flag bit mask. */
+#define TC2_LCMPBIF_bp  5  /* Low Byte Compare B Interrupt Flag bit position. */
+#define TC2_LCMPCIF_bm  0x40  /* Low Byte Compare C Interrupt Flag bit mask. */
+#define TC2_LCMPCIF_bp  6  /* Low Byte Compare C Interrupt Flag bit position. */
+#define TC2_LCMPDIF_bm  0x80  /* Low Byte Compare D Interrupt Flag bit mask. */
+#define TC2_LCMPDIF_bp  7  /* Low Byte Compare D Interrupt Flag bit position. */
+
+
+
+
+
+
+
+
+
+
+
+
+
+/* TWI - Two-Wire Interface */
+/* TWI_MASTER.CTRLA  bit masks and bit positions */
+#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
+#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
+#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
+#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
+#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
+#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
+#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
+#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
+#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
+#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
+#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
+#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
+
+/* TWI_MASTER.CTRLB  bit masks and bit positions */
+#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
+#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
+#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
+#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
+#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus timeout group mask. */
+#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus timeout group position. */
+#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus timeout bit 0 mask. */
+#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus timeout bit 0 position. */
+#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus timeout bit 1 mask. */
+#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus timeout bit 1 position. */
+
+/* TWI_MASTER.CTRLC  bit masks and bit positions */
+#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
+#define TWI_MASTER_CMD_gp  0  /* Command group position. */
+#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
+#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
+#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
+#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
+#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
+#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
+
+/* TWI_MASTER.STATUS  bit masks and bit positions */
+#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
+#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
+#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
+#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
+#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
+#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
+#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
+#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
+#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
+#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
+#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
+#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
+#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
+#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
+#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
+#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
+#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
+#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
+
+
+
+
+/* TWI_SLAVE.CTRLA  bit masks and bit positions */
+#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
+#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
+#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
+#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
+#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
+#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
+#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
+#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
+#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
+#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
+#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
+#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
+#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
+#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
+#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
+#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
+
+/* TWI_SLAVE.CTRLB  bit masks and bit positions */
+#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
+#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
+#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
+#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
+#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
+#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
+#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
+#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
+
+/* TWI_SLAVE.STATUS  bit masks and bit positions */
+#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
+#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
+#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
+#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
+#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
+#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
+#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
+#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
+#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
+#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
+#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
+#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
+#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
+#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
+#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
+#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
+
+
+
+/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
+#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
+#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
+#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
+#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
+#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
+#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
+#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
+#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
+#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
+#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
+#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
+#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
+#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
+#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
+#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
+#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
+#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
+#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
+
+/* TWI.CTRL  bit masks and bit positions */
+#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
+#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
+#define TWI_SDAHOLD_gm  0x06  /* SDA Hold Time Enable group mask. */
+#define TWI_SDAHOLD_gp  1  /* SDA Hold Time Enable group position. */
+#define TWI_SDAHOLD0_bm  (1<<1)  /* SDA Hold Time Enable bit 0 mask. */
+#define TWI_SDAHOLD0_bp  1  /* SDA Hold Time Enable bit 0 position. */
+#define TWI_SDAHOLD1_bm  (1<<2)  /* SDA Hold Time Enable bit 1 mask. */
+#define TWI_SDAHOLD1_bp  2  /* SDA Hold Time Enable bit 1 position. */
+
+
+/* USART - Universal Asynchronous Receiver-Transmitter */
+/* USART.STATUS  bit masks and bit positions */
+#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
+#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
+#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
+#define USART_PERR_bp  2  /* Parity Error bit position. */
+#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
+#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
+#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
+#define USART_FERR_bp  4  /* Frame Error bit position. */
+#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
+#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
+#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
+#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
+#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
+#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
+
+/* USART.CTRLA  bit masks and bit positions */
+#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
+#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
+#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
+#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
+#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
+#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
+#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
+#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
+#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
+#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
+#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
+#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
+#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
+#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
+#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
+#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
+#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
+#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
+
+/* USART.CTRLB  bit masks and bit positions */
+#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
+#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
+#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
+#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
+#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
+#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
+#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
+#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
+#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
+#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
+
+/* USART.CTRLC  bit masks and bit positions */
+#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
+#define USART_CHSIZE_gp  0  /* Character Size group position. */
+#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
+#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
+#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
+#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
+#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
+#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
+#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
+#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
+#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
+#define USART_PMODE_gp  4  /* Parity Mode group position. */
+#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
+#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
+#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
+#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
+#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
+#define USART_CMODE_gp  6  /* Communication Mode group position. */
+#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
+#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
+#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
+#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
+
+/* USART.BAUDCTRLA  bit masks and bit positions */
+#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
+#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
+#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
+#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
+#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
+#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
+#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
+#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
+#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
+#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
+#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
+#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
+#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
+#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
+#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
+#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
+#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
+#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
+
+/* USART.BAUDCTRLB  bit masks and bit positions */
+/* USART_BSEL  is already defined. */
+#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
+#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
+#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
+#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
+#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
+#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
+#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
+#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
+#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
+#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
+
+/* USB - USB */
+/* USB_EP.STATUS  bit masks and bit positions */
+#define USB_EP_TOGGLE_bm  0x01  /* Data Toggle bit mask. */
+#define USB_EP_TOGGLE_bp  0  /* Data Toggle bit position. */
+#define USB_EP_BUSNACK0_bm  0x02  /* Data Buffer 0 Not Acknowledge bit mask. */
+#define USB_EP_BUSNACK0_bp  1  /* Data Buffer 0 Not Acknowledge bit position. */
+#define USB_EP_BUSNACK1_bm  0x04  /* Data Buffer 1 Not Acknowledge bit mask. */
+#define USB_EP_BUSNACK1_bp  2  /* Data Buffer 1 Not Acknowledge bit position. */
+#define USB_EP_BANK_bm  0x08  /* Bank Select bit mask. */
+#define USB_EP_BANK_bp  3  /* Bank Select bit position. */
+#define USB_EP_TRNCOMPL1_bm  0x10  /* Transaction Complete 1 Flag bit mask. */
+#define USB_EP_TRNCOMPL1_bp  4  /* Transaction Complete 1 Flag bit position. */
+#define USB_EP_SETUP_bm  0x10  /* SETUP Transaction Complete Flag bit mask. */
+#define USB_EP_SETUP_bp  4  /* SETUP Transaction Complete Flag bit position. */
+#define USB_EP_TRNCOMPL0_bm  0x20  /* Transaction Complete 0 Flag bit mask. */
+#define USB_EP_TRNCOMPL0_bp  5  /* Transaction Complete 0 Flag bit position. */
+#define USB_EP_UNF_bm  0x40  /* Underflow Enpoint FLag bit mask. */
+#define USB_EP_UNF_bp  6  /* Underflow Enpoint FLag bit position. */
+#define USB_EP_OVF_bm  0x40  /* Overflow Enpoint Flag for Output Endpoints bit mask. */
+#define USB_EP_OVF_bp  6  /* Overflow Enpoint Flag for Output Endpoints bit position. */
+#define USB_EP_STALLF_bm  0x80  /* Endpoint Stall Flag bit mask. */
+#define USB_EP_STALLF_bp  7  /* Endpoint Stall Flag bit position. */
+#define USB_EP_CRC_bm  0x80  /* CRC Error Flag bit mask. */
+#define USB_EP_CRC_bp  7  /* CRC Error Flag bit position. */
+
+/* USB_EP.CTRL  bit masks and bit positions */
+#define USB_EP_STALL_bm  0x04  /* Data Stall bit mask. */
+#define USB_EP_STALL_bp  2  /* Data Stall bit position. */
+#define USB_EP_BUFSIZE_gm  0x07  /* Data Buffer Size group mask. */
+#define USB_EP_BUFSIZE_gp  0  /* Data Buffer Size group position. */
+#define USB_EP_BUFSIZE0_bm  (1<<0)  /* Data Buffer Size bit 0 mask. */
+#define USB_EP_BUFSIZE0_bp  0  /* Data Buffer Size bit 0 position. */
+#define USB_EP_BUFSIZE1_bm  (1<<1)  /* Data Buffer Size bit 1 mask. */
+#define USB_EP_BUFSIZE1_bp  1  /* Data Buffer Size bit 1 position. */
+#define USB_EP_BUFSIZE2_bm  (1<<2)  /* Data Buffer Size bit 2 mask. */
+#define USB_EP_BUFSIZE2_bp  2  /* Data Buffer Size bit 2 position. */
+#define USB_EP_INTDSBL_bm  0x08  /* Interrupt Disable bit mask. */
+#define USB_EP_INTDSBL_bp  3  /* Interrupt Disable bit position. */
+#define USB_EP_PINGPONG_bm  0x10  /* Ping-Pong Enable bit mask. */
+#define USB_EP_PINGPONG_bp  4  /* Ping-Pong Enable bit position. */
+#define USB_EP_MULTIPKT_bm  0x20  /* Multi Packet Transfer Enable bit mask. */
+#define USB_EP_MULTIPKT_bp  5  /* Multi Packet Transfer Enable bit position. */
+#define USB_EP_TYPE_gm  0xC0  /* Endpoint Type group mask. */
+#define USB_EP_TYPE_gp  6  /* Endpoint Type group position. */
+#define USB_EP_TYPE0_bm  (1<<6)  /* Endpoint Type bit 0 mask. */
+#define USB_EP_TYPE0_bp  6  /* Endpoint Type bit 0 position. */
+#define USB_EP_TYPE1_bm  (1<<7)  /* Endpoint Type bit 1 mask. */
+#define USB_EP_TYPE1_bp  7  /* Endpoint Type bit 1 position. */
+
+/* USB_EP.CNT  bit masks and bit positions */
+#define USB_EP_ZLP_bm  0x8000  /* Zero Length Packet bit mask. */
+#define USB_EP_ZLP_bp  15  /* Zero Length Packet bit position. */
+
+
+
+/* USB.CTRLA  bit masks and bit positions */
+#define USB_MAXEP_gm  0x0F  /* Maximum Endpoint Addresses group mask. */
+#define USB_MAXEP_gp  0  /* Maximum Endpoint Addresses group position. */
+#define USB_MAXEP0_bm  (1<<0)  /* Maximum Endpoint Addresses bit 0 mask. */
+#define USB_MAXEP0_bp  0  /* Maximum Endpoint Addresses bit 0 position. */
+#define USB_MAXEP1_bm  (1<<1)  /* Maximum Endpoint Addresses bit 1 mask. */
+#define USB_MAXEP1_bp  1  /* Maximum Endpoint Addresses bit 1 position. */
+#define USB_MAXEP2_bm  (1<<2)  /* Maximum Endpoint Addresses bit 2 mask. */
+#define USB_MAXEP2_bp  2  /* Maximum Endpoint Addresses bit 2 position. */
+#define USB_MAXEP3_bm  (1<<3)  /* Maximum Endpoint Addresses bit 3 mask. */
+#define USB_MAXEP3_bp  3  /* Maximum Endpoint Addresses bit 3 position. */
+#define USB_STFRNUM_bm  0x10  /* Store Frame Number Enable bit mask. */
+#define USB_STFRNUM_bp  4  /* Store Frame Number Enable bit position. */
+#define USB_FIFOEN_bm  0x20  /* USB FIFO Enable bit mask. */
+#define USB_FIFOEN_bp  5  /* USB FIFO Enable bit position. */
+#define USB_SPEED_bm  0x40  /* Speed Select bit mask. */
+#define USB_SPEED_bp  6  /* Speed Select bit position. */
+#define USB_ENABLE_bm  0x80  /* USB Enable bit mask. */
+#define USB_ENABLE_bp  7  /* USB Enable bit position. */
+
+/* USB.CTRLB  bit masks and bit positions */
+#define USB_ATTACH_bm  0x01  /* Attach bit mask. */
+#define USB_ATTACH_bp  0  /* Attach bit position. */
+#define USB_GNACK_bm  0x02  /* Global NACK bit mask. */
+#define USB_GNACK_bp  1  /* Global NACK bit position. */
+#define USB_RWAKEUP_bm  0x04  /* Remote Wake-up bit mask. */
+#define USB_RWAKEUP_bp  2  /* Remote Wake-up bit position. */
+#define USB_PULLRST_bm  0x10  /* Pull during Reset bit mask. */
+#define USB_PULLRST_bp  4  /* Pull during Reset bit position. */
+
+/* USB.STATUS  bit masks and bit positions */
+#define USB_BUSRST_bm  0x01  /* Bus Reset bit mask. */
+#define USB_BUSRST_bp  0  /* Bus Reset bit position. */
+#define USB_SUSPEND_bm  0x02  /* Bus Suspended bit mask. */
+#define USB_SUSPEND_bp  1  /* Bus Suspended bit position. */
+#define USB_RESUME_bm  0x04  /* Resume bit mask. */
+#define USB_RESUME_bp  2  /* Resume bit position. */
+#define USB_URESUME_bm  0x08  /* Upstream Resume bit mask. */
+#define USB_URESUME_bp  3  /* Upstream Resume bit position. */
+
+/* USB.ADDR  bit masks and bit positions */
+#define USB_ADDR_gm  0x7F  /* Device Address group mask. */
+#define USB_ADDR_gp  0  /* Device Address group position. */
+#define USB_ADDR0_bm  (1<<0)  /* Device Address bit 0 mask. */
+#define USB_ADDR0_bp  0  /* Device Address bit 0 position. */
+#define USB_ADDR1_bm  (1<<1)  /* Device Address bit 1 mask. */
+#define USB_ADDR1_bp  1  /* Device Address bit 1 position. */
+#define USB_ADDR2_bm  (1<<2)  /* Device Address bit 2 mask. */
+#define USB_ADDR2_bp  2  /* Device Address bit 2 position. */
+#define USB_ADDR3_bm  (1<<3)  /* Device Address bit 3 mask. */
+#define USB_ADDR3_bp  3  /* Device Address bit 3 position. */
+#define USB_ADDR4_bm  (1<<4)  /* Device Address bit 4 mask. */
+#define USB_ADDR4_bp  4  /* Device Address bit 4 position. */
+#define USB_ADDR5_bm  (1<<5)  /* Device Address bit 5 mask. */
+#define USB_ADDR5_bp  5  /* Device Address bit 5 position. */
+#define USB_ADDR6_bm  (1<<6)  /* Device Address bit 6 mask. */
+#define USB_ADDR6_bp  6  /* Device Address bit 6 position. */
+
+/* USB.FIFOWP  bit masks and bit positions */
+#define USB_FIFOWP_gm  0x1F  /* FIFO Write Pointer group mask. */
+#define USB_FIFOWP_gp  0  /* FIFO Write Pointer group position. */
+#define USB_FIFOWP0_bm  (1<<0)  /* FIFO Write Pointer bit 0 mask. */
+#define USB_FIFOWP0_bp  0  /* FIFO Write Pointer bit 0 position. */
+#define USB_FIFOWP1_bm  (1<<1)  /* FIFO Write Pointer bit 1 mask. */
+#define USB_FIFOWP1_bp  1  /* FIFO Write Pointer bit 1 position. */
+#define USB_FIFOWP2_bm  (1<<2)  /* FIFO Write Pointer bit 2 mask. */
+#define USB_FIFOWP2_bp  2  /* FIFO Write Pointer bit 2 position. */
+#define USB_FIFOWP3_bm  (1<<3)  /* FIFO Write Pointer bit 3 mask. */
+#define USB_FIFOWP3_bp  3  /* FIFO Write Pointer bit 3 position. */
+#define USB_FIFOWP4_bm  (1<<4)  /* FIFO Write Pointer bit 4 mask. */
+#define USB_FIFOWP4_bp  4  /* FIFO Write Pointer bit 4 position. */
+
+/* USB.FIFORP  bit masks and bit positions */
+#define USB_FIFORP_gm  0x1F  /* FIFO Read Pointer group mask. */
+#define USB_FIFORP_gp  0  /* FIFO Read Pointer group position. */
+#define USB_FIFORP0_bm  (1<<0)  /* FIFO Read Pointer bit 0 mask. */
+#define USB_FIFORP0_bp  0  /* FIFO Read Pointer bit 0 position. */
+#define USB_FIFORP1_bm  (1<<1)  /* FIFO Read Pointer bit 1 mask. */
+#define USB_FIFORP1_bp  1  /* FIFO Read Pointer bit 1 position. */
+#define USB_FIFORP2_bm  (1<<2)  /* FIFO Read Pointer bit 2 mask. */
+#define USB_FIFORP2_bp  2  /* FIFO Read Pointer bit 2 position. */
+#define USB_FIFORP3_bm  (1<<3)  /* FIFO Read Pointer bit 3 mask. */
+#define USB_FIFORP3_bp  3  /* FIFO Read Pointer bit 3 position. */
+#define USB_FIFORP4_bm  (1<<4)  /* FIFO Read Pointer bit 4 mask. */
+#define USB_FIFORP4_bp  4  /* FIFO Read Pointer bit 4 position. */
+
+
+/* USB.INTCTRLA  bit masks and bit positions */
+#define USB_INTLVL_gm  0x03  /* Interrupt Level group mask. */
+#define USB_INTLVL_gp  0  /* Interrupt Level group position. */
+#define USB_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
+#define USB_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
+#define USB_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
+#define USB_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
+#define USB_STALLIE_bm  0x10  /* STALL Interrupt Enable bit mask. */
+#define USB_STALLIE_bp  4  /* STALL Interrupt Enable bit position. */
+#define USB_BUSERRIE_bm  0x20  /* Bus Error Interrupt Enable bit mask. */
+#define USB_BUSERRIE_bp  5  /* Bus Error Interrupt Enable bit position. */
+#define USB_BUSEVIE_bm  0x40  /* Bus Event Interrupt Enable bit mask. */
+#define USB_BUSEVIE_bp  6  /* Bus Event Interrupt Enable bit position. */
+#define USB_SOFIE_bm  0x80  /* Start Of Frame Interrupt Enable bit mask. */
+#define USB_SOFIE_bp  7  /* Start Of Frame Interrupt Enable bit position. */
+
+/* USB.INTCTRLB  bit masks and bit positions */
+#define USB_SETUPIE_bm  0x01  /* SETUP Transaction Complete Interrupt Enable bit mask. */
+#define USB_SETUPIE_bp  0  /* SETUP Transaction Complete Interrupt Enable bit position. */
+#define USB_TRNIE_bm  0x02  /* Transaction Complete Interrupt Enable bit mask. */
+#define USB_TRNIE_bp  1  /* Transaction Complete Interrupt Enable bit position. */
+
+/* USB.INTFLAGSACLR  bit masks and bit positions */
+#define USB_STALLIF_bm  0x01  /* STALL Interrupt Flag bit mask. */
+#define USB_STALLIF_bp  0  /* STALL Interrupt Flag bit position. */
+#define USB_OVFIF_bm  0x02  /* Overflow Interrupt Flag bit mask. */
+#define USB_OVFIF_bp  1  /* Overflow Interrupt Flag bit position. */
+#define USB_UNFIF_bm  0x04  /* Underflow Interrupt Flag bit mask. */
+#define USB_UNFIF_bp  2  /* Underflow Interrupt Flag bit position. */
+#define USB_CRCIF_bm  0x08  /* Isochronous CRC Error Interrupt Flag bit mask. */
+#define USB_CRCIF_bp  3  /* Isochronous CRC Error Interrupt Flag bit position. */
+#define USB_RSTIF_bm  0x10  /* Reset Interrupt Flag bit mask. */
+#define USB_RSTIF_bp  4  /* Reset Interrupt Flag bit position. */
+#define USB_RESUMEIF_bm  0x20  /* Resume Interrupt Flag bit mask. */
+#define USB_RESUMEIF_bp  5  /* Resume Interrupt Flag bit position. */
+#define USB_SUSPENDIF_bm  0x40  /* Suspend Interrupt Flag bit mask. */
+#define USB_SUSPENDIF_bp  6  /* Suspend Interrupt Flag bit position. */
+#define USB_SOFIF_bm  0x80  /* Start Of Frame Interrupt Flag bit mask. */
+#define USB_SOFIF_bp  7  /* Start Of Frame Interrupt Flag bit position. */
+
+/* USB.INTFLAGSASET  bit masks and bit positions */
+/* USB_STALLIF  is already defined. */
+/* USB_OVFIF  is already defined. */
+/* USB_UNFIF  is already defined. */
+/* USB_CRCIF  is already defined. */
+/* USB_RSTIF  is already defined. */
+/* USB_RESUMEIF  is already defined. */
+/* USB_SUSPENDIF  is already defined. */
+/* USB_SOFIF  is already defined. */
+
+/* USB.INTFLAGSBCLR  bit masks and bit positions */
+#define USB_SETUPIF_bm  0x01  /* SETUP Transaction Complete Interrupt Flag bit mask. */
+#define USB_SETUPIF_bp  0  /* SETUP Transaction Complete Interrupt Flag bit position. */
+#define USB_TRNIF_bm  0x02  /* Transaction Complete Interrupt Flag bit mask. */
+#define USB_TRNIF_bp  1  /* Transaction Complete Interrupt Flag bit position. */
+
+/* USB.INTFLAGSBSET  bit masks and bit positions */
+/* USB_SETUPIF  is already defined. */
+/* USB_TRNIF  is already defined. */
+
+
+
+
+
+
+
+
+/* VPORT - Virtual Ports */
+/* VPORT.INTFLAGS  bit masks and bit positions */
+#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
+#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
+#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
+#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
+
+/* WDT - Watch-Dog Timer */
+/* WDT.CTRL  bit masks and bit positions */
+#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
+#define WDT_CEN_bp  0  /* Change Enable bit position. */
+#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
+#define WDT_ENABLE_bp  1  /* Enable bit position. */
+#define WDT_PER_gm  0x3C  /* Period group mask. */
+#define WDT_PER_gp  2  /* Period group position. */
+#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
+#define WDT_PER0_bp  2  /* Period bit 0 position. */
+#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
+#define WDT_PER1_bp  3  /* Period bit 1 position. */
+#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
+#define WDT_PER2_bp  4  /* Period bit 2 position. */
+#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
+#define WDT_PER3_bp  5  /* Period bit 3 position. */
+
+/* WDT.WINCTRL  bit masks and bit positions */
+#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
+#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
+#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
+#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
+#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
+#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
+#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
+#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
+#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
+#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
+#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
+#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
+#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
+#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
+
+/* WDT.STATUS  bit masks and bit positions */
+#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
+#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
+
+/* XOCD - On-Chip Debug System */
+/* OCD.OCDR0  bit masks and bit positions */
+#define OCD_OCDRD_gm  0xFF  /* OCDR Dirty group mask. */
+#define OCD_OCDRD_gp  0  /* OCDR Dirty group position. */
+#define OCD_OCDRD0_bm  (1<<0)  /* OCDR Dirty bit 0 mask. */
+#define OCD_OCDRD0_bp  0  /* OCDR Dirty bit 0 position. */
+#define OCD_OCDRD1_bm  (1<<1)  /* OCDR Dirty bit 1 mask. */
+#define OCD_OCDRD1_bp  1  /* OCDR Dirty bit 1 position. */
+#define OCD_OCDRD2_bm  (1<<2)  /* OCDR Dirty bit 2 mask. */
+#define OCD_OCDRD2_bp  2  /* OCDR Dirty bit 2 position. */
+#define OCD_OCDRD3_bm  (1<<3)  /* OCDR Dirty bit 3 mask. */
+#define OCD_OCDRD3_bp  3  /* OCDR Dirty bit 3 position. */
+#define OCD_OCDRD4_bm  (1<<4)  /* OCDR Dirty bit 4 mask. */
+#define OCD_OCDRD4_bp  4  /* OCDR Dirty bit 4 position. */
+#define OCD_OCDRD5_bm  (1<<5)  /* OCDR Dirty bit 5 mask. */
+#define OCD_OCDRD5_bp  5  /* OCDR Dirty bit 5 position. */
+#define OCD_OCDRD6_bm  (1<<6)  /* OCDR Dirty bit 6 mask. */
+#define OCD_OCDRD6_bp  6  /* OCDR Dirty bit 6 position. */
+#define OCD_OCDRD7_bm  (1<<7)  /* OCDR Dirty bit 7 mask. */
+#define OCD_OCDRD7_bp  7  /* OCDR Dirty bit 7 position. */
+
+/* OCD.OCDR1  bit masks and bit positions */
+/* OCD_OCDRD  is already defined. */
+
+
+
+// Generic Port Pins
+
+#define PIN0_bm 0x01
+#define PIN0_bp 0
+#define PIN1_bm 0x02
+#define PIN1_bp 1
+#define PIN2_bm 0x04
+#define PIN2_bp 2
+#define PIN3_bm 0x08
+#define PIN3_bp 3
+#define PIN4_bm 0x10
+#define PIN4_bp 4
+#define PIN5_bm 0x20
+#define PIN5_bp 5
+#define PIN6_bm 0x40
+#define PIN6_bp 6
+#define PIN7_bm 0x80
+#define PIN7_bp 7
+
+/* ========== Interrupt Vector Definitions ========== */
+/* Vector 0 is the reset vector */
+
+/* OSC interrupt vectors */
+#define OSC_OSCF_vect_num  1
+#define OSC_OSCF_vect      _VECTOR(1)  /* Oscillator Failure Interrupt (NMI) */
+
+/* PORTC interrupt vectors */
+#define PORTC_INT0_vect_num  2
+#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
+#define PORTC_INT1_vect_num  3
+#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
+
+/* PORTR interrupt vectors */
+#define PORTR_INT0_vect_num  4
+#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
+#define PORTR_INT1_vect_num  5
+#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
+
+/* DMA interrupt vectors */
+#define DMA_CH0_vect_num  6
+#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
+#define DMA_CH1_vect_num  7
+#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
+#define DMA_CH2_vect_num  8
+#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
+#define DMA_CH3_vect_num  9
+#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
+
+/* RTC interrupt vectors */
+#define RTC_OVF_vect_num  10
+#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
+#define RTC_COMP_vect_num  11
+#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
+
+/* TWIC interrupt vectors */
+#define TWIC_TWIS_vect_num  12
+#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
+#define TWIC_TWIM_vect_num  13
+#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_OVF_vect_num  14
+#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_LUNF_vect_num  14
+#define TCC2_LUNF_vect      _VECTOR(14)  /* Low Byte Underflow Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_ERR_vect_num  15
+#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_HUNF_vect_num  15
+#define TCC2_HUNF_vect      _VECTOR(15)  /* High Byte Underflow Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_CCA_vect_num  16
+#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_LCMPA_vect_num  16
+#define TCC2_LCMPA_vect      _VECTOR(16)  /* Low Byte Compare A Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_CCB_vect_num  17
+#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_LCMPB_vect_num  17
+#define TCC2_LCMPB_vect      _VECTOR(17)  /* Low Byte Compare B Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_CCC_vect_num  18
+#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_LCMPC_vect_num  18
+#define TCC2_LCMPC_vect      _VECTOR(18)  /* Low Byte Compare C Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_CCD_vect_num  19
+#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_LCMPD_vect_num  19
+#define TCC2_LCMPD_vect      _VECTOR(19)  /* Low Byte Compare D Interrupt */
+
+/* TCC1 interrupt vectors */
+#define TCC1_OVF_vect_num  20
+#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
+#define TCC1_ERR_vect_num  21
+#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
+#define TCC1_CCA_vect_num  22
+#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
+#define TCC1_CCB_vect_num  23
+#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
+
+/* SPIC interrupt vectors */
+#define SPIC_INT_vect_num  24
+#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
+
+/* USARTC0 interrupt vectors */
+#define USARTC0_RXC_vect_num  25
+#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
+#define USARTC0_DRE_vect_num  26
+#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
+#define USARTC0_TXC_vect_num  27
+#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
+
+/* USARTC1 interrupt vectors */
+#define USARTC1_RXC_vect_num  28
+#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
+#define USARTC1_DRE_vect_num  29
+#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
+#define USARTC1_TXC_vect_num  30
+#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
+
+/* AES interrupt vectors */
+#define AES_INT_vect_num  31
+#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
+
+/* NVM interrupt vectors */
+#define NVM_EE_vect_num  32
+#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
+#define NVM_SPM_vect_num  33
+#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
+
+/* PORTB interrupt vectors */
+#define PORTB_INT0_vect_num  34
+#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
+#define PORTB_INT1_vect_num  35
+#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
+
+/* ACB interrupt vectors */
+#define ACB_AC0_vect_num  36
+#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
+#define ACB_AC1_vect_num  37
+#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
+#define ACB_ACW_vect_num  38
+#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
+
+/* ADCB interrupt vectors */
+#define ADCB_CH0_vect_num  39
+#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
+#define ADCB_CH1_vect_num  40
+#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
+#define ADCB_CH2_vect_num  41
+#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
+#define ADCB_CH3_vect_num  42
+#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
+
+/* PORTE interrupt vectors */
+#define PORTE_INT0_vect_num  43
+#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
+#define PORTE_INT1_vect_num  44
+#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
+
+/* TWIE interrupt vectors */
+#define TWIE_TWIS_vect_num  45
+#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
+#define TWIE_TWIM_vect_num  46
+#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_OVF_vect_num  47
+#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_LUNF_vect_num  47
+#define TCE2_LUNF_vect      _VECTOR(47)  /* Low Byte Underflow Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_ERR_vect_num  48
+#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_HUNF_vect_num  48
+#define TCE2_HUNF_vect      _VECTOR(48)  /* High Byte Underflow Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_CCA_vect_num  49
+#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_LCMPA_vect_num  49
+#define TCE2_LCMPA_vect      _VECTOR(49)  /* Low Byte Compare A Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_CCB_vect_num  50
+#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_LCMPB_vect_num  50
+#define TCE2_LCMPB_vect      _VECTOR(50)  /* Low Byte Compare B Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_CCC_vect_num  51
+#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_LCMPC_vect_num  51
+#define TCE2_LCMPC_vect      _VECTOR(51)  /* Low Byte Compare C Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_CCD_vect_num  52
+#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_LCMPD_vect_num  52
+#define TCE2_LCMPD_vect      _VECTOR(52)  /* Low Byte Compare D Interrupt */
+
+/* TCE1 interrupt vectors */
+#define TCE1_OVF_vect_num  53
+#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
+#define TCE1_ERR_vect_num  54
+#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
+#define TCE1_CCA_vect_num  55
+#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
+#define TCE1_CCB_vect_num  56
+#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
+
+/* SPIE interrupt vectors */
+#define SPIE_INT_vect_num  57
+#define SPIE_INT_vect      _VECTOR(57)  /* SPI Interrupt */
+
+/* USARTE0 interrupt vectors */
+#define USARTE0_RXC_vect_num  58
+#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
+#define USARTE0_DRE_vect_num  59
+#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
+#define USARTE0_TXC_vect_num  60
+#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
+
+/* USARTE1 interrupt vectors */
+#define USARTE1_RXC_vect_num  61
+#define USARTE1_RXC_vect      _VECTOR(61)  /* Reception Complete Interrupt */
+#define USARTE1_DRE_vect_num  62
+#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
+#define USARTE1_TXC_vect_num  63
+#define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
+
+/* PORTD interrupt vectors */
+#define PORTD_INT0_vect_num  64
+#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
+#define PORTD_INT1_vect_num  65
+#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
+
+/* PORTA interrupt vectors */
+#define PORTA_INT0_vect_num  66
+#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
+#define PORTA_INT1_vect_num  67
+#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
+
+/* ACA interrupt vectors */
+#define ACA_AC0_vect_num  68
+#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
+#define ACA_AC1_vect_num  69
+#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
+#define ACA_ACW_vect_num  70
+#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
+
+/* ADCA interrupt vectors */
+#define ADCA_CH0_vect_num  71
+#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
+#define ADCA_CH1_vect_num  72
+#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
+#define ADCA_CH2_vect_num  73
+#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
+#define ADCA_CH3_vect_num  74
+#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
+
+/* TWID interrupt vectors */
+#define TWID_TWIS_vect_num  75
+#define TWID_TWIS_vect      _VECTOR(75)  /* TWI Slave Interrupt */
+#define TWID_TWIM_vect_num  76
+#define TWID_TWIM_vect      _VECTOR(76)  /* TWI Master Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_OVF_vect_num  77
+#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_LUNF_vect_num  77
+#define TCD2_LUNF_vect      _VECTOR(77)  /* Low Byte Underflow Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_ERR_vect_num  78
+#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_HUNF_vect_num  78
+#define TCD2_HUNF_vect      _VECTOR(78)  /* High Byte Underflow Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_CCA_vect_num  79
+#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_LCMPA_vect_num  79
+#define TCD2_LCMPA_vect      _VECTOR(79)  /* Low Byte Compare A Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_CCB_vect_num  80
+#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_LCMPB_vect_num  80
+#define TCD2_LCMPB_vect      _VECTOR(80)  /* Low Byte Compare B Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_CCC_vect_num  81
+#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_LCMPC_vect_num  81
+#define TCD2_LCMPC_vect      _VECTOR(81)  /* Low Byte Compare C Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_CCD_vect_num  82
+#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_LCMPD_vect_num  82
+#define TCD2_LCMPD_vect      _VECTOR(82)  /* Low Byte Compare D Interrupt */
+
+/* TCD1 interrupt vectors */
+#define TCD1_OVF_vect_num  83
+#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
+#define TCD1_ERR_vect_num  84
+#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
+#define TCD1_CCA_vect_num  85
+#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
+#define TCD1_CCB_vect_num  86
+#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
+
+/* SPID interrupt vectors */
+#define SPID_INT_vect_num  87
+#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
+
+/* USARTD0 interrupt vectors */
+#define USARTD0_RXC_vect_num  88
+#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
+#define USARTD0_DRE_vect_num  89
+#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
+#define USARTD0_TXC_vect_num  90
+#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
+
+/* USARTD1 interrupt vectors */
+#define USARTD1_RXC_vect_num  91
+#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
+#define USARTD1_DRE_vect_num  92
+#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
+#define USARTD1_TXC_vect_num  93
+#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
+
+/* PORTQ interrupt vectors */
+#define PORTQ_INT0_vect_num  94
+#define PORTQ_INT0_vect      _VECTOR(94)  /* External Interrupt 0 */
+#define PORTQ_INT1_vect_num  95
+#define PORTQ_INT1_vect      _VECTOR(95)  /* External Interrupt 1 */
+
+/* PORTH interrupt vectors */
+#define PORTH_INT0_vect_num  96
+#define PORTH_INT0_vect      _VECTOR(96)  /* External Interrupt 0 */
+#define PORTH_INT1_vect_num  97
+#define PORTH_INT1_vect      _VECTOR(97)  /* External Interrupt 1 */
+
+/* PORTJ interrupt vectors */
+#define PORTJ_INT0_vect_num  98
+#define PORTJ_INT0_vect      _VECTOR(98)  /* External Interrupt 0 */
+#define PORTJ_INT1_vect_num  99
+#define PORTJ_INT1_vect      _VECTOR(99)  /* External Interrupt 1 */
+
+/* PORTK interrupt vectors */
+#define PORTK_INT0_vect_num  100
+#define PORTK_INT0_vect      _VECTOR(100)  /* External Interrupt 0 */
+#define PORTK_INT1_vect_num  101
+#define PORTK_INT1_vect      _VECTOR(101)  /* External Interrupt 1 */
+
+/* PORTF interrupt vectors */
+#define PORTF_INT0_vect_num  104
+#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
+#define PORTF_INT1_vect_num  105
+#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
+
+/* TWIF interrupt vectors */
+#define TWIF_TWIS_vect_num  106
+#define TWIF_TWIS_vect      _VECTOR(106)  /* TWI Slave Interrupt */
+#define TWIF_TWIM_vect_num  107
+#define TWIF_TWIM_vect      _VECTOR(107)  /* TWI Master Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_OVF_vect_num  108
+#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_LUNF_vect_num  108
+#define TCF2_LUNF_vect      _VECTOR(108)  /* Low Byte Underflow Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_ERR_vect_num  109
+#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_HUNF_vect_num  109
+#define TCF2_HUNF_vect      _VECTOR(109)  /* High Byte Underflow Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_CCA_vect_num  110
+#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_LCMPA_vect_num  110
+#define TCF2_LCMPA_vect      _VECTOR(110)  /* Low Byte Compare A Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_CCB_vect_num  111
+#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_LCMPB_vect_num  111
+#define TCF2_LCMPB_vect      _VECTOR(111)  /* Low Byte Compare B Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_CCC_vect_num  112
+#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_LCMPC_vect_num  112
+#define TCF2_LCMPC_vect      _VECTOR(112)  /* Low Byte Compare C Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_CCD_vect_num  113
+#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_LCMPD_vect_num  113
+#define TCF2_LCMPD_vect      _VECTOR(113)  /* Low Byte Compare D Interrupt */
+
+/* TCF1 interrupt vectors */
+#define TCF1_OVF_vect_num  114
+#define TCF1_OVF_vect      _VECTOR(114)  /* Overflow Interrupt */
+#define TCF1_ERR_vect_num  115
+#define TCF1_ERR_vect      _VECTOR(115)  /* Error Interrupt */
+#define TCF1_CCA_vect_num  116
+#define TCF1_CCA_vect      _VECTOR(116)  /* Compare or Capture A Interrupt */
+#define TCF1_CCB_vect_num  117
+#define TCF1_CCB_vect      _VECTOR(117)  /* Compare or Capture B Interrupt */
+
+/* SPIF interrupt vectors */
+#define SPIF_INT_vect_num  118
+#define SPIF_INT_vect      _VECTOR(118)  /* SPI Interrupt */
+
+/* USARTF0 interrupt vectors */
+#define USARTF0_RXC_vect_num  119
+#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
+#define USARTF0_DRE_vect_num  120
+#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
+#define USARTF0_TXC_vect_num  121
+#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
+
+/* USARTF1 interrupt vectors */
+#define USARTF1_RXC_vect_num  122
+#define USARTF1_RXC_vect      _VECTOR(122)  /* Reception Complete Interrupt */
+#define USARTF1_DRE_vect_num  123
+#define USARTF1_DRE_vect      _VECTOR(123)  /* Data Register Empty Interrupt */
+#define USARTF1_TXC_vect_num  124
+#define USARTF1_TXC_vect      _VECTOR(124)  /* Transmission Complete Interrupt */
+
+/* USB interrupt vectors */
+#define USB_BUSEVENT_vect_num  125
+#define USB_BUSEVENT_vect      _VECTOR(125)  /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
+#define USB_TRNCOMPL_vect_num  126
+#define USB_TRNCOMPL_vect      _VECTOR(126)  /* Transaction complete interrupt */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
+
+
+/* ========== Constants ========== */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define PROGMEM_START     (0x0000)
+#  define PROGMEM_SIZE      (139264)
+#else
+#  define PROGMEM_START     (0x0000U)
+#  define PROGMEM_SIZE      (139264U)
+#endif
+#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define APP_SECTION_START     (0x0000)
+#  define APP_SECTION_SIZE      (131072)
+#  define APP_SECTION_PAGE_SIZE (512)
+#else
+#  define APP_SECTION_START     (0x0000U)
+#  define APP_SECTION_SIZE      (131072U)
+#  define APP_SECTION_PAGE_SIZE (512U)
+#endif
+#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define APPTABLE_SECTION_START     (0x1E000)
+#  define APPTABLE_SECTION_SIZE      (8192)
+#  define APPTABLE_SECTION_PAGE_SIZE (512)
+#else
+#  define APPTABLE_SECTION_START     (0x1E000U)
+#  define APPTABLE_SECTION_SIZE      (8192U)
+#  define APPTABLE_SECTION_PAGE_SIZE (512U)
+#endif
+#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define BOOT_SECTION_START     (0x20000)
+#  define BOOT_SECTION_SIZE      (8192)
+#  define BOOT_SECTION_PAGE_SIZE (512)
+#else
+#  define BOOT_SECTION_START     (0x20000U)
+#  define BOOT_SECTION_SIZE      (8192U)
+#  define BOOT_SECTION_PAGE_SIZE (512U)
+#endif
+#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define DATAMEM_START     (0x0000)
+#  define DATAMEM_SIZE      (16777216)
+#else
+#  define DATAMEM_START     (0x0000U)
+#  define DATAMEM_SIZE      (16777216U)
+#endif
+#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define IO_START     (0x0000)
+#  define IO_SIZE      (4096)
+#  define IO_PAGE_SIZE (0)
+#else
+#  define IO_START     (0x0000U)
+#  define IO_SIZE      (4096U)
+#  define IO_PAGE_SIZE (0U)
+#endif
+#define IO_END       (IO_START + IO_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define MAPPED_EEPROM_START     (0x1000)
+#  define MAPPED_EEPROM_SIZE      (2048)
+#  define MAPPED_EEPROM_PAGE_SIZE (0)
+#else
+#  define MAPPED_EEPROM_START     (0x1000U)
+#  define MAPPED_EEPROM_SIZE      (2048U)
+#  define MAPPED_EEPROM_PAGE_SIZE (0U)
+#endif
+#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define INTERNAL_SRAM_START     (0x2000)
+#  define INTERNAL_SRAM_SIZE      (8192)
+#  define INTERNAL_SRAM_PAGE_SIZE (0)
+#else
+#  define INTERNAL_SRAM_START     (0x2000U)
+#  define INTERNAL_SRAM_SIZE      (8192U)
+#  define INTERNAL_SRAM_PAGE_SIZE (0U)
+#endif
+#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define EXTERNAL_SRAM_START     (0x4000)
+#  define EXTERNAL_SRAM_SIZE      (16760831)
+#  define EXTERNAL_SRAM_PAGE_SIZE (0)
+#else
+#  define EXTERNAL_SRAM_START     (0x4000U)
+#  define EXTERNAL_SRAM_SIZE      (16760831U)
+#  define EXTERNAL_SRAM_PAGE_SIZE (0U)
+#endif
+#define EXTERNAL_SRAM_END       (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define EEPROM_START     (0x0000)
+#  define EEPROM_SIZE      (2048)
+#  define EEPROM_PAGE_SIZE (32)
+#else
+#  define EEPROM_START     (0x0000U)
+#  define EEPROM_SIZE      (2048U)
+#  define EEPROM_PAGE_SIZE (32U)
+#endif
+#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SIGNATURES_START     (0x0000)
+#  define SIGNATURES_SIZE      (3)
+#  define SIGNATURES_PAGE_SIZE (0)
+#else
+#  define SIGNATURES_START     (0x0000U)
+#  define SIGNATURES_SIZE      (3U)
+#  define SIGNATURES_PAGE_SIZE (0U)
+#endif
+#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define FUSES_START     (0x0000)
+#  define FUSES_SIZE      (6)
+#  define FUSES_PAGE_SIZE (0)
+#else
+#  define FUSES_START     (0x0000U)
+#  define FUSES_SIZE      (6U)
+#  define FUSES_PAGE_SIZE (0U)
+#endif
+#define FUSES_END       (FUSES_START + FUSES_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define LOCKBITS_START     (0x0000)
+#  define LOCKBITS_SIZE      (1)
+#  define LOCKBITS_PAGE_SIZE (0)
+#else
+#  define LOCKBITS_START     (0x0000U)
+#  define LOCKBITS_SIZE      (1U)
+#  define LOCKBITS_PAGE_SIZE (0U)
+#endif
+#define LOCKBITS_END       (LOCKBITS_START + LOCKBITS_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define USER_SIGNATURES_START     (0x0000)
+#  define USER_SIGNATURES_SIZE      (512)
+#  define USER_SIGNATURES_PAGE_SIZE (512)
+#else
+#  define USER_SIGNATURES_START     (0x0000U)
+#  define USER_SIGNATURES_SIZE      (512U)
+#  define USER_SIGNATURES_PAGE_SIZE (512U)
+#endif
+#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define PROD_SIGNATURES_START     (0x0000)
+#  define PROD_SIGNATURES_SIZE      (64)
+#  define PROD_SIGNATURES_PAGE_SIZE (512)
+#else
+#  define PROD_SIGNATURES_START     (0x0000U)
+#  define PROD_SIGNATURES_SIZE      (64U)
+#  define PROD_SIGNATURES_PAGE_SIZE (512U)
+#endif
+#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
+
+#define FLASHSTART   PROGMEM_START
+#define FLASHEND     PROGMEM_END
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 512
+#else
+#  define SPM_PAGESIZE 512U
+#endif
+#define RAMSTART     INTERNAL_SRAM_START
+#define RAMSIZE      INTERNAL_SRAM_SIZE
+#define RAMEND       INTERNAL_SRAM_END
+#define XRAMSTART    EXTERNAL_SRAM_START
+#define XRAMSIZE     EXTERNAL_SRAM_SIZE
+#define XRAMEND      EXTERNAL_SRAM_END
+#define E2END        EEPROM_END
+#define E2PAGESIZE   EEPROM_PAGE_SIZE
+
+
+/* ========== Fuses ========== */
+#define FUSE_MEMORY_SIZE 6
+
+/* Fuse Byte 0 (FUSEBYTE0) */
+#define FUSE_JTAGUID0  (unsigned char)~_BV(0)  /* JTAG User ID Bit 0 */
+#define FUSE_JTAGUID1  (unsigned char)~_BV(1)  /* JTAG User ID Bit 1 */
+#define FUSE_JTAGUID2  (unsigned char)~_BV(2)  /* JTAG User ID Bit 2 */
+#define FUSE_JTAGUID3  (unsigned char)~_BV(3)  /* JTAG User ID Bit 3 */
+#define FUSE_JTAGUID4  (unsigned char)~_BV(4)  /* JTAG User ID Bit 4 */
+#define FUSE_JTAGUID5  (unsigned char)~_BV(5)  /* JTAG User ID Bit 5 */
+#define FUSE_JTAGUID6  (unsigned char)~_BV(6)  /* JTAG User ID Bit 6 */
+#define FUSE_JTAGUID7  (unsigned char)~_BV(7)  /* JTAG User ID Bit 7 */
+#define FUSE0_DEFAULT  (0xff)
+#define FUSE_FUSEBYTE0_DEFAULT  (0xff)
+
+/* Fuse Byte 1 (FUSEBYTE1) */
+#define FUSE_WDPER0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDPER1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDPER2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDPER3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWPER0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWPER1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWPER2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWPER3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE1_DEFAULT  (0x0)
+#define FUSE_FUSEBYTE1_DEFAULT  (0x0)
+
+/* Fuse Byte 2 (FUSEBYTE2) */
+#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_TOSCSEL  (unsigned char)~_BV(5)  /* Timer Oscillator pin location */
+#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
+#define FUSE2_DEFAULT  (0xff)
+#define FUSE_FUSEBYTE2_DEFAULT  (0xff)
+
+/* Fuse Byte 3 Reserved */
+
+/* Fuse Byte 4 (FUSEBYTE4) */
+#define FUSE_JTAGEN  (unsigned char)~_BV(0)  /* JTAG Interface Enable */
+#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
+#define FUSE_STARTUPTIME0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
+#define FUSE_STARTUPTIME1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
+#define FUSE_RSTDISBL  (unsigned char)~_BV(4)  /* External Reset Disable */
+#define FUSE4_DEFAULT  (0xff)
+#define FUSE_FUSEBYTE4_DEFAULT  (0xff)
+
+/* Fuse Byte 5 (FUSEBYTE5) */
+#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brownout Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brownout Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brownout Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
+#define FUSE5_DEFAULT  (0xff)
+#define FUSE_FUSEBYTE5_DEFAULT  (0xff)
+
+/* ========== Lock Bits ========== */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_BITS_EXIST
+#define __BOOT_LOCK_BOOT_BITS_EXIST
+
+/* ========== Signature ========== */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x97
+#define SIGNATURE_2 0x4C
+
+/* ========== Power Reduction Condition Definitions ========== */
+
+/* PR.PRGEN */
+#define __AVR_HAVE_PRGEN	(PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm)
+#define __AVR_HAVE_PRGEN_USB
+#define __AVR_HAVE_PRGEN_AES
+#define __AVR_HAVE_PRGEN_EBI
+#define __AVR_HAVE_PRGEN_RTC
+#define __AVR_HAVE_PRGEN_EVSYS
+#define __AVR_HAVE_PRGEN_DMA
+
+/* PR.PRPA */
+#define __AVR_HAVE_PRPA	(PR_DAC_bm|PR_ADC_bm|PR_AC_bm)
+#define __AVR_HAVE_PRPA_DAC
+#define __AVR_HAVE_PRPA_ADC
+#define __AVR_HAVE_PRPA_AC
+
+/* PR.PRPB */
+#define __AVR_HAVE_PRPB	(PR_DAC_bm|PR_ADC_bm|PR_AC_bm)
+#define __AVR_HAVE_PRPB_DAC
+#define __AVR_HAVE_PRPB_ADC
+#define __AVR_HAVE_PRPB_AC
+
+/* PR.PRPC */
+#define __AVR_HAVE_PRPC	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
+#define __AVR_HAVE_PRPC_TWI
+#define __AVR_HAVE_PRPC_USART1
+#define __AVR_HAVE_PRPC_USART0
+#define __AVR_HAVE_PRPC_SPI
+#define __AVR_HAVE_PRPC_HIRES
+#define __AVR_HAVE_PRPC_TC1
+#define __AVR_HAVE_PRPC_TC0
+
+/* PR.PRPD */
+#define __AVR_HAVE_PRPD	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
+#define __AVR_HAVE_PRPD_TWI
+#define __AVR_HAVE_PRPD_USART1
+#define __AVR_HAVE_PRPD_USART0
+#define __AVR_HAVE_PRPD_SPI
+#define __AVR_HAVE_PRPD_HIRES
+#define __AVR_HAVE_PRPD_TC1
+#define __AVR_HAVE_PRPD_TC0
+
+/* PR.PRPE */
+#define __AVR_HAVE_PRPE	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
+#define __AVR_HAVE_PRPE_TWI
+#define __AVR_HAVE_PRPE_USART1
+#define __AVR_HAVE_PRPE_USART0
+#define __AVR_HAVE_PRPE_SPI
+#define __AVR_HAVE_PRPE_HIRES
+#define __AVR_HAVE_PRPE_TC1
+#define __AVR_HAVE_PRPE_TC0
+
+/* PR.PRPF */
+#define __AVR_HAVE_PRPF	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
+#define __AVR_HAVE_PRPF_TWI
+#define __AVR_HAVE_PRPF_USART1
+#define __AVR_HAVE_PRPF_USART0
+#define __AVR_HAVE_PRPF_SPI
+#define __AVR_HAVE_PRPF_HIRES
+#define __AVR_HAVE_PRPF_TC1
+#define __AVR_HAVE_PRPF_TC0
+
+
+#endif /* #ifdef _AVR_ATXMEGA128A1U_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iox128a3.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iox128a3.h
@@ -28,7 +28,7 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id$ */
+/* $Id: iox128a3.h 2200 2010-12-14 04:24:24Z arcanum $ */
 
 /* avr/iox128a3.h - definitions for ATxmega128A3 */
 
@@ -42,7 +42,7 @@
 #  define _AVR_IOXXX_H_ "iox128a3.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega128A3_H_
@@ -971,8 +971,8 @@
 typedef enum NVM_CMD_enum
 {
     NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
     NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
+    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
     NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
     NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
     NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
@@ -985,17 +985,25 @@
     NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
     NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
     NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
+    NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0),  /* Erase Flash Page */
     NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
     NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
+    NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0),  /* Write Flash Page */
+    NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0),  /* Erase-and-write Flash Page */
     NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
     NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
     NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
     NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
     NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
     NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
+    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Application section CRC */
+    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /*  Boot Section CRC */
+    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Flash Range CRC */
+    NVM_CMD_CHIP_ERASE_gc = (0x40<<0),  /* Erase Chip */
+    NVM_CMD_READ_NVM_gc = (0x43<<0),  /* Read NVM */
+    NVM_CMD_WRITE_FUSE_gc = (0x4C<<0),  /* Write Fuse byte */
+    NVM_CMD_ERASE_BOOT_gc = (0x68<<0),  /* Erase Boot Section */
+    NVM_CMD_FLASH_CRC_gc = (0x78<<0),  /* Flash CRC */
 } NVM_CMD_t;
 
 /* SPM ready interrupt level */
@@ -1284,16 +1292,34 @@
 /* Negative input multiplexer selection */
 typedef enum ADC_CH_MUXNEG_enum
 {
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
+    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN4_gc = (0x00<<0),  /* Input pin 4 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN5_gc = (0x01<<0),  /* Input pin 5 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN6_gc = (0x02<<0),  /* Input pin 6 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN7_gc = (0x03<<0),  /* Input pin 7 (Input Mode = 3) */
 } ADC_CH_MUXNEG_t;
 
+/* Negative input multiplexer selection when gain on 4 MSB pins */
+typedef enum ADC_CH_MUXNEGH_enum
+{
+    ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0),  /* Input pin 4 */
+    ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0),  /* Input pin 5 */
+    ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0),  /* Input pin 6 */
+    ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0),  /* Input pin 7 */
+} ADC_CH_MUXNEGH_t;
+
+/* Negative input multiplexer selection when gain on 4 LSB pins */
+typedef enum ADC_CH_MUXNEGL_enum
+{
+    ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0),  /* Input pin 0 */
+    ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0),  /* Input pin 1 */
+    ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0),  /* Input pin 2 */
+    ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0),  /* Input pin 3 */
+} ADC_CH_MUXNEGL_t;
+
 /* Input mode */
 typedef enum ADC_CH_INPUTMODE_enum
 {
@@ -4482,7 +4508,7 @@
 
 /* NVM - Non Volatile Memory Controller */
 /* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
+#define NVM_CMD_gm  0x7F  /* Command group mask. */
 #define NVM_CMD_gp  0  /* Command group position. */
 #define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
 #define NVM_CMD0_bp  0  /* Command bit 0 position. */
@@ -4498,8 +4524,6 @@
 #define NVM_CMD5_bp  5  /* Command bit 5 position. */
 #define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
 #define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
 
 
 /* NVM.CTRLA  bit masks and bit positions */
@@ -6473,21 +6497,21 @@
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iox128a3u.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iox128a3u.h
@@ -1,7700 +1,7746 @@
-/*****************************************************************************
- *
- * Copyright (C) 2014 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-/* $Id$ */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox128a3u.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#ifndef _AVR_ATXMEGA128A3U_H_INCLUDED
-#define _AVR_ATXMEGA128A3U_H_INCLUDED
-
-/* Ungrouped common registers */
-#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-/* Deprecated */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-    __extension__ union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-VPORT - Virtual Ports
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/*
---------------------------------------------------------------------------
-CPU - CPU
---------------------------------------------------------------------------
-*/
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-    register8_t USBCTRL;  /* USB Control Register */
-} CLK_t;
-
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2 MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32 MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32.768 kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1.024 kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1.024 kHz from internal 32.768 kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC32_gc = (0x06<<1),  /* 32.768 kHz from internal 32.768 kHz RC oscillator */
-    CLK_RTCSRC_EXTCLK_gc = (0x07<<1),  /* External Clock from TOSC1 */
-} CLK_RTCSRC_t;
-
-/* USB Prescaler Division Factor */
-typedef enum CLK_USBPSDIV_enum
-{
-    CLK_USBPSDIV_1_gc = (0x00<<3),  /* Divide by 1 */
-    CLK_USBPSDIV_2_gc = (0x01<<3),  /* Divide by 2 */
-    CLK_USBPSDIV_4_gc = (0x02<<3),  /* Divide by 4 */
-    CLK_USBPSDIV_8_gc = (0x03<<3),  /* Divide by 8 */
-    CLK_USBPSDIV_16_gc = (0x04<<3),  /* Divide by 16 */
-    CLK_USBPSDIV_32_gc = (0x05<<3),  /* Divide by 32 */
-} CLK_USBPSDIV_t;
-
-/* USB Clock Source */
-typedef enum CLK_USBSRC_enum
-{
-    CLK_USBSRC_PLL_gc = (0x00<<1),  /* PLL */
-    CLK_USBSRC_RC32M_gc = (0x01<<1),  /* Internal 32 MHz RC Oscillator */
-} CLK_USBSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32.768 kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control Register */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32.768 kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16 MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16 MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16 MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2 MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32 MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-/* 2 MHz DFLL Calibration Reference */
-typedef enum OSC_RC2MCREF_enum
-{
-    OSC_RC2MCREF_RC32K_gc = (0x00<<0),  /* Internal 32.768 kHz RC Oscillator */
-    OSC_RC2MCREF_XOSC32K_gc = (0x01<<0),  /* External 32.768 kHz Crystal Oscillator */
-} OSC_RC2MCREF_t;
-
-/* 32 MHz DFLL Calibration Reference */
-typedef enum OSC_RC32MCREF_enum
-{
-    OSC_RC32MCREF_RC32K_gc = (0x00<<1),  /* Internal 32.768 kHz RC Oscillator */
-    OSC_RC32MCREF_XOSC32K_gc = (0x01<<1),  /* External 32.768 kHz Crystal Oscillator */
-    OSC_RC32MCREF_USBSOF_gc = (0x02<<1),  /* USB Start of Frame */
-} OSC_RC32MCREF_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t ANAINIT;  /* Analog Startup Delay */
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x03;
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-PORTCFG - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-    register8_t EBIOUT;  /* EBI Output register */
-    register8_t EVOUTSEL;  /* Event Output Select */
-} PORTCFG_t;
-
-/* Virtual Port Mapping */
-typedef enum PORTCFG_VP02MAP_enum
-{
-    PORTCFG_VP02MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP02MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP02MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP02MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP02MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP02MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP02MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP02MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP02MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP02MAP_t;
-
-/* Virtual Port Mapping */
-typedef enum PORTCFG_VP13MAP_enum
-{
-    PORTCFG_VP13MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP13MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP13MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP13MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP13MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP13MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP13MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP13MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP13MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP13MAP_t;
-
-/* System Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* System Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* System Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* System Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* System Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Peripheral Clock Output Select */
-typedef enum PORTCFG_CLKOUTSEL_enum
-{
-    PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2),  /* 1x Peripheral Clock Output to pin */
-    PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2),  /* 2x Peripheral Clock Output to pin */
-    PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2),  /* 4x Peripheral Clock Output to pin */
-} PORTCFG_CLKOUTSEL_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Clock and Event Output Port */
-typedef enum PORTCFG_CLKEVPIN_enum
-{
-    PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7),  /* Clock and Event Ouput on PIN 7 */
-    PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7),  /* Clock and Event Ouput on PIN 4 */
-} PORTCFG_CLKEVPIN_t;
-
-/* EBI Address Output Port */
-typedef enum PORTCFG_EBIADROUT_enum
-{
-    PORTCFG_EBIADROUT_PF_gc = (0x00<<2),  /* EBI port 3 address output on PORTF pins 0 to 7 */
-    PORTCFG_EBIADROUT_PE_gc = (0x01<<2),  /* EBI port 3 address output on PORTE pins 0 to 7 */
-    PORTCFG_EBIADROUT_PFH_gc = (0x02<<2),  /* EBI port 3 address output on PORTF pins 4 to 7 */
-    PORTCFG_EBIADROUT_PEH_gc = (0x03<<2),  /* EBI port 3 address output on PORTE pins 4 to 7 */
-} PORTCFG_EBIADROUT_t;
-
-/* EBI Chip Select Output Port */
-typedef enum PORTCFG_EBICSOUT_enum
-{
-    PORTCFG_EBICSOUT_PH_gc = (0x00<<0),  /* EBI chip select output to PORTH pin 4 to 7 */
-    PORTCFG_EBICSOUT_PL_gc = (0x01<<0),  /* EBI chip select output to PORTL pin 4 to 7 */
-    PORTCFG_EBICSOUT_PF_gc = (0x02<<0),  /* EBI chip select output to PORTF pin 4 to 7 */
-    PORTCFG_EBICSOUT_PE_gc = (0x03<<0),  /* EBI chip select output to PORTE pin 4 to 7 */
-} PORTCFG_EBICSOUT_t;
-
-/* Event Output Select */
-typedef enum PORTCFG_EVOUTSEL_enum
-{
-    PORTCFG_EVOUTSEL_0_gc = (0x00<<0),  /* Event Channel 0 output to pin */
-    PORTCFG_EVOUTSEL_1_gc = (0x01<<0),  /* Event Channel 1 output to pin */
-    PORTCFG_EVOUTSEL_2_gc = (0x02<<0),  /* Event Channel 2 output to pin */
-    PORTCFG_EVOUTSEL_3_gc = (0x03<<0),  /* Event Channel 3 output to pin */
-    PORTCFG_EVOUTSEL_4_gc = (0x04<<0),  /* Event Channel 4 output to pin */
-    PORTCFG_EVOUTSEL_5_gc = (0x05<<0),  /* Event Channel 5 output to pin */
-    PORTCFG_EVOUTSEL_6_gc = (0x06<<0),  /* Event Channel 6 output to pin */
-    PORTCFG_EVOUTSEL_7_gc = (0x07<<0),  /* Event Channel 7 output to pin */
-} PORTCFG_EVOUTSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-CRC - Cyclic Redundancy Checker
---------------------------------------------------------------------------
-*/
-
-/* Cyclic Redundancy Checker */
-typedef struct CRC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t DATAIN;  /* Data Input */
-    register8_t CHECKSUM0;  /* Checksum byte 0 */
-    register8_t CHECKSUM1;  /* Checksum byte 1 */
-    register8_t CHECKSUM2;  /* Checksum byte 2 */
-    register8_t CHECKSUM3;  /* Checksum byte 3 */
-} CRC_t;
-
-/* Reset */
-typedef enum CRC_RESET_enum
-{
-    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
-    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
-    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
-} CRC_RESET_t;
-
-/* Input Source */
-typedef enum CRC_SOURCE_enum
-{
-    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
-    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
-    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
-    CRC_SOURCE_DMAC0_gc = (0x04<<0),  /* DMAC Channel 0 */
-    CRC_SOURCE_DMAC1_gc = (0x05<<0),  /* DMAC Channel 1 */
-    CRC_SOURCE_DMAC2_gc = (0x06<<0),  /* DMAC Channel 2 */
-    CRC_SOURCE_DMAC3_gc = (0x07<<0),  /* DMAC Channel 3 */
-} CRC_SOURCE_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_USB_gc = (0x0A<<0),  /* USB Setup, SOF, CRC error and UNF/OVF */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0),  /* Erase Flash Page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0),  /* Write Flash Page */
-    NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0),  /* Erase-and-write Flash Page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /*  Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Flash Range CRC */
-    NVM_CMD_CHIP_ERASE_gc = (0x40<<0),  /* Erase Chip */
-    NVM_CMD_READ_NVM_gc = (0x43<<0),  /* Read NVM */
-    NVM_CMD_WRITE_FUSE_gc = (0x4C<<0),  /* Write Fuse byte */
-    NVM_CMD_ERASE_BOOT_gc = (0x68<<0),  /* Erase Boot Section */
-    NVM_CMD_FLASH_CRC_gc = (0x78<<0),  /* Flash CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-} NVM_LB_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t SCAN;  /* Input Channel Scan */
-    register8_t reserved_0x07;
-} ADC_CH_t;
-
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t reserved_0x05;
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary Register */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-    ADC_CH_MUXPOS_PIN8_gc = (0x08<<3),  /* Input pin 8 */
-    ADC_CH_MUXPOS_PIN9_gc = (0x09<<3),  /* Input pin 9 */
-    ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3),  /* Input pin 10 */
-    ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3),  /* Input pin 11 */
-    ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3),  /* Input pin 12 */
-    ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3),  /* Input pin 13 */
-    ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3),  /* Input pin 14 */
-    ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3),  /* Input pin 15 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x00<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x01<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x02<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x03<<0),  /* Input pin 7 */
-    ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0),  /* PAD Ground (Input Mode = 3) */
-    ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0),  /* Internal Groud (Input Mode = 3) */
-    ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0),  /* Internal Groud (Input Mode = 4) */
-    ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0),  /* PAD Ground (Input Mode = 4) */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Current Limitation Mode */
-typedef enum ADC_CURRLIMIT_enum
-{
-    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No limit */
-    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit, max. sampling rate 1.5MSPS */
-    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, max. sampling rate 1MSPS */
-    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit, max. sampling rate 0.5MSPS */
-} ADC_CURRLIMIT_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_INTVCC_gc = (0x01<<4),  /* Internal VCC / 1.6 */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-    ADC_REFSEL_INTVCC2_gc = (0x04<<4),  /* Internal VCC / 2 */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCSWEEP_gc = (0x06<<0),  /* The ADC is flushed and restarted for accurate timing */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t reserved_0x04;
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t CH0GAINCAL;  /* Gain Calibration */
-    register8_t CH0OFFSETCAL;  /* Offset Calibration */
-    register8_t CH1GAINCAL;  /* Gain Calibration */
-    register8_t CH1OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel 0 only) */
-    DAC_CHSEL_SINGLE1_gc = (0x01<<5),  /* Single channel operation (Channel 1 only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (Channel 0 and channel 1) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Analog Comparator 0 Control */
-    register8_t AC1CTRL;  /* Analog Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Analog Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Analog Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Counter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* SDA Hold Time */
-typedef enum TWI_SDAHOLD_enum
-{
-    TWI_SDAHOLD_OFF_gc = (0x00<<1),  /* SDA Hold Time off */
-    TWI_SDAHOLD_50NS_gc = (0x01<<1),  /* SDA Hold Time 50 ns */
-    TWI_SDAHOLD_300NS_gc = (0x02<<1),  /* SDA Hold Time 300 ns */
-    TWI_SDAHOLD_400NS_gc = (0x03<<1),  /* SDA Hold Time 400 ns */
-} TWI_SDAHOLD_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-USB - USB
---------------------------------------------------------------------------
-*/
-
-/* USB Endpoint */
-typedef struct USB_EP_struct
-{
-    register8_t STATUS;  /* Endpoint Status */
-    register8_t CTRL;  /* Endpoint Control */
-    _WORDREGISTER(CNT);  /* USB Endpoint Counter */
-    _WORDREGISTER(DATAPTR);  /* Data Pointer */
-    _WORDREGISTER(AUXDATA);  /* Auxiliary Data */
-} USB_EP_t;
-
-
-/* Universal Serial Bus */
-typedef struct USB_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t FIFOWP;  /* FIFO Write Pointer Register */
-    register8_t FIFORP;  /* FIFO Read Pointer Register */
-    _WORDREGISTER(EPPTR);  /* Endpoint Configuration Table Pointer */
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t INTFLAGSACLR;  /* Clear Interrupt Flag Register A */
-    register8_t INTFLAGSASET;  /* Set Interrupt Flag Register A */
-    register8_t INTFLAGSBCLR;  /* Clear Interrupt Flag Register B */
-    register8_t INTFLAGSBSET;  /* Set Interrupt Flag Register B */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t reserved_0x20;
-    register8_t reserved_0x21;
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t CAL0;  /* Calibration Byte 0 */
-    register8_t CAL1;  /* Calibration Byte 1 */
-} USB_t;
-
-
-/* USB Endpoint Table */
-typedef struct USB_EP_TABLE_struct
-{
-    USB_EP_t EP0OUT;  /* Endpoint 0 */
-    USB_EP_t EP0IN;  /* Endpoint 0 */
-    USB_EP_t EP1OUT;  /* Endpoint 1 */
-    USB_EP_t EP1IN;  /* Endpoint 1 */
-    USB_EP_t EP2OUT;  /* Endpoint 2 */
-    USB_EP_t EP2IN;  /* Endpoint 2 */
-    USB_EP_t EP3OUT;  /* Endpoint 3 */
-    USB_EP_t EP3IN;  /* Endpoint 3 */
-    USB_EP_t EP4OUT;  /* Endpoint 4 */
-    USB_EP_t EP4IN;  /* Endpoint 4 */
-    USB_EP_t EP5OUT;  /* Endpoint 5 */
-    USB_EP_t EP5IN;  /* Endpoint 5 */
-    USB_EP_t EP6OUT;  /* Endpoint 6 */
-    USB_EP_t EP6IN;  /* Endpoint 6 */
-    USB_EP_t EP7OUT;  /* Endpoint 7 */
-    USB_EP_t EP7IN;  /* Endpoint 7 */
-    USB_EP_t EP8OUT;  /* Endpoint 8 */
-    USB_EP_t EP8IN;  /* Endpoint 8 */
-    USB_EP_t EP9OUT;  /* Endpoint 9 */
-    USB_EP_t EP9IN;  /* Endpoint 9 */
-    USB_EP_t EP10OUT;  /* Endpoint 10 */
-    USB_EP_t EP10IN;  /* Endpoint 10 */
-    USB_EP_t EP11OUT;  /* Endpoint 11 */
-    USB_EP_t EP11IN;  /* Endpoint 11 */
-    USB_EP_t EP12OUT;  /* Endpoint 12 */
-    USB_EP_t EP12IN;  /* Endpoint 12 */
-    USB_EP_t EP13OUT;  /* Endpoint 13 */
-    USB_EP_t EP13IN;  /* Endpoint 13 */
-    USB_EP_t EP14OUT;  /* Endpoint 14 */
-    USB_EP_t EP14IN;  /* Endpoint 14 */
-    USB_EP_t EP15OUT;  /* Endpoint 15 */
-    USB_EP_t EP15IN;  /* Endpoint 15 */
-    register8_t reserved_0x100;
-    register8_t reserved_0x101;
-    register8_t reserved_0x102;
-    register8_t reserved_0x103;
-    register8_t reserved_0x104;
-    register8_t reserved_0x105;
-    register8_t reserved_0x106;
-    register8_t reserved_0x107;
-    register8_t reserved_0x108;
-    register8_t reserved_0x109;
-    register8_t reserved_0x10A;
-    register8_t reserved_0x10B;
-    register8_t reserved_0x10C;
-    register8_t reserved_0x10D;
-    register8_t reserved_0x10E;
-    register8_t reserved_0x10F;
-    register8_t FRAMENUML;  /* Frame Number Low Byte */
-    register8_t FRAMENUMH;  /* Frame Number High Byte */
-} USB_EP_TABLE_t;
-
-/* Interrupt level */
-typedef enum USB_INTLVL_enum
-{
-    USB_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    USB_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    USB_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    USB_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} USB_INTLVL_t;
-
-/* USB Endpoint Type */
-typedef enum USB_EP_TYPE_enum
-{
-    USB_EP_TYPE_DISABLE_gc = (0x00<<6),  /* Endpoint Disabled */
-    USB_EP_TYPE_CONTROL_gc = (0x01<<6),  /* Control */
-    USB_EP_TYPE_BULK_gc = (0x02<<6),  /* Bulk/Interrupt */
-    USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6),  /* Isochronous */
-} USB_EP_TYPE_t;
-
-/* USB Endpoint Buffersize */
-typedef enum USB_EP_BUFSIZE_enum
-{
-    USB_EP_BUFSIZE_8_gc = (0x00<<0),  /* 8 bytes buffer size */
-    USB_EP_BUFSIZE_16_gc = (0x01<<0),  /* 16 bytes buffer size */
-    USB_EP_BUFSIZE_32_gc = (0x02<<0),  /* 32 bytes buffer size */
-    USB_EP_BUFSIZE_64_gc = (0x03<<0),  /* 64 bytes buffer size */
-    USB_EP_BUFSIZE_128_gc = (0x04<<0),  /* 128 bytes buffer size */
-    USB_EP_BUFSIZE_256_gc = (0x05<<0),  /* 256 bytes buffer size */
-    USB_EP_BUFSIZE_512_gc = (0x06<<0),  /* 512 bytes buffer size */
-    USB_EP_BUFSIZE_1023_gc = (0x07<<0),  /* 1023 bytes buffer size */
-} USB_EP_BUFSIZE_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - I/O Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t REMAP;  /* I/O Port Pin Remap Register */
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SINGLESLOPE_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DSTOP_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DSBOTH_gc = (0x06<<0),  /* Dual Slope, Update on both TOP and BOTTOM */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on both TOP and BOTTOM */
-    TC_WGMODE_DSBOTTOM_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Byte Mode */
-typedef enum TC_BYTEM_enum
-{
-    TC_BYTEM_NORMAL_gc = (0x00<<0),  /* 16-bit mode */
-    TC_BYTEM_BYTEMODE_gc = (0x01<<0),  /* Timer/Counter operating in byte mode only */
-    TC_BYTEM_SPLITMODE_gc = (0x02<<0),  /* Timer/Counter split into two 8-bit Counters (TC2) */
-} TC_BYTEM_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-TC2 - 16-bit Timer/Counter type 2
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter type 2 */
-typedef struct TC2_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t reserved_0x03;
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t reserved_0x08;
-    register8_t CTRLF;  /* Control Register F */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t LCNT;  /* Low Byte Count */
-    register8_t HCNT;  /* High Byte Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    register8_t LPER;  /* Low Byte Period */
-    register8_t HPER;  /* High Byte Period */
-    register8_t LCMPA;  /* Low Byte Compare A */
-    register8_t HCMPA;  /* High Byte Compare A */
-    register8_t LCMPB;  /* Low Byte Compare B */
-    register8_t HCMPB;  /* High Byte Compare B */
-    register8_t LCMPC;  /* Low Byte Compare C */
-    register8_t HCMPC;  /* High Byte Compare C */
-    register8_t LCMPD;  /* Low Byte Compare D */
-    register8_t HCMPD;  /* High Byte Compare D */
-} TC2_t;
-
-/* Clock Selection */
-typedef enum TC2_CLKSEL_enum
-{
-    TC2_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC2_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC2_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC2_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC2_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC2_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC2_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC2_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC2_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC2_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC2_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC2_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC2_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC2_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC2_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC2_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC2_CLKSEL_t;
-
-/* Byte Mode */
-typedef enum TC2_BYTEM_enum
-{
-    TC2_BYTEM_NORMAL_gc = (0x00<<0),  /* 16-bit mode */
-    TC2_BYTEM_BYTEMODE_gc = (0x01<<0),  /* Timer/Counter operating in byte mode only (TC2) */
-    TC2_BYTEM_SPLITMODE_gc = (0x02<<0),  /* Timer/Counter split into two 8-bit Counters */
-} TC2_BYTEM_t;
-
-/* High Byte Underflow Interrupt Level */
-typedef enum TC2_HUNFINTLVL_enum
-{
-    TC2_HUNFINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC2_HUNFINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC2_HUNFINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC2_HUNFINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC2_HUNFINTLVL_t;
-
-/* Low Byte Underflow Interrupt Level */
-typedef enum TC2_LUNFINTLVL_enum
-{
-    TC2_LUNFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC2_LUNFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC2_LUNFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC2_LUNFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC2_LUNFINTLVL_t;
-
-/* Low Byte Compare D Interrupt Level */
-typedef enum TC2_LCMPDINTLVL_enum
-{
-    TC2_LCMPDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC2_LCMPDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC2_LCMPDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC2_LCMPDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC2_LCMPDINTLVL_t;
-
-/* Low Byte Compare C Interrupt Level */
-typedef enum TC2_LCMPCINTLVL_enum
-{
-    TC2_LCMPCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC2_LCMPCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC2_LCMPCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC2_LCMPCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC2_LCMPCINTLVL_t;
-
-/* Low Byte Compare B Interrupt Level */
-typedef enum TC2_LCMPBINTLVL_enum
-{
-    TC2_LCMPBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC2_LCMPBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC2_LCMPBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC2_LCMPBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC2_LCMPBINTLVL_t;
-
-/* Low Byte Compare A Interrupt Level */
-typedef enum TC2_LCMPAINTLVL_enum
-{
-    TC2_LCMPAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC2_LCMPAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC2_LCMPAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC2_LCMPAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC2_LCMPAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC2_CMD_enum
-{
-    TC2_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC2_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC2_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC2_CMD_t;
-
-/* Timer/Counter Command */
-typedef enum TC2_CMDEN_enum
-{
-    TC2_CMDEN_LOW_gc = (0x01<<0),  /* Low Byte Timer/Counter */
-    TC2_CMDEN_HIGH_gc = (0x02<<0),  /* High Byte Timer/Counter */
-    TC2_CMDEN_BOTH_gc = (0x03<<0),  /* Both Low Byte and High Byte Timer/Counters */
-} TC2_CMDEN_t;
-
-
-/*
---------------------------------------------------------------------------
-AWEX - Timer/Counter Advanced Waveform Extension
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t STATUSSET;  /* Status Set Register */
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-
-/*
---------------------------------------------------------------------------
-HIRES - Timer/Counter High-Resolution Extension
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRLA;  /* Control Register */
-} HIRES_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-FUSE - Fuses and Lockbits
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* JTAG User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* Timer Oscillator pin location */
-typedef enum TOSCSEL_enum
-{
-    TOSCSEL_ALTERNATE_gc = (0x00<<5),  /* TOSC1 / TOSC2 on separate pins */
-    TOSCSEL_XTAL_gc = (0x01<<5),  /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
-} TOSCSEL_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_SAMPLED_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINUOUS_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* BOD operation */
-typedef enum BODACT_enum
-{
-    BODACT_SAMPLED_gc = (0x01<<4),  /* BOD enabled in sampled mode */
-    BODACT_CONTINUOUS_gc = (0x02<<4),  /* BOD enabled continuously */
-    BODACT_DISABLED_gc = (0x03<<4),  /* BOD Disabled */
-} BODACT_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WDP_enum
-{
-    WDP_8CLK_gc = (0x00<<0),  /* 8 cycles (8ms @ 3.3V) */
-    WDP_16CLK_gc = (0x01<<0),  /* 16 cycles (16ms @ 3.3V) */
-    WDP_32CLK_gc = (0x02<<0),  /* 32 cycles (32ms @ 3.3V) */
-    WDP_64CLK_gc = (0x03<<0),  /* 64 cycles (64ms @ 3.3V) */
-    WDP_128CLK_gc = (0x04<<0),  /* 128 cycles (0.125s @ 3.3V) */
-    WDP_256CLK_gc = (0x05<<0),  /* 256 cycles (0.25s @ 3.3V) */
-    WDP_512CLK_gc = (0x06<<0),  /* 512 cycles (0.5s @ 3.3V) */
-    WDP_1KCLK_gc = (0x07<<0),  /* 1K cycles (1s @ 3.3V) */
-    WDP_2KCLK_gc = (0x08<<0),  /* 2K cycles (2s @ 3.3V) */
-    WDP_4KCLK_gc = (0x09<<0),  /* 4K cycles (4s @ 3.3V) */
-    WDP_8KCLK_gc = (0x0A<<0),  /* 8K cycles (8s @ 3.3V) */
-} WDP_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V8_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V0_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V2_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V4_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V6_gc = (0x02<<0),  /* 2.6 V */
-    BODLVL_2V8_gc = (0x01<<0),  /* 2.8 V */
-    BODLVL_3V0_gc = (0x00<<0),  /* 3.0 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-LOCKBIT - Fuses and Lockbits
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum FUSE_BLBB_enum
-{
-    FUSE_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-    FUSE_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    FUSE_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    FUSE_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-} FUSE_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum FUSE_BLBA_enum
-{
-    FUSE_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-    FUSE_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    FUSE_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    FUSE_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-} FUSE_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum FUSE_BLBAT_enum
-{
-    FUSE_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-    FUSE_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    FUSE_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    FUSE_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-} FUSE_BLBAT_t;
-
-/* Lock bits */
-typedef enum FUSE_LB_enum
-{
-    FUSE_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-    FUSE_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    FUSE_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-} FUSE_LB_t;
-
-
-/*
---------------------------------------------------------------------------
-SIGROW - Signature Row
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2 MHz Calibration Value B */
-    register8_t RCOSC2MA;  /* RCOSC 2 MHz Calibration Value A */
-    register8_t RCOSC32K;  /* RCOSC 32.768 kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32 MHz Calibration Value B */
-    register8_t RCOSC32MA;  /* RCOSC 32 MHz Calibration Value A */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t USBCAL0;  /* USB Calibration Byte 0 */
-    register8_t USBCAL1;  /* USB Calibration Byte 1 */
-    register8_t USBRCOSC;  /* USB RCOSC Calibration Value B */
-    register8_t USBRCOSCA;  /* USB RCOSC Calibration Value A */
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 1 */
-    register8_t DACA0OFFCAL;  /* DACA0 Calibration Byte 0 */
-    register8_t DACA0GAINCAL;  /* DACA0 Calibration Byte 1 */
-    register8_t DACB0OFFCAL;  /* DACB0 Calibration Byte 0 */
-    register8_t DACB0GAINCAL;  /* DACB0 Calibration Byte 1 */
-    register8_t DACA1OFFCAL;  /* DACA1 Calibration Byte 0 */
-    register8_t DACA1GAINCAL;  /* DACA1 Calibration Byte 1 */
-    register8_t DACB1OFFCAL;  /* DACB1 Calibration Byte 0 */
-    register8_t DACB1GAINCAL;  /* DACB1 Calibration Byte 1 */
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-    register8_t reserved_0x3F;
-    register8_t reserved_0x40;
-    register8_t reserved_0x41;
-    register8_t reserved_0x42;
-    register8_t reserved_0x43;
-    register8_t reserved_0x44;
-    register8_t reserved_0x45;
-    register8_t reserved_0x46;
-    register8_t reserved_0x47;
-} NVM_PROD_SIGNATURES_t;
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Multi-level Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* I/O port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Module */
-#define CRC    (*(CRC_t *) 0x00D0)  /* Cyclic Redundancy Checker */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non-volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog-to-Digital Converter */
-#define ADCB    (*(ADC_t *) 0x0240)  /* Analog-to-Digital Converter */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital-to-Analog Converter */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator */
-#define ACB    (*(AC_t *) 0x0390)  /* Analog Comparator */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface */
-#define USB    (*(USB_t *) 0x04C0)  /* Universal Serial Bus */
-#define PORTA    (*(PORT_t *) 0x0600)  /* I/O Ports */
-#define PORTB    (*(PORT_t *) 0x0620)  /* I/O Ports */
-#define PORTC    (*(PORT_t *) 0x0640)  /* I/O Ports */
-#define PORTD    (*(PORT_t *) 0x0660)  /* I/O Ports */
-#define PORTE    (*(PORT_t *) 0x0680)  /* I/O Ports */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* I/O Ports */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* I/O Ports */
-#define TCC0    (*(TC0_t *) 0x0800)  /* 16-bit Timer/Counter 0 */
-#define TCC2    (*(TC2_t *) 0x0800)  /* 16-bit Timer/Counter type 2 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* 16-bit Timer/Counter 1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* 16-bit Timer/Counter 0 */
-#define TCD2    (*(TC2_t *) 0x0900)  /* 16-bit Timer/Counter type 2 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* 16-bit Timer/Counter 1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* 16-bit Timer/Counter 0 */
-#define TCE2    (*(TC2_t *) 0x0A00)  /* 16-bit Timer/Counter type 2 */
-#define TCE1    (*(TC1_t *) 0x0A40)  /* 16-bit Timer/Counter 1 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTE1    (*(USART_t *) 0x0AB0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* 16-bit Timer/Counter 0 */
-#define TCF2    (*(TC2_t *) 0x0B00)  /* 16-bit Timer/Counter type 2 */
-#define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension */
-#define USARTF0    (*(USART_t *) 0x0BA0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
-#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
-#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
-#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
-#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
-#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
-#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
-#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
-#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
-#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
-#define GPIO_GPIORA  _SFR_MEM8(0x000A)
-#define GPIO_GPIORB  _SFR_MEM8(0x000B)
-#define GPIO_GPIORC  _SFR_MEM8(0x000C)
-#define GPIO_GPIORD  _SFR_MEM8(0x000D)
-#define GPIO_GPIORE  _SFR_MEM8(0x000E)
-#define GPIO_GPIORF  _SFR_MEM8(0x000F)
-
-/* Deprecated */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* NVM_FUSES - Fuses */
-#define FUSE_FUSEBYTE0  _SFR_MEM8(0x0000)
-#define FUSE_FUSEBYTE1  _SFR_MEM8(0x0001)
-#define FUSE_FUSEBYTE2  _SFR_MEM8(0x0002)
-#define FUSE_FUSEBYTE4  _SFR_MEM8(0x0004)
-#define FUSE_FUSEBYTE5  _SFR_MEM8(0x0005)
-
-/* NVM_LOCKBITS - Lock Bits */
-#define LOCKBIT_LOCKBITS  _SFR_MEM8(0x0000)
-
-/* NVM_PROD_SIGNATURES - Production Signatures */
-#define PRODSIGNATURES_RCOSC2M  _SFR_MEM8(0x0000)
-#define PRODSIGNATURES_RCOSC2MA  _SFR_MEM8(0x0001)
-#define PRODSIGNATURES_RCOSC32K  _SFR_MEM8(0x0002)
-#define PRODSIGNATURES_RCOSC32M  _SFR_MEM8(0x0003)
-#define PRODSIGNATURES_RCOSC32MA  _SFR_MEM8(0x0004)
-#define PRODSIGNATURES_LOTNUM0  _SFR_MEM8(0x0008)
-#define PRODSIGNATURES_LOTNUM1  _SFR_MEM8(0x0009)
-#define PRODSIGNATURES_LOTNUM2  _SFR_MEM8(0x000A)
-#define PRODSIGNATURES_LOTNUM3  _SFR_MEM8(0x000B)
-#define PRODSIGNATURES_LOTNUM4  _SFR_MEM8(0x000C)
-#define PRODSIGNATURES_LOTNUM5  _SFR_MEM8(0x000D)
-#define PRODSIGNATURES_WAFNUM  _SFR_MEM8(0x0010)
-#define PRODSIGNATURES_COORDX0  _SFR_MEM8(0x0012)
-#define PRODSIGNATURES_COORDX1  _SFR_MEM8(0x0013)
-#define PRODSIGNATURES_COORDY0  _SFR_MEM8(0x0014)
-#define PRODSIGNATURES_COORDY1  _SFR_MEM8(0x0015)
-#define PRODSIGNATURES_USBCAL0  _SFR_MEM8(0x001A)
-#define PRODSIGNATURES_USBCAL1  _SFR_MEM8(0x001B)
-#define PRODSIGNATURES_USBRCOSC  _SFR_MEM8(0x001C)
-#define PRODSIGNATURES_USBRCOSCA  _SFR_MEM8(0x001D)
-#define PRODSIGNATURES_ADCACAL0  _SFR_MEM8(0x0020)
-#define PRODSIGNATURES_ADCACAL1  _SFR_MEM8(0x0021)
-#define PRODSIGNATURES_ADCBCAL0  _SFR_MEM8(0x0024)
-#define PRODSIGNATURES_ADCBCAL1  _SFR_MEM8(0x0025)
-#define PRODSIGNATURES_TEMPSENSE0  _SFR_MEM8(0x002E)
-#define PRODSIGNATURES_TEMPSENSE1  _SFR_MEM8(0x002F)
-#define PRODSIGNATURES_DACA0OFFCAL  _SFR_MEM8(0x0030)
-#define PRODSIGNATURES_DACA0GAINCAL  _SFR_MEM8(0x0031)
-#define PRODSIGNATURES_DACB0OFFCAL  _SFR_MEM8(0x0032)
-#define PRODSIGNATURES_DACB0GAINCAL  _SFR_MEM8(0x0033)
-#define PRODSIGNATURES_DACA1OFFCAL  _SFR_MEM8(0x0034)
-#define PRODSIGNATURES_DACA1GAINCAL  _SFR_MEM8(0x0035)
-#define PRODSIGNATURES_DACB1OFFCAL  _SFR_MEM8(0x0036)
-#define PRODSIGNATURES_DACB1GAINCAL  _SFR_MEM8(0x0037)
-
-/* VPORT - Virtual Port */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT - Virtual Port */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT - Virtual Port */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT - Virtual Port */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-#define CLK_USBCTRL  _SFR_MEM8(0x0044)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLL - DFLL */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLL - DFLL */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_ANAINIT  _SFR_MEM8(0x0097)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - I/O port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-#define PORTCFG_EBIOUT  _SFR_MEM8(0x00B5)
-#define PORTCFG_EVOUTSEL  _SFR_MEM8(0x00B6)
-
-/* AES - AES Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* CRC - Cyclic Redundancy Checker */
-#define CRC_CTRL  _SFR_MEM8(0x00D0)
-#define CRC_STATUS  _SFR_MEM8(0x00D1)
-#define CRC_DATAIN  _SFR_MEM8(0x00D3)
-#define CRC_CHECKSUM0  _SFR_MEM8(0x00D4)
-#define CRC_CHECKSUM1  _SFR_MEM8(0x00D5)
-#define CRC_CHECKSUM2  _SFR_MEM8(0x00D6)
-#define CRC_CHECKSUM3  _SFR_MEM8(0x00D7)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non-volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADC - Analog-to-Digital Converter */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_TEMP  _SFR_MEM8(0x0207)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH0_SCAN  _SFR_MEM8(0x0226)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH1_SCAN  _SFR_MEM8(0x022E)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH2_SCAN  _SFR_MEM8(0x0236)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-#define ADCA_CH3_SCAN  _SFR_MEM8(0x023E)
-
-/* ADC - Analog-to-Digital Converter */
-#define ADCB_CTRLA  _SFR_MEM8(0x0240)
-#define ADCB_CTRLB  _SFR_MEM8(0x0241)
-#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
-#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
-#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
-#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
-#define ADCB_TEMP  _SFR_MEM8(0x0247)
-#define ADCB_CAL  _SFR_MEM16(0x024C)
-#define ADCB_CH0RES  _SFR_MEM16(0x0250)
-#define ADCB_CH1RES  _SFR_MEM16(0x0252)
-#define ADCB_CH2RES  _SFR_MEM16(0x0254)
-#define ADCB_CH3RES  _SFR_MEM16(0x0256)
-#define ADCB_CMP  _SFR_MEM16(0x0258)
-#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
-#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
-#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
-#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
-#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
-#define ADCB_CH0_SCAN  _SFR_MEM8(0x0266)
-#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
-#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
-#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
-#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
-#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
-#define ADCB_CH1_SCAN  _SFR_MEM8(0x026E)
-#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
-#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
-#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
-#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
-#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
-#define ADCB_CH2_SCAN  _SFR_MEM8(0x0276)
-#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
-#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
-#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
-#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
-#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
-#define ADCB_CH3_SCAN  _SFR_MEM8(0x027E)
-
-/* DAC - Digital-to-Analog Converter */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_CH0GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_CH0OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH1GAINCAL  _SFR_MEM8(0x032A)
-#define DACB_CH1OFFSETCAL  _SFR_MEM8(0x032B)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* AC - Analog Comparator */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* AC - Analog Comparator */
-#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
-#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
-#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
-#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
-#define ACB_CTRLA  _SFR_MEM8(0x0394)
-#define ACB_CTRLB  _SFR_MEM8(0x0395)
-#define ACB_WINCTRL  _SFR_MEM8(0x0396)
-#define ACB_STATUS  _SFR_MEM8(0x0397)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWI - Two-Wire Interface */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWI - Two-Wire Interface */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* USB - Universal Serial Bus */
-#define USB_CTRLA  _SFR_MEM8(0x04C0)
-#define USB_CTRLB  _SFR_MEM8(0x04C1)
-#define USB_STATUS  _SFR_MEM8(0x04C2)
-#define USB_ADDR  _SFR_MEM8(0x04C3)
-#define USB_FIFOWP  _SFR_MEM8(0x04C4)
-#define USB_FIFORP  _SFR_MEM8(0x04C5)
-#define USB_EPPTR  _SFR_MEM16(0x04C6)
-#define USB_INTCTRLA  _SFR_MEM8(0x04C8)
-#define USB_INTCTRLB  _SFR_MEM8(0x04C9)
-#define USB_INTFLAGSACLR  _SFR_MEM8(0x04CA)
-#define USB_INTFLAGSASET  _SFR_MEM8(0x04CB)
-#define USB_INTFLAGSBCLR  _SFR_MEM8(0x04CC)
-#define USB_INTFLAGSBSET  _SFR_MEM8(0x04CD)
-#define USB_CAL0  _SFR_MEM8(0x04FA)
-#define USB_CAL1  _SFR_MEM8(0x04FB)
-
-/* PORT - I/O Ports */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_REMAP  _SFR_MEM8(0x060E)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORT - I/O Ports */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_REMAP  _SFR_MEM8(0x062E)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORT - I/O Ports */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_REMAP  _SFR_MEM8(0x064E)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORT - I/O Ports */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_REMAP  _SFR_MEM8(0x066E)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORT - I/O Ports */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_REMAP  _SFR_MEM8(0x068E)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORT - I/O Ports */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_REMAP  _SFR_MEM8(0x06AE)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORT - I/O Ports */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_REMAP  _SFR_MEM8(0x07EE)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TC0 - 16-bit Timer/Counter 0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TC2 - 16-bit Timer/Counter type 2 */
-#define TCC2_CTRLA  _SFR_MEM8(0x0800)
-#define TCC2_CTRLB  _SFR_MEM8(0x0801)
-#define TCC2_CTRLC  _SFR_MEM8(0x0802)
-#define TCC2_CTRLE  _SFR_MEM8(0x0804)
-#define TCC2_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC2_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC2_CTRLF  _SFR_MEM8(0x0809)
-#define TCC2_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC2_LCNT  _SFR_MEM8(0x0820)
-#define TCC2_HCNT  _SFR_MEM8(0x0821)
-#define TCC2_LPER  _SFR_MEM8(0x0826)
-#define TCC2_HPER  _SFR_MEM8(0x0827)
-#define TCC2_LCMPA  _SFR_MEM8(0x0828)
-#define TCC2_HCMPA  _SFR_MEM8(0x0829)
-#define TCC2_LCMPB  _SFR_MEM8(0x082A)
-#define TCC2_HCMPB  _SFR_MEM8(0x082B)
-#define TCC2_LCMPC  _SFR_MEM8(0x082C)
-#define TCC2_HCMPC  _SFR_MEM8(0x082D)
-#define TCC2_LCMPD  _SFR_MEM8(0x082E)
-#define TCC2_HCMPD  _SFR_MEM8(0x082F)
-
-/* TC1 - 16-bit Timer/Counter 1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEX - Advanced Waveform Extension */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_STATUSSET  _SFR_MEM8(0x0885)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRES - High-Resolution Extension */
-#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPI - Serial Peripheral Interface */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TC0 - 16-bit Timer/Counter 0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TC2 - 16-bit Timer/Counter type 2 */
-#define TCD2_CTRLA  _SFR_MEM8(0x0900)
-#define TCD2_CTRLB  _SFR_MEM8(0x0901)
-#define TCD2_CTRLC  _SFR_MEM8(0x0902)
-#define TCD2_CTRLE  _SFR_MEM8(0x0904)
-#define TCD2_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD2_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD2_CTRLF  _SFR_MEM8(0x0909)
-#define TCD2_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD2_LCNT  _SFR_MEM8(0x0920)
-#define TCD2_HCNT  _SFR_MEM8(0x0921)
-#define TCD2_LPER  _SFR_MEM8(0x0926)
-#define TCD2_HPER  _SFR_MEM8(0x0927)
-#define TCD2_LCMPA  _SFR_MEM8(0x0928)
-#define TCD2_HCMPA  _SFR_MEM8(0x0929)
-#define TCD2_LCMPB  _SFR_MEM8(0x092A)
-#define TCD2_HCMPB  _SFR_MEM8(0x092B)
-#define TCD2_LCMPC  _SFR_MEM8(0x092C)
-#define TCD2_HCMPC  _SFR_MEM8(0x092D)
-#define TCD2_LCMPD  _SFR_MEM8(0x092E)
-#define TCD2_HCMPD  _SFR_MEM8(0x092F)
-
-/* TC1 - 16-bit Timer/Counter 1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRES - High-Resolution Extension */
-#define HIRESD_CTRLA  _SFR_MEM8(0x0990)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPI - Serial Peripheral Interface */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TC0 - 16-bit Timer/Counter 0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* TC2 - 16-bit Timer/Counter type 2 */
-#define TCE2_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE2_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE2_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE2_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE2_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE2_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE2_CTRLF  _SFR_MEM8(0x0A09)
-#define TCE2_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE2_LCNT  _SFR_MEM8(0x0A20)
-#define TCE2_HCNT  _SFR_MEM8(0x0A21)
-#define TCE2_LPER  _SFR_MEM8(0x0A26)
-#define TCE2_HPER  _SFR_MEM8(0x0A27)
-#define TCE2_LCMPA  _SFR_MEM8(0x0A28)
-#define TCE2_HCMPA  _SFR_MEM8(0x0A29)
-#define TCE2_LCMPB  _SFR_MEM8(0x0A2A)
-#define TCE2_HCMPB  _SFR_MEM8(0x0A2B)
-#define TCE2_LCMPC  _SFR_MEM8(0x0A2C)
-#define TCE2_HCMPC  _SFR_MEM8(0x0A2D)
-#define TCE2_LCMPD  _SFR_MEM8(0x0A2E)
-#define TCE2_HCMPD  _SFR_MEM8(0x0A2F)
-
-/* TC1 - 16-bit Timer/Counter 1 */
-#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
-#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
-#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
-#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
-#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
-#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
-#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
-#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
-#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
-#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
-#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
-#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
-#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
-#define TCE1_CNT  _SFR_MEM16(0x0A60)
-#define TCE1_PER  _SFR_MEM16(0x0A66)
-#define TCE1_CCA  _SFR_MEM16(0x0A68)
-#define TCE1_CCB  _SFR_MEM16(0x0A6A)
-#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
-#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
-#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
-
-/* AWEX - Advanced Waveform Extension */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_STATUSSET  _SFR_MEM8(0x0A85)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* HIRES - High-Resolution Extension */
-#define HIRESE_CTRLA  _SFR_MEM8(0x0A90)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTE1_DATA  _SFR_MEM8(0x0AB0)
-#define USARTE1_STATUS  _SFR_MEM8(0x0AB1)
-#define USARTE1_CTRLA  _SFR_MEM8(0x0AB3)
-#define USARTE1_CTRLB  _SFR_MEM8(0x0AB4)
-#define USARTE1_CTRLC  _SFR_MEM8(0x0AB5)
-#define USARTE1_BAUDCTRLA  _SFR_MEM8(0x0AB6)
-#define USARTE1_BAUDCTRLB  _SFR_MEM8(0x0AB7)
-
-/* SPI - Serial Peripheral Interface */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TC0 - 16-bit Timer/Counter 0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-/* TC2 - 16-bit Timer/Counter type 2 */
-#define TCF2_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF2_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF2_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF2_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF2_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF2_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF2_CTRLF  _SFR_MEM8(0x0B09)
-#define TCF2_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF2_LCNT  _SFR_MEM8(0x0B20)
-#define TCF2_HCNT  _SFR_MEM8(0x0B21)
-#define TCF2_LPER  _SFR_MEM8(0x0B26)
-#define TCF2_HPER  _SFR_MEM8(0x0B27)
-#define TCF2_LCMPA  _SFR_MEM8(0x0B28)
-#define TCF2_HCMPA  _SFR_MEM8(0x0B29)
-#define TCF2_LCMPB  _SFR_MEM8(0x0B2A)
-#define TCF2_HCMPB  _SFR_MEM8(0x0B2B)
-#define TCF2_LCMPC  _SFR_MEM8(0x0B2C)
-#define TCF2_HCMPC  _SFR_MEM8(0x0B2D)
-#define TCF2_LCMPD  _SFR_MEM8(0x0B2E)
-#define TCF2_HCMPD  _SFR_MEM8(0x0B2F)
-
-/* HIRES - High-Resolution Extension */
-#define HIRESF_CTRLA  _SFR_MEM8(0x0B90)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
-#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
-#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
-#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
-#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
-#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
-#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* VPORT - Virtual Ports */
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR0  bit masks and bit positions */
-#define OCD_OCDRD_gm  0xFF  /* OCDR Dirty group mask. */
-#define OCD_OCDRD_gp  0  /* OCDR Dirty group position. */
-#define OCD_OCDRD0_bm  (1<<0)  /* OCDR Dirty bit 0 mask. */
-#define OCD_OCDRD0_bp  0  /* OCDR Dirty bit 0 position. */
-#define OCD_OCDRD1_bm  (1<<1)  /* OCDR Dirty bit 1 mask. */
-#define OCD_OCDRD1_bp  1  /* OCDR Dirty bit 1 position. */
-#define OCD_OCDRD2_bm  (1<<2)  /* OCDR Dirty bit 2 mask. */
-#define OCD_OCDRD2_bp  2  /* OCDR Dirty bit 2 position. */
-#define OCD_OCDRD3_bm  (1<<3)  /* OCDR Dirty bit 3 mask. */
-#define OCD_OCDRD3_bp  3  /* OCDR Dirty bit 3 position. */
-#define OCD_OCDRD4_bm  (1<<4)  /* OCDR Dirty bit 4 mask. */
-#define OCD_OCDRD4_bp  4  /* OCDR Dirty bit 4 position. */
-#define OCD_OCDRD5_bm  (1<<5)  /* OCDR Dirty bit 5 mask. */
-#define OCD_OCDRD5_bp  5  /* OCDR Dirty bit 5 position. */
-#define OCD_OCDRD6_bm  (1<<6)  /* OCDR Dirty bit 6 mask. */
-#define OCD_OCDRD6_bp  6  /* OCDR Dirty bit 6 position. */
-#define OCD_OCDRD7_bm  (1<<7)  /* OCDR Dirty bit 7 mask. */
-#define OCD_OCDRD7_bp  7  /* OCDR Dirty bit 7 position. */
-
-/* OCD.OCDR1  bit masks and bit positions */
-/* OCD_OCDRD  Predefined. */
-/* OCD_OCDRD  Predefined. */
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* Clock Source Enable bit position. */
-
-/* CLK.USBCTRL  bit masks and bit positions */
-#define CLK_USBPSDIV_gm  0x38  /* Prescaler Division Factor group mask. */
-#define CLK_USBPSDIV_gp  3  /* Prescaler Division Factor group position. */
-#define CLK_USBPSDIV0_bm  (1<<3)  /* Prescaler Division Factor bit 0 mask. */
-#define CLK_USBPSDIV0_bp  3  /* Prescaler Division Factor bit 0 position. */
-#define CLK_USBPSDIV1_bm  (1<<4)  /* Prescaler Division Factor bit 1 mask. */
-#define CLK_USBPSDIV1_bp  4  /* Prescaler Division Factor bit 1 position. */
-#define CLK_USBPSDIV2_bm  (1<<5)  /* Prescaler Division Factor bit 2 mask. */
-#define CLK_USBPSDIV2_bp  5  /* Prescaler Division Factor bit 2 position. */
-
-#define CLK_USBSRC_gm  0x06  /* Clock Source group mask. */
-#define CLK_USBSRC_gp  1  /* Clock Source group position. */
-#define CLK_USBSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_USBSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_USBSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_USBSRC1_bp  2  /* Clock Source bit 1 position. */
-
-#define CLK_USBSEN_bm  0x01  /* Clock Source Enable bit mask. */
-#define CLK_USBSEN_bp  0  /* Clock Source Enable bit position. */
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_USB_bm  0x40  /* USB bit mask. */
-#define PR_USB_bp  6  /* USB bit position. */
-
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC  Predefined. */
-/* PR_DAC  Predefined. */
-
-/* PR_ADC  Predefined. */
-/* PR_ADC  Predefined. */
-
-/* PR_AC  Predefined. */
-/* PR_AC  Predefined. */
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI  Predefined. */
-/* PR_TWI  Predefined. */
-
-/* PR_USART1  Predefined. */
-/* PR_USART1  Predefined. */
-
-/* PR_USART0  Predefined. */
-/* PR_USART0  Predefined. */
-
-/* PR_SPI  Predefined. */
-/* PR_SPI  Predefined. */
-
-/* PR_HIRES  Predefined. */
-/* PR_HIRES  Predefined. */
-
-/* PR_TC1  Predefined. */
-/* PR_TC1  Predefined. */
-
-/* PR_TC0  Predefined. */
-/* PR_TC0  Predefined. */
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI  Predefined. */
-/* PR_TWI  Predefined. */
-
-/* PR_USART1  Predefined. */
-/* PR_USART1  Predefined. */
-
-/* PR_USART0  Predefined. */
-/* PR_USART0  Predefined. */
-
-/* PR_SPI  Predefined. */
-/* PR_SPI  Predefined. */
-
-/* PR_HIRES  Predefined. */
-/* PR_HIRES  Predefined. */
-
-/* PR_TC1  Predefined. */
-/* PR_TC1  Predefined. */
-
-/* PR_TC0  Predefined. */
-/* PR_TC0  Predefined. */
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI  Predefined. */
-/* PR_TWI  Predefined. */
-
-/* PR_USART1  Predefined. */
-/* PR_USART1  Predefined. */
-
-/* PR_USART0  Predefined. */
-/* PR_USART0  Predefined. */
-
-/* PR_SPI  Predefined. */
-/* PR_SPI  Predefined. */
-
-/* PR_HIRES  Predefined. */
-/* PR_HIRES  Predefined. */
-
-/* PR_TC1  Predefined. */
-/* PR_TC1  Predefined. */
-
-/* PR_TC0  Predefined. */
-/* PR_TC0  Predefined. */
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32.768 kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32 MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32 MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2 MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2 MHz RC Oscillator Enable bit position. */
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32.768 kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32 MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32 MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2 MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2 MHz RC Oscillator Ready bit position. */
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCPWR_bm  0x10  /* 16 MHz Crystal Oscillator High Power mode bit mask. */
-#define OSC_XOSCPWR_bp  4  /* 16 MHz Crystal Oscillator High Power mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_PLLFDIF_bm  0x08  /* PLL Failure Detection Interrupt Flag bit mask. */
-#define OSC_PLLFDIF_bp  3  /* PLL Failure Detection Interrupt Flag bit position. */
-
-#define OSC_PLLFDEN_bm  0x04  /* PLL Failure Detection Enable bit mask. */
-#define OSC_PLLFDEN_bp  2  /* PLL Failure Detection Enable bit position. */
-
-#define OSC_XOSCFDIF_bm  0x02  /* XOSC Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* XOSC Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* XOSC Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* XOSC Failure Detection Enable bit position. */
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLDIV_bm  0x20  /* Divide by 2 bit mask. */
-#define OSC_PLLDIV_bp  5  /* Divide by 2 bit position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_gm  0x06  /* 32 MHz DFLL Calibration Reference group mask. */
-#define OSC_RC32MCREF_gp  1  /* 32 MHz DFLL Calibration Reference group position. */
-#define OSC_RC32MCREF0_bm  (1<<1)  /* 32 MHz DFLL Calibration Reference bit 0 mask. */
-#define OSC_RC32MCREF0_bp  1  /* 32 MHz DFLL Calibration Reference bit 0 position. */
-#define OSC_RC32MCREF1_bm  (1<<2)  /* 32 MHz DFLL Calibration Reference bit 1 mask. */
-#define OSC_RC32MCREF1_bp  2  /* 32 MHz DFLL Calibration Reference bit 1 position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2 MHz DFLL Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2 MHz DFLL Calibration Reference bit position. */
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration Value A group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration Value A group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration Value A bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration Value A bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration Value A bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration Value A bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration Value A bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration Value A bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration Value A bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration Value A bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration Value A bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration Value A bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration Value A bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration Value A bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration Value A bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration Value A bit 6 position. */
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration Value B group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration Value B group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration Value B bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration Value B bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration Value B bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration Value B bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration Value B bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration Value B bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration Value B bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration Value B bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration Value B bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration Value B bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration Value B bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration Value B bit 5 position. */
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-/* MCU.ANAINIT  bit masks and bit positions */
-#define MCU_STARTUPDLYB_gm  0x0C  /* Analog startup delay Port B group mask. */
-#define MCU_STARTUPDLYB_gp  2  /* Analog startup delay Port B group position. */
-#define MCU_STARTUPDLYB0_bm  (1<<2)  /* Analog startup delay Port B bit 0 mask. */
-#define MCU_STARTUPDLYB0_bp  2  /* Analog startup delay Port B bit 0 position. */
-#define MCU_STARTUPDLYB1_bm  (1<<3)  /* Analog startup delay Port B bit 1 mask. */
-#define MCU_STARTUPDLYB1_bp  3  /* Analog startup delay Port B bit 1 position. */
-
-#define MCU_STARTUPDLYA_gm  0x03  /* Analog startup delay Port A group mask. */
-#define MCU_STARTUPDLYA_gp  0  /* Analog startup delay Port A group position. */
-#define MCU_STARTUPDLYA0_bm  (1<<0)  /* Analog startup delay Port A bit 0 mask. */
-#define MCU_STARTUPDLYA0_bp  0  /* Analog startup delay Port A bit 0 position. */
-#define MCU_STARTUPDLYA1_bm  (1<<1)  /* Analog startup delay Port A bit 1 mask. */
-#define MCU_STARTUPDLYA1_bp  1  /* Analog startup delay Port A bit 1 position. */
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXFLOCK_bm  0x08  /* AWeX on T/C F0 Lock bit mask. */
-#define MCU_AWEXFLOCK_bp  3  /* AWeX on T/C F0 Lock bit position. */
-
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXDLOCK_bm  0x02  /* AWeX on T/C D0 Lock bit mask. */
-#define MCU_AWEXDLOCK_bp  1  /* AWeX on T/C D0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-/* PMIC.INTPRI  bit masks and bit positions */
-#define PMIC_INTPRI_gm  0xFF  /* Interrupt Priority group mask. */
-#define PMIC_INTPRI_gp  0  /* Interrupt Priority group position. */
-#define PMIC_INTPRI0_bm  (1<<0)  /* Interrupt Priority bit 0 mask. */
-#define PMIC_INTPRI0_bp  0  /* Interrupt Priority bit 0 position. */
-#define PMIC_INTPRI1_bm  (1<<1)  /* Interrupt Priority bit 1 mask. */
-#define PMIC_INTPRI1_bp  1  /* Interrupt Priority bit 1 position. */
-#define PMIC_INTPRI2_bm  (1<<2)  /* Interrupt Priority bit 2 mask. */
-#define PMIC_INTPRI2_bp  2  /* Interrupt Priority bit 2 position. */
-#define PMIC_INTPRI3_bm  (1<<3)  /* Interrupt Priority bit 3 mask. */
-#define PMIC_INTPRI3_bp  3  /* Interrupt Priority bit 3 position. */
-#define PMIC_INTPRI4_bm  (1<<4)  /* Interrupt Priority bit 4 mask. */
-#define PMIC_INTPRI4_bp  4  /* Interrupt Priority bit 4 position. */
-#define PMIC_INTPRI5_bm  (1<<5)  /* Interrupt Priority bit 5 mask. */
-#define PMIC_INTPRI5_bp  5  /* Interrupt Priority bit 5 position. */
-#define PMIC_INTPRI6_bm  (1<<6)  /* Interrupt Priority bit 6 mask. */
-#define PMIC_INTPRI6_bp  6  /* Interrupt Priority bit 6 position. */
-#define PMIC_INTPRI7_bm  (1<<7)  /* Interrupt Priority bit 7 mask. */
-#define PMIC_INTPRI7_bp  7  /* Interrupt Priority bit 7 position. */
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-/* PORTCFG - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Peripheral Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Peripheral Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Peripheral Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Peripheral Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Peripheral Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Peripheral Clock Output Port bit 1 position. */
-
-#define PORTCFG_CLKOUTSEL_gm  0x0C  /* Peripheral Clock Output Select group mask. */
-#define PORTCFG_CLKOUTSEL_gp  2  /* Peripheral Clock Output Select group position. */
-#define PORTCFG_CLKOUTSEL0_bm  (1<<2)  /* Peripheral Clock Output Select bit 0 mask. */
-#define PORTCFG_CLKOUTSEL0_bp  2  /* Peripheral Clock Output Select bit 0 position. */
-#define PORTCFG_CLKOUTSEL1_bm  (1<<3)  /* Peripheral Clock Output Select bit 1 mask. */
-#define PORTCFG_CLKOUTSEL1_bp  3  /* Peripheral Clock Output Select bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-#define PORTCFG_RTCOUT_bm  0x40  /* RTC Clock Output bit mask. */
-#define PORTCFG_RTCOUT_bp  6  /* RTC Clock Output bit position. */
-
-#define PORTCFG_CLKEVPIN_bm  0x80  /* Peripheral Clock and Event Output pin Select bit mask. */
-#define PORTCFG_CLKEVPIN_bp  7  /* Peripheral Clock and Event Output pin Select bit position. */
-
-/* PORTCFG.EBIOUT  bit masks and bit positions */
-#define PORTCFG_EBICSOUT_gm  0x03  /* EBI Chip Select Output group mask. */
-#define PORTCFG_EBICSOUT_gp  0  /* EBI Chip Select Output group position. */
-#define PORTCFG_EBICSOUT0_bm  (1<<0)  /* EBI Chip Select Output bit 0 mask. */
-#define PORTCFG_EBICSOUT0_bp  0  /* EBI Chip Select Output bit 0 position. */
-#define PORTCFG_EBICSOUT1_bm  (1<<1)  /* EBI Chip Select Output bit 1 mask. */
-#define PORTCFG_EBICSOUT1_bp  1  /* EBI Chip Select Output bit 1 position. */
-
-#define PORTCFG_EBIADROUT_gm  0x0C  /* EBI Address Output group mask. */
-#define PORTCFG_EBIADROUT_gp  2  /* EBI Address Output group position. */
-#define PORTCFG_EBIADROUT0_bm  (1<<2)  /* EBI Address Output bit 0 mask. */
-#define PORTCFG_EBIADROUT0_bp  2  /* EBI Address Output bit 0 position. */
-#define PORTCFG_EBIADROUT1_bm  (1<<3)  /* EBI Address Output bit 1 mask. */
-#define PORTCFG_EBIADROUT1_bp  3  /* EBI Address Output bit 1 position. */
-
-/* PORTCFG.EVOUTSEL  bit masks and bit positions */
-#define PORTCFG_EVOUTSEL_gm  0x07  /* Event Output Select group mask. */
-#define PORTCFG_EVOUTSEL_gp  0  /* Event Output Select group position. */
-#define PORTCFG_EVOUTSEL0_bm  (1<<0)  /* Event Output Select bit 0 mask. */
-#define PORTCFG_EVOUTSEL0_bp  0  /* Event Output Select bit 0 position. */
-#define PORTCFG_EVOUTSEL1_bm  (1<<1)  /* Event Output Select bit 1 mask. */
-#define PORTCFG_EVOUTSEL1_bp  1  /* Event Output Select bit 1 position. */
-#define PORTCFG_EVOUTSEL2_bm  (1<<2)  /* Event Output Select bit 2 mask. */
-#define PORTCFG_EVOUTSEL2_bp  2  /* Event Output Select bit 2 position. */
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-/* CRC - Cyclic Redundancy Checker */
-/* CRC.CTRL  bit masks and bit positions */
-#define CRC_RESET_gm  0xC0  /* Reset group mask. */
-#define CRC_RESET_gp  6  /* Reset group position. */
-#define CRC_RESET0_bm  (1<<6)  /* Reset bit 0 mask. */
-#define CRC_RESET0_bp  6  /* Reset bit 0 position. */
-#define CRC_RESET1_bm  (1<<7)  /* Reset bit 1 mask. */
-#define CRC_RESET1_bp  7  /* Reset bit 1 position. */
-
-#define CRC_CRC32_bm  0x20  /* CRC Mode bit mask. */
-#define CRC_CRC32_bp  5  /* CRC Mode bit position. */
-
-#define CRC_SOURCE_gm  0x0F  /* Input Source group mask. */
-#define CRC_SOURCE_gp  0  /* Input Source group position. */
-#define CRC_SOURCE0_bm  (1<<0)  /* Input Source bit 0 mask. */
-#define CRC_SOURCE0_bp  0  /* Input Source bit 0 position. */
-#define CRC_SOURCE1_bm  (1<<1)  /* Input Source bit 1 mask. */
-#define CRC_SOURCE1_bp  1  /* Input Source bit 1 position. */
-#define CRC_SOURCE2_bm  (1<<2)  /* Input Source bit 2 mask. */
-#define CRC_SOURCE2_bp  2  /* Input Source bit 2 position. */
-#define CRC_SOURCE3_bm  (1<<3)  /* Input Source bit 3 mask. */
-#define CRC_SOURCE3_bp  3  /* Input Source bit 3 position. */
-
-/* CRC.STATUS  bit masks and bit positions */
-#define CRC_ZERO_bm  0x02  /* Zero detection bit mask. */
-#define CRC_ZERO_bp  1  /* Zero detection bit position. */
-
-#define CRC_BUSY_bm  0x01  /* Busy bit mask. */
-#define CRC_BUSY_bp  0  /* Busy bit position. */
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM  Predefined. */
-/* EVSYS_QDIRM  Predefined. */
-
-/* EVSYS_QDIEN  Predefined. */
-/* EVSYS_QDIEN  Predefined. */
-
-/* EVSYS_QDEN  Predefined. */
-/* EVSYS_QDEN  Predefined. */
-
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM  Predefined. */
-/* EVSYS_QDIRM  Predefined. */
-
-/* EVSYS_QDIEN  Predefined. */
-/* EVSYS_QDIEN  Predefined. */
-
-/* EVSYS_QDEN  Predefined. */
-/* EVSYS_QDEN  Predefined. */
-
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0x7F  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAIN_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAIN_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAIN0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAIN0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAIN1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAIN1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAIN2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAIN2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* MUX selection on Positive ADC input group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* MUX selection on Positive ADC input group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* MUX selection on Positive ADC input bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* MUX selection on Positive ADC input bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* MUX selection on Positive ADC input bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* MUX selection on Positive ADC input bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* MUX selection on Positive ADC input bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* MUX selection on Positive ADC input bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* MUX selection on Positive ADC input bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* MUX selection on Positive ADC input bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* MUX selection on Internal ADC input group mask. */
-#define ADC_CH_MUXINT_gp  3  /* MUX selection on Internal ADC input group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* MUX selection on Internal ADC input bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* MUX selection on Internal ADC input bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* MUX selection on Internal ADC input bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* MUX selection on Internal ADC input bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* MUX selection on Internal ADC input bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* MUX selection on Internal ADC input bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* MUX selection on Internal ADC input bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* MUX selection on Internal ADC input bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x07  /* MUX selection on Negative ADC input group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* MUX selection on Negative ADC input group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* MUX selection on Negative ADC input bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* MUX selection on Negative ADC input bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* MUX selection on Negative ADC input bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* MUX selection on Negative ADC input bit 1 position. */
-#define ADC_CH_MUXNEG2_bm  (1<<2)  /* MUX selection on Negative ADC input bit 2 mask. */
-#define ADC_CH_MUXNEG2_bp  2  /* MUX selection on Negative ADC input bit 2 position. */
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-/* ADC_CH.SCAN  bit masks and bit positions */
-#define ADC_CH_OFFSET_gm  0xF0  /* Positive MUX setting offset group mask. */
-#define ADC_CH_OFFSET_gp  4  /* Positive MUX setting offset group position. */
-#define ADC_CH_OFFSET0_bm  (1<<4)  /* Positive MUX setting offset bit 0 mask. */
-#define ADC_CH_OFFSET0_bp  4  /* Positive MUX setting offset bit 0 position. */
-#define ADC_CH_OFFSET1_bm  (1<<5)  /* Positive MUX setting offset bit 1 mask. */
-#define ADC_CH_OFFSET1_bp  5  /* Positive MUX setting offset bit 1 position. */
-#define ADC_CH_OFFSET2_bm  (1<<6)  /* Positive MUX setting offset bit 2 mask. */
-#define ADC_CH_OFFSET2_bp  6  /* Positive MUX setting offset bit 2 position. */
-#define ADC_CH_OFFSET3_bm  (1<<7)  /* Positive MUX setting offset bit 3 mask. */
-#define ADC_CH_OFFSET3_bp  7  /* Positive MUX setting offset bit 3 position. */
-
-#define ADC_CH_SCANNUM_gm  0x0F  /* Number of Channels included in scan group mask. */
-#define ADC_CH_SCANNUM_gp  0  /* Number of Channels included in scan group position. */
-#define ADC_CH_SCANNUM0_bm  (1<<0)  /* Number of Channels included in scan bit 0 mask. */
-#define ADC_CH_SCANNUM0_bp  0  /* Number of Channels included in scan bit 0 position. */
-#define ADC_CH_SCANNUM1_bm  (1<<1)  /* Number of Channels included in scan bit 1 mask. */
-#define ADC_CH_SCANNUM1_bp  1  /* Number of Channels included in scan bit 1 position. */
-#define ADC_CH_SCANNUM2_bm  (1<<2)  /* Number of Channels included in scan bit 2 mask. */
-#define ADC_CH_SCANNUM2_bp  2  /* Number of Channels included in scan bit 2 position. */
-#define ADC_CH_SCANNUM3_bm  (1<<3)  /* Number of Channels included in scan bit 3 mask. */
-#define ADC_CH_SCANNUM3_bp  3  /* Number of Channels included in scan bit 3 position. */
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_IMPMODE_bm  0x80  /* Gain Stage Impedance Mode bit mask. */
-#define ADC_IMPMODE_bp  7  /* Gain Stage Impedance Mode bit position. */
-
-#define ADC_CURRLIMIT_gm  0x60  /* Current Limitation group mask. */
-#define ADC_CURRLIMIT_gp  5  /* Current Limitation group position. */
-#define ADC_CURRLIMIT0_bm  (1<<5)  /* Current Limitation bit 0 mask. */
-#define ADC_CURRLIMIT0_bp  5  /* Current Limitation bit 0 position. */
-#define ADC_CURRLIMIT1_bm  (1<<6)  /* Current Limitation bit 1 mask. */
-#define ADC_CURRLIMIT1_bp  6  /* Current Limitation bit 1 position. */
-
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
-#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSPLIT_bm  0x08  /* Separate Event Channel Input for Channel 1 bit mask. */
-#define DAC_EVSPLIT_bp  3  /* Separate Event Channel Input for Channel 1 bit position. */
-
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-/* DAC.CH0GAINCAL  bit masks and bit positions */
-#define DAC_CH0GAINCAL_gm  0x7F  /* Gain Calibration group mask. */
-#define DAC_CH0GAINCAL_gp  0  /* Gain Calibration group position. */
-#define DAC_CH0GAINCAL0_bm  (1<<0)  /* Gain Calibration bit 0 mask. */
-#define DAC_CH0GAINCAL0_bp  0  /* Gain Calibration bit 0 position. */
-#define DAC_CH0GAINCAL1_bm  (1<<1)  /* Gain Calibration bit 1 mask. */
-#define DAC_CH0GAINCAL1_bp  1  /* Gain Calibration bit 1 position. */
-#define DAC_CH0GAINCAL2_bm  (1<<2)  /* Gain Calibration bit 2 mask. */
-#define DAC_CH0GAINCAL2_bp  2  /* Gain Calibration bit 2 position. */
-#define DAC_CH0GAINCAL3_bm  (1<<3)  /* Gain Calibration bit 3 mask. */
-#define DAC_CH0GAINCAL3_bp  3  /* Gain Calibration bit 3 position. */
-#define DAC_CH0GAINCAL4_bm  (1<<4)  /* Gain Calibration bit 4 mask. */
-#define DAC_CH0GAINCAL4_bp  4  /* Gain Calibration bit 4 position. */
-#define DAC_CH0GAINCAL5_bm  (1<<5)  /* Gain Calibration bit 5 mask. */
-#define DAC_CH0GAINCAL5_bp  5  /* Gain Calibration bit 5 position. */
-#define DAC_CH0GAINCAL6_bm  (1<<6)  /* Gain Calibration bit 6 mask. */
-#define DAC_CH0GAINCAL6_bp  6  /* Gain Calibration bit 6 position. */
-
-/* DAC.CH0OFFSETCAL  bit masks and bit positions */
-#define DAC_CH0OFFSETCAL_gm  0x7F  /* Offset Calibration group mask. */
-#define DAC_CH0OFFSETCAL_gp  0  /* Offset Calibration group position. */
-#define DAC_CH0OFFSETCAL0_bm  (1<<0)  /* Offset Calibration bit 0 mask. */
-#define DAC_CH0OFFSETCAL0_bp  0  /* Offset Calibration bit 0 position. */
-#define DAC_CH0OFFSETCAL1_bm  (1<<1)  /* Offset Calibration bit 1 mask. */
-#define DAC_CH0OFFSETCAL1_bp  1  /* Offset Calibration bit 1 position. */
-#define DAC_CH0OFFSETCAL2_bm  (1<<2)  /* Offset Calibration bit 2 mask. */
-#define DAC_CH0OFFSETCAL2_bp  2  /* Offset Calibration bit 2 position. */
-#define DAC_CH0OFFSETCAL3_bm  (1<<3)  /* Offset Calibration bit 3 mask. */
-#define DAC_CH0OFFSETCAL3_bp  3  /* Offset Calibration bit 3 position. */
-#define DAC_CH0OFFSETCAL4_bm  (1<<4)  /* Offset Calibration bit 4 mask. */
-#define DAC_CH0OFFSETCAL4_bp  4  /* Offset Calibration bit 4 position. */
-#define DAC_CH0OFFSETCAL5_bm  (1<<5)  /* Offset Calibration bit 5 mask. */
-#define DAC_CH0OFFSETCAL5_bp  5  /* Offset Calibration bit 5 position. */
-#define DAC_CH0OFFSETCAL6_bm  (1<<6)  /* Offset Calibration bit 6 mask. */
-#define DAC_CH0OFFSETCAL6_bp  6  /* Offset Calibration bit 6 position. */
-
-/* DAC.CH1GAINCAL  bit masks and bit positions */
-#define DAC_CH1GAINCAL_gm  0x7F  /* Gain Calibration group mask. */
-#define DAC_CH1GAINCAL_gp  0  /* Gain Calibration group position. */
-#define DAC_CH1GAINCAL0_bm  (1<<0)  /* Gain Calibration bit 0 mask. */
-#define DAC_CH1GAINCAL0_bp  0  /* Gain Calibration bit 0 position. */
-#define DAC_CH1GAINCAL1_bm  (1<<1)  /* Gain Calibration bit 1 mask. */
-#define DAC_CH1GAINCAL1_bp  1  /* Gain Calibration bit 1 position. */
-#define DAC_CH1GAINCAL2_bm  (1<<2)  /* Gain Calibration bit 2 mask. */
-#define DAC_CH1GAINCAL2_bp  2  /* Gain Calibration bit 2 position. */
-#define DAC_CH1GAINCAL3_bm  (1<<3)  /* Gain Calibration bit 3 mask. */
-#define DAC_CH1GAINCAL3_bp  3  /* Gain Calibration bit 3 position. */
-#define DAC_CH1GAINCAL4_bm  (1<<4)  /* Gain Calibration bit 4 mask. */
-#define DAC_CH1GAINCAL4_bp  4  /* Gain Calibration bit 4 position. */
-#define DAC_CH1GAINCAL5_bm  (1<<5)  /* Gain Calibration bit 5 mask. */
-#define DAC_CH1GAINCAL5_bp  5  /* Gain Calibration bit 5 position. */
-#define DAC_CH1GAINCAL6_bm  (1<<6)  /* Gain Calibration bit 6 mask. */
-#define DAC_CH1GAINCAL6_bp  6  /* Gain Calibration bit 6 position. */
-
-/* DAC.CH1OFFSETCAL  bit masks and bit positions */
-#define DAC_CH1OFFSETCAL_gm  0x7F  /* Offset Calibration group mask. */
-#define DAC_CH1OFFSETCAL_gp  0  /* Offset Calibration group position. */
-#define DAC_CH1OFFSETCAL0_bm  (1<<0)  /* Offset Calibration bit 0 mask. */
-#define DAC_CH1OFFSETCAL0_bp  0  /* Offset Calibration bit 0 position. */
-#define DAC_CH1OFFSETCAL1_bm  (1<<1)  /* Offset Calibration bit 1 mask. */
-#define DAC_CH1OFFSETCAL1_bp  1  /* Offset Calibration bit 1 position. */
-#define DAC_CH1OFFSETCAL2_bm  (1<<2)  /* Offset Calibration bit 2 mask. */
-#define DAC_CH1OFFSETCAL2_bp  2  /* Offset Calibration bit 2 position. */
-#define DAC_CH1OFFSETCAL3_bm  (1<<3)  /* Offset Calibration bit 3 mask. */
-#define DAC_CH1OFFSETCAL3_bp  3  /* Offset Calibration bit 3 position. */
-#define DAC_CH1OFFSETCAL4_bm  (1<<4)  /* Offset Calibration bit 4 mask. */
-#define DAC_CH1OFFSETCAL4_bp  4  /* Offset Calibration bit 4 position. */
-#define DAC_CH1OFFSETCAL5_bm  (1<<5)  /* Offset Calibration bit 5 mask. */
-#define DAC_CH1OFFSETCAL5_bp  5  /* Offset Calibration bit 5 position. */
-#define DAC_CH1OFFSETCAL6_bm  (1<<6)  /* Offset Calibration bit 6 mask. */
-#define DAC_CH1OFFSETCAL6_bp  6  /* Offset Calibration bit 6 position. */
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE  Predefined. */
-/* AC_INTMODE  Predefined. */
-
-/* AC_INTLVL  Predefined. */
-/* AC_INTLVL  Predefined. */
-
-/* AC_HSMODE  Predefined. */
-/* AC_HSMODE  Predefined. */
-
-/* AC_HYSMODE  Predefined. */
-/* AC_HYSMODE  Predefined. */
-
-/* AC_ENABLE  Predefined. */
-/* AC_ENABLE  Predefined. */
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS  Predefined. */
-/* AC_MUXPOS  Predefined. */
-
-/* AC_MUXNEG  Predefined. */
-/* AC_MUXNEG  Predefined. */
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC1OUT_bm  0x02  /* Analog Comparator 1 Output Enable bit mask. */
-#define AC_AC1OUT_bp  1  /* Analog Comparator 1 Output Enable bit position. */
-
-#define AC_AC0OUT_bm  0x01  /* Analog Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Analog Comparator 0 Output Enable bit position. */
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Analog Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Analog Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Analog Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Analog Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Analog Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Analog Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Analog Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Analog Comparator 0 Interrupt Flag bit position. */
-
-/* RTC - Real-Time Counter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_gm  0x06  /* SDA Hold Time Enable group mask. */
-#define TWI_SDAHOLD_gp  1  /* SDA Hold Time Enable group position. */
-#define TWI_SDAHOLD0_bm  (1<<1)  /* SDA Hold Time Enable bit 0 mask. */
-#define TWI_SDAHOLD0_bp  1  /* SDA Hold Time Enable bit 0 position. */
-#define TWI_SDAHOLD1_bm  (1<<2)  /* SDA Hold Time Enable bit 1 mask. */
-#define TWI_SDAHOLD1_bp  2  /* SDA Hold Time Enable bit 1 position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-/* USB - USB */
-/* USB_EP.STATUS  bit masks and bit positions */
-#define USB_EP_STALLF_bm  0x80  /* Endpoint Stall Flag bit mask. */
-#define USB_EP_STALLF_bp  7  /* Endpoint Stall Flag bit position. */
-
-#define USB_EP_CRC_bm  0x80  /* CRC Error Flag bit mask. */
-#define USB_EP_CRC_bp  7  /* CRC Error Flag bit position. */
-
-#define USB_EP_UNF_bm  0x40  /* Underflow Enpoint FLag bit mask. */
-#define USB_EP_UNF_bp  6  /* Underflow Enpoint FLag bit position. */
-
-#define USB_EP_OVF_bm  0x40  /* Overflow Enpoint Flag for Output Endpoints bit mask. */
-#define USB_EP_OVF_bp  6  /* Overflow Enpoint Flag for Output Endpoints bit position. */
-
-#define USB_EP_TRNCOMPL0_bm  0x20  /* Transaction Complete 0 Flag bit mask. */
-#define USB_EP_TRNCOMPL0_bp  5  /* Transaction Complete 0 Flag bit position. */
-
-#define USB_EP_TRNCOMPL1_bm  0x10  /* Transaction Complete 1 Flag bit mask. */
-#define USB_EP_TRNCOMPL1_bp  4  /* Transaction Complete 1 Flag bit position. */
-
-#define USB_EP_SETUP_bm  0x10  /* SETUP Transaction Complete Flag bit mask. */
-#define USB_EP_SETUP_bp  4  /* SETUP Transaction Complete Flag bit position. */
-
-#define USB_EP_BANK_bm  0x08  /* Bank Select bit mask. */
-#define USB_EP_BANK_bp  3  /* Bank Select bit position. */
-
-#define USB_EP_BUSNACK1_bm  0x04  /* Data Buffer 1 Not Acknowledge bit mask. */
-#define USB_EP_BUSNACK1_bp  2  /* Data Buffer 1 Not Acknowledge bit position. */
-
-#define USB_EP_BUSNACK0_bm  0x02  /* Data Buffer 0 Not Acknowledge bit mask. */
-#define USB_EP_BUSNACK0_bp  1  /* Data Buffer 0 Not Acknowledge bit position. */
-
-#define USB_EP_TOGGLE_bm  0x01  /* Data Toggle bit mask. */
-#define USB_EP_TOGGLE_bp  0  /* Data Toggle bit position. */
-
-/* USB_EP.CTRL  bit masks and bit positions */
-#define USB_EP_TYPE_gm  0xC0  /* Endpoint Type group mask. */
-#define USB_EP_TYPE_gp  6  /* Endpoint Type group position. */
-#define USB_EP_TYPE0_bm  (1<<6)  /* Endpoint Type bit 0 mask. */
-#define USB_EP_TYPE0_bp  6  /* Endpoint Type bit 0 position. */
-#define USB_EP_TYPE1_bm  (1<<7)  /* Endpoint Type bit 1 mask. */
-#define USB_EP_TYPE1_bp  7  /* Endpoint Type bit 1 position. */
-
-#define USB_EP_MULTIPKT_bm  0x20  /* Multi Packet Transfer Enable bit mask. */
-#define USB_EP_MULTIPKT_bp  5  /* Multi Packet Transfer Enable bit position. */
-
-#define USB_EP_PINGPONG_bm  0x10  /* Ping-Pong Enable bit mask. */
-#define USB_EP_PINGPONG_bp  4  /* Ping-Pong Enable bit position. */
-
-#define USB_EP_INTDSBL_bm  0x08  /* Interrupt Disable bit mask. */
-#define USB_EP_INTDSBL_bp  3  /* Interrupt Disable bit position. */
-
-#define USB_EP_STALL_bm  0x04  /* Data Stall bit mask. */
-#define USB_EP_STALL_bp  2  /* Data Stall bit position. */
-
-#define USB_EP_BUFSIZE_gm  0x07  /* Data Buffer Size group mask. */
-#define USB_EP_BUFSIZE_gp  0  /* Data Buffer Size group position. */
-#define USB_EP_BUFSIZE0_bm  (1<<0)  /* Data Buffer Size bit 0 mask. */
-#define USB_EP_BUFSIZE0_bp  0  /* Data Buffer Size bit 0 position. */
-#define USB_EP_BUFSIZE1_bm  (1<<1)  /* Data Buffer Size bit 1 mask. */
-#define USB_EP_BUFSIZE1_bp  1  /* Data Buffer Size bit 1 position. */
-#define USB_EP_BUFSIZE2_bm  (1<<2)  /* Data Buffer Size bit 2 mask. */
-#define USB_EP_BUFSIZE2_bp  2  /* Data Buffer Size bit 2 position. */
-
-/* USB_EP.CNT  bit masks and bit positions */
-#define USB_EP_ZLP_bm  0x8000  /* Zero Length Packet bit mask. */
-#define USB_EP_ZLP_bp  15  /* Zero Length Packet bit position. */
-
-/* USB.CTRLA  bit masks and bit positions */
-#define USB_ENABLE_bm  0x80  /* USB Enable bit mask. */
-#define USB_ENABLE_bp  7  /* USB Enable bit position. */
-
-#define USB_SPEED_bm  0x40  /* Speed Select bit mask. */
-#define USB_SPEED_bp  6  /* Speed Select bit position. */
-
-#define USB_FIFOEN_bm  0x20  /* USB FIFO Enable bit mask. */
-#define USB_FIFOEN_bp  5  /* USB FIFO Enable bit position. */
-
-#define USB_STFRNUM_bm  0x10  /* Store Frame Number Enable bit mask. */
-#define USB_STFRNUM_bp  4  /* Store Frame Number Enable bit position. */
-
-#define USB_MAXEP_gm  0x0F  /* Maximum Endpoint Addresses group mask. */
-#define USB_MAXEP_gp  0  /* Maximum Endpoint Addresses group position. */
-#define USB_MAXEP0_bm  (1<<0)  /* Maximum Endpoint Addresses bit 0 mask. */
-#define USB_MAXEP0_bp  0  /* Maximum Endpoint Addresses bit 0 position. */
-#define USB_MAXEP1_bm  (1<<1)  /* Maximum Endpoint Addresses bit 1 mask. */
-#define USB_MAXEP1_bp  1  /* Maximum Endpoint Addresses bit 1 position. */
-#define USB_MAXEP2_bm  (1<<2)  /* Maximum Endpoint Addresses bit 2 mask. */
-#define USB_MAXEP2_bp  2  /* Maximum Endpoint Addresses bit 2 position. */
-#define USB_MAXEP3_bm  (1<<3)  /* Maximum Endpoint Addresses bit 3 mask. */
-#define USB_MAXEP3_bp  3  /* Maximum Endpoint Addresses bit 3 position. */
-
-/* USB.CTRLB  bit masks and bit positions */
-#define USB_PULLRST_bm  0x10  /* Pull during Reset bit mask. */
-#define USB_PULLRST_bp  4  /* Pull during Reset bit position. */
-
-#define USB_RWAKEUP_bm  0x04  /* Remote Wake-up bit mask. */
-#define USB_RWAKEUP_bp  2  /* Remote Wake-up bit position. */
-
-#define USB_GNACK_bm  0x02  /* Global NACK bit mask. */
-#define USB_GNACK_bp  1  /* Global NACK bit position. */
-
-#define USB_ATTACH_bm  0x01  /* Attach bit mask. */
-#define USB_ATTACH_bp  0  /* Attach bit position. */
-
-/* USB.STATUS  bit masks and bit positions */
-#define USB_URESUME_bm  0x08  /* Upstream Resume bit mask. */
-#define USB_URESUME_bp  3  /* Upstream Resume bit position. */
-
-#define USB_RESUME_bm  0x04  /* Resume bit mask. */
-#define USB_RESUME_bp  2  /* Resume bit position. */
-
-#define USB_SUSPEND_bm  0x02  /* Bus Suspended bit mask. */
-#define USB_SUSPEND_bp  1  /* Bus Suspended bit position. */
-
-#define USB_BUSRST_bm  0x01  /* Bus Reset bit mask. */
-#define USB_BUSRST_bp  0  /* Bus Reset bit position. */
-
-/* USB.ADDR  bit masks and bit positions */
-#define USB_ADDR_gm  0x7F  /* Device Address group mask. */
-#define USB_ADDR_gp  0  /* Device Address group position. */
-#define USB_ADDR0_bm  (1<<0)  /* Device Address bit 0 mask. */
-#define USB_ADDR0_bp  0  /* Device Address bit 0 position. */
-#define USB_ADDR1_bm  (1<<1)  /* Device Address bit 1 mask. */
-#define USB_ADDR1_bp  1  /* Device Address bit 1 position. */
-#define USB_ADDR2_bm  (1<<2)  /* Device Address bit 2 mask. */
-#define USB_ADDR2_bp  2  /* Device Address bit 2 position. */
-#define USB_ADDR3_bm  (1<<3)  /* Device Address bit 3 mask. */
-#define USB_ADDR3_bp  3  /* Device Address bit 3 position. */
-#define USB_ADDR4_bm  (1<<4)  /* Device Address bit 4 mask. */
-#define USB_ADDR4_bp  4  /* Device Address bit 4 position. */
-#define USB_ADDR5_bm  (1<<5)  /* Device Address bit 5 mask. */
-#define USB_ADDR5_bp  5  /* Device Address bit 5 position. */
-#define USB_ADDR6_bm  (1<<6)  /* Device Address bit 6 mask. */
-#define USB_ADDR6_bp  6  /* Device Address bit 6 position. */
-
-/* USB.FIFOWP  bit masks and bit positions */
-#define USB_FIFOWP_gm  0x1F  /* FIFO Write Pointer group mask. */
-#define USB_FIFOWP_gp  0  /* FIFO Write Pointer group position. */
-#define USB_FIFOWP0_bm  (1<<0)  /* FIFO Write Pointer bit 0 mask. */
-#define USB_FIFOWP0_bp  0  /* FIFO Write Pointer bit 0 position. */
-#define USB_FIFOWP1_bm  (1<<1)  /* FIFO Write Pointer bit 1 mask. */
-#define USB_FIFOWP1_bp  1  /* FIFO Write Pointer bit 1 position. */
-#define USB_FIFOWP2_bm  (1<<2)  /* FIFO Write Pointer bit 2 mask. */
-#define USB_FIFOWP2_bp  2  /* FIFO Write Pointer bit 2 position. */
-#define USB_FIFOWP3_bm  (1<<3)  /* FIFO Write Pointer bit 3 mask. */
-#define USB_FIFOWP3_bp  3  /* FIFO Write Pointer bit 3 position. */
-#define USB_FIFOWP4_bm  (1<<4)  /* FIFO Write Pointer bit 4 mask. */
-#define USB_FIFOWP4_bp  4  /* FIFO Write Pointer bit 4 position. */
-
-/* USB.FIFORP  bit masks and bit positions */
-#define USB_FIFORP_gm  0x1F  /* FIFO Read Pointer group mask. */
-#define USB_FIFORP_gp  0  /* FIFO Read Pointer group position. */
-#define USB_FIFORP0_bm  (1<<0)  /* FIFO Read Pointer bit 0 mask. */
-#define USB_FIFORP0_bp  0  /* FIFO Read Pointer bit 0 position. */
-#define USB_FIFORP1_bm  (1<<1)  /* FIFO Read Pointer bit 1 mask. */
-#define USB_FIFORP1_bp  1  /* FIFO Read Pointer bit 1 position. */
-#define USB_FIFORP2_bm  (1<<2)  /* FIFO Read Pointer bit 2 mask. */
-#define USB_FIFORP2_bp  2  /* FIFO Read Pointer bit 2 position. */
-#define USB_FIFORP3_bm  (1<<3)  /* FIFO Read Pointer bit 3 mask. */
-#define USB_FIFORP3_bp  3  /* FIFO Read Pointer bit 3 position. */
-#define USB_FIFORP4_bm  (1<<4)  /* FIFO Read Pointer bit 4 mask. */
-#define USB_FIFORP4_bp  4  /* FIFO Read Pointer bit 4 position. */
-
-/* USB.INTCTRLA  bit masks and bit positions */
-#define USB_SOFIE_bm  0x80  /* Start Of Frame Interrupt Enable bit mask. */
-#define USB_SOFIE_bp  7  /* Start Of Frame Interrupt Enable bit position. */
-
-#define USB_BUSEVIE_bm  0x40  /* Bus Event Interrupt Enable bit mask. */
-#define USB_BUSEVIE_bp  6  /* Bus Event Interrupt Enable bit position. */
-
-#define USB_BUSERRIE_bm  0x20  /* Bus Error Interrupt Enable bit mask. */
-#define USB_BUSERRIE_bp  5  /* Bus Error Interrupt Enable bit position. */
-
-#define USB_STALLIE_bm  0x10  /* STALL Interrupt Enable bit mask. */
-#define USB_STALLIE_bp  4  /* STALL Interrupt Enable bit position. */
-
-#define USB_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define USB_INTLVL_gp  0  /* Interrupt Level group position. */
-#define USB_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define USB_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define USB_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define USB_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-/* USB.INTCTRLB  bit masks and bit positions */
-#define USB_TRNIE_bm  0x02  /* Transaction Complete Interrupt Enable bit mask. */
-#define USB_TRNIE_bp  1  /* Transaction Complete Interrupt Enable bit position. */
-
-#define USB_SETUPIE_bm  0x01  /* SETUP Transaction Complete Interrupt Enable bit mask. */
-#define USB_SETUPIE_bp  0  /* SETUP Transaction Complete Interrupt Enable bit position. */
-
-/* USB.INTFLAGSACLR  bit masks and bit positions */
-#define USB_SOFIF_bm  0x80  /* Start Of Frame Interrupt Flag bit mask. */
-#define USB_SOFIF_bp  7  /* Start Of Frame Interrupt Flag bit position. */
-
-#define USB_SUSPENDIF_bm  0x40  /* Suspend Interrupt Flag bit mask. */
-#define USB_SUSPENDIF_bp  6  /* Suspend Interrupt Flag bit position. */
-
-#define USB_RESUMEIF_bm  0x20  /* Resume Interrupt Flag bit mask. */
-#define USB_RESUMEIF_bp  5  /* Resume Interrupt Flag bit position. */
-
-#define USB_RSTIF_bm  0x10  /* Reset Interrupt Flag bit mask. */
-#define USB_RSTIF_bp  4  /* Reset Interrupt Flag bit position. */
-
-#define USB_CRCIF_bm  0x08  /* Isochronous CRC Error Interrupt Flag bit mask. */
-#define USB_CRCIF_bp  3  /* Isochronous CRC Error Interrupt Flag bit position. */
-
-#define USB_UNFIF_bm  0x04  /* Underflow Interrupt Flag bit mask. */
-#define USB_UNFIF_bp  2  /* Underflow Interrupt Flag bit position. */
-
-#define USB_OVFIF_bm  0x02  /* Overflow Interrupt Flag bit mask. */
-#define USB_OVFIF_bp  1  /* Overflow Interrupt Flag bit position. */
-
-#define USB_STALLIF_bm  0x01  /* STALL Interrupt Flag bit mask. */
-#define USB_STALLIF_bp  0  /* STALL Interrupt Flag bit position. */
-
-/* USB.INTFLAGSASET  bit masks and bit positions */
-/* USB_SOFIF  Predefined. */
-/* USB_SOFIF  Predefined. */
-
-/* USB_SUSPENDIF  Predefined. */
-/* USB_SUSPENDIF  Predefined. */
-
-/* USB_RESUMEIF  Predefined. */
-/* USB_RESUMEIF  Predefined. */
-
-/* USB_RSTIF  Predefined. */
-/* USB_RSTIF  Predefined. */
-
-/* USB_CRCIF  Predefined. */
-/* USB_CRCIF  Predefined. */
-
-/* USB_UNFIF  Predefined. */
-/* USB_UNFIF  Predefined. */
-
-/* USB_OVFIF  Predefined. */
-/* USB_OVFIF  Predefined. */
-
-/* USB_STALLIF  Predefined. */
-/* USB_STALLIF  Predefined. */
-
-/* USB.INTFLAGSBCLR  bit masks and bit positions */
-#define USB_TRNIF_bm  0x02  /* Transaction Complete Interrupt Flag bit mask. */
-#define USB_TRNIF_bp  1  /* Transaction Complete Interrupt Flag bit position. */
-
-#define USB_SETUPIF_bm  0x01  /* SETUP Transaction Complete Interrupt Flag bit mask. */
-#define USB_SETUPIF_bp  0  /* SETUP Transaction Complete Interrupt Flag bit position. */
-
-/* USB.INTFLAGSBSET  bit masks and bit positions */
-/* USB_TRNIF  Predefined. */
-/* USB_TRNIF  Predefined. */
-
-/* USB_SETUPIF  Predefined. */
-/* USB_SETUPIF  Predefined. */
-
-/* PORT - I/O Port Configuration */
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-/* PORT.REMAP  bit masks and bit positions */
-#define PORT_SPI_bm  0x20  /* SPI bit mask. */
-#define PORT_SPI_bp  5  /* SPI bit position. */
-
-#define PORT_USART0_bm  0x10  /* USART0 bit mask. */
-#define PORT_USART0_bp  4  /* USART0 bit position. */
-
-#define PORT_TC0D_bm  0x08  /* Timer/Counter 0 Output Compare D bit mask. */
-#define PORT_TC0D_bp  3  /* Timer/Counter 0 Output Compare D bit position. */
-
-#define PORT_TC0C_bm  0x04  /* Timer/Counter 0 Output Compare C bit mask. */
-#define PORT_TC0C_bp  2  /* Timer/Counter 0 Output Compare C bit position. */
-
-#define PORT_TC0B_bm  0x02  /* Timer/Counter 0 Output Compare B bit mask. */
-#define PORT_TC0B_bp  1  /* Timer/Counter 0 Output Compare B bit position. */
-
-#define PORT_TC0A_bm  0x01  /* Timer/Counter 0 Output Compare A bit mask. */
-#define PORT_TC0A_bp  0  /* Timer/Counter 0 Output Compare A bit position. */
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN  Predefined. */
-/* PORT_SRLEN  Predefined. */
-
-/* PORT_INVEN  Predefined. */
-/* PORT_INVEN  Predefined. */
-
-/* PORT_OPC  Predefined. */
-/* PORT_OPC  Predefined. */
-
-/* PORT_ISC  Predefined. */
-/* PORT_ISC  Predefined. */
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN  Predefined. */
-/* PORT_SRLEN  Predefined. */
-
-/* PORT_INVEN  Predefined. */
-/* PORT_INVEN  Predefined. */
-
-/* PORT_OPC  Predefined. */
-/* PORT_OPC  Predefined. */
-
-/* PORT_ISC  Predefined. */
-/* PORT_ISC  Predefined. */
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN  Predefined. */
-/* PORT_SRLEN  Predefined. */
-
-/* PORT_INVEN  Predefined. */
-/* PORT_INVEN  Predefined. */
-
-/* PORT_OPC  Predefined. */
-/* PORT_OPC  Predefined. */
-
-/* PORT_ISC  Predefined. */
-/* PORT_ISC  Predefined. */
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN  Predefined. */
-/* PORT_SRLEN  Predefined. */
-
-/* PORT_INVEN  Predefined. */
-/* PORT_INVEN  Predefined. */
-
-/* PORT_OPC  Predefined. */
-/* PORT_OPC  Predefined. */
-
-/* PORT_ISC  Predefined. */
-/* PORT_ISC  Predefined. */
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN  Predefined. */
-/* PORT_SRLEN  Predefined. */
-
-/* PORT_INVEN  Predefined. */
-/* PORT_INVEN  Predefined. */
-
-/* PORT_OPC  Predefined. */
-/* PORT_OPC  Predefined. */
-
-/* PORT_ISC  Predefined. */
-/* PORT_ISC  Predefined. */
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN  Predefined. */
-/* PORT_SRLEN  Predefined. */
-
-/* PORT_INVEN  Predefined. */
-/* PORT_INVEN  Predefined. */
-
-/* PORT_OPC  Predefined. */
-/* PORT_OPC  Predefined. */
-
-/* PORT_ISC  Predefined. */
-/* PORT_ISC  Predefined. */
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN  Predefined. */
-/* PORT_SRLEN  Predefined. */
-
-/* PORT_INVEN  Predefined. */
-/* PORT_INVEN  Predefined. */
-
-/* PORT_OPC  Predefined. */
-/* PORT_OPC  Predefined. */
-
-/* PORT_ISC  Predefined. */
-/* PORT_ISC  Predefined. */
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_BYTEM_gm  0x03  /* Byte Mode group mask. */
-#define TC0_BYTEM_gp  0  /* Byte Mode group position. */
-#define TC0_BYTEM0_bm  (1<<0)  /* Byte Mode bit 0 mask. */
-#define TC0_BYTEM0_bp  0  /* Byte Mode bit 0 position. */
-#define TC0_BYTEM1_bm  (1<<1)  /* Byte Mode bit 1 mask. */
-#define TC0_BYTEM1_bp  1  /* Byte Mode bit 1 position. */
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD  Predefined. */
-/* TC0_CMD  Predefined. */
-
-/* TC0_LUPD  Predefined. */
-/* TC0_LUPD  Predefined. */
-
-/* TC0_DIR  Predefined. */
-/* TC0_DIR  Predefined. */
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV  Predefined. */
-/* TC0_CCDBV  Predefined. */
-
-/* TC0_CCCBV  Predefined. */
-/* TC0_CCCBV  Predefined. */
-
-/* TC0_CCBBV  Predefined. */
-/* TC0_CCBBV  Predefined. */
-
-/* TC0_CCABV  Predefined. */
-/* TC0_CCABV  Predefined. */
-
-/* TC0_PERBV  Predefined. */
-/* TC0_PERBV  Predefined. */
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD  Predefined. */
-/* TC1_CMD  Predefined. */
-
-/* TC1_LUPD  Predefined. */
-/* TC1_LUPD  Predefined. */
-
-/* TC1_DIR  Predefined. */
-/* TC1_DIR  Predefined. */
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV  Predefined. */
-/* TC1_CCBBV  Predefined. */
-
-/* TC1_CCABV  Predefined. */
-/* TC1_CCABV  Predefined. */
-
-/* TC1_PERBV  Predefined. */
-/* TC1_PERBV  Predefined. */
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-/* TC2 - 16-bit Timer/Counter type 2 */
-/* TC2.CTRLA  bit masks and bit positions */
-#define TC2_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC2_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC2_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC2_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC2_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC2_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC2_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC2_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC2_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC2_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-/* TC2.CTRLB  bit masks and bit positions */
-#define TC2_HCMPDEN_bm  0x80  /* High Byte Compare D Enable bit mask. */
-#define TC2_HCMPDEN_bp  7  /* High Byte Compare D Enable bit position. */
-
-#define TC2_HCMPCEN_bm  0x40  /* High Byte Compare C Enable bit mask. */
-#define TC2_HCMPCEN_bp  6  /* High Byte Compare C Enable bit position. */
-
-#define TC2_HCMPBEN_bm  0x20  /* High Byte Compare B Enable bit mask. */
-#define TC2_HCMPBEN_bp  5  /* High Byte Compare B Enable bit position. */
-
-#define TC2_HCMPAEN_bm  0x10  /* High Byte Compare A Enable bit mask. */
-#define TC2_HCMPAEN_bp  4  /* High Byte Compare A Enable bit position. */
-
-#define TC2_LCMPDEN_bm  0x08  /* Low Byte Compare D Enable bit mask. */
-#define TC2_LCMPDEN_bp  3  /* Low Byte Compare D Enable bit position. */
-
-#define TC2_LCMPCEN_bm  0x04  /* Low Byte Compare C Enable bit mask. */
-#define TC2_LCMPCEN_bp  2  /* Low Byte Compare C Enable bit position. */
-
-#define TC2_LCMPBEN_bm  0x02  /* Low Byte Compare B Enable bit mask. */
-#define TC2_LCMPBEN_bp  1  /* Low Byte Compare B Enable bit position. */
-
-#define TC2_LCMPAEN_bm  0x01  /* Low Byte Compare A Enable bit mask. */
-#define TC2_LCMPAEN_bp  0  /* Low Byte Compare A Enable bit position. */
-
-/* TC2.CTRLC  bit masks and bit positions */
-#define TC2_HCMPD_bm  0x80  /* High Byte Compare D Output Value bit mask. */
-#define TC2_HCMPD_bp  7  /* High Byte Compare D Output Value bit position. */
-
-#define TC2_HCMPC_bm  0x40  /* High Byte Compare C Output Value bit mask. */
-#define TC2_HCMPC_bp  6  /* High Byte Compare C Output Value bit position. */
-
-#define TC2_HCMPB_bm  0x20  /* High Byte Compare B Output Value bit mask. */
-#define TC2_HCMPB_bp  5  /* High Byte Compare B Output Value bit position. */
-
-#define TC2_HCMPA_bm  0x10  /* High Byte Compare A Output Value bit mask. */
-#define TC2_HCMPA_bp  4  /* High Byte Compare A Output Value bit position. */
-
-#define TC2_LCMPD_bm  0x08  /* Low Byte Compare D Output Value bit mask. */
-#define TC2_LCMPD_bp  3  /* Low Byte Compare D Output Value bit position. */
-
-#define TC2_LCMPC_bm  0x04  /* Low Byte Compare C Output Value bit mask. */
-#define TC2_LCMPC_bp  2  /* Low Byte Compare C Output Value bit position. */
-
-#define TC2_LCMPB_bm  0x02  /* Low Byte Compare B Output Value bit mask. */
-#define TC2_LCMPB_bp  1  /* Low Byte Compare B Output Value bit position. */
-
-#define TC2_LCMPA_bm  0x01  /* Low Byte Compare A Output Value bit mask. */
-#define TC2_LCMPA_bp  0  /* Low Byte Compare A Output Value bit position. */
-
-/* TC2.CTRLE  bit masks and bit positions */
-#define TC2_BYTEM_gm  0x03  /* Byte Mode group mask. */
-#define TC2_BYTEM_gp  0  /* Byte Mode group position. */
-#define TC2_BYTEM0_bm  (1<<0)  /* Byte Mode bit 0 mask. */
-#define TC2_BYTEM0_bp  0  /* Byte Mode bit 0 position. */
-#define TC2_BYTEM1_bm  (1<<1)  /* Byte Mode bit 1 mask. */
-#define TC2_BYTEM1_bp  1  /* Byte Mode bit 1 position. */
-
-/* TC2.INTCTRLA  bit masks and bit positions */
-#define TC2_HUNFINTLVL_gm  0x0C  /* High Byte Underflow Interrupt Level group mask. */
-#define TC2_HUNFINTLVL_gp  2  /* High Byte Underflow Interrupt Level group position. */
-#define TC2_HUNFINTLVL0_bm  (1<<2)  /* High Byte Underflow Interrupt Level bit 0 mask. */
-#define TC2_HUNFINTLVL0_bp  2  /* High Byte Underflow Interrupt Level bit 0 position. */
-#define TC2_HUNFINTLVL1_bm  (1<<3)  /* High Byte Underflow Interrupt Level bit 1 mask. */
-#define TC2_HUNFINTLVL1_bp  3  /* High Byte Underflow Interrupt Level bit 1 position. */
-
-#define TC2_LUNFINTLVL_gm  0x03  /* Low Byte Underflow interrupt level group mask. */
-#define TC2_LUNFINTLVL_gp  0  /* Low Byte Underflow interrupt level group position. */
-#define TC2_LUNFINTLVL0_bm  (1<<0)  /* Low Byte Underflow interrupt level bit 0 mask. */
-#define TC2_LUNFINTLVL0_bp  0  /* Low Byte Underflow interrupt level bit 0 position. */
-#define TC2_LUNFINTLVL1_bm  (1<<1)  /* Low Byte Underflow interrupt level bit 1 mask. */
-#define TC2_LUNFINTLVL1_bp  1  /* Low Byte Underflow interrupt level bit 1 position. */
-
-/* TC2.INTCTRLB  bit masks and bit positions */
-#define TC2_LCMPDINTLVL_gm  0xC0  /* Low Byte Compare D Interrupt Level group mask. */
-#define TC2_LCMPDINTLVL_gp  6  /* Low Byte Compare D Interrupt Level group position. */
-#define TC2_LCMPDINTLVL0_bm  (1<<6)  /* Low Byte Compare D Interrupt Level bit 0 mask. */
-#define TC2_LCMPDINTLVL0_bp  6  /* Low Byte Compare D Interrupt Level bit 0 position. */
-#define TC2_LCMPDINTLVL1_bm  (1<<7)  /* Low Byte Compare D Interrupt Level bit 1 mask. */
-#define TC2_LCMPDINTLVL1_bp  7  /* Low Byte Compare D Interrupt Level bit 1 position. */
-
-#define TC2_LCMPCINTLVL_gm  0x30  /* Low Byte Compare C Interrupt Level group mask. */
-#define TC2_LCMPCINTLVL_gp  4  /* Low Byte Compare C Interrupt Level group position. */
-#define TC2_LCMPCINTLVL0_bm  (1<<4)  /* Low Byte Compare C Interrupt Level bit 0 mask. */
-#define TC2_LCMPCINTLVL0_bp  4  /* Low Byte Compare C Interrupt Level bit 0 position. */
-#define TC2_LCMPCINTLVL1_bm  (1<<5)  /* Low Byte Compare C Interrupt Level bit 1 mask. */
-#define TC2_LCMPCINTLVL1_bp  5  /* Low Byte Compare C Interrupt Level bit 1 position. */
-
-#define TC2_LCMPBINTLVL_gm  0x0C  /* Low Byte Compare B Interrupt Level group mask. */
-#define TC2_LCMPBINTLVL_gp  2  /* Low Byte Compare B Interrupt Level group position. */
-#define TC2_LCMPBINTLVL0_bm  (1<<2)  /* Low Byte Compare B Interrupt Level bit 0 mask. */
-#define TC2_LCMPBINTLVL0_bp  2  /* Low Byte Compare B Interrupt Level bit 0 position. */
-#define TC2_LCMPBINTLVL1_bm  (1<<3)  /* Low Byte Compare B Interrupt Level bit 1 mask. */
-#define TC2_LCMPBINTLVL1_bp  3  /* Low Byte Compare B Interrupt Level bit 1 position. */
-
-#define TC2_LCMPAINTLVL_gm  0x03  /* Low Byte Compare A Interrupt Level group mask. */
-#define TC2_LCMPAINTLVL_gp  0  /* Low Byte Compare A Interrupt Level group position. */
-#define TC2_LCMPAINTLVL0_bm  (1<<0)  /* Low Byte Compare A Interrupt Level bit 0 mask. */
-#define TC2_LCMPAINTLVL0_bp  0  /* Low Byte Compare A Interrupt Level bit 0 position. */
-#define TC2_LCMPAINTLVL1_bm  (1<<1)  /* Low Byte Compare A Interrupt Level bit 1 mask. */
-#define TC2_LCMPAINTLVL1_bp  1  /* Low Byte Compare A Interrupt Level bit 1 position. */
-
-/* TC2.CTRLF  bit masks and bit positions */
-#define TC2_CMD_gm  0x0C  /* Command group mask. */
-#define TC2_CMD_gp  2  /* Command group position. */
-#define TC2_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC2_CMD0_bp  2  /* Command bit 0 position. */
-#define TC2_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC2_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC2_CMDEN_gm  0x03  /* Command Enable group mask. */
-#define TC2_CMDEN_gp  0  /* Command Enable group position. */
-#define TC2_CMDEN0_bm  (1<<0)  /* Command Enable bit 0 mask. */
-#define TC2_CMDEN0_bp  0  /* Command Enable bit 0 position. */
-#define TC2_CMDEN1_bm  (1<<1)  /* Command Enable bit 1 mask. */
-#define TC2_CMDEN1_bp  1  /* Command Enable bit 1 position. */
-
-/* TC2.INTFLAGS  bit masks and bit positions */
-#define TC2_LCMPDIF_bm  0x80  /* Low Byte Compare D Interrupt Flag bit mask. */
-#define TC2_LCMPDIF_bp  7  /* Low Byte Compare D Interrupt Flag bit position. */
-
-#define TC2_LCMPCIF_bm  0x40  /* Low Byte Compare C Interrupt Flag bit mask. */
-#define TC2_LCMPCIF_bp  6  /* Low Byte Compare C Interrupt Flag bit position. */
-
-#define TC2_LCMPBIF_bm  0x20  /* Low Byte Compare B Interrupt Flag bit mask. */
-#define TC2_LCMPBIF_bp  5  /* Low Byte Compare B Interrupt Flag bit position. */
-
-#define TC2_LCMPAIF_bm  0x10  /* Low Byte Compare A Interrupt Flag bit mask. */
-#define TC2_LCMPAIF_bp  4  /* Low Byte Compare A Interrupt Flag bit position. */
-
-#define TC2_HUNFIF_bm  0x02  /* High Byte Underflow Interrupt Flag bit mask. */
-#define TC2_HUNFIF_bp  1  /* High Byte Underflow Interrupt Flag bit position. */
-
-#define TC2_LUNFIF_bm  0x01  /* Low Byte Underflow Interrupt Flag bit mask. */
-#define TC2_LUNFIF_bp  0  /* Low Byte Underflow Interrupt Flag bit position. */
-
-/* AWEX - Timer/Counter Advanced Waveform Extension */
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-/* AWEX.STATUSSET  bit masks and bit positions */
-/* AWEX_FDF  Predefined. */
-/* AWEX_FDF  Predefined. */
-
-/* AWEX_DTHSBUFV  Predefined. */
-/* AWEX_DTHSBUFV  Predefined. */
-
-/* AWEX_DTLSBUFV  Predefined. */
-/* AWEX_DTLSBUFV  Predefined. */
-
-/* HIRES - Timer/Counter High-Resolution Extension */
-/* HIRES.CTRLA  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL  Predefined. */
-/* USART_BSEL  Predefined. */
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-/* FUSE - Fuses and Lockbits */
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_JTAGUSERID_gm  0xFF  /* JTAG User ID group mask. */
-#define NVM_FUSES_JTAGUSERID_gp  0  /* JTAG User ID group position. */
-#define NVM_FUSES_JTAGUSERID0_bm  (1<<0)  /* JTAG User ID bit 0 mask. */
-#define NVM_FUSES_JTAGUSERID0_bp  0  /* JTAG User ID bit 0 position. */
-#define NVM_FUSES_JTAGUSERID1_bm  (1<<1)  /* JTAG User ID bit 1 mask. */
-#define NVM_FUSES_JTAGUSERID1_bp  1  /* JTAG User ID bit 1 position. */
-#define NVM_FUSES_JTAGUSERID2_bm  (1<<2)  /* JTAG User ID bit 2 mask. */
-#define NVM_FUSES_JTAGUSERID2_bp  2  /* JTAG User ID bit 2 position. */
-#define NVM_FUSES_JTAGUSERID3_bm  (1<<3)  /* JTAG User ID bit 3 mask. */
-#define NVM_FUSES_JTAGUSERID3_bp  3  /* JTAG User ID bit 3 position. */
-#define NVM_FUSES_JTAGUSERID4_bm  (1<<4)  /* JTAG User ID bit 4 mask. */
-#define NVM_FUSES_JTAGUSERID4_bp  4  /* JTAG User ID bit 4 position. */
-#define NVM_FUSES_JTAGUSERID5_bm  (1<<5)  /* JTAG User ID bit 5 mask. */
-#define NVM_FUSES_JTAGUSERID5_bp  5  /* JTAG User ID bit 5 position. */
-#define NVM_FUSES_JTAGUSERID6_bm  (1<<6)  /* JTAG User ID bit 6 mask. */
-#define NVM_FUSES_JTAGUSERID6_bp  6  /* JTAG User ID bit 6 position. */
-#define NVM_FUSES_JTAGUSERID7_bm  (1<<7)  /* JTAG User ID bit 7 mask. */
-#define NVM_FUSES_JTAGUSERID7_bp  7  /* JTAG User ID bit 7 position. */
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_TOSCSEL_bm  0x20  /* Timer Oscillator pin location bit mask. */
-#define NVM_FUSES_TOSCSEL_bp  5  /* Timer Oscillator pin location bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_RSTDISBL_bm  0x10  /* External Reset Disable bit mask. */
-#define NVM_FUSES_RSTDISBL_bp  4  /* External Reset Disable bit position. */
-
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-#define NVM_FUSES_JTAGEN_bm  0x01  /* JTAG Interface Enable bit mask. */
-#define NVM_FUSES_JTAGEN_bp  0  /* JTAG Interface Enable bit position. */
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-/* LOCKBIT - Fuses and Lockbits */
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_OSCF_vect_num  1
-#define OSC_OSCF_vect      _VECTOR(1)  /* Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-
-/* TCC2 interrupt vectors */
-#define TCC2_LUNF_vect_num  14
-#define TCC2_LUNF_vect      _VECTOR(14)  /* Low Byte Underflow Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-
-/* TCC2 interrupt vectors */
-#define TCC2_HUNF_vect_num  15
-#define TCC2_HUNF_vect      _VECTOR(15)  /* High Byte Underflow Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-
-/* TCC2 interrupt vectors */
-#define TCC2_LCMPA_vect_num  16
-#define TCC2_LCMPA_vect      _VECTOR(16)  /* Low Byte Compare A Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-
-/* TCC2 interrupt vectors */
-#define TCC2_LCMPB_vect_num  17
-#define TCC2_LCMPB_vect      _VECTOR(17)  /* Low Byte Compare B Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-
-/* TCC2 interrupt vectors */
-#define TCC2_LCMPC_vect_num  18
-#define TCC2_LCMPC_vect      _VECTOR(18)  /* Low Byte Compare C Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC2 interrupt vectors */
-#define TCC2_LCMPD_vect_num  19
-#define TCC2_LCMPD_vect      _VECTOR(19)  /* Low Byte Compare D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* ACB interrupt vectors */
-#define ACB_AC0_vect_num  36
-#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
-#define ACB_AC1_vect_num  37
-#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
-#define ACB_ACW_vect_num  38
-#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
-
-/* ADCB interrupt vectors */
-#define ADCB_CH0_vect_num  39
-#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
-#define ADCB_CH1_vect_num  40
-#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
-#define ADCB_CH2_vect_num  41
-#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
-#define ADCB_CH3_vect_num  42
-#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-
-/* TCE2 interrupt vectors */
-#define TCE2_LUNF_vect_num  47
-#define TCE2_LUNF_vect      _VECTOR(47)  /* Low Byte Underflow Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-
-/* TCE2 interrupt vectors */
-#define TCE2_HUNF_vect_num  48
-#define TCE2_HUNF_vect      _VECTOR(48)  /* High Byte Underflow Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-
-/* TCE2 interrupt vectors */
-#define TCE2_LCMPA_vect_num  49
-#define TCE2_LCMPA_vect      _VECTOR(49)  /* Low Byte Compare A Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-
-/* TCE2 interrupt vectors */
-#define TCE2_LCMPB_vect_num  50
-#define TCE2_LCMPB_vect      _VECTOR(50)  /* Low Byte Compare B Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-
-/* TCE2 interrupt vectors */
-#define TCE2_LCMPC_vect_num  51
-#define TCE2_LCMPC_vect      _VECTOR(51)  /* Low Byte Compare C Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE2 interrupt vectors */
-#define TCE2_LCMPD_vect_num  52
-#define TCE2_LCMPD_vect      _VECTOR(52)  /* Low Byte Compare D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* SPIE interrupt vectors */
-#define SPIE_INT_vect_num  57
-#define SPIE_INT_vect      _VECTOR(57)  /* SPI Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* USARTE1 interrupt vectors */
-#define USARTE1_RXC_vect_num  61
-#define USARTE1_RXC_vect      _VECTOR(61)  /* Reception Complete Interrupt */
-#define USARTE1_DRE_vect_num  62
-#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
-#define USARTE1_TXC_vect_num  63
-#define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-
-/* TCD2 interrupt vectors */
-#define TCD2_LUNF_vect_num  77
-#define TCD2_LUNF_vect      _VECTOR(77)  /* Low Byte Underflow Interrupt */
-
-/* TCD0 interrupt vectors */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-
-/* TCD2 interrupt vectors */
-#define TCD2_HUNF_vect_num  78
-#define TCD2_HUNF_vect      _VECTOR(78)  /* High Byte Underflow Interrupt */
-
-/* TCD0 interrupt vectors */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-
-/* TCD2 interrupt vectors */
-#define TCD2_LCMPA_vect_num  79
-#define TCD2_LCMPA_vect      _VECTOR(79)  /* Low Byte Compare A Interrupt */
-
-/* TCD0 interrupt vectors */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-
-/* TCD2 interrupt vectors */
-#define TCD2_LCMPB_vect_num  80
-#define TCD2_LCMPB_vect      _VECTOR(80)  /* Low Byte Compare B Interrupt */
-
-/* TCD0 interrupt vectors */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-
-/* TCD2 interrupt vectors */
-#define TCD2_LCMPC_vect_num  81
-#define TCD2_LCMPC_vect      _VECTOR(81)  /* Low Byte Compare C Interrupt */
-
-/* TCD0 interrupt vectors */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD2 interrupt vectors */
-#define TCD2_LCMPD_vect_num  82
-#define TCD2_LCMPD_vect      _VECTOR(82)  /* Low Byte Compare D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-
-/* TCF2 interrupt vectors */
-#define TCF2_LUNF_vect_num  108
-#define TCF2_LUNF_vect      _VECTOR(108)  /* Low Byte Underflow Interrupt */
-
-/* TCF0 interrupt vectors */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-
-/* TCF2 interrupt vectors */
-#define TCF2_HUNF_vect_num  109
-#define TCF2_HUNF_vect      _VECTOR(109)  /* High Byte Underflow Interrupt */
-
-/* TCF0 interrupt vectors */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-
-/* TCF2 interrupt vectors */
-#define TCF2_LCMPA_vect_num  110
-#define TCF2_LCMPA_vect      _VECTOR(110)  /* Low Byte Compare A Interrupt */
-
-/* TCF0 interrupt vectors */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-
-/* TCF2 interrupt vectors */
-#define TCF2_LCMPB_vect_num  111
-#define TCF2_LCMPB_vect      _VECTOR(111)  /* Low Byte Compare B Interrupt */
-
-/* TCF0 interrupt vectors */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-
-/* TCF2 interrupt vectors */
-#define TCF2_LCMPC_vect_num  112
-#define TCF2_LCMPC_vect      _VECTOR(112)  /* Low Byte Compare C Interrupt */
-
-/* TCF0 interrupt vectors */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-/* TCF2 interrupt vectors */
-#define TCF2_LCMPD_vect_num  113
-#define TCF2_LCMPD_vect      _VECTOR(113)  /* Low Byte Compare D Interrupt */
-
-/* USARTF0 interrupt vectors */
-#define USARTF0_RXC_vect_num  119
-#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
-#define USARTF0_DRE_vect_num  120
-#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
-#define USARTF0_TXC_vect_num  121
-#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
-
-/* USB interrupt vectors */
-#define USB_BUSEVENT_vect_num  125
-#define USB_BUSEVENT_vect      _VECTOR(125)  /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
-#define USB_TRNCOMPL_vect_num  126
-#define USB_TRNCOMPL_vect      _VECTOR(126)  /* Transaction complete interrupt */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (139264)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (131072)
-#define APP_SECTION_PAGE_SIZE (512)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x1E000)
-#define APPTABLE_SECTION_SIZE      (8192)
-#define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x20000)
-#define BOOT_SECTION_SIZE      (8192)
-#define BOOT_SECTION_PAGE_SIZE (512)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (16384)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (2048)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (8192)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (2048)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define FUSES_START     (0x0000)
-#define FUSES_SIZE      (6)
-#define FUSES_PAGE_SIZE (0)
-#define FUSES_END       (FUSES_START + FUSES_SIZE - 1)
-
-#define LOCKBITS_START     (0x0000)
-#define LOCKBITS_SIZE      (1)
-#define LOCKBITS_PAGE_SIZE (0)
-#define LOCKBITS_END       (LOCKBITS_START + LOCKBITS_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (512)
-#define USER_SIGNATURES_PAGE_SIZE (512)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (512)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHSTART   PROGMEM_START
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE 512
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0  (unsigned char)~_BV(0)  /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1  (unsigned char)~_BV(1)  /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2  (unsigned char)~_BV(2)  /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3  (unsigned char)~_BV(3)  /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4  (unsigned char)~_BV(4)  /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5  (unsigned char)~_BV(5)  /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6  (unsigned char)~_BV(6)  /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7  (unsigned char)~_BV(7)  /* JTAG User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_TOSCSEL  (unsigned char)~_BV(5)  /* Timer Oscillator pin location */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_JTAGEN  (unsigned char)~_BV(0)  /* JTAG Interface Enable */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(4)  /* External Reset Disable */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x42
-
-/* ========== Power Reduction Condition Definitions ========== */
-
-/* PR.PRGEN */
-#define __AVR_HAVE_PRGEN	(PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm)
-#define __AVR_HAVE_PRGEN_USB
-#define __AVR_HAVE_PRGEN_AES
-#define __AVR_HAVE_PRGEN_EBI
-#define __AVR_HAVE_PRGEN_RTC
-#define __AVR_HAVE_PRGEN_EVSYS
-#define __AVR_HAVE_PRGEN_DMA
-
-/* PR.PRPA */
-#define __AVR_HAVE_PRPA	(PR_DAC_bm|PR_ADC_bm|PR_AC_bm)
-#define __AVR_HAVE_PRPA_DAC
-#define __AVR_HAVE_PRPA_ADC
-#define __AVR_HAVE_PRPA_AC
-
-/* PR.PRPB */
-#define __AVR_HAVE_PRPB	(PR_DAC_bm|PR_ADC_bm|PR_AC_bm)
-#define __AVR_HAVE_PRPB_DAC
-#define __AVR_HAVE_PRPB_ADC
-#define __AVR_HAVE_PRPB_AC
-
-/* PR.PRPC */
-#define __AVR_HAVE_PRPC	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
-#define __AVR_HAVE_PRPC_TWI
-#define __AVR_HAVE_PRPC_USART1
-#define __AVR_HAVE_PRPC_USART0
-#define __AVR_HAVE_PRPC_SPI
-#define __AVR_HAVE_PRPC_HIRES
-#define __AVR_HAVE_PRPC_TC1
-#define __AVR_HAVE_PRPC_TC0
-
-/* PR.PRPD */
-#define __AVR_HAVE_PRPD	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
-#define __AVR_HAVE_PRPD_TWI
-#define __AVR_HAVE_PRPD_USART1
-#define __AVR_HAVE_PRPD_USART0
-#define __AVR_HAVE_PRPD_SPI
-#define __AVR_HAVE_PRPD_HIRES
-#define __AVR_HAVE_PRPD_TC1
-#define __AVR_HAVE_PRPD_TC0
-
-/* PR.PRPE */
-#define __AVR_HAVE_PRPE	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
-#define __AVR_HAVE_PRPE_TWI
-#define __AVR_HAVE_PRPE_USART1
-#define __AVR_HAVE_PRPE_USART0
-#define __AVR_HAVE_PRPE_SPI
-#define __AVR_HAVE_PRPE_HIRES
-#define __AVR_HAVE_PRPE_TC1
-#define __AVR_HAVE_PRPE_TC0
-
-/* PR.PRPF */
-#define __AVR_HAVE_PRPF	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
-#define __AVR_HAVE_PRPF_TWI
-#define __AVR_HAVE_PRPF_USART1
-#define __AVR_HAVE_PRPF_USART0
-#define __AVR_HAVE_PRPF_SPI
-#define __AVR_HAVE_PRPF_HIRES
-#define __AVR_HAVE_PRPF_TC1
-#define __AVR_HAVE_PRPF_TC0
-
-
-#endif /* #ifdef _AVR_ATXMEGA128A3U_H_INCLUDED */
-
+/*****************************************************************************
+ *
+ * Copyright (C) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ * All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ****************************************************************************/
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iox128a3u.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+#ifndef _AVR_ATXMEGA128A3U_H_INCLUDED
+#define _AVR_ATXMEGA128A3U_H_INCLUDED
+
+/* Ungrouped common registers */
+#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
+#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
+#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
+#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
+#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
+#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
+#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
+#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
+#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
+#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
+#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
+#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
+#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
+#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
+#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
+#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
+
+/* Deprecated */
+#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
+#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
+#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
+#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
+#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
+#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
+#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
+#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
+#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
+#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
+#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
+#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
+#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
+#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
+#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
+#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
+
+#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
+#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
+#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
+#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
+#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
+#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
+#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
+#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
+#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
+
+/* C Language Only */
+#if !defined (__ASSEMBLER__)
+
+#include <stdint.h>
+
+typedef volatile uint8_t register8_t;
+typedef volatile uint16_t register16_t;
+typedef volatile uint32_t register32_t;
+
+
+#ifdef _WORDREGISTER
+#undef _WORDREGISTER
+#endif
+#define _WORDREGISTER(regname)   \
+    __extension__ union \
+    { \
+        register16_t regname; \
+        struct \
+        { \
+            register8_t regname ## L; \
+            register8_t regname ## H; \
+        }; \
+    }
+
+#ifdef _DWORDREGISTER
+#undef _DWORDREGISTER
+#endif
+#define _DWORDREGISTER(regname)  \
+    __extension__ union \
+    { \
+        register32_t regname; \
+        struct \
+        { \
+            register8_t regname ## 0; \
+            register8_t regname ## 1; \
+            register8_t regname ## 2; \
+            register8_t regname ## 3; \
+        }; \
+    }
+
+
+/*
+==========================================================================
+IO Module Structures
+==========================================================================
+*/
+
+
+/*
+--------------------------------------------------------------------------
+AC - Analog Comparator
+--------------------------------------------------------------------------
+*/
+
+/* Analog Comparator */
+typedef struct AC_struct
+{
+    register8_t AC0CTRL;  /* Analog Comparator 0 Control */
+    register8_t AC1CTRL;  /* Analog Comparator 1 Control */
+    register8_t AC0MUXCTRL;  /* Analog Comparator 0 MUX Control */
+    register8_t AC1MUXCTRL;  /* Analog Comparator 1 MUX Control */
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t WINCTRL;  /* Window Mode Control */
+    register8_t STATUS;  /* Status */
+    register8_t CURRCTRL;  /* Current Source Control */
+    register8_t CURRCALIB;  /* Current Source Calibration */
+} AC_t;
+
+/* Hysteresis mode selection */
+typedef enum AC_HYSMODE_enum
+{
+    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
+    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
+    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
+} AC_HYSMODE_t;
+
+/* Interrupt level */
+typedef enum AC_INTLVL_enum
+{
+    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
+    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
+    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
+    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
+} AC_INTLVL_t;
+
+/* Interrupt mode */
+typedef enum AC_INTMODE_enum
+{
+    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
+    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
+    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
+} AC_INTMODE_t;
+
+/* Negative input multiplexer selection */
+typedef enum AC_MUXNEG_enum
+{
+    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
+    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
+    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
+    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
+    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
+    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
+    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
+    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
+} AC_MUXNEG_t;
+
+/* Positive input multiplexer selection */
+typedef enum AC_MUXPOS_enum
+{
+    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
+    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
+    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
+    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
+    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
+    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
+    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
+    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
+} AC_MUXPOS_t;
+
+/* Window interrupt level */
+typedef enum AC_WINTLVL_enum
+{
+    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
+    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
+    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
+    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
+} AC_WINTLVL_t;
+
+/* Windows interrupt mode */
+typedef enum AC_WINTMODE_enum
+{
+    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
+    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
+    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
+    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
+} AC_WINTMODE_t;
+
+/* Window mode state */
+typedef enum AC_WSTATE_enum
+{
+    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
+    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
+    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
+} AC_WSTATE_t;
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* ADC Channel */
+typedef struct ADC_CH_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t MUXCTRL;  /* MUX Control */
+    register8_t INTCTRL;  /* Channel Interrupt Control Register */
+    register8_t INTFLAGS;  /* Interrupt Flags */
+    _WORDREGISTER(RES);  /* Channel Result */
+    register8_t SCAN;  /* Input Channel Scan */
+    register8_t reserved_0x07;
+} ADC_CH_t;
+
+
+/* Analog-to-Digital Converter */
+typedef struct ADC_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t REFCTRL;  /* Reference Control */
+    register8_t EVCTRL;  /* Event Control */
+    register8_t PRESCALER;  /* Clock Prescaler */
+    register8_t reserved_0x05;
+    register8_t INTFLAGS;  /* Interrupt Flags */
+    register8_t TEMP;  /* Temporary Register */
+    register8_t reserved_0x08;
+    register8_t reserved_0x09;
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+    _WORDREGISTER(CAL);  /* Calibration Value */
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
+    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
+    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
+    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
+    _WORDREGISTER(CMP);  /* Compare Value */
+    register8_t reserved_0x1A;
+    register8_t reserved_0x1B;
+    register8_t reserved_0x1C;
+    register8_t reserved_0x1D;
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    ADC_CH_t CH0;  /* ADC Channel 0 */
+    ADC_CH_t CH1;  /* ADC Channel 1 */
+    ADC_CH_t CH2;  /* ADC Channel 2 */
+    ADC_CH_t CH3;  /* ADC Channel 3 */
+} ADC_t;
+
+/* Gain factor */
+typedef enum ADC_CH_GAIN_enum
+{
+    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
+    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
+    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
+    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
+    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
+    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
+    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
+    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */
+} ADC_CH_GAIN_t;
+
+/* Input mode */
+typedef enum ADC_CH_INPUTMODE_enum
+{
+    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
+    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
+    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
+    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
+} ADC_CH_INPUTMODE_t;
+
+/* Interrupt level */
+typedef enum ADC_CH_INTLVL_enum
+{
+    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
+    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
+    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
+    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
+} ADC_CH_INTLVL_t;
+
+/* Interrupt mode */
+typedef enum ADC_CH_INTMODE_enum
+{
+    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
+    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
+    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
+} ADC_CH_INTMODE_t;
+
+/* Internal input multiplexer selections */
+typedef enum ADC_CH_MUXINT_enum
+{
+    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
+    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
+    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
+    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
+} ADC_CH_MUXINT_t;
+
+/* Negative input multiplexer selection */
+typedef enum ADC_CH_MUXNEG_enum
+{
+    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN4_gc = (0x00<<0),  /* Input pin 4 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN5_gc = (0x01<<0),  /* Input pin 5 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN6_gc = (0x02<<0),  /* Input pin 6 (Input Mode = 3) */
+    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 (Input Mode = 2) */
+    ADC_CH_MUXNEG_PIN7_gc = (0x03<<0),  /* Input pin 7 (Input Mode = 3) */
+    ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0),  /* Internal Ground (Input Mode = 3) */
+    ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0),  /* PAD Ground (Input Mode = 2) */
+    ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0),  /* Internal Ground (Input Mode = 2) */
+    ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0),  /* PAD Ground (Input Mode = 3) */
+} ADC_CH_MUXNEG_t;
+
+/* Positive input multiplexer selection */
+typedef enum ADC_CH_MUXPOS_enum
+{
+    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
+    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
+    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
+    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
+    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
+    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
+    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
+    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
+    ADC_CH_MUXPOS_PIN8_gc = (0x08<<3),  /* Input pin 8 */
+    ADC_CH_MUXPOS_PIN9_gc = (0x09<<3),  /* Input pin 9 */
+    ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3),  /* Input pin 10 */
+    ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3),  /* Input pin 11 */
+    ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3),  /* Input pin 12 */
+    ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3),  /* Input pin 13 */
+    ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3),  /* Input pin 14 */
+    ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3),  /* Input pin 15 */
+} ADC_CH_MUXPOS_t;
+
+/* Current Limitation Mode */
+typedef enum ADC_CURRLIMIT_enum
+{
+    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No limit */
+    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit, max. sampling rate 1.5MSPS */
+    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, max. sampling rate 1MSPS */
+    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit, max. sampling rate 0.5MSPS */
+} ADC_CURRLIMIT_t;
+
+/* DMA request selection */
+typedef enum ADC_DMASEL_enum
+{
+    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
+    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
+    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
+    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
+} ADC_DMASEL_t;
+
+/* Event action selection */
+typedef enum ADC_EVACT_enum
+{
+    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
+    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
+    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
+    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
+    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
+    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
+    ADC_EVACT_SYNCSWEEP_gc = (0x06<<0),  /* The ADC is flushed and restarted for accurate timing */
+} ADC_EVACT_t;
+
+/* Event channel input selection */
+typedef enum ADC_EVSEL_enum
+{
+    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
+    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
+    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
+    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
+    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
+    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
+    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
+    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
+} ADC_EVSEL_t;
+
+/* Clock prescaler */
+typedef enum ADC_PRESCALER_enum
+{
+    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
+    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
+    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
+    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
+    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
+    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
+    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
+    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
+} ADC_PRESCALER_t;
+
+/* Voltage reference selection */
+typedef enum ADC_REFSEL_enum
+{
+    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
+    ADC_REFSEL_INTVCC_gc = (0x01<<4),  /* Internal VCC / 1.6 */
+    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
+    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
+    ADC_REFSEL_INTVCC2_gc = (0x04<<4),  /* Internal VCC / 2 */
+} ADC_REFSEL_t;
+
+/* Conversion result resolution */
+typedef enum ADC_RESOLUTION_enum
+{
+    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
+    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
+    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
+} ADC_RESOLUTION_t;
+
+/* Channel sweep selection */
+typedef enum ADC_SWEEP_enum
+{
+    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
+    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
+    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
+    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
+} ADC_SWEEP_t;
+
+/*
+--------------------------------------------------------------------------
+AES - AES Module
+--------------------------------------------------------------------------
+*/
+
+/* AES Module */
+typedef struct AES_struct
+{
+    register8_t CTRL;  /* AES Control Register */
+    register8_t STATUS;  /* AES Status Register */
+    register8_t STATE;  /* AES State Register */
+    register8_t KEY;  /* AES Key Register */
+    register8_t INTCTRL;  /* AES Interrupt Control Register */
+} AES_t;
+
+/* Interrupt level */
+typedef enum AES_INTLVL_enum
+{
+    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
+} AES_INTLVL_t;
+
+/*
+--------------------------------------------------------------------------
+AWEX - Timer/Counter Advanced Waveform Extension
+--------------------------------------------------------------------------
+*/
+
+/* Advanced Waveform Extension */
+typedef struct AWEX_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t reserved_0x01;
+    register8_t FDEMASK;  /* Fault Detection Event Mask */
+    register8_t FDCTRL;  /* Fault Detection Control Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t STATUSSET;  /* Status Set Register */
+    register8_t DTBOTH;  /* Dead Time Both Sides */
+    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
+    register8_t DTLS;  /* Dead Time Low Side */
+    register8_t DTHS;  /* Dead Time High Side */
+    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
+    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
+    register8_t OUTOVEN;  /* Output Override Enable */
+} AWEX_t;
+
+/* Fault Detect Action */
+typedef enum AWEX_FDACT_enum
+{
+    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
+    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
+    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
+} AWEX_FDACT_t;
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Clock System */
+typedef struct CLK_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t PSCTRL;  /* Prescaler Control Register */
+    register8_t LOCK;  /* Lock register */
+    register8_t RTCCTRL;  /* RTC Control Register */
+    register8_t USBCTRL;  /* USB Control Register */
+} CLK_t;
+
+/* Prescaler A Division Factor */
+typedef enum CLK_PSADIV_enum
+{
+    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
+    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
+    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
+    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
+    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
+    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
+    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
+    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
+    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
+    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
+} CLK_PSADIV_t;
+
+/* Prescaler B and C Division Factor */
+typedef enum CLK_PSBCDIV_enum
+{
+    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
+    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
+    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
+    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
+} CLK_PSBCDIV_t;
+
+/* RTC Clock Source */
+typedef enum CLK_RTCSRC_enum
+{
+    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1.024 kHz from internal 32kHz ULP */
+    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
+    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1.024 kHz from internal 32.768 kHz RC oscillator */
+    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
+    CLK_RTCSRC_RCOSC32_gc = (0x06<<1),  /* 32.768 kHz from internal 32.768 kHz RC oscillator */
+    CLK_RTCSRC_EXTCLK_gc = (0x07<<1),  /* External Clock from TOSC1 */
+} CLK_RTCSRC_t;
+
+/* System Clock Selection */
+typedef enum CLK_SCLKSEL_enum
+{
+    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2 MHz RC Oscillator */
+    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32 MHz RC Oscillator */
+    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32.768 kHz RC Oscillator */
+    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
+    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
+} CLK_SCLKSEL_t;
+
+/* USB Prescaler Division Factor */
+typedef enum CLK_USBPSDIV_enum
+{
+    CLK_USBPSDIV_1_gc = (0x00<<3),  /* Divide by 1 */
+    CLK_USBPSDIV_2_gc = (0x01<<3),  /* Divide by 2 */
+    CLK_USBPSDIV_4_gc = (0x02<<3),  /* Divide by 4 */
+    CLK_USBPSDIV_8_gc = (0x03<<3),  /* Divide by 8 */
+    CLK_USBPSDIV_16_gc = (0x04<<3),  /* Divide by 16 */
+    CLK_USBPSDIV_32_gc = (0x05<<3),  /* Divide by 32 */
+} CLK_USBPSDIV_t;
+
+/* USB Clock Source */
+typedef enum CLK_USBSRC_enum
+{
+    CLK_USBSRC_PLL_gc = (0x00<<1),  /* PLL */
+    CLK_USBSRC_RC32M_gc = (0x01<<1),  /* Internal 32 MHz RC Oscillator */
+} CLK_USBSRC_t;
+
+/*
+--------------------------------------------------------------------------
+CPU - CPU
+--------------------------------------------------------------------------
+*/
+
+/* CCP signatures */
+typedef enum CCP_enum
+{
+    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
+    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
+} CCP_t;
+
+/*
+--------------------------------------------------------------------------
+CRC - Cyclic Redundancy Checker
+--------------------------------------------------------------------------
+*/
+
+/* Cyclic Redundancy Checker */
+typedef struct CRC_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t reserved_0x02;
+    register8_t DATAIN;  /* Data Input */
+    register8_t CHECKSUM0;  /* Checksum byte 0 */
+    register8_t CHECKSUM1;  /* Checksum byte 1 */
+    register8_t CHECKSUM2;  /* Checksum byte 2 */
+    register8_t CHECKSUM3;  /* Checksum byte 3 */
+} CRC_t;
+
+/* Reset */
+typedef enum CRC_RESET_enum
+{
+    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
+    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
+    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
+} CRC_RESET_t;
+
+/* Input Source */
+typedef enum CRC_SOURCE_enum
+{
+    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
+    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
+    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
+    CRC_SOURCE_DMAC0_gc = (0x04<<0),  /* DMAC Channel 0 */
+    CRC_SOURCE_DMAC1_gc = (0x05<<0),  /* DMAC Channel 1 */
+    CRC_SOURCE_DMAC2_gc = (0x06<<0),  /* DMAC Channel 2 */
+    CRC_SOURCE_DMAC3_gc = (0x07<<0),  /* DMAC Channel 3 */
+} CRC_SOURCE_t;
+
+/*
+--------------------------------------------------------------------------
+DAC - Digital/Analog Converter
+--------------------------------------------------------------------------
+*/
+
+/* Digital-to-Analog Converter */
+typedef struct DAC_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control Register C */
+    register8_t EVCTRL;  /* Event Input Control */
+    register8_t reserved_0x04;
+    register8_t STATUS;  /* Status */
+    register8_t reserved_0x06;
+    register8_t reserved_0x07;
+    register8_t CH0GAINCAL;  /* Gain Calibration */
+    register8_t CH0OFFSETCAL;  /* Offset Calibration */
+    register8_t CH1GAINCAL;  /* Gain Calibration */
+    register8_t CH1OFFSETCAL;  /* Offset Calibration */
+    register8_t reserved_0x0C;
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    register8_t reserved_0x10;
+    register8_t reserved_0x11;
+    register8_t reserved_0x12;
+    register8_t reserved_0x13;
+    register8_t reserved_0x14;
+    register8_t reserved_0x15;
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
+    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
+} DAC_t;
+
+/* Output channel selection */
+typedef enum DAC_CHSEL_enum
+{
+    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel 0 only) */
+    DAC_CHSEL_SINGLE1_gc = (0x01<<5),  /* Single channel operation (Channel 1 only) */
+    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (Channel 0 and channel 1) */
+} DAC_CHSEL_t;
+
+/* Event channel selection */
+typedef enum DAC_EVSEL_enum
+{
+    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
+    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
+    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
+    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
+    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
+    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
+    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
+    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
+} DAC_EVSEL_t;
+
+/* Reference voltage selection */
+typedef enum DAC_REFSEL_enum
+{
+    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
+    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
+    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
+    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
+} DAC_REFSEL_t;
+
+/*
+--------------------------------------------------------------------------
+DFLL - DFLL
+--------------------------------------------------------------------------
+*/
+
+/* DFLL */
+typedef struct DFLL_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t reserved_0x01;
+    register8_t CALA;  /* Calibration Register A */
+    register8_t CALB;  /* Calibration Register B */
+    register8_t COMP0;  /* Oscillator Compare Register 0 */
+    register8_t COMP1;  /* Oscillator Compare Register 1 */
+    register8_t COMP2;  /* Oscillator Compare Register 2 */
+    register8_t reserved_0x07;
+} DFLL_t;
+
+
+/*
+--------------------------------------------------------------------------
+DMA - DMA Controller
+--------------------------------------------------------------------------
+*/
+
+/* DMA Channel */
+typedef struct DMA_CH_struct
+{
+    register8_t CTRLA;  /* Channel Control */
+    register8_t CTRLB;  /* Channel Control */
+    register8_t ADDRCTRL;  /* Address Control */
+    register8_t TRIGSRC;  /* Channel Trigger Source */
+    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
+    register8_t REPCNT;  /* Channel Repeat Count */
+    register8_t reserved_0x07;
+    register8_t SRCADDR0;  /* Channel Source Address 0 */
+    register8_t SRCADDR1;  /* Channel Source Address 1 */
+    register8_t SRCADDR2;  /* Channel Source Address 2 */
+    register8_t reserved_0x0B;
+    register8_t DESTADDR0;  /* Channel Destination Address 0 */
+    register8_t DESTADDR1;  /* Channel Destination Address 1 */
+    register8_t DESTADDR2;  /* Channel Destination Address 2 */
+    register8_t reserved_0x0F;
+} DMA_CH_t;
+
+
+/* DMA Controller */
+typedef struct DMA_struct
+{
+    register8_t CTRL;  /* Control */
+    register8_t reserved_0x01;
+    register8_t reserved_0x02;
+    register8_t INTFLAGS;  /* Transfer Interrupt Status */
+    register8_t STATUS;  /* Status */
+    register8_t reserved_0x05;
+    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
+    register8_t reserved_0x08;
+    register8_t reserved_0x09;
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+    register8_t reserved_0x0C;
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    DMA_CH_t CH0;  /* DMA Channel 0 */
+    DMA_CH_t CH1;  /* DMA Channel 1 */
+    DMA_CH_t CH2;  /* DMA Channel 2 */
+    DMA_CH_t CH3;  /* DMA Channel 3 */
+} DMA_t;
+
+/* Burst mode */
+typedef enum DMA_CH_BURSTLEN_enum
+{
+    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
+    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
+    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
+    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
+} DMA_CH_BURSTLEN_t;
+
+/* Destination addressing mode */
+typedef enum DMA_CH_DESTDIR_enum
+{
+    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
+    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
+    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
+} DMA_CH_DESTDIR_t;
+
+/* Destination address reload mode */
+typedef enum DMA_CH_DESTRELOAD_enum
+{
+    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
+    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
+    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
+    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
+} DMA_CH_DESTRELOAD_t;
+
+/* Interrupt level */
+typedef enum DMA_CH_ERRINTLVL_enum
+{
+    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
+    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
+    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
+    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
+} DMA_CH_ERRINTLVL_t;
+
+/* Source addressing mode */
+typedef enum DMA_CH_SRCDIR_enum
+{
+    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
+    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
+    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
+} DMA_CH_SRCDIR_t;
+
+/* Source address reload mode */
+typedef enum DMA_CH_SRCRELOAD_enum
+{
+    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
+    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
+    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
+    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
+} DMA_CH_SRCRELOAD_t;
+
+/* Transfer trigger source */
+typedef enum DMA_CH_TRIGSRC_enum
+{
+    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
+    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
+    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
+    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
+    DMA_CH_TRIGSRC_AES_gc = (0x04<<0),  /* AES */
+    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
+    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
+    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
+    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
+    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
+    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
+    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
+    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
+    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
+    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
+    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
+    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
+    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
+    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
+    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
+    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
+    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
+    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
+    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
+    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
+    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
+    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
+    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
+    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
+    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
+    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
+    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
+    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
+    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
+    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
+    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
+    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
+    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
+    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
+    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
+    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
+    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
+    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
+    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
+    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
+    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
+    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
+} DMA_CH_TRIGSRC_t;
+
+/* Interrupt level */
+typedef enum DMA_CH_TRNINTLVL_enum
+{
+    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
+    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
+    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
+    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
+} DMA_CH_TRNINTLVL_t;
+
+/* Double buffering mode */
+typedef enum DMA_DBUFMODE_enum
+{
+    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
+    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
+    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
+    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
+} DMA_DBUFMODE_t;
+
+/* Priority mode */
+typedef enum DMA_PRIMODE_enum
+{
+    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
+    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
+    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
+    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
+} DMA_PRIMODE_t;
+
+/*
+--------------------------------------------------------------------------
+EVSYS - Event System
+--------------------------------------------------------------------------
+*/
+
+/* Event System */
+typedef struct EVSYS_struct
+{
+    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
+    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
+    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
+    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
+    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
+    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
+    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
+    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
+    register8_t CH0CTRL;  /* Channel 0 Control Register */
+    register8_t CH1CTRL;  /* Channel 1 Control Register */
+    register8_t CH2CTRL;  /* Channel 2 Control Register */
+    register8_t CH3CTRL;  /* Channel 3 Control Register */
+    register8_t CH4CTRL;  /* Channel 4 Control Register */
+    register8_t CH5CTRL;  /* Channel 5 Control Register */
+    register8_t CH6CTRL;  /* Channel 6 Control Register */
+    register8_t CH7CTRL;  /* Channel 7 Control Register */
+    register8_t STROBE;  /* Event Strobe */
+    register8_t DATA;  /* Event Data */
+} EVSYS_t;
+
+/* Event Channel multiplexer input selection */
+typedef enum EVSYS_CHMUX_enum
+{
+    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
+    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
+    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
+    EVSYS_CHMUX_USB_gc = (0x0A<<0),  /* USB Setup, SOF, CRC error and UNF/OVF */
+    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
+    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
+    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
+    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
+    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
+    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
+    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
+    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
+    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
+    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
+    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
+    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
+    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
+    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
+    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
+    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
+    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
+    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
+    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
+    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
+    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
+    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
+    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
+    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
+    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
+    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
+    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
+    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
+    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
+    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
+    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
+    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
+    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
+    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
+    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
+    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
+    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
+    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
+    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
+    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
+    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
+    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
+    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
+    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
+    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
+    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
+    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
+    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
+    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
+    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
+    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
+    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
+    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
+    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
+    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
+    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
+    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
+    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
+    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
+    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
+    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
+    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
+    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
+    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
+    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
+    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
+    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
+    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
+    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
+    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
+    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
+    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
+    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
+    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
+    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
+    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
+    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
+    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
+    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
+    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
+    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
+    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
+    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
+    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
+    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
+    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
+    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
+    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
+    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
+    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
+    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
+    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
+    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
+    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
+    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
+    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
+    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
+    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
+    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
+    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
+    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
+    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
+    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
+    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
+    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
+    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
+    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
+    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
+    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
+    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
+    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
+    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
+    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
+    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
+    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
+    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
+    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
+    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
+} EVSYS_CHMUX_t;
+
+/* Digital filter coefficient */
+typedef enum EVSYS_DIGFILT_enum
+{
+    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
+    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
+    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
+    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
+    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
+    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
+    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
+    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
+} EVSYS_DIGFILT_t;
+
+/* Quadrature Decoder Index Recognition Mode */
+typedef enum EVSYS_QDIRM_enum
+{
+    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
+    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
+    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
+    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
+} EVSYS_QDIRM_t;
+
+/*
+--------------------------------------------------------------------------
+FUSE - Fuses and Lockbits
+--------------------------------------------------------------------------
+*/
+
+/* Fuses */
+typedef struct NVM_FUSES_struct
+{
+    register8_t FUSEBYTE0;  /* JTAG User ID */
+    register8_t FUSEBYTE1;  /* Watchdog Configuration */
+    register8_t FUSEBYTE2;  /* Reset Configuration */
+    register8_t reserved_0x03;
+    register8_t FUSEBYTE4;  /* Start-up Configuration */
+    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
+} NVM_FUSES_t;
+
+/* BOD operation */
+typedef enum BODACT_enum
+{
+    BODACT_SAMPLED_gc = (0x01<<4),  /* BOD enabled in sampled mode */
+    BODACT_CONTINUOUS_gc = (0x02<<4),  /* BOD enabled continuously */
+    BODACT_DISABLED_gc = (0x03<<4),  /* BOD Disabled */
+} BODACT_t;
+
+/* Brownout Detection Voltage Level */
+typedef enum BODLVL_enum
+{
+    BODLVL_3V0_gc = (0x00<<0),  /* 3.0 V */
+    BODLVL_2V8_gc = (0x01<<0),  /* 2.8 V */
+    BODLVL_2V6_gc = (0x02<<0),  /* 2.6 V */
+    BODLVL_2V4_gc = (0x03<<0),  /* 2.4 V */
+    BODLVL_2V2_gc = (0x04<<0),  /* 2.2 V */
+    BODLVL_2V0_gc = (0x05<<0),  /* 2.0 V */
+    BODLVL_1V8_gc = (0x06<<0),  /* 1.8 V */
+    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
+} BODLVL_t;
+
+/* BOD operation */
+typedef enum BODPD_enum
+{
+    BODPD_SAMPLED_gc = (0x01<<0),  /* BOD enabled in sampled mode */
+    BODPD_CONTINUOUS_gc = (0x02<<0),  /* BOD enabled continuously */
+    BODPD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
+} BODPD_t;
+
+/* Boot Loader Section Reset Vector */
+typedef enum BOOTRST_enum
+{
+    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
+    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
+} BOOTRST_t;
+
+/* Start-up Time */
+typedef enum STARTUPTIME_enum
+{
+    STARTUPTIME_64MS_gc = (0x00<<2),  /* 64 ms */
+    STARTUPTIME_4MS_gc = (0x01<<2),  /* 4 ms */
+    STARTUPTIME_0MS_gc = (0x03<<2),  /* 0 ms */
+} STARTUPTIME_t;
+
+/* Timer Oscillator pin location */
+typedef enum TOSCSEL_enum
+{
+    TOSCSEL_ALTERNATE_gc = (0x00<<5),  /* TOSC1 / TOSC2 on separate pins */
+    TOSCSEL_XTAL_gc = (0x01<<5),  /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
+} TOSCSEL_t;
+
+/* Watchdog (Window) Timeout Period */
+typedef enum WDPER_enum
+{
+    WDPER_8CLK_gc = (0x00<<0),  /* 8 cycles (8ms @ 3.3V) */
+    WDPER_16CLK_gc = (0x01<<0),  /* 16 cycles (16ms @ 3.3V) */
+    WDPER_32CLK_gc = (0x02<<0),  /* 32 cycles (32ms @ 3.3V) */
+    WDPER_64CLK_gc = (0x03<<0),  /* 64 cycles (64ms @ 3.3V) */
+    WDPER_128CLK_gc = (0x04<<0),  /* 128 cycles (0.125s @ 3.3V) */
+    WDPER_256CLK_gc = (0x05<<0),  /* 256 cycles (0.25s @ 3.3V) */
+    WDPER_512CLK_gc = (0x06<<0),  /* 512 cycles (0.5s @ 3.3V) */
+    WDPER_1KCLK_gc = (0x07<<0),  /* 1K cycles (1s @ 3.3V) */
+    WDPER_2KCLK_gc = (0x08<<0),  /* 2K cycles (2s @ 3.3V) */
+    WDPER_4KCLK_gc = (0x09<<0),  /* 4K cycles (4s @ 3.3V) */
+    WDPER_8KCLK_gc = (0x0A<<0),  /* 8K cycles (8s @ 3.3V) */
+} WDPER_t;
+
+/* Watchdog (Window) Timeout Period */
+typedef enum WDWPER_enum
+{
+    WDWPER_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
+    WDWPER_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
+    WDWPER_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
+    WDWPER_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
+    WDWPER_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
+    WDWPER_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
+    WDWPER_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
+    WDWPER_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
+    WDWPER_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
+    WDWPER_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
+    WDWPER_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
+} WDWPER_t;
+
+/*
+--------------------------------------------------------------------------
+HIRES - Timer/Counter High-Resolution Extension
+--------------------------------------------------------------------------
+*/
+
+/* High-Resolution Extension */
+typedef struct HIRES_struct
+{
+    register8_t CTRLA;  /* Control Register */
+} HIRES_t;
+
+/* High Resolution Enable */
+typedef enum HIRES_HREN_enum
+{
+    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
+    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
+    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
+    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
+} HIRES_HREN_t;
+
+/*
+--------------------------------------------------------------------------
+IRCOM - IR Communication Module
+--------------------------------------------------------------------------
+*/
+
+/* IR Communication Module */
+typedef struct IRCOM_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
+    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
+} IRCOM_t;
+
+/* Event channel selection */
+typedef enum IRCOM_EVSEL_enum
+{
+    IRCOM_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
+    IRCOM_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
+    IRCOM_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
+    IRCOM_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
+    IRCOM_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
+    IRCOM_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
+    IRCOM_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
+    IRCOM_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
+    IRCOM_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
+} IRCOM_EVSEL_t;
+
+/*
+--------------------------------------------------------------------------
+LOCKBIT - Fuses and Lockbits
+--------------------------------------------------------------------------
+*/
+
+/* Lock Bits */
+typedef struct NVM_LOCKBITS_struct
+{
+    register8_t LOCK_BITS;  /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */
+} NVM_LOCKBITS_t;
+
+/* Boot lock bits - application section */
+typedef enum BLBA_enum
+{
+    BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
+    BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
+    BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
+    BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
+} BLBA_t;
+
+/* Boot lock bits - application table section */
+typedef enum BLBAT_enum
+{
+    BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
+    BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
+    BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
+    BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
+} BLBAT_t;
+
+/* Boot lock bits - boot section */
+typedef enum BLBB_enum
+{
+    BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
+    BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
+    BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
+    BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
+} BLBB_t;
+
+/* Lock bits */
+typedef enum LB_enum
+{
+    LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
+    LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
+    LB_NOLOCK_gc = (0x03<<0),  /* No locks */
+} LB_t;
+
+/*
+--------------------------------------------------------------------------
+MCU - MCU Control
+--------------------------------------------------------------------------
+*/
+
+/* MCU Control */
+typedef struct MCU_struct
+{
+    register8_t DEVID0;  /* Device ID byte 0 */
+    register8_t DEVID1;  /* Device ID byte 1 */
+    register8_t DEVID2;  /* Device ID byte 2 */
+    register8_t REVID;  /* Revision ID */
+    register8_t JTAGUID;  /* JTAG User ID */
+    register8_t reserved_0x05;
+    register8_t MCUCR;  /* MCU Control */
+    register8_t ANAINIT;  /* Analog Startup Delay */
+    register8_t EVSYSLOCK;  /* Event System Lock */
+    register8_t AWEXLOCK;  /* AWEX Lock */
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+} MCU_t;
+
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Non-volatile Memory Controller */
+typedef struct NVM_struct
+{
+    register8_t ADDR0;  /* Address Register 0 */
+    register8_t ADDR1;  /* Address Register 1 */
+    register8_t ADDR2;  /* Address Register 2 */
+    register8_t reserved_0x03;
+    register8_t DATA0;  /* Data Register 0 */
+    register8_t DATA1;  /* Data Register 1 */
+    register8_t DATA2;  /* Data Register 2 */
+    register8_t reserved_0x07;
+    register8_t reserved_0x08;
+    register8_t reserved_0x09;
+    register8_t CMD;  /* Command */
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t INTCTRL;  /* Interrupt Control */
+    register8_t reserved_0x0E;
+    register8_t STATUS;  /* Status */
+    register8_t LOCK_BITS;  /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */
+} NVM_t;
+
+/* Boot lock bits - application section */
+typedef enum NVM_BLBA_enum
+{
+    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
+    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
+    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
+    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
+} NVM_BLBA_t;
+
+/* Boot lock bits - application table section */
+typedef enum NVM_BLBAT_enum
+{
+    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
+    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
+    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
+    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
+} NVM_BLBAT_t;
+
+/* Boot lock bits - boot section */
+typedef enum NVM_BLBB_enum
+{
+    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
+    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
+    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
+    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
+} NVM_BLBB_t;
+
+/* NVM Command */
+typedef enum NVM_CMD_enum
+{
+    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
+    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
+    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
+    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
+    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
+    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
+    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
+    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
+    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
+    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
+    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
+    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
+    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
+    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
+    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
+    NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0),  /* Erase Flash Page */
+    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
+    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
+    NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0),  /* Write Flash Page */
+    NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0),  /* Erase-and-write Flash Page */
+    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
+    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
+    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
+    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
+    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
+    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
+    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Application section CRC */
+    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /*  Boot Section CRC */
+    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Flash Range CRC */
+    NVM_CMD_CHIP_ERASE_gc = (0x40<<0),  /* Erase Chip */
+    NVM_CMD_READ_NVM_gc = (0x43<<0),  /* Read NVM */
+    NVM_CMD_WRITE_FUSE_gc = (0x4C<<0),  /* Write Fuse byte */
+    NVM_CMD_ERASE_BOOT_gc = (0x68<<0),  /* Erase Boot Section */
+    NVM_CMD_FLASH_CRC_gc = (0x78<<0),  /* Flash CRC */
+} NVM_CMD_t;
+
+/* EEPROM ready interrupt level */
+typedef enum NVM_EELVL_enum
+{
+    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
+    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
+    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
+    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
+} NVM_EELVL_t;
+
+/* Lock bits */
+typedef enum NVM_LB_enum
+{
+    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
+    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
+    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
+} NVM_LB_t;
+
+/* SPM ready interrupt level */
+typedef enum NVM_SPMLVL_enum
+{
+    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
+    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
+    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
+    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
+} NVM_SPMLVL_t;
+
+/*
+--------------------------------------------------------------------------
+OSC - Oscillator
+--------------------------------------------------------------------------
+*/
+
+/* Oscillator */
+typedef struct OSC_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t XOSCCTRL;  /* External Oscillator Control Register */
+    register8_t XOSCFAIL;  /* Oscillator Failure Detection Register */
+    register8_t RC32KCAL;  /* 32.768 kHz Internal Oscillator Calibration Register */
+    register8_t PLLCTRL;  /* PLL Control Register */
+    register8_t DFLLCTRL;  /* DFLL Control Register */
+} OSC_t;
+
+/* Oscillator Frequency Range */
+typedef enum OSC_FRQRANGE_enum
+{
+    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
+    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
+    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
+    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
+} OSC_FRQRANGE_t;
+
+/* PLL Clock Source */
+typedef enum OSC_PLLSRC_enum
+{
+    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2 MHz RC Oscillator */
+    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32 MHz RC Oscillator */
+    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
+} OSC_PLLSRC_t;
+
+/* 2 MHz DFLL Calibration Reference */
+typedef enum OSC_RC2MCREF_enum
+{
+    OSC_RC2MCREF_RC32K_gc = (0x00<<0),  /* Internal 32.768 kHz RC Oscillator */
+    OSC_RC2MCREF_XOSC32K_gc = (0x01<<0),  /* External 32.768 kHz Crystal Oscillator */
+} OSC_RC2MCREF_t;
+
+/* 32 MHz DFLL Calibration Reference */
+typedef enum OSC_RC32MCREF_enum
+{
+    OSC_RC32MCREF_RC32K_gc = (0x00<<1),  /* Internal 32.768 kHz RC Oscillator */
+    OSC_RC32MCREF_XOSC32K_gc = (0x01<<1),  /* External 32.768 kHz Crystal Oscillator */
+    OSC_RC32MCREF_USBSOF_gc = (0x02<<1),  /* USB Start of Frame */
+} OSC_RC32MCREF_t;
+
+/* External Oscillator Selection and Startup Time */
+typedef enum OSC_XOSCSEL_enum
+{
+    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
+    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32.768 kHz TOSC - 32K CLK */
+    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16 MHz XTAL - 256 CLK */
+    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16 MHz XTAL - 1K CLK */
+    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16 MHz XTAL - 16K CLK */
+} OSC_XOSCSEL_t;
+
+/*
+--------------------------------------------------------------------------
+PMIC - Programmable Multi-level Interrupt Controller
+--------------------------------------------------------------------------
+*/
+
+/* Programmable Multi-level Interrupt Controller */
+typedef struct PMIC_struct
+{
+    register8_t STATUS;  /* Status Register */
+    register8_t INTPRI;  /* Interrupt Priority */
+    register8_t CTRL;  /* Control Register */
+    register8_t reserved_0x03;
+    register8_t reserved_0x04;
+    register8_t reserved_0x05;
+    register8_t reserved_0x06;
+    register8_t reserved_0x07;
+    register8_t reserved_0x08;
+    register8_t reserved_0x09;
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+    register8_t reserved_0x0C;
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+} PMIC_t;
+
+
+/*
+--------------------------------------------------------------------------
+PORT - I/O Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O Ports */
+typedef struct PORT_struct
+{
+    register8_t DIR;  /* I/O Port Data Direction */
+    register8_t DIRSET;  /* I/O Port Data Direction Set */
+    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
+    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
+    register8_t OUT;  /* I/O Port Output */
+    register8_t OUTSET;  /* I/O Port Output Set */
+    register8_t OUTCLR;  /* I/O Port Output Clear */
+    register8_t OUTTGL;  /* I/O Port Output Toggle */
+    register8_t IN;  /* I/O port Input */
+    register8_t INTCTRL;  /* Interrupt Control Register */
+    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
+    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
+    register8_t INTFLAGS;  /* Interrupt Flag Register */
+    register8_t reserved_0x0D;
+    register8_t REMAP;  /* I/O Port Pin Remap Register */
+    register8_t reserved_0x0F;
+    register8_t PIN0CTRL;  /* Pin 0 Control Register */
+    register8_t PIN1CTRL;  /* Pin 1 Control Register */
+    register8_t PIN2CTRL;  /* Pin 2 Control Register */
+    register8_t PIN3CTRL;  /* Pin 3 Control Register */
+    register8_t PIN4CTRL;  /* Pin 4 Control Register */
+    register8_t PIN5CTRL;  /* Pin 5 Control Register */
+    register8_t PIN6CTRL;  /* Pin 6 Control Register */
+    register8_t PIN7CTRL;  /* Pin 7 Control Register */
+} PORT_t;
+
+/* Port Interrupt 0 Level */
+typedef enum PORT_INT0LVL_enum
+{
+    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
+    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
+    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
+} PORT_INT0LVL_t;
+
+/* Port Interrupt 1 Level */
+typedef enum PORT_INT1LVL_enum
+{
+    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
+    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
+    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
+} PORT_INT1LVL_t;
+
+/* Input/Sense Configuration */
+typedef enum PORT_ISC_enum
+{
+    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
+    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
+    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
+    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
+    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
+} PORT_ISC_t;
+
+/* Output/Pull Configuration */
+typedef enum PORT_OPC_enum
+{
+    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
+    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
+    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
+    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
+    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
+    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
+    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
+    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
+} PORT_OPC_t;
+
+/*
+--------------------------------------------------------------------------
+PORTCFG - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O port Configuration */
+typedef struct PORTCFG_struct
+{
+    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
+    register8_t reserved_0x01;
+    register8_t VPCTRLA;  /* Virtual Port Control Register A */
+    register8_t VPCTRLB;  /* Virtual Port Control Register B */
+    register8_t CLKEVOUT;  /* Clock and Event Out Register */
+    register8_t reserved_0x05;
+    register8_t EVOUTSEL;  /* Event Output Select */
+} PORTCFG_t;
+
+/* Clock and Event Output Port */
+typedef enum PORTCFG_CLKEVPIN_enum
+{
+    PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7),  /* Clock and Event Output on PIN 7 */
+    PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7),  /* Clock and Event Output on PIN 4 */
+} PORTCFG_CLKEVPIN_t;
+
+/* System Clock Output Port */
+typedef enum PORTCFG_CLKOUT_enum
+{
+    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* System Clock Output Disabled */
+    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* System Clock Output on Port C pin 7 */
+    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* System Clock Output on Port D pin 7 */
+    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* System Clock Output on Port E pin 7 */
+} PORTCFG_CLKOUT_t;
+
+/* Peripheral Clock Output Select */
+typedef enum PORTCFG_CLKOUTSEL_enum
+{
+    PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2),  /* 1x Peripheral Clock Output to pin */
+    PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2),  /* 2x Peripheral Clock Output to pin */
+    PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2),  /* 4x Peripheral Clock Output to pin */
+} PORTCFG_CLKOUTSEL_t;
+
+/* Event Output Port */
+typedef enum PORTCFG_EVOUT_enum
+{
+    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
+    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
+    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
+    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
+} PORTCFG_EVOUT_t;
+
+/* Event Output Select */
+typedef enum PORTCFG_EVOUTSEL_enum
+{
+    PORTCFG_EVOUTSEL_0_gc = (0x00<<0),  /* Event Channel 0 output to pin */
+    PORTCFG_EVOUTSEL_1_gc = (0x01<<0),  /* Event Channel 1 output to pin */
+    PORTCFG_EVOUTSEL_2_gc = (0x02<<0),  /* Event Channel 2 output to pin */
+    PORTCFG_EVOUTSEL_3_gc = (0x03<<0),  /* Event Channel 3 output to pin */
+    PORTCFG_EVOUTSEL_4_gc = (0x04<<0),  /* Event Channel 4 output to pin */
+    PORTCFG_EVOUTSEL_5_gc = (0x05<<0),  /* Event Channel 5 output to pin */
+    PORTCFG_EVOUTSEL_6_gc = (0x06<<0),  /* Event Channel 6 output to pin */
+    PORTCFG_EVOUTSEL_7_gc = (0x07<<0),  /* Event Channel 7 output to pin */
+} PORTCFG_EVOUTSEL_t;
+
+/* Virtual Port Mapping */
+typedef enum PORTCFG_VP0MAP_enum
+{
+    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
+    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
+    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
+    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
+    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
+    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
+    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
+    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
+    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
+    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
+    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
+    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
+    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
+    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
+    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
+    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
+
+    /* Deprecated aliases */
+    PORTCFG_VP02MAP_PORTA_gc = (0x00<<0),  /* Deprecated Mapped To PORTA */
+    PORTCFG_VP02MAP_PORTB_gc = (0x01<<0),  /* Deprecated Mapped To PORTB */
+    PORTCFG_VP02MAP_PORTC_gc = (0x02<<0),  /* Deprecated Mapped To PORTC */
+    PORTCFG_VP02MAP_PORTD_gc = (0x03<<0),  /* Deprecated Mapped To PORTD */
+    PORTCFG_VP02MAP_PORTE_gc = (0x04<<0),  /* Deprecated Mapped To PORTE */
+    PORTCFG_VP02MAP_PORTF_gc = (0x05<<0),  /* Deprecated Mapped To PORTF */
+    PORTCFG_VP02MAP_PORTG_gc = (0x06<<0),  /* Deprecated Mapped To PORTG */
+    PORTCFG_VP02MAP_PORTH_gc = (0x07<<0),  /* Deprecated Mapped To PORTH */
+    PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0),  /* Deprecated Mapped To PORTJ */
+    PORTCFG_VP02MAP_PORTK_gc = (0x09<<0),  /* Deprecated Mapped To PORTK */
+    PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0),  /* Deprecated Mapped To PORTL */
+    PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0),  /* Deprecated Mapped To PORTM */
+    PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0),  /* Deprecated Mapped To PORTN */
+    PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0),  /* Deprecated Mapped To PORTP */
+    PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0),  /* Deprecated Mapped To PORTQ */
+    PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0),  /* Deprecated Mapped To PORTR */
+} PORTCFG_VP0MAP_t;
+
+/* Deprecated type definition */
+typedef enum PORTCFG_VP0MAP_enum PORTCFG_VP02MAP_t;
+
+/* Virtual Port Mapping */
+typedef enum PORTCFG_VP1MAP_enum
+{
+    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
+    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
+    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
+    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
+    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
+    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
+    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
+    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
+    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
+    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
+    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
+    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
+    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
+    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
+    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
+    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
+
+    /* Deprecated aliases */
+    PORTCFG_VP13MAP_PORTA_gc = (0x00<<4),  /* Deprecated Mapped To PORTA */
+    PORTCFG_VP13MAP_PORTB_gc = (0x01<<4),  /* Deprecated Mapped To PORTB */
+    PORTCFG_VP13MAP_PORTC_gc = (0x02<<4),  /* Deprecated Mapped To PORTC */
+    PORTCFG_VP13MAP_PORTD_gc = (0x03<<4),  /* Deprecated Mapped To PORTD */
+    PORTCFG_VP13MAP_PORTE_gc = (0x04<<4),  /* Deprecated Mapped To PORTE */
+    PORTCFG_VP13MAP_PORTF_gc = (0x05<<4),  /* Deprecated Mapped To PORTF */
+    PORTCFG_VP13MAP_PORTG_gc = (0x06<<4),  /* Deprecated Mapped To PORTG */
+    PORTCFG_VP13MAP_PORTH_gc = (0x07<<4),  /* Deprecated Mapped To PORTH */
+    PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4),  /* Deprecated Mapped To PORTJ */
+    PORTCFG_VP13MAP_PORTK_gc = (0x09<<4),  /* Deprecated Mapped To PORTK */
+    PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4),  /* Deprecated Mapped To PORTL */
+    PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4),  /* Deprecated Mapped To PORTM */
+    PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4),  /* Deprecated Mapped To PORTN */
+    PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4),  /* Deprecated Mapped To PORTP */
+    PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4),  /* Deprecated Mapped To PORTQ */
+    PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4),  /* Deprecated Mapped To PORTR */
+} PORTCFG_VP1MAP_t;
+
+/* Deprecated type definition */
+typedef enum PORTCFG_VP1MAP_enum PORTCFG_VP13MAP_t;
+
+/* Virtual Port Mapping */
+typedef enum PORTCFG_VP2MAP_enum
+{
+    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
+    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
+    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
+    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
+    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
+    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
+    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
+    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
+    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
+    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
+    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
+    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
+    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
+    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
+    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
+    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
+} PORTCFG_VP2MAP_t;
+
+/* Virtual Port Mapping */
+typedef enum PORTCFG_VP3MAP_enum
+{
+    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
+    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
+    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
+    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
+    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
+    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
+    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
+    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
+    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
+    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
+    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
+    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
+    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
+    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
+    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
+    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
+} PORTCFG_VP3MAP_t;
+
+/*
+--------------------------------------------------------------------------
+PR - Power Reduction
+--------------------------------------------------------------------------
+*/
+
+/* Power Reduction */
+typedef struct PR_struct
+{
+    register8_t PRGEN;  /* General Power Reduction */
+    register8_t PRPA;  /* Power Reduction Port A */
+    register8_t PRPB;  /* Power Reduction Port B */
+    register8_t PRPC;  /* Power Reduction Port C */
+    register8_t PRPD;  /* Power Reduction Port D */
+    register8_t PRPE;  /* Power Reduction Port E */
+    register8_t PRPF;  /* Power Reduction Port F */
+} PR_t;
+
+
+/*
+--------------------------------------------------------------------------
+RST - Reset
+--------------------------------------------------------------------------
+*/
+
+/* Reset */
+typedef struct RST_struct
+{
+    register8_t STATUS;  /* Status Register */
+    register8_t CTRL;  /* Control Register */
+} RST_t;
+
+
+/*
+--------------------------------------------------------------------------
+RTC - Real-Time Counter
+--------------------------------------------------------------------------
+*/
+
+/* Real-Time Counter */
+typedef struct RTC_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t INTCTRL;  /* Interrupt Control Register */
+    register8_t INTFLAGS;  /* Interrupt Flags */
+    register8_t TEMP;  /* Temporary register */
+    register8_t reserved_0x05;
+    register8_t reserved_0x06;
+    register8_t reserved_0x07;
+    _WORDREGISTER(CNT);  /* Count Register */
+    _WORDREGISTER(PER);  /* Period Register */
+    _WORDREGISTER(COMP);  /* Compare Register */
+} RTC_t;
+
+/* Compare Interrupt level */
+typedef enum RTC_COMPINTLVL_enum
+{
+    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} RTC_COMPINTLVL_t;
+
+/* Overflow Interrupt level */
+typedef enum RTC_OVFINTLVL_enum
+{
+    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} RTC_OVFINTLVL_t;
+
+/* Prescaler Factor */
+typedef enum RTC_PRESCALER_enum
+{
+    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
+    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
+    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
+    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
+    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
+    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
+    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
+    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
+} RTC_PRESCALER_t;
+
+/*
+--------------------------------------------------------------------------
+SIGROW - Signature Row
+--------------------------------------------------------------------------
+*/
+
+/* Production Signatures */
+typedef struct NVM_PROD_SIGNATURES_struct
+{
+    register8_t RCOSC2M;  /* RCOSC 2 MHz Calibration Value B */
+    register8_t RCOSC2MA;  /* RCOSC 2 MHz Calibration Value A */
+    register8_t RCOSC32K;  /* RCOSC 32.768 kHz Calibration Value */
+    register8_t RCOSC32M;  /* RCOSC 32 MHz Calibration Value B */
+    register8_t RCOSC32MA;  /* RCOSC 32 MHz Calibration Value A */
+    register8_t reserved_0x05;
+    register8_t reserved_0x06;
+    register8_t reserved_0x07;
+    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
+    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
+    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
+    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
+    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
+    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    register8_t WAFNUM;  /* Wafer Number */
+    register8_t reserved_0x11;
+    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
+    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
+    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
+    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    register8_t reserved_0x18;
+    register8_t reserved_0x19;
+    register8_t USBCAL0;  /* USB Calibration Byte 0 */
+    register8_t USBCAL1;  /* USB Calibration Byte 1 */
+    register8_t USBRCOSC;  /* USB RCOSC Calibration Value B */
+    register8_t USBRCOSCA;  /* USB RCOSC Calibration Value A */
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
+    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
+    register8_t reserved_0x22;
+    register8_t reserved_0x23;
+    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
+    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
+    register8_t reserved_0x26;
+    register8_t reserved_0x27;
+    register8_t reserved_0x28;
+    register8_t reserved_0x29;
+    register8_t reserved_0x2A;
+    register8_t reserved_0x2B;
+    register8_t reserved_0x2C;
+    register8_t reserved_0x2D;
+    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
+    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 1 */
+    register8_t DACA0OFFCAL;  /* DACA0 Calibration Byte 0 */
+    register8_t DACA0GAINCAL;  /* DACA0 Calibration Byte 1 */
+    register8_t DACB0OFFCAL;  /* DACB0 Calibration Byte 0 */
+    register8_t DACB0GAINCAL;  /* DACB0 Calibration Byte 1 */
+    register8_t DACA1OFFCAL;  /* DACA1 Calibration Byte 0 */
+    register8_t DACA1GAINCAL;  /* DACA1 Calibration Byte 1 */
+    register8_t DACB1OFFCAL;  /* DACB1 Calibration Byte 0 */
+    register8_t DACB1GAINCAL;  /* DACB1 Calibration Byte 1 */
+    register8_t reserved_0x38;
+    register8_t reserved_0x39;
+    register8_t reserved_0x3A;
+    register8_t reserved_0x3B;
+    register8_t reserved_0x3C;
+    register8_t reserved_0x3D;
+    register8_t reserved_0x3E;
+    register8_t reserved_0x3F;
+    register8_t reserved_0x40;
+    register8_t reserved_0x41;
+    register8_t reserved_0x42;
+    register8_t reserved_0x43;
+    register8_t reserved_0x44;
+    register8_t reserved_0x45;
+    register8_t reserved_0x46;
+    register8_t reserved_0x47;
+} NVM_PROD_SIGNATURES_t;
+
+
+/*
+--------------------------------------------------------------------------
+SLEEP - Sleep Controller
+--------------------------------------------------------------------------
+*/
+
+/* Sleep Controller */
+typedef struct SLEEP_struct
+{
+    register8_t CTRL;  /* Control Register */
+} SLEEP_t;
+
+/* Sleep Mode */
+typedef enum SLEEP_SMODE_enum
+{
+    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
+    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
+    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
+    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
+    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
+} SLEEP_SMODE_t;
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+/*
+--------------------------------------------------------------------------
+SPI - Serial Peripheral Interface
+--------------------------------------------------------------------------
+*/
+
+/* Serial Peripheral Interface */
+typedef struct SPI_struct
+{
+    register8_t CTRL;  /* Control Register */
+    register8_t INTCTRL;  /* Interrupt Control Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t DATA;  /* Data Register */
+} SPI_t;
+
+/* Interrupt level */
+typedef enum SPI_INTLVL_enum
+{
+    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
+} SPI_INTLVL_t;
+
+/* SPI Mode */
+typedef enum SPI_MODE_enum
+{
+    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
+    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
+    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
+    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
+} SPI_MODE_t;
+
+/* Prescaler setting */
+typedef enum SPI_PRESCALER_enum
+{
+    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
+    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
+    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
+    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
+} SPI_PRESCALER_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 0 */
+typedef struct TC0_struct
+{
+    register8_t CTRLA;  /* Control  Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control register C */
+    register8_t CTRLD;  /* Control Register D */
+    register8_t CTRLE;  /* Control Register E */
+    register8_t reserved_0x05;
+    register8_t INTCTRLA;  /* Interrupt Control Register A */
+    register8_t INTCTRLB;  /* Interrupt Control Register B */
+    register8_t CTRLFCLR;  /* Control Register F Clear */
+    register8_t CTRLFSET;  /* Control Register F Set */
+    register8_t CTRLGCLR;  /* Control Register G Clear */
+    register8_t CTRLGSET;  /* Control Register G Set */
+    register8_t INTFLAGS;  /* Interrupt Flag Register */
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t TEMP;  /* Temporary Register For 16-bit Access */
+    register8_t reserved_0x10;
+    register8_t reserved_0x11;
+    register8_t reserved_0x12;
+    register8_t reserved_0x13;
+    register8_t reserved_0x14;
+    register8_t reserved_0x15;
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    register8_t reserved_0x18;
+    register8_t reserved_0x19;
+    register8_t reserved_0x1A;
+    register8_t reserved_0x1B;
+    register8_t reserved_0x1C;
+    register8_t reserved_0x1D;
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    _WORDREGISTER(CNT);  /* Count */
+    register8_t reserved_0x22;
+    register8_t reserved_0x23;
+    register8_t reserved_0x24;
+    register8_t reserved_0x25;
+    _WORDREGISTER(PER);  /* Period */
+    _WORDREGISTER(CCA);  /* Compare or Capture A */
+    _WORDREGISTER(CCB);  /* Compare or Capture B */
+    _WORDREGISTER(CCC);  /* Compare or Capture C */
+    _WORDREGISTER(CCD);  /* Compare or Capture D */
+    register8_t reserved_0x30;
+    register8_t reserved_0x31;
+    register8_t reserved_0x32;
+    register8_t reserved_0x33;
+    register8_t reserved_0x34;
+    register8_t reserved_0x35;
+    _WORDREGISTER(PERBUF);  /* Period Buffer */
+    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
+    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
+    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
+    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
+} TC0_t;
+
+
+/* 16-bit Timer/Counter 1 */
+typedef struct TC1_struct
+{
+    register8_t CTRLA;  /* Control  Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control register C */
+    register8_t CTRLD;  /* Control Register D */
+    register8_t CTRLE;  /* Control Register E */
+    register8_t reserved_0x05;
+    register8_t INTCTRLA;  /* Interrupt Control Register A */
+    register8_t INTCTRLB;  /* Interrupt Control Register B */
+    register8_t CTRLFCLR;  /* Control Register F Clear */
+    register8_t CTRLFSET;  /* Control Register F Set */
+    register8_t CTRLGCLR;  /* Control Register G Clear */
+    register8_t CTRLGSET;  /* Control Register G Set */
+    register8_t INTFLAGS;  /* Interrupt Flag Register */
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t TEMP;  /* Temporary Register For 16-bit Access */
+    register8_t reserved_0x10;
+    register8_t reserved_0x11;
+    register8_t reserved_0x12;
+    register8_t reserved_0x13;
+    register8_t reserved_0x14;
+    register8_t reserved_0x15;
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    register8_t reserved_0x18;
+    register8_t reserved_0x19;
+    register8_t reserved_0x1A;
+    register8_t reserved_0x1B;
+    register8_t reserved_0x1C;
+    register8_t reserved_0x1D;
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    _WORDREGISTER(CNT);  /* Count */
+    register8_t reserved_0x22;
+    register8_t reserved_0x23;
+    register8_t reserved_0x24;
+    register8_t reserved_0x25;
+    _WORDREGISTER(PER);  /* Period */
+    _WORDREGISTER(CCA);  /* Compare or Capture A */
+    _WORDREGISTER(CCB);  /* Compare or Capture B */
+    register8_t reserved_0x2C;
+    register8_t reserved_0x2D;
+    register8_t reserved_0x2E;
+    register8_t reserved_0x2F;
+    register8_t reserved_0x30;
+    register8_t reserved_0x31;
+    register8_t reserved_0x32;
+    register8_t reserved_0x33;
+    register8_t reserved_0x34;
+    register8_t reserved_0x35;
+    _WORDREGISTER(PERBUF);  /* Period Buffer */
+    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
+    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
+} TC1_t;
+
+/* Byte Mode */
+typedef enum TC_BYTEM_enum
+{
+    TC_BYTEM_NORMAL_gc = (0x00<<0),  /* 16-bit mode */
+    TC_BYTEM_BYTEMODE_gc = (0x01<<0),  /* Timer/Counter operating in byte mode only */
+    TC_BYTEM_SPLITMODE_gc = (0x02<<0),  /* Timer/Counter split into two 8-bit Counters (TC2) */
+} TC_BYTEM_t;
+
+/* Compare or Capture A Interrupt Level */
+typedef enum TC_CCAINTLVL_enum
+{
+    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} TC_CCAINTLVL_t;
+
+/* Compare or Capture B Interrupt Level */
+typedef enum TC_CCBINTLVL_enum
+{
+    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} TC_CCBINTLVL_t;
+
+/* Compare or Capture C Interrupt Level */
+typedef enum TC_CCCINTLVL_enum
+{
+    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
+    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
+    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
+    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
+} TC_CCCINTLVL_t;
+
+/* Compare or Capture D Interrupt Level */
+typedef enum TC_CCDINTLVL_enum
+{
+    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
+    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
+    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
+    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
+} TC_CCDINTLVL_t;
+
+/* Clock Selection */
+typedef enum TC_CLKSEL_enum
+{
+    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
+    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
+    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
+    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
+    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
+    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
+    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
+    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
+    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
+    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
+    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
+    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
+    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
+    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
+    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
+    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
+} TC_CLKSEL_t;
+
+/* Timer/Counter Command */
+typedef enum TC_CMD_enum
+{
+    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
+    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
+    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
+    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
+} TC_CMD_t;
+
+/* Error Interrupt Level */
+typedef enum TC_ERRINTLVL_enum
+{
+    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} TC_ERRINTLVL_t;
+
+/* Event Action */
+typedef enum TC_EVACT_enum
+{
+    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
+    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
+    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
+    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
+    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
+    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
+    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
+} TC_EVACT_t;
+
+/* Event Selection */
+typedef enum TC_EVSEL_enum
+{
+    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
+    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
+    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
+    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
+    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
+    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
+    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
+    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
+    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
+} TC_EVSEL_t;
+
+/* Overflow Interrupt Level */
+typedef enum TC_OVFINTLVL_enum
+{
+    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} TC_OVFINTLVL_t;
+
+/* Waveform Generation Mode */
+typedef enum TC_WGMODE_enum
+{
+    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
+    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
+    TC_WGMODE_SINGLESLOPE_gc = (0x03<<0),  /* Single Slope */
+    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
+    TC_WGMODE_DSTOP_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
+    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
+    TC_WGMODE_DSBOTH_gc = (0x06<<0),  /* Dual Slope, Update on both TOP and BOTTOM */
+    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on both TOP and BOTTOM */
+    TC_WGMODE_DSBOTTOM_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
+    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
+} TC_WGMODE_t;
+
+/*
+--------------------------------------------------------------------------
+TC2 - 16-bit Timer/Counter type 2
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter type 2 */
+typedef struct TC2_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control register C */
+    register8_t reserved_0x03;
+    register8_t CTRLE;  /* Control Register E */
+    register8_t reserved_0x05;
+    register8_t INTCTRLA;  /* Interrupt Control Register A */
+    register8_t INTCTRLB;  /* Interrupt Control Register B */
+    register8_t reserved_0x08;
+    register8_t CTRLF;  /* Control Register F */
+    register8_t reserved_0x0A;
+    register8_t reserved_0x0B;
+    register8_t INTFLAGS;  /* Interrupt Flag Register */
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    register8_t reserved_0x10;
+    register8_t reserved_0x11;
+    register8_t reserved_0x12;
+    register8_t reserved_0x13;
+    register8_t reserved_0x14;
+    register8_t reserved_0x15;
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    register8_t reserved_0x18;
+    register8_t reserved_0x19;
+    register8_t reserved_0x1A;
+    register8_t reserved_0x1B;
+    register8_t reserved_0x1C;
+    register8_t reserved_0x1D;
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    register8_t LCNT;  /* Low Byte Count */
+    register8_t HCNT;  /* High Byte Count */
+    register8_t reserved_0x22;
+    register8_t reserved_0x23;
+    register8_t reserved_0x24;
+    register8_t reserved_0x25;
+    register8_t LPER;  /* Low Byte Period */
+    register8_t HPER;  /* High Byte Period */
+    register8_t LCMPA;  /* Low Byte Compare A */
+    register8_t HCMPA;  /* High Byte Compare A */
+    register8_t LCMPB;  /* Low Byte Compare B */
+    register8_t HCMPB;  /* High Byte Compare B */
+    register8_t LCMPC;  /* Low Byte Compare C */
+    register8_t HCMPC;  /* High Byte Compare C */
+    register8_t LCMPD;  /* Low Byte Compare D */
+    register8_t HCMPD;  /* High Byte Compare D */
+} TC2_t;
+
+/* Byte Mode */
+typedef enum TC2_BYTEM_enum
+{
+    TC2_BYTEM_NORMAL_gc = (0x00<<0),  /* 16-bit mode */
+    TC2_BYTEM_BYTEMODE_gc = (0x01<<0),  /* Timer/Counter operating in byte mode only (TC2) */
+    TC2_BYTEM_SPLITMODE_gc = (0x02<<0),  /* Timer/Counter split into two 8-bit Counters */
+} TC2_BYTEM_t;
+
+/* Clock Selection */
+typedef enum TC2_CLKSEL_enum
+{
+    TC2_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
+    TC2_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
+    TC2_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
+    TC2_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
+    TC2_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
+    TC2_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
+    TC2_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
+    TC2_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
+    TC2_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
+    TC2_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
+    TC2_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
+    TC2_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
+    TC2_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
+    TC2_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
+    TC2_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
+    TC2_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
+} TC2_CLKSEL_t;
+
+/* Timer/Counter Command */
+typedef enum TC2_CMD_enum
+{
+    TC2_CMD_NONE_gc = (0x00<<2),  /* No Command */
+    TC2_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
+    TC2_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
+} TC2_CMD_t;
+
+/* Timer/Counter Command */
+typedef enum TC2_CMDEN_enum
+{
+    TC2_CMDEN_LOW_gc = (0x01<<0),  /* Low Byte Timer/Counter */
+    TC2_CMDEN_HIGH_gc = (0x02<<0),  /* High Byte Timer/Counter */
+    TC2_CMDEN_BOTH_gc = (0x03<<0),  /* Both Low Byte and High Byte Timer/Counters */
+} TC2_CMDEN_t;
+
+/* High Byte Underflow Interrupt Level */
+typedef enum TC2_HUNFINTLVL_enum
+{
+    TC2_HUNFINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    TC2_HUNFINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    TC2_HUNFINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    TC2_HUNFINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} TC2_HUNFINTLVL_t;
+
+/* Low Byte Compare A Interrupt Level */
+typedef enum TC2_LCMPAINTLVL_enum
+{
+    TC2_LCMPAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    TC2_LCMPAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    TC2_LCMPAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    TC2_LCMPAINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} TC2_LCMPAINTLVL_t;
+
+/* Low Byte Compare B Interrupt Level */
+typedef enum TC2_LCMPBINTLVL_enum
+{
+    TC2_LCMPBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    TC2_LCMPBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    TC2_LCMPBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    TC2_LCMPBINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} TC2_LCMPBINTLVL_t;
+
+/* Low Byte Compare C Interrupt Level */
+typedef enum TC2_LCMPCINTLVL_enum
+{
+    TC2_LCMPCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
+    TC2_LCMPCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
+    TC2_LCMPCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
+    TC2_LCMPCINTLVL_HI_gc = (0x03<<4),  /* High Level */
+} TC2_LCMPCINTLVL_t;
+
+/* Low Byte Compare D Interrupt Level */
+typedef enum TC2_LCMPDINTLVL_enum
+{
+    TC2_LCMPDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
+    TC2_LCMPDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
+    TC2_LCMPDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
+    TC2_LCMPDINTLVL_HI_gc = (0x03<<6),  /* High Level */
+} TC2_LCMPDINTLVL_t;
+
+/* Low Byte Underflow Interrupt Level */
+typedef enum TC2_LUNFINTLVL_enum
+{
+    TC2_LUNFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    TC2_LUNFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    TC2_LUNFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    TC2_LUNFINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} TC2_LUNFINTLVL_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/*  */
+typedef struct TWI_MASTER_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control Register C */
+    register8_t STATUS;  /* Status Register */
+    register8_t BAUD;  /* Baud Rate Control Register */
+    register8_t ADDR;  /* Address Register */
+    register8_t DATA;  /* Data Register */
+} TWI_MASTER_t;
+
+
+/*  */
+typedef struct TWI_SLAVE_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t STATUS;  /* Status Register */
+    register8_t ADDR;  /* Address Register */
+    register8_t DATA;  /* Data Register */
+    register8_t ADDRMASK;  /* Address Mask Register */
+} TWI_SLAVE_t;
+
+
+/* Two-Wire Interface */
+typedef struct TWI_struct
+{
+    register8_t CTRL;  /* TWI Common Control Register */
+    TWI_MASTER_t MASTER;  /* TWI master module */
+    TWI_SLAVE_t SLAVE;  /* TWI slave module */
+} TWI_t;
+
+/* Master Bus State */
+typedef enum TWI_MASTER_BUSSTATE_enum
+{
+    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
+    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
+    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
+    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
+} TWI_MASTER_BUSSTATE_t;
+
+/* Master Command */
+typedef enum TWI_MASTER_CMD_enum
+{
+    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
+    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
+    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
+    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
+} TWI_MASTER_CMD_t;
+
+/* Master Interrupt Level */
+typedef enum TWI_MASTER_INTLVL_enum
+{
+    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
+    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
+    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
+    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
+} TWI_MASTER_INTLVL_t;
+
+/* Inactive Timeout */
+typedef enum TWI_MASTER_TIMEOUT_enum
+{
+    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
+    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
+    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
+    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
+} TWI_MASTER_TIMEOUT_t;
+
+/* Slave Command */
+typedef enum TWI_SLAVE_CMD_enum
+{
+    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
+    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
+    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
+} TWI_SLAVE_CMD_t;
+
+/* Slave Interrupt Level */
+typedef enum TWI_SLAVE_INTLVL_enum
+{
+    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
+    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
+    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
+    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
+} TWI_SLAVE_INTLVL_t;
+
+/* SDA Hold Time */
+typedef enum TWI_SDAHOLD_enum
+{
+    TWI_SDAHOLD_OFF_gc = (0x00<<1),  /* SDA Hold Time off */
+    TWI_SDAHOLD_50NS_gc = (0x01<<1),  /* SDA Hold Time 50 ns */
+    TWI_SDAHOLD_300NS_gc = (0x02<<1),  /* SDA Hold Time 300 ns */
+    TWI_SDAHOLD_400NS_gc = (0x03<<1),  /* SDA Hold Time 400 ns */
+} TWI_SDAHOLD_t;
+
+/*
+--------------------------------------------------------------------------
+USART - Universal Asynchronous Receiver-Transmitter
+--------------------------------------------------------------------------
+*/
+
+/* Universal Synchronous/Asynchronous Receiver/Transmitter */
+typedef struct USART_struct
+{
+    register8_t DATA;  /* Data Register */
+    register8_t STATUS;  /* Status Register */
+    register8_t reserved_0x02;
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t CTRLC;  /* Control Register C */
+    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
+    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
+} USART_t;
+
+/* Character Size */
+typedef enum USART_CHSIZE_enum
+{
+    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
+    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
+    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
+    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
+    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
+} USART_CHSIZE_t;
+
+/* Communication Mode */
+typedef enum USART_CMODE_enum
+{
+    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
+    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
+    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
+    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
+} USART_CMODE_t;
+
+/* Data Register Empty Interrupt level */
+typedef enum USART_DREINTLVL_enum
+{
+    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
+    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
+    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
+    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
+} USART_DREINTLVL_t;
+
+/* Parity Mode */
+typedef enum USART_PMODE_enum
+{
+    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
+    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
+    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
+} USART_PMODE_t;
+
+/* Receive Complete Interrupt level */
+typedef enum USART_RXCINTLVL_enum
+{
+    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
+    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
+    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
+    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
+} USART_RXCINTLVL_t;
+
+/* Transmit Complete Interrupt level */
+typedef enum USART_TXCINTLVL_enum
+{
+    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
+    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
+    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
+    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
+} USART_TXCINTLVL_t;
+
+/*
+--------------------------------------------------------------------------
+USB - USB
+--------------------------------------------------------------------------
+*/
+
+/* USB Endpoint */
+typedef struct USB_EP_struct
+{
+    register8_t STATUS;  /* Endpoint Status */
+    register8_t CTRL;  /* Endpoint Control */
+    _WORDREGISTER(CNT);  /* USB Endpoint Counter */
+    _WORDREGISTER(DATAPTR);  /* Data Pointer */
+    _WORDREGISTER(AUXDATA);  /* Auxiliary Data */
+} USB_EP_t;
+
+
+/* Universal Serial Bus */
+typedef struct USB_struct
+{
+    register8_t CTRLA;  /* Control Register A */
+    register8_t CTRLB;  /* Control Register B */
+    register8_t STATUS;  /* Status Register */
+    register8_t ADDR;  /* Address Register */
+    register8_t FIFOWP;  /* FIFO Write Pointer Register */
+    register8_t FIFORP;  /* FIFO Read Pointer Register */
+    _WORDREGISTER(EPPTR);  /* Endpoint Configuration Table Pointer */
+    register8_t INTCTRLA;  /* Interrupt Control Register A */
+    register8_t INTCTRLB;  /* Interrupt Control Register B */
+    register8_t INTFLAGSACLR;  /* Clear Interrupt Flag Register A */
+    register8_t INTFLAGSASET;  /* Set Interrupt Flag Register A */
+    register8_t INTFLAGSBCLR;  /* Clear Interrupt Flag Register B */
+    register8_t INTFLAGSBSET;  /* Set Interrupt Flag Register B */
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
+    register8_t reserved_0x10;
+    register8_t reserved_0x11;
+    register8_t reserved_0x12;
+    register8_t reserved_0x13;
+    register8_t reserved_0x14;
+    register8_t reserved_0x15;
+    register8_t reserved_0x16;
+    register8_t reserved_0x17;
+    register8_t reserved_0x18;
+    register8_t reserved_0x19;
+    register8_t reserved_0x1A;
+    register8_t reserved_0x1B;
+    register8_t reserved_0x1C;
+    register8_t reserved_0x1D;
+    register8_t reserved_0x1E;
+    register8_t reserved_0x1F;
+    register8_t reserved_0x20;
+    register8_t reserved_0x21;
+    register8_t reserved_0x22;
+    register8_t reserved_0x23;
+    register8_t reserved_0x24;
+    register8_t reserved_0x25;
+    register8_t reserved_0x26;
+    register8_t reserved_0x27;
+    register8_t reserved_0x28;
+    register8_t reserved_0x29;
+    register8_t reserved_0x2A;
+    register8_t reserved_0x2B;
+    register8_t reserved_0x2C;
+    register8_t reserved_0x2D;
+    register8_t reserved_0x2E;
+    register8_t reserved_0x2F;
+    register8_t reserved_0x30;
+    register8_t reserved_0x31;
+    register8_t reserved_0x32;
+    register8_t reserved_0x33;
+    register8_t reserved_0x34;
+    register8_t reserved_0x35;
+    register8_t reserved_0x36;
+    register8_t reserved_0x37;
+    register8_t reserved_0x38;
+    register8_t reserved_0x39;
+    register8_t CAL0;  /* Calibration Byte 0 */
+    register8_t CAL1;  /* Calibration Byte 1 */
+} USB_t;
+
+
+/* USB Endpoint Table */
+typedef struct USB_EP_TABLE_struct
+{
+    USB_EP_t EP0OUT;  /* Endpoint 0 */
+    USB_EP_t EP0IN;  /* Endpoint 0 */
+    USB_EP_t EP1OUT;  /* Endpoint 1 */
+    USB_EP_t EP1IN;  /* Endpoint 1 */
+    USB_EP_t EP2OUT;  /* Endpoint 2 */
+    USB_EP_t EP2IN;  /* Endpoint 2 */
+    USB_EP_t EP3OUT;  /* Endpoint 3 */
+    USB_EP_t EP3IN;  /* Endpoint 3 */
+    USB_EP_t EP4OUT;  /* Endpoint 4 */
+    USB_EP_t EP4IN;  /* Endpoint 4 */
+    USB_EP_t EP5OUT;  /* Endpoint 5 */
+    USB_EP_t EP5IN;  /* Endpoint 5 */
+    USB_EP_t EP6OUT;  /* Endpoint 6 */
+    USB_EP_t EP6IN;  /* Endpoint 6 */
+    USB_EP_t EP7OUT;  /* Endpoint 7 */
+    USB_EP_t EP7IN;  /* Endpoint 7 */
+    USB_EP_t EP8OUT;  /* Endpoint 8 */
+    USB_EP_t EP8IN;  /* Endpoint 8 */
+    USB_EP_t EP9OUT;  /* Endpoint 9 */
+    USB_EP_t EP9IN;  /* Endpoint 9 */
+    USB_EP_t EP10OUT;  /* Endpoint 10 */
+    USB_EP_t EP10IN;  /* Endpoint 10 */
+    USB_EP_t EP11OUT;  /* Endpoint 11 */
+    USB_EP_t EP11IN;  /* Endpoint 11 */
+    USB_EP_t EP12OUT;  /* Endpoint 12 */
+    USB_EP_t EP12IN;  /* Endpoint 12 */
+    USB_EP_t EP13OUT;  /* Endpoint 13 */
+    USB_EP_t EP13IN;  /* Endpoint 13 */
+    USB_EP_t EP14OUT;  /* Endpoint 14 */
+    USB_EP_t EP14IN;  /* Endpoint 14 */
+    USB_EP_t EP15OUT;  /* Endpoint 15 */
+    USB_EP_t EP15IN;  /* Endpoint 15 */
+    register8_t reserved_0x100;
+    register8_t reserved_0x101;
+    register8_t reserved_0x102;
+    register8_t reserved_0x103;
+    register8_t reserved_0x104;
+    register8_t reserved_0x105;
+    register8_t reserved_0x106;
+    register8_t reserved_0x107;
+    register8_t reserved_0x108;
+    register8_t reserved_0x109;
+    register8_t reserved_0x10A;
+    register8_t reserved_0x10B;
+    register8_t reserved_0x10C;
+    register8_t reserved_0x10D;
+    register8_t reserved_0x10E;
+    register8_t reserved_0x10F;
+    register8_t FRAMENUML;  /* Frame Number Low Byte */
+    register8_t FRAMENUMH;  /* Frame Number High Byte */
+} USB_EP_TABLE_t;
+
+/* USB Endpoint Buffersize */
+typedef enum USB_EP_BUFSIZE_enum
+{
+    USB_EP_BUFSIZE_8_gc = (0x00<<0),  /* 8 bytes buffer size */
+    USB_EP_BUFSIZE_16_gc = (0x01<<0),  /* 16 bytes buffer size */
+    USB_EP_BUFSIZE_32_gc = (0x02<<0),  /* 32 bytes buffer size */
+    USB_EP_BUFSIZE_64_gc = (0x03<<0),  /* 64 bytes buffer size */
+    USB_EP_BUFSIZE_128_gc = (0x04<<0),  /* 128 bytes buffer size */
+    USB_EP_BUFSIZE_256_gc = (0x05<<0),  /* 256 bytes buffer size */
+    USB_EP_BUFSIZE_512_gc = (0x06<<0),  /* 512 bytes buffer size */
+    USB_EP_BUFSIZE_1023_gc = (0x07<<0),  /* 1023 bytes buffer size */
+} USB_EP_BUFSIZE_t;
+
+/* USB Endpoint Type */
+typedef enum USB_EP_TYPE_enum
+{
+    USB_EP_TYPE_DISABLE_gc = (0x00<<6),  /* Endpoint Disabled */
+    USB_EP_TYPE_CONTROL_gc = (0x01<<6),  /* Control */
+    USB_EP_TYPE_BULK_gc = (0x02<<6),  /* Bulk/Interrupt */
+    USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6),  /* Isochronous */
+} USB_EP_TYPE_t;
+
+/* Interrupt level */
+typedef enum USB_INTLVL_enum
+{
+    USB_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
+    USB_INTLVL_LO_gc = (0x01<<0),  /* Low level */
+    USB_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
+    USB_INTLVL_HI_gc = (0x03<<0),  /* High level */
+} USB_INTLVL_t;
+
+/*
+--------------------------------------------------------------------------
+VPORT - Virtual Ports
+--------------------------------------------------------------------------
+*/
+
+/* Virtual Port */
+typedef struct VPORT_struct
+{
+    register8_t DIR;  /* I/O Port Data Direction */
+    register8_t OUT;  /* I/O Port Output */
+    register8_t IN;  /* I/O Port Input */
+    register8_t INTFLAGS;  /* Interrupt Flag Register */
+} VPORT_t;
+
+
+/*
+--------------------------------------------------------------------------
+WDT - Watch-Dog Timer
+--------------------------------------------------------------------------
+*/
+
+/* Watch-Dog Timer */
+typedef struct WDT_struct
+{
+    register8_t CTRL;  /* Control */
+    register8_t WINCTRL;  /* Windowed Mode Control */
+    register8_t STATUS;  /* Status */
+} WDT_t;
+
+/* Period setting */
+typedef enum WDT_PER_enum
+{
+    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
+    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
+    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
+    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
+    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
+    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
+    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
+    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
+    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
+    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
+    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
+} WDT_PER_t;
+
+/* Closed window period */
+typedef enum WDT_WPER_enum
+{
+    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
+    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
+    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
+    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
+    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
+    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
+    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
+    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
+    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
+    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
+    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
+} WDT_WPER_t;
+
+/*
+--------------------------------------------------------------------------
+XOCD - On-Chip Debug System
+--------------------------------------------------------------------------
+*/
+
+/* On-Chip Debug System */
+typedef struct OCD_struct
+{
+    register8_t OCDR0;  /* OCD Register 0 */
+    register8_t OCDR1;  /* OCD Register 1 */
+} OCD_t;
+
+/*
+==========================================================================
+IO Module Instances. Mapped to memory.
+==========================================================================
+*/
+
+#define VPORT0              (*(VPORT_t *) 0x0010) /* Virtual Port */
+#define VPORT1              (*(VPORT_t *) 0x0014) /* Virtual Port */
+#define VPORT2              (*(VPORT_t *) 0x0018) /* Virtual Port */
+#define VPORT3              (*(VPORT_t *) 0x001C) /* Virtual Port */
+#define OCD                   (*(OCD_t *) 0x002E) /* On-Chip Debug System */
+#define CLK                   (*(CLK_t *) 0x0040) /* Clock System */
+#define SLEEP               (*(SLEEP_t *) 0x0048) /* Sleep Controller */
+#define OSC                   (*(OSC_t *) 0x0050) /* Oscillator */
+#define DFLLRC32M            (*(DFLL_t *) 0x0060) /* DFLL */
+#define DFLLRC2M             (*(DFLL_t *) 0x0068) /* DFLL */
+#define PR                     (*(PR_t *) 0x0070) /* Power Reduction */
+#define RST                   (*(RST_t *) 0x0078) /* Reset */
+#define WDT                   (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
+#define MCU                   (*(MCU_t *) 0x0090) /* MCU Control */
+#define PMIC                 (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
+#define PORTCFG           (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
+#define AES                   (*(AES_t *) 0x00C0) /* AES Module */
+#define CRC                   (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
+#define DMA                   (*(DMA_t *) 0x0100) /* DMA Controller */
+#define EVSYS               (*(EVSYS_t *) 0x0180) /* Event System */
+#define NVM                   (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
+#define ADCA                  (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
+#define ADCB                  (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
+#define DACB                  (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
+#define ACA                    (*(AC_t *) 0x0380) /* Analog Comparator */
+#define ACB                    (*(AC_t *) 0x0390) /* Analog Comparator */
+#define RTC                   (*(RTC_t *) 0x0400) /* Real-Time Counter */
+#define TWIC                  (*(TWI_t *) 0x0480) /* Two-Wire Interface */
+#define TWIE                  (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
+#define USB                   (*(USB_t *) 0x04C0) /* Universal Serial Bus */
+#define PORTA                (*(PORT_t *) 0x0600) /* I/O Ports */
+#define PORTB                (*(PORT_t *) 0x0620) /* I/O Ports */
+#define PORTC                (*(PORT_t *) 0x0640) /* I/O Ports */
+#define PORTD                (*(PORT_t *) 0x0660) /* I/O Ports */
+#define PORTE                (*(PORT_t *) 0x0680) /* I/O Ports */
+#define PORTF                (*(PORT_t *) 0x06A0) /* I/O Ports */
+#define PORTR                (*(PORT_t *) 0x07E0) /* I/O Ports */
+#define TCC0                  (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
+#define TCC2                  (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
+#define TCC1                  (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
+#define AWEXC                (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
+#define HIRESC              (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
+#define USARTC0             (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTC1             (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define SPIC                  (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
+#define IRCOM               (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
+#define TCD0                  (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
+#define TCD2                  (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
+#define TCD1                  (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
+#define HIRESD              (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
+#define USARTD0             (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTD1             (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define SPID                  (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
+#define TCE0                  (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
+#define TCE2                  (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
+#define TCE1                  (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */
+#define AWEXE                (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */
+#define HIRESE              (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
+#define USARTE0             (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTE1             (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define SPIE                  (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */
+#define TCF0                  (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
+#define TCF2                  (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
+#define HIRESF              (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */
+#define USARTF0             (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
+
+#endif /* !defined (__ASSEMBLER__) */
+
+
+/* ========== Flattened fully qualified IO register names ========== */
+
+
+/* GPIO - General Purpose IO Registers */
+#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
+#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
+#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
+#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
+#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
+#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
+#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
+#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
+#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
+#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
+#define GPIO_GPIORA  _SFR_MEM8(0x000A)
+#define GPIO_GPIORB  _SFR_MEM8(0x000B)
+#define GPIO_GPIORC  _SFR_MEM8(0x000C)
+#define GPIO_GPIORD  _SFR_MEM8(0x000D)
+#define GPIO_GPIORE  _SFR_MEM8(0x000E)
+#define GPIO_GPIORF  _SFR_MEM8(0x000F)
+
+
+/* Deprecated */
+#define GPIO_GPIO0  _SFR_MEM8(0x0000)
+#define GPIO_GPIO1  _SFR_MEM8(0x0001)
+#define GPIO_GPIO2  _SFR_MEM8(0x0002)
+#define GPIO_GPIO3  _SFR_MEM8(0x0003)
+#define GPIO_GPIO4  _SFR_MEM8(0x0004)
+#define GPIO_GPIO5  _SFR_MEM8(0x0005)
+#define GPIO_GPIO6  _SFR_MEM8(0x0006)
+#define GPIO_GPIO7  _SFR_MEM8(0x0007)
+#define GPIO_GPIO8  _SFR_MEM8(0x0008)
+#define GPIO_GPIO9  _SFR_MEM8(0x0009)
+#define GPIO_GPIOA  _SFR_MEM8(0x000A)
+#define GPIO_GPIOB  _SFR_MEM8(0x000B)
+#define GPIO_GPIOC  _SFR_MEM8(0x000C)
+#define GPIO_GPIOD  _SFR_MEM8(0x000D)
+#define GPIO_GPIOE  _SFR_MEM8(0x000E)
+#define GPIO_GPIOF  _SFR_MEM8(0x000F)
+
+
+/* NVM_FUSES (FUSE) - Fuses */
+#define FUSE_FUSEBYTE0  _SFR_MEM8(0x0000)
+#define FUSE_FUSEBYTE1  _SFR_MEM8(0x0001)
+#define FUSE_FUSEBYTE2  _SFR_MEM8(0x0002)
+#define FUSE_FUSEBYTE4  _SFR_MEM8(0x0004)
+#define FUSE_FUSEBYTE5  _SFR_MEM8(0x0005)
+
+
+/* NVM_LOCKBITS (LOCKBIT) - Lock Bits */
+#define LOCKBIT_LOCKBITS  _SFR_MEM8(0x0000)
+
+
+/* NVM_PROD_SIGNATURES (PROD_SIGNATURES) - Production Signatures */
+#define PRODSIGNATURES_RCOSC2M  _SFR_MEM8(0x0000)
+#define PRODSIGNATURES_RCOSC2MA  _SFR_MEM8(0x0001)
+#define PRODSIGNATURES_RCOSC32K  _SFR_MEM8(0x0002)
+#define PRODSIGNATURES_RCOSC32M  _SFR_MEM8(0x0003)
+#define PRODSIGNATURES_RCOSC32MA  _SFR_MEM8(0x0004)
+#define PRODSIGNATURES_LOTNUM0  _SFR_MEM8(0x0008)
+#define PRODSIGNATURES_LOTNUM1  _SFR_MEM8(0x0009)
+#define PRODSIGNATURES_LOTNUM2  _SFR_MEM8(0x000A)
+#define PRODSIGNATURES_LOTNUM3  _SFR_MEM8(0x000B)
+#define PRODSIGNATURES_LOTNUM4  _SFR_MEM8(0x000C)
+#define PRODSIGNATURES_LOTNUM5  _SFR_MEM8(0x000D)
+#define PRODSIGNATURES_WAFNUM  _SFR_MEM8(0x0010)
+#define PRODSIGNATURES_COORDX0  _SFR_MEM8(0x0012)
+#define PRODSIGNATURES_COORDX1  _SFR_MEM8(0x0013)
+#define PRODSIGNATURES_COORDY0  _SFR_MEM8(0x0014)
+#define PRODSIGNATURES_COORDY1  _SFR_MEM8(0x0015)
+#define PRODSIGNATURES_USBCAL0  _SFR_MEM8(0x001A)
+#define PRODSIGNATURES_USBCAL1  _SFR_MEM8(0x001B)
+#define PRODSIGNATURES_USBRCOSC  _SFR_MEM8(0x001C)
+#define PRODSIGNATURES_USBRCOSCA  _SFR_MEM8(0x001D)
+#define PRODSIGNATURES_ADCACAL0  _SFR_MEM8(0x0020)
+#define PRODSIGNATURES_ADCACAL1  _SFR_MEM8(0x0021)
+#define PRODSIGNATURES_ADCBCAL0  _SFR_MEM8(0x0024)
+#define PRODSIGNATURES_ADCBCAL1  _SFR_MEM8(0x0025)
+#define PRODSIGNATURES_TEMPSENSE0  _SFR_MEM8(0x002E)
+#define PRODSIGNATURES_TEMPSENSE1  _SFR_MEM8(0x002F)
+#define PRODSIGNATURES_DACA0OFFCAL  _SFR_MEM8(0x0030)
+#define PRODSIGNATURES_DACA0GAINCAL  _SFR_MEM8(0x0031)
+#define PRODSIGNATURES_DACB0OFFCAL  _SFR_MEM8(0x0032)
+#define PRODSIGNATURES_DACB0GAINCAL  _SFR_MEM8(0x0033)
+#define PRODSIGNATURES_DACA1OFFCAL  _SFR_MEM8(0x0034)
+#define PRODSIGNATURES_DACA1GAINCAL  _SFR_MEM8(0x0035)
+#define PRODSIGNATURES_DACB1OFFCAL  _SFR_MEM8(0x0036)
+#define PRODSIGNATURES_DACB1GAINCAL  _SFR_MEM8(0x0037)
+
+
+/* VPORT (VPORT0) - Virtual Port */
+#define VPORT0_DIR  _SFR_MEM8(0x0010)
+#define VPORT0_OUT  _SFR_MEM8(0x0011)
+#define VPORT0_IN  _SFR_MEM8(0x0012)
+#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
+
+
+/* VPORT (VPORT1) - Virtual Port */
+#define VPORT1_DIR  _SFR_MEM8(0x0014)
+#define VPORT1_OUT  _SFR_MEM8(0x0015)
+#define VPORT1_IN  _SFR_MEM8(0x0016)
+#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
+
+
+/* VPORT (VPORT2) - Virtual Port */
+#define VPORT2_DIR  _SFR_MEM8(0x0018)
+#define VPORT2_OUT  _SFR_MEM8(0x0019)
+#define VPORT2_IN  _SFR_MEM8(0x001A)
+#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
+
+
+/* VPORT (VPORT3) - Virtual Port */
+#define VPORT3_DIR  _SFR_MEM8(0x001C)
+#define VPORT3_OUT  _SFR_MEM8(0x001D)
+#define VPORT3_IN  _SFR_MEM8(0x001E)
+#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
+
+
+/* OCD - On-Chip Debug System */
+#define OCD_OCDR0  _SFR_MEM8(0x002E)
+#define OCD_OCDR1  _SFR_MEM8(0x002F)
+
+
+/* CPU - CPU registers */
+#define CPU_CCP  _SFR_MEM8(0x0034)
+#define CPU_RAMPD  _SFR_MEM8(0x0038)
+#define CPU_RAMPX  _SFR_MEM8(0x0039)
+#define CPU_RAMPY  _SFR_MEM8(0x003A)
+#define CPU_RAMPZ  _SFR_MEM8(0x003B)
+#define CPU_EIND  _SFR_MEM8(0x003C)
+#define CPU_SPL  _SFR_MEM8(0x003D)
+#define CPU_SPH  _SFR_MEM8(0x003E)
+#define CPU_SREG  _SFR_MEM8(0x003F)
+
+
+/* CLK - Clock System */
+#define CLK_CTRL  _SFR_MEM8(0x0040)
+#define CLK_PSCTRL  _SFR_MEM8(0x0041)
+#define CLK_LOCK  _SFR_MEM8(0x0042)
+#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
+#define CLK_USBCTRL  _SFR_MEM8(0x0044)
+
+
+/* SLEEP - Sleep Controller */
+#define SLEEP_CTRL  _SFR_MEM8(0x0048)
+
+
+/* OSC - Oscillator */
+#define OSC_CTRL  _SFR_MEM8(0x0050)
+#define OSC_STATUS  _SFR_MEM8(0x0051)
+#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
+#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
+#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
+#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
+#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
+
+
+/* DFLL (DFLLRC32M) - DFLL */
+#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
+#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
+#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
+#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
+#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
+#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
+
+
+/* DFLL (DFLLRC2M) - DFLL */
+#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
+#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
+#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
+#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
+#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
+#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
+
+
+/* PR - Power Reduction */
+#define PR_PRGEN  _SFR_MEM8(0x0070)
+#define PR_PRPA  _SFR_MEM8(0x0071)
+#define PR_PRPB  _SFR_MEM8(0x0072)
+#define PR_PRPC  _SFR_MEM8(0x0073)
+#define PR_PRPD  _SFR_MEM8(0x0074)
+#define PR_PRPE  _SFR_MEM8(0x0075)
+#define PR_PRPF  _SFR_MEM8(0x0076)
+
+
+/* RST - Reset */
+#define RST_STATUS  _SFR_MEM8(0x0078)
+#define RST_CTRL  _SFR_MEM8(0x0079)
+
+
+/* WDT - Watch-Dog Timer */
+#define WDT_CTRL  _SFR_MEM8(0x0080)
+#define WDT_WINCTRL  _SFR_MEM8(0x0081)
+#define WDT_STATUS  _SFR_MEM8(0x0082)
+
+
+/* MCU - MCU Control */
+#define MCU_DEVID0  _SFR_MEM8(0x0090)
+#define MCU_DEVID1  _SFR_MEM8(0x0091)
+#define MCU_DEVID2  _SFR_MEM8(0x0092)
+#define MCU_REVID  _SFR_MEM8(0x0093)
+#define MCU_JTAGUID  _SFR_MEM8(0x0094)
+#define MCU_MCUCR  _SFR_MEM8(0x0096)
+#define MCU_ANAINIT  _SFR_MEM8(0x0097)
+#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
+#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
+
+
+/* PMIC - Programmable Multi-level Interrupt Controller */
+#define PMIC_STATUS  _SFR_MEM8(0x00A0)
+#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
+#define PMIC_CTRL  _SFR_MEM8(0x00A2)
+
+
+/* PORTCFG - I/O port Configuration */
+#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
+#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
+#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
+#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
+#define PORTCFG_EVOUTSEL  _SFR_MEM8(0x00B6)
+
+
+/* AES - AES Module */
+#define AES_CTRL  _SFR_MEM8(0x00C0)
+#define AES_STATUS  _SFR_MEM8(0x00C1)
+#define AES_STATE  _SFR_MEM8(0x00C2)
+#define AES_KEY  _SFR_MEM8(0x00C3)
+#define AES_INTCTRL  _SFR_MEM8(0x00C4)
+
+
+/* CRC - Cyclic Redundancy Checker */
+#define CRC_CTRL  _SFR_MEM8(0x00D0)
+#define CRC_STATUS  _SFR_MEM8(0x00D1)
+#define CRC_DATAIN  _SFR_MEM8(0x00D3)
+#define CRC_CHECKSUM0  _SFR_MEM8(0x00D4)
+#define CRC_CHECKSUM1  _SFR_MEM8(0x00D5)
+#define CRC_CHECKSUM2  _SFR_MEM8(0x00D6)
+#define CRC_CHECKSUM3  _SFR_MEM8(0x00D7)
+
+
+/* DMA - DMA Controller */
+#define DMA_CTRL  _SFR_MEM8(0x0100)
+#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
+#define DMA_STATUS  _SFR_MEM8(0x0104)
+#define DMA_TEMP  _SFR_MEM16(0x0106)
+#define DMA_TEMPL  _SFR_MEM8(0x0106)
+#define DMA_TEMPH  _SFR_MEM8(0x0107)
+#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
+#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
+#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
+#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
+#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
+#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
+#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
+#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
+#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
+#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
+#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
+#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
+
+
+#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
+#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
+#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
+#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
+#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
+#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
+#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
+#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
+#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
+#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
+#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
+#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
+
+
+#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
+#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
+#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
+#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
+#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
+#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
+#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
+#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
+#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
+#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
+#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
+#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
+
+
+#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
+#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
+#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
+#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
+#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
+#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
+#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
+#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
+#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
+#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
+#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
+#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
+
+
+
+
+/* EVSYS - Event System */
+#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
+#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
+#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
+#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
+#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
+#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
+#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
+#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
+#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
+#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
+#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
+#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
+#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
+#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
+#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
+#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
+#define EVSYS_STROBE  _SFR_MEM8(0x0190)
+#define EVSYS_DATA  _SFR_MEM8(0x0191)
+
+
+/* NVM - Non-volatile Memory Controller */
+#define NVM_ADDR0  _SFR_MEM8(0x01C0)
+#define NVM_ADDR1  _SFR_MEM8(0x01C1)
+#define NVM_ADDR2  _SFR_MEM8(0x01C2)
+#define NVM_DATA0  _SFR_MEM8(0x01C4)
+#define NVM_DATA1  _SFR_MEM8(0x01C5)
+#define NVM_DATA2  _SFR_MEM8(0x01C6)
+#define NVM_CMD  _SFR_MEM8(0x01CA)
+#define NVM_CTRLA  _SFR_MEM8(0x01CB)
+#define NVM_CTRLB  _SFR_MEM8(0x01CC)
+#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
+#define NVM_STATUS  _SFR_MEM8(0x01CF)
+#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
+
+
+/* ADC (ADCA) - Analog-to-Digital Converter */
+#define ADCA_CTRLA  _SFR_MEM8(0x0200)
+#define ADCA_CTRLB  _SFR_MEM8(0x0201)
+#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
+#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
+#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
+#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
+#define ADCA_TEMP  _SFR_MEM8(0x0207)
+#define ADCA_CAL  _SFR_MEM16(0x020C)
+#define ADCA_CALL  _SFR_MEM8(0x020C)
+#define ADCA_CALH  _SFR_MEM8(0x020D)
+#define ADCA_CH0RES  _SFR_MEM16(0x0210)
+#define ADCA_CH0RESL  _SFR_MEM8(0x0210)
+#define ADCA_CH0RESH  _SFR_MEM8(0x0211)
+#define ADCA_CH1RES  _SFR_MEM16(0x0212)
+#define ADCA_CH1RESL  _SFR_MEM8(0x0212)
+#define ADCA_CH1RESH  _SFR_MEM8(0x0213)
+#define ADCA_CH2RES  _SFR_MEM16(0x0214)
+#define ADCA_CH2RESL  _SFR_MEM8(0x0214)
+#define ADCA_CH2RESH  _SFR_MEM8(0x0215)
+#define ADCA_CH3RES  _SFR_MEM16(0x0216)
+#define ADCA_CH3RESL  _SFR_MEM8(0x0216)
+#define ADCA_CH3RESH  _SFR_MEM8(0x0217)
+#define ADCA_CMP  _SFR_MEM16(0x0218)
+#define ADCA_CMPL  _SFR_MEM8(0x0218)
+#define ADCA_CMPH  _SFR_MEM8(0x0219)
+#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
+#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
+#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
+#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
+#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
+#define ADCA_CH0_SCAN  _SFR_MEM8(0x0226)
+
+
+#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
+#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
+#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
+#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
+#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
+#define ADCA_CH1_SCAN  _SFR_MEM8(0x022E)
+
+
+#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
+#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
+#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
+#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
+#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
+#define ADCA_CH2_SCAN  _SFR_MEM8(0x0236)
+
+
+#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
+#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
+#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
+#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
+#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
+#define ADCA_CH3_SCAN  _SFR_MEM8(0x023E)
+
+
+
+
+/* ADC (ADCB) - Analog-to-Digital Converter */
+#define ADCB_CTRLA  _SFR_MEM8(0x0240)
+#define ADCB_CTRLB  _SFR_MEM8(0x0241)
+#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
+#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
+#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
+#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
+#define ADCB_TEMP  _SFR_MEM8(0x0247)
+#define ADCB_CAL  _SFR_MEM16(0x024C)
+#define ADCB_CALL  _SFR_MEM8(0x024C)
+#define ADCB_CALH  _SFR_MEM8(0x024D)
+#define ADCB_CH0RES  _SFR_MEM16(0x0250)
+#define ADCB_CH0RESL  _SFR_MEM8(0x0250)
+#define ADCB_CH0RESH  _SFR_MEM8(0x0251)
+#define ADCB_CH1RES  _SFR_MEM16(0x0252)
+#define ADCB_CH1RESL  _SFR_MEM8(0x0252)
+#define ADCB_CH1RESH  _SFR_MEM8(0x0253)
+#define ADCB_CH2RES  _SFR_MEM16(0x0254)
+#define ADCB_CH2RESL  _SFR_MEM8(0x0254)
+#define ADCB_CH2RESH  _SFR_MEM8(0x0255)
+#define ADCB_CH3RES  _SFR_MEM16(0x0256)
+#define ADCB_CH3RESL  _SFR_MEM8(0x0256)
+#define ADCB_CH3RESH  _SFR_MEM8(0x0257)
+#define ADCB_CMP  _SFR_MEM16(0x0258)
+#define ADCB_CMPL  _SFR_MEM8(0x0258)
+#define ADCB_CMPH  _SFR_MEM8(0x0259)
+#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
+#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
+#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
+#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
+#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
+#define ADCB_CH0_SCAN  _SFR_MEM8(0x0266)
+
+
+#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
+#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
+#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
+#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
+#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
+#define ADCB_CH1_SCAN  _SFR_MEM8(0x026E)
+
+
+#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
+#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
+#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
+#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
+#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
+#define ADCB_CH2_SCAN  _SFR_MEM8(0x0276)
+
+
+#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
+#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
+#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
+#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
+#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
+#define ADCB_CH3_SCAN  _SFR_MEM8(0x027E)
+
+
+
+
+/* DAC (DACB) - Digital-to-Analog Converter */
+#define DACB_CTRLA  _SFR_MEM8(0x0320)
+#define DACB_CTRLB  _SFR_MEM8(0x0321)
+#define DACB_CTRLC  _SFR_MEM8(0x0322)
+#define DACB_EVCTRL  _SFR_MEM8(0x0323)
+#define DACB_STATUS  _SFR_MEM8(0x0325)
+#define DACB_CH0GAINCAL  _SFR_MEM8(0x0328)
+#define DACB_CH0OFFSETCAL  _SFR_MEM8(0x0329)
+#define DACB_CH1GAINCAL  _SFR_MEM8(0x032A)
+#define DACB_CH1OFFSETCAL  _SFR_MEM8(0x032B)
+#define DACB_CH0DATA  _SFR_MEM16(0x0338)
+#define DACB_CH0DATAL  _SFR_MEM8(0x0338)
+#define DACB_CH0DATAH  _SFR_MEM8(0x0339)
+#define DACB_CH1DATA  _SFR_MEM16(0x033A)
+#define DACB_CH1DATAL  _SFR_MEM8(0x033A)
+#define DACB_CH1DATAH  _SFR_MEM8(0x033B)
+
+
+/* AC (ACA) - Analog Comparator */
+#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
+#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
+#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
+#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
+#define ACA_CTRLA  _SFR_MEM8(0x0384)
+#define ACA_CTRLB  _SFR_MEM8(0x0385)
+#define ACA_WINCTRL  _SFR_MEM8(0x0386)
+#define ACA_STATUS  _SFR_MEM8(0x0387)
+#define ACA_CURRCTRL  _SFR_MEM8(0x0388)
+#define ACA_CURRCALIB  _SFR_MEM8(0x0389)
+
+
+/* AC (ACB) - Analog Comparator */
+#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
+#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
+#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
+#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
+#define ACB_CTRLA  _SFR_MEM8(0x0394)
+#define ACB_CTRLB  _SFR_MEM8(0x0395)
+#define ACB_WINCTRL  _SFR_MEM8(0x0396)
+#define ACB_STATUS  _SFR_MEM8(0x0397)
+#define ACB_CURRCTRL  _SFR_MEM8(0x0398)
+#define ACB_CURRCALIB  _SFR_MEM8(0x0399)
+
+
+/* RTC - Real-Time Counter */
+#define RTC_CTRL  _SFR_MEM8(0x0400)
+#define RTC_STATUS  _SFR_MEM8(0x0401)
+#define RTC_INTCTRL  _SFR_MEM8(0x0402)
+#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
+#define RTC_TEMP  _SFR_MEM8(0x0404)
+#define RTC_CNT  _SFR_MEM16(0x0408)
+#define RTC_CNTL  _SFR_MEM8(0x0408)
+#define RTC_CNTH  _SFR_MEM8(0x0409)
+#define RTC_PER  _SFR_MEM16(0x040A)
+#define RTC_PERL  _SFR_MEM8(0x040A)
+#define RTC_PERH  _SFR_MEM8(0x040B)
+#define RTC_COMP  _SFR_MEM16(0x040C)
+#define RTC_COMPL  _SFR_MEM8(0x040C)
+#define RTC_COMPH  _SFR_MEM8(0x040D)
+
+
+/* TWI (TWIC) - Two-Wire Interface */
+#define TWIC_CTRL  _SFR_MEM8(0x0480)
+#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
+#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
+#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
+#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
+#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
+#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
+#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
+
+
+#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
+#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
+#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
+#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
+#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
+
+
+
+
+/* TWI (TWIE) - Two-Wire Interface */
+#define TWIE_CTRL  _SFR_MEM8(0x04A0)
+#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
+#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
+#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
+#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
+#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
+#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
+#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
+
+
+#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
+#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
+#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
+#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
+#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
+#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
+
+
+
+
+/* USB - Universal Serial Bus */
+#define USB_CTRLA  _SFR_MEM8(0x04C0)
+#define USB_CTRLB  _SFR_MEM8(0x04C1)
+#define USB_STATUS  _SFR_MEM8(0x04C2)
+#define USB_ADDR  _SFR_MEM8(0x04C3)
+#define USB_FIFOWP  _SFR_MEM8(0x04C4)
+#define USB_FIFORP  _SFR_MEM8(0x04C5)
+#define USB_EPPTR  _SFR_MEM16(0x04C6)
+#define USB_EPPTRL  _SFR_MEM8(0x04C6)
+#define USB_EPPTRH  _SFR_MEM8(0x04C7)
+#define USB_INTCTRLA  _SFR_MEM8(0x04C8)
+#define USB_INTCTRLB  _SFR_MEM8(0x04C9)
+#define USB_INTFLAGSACLR  _SFR_MEM8(0x04CA)
+#define USB_INTFLAGSASET  _SFR_MEM8(0x04CB)
+#define USB_INTFLAGSBCLR  _SFR_MEM8(0x04CC)
+#define USB_INTFLAGSBSET  _SFR_MEM8(0x04CD)
+#define USB_CAL0  _SFR_MEM8(0x04FA)
+#define USB_CAL1  _SFR_MEM8(0x04FB)
+
+
+/* PORT (PORTA) - I/O Ports */
+#define PORTA_DIR  _SFR_MEM8(0x0600)
+#define PORTA_DIRSET  _SFR_MEM8(0x0601)
+#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
+#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
+#define PORTA_OUT  _SFR_MEM8(0x0604)
+#define PORTA_OUTSET  _SFR_MEM8(0x0605)
+#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
+#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
+#define PORTA_IN  _SFR_MEM8(0x0608)
+#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
+#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
+#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
+#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
+#define PORTA_REMAP  _SFR_MEM8(0x060E)
+#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
+#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
+#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
+#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
+#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
+#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
+#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
+#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
+
+
+/* PORT (PORTB) - I/O Ports */
+#define PORTB_DIR  _SFR_MEM8(0x0620)
+#define PORTB_DIRSET  _SFR_MEM8(0x0621)
+#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
+#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
+#define PORTB_OUT  _SFR_MEM8(0x0624)
+#define PORTB_OUTSET  _SFR_MEM8(0x0625)
+#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
+#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
+#define PORTB_IN  _SFR_MEM8(0x0628)
+#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
+#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
+#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
+#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
+#define PORTB_REMAP  _SFR_MEM8(0x062E)
+#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
+#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
+#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
+#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
+#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
+#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
+#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
+#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
+
+
+/* PORT (PORTC) - I/O Ports */
+#define PORTC_DIR  _SFR_MEM8(0x0640)
+#define PORTC_DIRSET  _SFR_MEM8(0x0641)
+#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
+#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
+#define PORTC_OUT  _SFR_MEM8(0x0644)
+#define PORTC_OUTSET  _SFR_MEM8(0x0645)
+#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
+#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
+#define PORTC_IN  _SFR_MEM8(0x0648)
+#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
+#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
+#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
+#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
+#define PORTC_REMAP  _SFR_MEM8(0x064E)
+#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
+#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
+#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
+#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
+#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
+#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
+#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
+#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
+
+
+/* PORT (PORTD) - I/O Ports */
+#define PORTD_DIR  _SFR_MEM8(0x0660)
+#define PORTD_DIRSET  _SFR_MEM8(0x0661)
+#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
+#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
+#define PORTD_OUT  _SFR_MEM8(0x0664)
+#define PORTD_OUTSET  _SFR_MEM8(0x0665)
+#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
+#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
+#define PORTD_IN  _SFR_MEM8(0x0668)
+#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
+#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
+#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
+#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
+#define PORTD_REMAP  _SFR_MEM8(0x066E)
+#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
+#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
+#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
+#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
+#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
+#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
+#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
+#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
+
+
+/* PORT (PORTE) - I/O Ports */
+#define PORTE_DIR  _SFR_MEM8(0x0680)
+#define PORTE_DIRSET  _SFR_MEM8(0x0681)
+#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
+#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
+#define PORTE_OUT  _SFR_MEM8(0x0684)
+#define PORTE_OUTSET  _SFR_MEM8(0x0685)
+#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
+#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
+#define PORTE_IN  _SFR_MEM8(0x0688)
+#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
+#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
+#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
+#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
+#define PORTE_REMAP  _SFR_MEM8(0x068E)
+#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
+#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
+#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
+#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
+#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
+#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
+#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
+#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
+
+
+/* PORT (PORTF) - I/O Ports */
+#define PORTF_DIR  _SFR_MEM8(0x06A0)
+#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
+#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
+#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
+#define PORTF_OUT  _SFR_MEM8(0x06A4)
+#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
+#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
+#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
+#define PORTF_IN  _SFR_MEM8(0x06A8)
+#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
+#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
+#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
+#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
+#define PORTF_REMAP  _SFR_MEM8(0x06AE)
+#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
+#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
+#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
+#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
+#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
+#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
+#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
+#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
+
+
+/* PORT (PORTR) - I/O Ports */
+#define PORTR_DIR  _SFR_MEM8(0x07E0)
+#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
+#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
+#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
+#define PORTR_OUT  _SFR_MEM8(0x07E4)
+#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
+#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
+#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
+#define PORTR_IN  _SFR_MEM8(0x07E8)
+#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
+#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
+#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
+#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
+#define PORTR_REMAP  _SFR_MEM8(0x07EE)
+#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
+#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
+#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
+#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
+#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
+#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
+#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
+#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
+
+
+/* TC0 (TCC0) - 16-bit Timer/Counter 0 */
+#define TCC0_CTRLA  _SFR_MEM8(0x0800)
+#define TCC0_CTRLB  _SFR_MEM8(0x0801)
+#define TCC0_CTRLC  _SFR_MEM8(0x0802)
+#define TCC0_CTRLD  _SFR_MEM8(0x0803)
+#define TCC0_CTRLE  _SFR_MEM8(0x0804)
+#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
+#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
+#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
+#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
+#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
+#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
+#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
+#define TCC0_TEMP  _SFR_MEM8(0x080F)
+#define TCC0_CNT  _SFR_MEM16(0x0820)
+#define TCC0_CNTL  _SFR_MEM8(0x0820)
+#define TCC0_CNTH  _SFR_MEM8(0x0821)
+#define TCC0_PER  _SFR_MEM16(0x0826)
+#define TCC0_PERL  _SFR_MEM8(0x0826)
+#define TCC0_PERH  _SFR_MEM8(0x0827)
+#define TCC0_CCA  _SFR_MEM16(0x0828)
+#define TCC0_CCAL  _SFR_MEM8(0x0828)
+#define TCC0_CCAH  _SFR_MEM8(0x0829)
+#define TCC0_CCB  _SFR_MEM16(0x082A)
+#define TCC0_CCBL  _SFR_MEM8(0x082A)
+#define TCC0_CCBH  _SFR_MEM8(0x082B)
+#define TCC0_CCC  _SFR_MEM16(0x082C)
+#define TCC0_CCCL  _SFR_MEM8(0x082C)
+#define TCC0_CCCH  _SFR_MEM8(0x082D)
+#define TCC0_CCD  _SFR_MEM16(0x082E)
+#define TCC0_CCDL  _SFR_MEM8(0x082E)
+#define TCC0_CCDH  _SFR_MEM8(0x082F)
+#define TCC0_PERBUF  _SFR_MEM16(0x0836)
+#define TCC0_PERBUFL  _SFR_MEM8(0x0836)
+#define TCC0_PERBUFH  _SFR_MEM8(0x0837)
+#define TCC0_CCABUF  _SFR_MEM16(0x0838)
+#define TCC0_CCABUFL  _SFR_MEM8(0x0838)
+#define TCC0_CCABUFH  _SFR_MEM8(0x0839)
+#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
+#define TCC0_CCBBUFL  _SFR_MEM8(0x083A)
+#define TCC0_CCBBUFH  _SFR_MEM8(0x083B)
+#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
+#define TCC0_CCCBUFL  _SFR_MEM8(0x083C)
+#define TCC0_CCCBUFH  _SFR_MEM8(0x083D)
+#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
+#define TCC0_CCDBUFL  _SFR_MEM8(0x083E)
+#define TCC0_CCDBUFH  _SFR_MEM8(0x083F)
+
+
+/* TC2 (TCC2) - 16-bit Timer/Counter type 2 */
+#define TCC2_CTRLA  _SFR_MEM8(0x0800)
+#define TCC2_CTRLB  _SFR_MEM8(0x0801)
+#define TCC2_CTRLC  _SFR_MEM8(0x0802)
+#define TCC2_CTRLE  _SFR_MEM8(0x0804)
+#define TCC2_INTCTRLA  _SFR_MEM8(0x0806)
+#define TCC2_INTCTRLB  _SFR_MEM8(0x0807)
+#define TCC2_CTRLF  _SFR_MEM8(0x0809)
+#define TCC2_INTFLAGS  _SFR_MEM8(0x080C)
+#define TCC2_LCNT  _SFR_MEM8(0x0820)
+#define TCC2_HCNT  _SFR_MEM8(0x0821)
+#define TCC2_LPER  _SFR_MEM8(0x0826)
+#define TCC2_HPER  _SFR_MEM8(0x0827)
+#define TCC2_LCMPA  _SFR_MEM8(0x0828)
+#define TCC2_HCMPA  _SFR_MEM8(0x0829)
+#define TCC2_LCMPB  _SFR_MEM8(0x082A)
+#define TCC2_HCMPB  _SFR_MEM8(0x082B)
+#define TCC2_LCMPC  _SFR_MEM8(0x082C)
+#define TCC2_HCMPC  _SFR_MEM8(0x082D)
+#define TCC2_LCMPD  _SFR_MEM8(0x082E)
+#define TCC2_HCMPD  _SFR_MEM8(0x082F)
+
+
+/* TC1 (TCC1) - 16-bit Timer/Counter 1 */
+#define TCC1_CTRLA  _SFR_MEM8(0x0840)
+#define TCC1_CTRLB  _SFR_MEM8(0x0841)
+#define TCC1_CTRLC  _SFR_MEM8(0x0842)
+#define TCC1_CTRLD  _SFR_MEM8(0x0843)
+#define TCC1_CTRLE  _SFR_MEM8(0x0844)
+#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
+#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
+#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
+#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
+#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
+#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
+#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
+#define TCC1_TEMP  _SFR_MEM8(0x084F)
+#define TCC1_CNT  _SFR_MEM16(0x0860)
+#define TCC1_CNTL  _SFR_MEM8(0x0860)
+#define TCC1_CNTH  _SFR_MEM8(0x0861)
+#define TCC1_PER  _SFR_MEM16(0x0866)
+#define TCC1_PERL  _SFR_MEM8(0x0866)
+#define TCC1_PERH  _SFR_MEM8(0x0867)
+#define TCC1_CCA  _SFR_MEM16(0x0868)
+#define TCC1_CCAL  _SFR_MEM8(0x0868)
+#define TCC1_CCAH  _SFR_MEM8(0x0869)
+#define TCC1_CCB  _SFR_MEM16(0x086A)
+#define TCC1_CCBL  _SFR_MEM8(0x086A)
+#define TCC1_CCBH  _SFR_MEM8(0x086B)
+#define TCC1_PERBUF  _SFR_MEM16(0x0876)
+#define TCC1_PERBUFL  _SFR_MEM8(0x0876)
+#define TCC1_PERBUFH  _SFR_MEM8(0x0877)
+#define TCC1_CCABUF  _SFR_MEM16(0x0878)
+#define TCC1_CCABUFL  _SFR_MEM8(0x0878)
+#define TCC1_CCABUFH  _SFR_MEM8(0x0879)
+#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
+#define TCC1_CCBBUFL  _SFR_MEM8(0x087A)
+#define TCC1_CCBBUFH  _SFR_MEM8(0x087B)
+
+
+/* AWEX (AWEXC) - Advanced Waveform Extension */
+#define AWEXC_CTRL  _SFR_MEM8(0x0880)
+#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
+#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
+#define AWEXC_STATUS  _SFR_MEM8(0x0884)
+#define AWEXC_STATUSSET  _SFR_MEM8(0x0885)
+#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
+#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
+#define AWEXC_DTLS  _SFR_MEM8(0x0888)
+#define AWEXC_DTHS  _SFR_MEM8(0x0889)
+#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
+#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
+#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
+
+
+/* HIRES (HIRESC) - High-Resolution Extension */
+#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
+
+
+/* USART (USARTC0) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTC0_DATA  _SFR_MEM8(0x08A0)
+#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
+#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
+#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
+#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
+#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
+#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
+
+
+/* USART (USARTC1) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTC1_DATA  _SFR_MEM8(0x08B0)
+#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
+#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
+#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
+#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
+#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
+#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
+
+
+/* SPI (SPIC) - Serial Peripheral Interface */
+#define SPIC_CTRL  _SFR_MEM8(0x08C0)
+#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
+#define SPIC_STATUS  _SFR_MEM8(0x08C2)
+#define SPIC_DATA  _SFR_MEM8(0x08C3)
+
+
+/* IRCOM - IR Communication Module */
+#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
+#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
+#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
+
+
+/* TC0 (TCD0) - 16-bit Timer/Counter 0 */
+#define TCD0_CTRLA  _SFR_MEM8(0x0900)
+#define TCD0_CTRLB  _SFR_MEM8(0x0901)
+#define TCD0_CTRLC  _SFR_MEM8(0x0902)
+#define TCD0_CTRLD  _SFR_MEM8(0x0903)
+#define TCD0_CTRLE  _SFR_MEM8(0x0904)
+#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
+#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
+#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
+#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
+#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
+#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
+#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
+#define TCD0_TEMP  _SFR_MEM8(0x090F)
+#define TCD0_CNT  _SFR_MEM16(0x0920)
+#define TCD0_CNTL  _SFR_MEM8(0x0920)
+#define TCD0_CNTH  _SFR_MEM8(0x0921)
+#define TCD0_PER  _SFR_MEM16(0x0926)
+#define TCD0_PERL  _SFR_MEM8(0x0926)
+#define TCD0_PERH  _SFR_MEM8(0x0927)
+#define TCD0_CCA  _SFR_MEM16(0x0928)
+#define TCD0_CCAL  _SFR_MEM8(0x0928)
+#define TCD0_CCAH  _SFR_MEM8(0x0929)
+#define TCD0_CCB  _SFR_MEM16(0x092A)
+#define TCD0_CCBL  _SFR_MEM8(0x092A)
+#define TCD0_CCBH  _SFR_MEM8(0x092B)
+#define TCD0_CCC  _SFR_MEM16(0x092C)
+#define TCD0_CCCL  _SFR_MEM8(0x092C)
+#define TCD0_CCCH  _SFR_MEM8(0x092D)
+#define TCD0_CCD  _SFR_MEM16(0x092E)
+#define TCD0_CCDL  _SFR_MEM8(0x092E)
+#define TCD0_CCDH  _SFR_MEM8(0x092F)
+#define TCD0_PERBUF  _SFR_MEM16(0x0936)
+#define TCD0_PERBUFL  _SFR_MEM8(0x0936)
+#define TCD0_PERBUFH  _SFR_MEM8(0x0937)
+#define TCD0_CCABUF  _SFR_MEM16(0x0938)
+#define TCD0_CCABUFL  _SFR_MEM8(0x0938)
+#define TCD0_CCABUFH  _SFR_MEM8(0x0939)
+#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
+#define TCD0_CCBBUFL  _SFR_MEM8(0x093A)
+#define TCD0_CCBBUFH  _SFR_MEM8(0x093B)
+#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
+#define TCD0_CCCBUFL  _SFR_MEM8(0x093C)
+#define TCD0_CCCBUFH  _SFR_MEM8(0x093D)
+#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
+#define TCD0_CCDBUFL  _SFR_MEM8(0x093E)
+#define TCD0_CCDBUFH  _SFR_MEM8(0x093F)
+
+
+/* TC2 (TCD2) - 16-bit Timer/Counter type 2 */
+#define TCD2_CTRLA  _SFR_MEM8(0x0900)
+#define TCD2_CTRLB  _SFR_MEM8(0x0901)
+#define TCD2_CTRLC  _SFR_MEM8(0x0902)
+#define TCD2_CTRLE  _SFR_MEM8(0x0904)
+#define TCD2_INTCTRLA  _SFR_MEM8(0x0906)
+#define TCD2_INTCTRLB  _SFR_MEM8(0x0907)
+#define TCD2_CTRLF  _SFR_MEM8(0x0909)
+#define TCD2_INTFLAGS  _SFR_MEM8(0x090C)
+#define TCD2_LCNT  _SFR_MEM8(0x0920)
+#define TCD2_HCNT  _SFR_MEM8(0x0921)
+#define TCD2_LPER  _SFR_MEM8(0x0926)
+#define TCD2_HPER  _SFR_MEM8(0x0927)
+#define TCD2_LCMPA  _SFR_MEM8(0x0928)
+#define TCD2_HCMPA  _SFR_MEM8(0x0929)
+#define TCD2_LCMPB  _SFR_MEM8(0x092A)
+#define TCD2_HCMPB  _SFR_MEM8(0x092B)
+#define TCD2_LCMPC  _SFR_MEM8(0x092C)
+#define TCD2_HCMPC  _SFR_MEM8(0x092D)
+#define TCD2_LCMPD  _SFR_MEM8(0x092E)
+#define TCD2_HCMPD  _SFR_MEM8(0x092F)
+
+
+/* TC1 (TCD1) - 16-bit Timer/Counter 1 */
+#define TCD1_CTRLA  _SFR_MEM8(0x0940)
+#define TCD1_CTRLB  _SFR_MEM8(0x0941)
+#define TCD1_CTRLC  _SFR_MEM8(0x0942)
+#define TCD1_CTRLD  _SFR_MEM8(0x0943)
+#define TCD1_CTRLE  _SFR_MEM8(0x0944)
+#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
+#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
+#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
+#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
+#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
+#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
+#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
+#define TCD1_TEMP  _SFR_MEM8(0x094F)
+#define TCD1_CNT  _SFR_MEM16(0x0960)
+#define TCD1_CNTL  _SFR_MEM8(0x0960)
+#define TCD1_CNTH  _SFR_MEM8(0x0961)
+#define TCD1_PER  _SFR_MEM16(0x0966)
+#define TCD1_PERL  _SFR_MEM8(0x0966)
+#define TCD1_PERH  _SFR_MEM8(0x0967)
+#define TCD1_CCA  _SFR_MEM16(0x0968)
+#define TCD1_CCAL  _SFR_MEM8(0x0968)
+#define TCD1_CCAH  _SFR_MEM8(0x0969)
+#define TCD1_CCB  _SFR_MEM16(0x096A)
+#define TCD1_CCBL  _SFR_MEM8(0x096A)
+#define TCD1_CCBH  _SFR_MEM8(0x096B)
+#define TCD1_PERBUF  _SFR_MEM16(0x0976)
+#define TCD1_PERBUFL  _SFR_MEM8(0x0976)
+#define TCD1_PERBUFH  _SFR_MEM8(0x0977)
+#define TCD1_CCABUF  _SFR_MEM16(0x0978)
+#define TCD1_CCABUFL  _SFR_MEM8(0x0978)
+#define TCD1_CCABUFH  _SFR_MEM8(0x0979)
+#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
+#define TCD1_CCBBUFL  _SFR_MEM8(0x097A)
+#define TCD1_CCBBUFH  _SFR_MEM8(0x097B)
+
+
+/* HIRES (HIRESD) - High-Resolution Extension */
+#define HIRESD_CTRLA  _SFR_MEM8(0x0990)
+
+
+/* USART (USARTD0) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTD0_DATA  _SFR_MEM8(0x09A0)
+#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
+#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
+#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
+#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
+#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
+#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
+
+
+/* USART (USARTD1) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTD1_DATA  _SFR_MEM8(0x09B0)
+#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
+#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
+#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
+#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
+#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
+#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
+
+
+/* SPI (SPID) - Serial Peripheral Interface */
+#define SPID_CTRL  _SFR_MEM8(0x09C0)
+#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
+#define SPID_STATUS  _SFR_MEM8(0x09C2)
+#define SPID_DATA  _SFR_MEM8(0x09C3)
+
+
+/* TC0 (TCE0) - 16-bit Timer/Counter 0 */
+#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
+#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
+#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
+#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
+#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
+#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
+#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
+#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
+#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
+#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
+#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
+#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
+#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
+#define TCE0_CNT  _SFR_MEM16(0x0A20)
+#define TCE0_CNTL  _SFR_MEM8(0x0A20)
+#define TCE0_CNTH  _SFR_MEM8(0x0A21)
+#define TCE0_PER  _SFR_MEM16(0x0A26)
+#define TCE0_PERL  _SFR_MEM8(0x0A26)
+#define TCE0_PERH  _SFR_MEM8(0x0A27)
+#define TCE0_CCA  _SFR_MEM16(0x0A28)
+#define TCE0_CCAL  _SFR_MEM8(0x0A28)
+#define TCE0_CCAH  _SFR_MEM8(0x0A29)
+#define TCE0_CCB  _SFR_MEM16(0x0A2A)
+#define TCE0_CCBL  _SFR_MEM8(0x0A2A)
+#define TCE0_CCBH  _SFR_MEM8(0x0A2B)
+#define TCE0_CCC  _SFR_MEM16(0x0A2C)
+#define TCE0_CCCL  _SFR_MEM8(0x0A2C)
+#define TCE0_CCCH  _SFR_MEM8(0x0A2D)
+#define TCE0_CCD  _SFR_MEM16(0x0A2E)
+#define TCE0_CCDL  _SFR_MEM8(0x0A2E)
+#define TCE0_CCDH  _SFR_MEM8(0x0A2F)
+#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
+#define TCE0_PERBUFL  _SFR_MEM8(0x0A36)
+#define TCE0_PERBUFH  _SFR_MEM8(0x0A37)
+#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
+#define TCE0_CCABUFL  _SFR_MEM8(0x0A38)
+#define TCE0_CCABUFH  _SFR_MEM8(0x0A39)
+#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
+#define TCE0_CCBBUFL  _SFR_MEM8(0x0A3A)
+#define TCE0_CCBBUFH  _SFR_MEM8(0x0A3B)
+#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
+#define TCE0_CCCBUFL  _SFR_MEM8(0x0A3C)
+#define TCE0_CCCBUFH  _SFR_MEM8(0x0A3D)
+#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
+#define TCE0_CCDBUFL  _SFR_MEM8(0x0A3E)
+#define TCE0_CCDBUFH  _SFR_MEM8(0x0A3F)
+
+
+/* TC2 (TCE2) - 16-bit Timer/Counter type 2 */
+#define TCE2_CTRLA  _SFR_MEM8(0x0A00)
+#define TCE2_CTRLB  _SFR_MEM8(0x0A01)
+#define TCE2_CTRLC  _SFR_MEM8(0x0A02)
+#define TCE2_CTRLE  _SFR_MEM8(0x0A04)
+#define TCE2_INTCTRLA  _SFR_MEM8(0x0A06)
+#define TCE2_INTCTRLB  _SFR_MEM8(0x0A07)
+#define TCE2_CTRLF  _SFR_MEM8(0x0A09)
+#define TCE2_INTFLAGS  _SFR_MEM8(0x0A0C)
+#define TCE2_LCNT  _SFR_MEM8(0x0A20)
+#define TCE2_HCNT  _SFR_MEM8(0x0A21)
+#define TCE2_LPER  _SFR_MEM8(0x0A26)
+#define TCE2_HPER  _SFR_MEM8(0x0A27)
+#define TCE2_LCMPA  _SFR_MEM8(0x0A28)
+#define TCE2_HCMPA  _SFR_MEM8(0x0A29)
+#define TCE2_LCMPB  _SFR_MEM8(0x0A2A)
+#define TCE2_HCMPB  _SFR_MEM8(0x0A2B)
+#define TCE2_LCMPC  _SFR_MEM8(0x0A2C)
+#define TCE2_HCMPC  _SFR_MEM8(0x0A2D)
+#define TCE2_LCMPD  _SFR_MEM8(0x0A2E)
+#define TCE2_HCMPD  _SFR_MEM8(0x0A2F)
+
+
+/* TC1 (TCE1) - 16-bit Timer/Counter 1 */
+#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
+#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
+#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
+#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
+#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
+#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
+#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
+#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
+#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
+#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
+#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
+#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
+#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
+#define TCE1_CNT  _SFR_MEM16(0x0A60)
+#define TCE1_CNTL  _SFR_MEM8(0x0A60)
+#define TCE1_CNTH  _SFR_MEM8(0x0A61)
+#define TCE1_PER  _SFR_MEM16(0x0A66)
+#define TCE1_PERL  _SFR_MEM8(0x0A66)
+#define TCE1_PERH  _SFR_MEM8(0x0A67)
+#define TCE1_CCA  _SFR_MEM16(0x0A68)
+#define TCE1_CCAL  _SFR_MEM8(0x0A68)
+#define TCE1_CCAH  _SFR_MEM8(0x0A69)
+#define TCE1_CCB  _SFR_MEM16(0x0A6A)
+#define TCE1_CCBL  _SFR_MEM8(0x0A6A)
+#define TCE1_CCBH  _SFR_MEM8(0x0A6B)
+#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
+#define TCE1_PERBUFL  _SFR_MEM8(0x0A76)
+#define TCE1_PERBUFH  _SFR_MEM8(0x0A77)
+#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
+#define TCE1_CCABUFL  _SFR_MEM8(0x0A78)
+#define TCE1_CCABUFH  _SFR_MEM8(0x0A79)
+#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
+#define TCE1_CCBBUFL  _SFR_MEM8(0x0A7A)
+#define TCE1_CCBBUFH  _SFR_MEM8(0x0A7B)
+
+
+/* AWEX (AWEXE) - Advanced Waveform Extension */
+#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
+#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
+#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
+#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
+#define AWEXE_STATUSSET  _SFR_MEM8(0x0A85)
+#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
+#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
+#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
+#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
+#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
+#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
+#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
+
+
+/* HIRES (HIRESE) - High-Resolution Extension */
+#define HIRESE_CTRLA  _SFR_MEM8(0x0A90)
+
+
+/* USART (USARTE0) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
+#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
+#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
+#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
+#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
+#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
+#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
+
+
+/* USART (USARTE1) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTE1_DATA  _SFR_MEM8(0x0AB0)
+#define USARTE1_STATUS  _SFR_MEM8(0x0AB1)
+#define USARTE1_CTRLA  _SFR_MEM8(0x0AB3)
+#define USARTE1_CTRLB  _SFR_MEM8(0x0AB4)
+#define USARTE1_CTRLC  _SFR_MEM8(0x0AB5)
+#define USARTE1_BAUDCTRLA  _SFR_MEM8(0x0AB6)
+#define USARTE1_BAUDCTRLB  _SFR_MEM8(0x0AB7)
+
+
+/* SPI (SPIE) - Serial Peripheral Interface */
+#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
+#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
+#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
+#define SPIE_DATA  _SFR_MEM8(0x0AC3)
+
+
+/* TC0 (TCF0) - 16-bit Timer/Counter 0 */
+#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
+#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
+#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
+#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
+#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
+#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
+#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
+#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
+#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
+#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
+#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
+#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
+#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
+#define TCF0_CNT  _SFR_MEM16(0x0B20)
+#define TCF0_CNTL  _SFR_MEM8(0x0B20)
+#define TCF0_CNTH  _SFR_MEM8(0x0B21)
+#define TCF0_PER  _SFR_MEM16(0x0B26)
+#define TCF0_PERL  _SFR_MEM8(0x0B26)
+#define TCF0_PERH  _SFR_MEM8(0x0B27)
+#define TCF0_CCA  _SFR_MEM16(0x0B28)
+#define TCF0_CCAL  _SFR_MEM8(0x0B28)
+#define TCF0_CCAH  _SFR_MEM8(0x0B29)
+#define TCF0_CCB  _SFR_MEM16(0x0B2A)
+#define TCF0_CCBL  _SFR_MEM8(0x0B2A)
+#define TCF0_CCBH  _SFR_MEM8(0x0B2B)
+#define TCF0_CCC  _SFR_MEM16(0x0B2C)
+#define TCF0_CCCL  _SFR_MEM8(0x0B2C)
+#define TCF0_CCCH  _SFR_MEM8(0x0B2D)
+#define TCF0_CCD  _SFR_MEM16(0x0B2E)
+#define TCF0_CCDL  _SFR_MEM8(0x0B2E)
+#define TCF0_CCDH  _SFR_MEM8(0x0B2F)
+#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
+#define TCF0_PERBUFL  _SFR_MEM8(0x0B36)
+#define TCF0_PERBUFH  _SFR_MEM8(0x0B37)
+#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
+#define TCF0_CCABUFL  _SFR_MEM8(0x0B38)
+#define TCF0_CCABUFH  _SFR_MEM8(0x0B39)
+#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
+#define TCF0_CCBBUFL  _SFR_MEM8(0x0B3A)
+#define TCF0_CCBBUFH  _SFR_MEM8(0x0B3B)
+#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
+#define TCF0_CCCBUFL  _SFR_MEM8(0x0B3C)
+#define TCF0_CCCBUFH  _SFR_MEM8(0x0B3D)
+#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
+#define TCF0_CCDBUFL  _SFR_MEM8(0x0B3E)
+#define TCF0_CCDBUFH  _SFR_MEM8(0x0B3F)
+
+
+/* TC2 (TCF2) - 16-bit Timer/Counter type 2 */
+#define TCF2_CTRLA  _SFR_MEM8(0x0B00)
+#define TCF2_CTRLB  _SFR_MEM8(0x0B01)
+#define TCF2_CTRLC  _SFR_MEM8(0x0B02)
+#define TCF2_CTRLE  _SFR_MEM8(0x0B04)
+#define TCF2_INTCTRLA  _SFR_MEM8(0x0B06)
+#define TCF2_INTCTRLB  _SFR_MEM8(0x0B07)
+#define TCF2_CTRLF  _SFR_MEM8(0x0B09)
+#define TCF2_INTFLAGS  _SFR_MEM8(0x0B0C)
+#define TCF2_LCNT  _SFR_MEM8(0x0B20)
+#define TCF2_HCNT  _SFR_MEM8(0x0B21)
+#define TCF2_LPER  _SFR_MEM8(0x0B26)
+#define TCF2_HPER  _SFR_MEM8(0x0B27)
+#define TCF2_LCMPA  _SFR_MEM8(0x0B28)
+#define TCF2_HCMPA  _SFR_MEM8(0x0B29)
+#define TCF2_LCMPB  _SFR_MEM8(0x0B2A)
+#define TCF2_HCMPB  _SFR_MEM8(0x0B2B)
+#define TCF2_LCMPC  _SFR_MEM8(0x0B2C)
+#define TCF2_HCMPC  _SFR_MEM8(0x0B2D)
+#define TCF2_LCMPD  _SFR_MEM8(0x0B2E)
+#define TCF2_HCMPD  _SFR_MEM8(0x0B2F)
+
+
+/* HIRES (HIRESF) - High-Resolution Extension */
+#define HIRESF_CTRLA  _SFR_MEM8(0x0B90)
+
+
+/* USART (USARTF0) - Universal Synchronous/Asynchronous Receiver/Transmitter */
+#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
+#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
+#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
+#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
+#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
+#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
+#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
+
+
+
+/*================== Bitfield Definitions ================== */
+
+/* AC - Analog Comparator */
+/* AC.AC0CTRL  bit masks and bit positions */
+#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
+#define AC_ENABLE_bp  0  /* Enable bit position. */
+#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
+#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
+#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
+#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
+#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
+#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
+#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
+#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
+#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
+#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
+#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
+#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
+#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
+#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
+#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
+#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
+#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
+#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
+#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
+#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
+
+/* AC.AC1CTRL  bit masks and bit positions */
+/* AC_ENABLE  is already defined. */
+/* AC_HYSMODE  is already defined. */
+/* AC_HSMODE  is already defined. */
+/* AC_INTLVL  is already defined. */
+/* AC_INTMODE  is already defined. */
+
+/* AC.AC0MUXCTRL  bit masks and bit positions */
+#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
+#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
+#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
+#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
+#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
+#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
+#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
+#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
+#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
+#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
+#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
+#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
+#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
+#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
+#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
+#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
+
+/* AC.AC1MUXCTRL  bit masks and bit positions */
+/* AC_MUXNEG  is already defined. */
+/* AC_MUXPOS  is already defined. */
+
+/* AC.CTRLA  bit masks and bit positions */
+#define AC_AC0OUT_bm  0x01  /* Analog Comparator 0 Output Enable bit mask. */
+#define AC_AC0OUT_bp  0  /* Analog Comparator 0 Output Enable bit position. */
+#define AC_AC1OUT_bm  0x02  /* Analog Comparator 1 Output Enable bit mask. */
+#define AC_AC1OUT_bp  1  /* Analog Comparator 1 Output Enable bit position. */
+
+/* AC.CTRLB  bit masks and bit positions */
+#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
+#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
+#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
+#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
+#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
+#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
+#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
+#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
+#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
+#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
+#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
+#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
+#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
+#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
+
+/* AC.WINCTRL  bit masks and bit positions */
+#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
+#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
+#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
+#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
+#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
+#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
+#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
+#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
+#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
+#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
+#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
+#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
+#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
+#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
+
+/* AC.STATUS  bit masks and bit positions */
+#define AC_AC0IF_bm  0x01  /* Analog Comparator 0 Interrupt Flag bit mask. */
+#define AC_AC0IF_bp  0  /* Analog Comparator 0 Interrupt Flag bit position. */
+#define AC_AC1IF_bm  0x02  /* Analog Comparator 1 Interrupt Flag bit mask. */
+#define AC_AC1IF_bp  1  /* Analog Comparator 1 Interrupt Flag bit position. */
+#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
+#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
+#define AC_AC0STATE_bm  0x10  /* Analog Comparator 0 State bit mask. */
+#define AC_AC0STATE_bp  4  /* Analog Comparator 0 State bit position. */
+#define AC_AC1STATE_bm  0x20  /* Analog Comparator 1 State bit mask. */
+#define AC_AC1STATE_bp  5  /* Analog Comparator 1 State bit position. */
+#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
+#define AC_WSTATE_gp  6  /* Window Mode State group position. */
+#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
+#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
+#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
+#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
+
+/* AC.CURRCTRL  bit masks and bit positions */
+#define AC_AC0CURR_bm  0x01  /* AC0 Current Source Output Enable bit mask. */
+#define AC_AC0CURR_bp  0  /* AC0 Current Source Output Enable bit position. */
+#define AC_AC1CURR_bm  0x02  /* AC1 Current Source Output Enable bit mask. */
+#define AC_AC1CURR_bp  1  /* AC1 Current Source Output Enable bit position. */
+#define AC_CURRMODE_bm  0x40  /* Current Mode bit mask. */
+#define AC_CURRMODE_bp  6  /* Current Mode bit position. */
+#define AC_CURRENT_bm  0x80  /* Current Source Enable bit mask. */
+#define AC_CURRENT_bp  7  /* Current Source Enable bit position. */
+
+/* AC.CURRCALIB  bit masks and bit positions */
+#define AC_CALIB_gm  0x0F  /* Current Source Calibration group mask. */
+#define AC_CALIB_gp  0  /* Current Source Calibration group position. */
+#define AC_CALIB0_bm  (1<<0)  /* Current Source Calibration bit 0 mask. */
+#define AC_CALIB0_bp  0  /* Current Source Calibration bit 0 position. */
+#define AC_CALIB1_bm  (1<<1)  /* Current Source Calibration bit 1 mask. */
+#define AC_CALIB1_bp  1  /* Current Source Calibration bit 1 position. */
+#define AC_CALIB2_bm  (1<<2)  /* Current Source Calibration bit 2 mask. */
+#define AC_CALIB2_bp  2  /* Current Source Calibration bit 2 position. */
+#define AC_CALIB3_bm  (1<<3)  /* Current Source Calibration bit 3 mask. */
+#define AC_CALIB3_bp  3  /* Current Source Calibration bit 3 position. */
+
+/* ADC - Analog/Digital Converter */
+/* ADC_CH.CTRL  bit masks and bit positions */
+#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
+#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
+#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
+#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
+#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
+#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
+#define ADC_CH_GAIN_gm  0x1C  /* Gain Factor group mask. */
+#define ADC_CH_GAIN_gp  2  /* Gain Factor group position. */
+#define ADC_CH_GAIN0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
+#define ADC_CH_GAIN0_bp  2  /* Gain Factor bit 0 position. */
+#define ADC_CH_GAIN1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
+#define ADC_CH_GAIN1_bp  3  /* Gain Factor bit 1 position. */
+#define ADC_CH_GAIN2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
+#define ADC_CH_GAIN2_bp  4  /* Gain Factor bit 2 position. */
+#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
+#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
+
+/* ADC_CH.MUXCTRL  bit masks and bit positions */
+#define ADC_CH_MUXNEG_gm  0x07  /* MUX selection on Negative ADC input group mask. */
+#define ADC_CH_MUXNEG_gp  0  /* MUX selection on Negative ADC input group position. */
+#define ADC_CH_MUXNEG0_bm  (1<<0)  /* MUX selection on Negative ADC input bit 0 mask. */
+#define ADC_CH_MUXNEG0_bp  0  /* MUX selection on Negative ADC input bit 0 position. */
+#define ADC_CH_MUXNEG1_bm  (1<<1)  /* MUX selection on Negative ADC input bit 1 mask. */
+#define ADC_CH_MUXNEG1_bp  1  /* MUX selection on Negative ADC input bit 1 position. */
+#define ADC_CH_MUXNEG2_bm  (1<<2)  /* MUX selection on Negative ADC input bit 2 mask. */
+#define ADC_CH_MUXNEG2_bp  2  /* MUX selection on Negative ADC input bit 2 position. */
+#define ADC_CH_MUXPOS_gm  0x78  /* MUX selection on Positive ADC input group mask. */
+#define ADC_CH_MUXPOS_gp  3  /* MUX selection on Positive ADC input group position. */
+#define ADC_CH_MUXPOS0_bm  (1<<3)  /* MUX selection on Positive ADC input bit 0 mask. */
+#define ADC_CH_MUXPOS0_bp  3  /* MUX selection on Positive ADC input bit 0 position. */
+#define ADC_CH_MUXPOS1_bm  (1<<4)  /* MUX selection on Positive ADC input bit 1 mask. */
+#define ADC_CH_MUXPOS1_bp  4  /* MUX selection on Positive ADC input bit 1 position. */
+#define ADC_CH_MUXPOS2_bm  (1<<5)  /* MUX selection on Positive ADC input bit 2 mask. */
+#define ADC_CH_MUXPOS2_bp  5  /* MUX selection on Positive ADC input bit 2 position. */
+#define ADC_CH_MUXPOS3_bm  (1<<6)  /* MUX selection on Positive ADC input bit 3 mask. */
+#define ADC_CH_MUXPOS3_bp  6  /* MUX selection on Positive ADC input bit 3 position. */
+#define ADC_CH_MUXINT_gm  0x78  /* MUX selection on Internal ADC input group mask. */
+#define ADC_CH_MUXINT_gp  3  /* MUX selection on Internal ADC input group position. */
+#define ADC_CH_MUXINT0_bm  (1<<3)  /* MUX selection on Internal ADC input bit 0 mask. */
+#define ADC_CH_MUXINT0_bp  3  /* MUX selection on Internal ADC input bit 0 position. */
+#define ADC_CH_MUXINT1_bm  (1<<4)  /* MUX selection on Internal ADC input bit 1 mask. */
+#define ADC_CH_MUXINT1_bp  4  /* MUX selection on Internal ADC input bit 1 position. */
+#define ADC_CH_MUXINT2_bm  (1<<5)  /* MUX selection on Internal ADC input bit 2 mask. */
+#define ADC_CH_MUXINT2_bp  5  /* MUX selection on Internal ADC input bit 2 position. */
+#define ADC_CH_MUXINT3_bm  (1<<6)  /* MUX selection on Internal ADC input bit 3 mask. */
+#define ADC_CH_MUXINT3_bp  6  /* MUX selection on Internal ADC input bit 3 position. */
+
+/* ADC_CH.INTCTRL  bit masks and bit positions */
+#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
+#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
+#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
+#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
+#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
+#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
+#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
+#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
+#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
+#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
+#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
+#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
+
+/* ADC_CH.INTFLAGS  bit masks and bit positions */
+#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
+#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
+
+
+/* ADC_CH.SCAN  bit masks and bit positions */
+#define ADC_CH_SCANNUM_gm  0x0F  /* Number of Channels included in scan group mask. */
+#define ADC_CH_SCANNUM_gp  0  /* Number of Channels included in scan group position. */
+#define ADC_CH_SCANNUM0_bm  (1<<0)  /* Number of Channels included in scan bit 0 mask. */
+#define ADC_CH_SCANNUM0_bp  0  /* Number of Channels included in scan bit 0 position. */
+#define ADC_CH_SCANNUM1_bm  (1<<1)  /* Number of Channels included in scan bit 1 mask. */
+#define ADC_CH_SCANNUM1_bp  1  /* Number of Channels included in scan bit 1 position. */
+#define ADC_CH_SCANNUM2_bm  (1<<2)  /* Number of Channels included in scan bit 2 mask. */
+#define ADC_CH_SCANNUM2_bp  2  /* Number of Channels included in scan bit 2 position. */
+#define ADC_CH_SCANNUM3_bm  (1<<3)  /* Number of Channels included in scan bit 3 mask. */
+#define ADC_CH_SCANNUM3_bp  3  /* Number of Channels included in scan bit 3 position. */
+#define ADC_CH_OFFSET_gm  0xF0  /* Positive MUX setting offset group mask. */
+#define ADC_CH_OFFSET_gp  4  /* Positive MUX setting offset group position. */
+#define ADC_CH_OFFSET0_bm  (1<<4)  /* Positive MUX setting offset bit 0 mask. */
+#define ADC_CH_OFFSET0_bp  4  /* Positive MUX setting offset bit 0 position. */
+#define ADC_CH_OFFSET1_bm  (1<<5)  /* Positive MUX setting offset bit 1 mask. */
+#define ADC_CH_OFFSET1_bp  5  /* Positive MUX setting offset bit 1 position. */
+#define ADC_CH_OFFSET2_bm  (1<<6)  /* Positive MUX setting offset bit 2 mask. */
+#define ADC_CH_OFFSET2_bp  6  /* Positive MUX setting offset bit 2 position. */
+#define ADC_CH_OFFSET3_bm  (1<<7)  /* Positive MUX setting offset bit 3 mask. */
+#define ADC_CH_OFFSET3_bp  7  /* Positive MUX setting offset bit 3 position. */
+
+/* ADC.CTRLA  bit masks and bit positions */
+#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
+#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
+#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
+#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
+#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
+#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
+#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
+#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
+#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
+#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
+#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
+#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
+#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
+#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
+#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
+#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
+#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
+#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
+
+/* ADC.CTRLB  bit masks and bit positions */
+#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
+#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
+#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
+#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
+#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
+#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
+#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
+#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
+#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
+#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
+#define ADC_CURRLIMIT_gm  0x60  /* Current Limitation group mask. */
+#define ADC_CURRLIMIT_gp  5  /* Current Limitation group position. */
+#define ADC_CURRLIMIT0_bm  (1<<5)  /* Current Limitation bit 0 mask. */
+#define ADC_CURRLIMIT0_bp  5  /* Current Limitation bit 0 position. */
+#define ADC_CURRLIMIT1_bm  (1<<6)  /* Current Limitation bit 1 mask. */
+#define ADC_CURRLIMIT1_bp  6  /* Current Limitation bit 1 position. */
+#define ADC_IMPMODE_bm  0x80  /* Gain Stage Impedance Mode bit mask. */
+#define ADC_IMPMODE_bp  7  /* Gain Stage Impedance Mode bit position. */
+
+/* ADC.REFCTRL  bit masks and bit positions */
+#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
+#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
+#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
+#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
+#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
+#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
+#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
+#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
+#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
+#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
+#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
+#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
+
+/* ADC.EVCTRL  bit masks and bit positions */
+#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
+#define ADC_EVACT_gp  0  /* Event Action Select group position. */
+#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
+#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
+#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
+#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
+#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
+#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
+#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
+#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
+#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
+#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
+#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
+#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
+#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
+#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
+#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
+#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
+#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
+#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
+#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
+#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
+
+/* ADC.PRESCALER  bit masks and bit positions */
+#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
+#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
+#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
+#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
+#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
+#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
+#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
+#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
+
+/* ADC.INTFLAGS  bit masks and bit positions */
+#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
+#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
+#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
+#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
+#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
+#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
+#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
+#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
+
+
+
+
+
+
+
+
+/* AES - AES Module */
+/* AES.CTRL  bit masks and bit positions */
+#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
+#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
+#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
+#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
+#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
+#define AES_RESET_bp  5  /* AES Software Reset bit position. */
+#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
+#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
+#define AES_START_bm  0x80  /* Start/Run bit mask. */
+#define AES_START_bp  7  /* Start/Run bit position. */
+
+/* AES.STATUS  bit masks and bit positions */
+#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
+#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
+#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
+#define AES_ERROR_bp  7  /* AES Error bit position. */
+
+
+
+/* AES.INTCTRL  bit masks and bit positions */
+#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
+#define AES_INTLVL_gp  0  /* Interrupt level group position. */
+#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
+#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
+#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
+#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
+
+/* AWEX - Timer/Counter Advanced Waveform Extension */
+/* AWEX.CTRL  bit masks and bit positions */
+#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
+#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
+#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
+#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
+#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
+#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
+#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
+#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
+#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
+#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
+#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
+#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
+
+
+/* AWEX.FDCTRL  bit masks and bit positions */
+#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
+#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
+#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
+#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
+#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
+#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
+#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
+#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
+#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
+#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
+
+/* AWEX.STATUS  bit masks and bit positions */
+#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
+#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
+#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
+#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
+#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
+#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
+
+/* AWEX.STATUSSET  bit masks and bit positions */
+/* AWEX_DTLSBUFV  is already defined. */
+/* AWEX_DTHSBUFV  is already defined. */
+/* AWEX_FDF  is already defined. */
+
+
+
+
+
+
+
+
+/* CLK - Clock System */
+/* CLK.CTRL  bit masks and bit positions */
+#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
+#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
+#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
+#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
+#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
+#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
+#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
+#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
+
+/* CLK.PSCTRL  bit masks and bit positions */
+#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
+#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
+#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
+#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
+#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
+#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
+#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
+#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
+#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
+#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
+#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
+#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
+#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
+#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
+#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
+#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
+#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
+#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
+
+/* CLK.LOCK  bit masks and bit positions */
+#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
+#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
+
+/* CLK.RTCCTRL  bit masks and bit positions */
+#define CLK_RTCEN_bm  0x01  /* Clock Source Enable bit mask. */
+#define CLK_RTCEN_bp  0  /* Clock Source Enable bit position. */
+#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
+#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
+#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
+#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
+#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
+#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
+#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
+#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
+
+/* CLK.USBCTRL  bit masks and bit positions */
+#define CLK_USBSEN_bm  0x01  /* Clock Source Enable bit mask. */
+#define CLK_USBSEN_bp  0  /* Clock Source Enable bit position. */
+#define CLK_USBSRC_gm  0x06  /* Clock Source group mask. */
+#define CLK_USBSRC_gp  1  /* Clock Source group position. */
+#define CLK_USBSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
+#define CLK_USBSRC0_bp  1  /* Clock Source bit 0 position. */
+#define CLK_USBSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
+#define CLK_USBSRC1_bp  2  /* Clock Source bit 1 position. */
+#define CLK_USBPSDIV_gm  0x38  /* Prescaler Division Factor group mask. */
+#define CLK_USBPSDIV_gp  3  /* Prescaler Division Factor group position. */
+#define CLK_USBPSDIV0_bm  (1<<3)  /* Prescaler Division Factor bit 0 mask. */
+#define CLK_USBPSDIV0_bp  3  /* Prescaler Division Factor bit 0 position. */
+#define CLK_USBPSDIV1_bm  (1<<4)  /* Prescaler Division Factor bit 1 mask. */
+#define CLK_USBPSDIV1_bp  4  /* Prescaler Division Factor bit 1 position. */
+#define CLK_USBPSDIV2_bm  (1<<5)  /* Prescaler Division Factor bit 2 mask. */
+#define CLK_USBPSDIV2_bp  5  /* Prescaler Division Factor bit 2 position. */
+
+/* CPU - CPU */
+/* CPU.CCP  bit masks and bit positions */
+#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
+#define CPU_CCP_gp  0  /* CCP signature group position. */
+#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
+#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
+#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
+#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
+#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
+#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
+#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
+#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
+#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
+#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
+#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
+#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
+#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
+#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
+#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
+#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
+
+
+
+
+
+
+
+
+/* CPU.SREG  bit masks and bit positions */
+#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
+#define CPU_C_bp  0  /* Carry Flag bit position. */
+#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
+#define CPU_Z_bp  1  /* Zero Flag bit position. */
+#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
+#define CPU_N_bp  2  /* Negative Flag bit position. */
+#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
+#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
+#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
+#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
+#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
+#define CPU_H_bp  5  /* Half Carry Flag bit position. */
+#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
+#define CPU_T_bp  6  /* Transfer Bit bit position. */
+#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
+#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
+
+/* CRC - Cyclic Redundancy Checker */
+/* CRC.CTRL  bit masks and bit positions */
+#define CRC_SOURCE_gm  0x0F  /* Input Source group mask. */
+#define CRC_SOURCE_gp  0  /* Input Source group position. */
+#define CRC_SOURCE0_bm  (1<<0)  /* Input Source bit 0 mask. */
+#define CRC_SOURCE0_bp  0  /* Input Source bit 0 position. */
+#define CRC_SOURCE1_bm  (1<<1)  /* Input Source bit 1 mask. */
+#define CRC_SOURCE1_bp  1  /* Input Source bit 1 position. */
+#define CRC_SOURCE2_bm  (1<<2)  /* Input Source bit 2 mask. */
+#define CRC_SOURCE2_bp  2  /* Input Source bit 2 position. */
+#define CRC_SOURCE3_bm  (1<<3)  /* Input Source bit 3 mask. */
+#define CRC_SOURCE3_bp  3  /* Input Source bit 3 position. */
+#define CRC_CRC32_bm  0x20  /* CRC Mode bit mask. */
+#define CRC_CRC32_bp  5  /* CRC Mode bit position. */
+#define CRC_RESET_gm  0xC0  /* Reset group mask. */
+#define CRC_RESET_gp  6  /* Reset group position. */
+#define CRC_RESET0_bm  (1<<6)  /* Reset bit 0 mask. */
+#define CRC_RESET0_bp  6  /* Reset bit 0 position. */
+#define CRC_RESET1_bm  (1<<7)  /* Reset bit 1 mask. */
+#define CRC_RESET1_bp  7  /* Reset bit 1 position. */
+
+/* CRC.STATUS  bit masks and bit positions */
+#define CRC_BUSY_bm  0x01  /* Busy bit mask. */
+#define CRC_BUSY_bp  0  /* Busy bit position. */
+#define CRC_ZERO_bm  0x02  /* Zero detection bit mask. */
+#define CRC_ZERO_bp  1  /* Zero detection bit position. */
+
+
+
+
+
+
+/* DAC - Digital/Analog Converter */
+/* DAC.CTRLA  bit masks and bit positions */
+#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
+#define DAC_ENABLE_bp  0  /* Enable bit position. */
+#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
+#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
+#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
+#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
+#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
+#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
+#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
+#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
+
+/* DAC.CTRLB  bit masks and bit positions */
+#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
+#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
+#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
+#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
+#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
+#define DAC_CHSEL_gp  5  /* Channel Select group position. */
+#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
+#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
+#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
+#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
+
+/* DAC.CTRLC  bit masks and bit positions */
+#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
+#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
+#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
+#define DAC_REFSEL_gp  3  /* Reference Select group position. */
+#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
+#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
+#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
+#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
+
+/* DAC.EVCTRL  bit masks and bit positions */
+#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
+#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
+#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
+#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
+#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
+#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
+#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
+#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
+#define DAC_EVSPLIT_bm  0x08  /* Separate Event Channel Input for Channel 1 bit mask. */
+#define DAC_EVSPLIT_bp  3  /* Separate Event Channel Input for Channel 1 bit position. */
+
+/* DAC.STATUS  bit masks and bit positions */
+#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
+#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
+#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
+#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
+
+/* DAC.CH0GAINCAL  bit masks and bit positions */
+#define DAC_CH0GAINCAL_gm  0x7F  /* Gain Calibration group mask. */
+#define DAC_CH0GAINCAL_gp  0  /* Gain Calibration group position. */
+#define DAC_CH0GAINCAL0_bm  (1<<0)  /* Gain Calibration bit 0 mask. */
+#define DAC_CH0GAINCAL0_bp  0  /* Gain Calibration bit 0 position. */
+#define DAC_CH0GAINCAL1_bm  (1<<1)  /* Gain Calibration bit 1 mask. */
+#define DAC_CH0GAINCAL1_bp  1  /* Gain Calibration bit 1 position. */
+#define DAC_CH0GAINCAL2_bm  (1<<2)  /* Gain Calibration bit 2 mask. */
+#define DAC_CH0GAINCAL2_bp  2  /* Gain Calibration bit 2 position. */
+#define DAC_CH0GAINCAL3_bm  (1<<3)  /* Gain Calibration bit 3 mask. */
+#define DAC_CH0GAINCAL3_bp  3  /* Gain Calibration bit 3 position. */
+#define DAC_CH0GAINCAL4_bm  (1<<4)  /* Gain Calibration bit 4 mask. */
+#define DAC_CH0GAINCAL4_bp  4  /* Gain Calibration bit 4 position. */
+#define DAC_CH0GAINCAL5_bm  (1<<5)  /* Gain Calibration bit 5 mask. */
+#define DAC_CH0GAINCAL5_bp  5  /* Gain Calibration bit 5 position. */
+#define DAC_CH0GAINCAL6_bm  (1<<6)  /* Gain Calibration bit 6 mask. */
+#define DAC_CH0GAINCAL6_bp  6  /* Gain Calibration bit 6 position. */
+
+/* DAC.CH0OFFSETCAL  bit masks and bit positions */
+#define DAC_CH0OFFSETCAL_gm  0x7F  /* Offset Calibration group mask. */
+#define DAC_CH0OFFSETCAL_gp  0  /* Offset Calibration group position. */
+#define DAC_CH0OFFSETCAL0_bm  (1<<0)  /* Offset Calibration bit 0 mask. */
+#define DAC_CH0OFFSETCAL0_bp  0  /* Offset Calibration bit 0 position. */
+#define DAC_CH0OFFSETCAL1_bm  (1<<1)  /* Offset Calibration bit 1 mask. */
+#define DAC_CH0OFFSETCAL1_bp  1  /* Offset Calibration bit 1 position. */
+#define DAC_CH0OFFSETCAL2_bm  (1<<2)  /* Offset Calibration bit 2 mask. */
+#define DAC_CH0OFFSETCAL2_bp  2  /* Offset Calibration bit 2 position. */
+#define DAC_CH0OFFSETCAL3_bm  (1<<3)  /* Offset Calibration bit 3 mask. */
+#define DAC_CH0OFFSETCAL3_bp  3  /* Offset Calibration bit 3 position. */
+#define DAC_CH0OFFSETCAL4_bm  (1<<4)  /* Offset Calibration bit 4 mask. */
+#define DAC_CH0OFFSETCAL4_bp  4  /* Offset Calibration bit 4 position. */
+#define DAC_CH0OFFSETCAL5_bm  (1<<5)  /* Offset Calibration bit 5 mask. */
+#define DAC_CH0OFFSETCAL5_bp  5  /* Offset Calibration bit 5 position. */
+#define DAC_CH0OFFSETCAL6_bm  (1<<6)  /* Offset Calibration bit 6 mask. */
+#define DAC_CH0OFFSETCAL6_bp  6  /* Offset Calibration bit 6 position. */
+
+/* DAC.CH1GAINCAL  bit masks and bit positions */
+#define DAC_CH1GAINCAL_gm  0x7F  /* Gain Calibration group mask. */
+#define DAC_CH1GAINCAL_gp  0  /* Gain Calibration group position. */
+#define DAC_CH1GAINCAL0_bm  (1<<0)  /* Gain Calibration bit 0 mask. */
+#define DAC_CH1GAINCAL0_bp  0  /* Gain Calibration bit 0 position. */
+#define DAC_CH1GAINCAL1_bm  (1<<1)  /* Gain Calibration bit 1 mask. */
+#define DAC_CH1GAINCAL1_bp  1  /* Gain Calibration bit 1 position. */
+#define DAC_CH1GAINCAL2_bm  (1<<2)  /* Gain Calibration bit 2 mask. */
+#define DAC_CH1GAINCAL2_bp  2  /* Gain Calibration bit 2 position. */
+#define DAC_CH1GAINCAL3_bm  (1<<3)  /* Gain Calibration bit 3 mask. */
+#define DAC_CH1GAINCAL3_bp  3  /* Gain Calibration bit 3 position. */
+#define DAC_CH1GAINCAL4_bm  (1<<4)  /* Gain Calibration bit 4 mask. */
+#define DAC_CH1GAINCAL4_bp  4  /* Gain Calibration bit 4 position. */
+#define DAC_CH1GAINCAL5_bm  (1<<5)  /* Gain Calibration bit 5 mask. */
+#define DAC_CH1GAINCAL5_bp  5  /* Gain Calibration bit 5 position. */
+#define DAC_CH1GAINCAL6_bm  (1<<6)  /* Gain Calibration bit 6 mask. */
+#define DAC_CH1GAINCAL6_bp  6  /* Gain Calibration bit 6 position. */
+
+/* DAC.CH1OFFSETCAL  bit masks and bit positions */
+#define DAC_CH1OFFSETCAL_gm  0x7F  /* Offset Calibration group mask. */
+#define DAC_CH1OFFSETCAL_gp  0  /* Offset Calibration group position. */
+#define DAC_CH1OFFSETCAL0_bm  (1<<0)  /* Offset Calibration bit 0 mask. */
+#define DAC_CH1OFFSETCAL0_bp  0  /* Offset Calibration bit 0 position. */
+#define DAC_CH1OFFSETCAL1_bm  (1<<1)  /* Offset Calibration bit 1 mask. */
+#define DAC_CH1OFFSETCAL1_bp  1  /* Offset Calibration bit 1 position. */
+#define DAC_CH1OFFSETCAL2_bm  (1<<2)  /* Offset Calibration bit 2 mask. */
+#define DAC_CH1OFFSETCAL2_bp  2  /* Offset Calibration bit 2 position. */
+#define DAC_CH1OFFSETCAL3_bm  (1<<3)  /* Offset Calibration bit 3 mask. */
+#define DAC_CH1OFFSETCAL3_bp  3  /* Offset Calibration bit 3 position. */
+#define DAC_CH1OFFSETCAL4_bm  (1<<4)  /* Offset Calibration bit 4 mask. */
+#define DAC_CH1OFFSETCAL4_bp  4  /* Offset Calibration bit 4 position. */
+#define DAC_CH1OFFSETCAL5_bm  (1<<5)  /* Offset Calibration bit 5 mask. */
+#define DAC_CH1OFFSETCAL5_bp  5  /* Offset Calibration bit 5 position. */
+#define DAC_CH1OFFSETCAL6_bm  (1<<6)  /* Offset Calibration bit 6 mask. */
+#define DAC_CH1OFFSETCAL6_bp  6  /* Offset Calibration bit 6 position. */
+
+
+
+/* DFLL - DFLL */
+/* DFLL.CTRL  bit masks and bit positions */
+#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
+#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
+
+/* DFLL.CALA  bit masks and bit positions */
+#define DFLL_CALL_gm  0x7F  /* DFLL Calibration Value A group mask. */
+#define DFLL_CALL_gp  0  /* DFLL Calibration Value A group position. */
+#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration Value A bit 0 mask. */
+#define DFLL_CALL0_bp  0  /* DFLL Calibration Value A bit 0 position. */
+#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration Value A bit 1 mask. */
+#define DFLL_CALL1_bp  1  /* DFLL Calibration Value A bit 1 position. */
+#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration Value A bit 2 mask. */
+#define DFLL_CALL2_bp  2  /* DFLL Calibration Value A bit 2 position. */
+#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration Value A bit 3 mask. */
+#define DFLL_CALL3_bp  3  /* DFLL Calibration Value A bit 3 position. */
+#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration Value A bit 4 mask. */
+#define DFLL_CALL4_bp  4  /* DFLL Calibration Value A bit 4 position. */
+#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration Value A bit 5 mask. */
+#define DFLL_CALL5_bp  5  /* DFLL Calibration Value A bit 5 position. */
+#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration Value A bit 6 mask. */
+#define DFLL_CALL6_bp  6  /* DFLL Calibration Value A bit 6 position. */
+
+/* DFLL.CALB  bit masks and bit positions */
+#define DFLL_CALH_gm  0x3F  /* DFLL Calibration Value B group mask. */
+#define DFLL_CALH_gp  0  /* DFLL Calibration Value B group position. */
+#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration Value B bit 0 mask. */
+#define DFLL_CALH0_bp  0  /* DFLL Calibration Value B bit 0 position. */
+#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration Value B bit 1 mask. */
+#define DFLL_CALH1_bp  1  /* DFLL Calibration Value B bit 1 position. */
+#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration Value B bit 2 mask. */
+#define DFLL_CALH2_bp  2  /* DFLL Calibration Value B bit 2 position. */
+#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration Value B bit 3 mask. */
+#define DFLL_CALH3_bp  3  /* DFLL Calibration Value B bit 3 position. */
+#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration Value B bit 4 mask. */
+#define DFLL_CALH4_bp  4  /* DFLL Calibration Value B bit 4 position. */
+#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration Value B bit 5 mask. */
+#define DFLL_CALH5_bp  5  /* DFLL Calibration Value B bit 5 position. */
+
+
+
+
+/* DMA - DMA Controller */
+/* DMA_CH.CTRLA  bit masks and bit positions */
+#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
+#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
+#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
+#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
+#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
+#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
+#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
+#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
+#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
+#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
+#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
+#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
+#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
+#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
+#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
+#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
+
+/* DMA_CH.CTRLB  bit masks and bit positions */
+#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
+#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
+#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
+#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
+#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
+#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
+#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
+#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
+#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
+#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
+#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
+#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
+#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
+#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
+#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
+#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
+
+/* DMA_CH.ADDRCTRL  bit masks and bit positions */
+#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
+#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
+#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
+#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
+#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
+#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
+#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
+#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
+#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
+#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
+#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
+#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
+#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
+#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
+#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
+#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
+#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
+#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
+#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
+#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
+#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
+#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
+#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
+#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
+
+/* DMA_CH.TRIGSRC  bit masks and bit positions */
+#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
+#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
+#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
+#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
+#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
+#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
+#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
+#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
+#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
+#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
+#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
+#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
+#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
+#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
+#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
+#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
+#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
+#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
+
+
+
+
+
+
+
+
+
+/* DMA.CTRL  bit masks and bit positions */
+#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
+#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
+#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
+#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
+#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
+#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
+#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
+#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
+#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
+#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
+#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
+#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
+#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
+#define DMA_RESET_bp  6  /* Software Reset bit position. */
+#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
+#define DMA_ENABLE_bp  7  /* Enable bit position. */
+
+/* DMA.INTFLAGS  bit masks and bit positions */
+#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
+
+/* DMA.STATUS  bit masks and bit positions */
+#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
+#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
+#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
+#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
+#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
+#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
+#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
+#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
+#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
+#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
+#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
+#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
+#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
+#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
+#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
+#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
+
+
+/* EVSYS - Event System */
+/* EVSYS.CH0MUX  bit masks and bit positions */
+#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
+#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
+#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
+#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
+#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
+#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
+#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
+#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
+#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
+#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
+#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
+#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
+#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
+#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
+#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
+#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
+#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
+#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
+
+/* EVSYS.CH1MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH2MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH3MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH4MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH5MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH6MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH7MUX  bit masks and bit positions */
+/* EVSYS_CHMUX  is already defined. */
+
+/* EVSYS.CH0CTRL  bit masks and bit positions */
+#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
+#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
+#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
+#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
+#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
+#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
+#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
+#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
+#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
+#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
+#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
+#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
+#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
+#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
+#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
+#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
+#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
+#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
+
+/* EVSYS.CH1CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+
+/* EVSYS.CH2CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+/* EVSYS_QDEN  is already defined. */
+/* EVSYS_QDIEN  is already defined. */
+/* EVSYS_QDIRM  is already defined. */
+
+/* EVSYS.CH3CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+
+/* EVSYS.CH4CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+/* EVSYS_QDEN  is already defined. */
+/* EVSYS_QDIEN  is already defined. */
+/* EVSYS_QDIRM  is already defined. */
+
+/* EVSYS.CH5CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+
+/* EVSYS.CH6CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+
+/* EVSYS.CH7CTRL  bit masks and bit positions */
+/* EVSYS_DIGFILT  is already defined. */
+
+
+
+/* FUSE - Fuses and Lockbits */
+/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
+#define NVM_FUSES_JTAGUID_gm  0xFF  /* JTAG User ID group mask. */
+#define NVM_FUSES_JTAGUID_gp  0  /* JTAG User ID group position. */
+#define NVM_FUSES_JTAGUID0_bm  (1<<0)  /* JTAG User ID bit 0 mask. */
+#define NVM_FUSES_JTAGUID0_bp  0  /* JTAG User ID bit 0 position. */
+#define NVM_FUSES_JTAGUID1_bm  (1<<1)  /* JTAG User ID bit 1 mask. */
+#define NVM_FUSES_JTAGUID1_bp  1  /* JTAG User ID bit 1 position. */
+#define NVM_FUSES_JTAGUID2_bm  (1<<2)  /* JTAG User ID bit 2 mask. */
+#define NVM_FUSES_JTAGUID2_bp  2  /* JTAG User ID bit 2 position. */
+#define NVM_FUSES_JTAGUID3_bm  (1<<3)  /* JTAG User ID bit 3 mask. */
+#define NVM_FUSES_JTAGUID3_bp  3  /* JTAG User ID bit 3 position. */
+#define NVM_FUSES_JTAGUID4_bm  (1<<4)  /* JTAG User ID bit 4 mask. */
+#define NVM_FUSES_JTAGUID4_bp  4  /* JTAG User ID bit 4 position. */
+#define NVM_FUSES_JTAGUID5_bm  (1<<5)  /* JTAG User ID bit 5 mask. */
+#define NVM_FUSES_JTAGUID5_bp  5  /* JTAG User ID bit 5 position. */
+#define NVM_FUSES_JTAGUID6_bm  (1<<6)  /* JTAG User ID bit 6 mask. */
+#define NVM_FUSES_JTAGUID6_bp  6  /* JTAG User ID bit 6 position. */
+#define NVM_FUSES_JTAGUID7_bm  (1<<7)  /* JTAG User ID bit 7 mask. */
+#define NVM_FUSES_JTAGUID7_bp  7  /* JTAG User ID bit 7 position. */
+
+/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
+#define NVM_FUSES_WDPER_gm  0x0F  /* Watchdog Timeout Period group mask. */
+#define NVM_FUSES_WDPER_gp  0  /* Watchdog Timeout Period group position. */
+#define NVM_FUSES_WDPER0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDPER0_bp  0  /* Watchdog Timeout Period bit 0 position. */
+#define NVM_FUSES_WDPER1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDPER1_bp  1  /* Watchdog Timeout Period bit 1 position. */
+#define NVM_FUSES_WDPER2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDPER2_bp  2  /* Watchdog Timeout Period bit 2 position. */
+#define NVM_FUSES_WDPER3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDPER3_bp  3  /* Watchdog Timeout Period bit 3 position. */
+#define NVM_FUSES_WDWPER_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
+#define NVM_FUSES_WDWPER_gp  4  /* Watchdog Window Timeout Period group position. */
+#define NVM_FUSES_WDWPER0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDWPER0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
+#define NVM_FUSES_WDWPER1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDWPER1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
+#define NVM_FUSES_WDWPER2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDWPER2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
+#define NVM_FUSES_WDWPER3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDWPER3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
+
+/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
+#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
+#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
+#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
+#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
+#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
+#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
+#define NVM_FUSES_TOSCSEL_bm  0x20  /* Timer Oscillator pin location bit mask. */
+#define NVM_FUSES_TOSCSEL_bp  5  /* Timer Oscillator pin location bit position. */
+#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
+#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
+
+/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
+#define NVM_FUSES_JTAGEN_bm  0x01  /* JTAG Interface Enable bit mask. */
+#define NVM_FUSES_JTAGEN_bp  0  /* JTAG Interface Enable bit position. */
+#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
+#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
+#define NVM_FUSES_STARTUPTIME_gm  0x0C  /* Start-up Time group mask. */
+#define NVM_FUSES_STARTUPTIME_gp  2  /* Start-up Time group position. */
+#define NVM_FUSES_STARTUPTIME0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
+#define NVM_FUSES_STARTUPTIME0_bp  2  /* Start-up Time bit 0 position. */
+#define NVM_FUSES_STARTUPTIME1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
+#define NVM_FUSES_STARTUPTIME1_bp  3  /* Start-up Time bit 1 position. */
+#define NVM_FUSES_RSTDISBL_bm  0x10  /* External Reset Disable bit mask. */
+#define NVM_FUSES_RSTDISBL_bp  4  /* External Reset Disable bit position. */
+
+/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
+#define NVM_FUSES_BODLVL_gm  0x07  /* Brownout Detection Voltage Level group mask. */
+#define NVM_FUSES_BODLVL_gp  0  /* Brownout Detection Voltage Level group position. */
+#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brownout Detection Voltage Level bit 0 mask. */
+#define NVM_FUSES_BODLVL0_bp  0  /* Brownout Detection Voltage Level bit 0 position. */
+#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brownout Detection Voltage Level bit 1 mask. */
+#define NVM_FUSES_BODLVL1_bp  1  /* Brownout Detection Voltage Level bit 1 position. */
+#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brownout Detection Voltage Level bit 2 mask. */
+#define NVM_FUSES_BODLVL2_bp  2  /* Brownout Detection Voltage Level bit 2 position. */
+#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
+#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
+#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
+#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
+#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
+#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
+#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
+#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+/* HIRES - Timer/Counter High-Resolution Extension */
+/* HIRES.CTRLA  bit masks and bit positions */
+#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
+#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
+#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
+#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
+#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
+#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
+#define HIRES_HRPLUS_bm  0x04  /* High Resolution Plus bit mask. */
+#define HIRES_HRPLUS_bp  2  /* High Resolution Plus bit position. */
+
+/* IRCOM - IR Communication Module */
+/* IRCOM.CTRL  bit masks and bit positions */
+#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
+#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
+#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
+#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
+#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
+#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
+#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
+#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
+#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
+#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
+
+
+
+/* LOCKBIT - Fuses and Lockbits */
+/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
+#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
+#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
+#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
+#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
+#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
+#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
+#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
+#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
+#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
+#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
+#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
+#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
+#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
+#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
+
+
+
+
+
+
+/* MCU - MCU Control */
+/* MCU.MCUCR  bit masks and bit positions */
+#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
+#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
+
+/* MCU.ANAINIT  bit masks and bit positions */
+#define MCU_STARTUPDLYA_gm  0x03  /* Analog startup delay Port A group mask. */
+#define MCU_STARTUPDLYA_gp  0  /* Analog startup delay Port A group position. */
+#define MCU_STARTUPDLYA0_bm  (1<<0)  /* Analog startup delay Port A bit 0 mask. */
+#define MCU_STARTUPDLYA0_bp  0  /* Analog startup delay Port A bit 0 position. */
+#define MCU_STARTUPDLYA1_bm  (1<<1)  /* Analog startup delay Port A bit 1 mask. */
+#define MCU_STARTUPDLYA1_bp  1  /* Analog startup delay Port A bit 1 position. */
+#define MCU_STARTUPDLYB_gm  0x0C  /* Analog startup delay Port B group mask. */
+#define MCU_STARTUPDLYB_gp  2  /* Analog startup delay Port B group position. */
+#define MCU_STARTUPDLYB0_bm  (1<<2)  /* Analog startup delay Port B bit 0 mask. */
+#define MCU_STARTUPDLYB0_bp  2  /* Analog startup delay Port B bit 0 position. */
+#define MCU_STARTUPDLYB1_bm  (1<<3)  /* Analog startup delay Port B bit 1 mask. */
+#define MCU_STARTUPDLYB1_bp  3  /* Analog startup delay Port B bit 1 position. */
+
+/* MCU.EVSYSLOCK  bit masks and bit positions */
+#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
+#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
+#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
+#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
+
+/* MCU.AWEXLOCK  bit masks and bit positions */
+#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
+#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
+#define MCU_AWEXDLOCK_bm  0x02  /* AWeX on T/C D0 Lock bit mask. */
+#define MCU_AWEXDLOCK_bp  1  /* AWeX on T/C D0 Lock bit position. */
+#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
+#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
+#define MCU_AWEXFLOCK_bm  0x08  /* AWeX on T/C F0 Lock bit mask. */
+#define MCU_AWEXFLOCK_bp  3  /* AWeX on T/C F0 Lock bit position. */
+
+
+
+
+
+
+
+/* NVM - Non Volatile Memory Controller */
+/* NVM.CMD  bit masks and bit positions */
+#define NVM_CMD_gm  0x7F  /* Command group mask. */
+#define NVM_CMD_gp  0  /* Command group position. */
+#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
+#define NVM_CMD0_bp  0  /* Command bit 0 position. */
+#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
+#define NVM_CMD1_bp  1  /* Command bit 1 position. */
+#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
+#define NVM_CMD2_bp  2  /* Command bit 2 position. */
+#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
+#define NVM_CMD3_bp  3  /* Command bit 3 position. */
+#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
+#define NVM_CMD4_bp  4  /* Command bit 4 position. */
+#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
+#define NVM_CMD5_bp  5  /* Command bit 5 position. */
+#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
+#define NVM_CMD6_bp  6  /* Command bit 6 position. */
+
+/* NVM.CTRLA  bit masks and bit positions */
+#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
+#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
+
+/* NVM.CTRLB  bit masks and bit positions */
+#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
+#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
+#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
+#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
+#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
+#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
+#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
+#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
+
+/* NVM.INTCTRL  bit masks and bit positions */
+#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
+#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
+#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
+#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
+#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
+#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
+#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
+#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
+#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
+#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
+#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
+#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
+
+/* NVM.STATUS  bit masks and bit positions */
+#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
+#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
+#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
+#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
+#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
+#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
+#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
+#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
+
+/* NVM.LOCKBITS  bit masks and bit positions */
+#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
+#define NVM_LB_gp  0  /* Lock Bits group position. */
+#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
+#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
+#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
+#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
+#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
+#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
+#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
+#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
+#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
+#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
+#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
+#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
+
+/* OSC - Oscillator */
+/* OSC.CTRL  bit masks and bit positions */
+#define OSC_RC2MEN_bm  0x01  /* Internal 2 MHz RC Oscillator Enable bit mask. */
+#define OSC_RC2MEN_bp  0  /* Internal 2 MHz RC Oscillator Enable bit position. */
+#define OSC_RC32MEN_bm  0x02  /* Internal 32 MHz RC Oscillator Enable bit mask. */
+#define OSC_RC32MEN_bp  1  /* Internal 32 MHz RC Oscillator Enable bit position. */
+#define OSC_RC32KEN_bm  0x04  /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
+#define OSC_RC32KEN_bp  2  /* Internal 32.768 kHz RC Oscillator Enable bit position. */
+#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
+#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
+#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
+#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
+
+/* OSC.STATUS  bit masks and bit positions */
+#define OSC_RC2MRDY_bm  0x01  /* Internal 2 MHz RC Oscillator Ready bit mask. */
+#define OSC_RC2MRDY_bp  0  /* Internal 2 MHz RC Oscillator Ready bit position. */
+#define OSC_RC32MRDY_bm  0x02  /* Internal 32 MHz RC Oscillator Ready bit mask. */
+#define OSC_RC32MRDY_bp  1  /* Internal 32 MHz RC Oscillator Ready bit position. */
+#define OSC_RC32KRDY_bm  0x04  /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
+#define OSC_RC32KRDY_bp  2  /* Internal 32.768 kHz RC Oscillator Ready bit position. */
+#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
+#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
+#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
+#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
+
+/* OSC.XOSCCTRL  bit masks and bit positions */
+#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
+#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
+#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
+#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
+#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
+#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
+#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
+#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
+#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
+#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
+#define OSC_XOSCPWR_bm  0x10  /* 16 MHz Crystal Oscillator High Power mode bit mask. */
+#define OSC_XOSCPWR_bp  4  /* 16 MHz Crystal Oscillator High Power mode bit position. */
+#define OSC_X32KLPM_bm  0x20  /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
+#define OSC_X32KLPM_bp  5  /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
+#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
+#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
+#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
+#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
+#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
+#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
+
+/* OSC.XOSCFAIL  bit masks and bit positions */
+#define OSC_XOSCFDEN_bm  0x01  /* XOSC Failure Detection Enable bit mask. */
+#define OSC_XOSCFDEN_bp  0  /* XOSC Failure Detection Enable bit position. */
+#define OSC_XOSCFDIF_bm  0x02  /* XOSC Failure Detection Interrupt Flag bit mask. */
+#define OSC_XOSCFDIF_bp  1  /* XOSC Failure Detection Interrupt Flag bit position. */
+#define OSC_PLLFDEN_bm  0x04  /* PLL Failure Detection Enable bit mask. */
+#define OSC_PLLFDEN_bp  2  /* PLL Failure Detection Enable bit position. */
+#define OSC_PLLFDIF_bm  0x08  /* PLL Failure Detection Interrupt Flag bit mask. */
+#define OSC_PLLFDIF_bp  3  /* PLL Failure Detection Interrupt Flag bit position. */
+
+
+/* OSC.PLLCTRL  bit masks and bit positions */
+#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
+#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
+#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
+#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
+#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
+#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
+#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
+#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
+#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
+#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
+#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
+#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
+#define OSC_PLLDIV_bm  0x20  /* Divide by 2 bit mask. */
+#define OSC_PLLDIV_bp  5  /* Divide by 2 bit position. */
+#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
+#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
+#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
+#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
+#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
+#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
+
+/* OSC.DFLLCTRL  bit masks and bit positions */
+#define OSC_RC2MCREF_bm  0x01  /* 2 MHz DFLL Calibration Reference bit mask. */
+#define OSC_RC2MCREF_bp  0  /* 2 MHz DFLL Calibration Reference bit position. */
+#define OSC_RC32MCREF_gm  0x06  /* 32 MHz DFLL Calibration Reference group mask. */
+#define OSC_RC32MCREF_gp  1  /* 32 MHz DFLL Calibration Reference group position. */
+#define OSC_RC32MCREF0_bm  (1<<1)  /* 32 MHz DFLL Calibration Reference bit 0 mask. */
+#define OSC_RC32MCREF0_bp  1  /* 32 MHz DFLL Calibration Reference bit 0 position. */
+#define OSC_RC32MCREF1_bm  (1<<2)  /* 32 MHz DFLL Calibration Reference bit 1 mask. */
+#define OSC_RC32MCREF1_bp  2  /* 32 MHz DFLL Calibration Reference bit 1 position. */
+
+/* PMIC - Programmable Multi-level Interrupt Controller */
+/* PMIC.STATUS  bit masks and bit positions */
+#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
+#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
+#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
+#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
+#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
+#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
+#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
+#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
+
+/* PMIC.INTPRI  bit masks and bit positions */
+#define PMIC_INTPRI_gm  0xFF  /* Interrupt Priority group mask. */
+#define PMIC_INTPRI_gp  0  /* Interrupt Priority group position. */
+#define PMIC_INTPRI0_bm  (1<<0)  /* Interrupt Priority bit 0 mask. */
+#define PMIC_INTPRI0_bp  0  /* Interrupt Priority bit 0 position. */
+#define PMIC_INTPRI1_bm  (1<<1)  /* Interrupt Priority bit 1 mask. */
+#define PMIC_INTPRI1_bp  1  /* Interrupt Priority bit 1 position. */
+#define PMIC_INTPRI2_bm  (1<<2)  /* Interrupt Priority bit 2 mask. */
+#define PMIC_INTPRI2_bp  2  /* Interrupt Priority bit 2 position. */
+#define PMIC_INTPRI3_bm  (1<<3)  /* Interrupt Priority bit 3 mask. */
+#define PMIC_INTPRI3_bp  3  /* Interrupt Priority bit 3 position. */
+#define PMIC_INTPRI4_bm  (1<<4)  /* Interrupt Priority bit 4 mask. */
+#define PMIC_INTPRI4_bp  4  /* Interrupt Priority bit 4 position. */
+#define PMIC_INTPRI5_bm  (1<<5)  /* Interrupt Priority bit 5 mask. */
+#define PMIC_INTPRI5_bp  5  /* Interrupt Priority bit 5 position. */
+#define PMIC_INTPRI6_bm  (1<<6)  /* Interrupt Priority bit 6 mask. */
+#define PMIC_INTPRI6_bp  6  /* Interrupt Priority bit 6 position. */
+#define PMIC_INTPRI7_bm  (1<<7)  /* Interrupt Priority bit 7 mask. */
+#define PMIC_INTPRI7_bp  7  /* Interrupt Priority bit 7 position. */
+
+/* PMIC.CTRL  bit masks and bit positions */
+#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
+#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
+#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
+#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
+#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
+#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
+#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
+#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
+#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
+#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
+
+
+
+
+
+
+
+
+
+
+/* PORT - I/O Port Configuration */
+/* PORT.INTCTRL  bit masks and bit positions */
+#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
+#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
+#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
+#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
+#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
+#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
+#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
+#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
+#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
+#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
+#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
+#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
+
+
+
+/* PORT.INTFLAGS  bit masks and bit positions */
+#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
+#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
+#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
+#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
+
+/* PORT.REMAP  bit masks and bit positions */
+#define PORT_TC0A_bm  0x01  /* Timer/Counter 0 Output Compare A bit mask. */
+#define PORT_TC0A_bp  0  /* Timer/Counter 0 Output Compare A bit position. */
+#define PORT_TC0B_bm  0x02  /* Timer/Counter 0 Output Compare B bit mask. */
+#define PORT_TC0B_bp  1  /* Timer/Counter 0 Output Compare B bit position. */
+#define PORT_TC0C_bm  0x04  /* Timer/Counter 0 Output Compare C bit mask. */
+#define PORT_TC0C_bp  2  /* Timer/Counter 0 Output Compare C bit position. */
+#define PORT_TC0D_bm  0x08  /* Timer/Counter 0 Output Compare D bit mask. */
+#define PORT_TC0D_bp  3  /* Timer/Counter 0 Output Compare D bit position. */
+#define PORT_USART0_bm  0x10  /* USART0 bit mask. */
+#define PORT_USART0_bp  4  /* USART0 bit position. */
+#define PORT_SPI_bm  0x20  /* SPI bit mask. */
+#define PORT_SPI_bp  5  /* SPI bit position. */
+
+/* PORT.PIN0CTRL  bit masks and bit positions */
+#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
+#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
+#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
+#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
+#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
+#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
+#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
+#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
+#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
+#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
+#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
+#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
+#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
+#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
+#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
+#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
+#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
+#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
+#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
+#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
+
+/* PORT.PIN1CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN2CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN3CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN4CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN5CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN6CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+/* PORT.PIN7CTRL  bit masks and bit positions */
+/* PORT_ISC  is already defined. */
+/* PORT_OPC  is already defined. */
+/* PORT_INVEN  is already defined. */
+/* PORT_SRLEN  is already defined. */
+
+
+/* PORTCFG - Port Configuration */
+/* PORTCFG.VPCTRLA  bit masks and bit positions */
+#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
+#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
+#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
+#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
+#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
+#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
+#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
+#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
+#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
+#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
+#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
+#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
+#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
+#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
+#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
+#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
+#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
+#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
+#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
+#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
+
+/* PORTCFG.VPCTRLB  bit masks and bit positions */
+#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
+#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
+#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
+#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
+#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
+#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
+#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
+#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
+#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
+#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
+#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
+#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
+#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
+#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
+#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
+#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
+#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
+#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
+#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
+#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
+
+/* PORTCFG.CLKEVOUT  bit masks and bit positions */
+#define PORTCFG_CLKOUT_gm  0x03  /* Peripheral Clock Output Port group mask. */
+#define PORTCFG_CLKOUT_gp  0  /* Peripheral Clock Output Port group position. */
+#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Peripheral Clock Output Port bit 0 mask. */
+#define PORTCFG_CLKOUT0_bp  0  /* Peripheral Clock Output Port bit 0 position. */
+#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Peripheral Clock Output Port bit 1 mask. */
+#define PORTCFG_CLKOUT1_bp  1  /* Peripheral Clock Output Port bit 1 position. */
+#define PORTCFG_CLKOUTSEL_gm  0x0C  /* Peripheral Clock Output Select group mask. */
+#define PORTCFG_CLKOUTSEL_gp  2  /* Peripheral Clock Output Select group position. */
+#define PORTCFG_CLKOUTSEL0_bm  (1<<2)  /* Peripheral Clock Output Select bit 0 mask. */
+#define PORTCFG_CLKOUTSEL0_bp  2  /* Peripheral Clock Output Select bit 0 position. */
+#define PORTCFG_CLKOUTSEL1_bm  (1<<3)  /* Peripheral Clock Output Select bit 1 mask. */
+#define PORTCFG_CLKOUTSEL1_bp  3  /* Peripheral Clock Output Select bit 1 position. */
+#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
+#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
+#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
+#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
+#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
+#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
+#define PORTCFG_RTCOUT_bm  0x40  /* RTC Clock Output bit mask. */
+#define PORTCFG_RTCOUT_bp  6  /* RTC Clock Output bit position. */
+#define PORTCFG_CLKEVPIN_bm  0x80  /* Peripheral Clock and Event Output pin Select bit mask. */
+#define PORTCFG_CLKEVPIN_bp  7  /* Peripheral Clock and Event Output pin Select bit position. */
+
+/* PORTCFG.EVOUTSEL  bit masks and bit positions */
+#define PORTCFG_EVOUTSEL_gm  0x07  /* Event Output Select group mask. */
+#define PORTCFG_EVOUTSEL_gp  0  /* Event Output Select group position. */
+#define PORTCFG_EVOUTSEL0_bm  (1<<0)  /* Event Output Select bit 0 mask. */
+#define PORTCFG_EVOUTSEL0_bp  0  /* Event Output Select bit 0 position. */
+#define PORTCFG_EVOUTSEL1_bm  (1<<1)  /* Event Output Select bit 1 mask. */
+#define PORTCFG_EVOUTSEL1_bp  1  /* Event Output Select bit 1 position. */
+#define PORTCFG_EVOUTSEL2_bm  (1<<2)  /* Event Output Select bit 2 mask. */
+#define PORTCFG_EVOUTSEL2_bp  2  /* Event Output Select bit 2 position. */
+
+/* PR - Power Reduction */
+/* PR.PRGEN  bit masks and bit positions */
+#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
+#define PR_DMA_bp  0  /* DMA-Controller bit position. */
+#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
+#define PR_EVSYS_bp  1  /* Event System bit position. */
+#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
+#define PR_RTC_bp  2  /* Real-time Counter bit position. */
+#define PR_AES_bm  0x10  /* AES bit mask. */
+#define PR_AES_bp  4  /* AES bit position. */
+#define PR_USB_bm  0x40  /* USB bit mask. */
+#define PR_USB_bp  6  /* USB bit position. */
+
+/* PR.PRPA  bit masks and bit positions */
+#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
+#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
+#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
+#define PR_ADC_bp  1  /* Port A ADC bit position. */
+#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
+#define PR_DAC_bp  2  /* Port A DAC bit position. */
+
+/* PR.PRPB  bit masks and bit positions */
+/* PR_AC  is already defined. */
+/* PR_ADC  is already defined. */
+/* PR_DAC  is already defined. */
+
+/* PR.PRPC  bit masks and bit positions */
+#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
+#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
+#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
+#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
+#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
+#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
+#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
+#define PR_SPI_bp  3  /* Port C SPI bit position. */
+#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
+#define PR_USART0_bp  4  /* Port C USART0 bit position. */
+#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
+#define PR_USART1_bp  5  /* Port C USART1 bit position. */
+#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
+#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
+
+/* PR.PRPD  bit masks and bit positions */
+/* PR_TC0  is already defined. */
+/* PR_TC1  is already defined. */
+/* PR_HIRES  is already defined. */
+/* PR_SPI  is already defined. */
+/* PR_USART0  is already defined. */
+/* PR_USART1  is already defined. */
+/* PR_TWI  is already defined. */
+
+/* PR.PRPE  bit masks and bit positions */
+/* PR_TC0  is already defined. */
+/* PR_TC1  is already defined. */
+/* PR_HIRES  is already defined. */
+/* PR_SPI  is already defined. */
+/* PR_USART0  is already defined. */
+/* PR_USART1  is already defined. */
+/* PR_TWI  is already defined. */
+
+/* PR.PRPF  bit masks and bit positions */
+/* PR_TC0  is already defined. */
+/* PR_TC1  is already defined. */
+/* PR_HIRES  is already defined. */
+/* PR_SPI  is already defined. */
+/* PR_USART0  is already defined. */
+/* PR_USART1  is already defined. */
+/* PR_TWI  is already defined. */
+
+/* RST - Reset */
+/* RST.STATUS  bit masks and bit positions */
+#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
+#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
+#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
+#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
+#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
+#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
+#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
+#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
+#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
+#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
+#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
+#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
+#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
+#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
+
+/* RST.CTRL  bit masks and bit positions */
+#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
+#define RST_SWRST_bp  0  /* Software Reset bit position. */
+
+/* RTC - Real-Time Counter */
+/* RTC.CTRL  bit masks and bit positions */
+#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
+#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
+#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
+#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
+#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
+#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
+#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
+#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
+
+/* RTC.STATUS  bit masks and bit positions */
+#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
+#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
+
+/* RTC.INTCTRL  bit masks and bit positions */
+#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
+#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
+#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
+#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
+#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
+#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
+#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
+#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
+#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
+#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
+#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
+#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
+
+/* RTC.INTFLAGS  bit masks and bit positions */
+#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
+#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
+#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
+#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+/* SLEEP - Sleep Controller */
+/* SLEEP.CTRL  bit masks and bit positions */
+#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
+#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
+#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
+#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
+#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
+#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
+#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
+#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
+#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
+#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
+
+/* SPI - Serial Peripheral Interface */
+/* SPI.CTRL  bit masks and bit positions */
+#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
+#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
+#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
+#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
+#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
+#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
+#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
+#define SPI_MODE_gp  2  /* SPI Mode group position. */
+#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
+#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
+#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
+#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
+#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
+#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
+#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
+#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
+#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
+#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
+#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
+#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
+
+/* SPI.INTCTRL  bit masks and bit positions */
+#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
+#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
+#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
+#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
+#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
+#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
+
+/* SPI.STATUS  bit masks and bit positions */
+#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
+#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
+#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
+#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
+
+
+/* TC - 16-bit Timer/Counter With PWM */
+/* TC0.CTRLA  bit masks and bit positions */
+#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
+#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
+#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
+#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
+#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
+#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
+#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
+#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
+#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
+#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
+
+/* TC0.CTRLB  bit masks and bit positions */
+#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
+#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
+#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
+#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
+#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
+#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
+#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
+#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
+#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
+#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
+#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
+#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
+#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
+#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
+#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
+#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
+
+/* TC0.CTRLC  bit masks and bit positions */
+#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
+#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
+#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
+#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
+#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
+#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
+#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
+#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
+
+/* TC0.CTRLD  bit masks and bit positions */
+#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
+#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
+#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
+#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
+#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
+#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
+#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
+#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
+#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
+#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
+#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
+#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
+#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
+#define TC0_EVACT_gp  5  /* Event Action group position. */
+#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
+#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
+#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
+#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
+#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
+#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
+
+/* TC0.CTRLE  bit masks and bit positions */
+#define TC0_BYTEM_gm  0x03  /* Byte Mode group mask. */
+#define TC0_BYTEM_gp  0  /* Byte Mode group position. */
+#define TC0_BYTEM0_bm  (1<<0)  /* Byte Mode bit 0 mask. */
+#define TC0_BYTEM0_bp  0  /* Byte Mode bit 0 position. */
+#define TC0_BYTEM1_bm  (1<<1)  /* Byte Mode bit 1 mask. */
+#define TC0_BYTEM1_bp  1  /* Byte Mode bit 1 position. */
+
+/* TC0.INTCTRLA  bit masks and bit positions */
+#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
+#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
+#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
+#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
+#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
+#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
+#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
+#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
+#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
+#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
+#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
+#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
+
+/* TC0.INTCTRLB  bit masks and bit positions */
+#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
+#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
+#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
+#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
+#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
+#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
+#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
+#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
+#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
+#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
+#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
+#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
+#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
+#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
+#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
+#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
+#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
+#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
+
+/* TC0.CTRLFCLR  bit masks and bit positions */
+#define TC0_DIR_bm  0x01  /* Direction bit mask. */
+#define TC0_DIR_bp  0  /* Direction bit position. */
+#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
+#define TC0_LUPD_bp  1  /* Lock Update bit position. */
+#define TC0_CMD_gm  0x0C  /* Command group mask. */
+#define TC0_CMD_gp  2  /* Command group position. */
+#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
+#define TC0_CMD0_bp  2  /* Command bit 0 position. */
+#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
+#define TC0_CMD1_bp  3  /* Command bit 1 position. */
+
+/* TC0.CTRLFSET  bit masks and bit positions */
+/* TC0_DIR  is already defined. */
+/* TC0_LUPD  is already defined. */
+/* TC0_CMD  is already defined. */
+
+/* TC0.CTRLGCLR  bit masks and bit positions */
+#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
+#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
+#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
+#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
+#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
+#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
+#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
+#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
+#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
+#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
+
+/* TC0.CTRLGSET  bit masks and bit positions */
+/* TC0_PERBV  is already defined. */
+/* TC0_CCABV  is already defined. */
+/* TC0_CCBBV  is already defined. */
+/* TC0_CCCBV  is already defined. */
+/* TC0_CCDBV  is already defined. */
+
+/* TC0.INTFLAGS  bit masks and bit positions */
+#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
+#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
+#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
+#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
+#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
+#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
+#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
+#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
+#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
+#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
+
+
+
+
+
+
+
+
+
+
+
+
+
+/* TC1.CTRLA  bit masks and bit positions */
+#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
+#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
+#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
+#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
+#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
+#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
+#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
+#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
+#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
+#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
+
+/* TC1.CTRLB  bit masks and bit positions */
+#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
+#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
+#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
+#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
+#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
+#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
+#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
+#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
+#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
+#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
+#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
+#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
+
+/* TC1.CTRLC  bit masks and bit positions */
+#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
+#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
+#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
+#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
+
+/* TC1.CTRLD  bit masks and bit positions */
+#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
+#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
+#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
+#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
+#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
+#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
+#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
+#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
+#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
+#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
+#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
+#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
+#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
+#define TC1_EVACT_gp  5  /* Event Action group position. */
+#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
+#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
+#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
+#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
+#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
+#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
+
+/* TC1.CTRLE  bit masks and bit positions */
+#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
+#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
+
+/* TC1.INTCTRLA  bit masks and bit positions */
+#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
+#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
+#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
+#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
+#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
+#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
+#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
+#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
+#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
+#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
+#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
+#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
+
+/* TC1.INTCTRLB  bit masks and bit positions */
+#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
+#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
+#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
+#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
+#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
+#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
+
+/* TC1.CTRLFCLR  bit masks and bit positions */
+#define TC1_DIR_bm  0x01  /* Direction bit mask. */
+#define TC1_DIR_bp  0  /* Direction bit position. */
+#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
+#define TC1_LUPD_bp  1  /* Lock Update bit position. */
+#define TC1_CMD_gm  0x0C  /* Command group mask. */
+#define TC1_CMD_gp  2  /* Command group position. */
+#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
+#define TC1_CMD0_bp  2  /* Command bit 0 position. */
+#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
+#define TC1_CMD1_bp  3  /* Command bit 1 position. */
+
+/* TC1.CTRLFSET  bit masks and bit positions */
+/* TC1_DIR  is already defined. */
+/* TC1_LUPD  is already defined. */
+/* TC1_CMD  is already defined. */
+
+/* TC1.CTRLGCLR  bit masks and bit positions */
+#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
+#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
+#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
+#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
+#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
+#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
+
+/* TC1.CTRLGSET  bit masks and bit positions */
+/* TC1_PERBV  is already defined. */
+/* TC1_CCABV  is already defined. */
+/* TC1_CCBBV  is already defined. */
+
+/* TC1.INTFLAGS  bit masks and bit positions */
+#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
+#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
+#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
+#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
+#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
+#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
+
+
+
+
+
+
+
+
+
+/* TC2 - 16-bit Timer/Counter type 2 */
+/* TC2.CTRLA  bit masks and bit positions */
+#define TC2_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
+#define TC2_CLKSEL_gp  0  /* Clock Selection group position. */
+#define TC2_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
+#define TC2_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
+#define TC2_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
+#define TC2_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
+#define TC2_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
+#define TC2_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
+#define TC2_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
+#define TC2_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
+
+/* TC2.CTRLB  bit masks and bit positions */
+#define TC2_LCMPAEN_bm  0x01  /* Low Byte Compare A Enable bit mask. */
+#define TC2_LCMPAEN_bp  0  /* Low Byte Compare A Enable bit position. */
+#define TC2_LCMPBEN_bm  0x02  /* Low Byte Compare B Enable bit mask. */
+#define TC2_LCMPBEN_bp  1  /* Low Byte Compare B Enable bit position. */
+#define TC2_LCMPCEN_bm  0x04  /* Low Byte Compare C Enable bit mask. */
+#define TC2_LCMPCEN_bp  2  /* Low Byte Compare C Enable bit position. */
+#define TC2_LCMPDEN_bm  0x08  /* Low Byte Compare D Enable bit mask. */
+#define TC2_LCMPDEN_bp  3  /* Low Byte Compare D Enable bit position. */
+#define TC2_HCMPAEN_bm  0x10  /* High Byte Compare A Enable bit mask. */
+#define TC2_HCMPAEN_bp  4  /* High Byte Compare A Enable bit position. */
+#define TC2_HCMPBEN_bm  0x20  /* High Byte Compare B Enable bit mask. */
+#define TC2_HCMPBEN_bp  5  /* High Byte Compare B Enable bit position. */
+#define TC2_HCMPCEN_bm  0x40  /* High Byte Compare C Enable bit mask. */
+#define TC2_HCMPCEN_bp  6  /* High Byte Compare C Enable bit position. */
+#define TC2_HCMPDEN_bm  0x80  /* High Byte Compare D Enable bit mask. */
+#define TC2_HCMPDEN_bp  7  /* High Byte Compare D Enable bit position. */
+
+/* TC2.CTRLC  bit masks and bit positions */
+#define TC2_LCMPA_bm  0x01  /* Low Byte Compare A Output Value bit mask. */
+#define TC2_LCMPA_bp  0  /* Low Byte Compare A Output Value bit position. */
+#define TC2_LCMPB_bm  0x02  /* Low Byte Compare B Output Value bit mask. */
+#define TC2_LCMPB_bp  1  /* Low Byte Compare B Output Value bit position. */
+#define TC2_LCMPC_bm  0x04  /* Low Byte Compare C Output Value bit mask. */
+#define TC2_LCMPC_bp  2  /* Low Byte Compare C Output Value bit position. */
+#define TC2_LCMPD_bm  0x08  /* Low Byte Compare D Output Value bit mask. */
+#define TC2_LCMPD_bp  3  /* Low Byte Compare D Output Value bit position. */
+#define TC2_HCMPA_bm  0x10  /* High Byte Compare A Output Value bit mask. */
+#define TC2_HCMPA_bp  4  /* High Byte Compare A Output Value bit position. */
+#define TC2_HCMPB_bm  0x20  /* High Byte Compare B Output Value bit mask. */
+#define TC2_HCMPB_bp  5  /* High Byte Compare B Output Value bit position. */
+#define TC2_HCMPC_bm  0x40  /* High Byte Compare C Output Value bit mask. */
+#define TC2_HCMPC_bp  6  /* High Byte Compare C Output Value bit position. */
+#define TC2_HCMPD_bm  0x80  /* High Byte Compare D Output Value bit mask. */
+#define TC2_HCMPD_bp  7  /* High Byte Compare D Output Value bit position. */
+
+/* TC2.CTRLE  bit masks and bit positions */
+#define TC2_BYTEM_gm  0x03  /* Byte Mode group mask. */
+#define TC2_BYTEM_gp  0  /* Byte Mode group position. */
+#define TC2_BYTEM0_bm  (1<<0)  /* Byte Mode bit 0 mask. */
+#define TC2_BYTEM0_bp  0  /* Byte Mode bit 0 position. */
+#define TC2_BYTEM1_bm  (1<<1)  /* Byte Mode bit 1 mask. */
+#define TC2_BYTEM1_bp  1  /* Byte Mode bit 1 position. */
+
+/* TC2.INTCTRLA  bit masks and bit positions */
+#define TC2_LUNFINTLVL_gm  0x03  /* Low Byte Underflow interrupt level group mask. */
+#define TC2_LUNFINTLVL_gp  0  /* Low Byte Underflow interrupt level group position. */
+#define TC2_LUNFINTLVL0_bm  (1<<0)  /* Low Byte Underflow interrupt level bit 0 mask. */
+#define TC2_LUNFINTLVL0_bp  0  /* Low Byte Underflow interrupt level bit 0 position. */
+#define TC2_LUNFINTLVL1_bm  (1<<1)  /* Low Byte Underflow interrupt level bit 1 mask. */
+#define TC2_LUNFINTLVL1_bp  1  /* Low Byte Underflow interrupt level bit 1 position. */
+#define TC2_HUNFINTLVL_gm  0x0C  /* High Byte Underflow Interrupt Level group mask. */
+#define TC2_HUNFINTLVL_gp  2  /* High Byte Underflow Interrupt Level group position. */
+#define TC2_HUNFINTLVL0_bm  (1<<2)  /* High Byte Underflow Interrupt Level bit 0 mask. */
+#define TC2_HUNFINTLVL0_bp  2  /* High Byte Underflow Interrupt Level bit 0 position. */
+#define TC2_HUNFINTLVL1_bm  (1<<3)  /* High Byte Underflow Interrupt Level bit 1 mask. */
+#define TC2_HUNFINTLVL1_bp  3  /* High Byte Underflow Interrupt Level bit 1 position. */
+
+/* TC2.INTCTRLB  bit masks and bit positions */
+#define TC2_LCMPAINTLVL_gm  0x03  /* Low Byte Compare A Interrupt Level group mask. */
+#define TC2_LCMPAINTLVL_gp  0  /* Low Byte Compare A Interrupt Level group position. */
+#define TC2_LCMPAINTLVL0_bm  (1<<0)  /* Low Byte Compare A Interrupt Level bit 0 mask. */
+#define TC2_LCMPAINTLVL0_bp  0  /* Low Byte Compare A Interrupt Level bit 0 position. */
+#define TC2_LCMPAINTLVL1_bm  (1<<1)  /* Low Byte Compare A Interrupt Level bit 1 mask. */
+#define TC2_LCMPAINTLVL1_bp  1  /* Low Byte Compare A Interrupt Level bit 1 position. */
+#define TC2_LCMPBINTLVL_gm  0x0C  /* Low Byte Compare B Interrupt Level group mask. */
+#define TC2_LCMPBINTLVL_gp  2  /* Low Byte Compare B Interrupt Level group position. */
+#define TC2_LCMPBINTLVL0_bm  (1<<2)  /* Low Byte Compare B Interrupt Level bit 0 mask. */
+#define TC2_LCMPBINTLVL0_bp  2  /* Low Byte Compare B Interrupt Level bit 0 position. */
+#define TC2_LCMPBINTLVL1_bm  (1<<3)  /* Low Byte Compare B Interrupt Level bit 1 mask. */
+#define TC2_LCMPBINTLVL1_bp  3  /* Low Byte Compare B Interrupt Level bit 1 position. */
+#define TC2_LCMPCINTLVL_gm  0x30  /* Low Byte Compare C Interrupt Level group mask. */
+#define TC2_LCMPCINTLVL_gp  4  /* Low Byte Compare C Interrupt Level group position. */
+#define TC2_LCMPCINTLVL0_bm  (1<<4)  /* Low Byte Compare C Interrupt Level bit 0 mask. */
+#define TC2_LCMPCINTLVL0_bp  4  /* Low Byte Compare C Interrupt Level bit 0 position. */
+#define TC2_LCMPCINTLVL1_bm  (1<<5)  /* Low Byte Compare C Interrupt Level bit 1 mask. */
+#define TC2_LCMPCINTLVL1_bp  5  /* Low Byte Compare C Interrupt Level bit 1 position. */
+#define TC2_LCMPDINTLVL_gm  0xC0  /* Low Byte Compare D Interrupt Level group mask. */
+#define TC2_LCMPDINTLVL_gp  6  /* Low Byte Compare D Interrupt Level group position. */
+#define TC2_LCMPDINTLVL0_bm  (1<<6)  /* Low Byte Compare D Interrupt Level bit 0 mask. */
+#define TC2_LCMPDINTLVL0_bp  6  /* Low Byte Compare D Interrupt Level bit 0 position. */
+#define TC2_LCMPDINTLVL1_bm  (1<<7)  /* Low Byte Compare D Interrupt Level bit 1 mask. */
+#define TC2_LCMPDINTLVL1_bp  7  /* Low Byte Compare D Interrupt Level bit 1 position. */
+
+/* TC2.CTRLF  bit masks and bit positions */
+#define TC2_CMDEN_gm  0x03  /* Command Enable group mask. */
+#define TC2_CMDEN_gp  0  /* Command Enable group position. */
+#define TC2_CMDEN0_bm  (1<<0)  /* Command Enable bit 0 mask. */
+#define TC2_CMDEN0_bp  0  /* Command Enable bit 0 position. */
+#define TC2_CMDEN1_bm  (1<<1)  /* Command Enable bit 1 mask. */
+#define TC2_CMDEN1_bp  1  /* Command Enable bit 1 position. */
+#define TC2_CMD_gm  0x0C  /* Command group mask. */
+#define TC2_CMD_gp  2  /* Command group position. */
+#define TC2_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
+#define TC2_CMD0_bp  2  /* Command bit 0 position. */
+#define TC2_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
+#define TC2_CMD1_bp  3  /* Command bit 1 position. */
+
+/* TC2.INTFLAGS  bit masks and bit positions */
+#define TC2_LUNFIF_bm  0x01  /* Low Byte Underflow Interrupt Flag bit mask. */
+#define TC2_LUNFIF_bp  0  /* Low Byte Underflow Interrupt Flag bit position. */
+#define TC2_HUNFIF_bm  0x02  /* High Byte Underflow Interrupt Flag bit mask. */
+#define TC2_HUNFIF_bp  1  /* High Byte Underflow Interrupt Flag bit position. */
+#define TC2_LCMPAIF_bm  0x10  /* Low Byte Compare A Interrupt Flag bit mask. */
+#define TC2_LCMPAIF_bp  4  /* Low Byte Compare A Interrupt Flag bit position. */
+#define TC2_LCMPBIF_bm  0x20  /* Low Byte Compare B Interrupt Flag bit mask. */
+#define TC2_LCMPBIF_bp  5  /* Low Byte Compare B Interrupt Flag bit position. */
+#define TC2_LCMPCIF_bm  0x40  /* Low Byte Compare C Interrupt Flag bit mask. */
+#define TC2_LCMPCIF_bp  6  /* Low Byte Compare C Interrupt Flag bit position. */
+#define TC2_LCMPDIF_bm  0x80  /* Low Byte Compare D Interrupt Flag bit mask. */
+#define TC2_LCMPDIF_bp  7  /* Low Byte Compare D Interrupt Flag bit position. */
+
+
+
+
+
+
+
+
+
+
+
+
+
+/* TWI - Two-Wire Interface */
+/* TWI_MASTER.CTRLA  bit masks and bit positions */
+#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
+#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
+#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
+#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
+#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
+#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
+#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
+#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
+#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
+#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
+#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
+#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
+
+/* TWI_MASTER.CTRLB  bit masks and bit positions */
+#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
+#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
+#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
+#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
+#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
+#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
+#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
+#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
+#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
+#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
+
+/* TWI_MASTER.CTRLC  bit masks and bit positions */
+#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
+#define TWI_MASTER_CMD_gp  0  /* Command group position. */
+#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
+#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
+#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
+#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
+#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
+#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
+
+/* TWI_MASTER.STATUS  bit masks and bit positions */
+#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
+#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
+#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
+#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
+#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
+#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
+#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
+#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
+#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
+#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
+#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
+#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
+#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
+#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
+#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
+#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
+#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
+#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
+
+
+
+
+/* TWI_SLAVE.CTRLA  bit masks and bit positions */
+#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
+#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
+#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
+#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
+#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
+#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
+#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
+#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
+#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
+#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
+#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
+#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
+#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
+#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
+#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
+#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
+
+/* TWI_SLAVE.CTRLB  bit masks and bit positions */
+#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
+#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
+#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
+#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
+#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
+#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
+#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
+#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
+
+/* TWI_SLAVE.STATUS  bit masks and bit positions */
+#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
+#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
+#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
+#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
+#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
+#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
+#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
+#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
+#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
+#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
+#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
+#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
+#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
+#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
+#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
+#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
+
+
+
+/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
+#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
+#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
+#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
+#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
+#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
+#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
+#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
+#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
+#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
+#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
+#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
+#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
+#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
+#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
+#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
+#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
+#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
+#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
+
+/* TWI.CTRL  bit masks and bit positions */
+#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
+#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
+#define TWI_SDAHOLD_gm  0x06  /* SDA Hold Time Enable group mask. */
+#define TWI_SDAHOLD_gp  1  /* SDA Hold Time Enable group position. */
+#define TWI_SDAHOLD0_bm  (1<<1)  /* SDA Hold Time Enable bit 0 mask. */
+#define TWI_SDAHOLD0_bp  1  /* SDA Hold Time Enable bit 0 position. */
+#define TWI_SDAHOLD1_bm  (1<<2)  /* SDA Hold Time Enable bit 1 mask. */
+#define TWI_SDAHOLD1_bp  2  /* SDA Hold Time Enable bit 1 position. */
+
+
+/* USART - Universal Asynchronous Receiver-Transmitter */
+/* USART.STATUS  bit masks and bit positions */
+#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
+#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
+#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
+#define USART_PERR_bp  2  /* Parity Error bit position. */
+#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
+#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
+#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
+#define USART_FERR_bp  4  /* Frame Error bit position. */
+#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
+#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
+#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
+#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
+#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
+#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
+
+/* USART.CTRLA  bit masks and bit positions */
+#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
+#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
+#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
+#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
+#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
+#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
+#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
+#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
+#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
+#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
+#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
+#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
+#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
+#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
+#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
+#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
+#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
+#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
+
+/* USART.CTRLB  bit masks and bit positions */
+#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
+#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
+#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
+#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
+#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
+#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
+#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
+#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
+#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
+#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
+
+/* USART.CTRLC  bit masks and bit positions */
+#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
+#define USART_CHSIZE_gp  0  /* Character Size group position. */
+#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
+#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
+#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
+#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
+#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
+#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
+#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
+#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
+#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
+#define USART_PMODE_gp  4  /* Parity Mode group position. */
+#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
+#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
+#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
+#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
+#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
+#define USART_CMODE_gp  6  /* Communication Mode group position. */
+#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
+#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
+#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
+#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
+
+/* USART.BAUDCTRLA  bit masks and bit positions */
+#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
+#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
+#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
+#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
+#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
+#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
+#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
+#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
+#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
+#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
+#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
+#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
+#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
+#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
+#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
+#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
+#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
+#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
+
+/* USART.BAUDCTRLB  bit masks and bit positions */
+/* USART_BSEL  is already defined. */
+#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
+#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
+#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
+#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
+#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
+#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
+#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
+#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
+#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
+#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
+
+/* USB - USB */
+/* USB_EP.STATUS  bit masks and bit positions */
+#define USB_EP_TOGGLE_bm  0x01  /* Data Toggle bit mask. */
+#define USB_EP_TOGGLE_bp  0  /* Data Toggle bit position. */
+#define USB_EP_BUSNACK0_bm  0x02  /* Data Buffer 0 Not Acknowledge bit mask. */
+#define USB_EP_BUSNACK0_bp  1  /* Data Buffer 0 Not Acknowledge bit position. */
+#define USB_EP_BUSNACK1_bm  0x04  /* Data Buffer 1 Not Acknowledge bit mask. */
+#define USB_EP_BUSNACK1_bp  2  /* Data Buffer 1 Not Acknowledge bit position. */
+#define USB_EP_BANK_bm  0x08  /* Bank Select bit mask. */
+#define USB_EP_BANK_bp  3  /* Bank Select bit position. */
+#define USB_EP_TRNCOMPL1_bm  0x10  /* Transaction Complete 1 Flag bit mask. */
+#define USB_EP_TRNCOMPL1_bp  4  /* Transaction Complete 1 Flag bit position. */
+#define USB_EP_SETUP_bm  0x10  /* SETUP Transaction Complete Flag bit mask. */
+#define USB_EP_SETUP_bp  4  /* SETUP Transaction Complete Flag bit position. */
+#define USB_EP_TRNCOMPL0_bm  0x20  /* Transaction Complete 0 Flag bit mask. */
+#define USB_EP_TRNCOMPL0_bp  5  /* Transaction Complete 0 Flag bit position. */
+#define USB_EP_UNF_bm  0x40  /* Underflow Enpoint FLag bit mask. */
+#define USB_EP_UNF_bp  6  /* Underflow Enpoint FLag bit position. */
+#define USB_EP_OVF_bm  0x40  /* Overflow Enpoint Flag for Output Endpoints bit mask. */
+#define USB_EP_OVF_bp  6  /* Overflow Enpoint Flag for Output Endpoints bit position. */
+#define USB_EP_STALLF_bm  0x80  /* Endpoint Stall Flag bit mask. */
+#define USB_EP_STALLF_bp  7  /* Endpoint Stall Flag bit position. */
+#define USB_EP_CRC_bm  0x80  /* CRC Error Flag bit mask. */
+#define USB_EP_CRC_bp  7  /* CRC Error Flag bit position. */
+
+/* USB_EP.CTRL  bit masks and bit positions */
+#define USB_EP_STALL_bm  0x04  /* Data Stall bit mask. */
+#define USB_EP_STALL_bp  2  /* Data Stall bit position. */
+#define USB_EP_BUFSIZE_gm  0x07  /* Data Buffer Size group mask. */
+#define USB_EP_BUFSIZE_gp  0  /* Data Buffer Size group position. */
+#define USB_EP_BUFSIZE0_bm  (1<<0)  /* Data Buffer Size bit 0 mask. */
+#define USB_EP_BUFSIZE0_bp  0  /* Data Buffer Size bit 0 position. */
+#define USB_EP_BUFSIZE1_bm  (1<<1)  /* Data Buffer Size bit 1 mask. */
+#define USB_EP_BUFSIZE1_bp  1  /* Data Buffer Size bit 1 position. */
+#define USB_EP_BUFSIZE2_bm  (1<<2)  /* Data Buffer Size bit 2 mask. */
+#define USB_EP_BUFSIZE2_bp  2  /* Data Buffer Size bit 2 position. */
+#define USB_EP_INTDSBL_bm  0x08  /* Interrupt Disable bit mask. */
+#define USB_EP_INTDSBL_bp  3  /* Interrupt Disable bit position. */
+#define USB_EP_PINGPONG_bm  0x10  /* Ping-Pong Enable bit mask. */
+#define USB_EP_PINGPONG_bp  4  /* Ping-Pong Enable bit position. */
+#define USB_EP_MULTIPKT_bm  0x20  /* Multi Packet Transfer Enable bit mask. */
+#define USB_EP_MULTIPKT_bp  5  /* Multi Packet Transfer Enable bit position. */
+#define USB_EP_TYPE_gm  0xC0  /* Endpoint Type group mask. */
+#define USB_EP_TYPE_gp  6  /* Endpoint Type group position. */
+#define USB_EP_TYPE0_bm  (1<<6)  /* Endpoint Type bit 0 mask. */
+#define USB_EP_TYPE0_bp  6  /* Endpoint Type bit 0 position. */
+#define USB_EP_TYPE1_bm  (1<<7)  /* Endpoint Type bit 1 mask. */
+#define USB_EP_TYPE1_bp  7  /* Endpoint Type bit 1 position. */
+
+/* USB_EP.CNT  bit masks and bit positions */
+#define USB_EP_ZLP_bm  0x8000  /* Zero Length Packet bit mask. */
+#define USB_EP_ZLP_bp  15  /* Zero Length Packet bit position. */
+
+
+
+/* USB.CTRLA  bit masks and bit positions */
+#define USB_MAXEP_gm  0x0F  /* Maximum Endpoint Addresses group mask. */
+#define USB_MAXEP_gp  0  /* Maximum Endpoint Addresses group position. */
+#define USB_MAXEP0_bm  (1<<0)  /* Maximum Endpoint Addresses bit 0 mask. */
+#define USB_MAXEP0_bp  0  /* Maximum Endpoint Addresses bit 0 position. */
+#define USB_MAXEP1_bm  (1<<1)  /* Maximum Endpoint Addresses bit 1 mask. */
+#define USB_MAXEP1_bp  1  /* Maximum Endpoint Addresses bit 1 position. */
+#define USB_MAXEP2_bm  (1<<2)  /* Maximum Endpoint Addresses bit 2 mask. */
+#define USB_MAXEP2_bp  2  /* Maximum Endpoint Addresses bit 2 position. */
+#define USB_MAXEP3_bm  (1<<3)  /* Maximum Endpoint Addresses bit 3 mask. */
+#define USB_MAXEP3_bp  3  /* Maximum Endpoint Addresses bit 3 position. */
+#define USB_STFRNUM_bm  0x10  /* Store Frame Number Enable bit mask. */
+#define USB_STFRNUM_bp  4  /* Store Frame Number Enable bit position. */
+#define USB_FIFOEN_bm  0x20  /* USB FIFO Enable bit mask. */
+#define USB_FIFOEN_bp  5  /* USB FIFO Enable bit position. */
+#define USB_SPEED_bm  0x40  /* Speed Select bit mask. */
+#define USB_SPEED_bp  6  /* Speed Select bit position. */
+#define USB_ENABLE_bm  0x80  /* USB Enable bit mask. */
+#define USB_ENABLE_bp  7  /* USB Enable bit position. */
+
+/* USB.CTRLB  bit masks and bit positions */
+#define USB_ATTACH_bm  0x01  /* Attach bit mask. */
+#define USB_ATTACH_bp  0  /* Attach bit position. */
+#define USB_GNACK_bm  0x02  /* Global NACK bit mask. */
+#define USB_GNACK_bp  1  /* Global NACK bit position. */
+#define USB_RWAKEUP_bm  0x04  /* Remote Wake-up bit mask. */
+#define USB_RWAKEUP_bp  2  /* Remote Wake-up bit position. */
+#define USB_PULLRST_bm  0x10  /* Pull during Reset bit mask. */
+#define USB_PULLRST_bp  4  /* Pull during Reset bit position. */
+
+/* USB.STATUS  bit masks and bit positions */
+#define USB_BUSRST_bm  0x01  /* Bus Reset bit mask. */
+#define USB_BUSRST_bp  0  /* Bus Reset bit position. */
+#define USB_SUSPEND_bm  0x02  /* Bus Suspended bit mask. */
+#define USB_SUSPEND_bp  1  /* Bus Suspended bit position. */
+#define USB_RESUME_bm  0x04  /* Resume bit mask. */
+#define USB_RESUME_bp  2  /* Resume bit position. */
+#define USB_URESUME_bm  0x08  /* Upstream Resume bit mask. */
+#define USB_URESUME_bp  3  /* Upstream Resume bit position. */
+
+/* USB.ADDR  bit masks and bit positions */
+#define USB_ADDR_gm  0x7F  /* Device Address group mask. */
+#define USB_ADDR_gp  0  /* Device Address group position. */
+#define USB_ADDR0_bm  (1<<0)  /* Device Address bit 0 mask. */
+#define USB_ADDR0_bp  0  /* Device Address bit 0 position. */
+#define USB_ADDR1_bm  (1<<1)  /* Device Address bit 1 mask. */
+#define USB_ADDR1_bp  1  /* Device Address bit 1 position. */
+#define USB_ADDR2_bm  (1<<2)  /* Device Address bit 2 mask. */
+#define USB_ADDR2_bp  2  /* Device Address bit 2 position. */
+#define USB_ADDR3_bm  (1<<3)  /* Device Address bit 3 mask. */
+#define USB_ADDR3_bp  3  /* Device Address bit 3 position. */
+#define USB_ADDR4_bm  (1<<4)  /* Device Address bit 4 mask. */
+#define USB_ADDR4_bp  4  /* Device Address bit 4 position. */
+#define USB_ADDR5_bm  (1<<5)  /* Device Address bit 5 mask. */
+#define USB_ADDR5_bp  5  /* Device Address bit 5 position. */
+#define USB_ADDR6_bm  (1<<6)  /* Device Address bit 6 mask. */
+#define USB_ADDR6_bp  6  /* Device Address bit 6 position. */
+
+/* USB.FIFOWP  bit masks and bit positions */
+#define USB_FIFOWP_gm  0x1F  /* FIFO Write Pointer group mask. */
+#define USB_FIFOWP_gp  0  /* FIFO Write Pointer group position. */
+#define USB_FIFOWP0_bm  (1<<0)  /* FIFO Write Pointer bit 0 mask. */
+#define USB_FIFOWP0_bp  0  /* FIFO Write Pointer bit 0 position. */
+#define USB_FIFOWP1_bm  (1<<1)  /* FIFO Write Pointer bit 1 mask. */
+#define USB_FIFOWP1_bp  1  /* FIFO Write Pointer bit 1 position. */
+#define USB_FIFOWP2_bm  (1<<2)  /* FIFO Write Pointer bit 2 mask. */
+#define USB_FIFOWP2_bp  2  /* FIFO Write Pointer bit 2 position. */
+#define USB_FIFOWP3_bm  (1<<3)  /* FIFO Write Pointer bit 3 mask. */
+#define USB_FIFOWP3_bp  3  /* FIFO Write Pointer bit 3 position. */
+#define USB_FIFOWP4_bm  (1<<4)  /* FIFO Write Pointer bit 4 mask. */
+#define USB_FIFOWP4_bp  4  /* FIFO Write Pointer bit 4 position. */
+
+/* USB.FIFORP  bit masks and bit positions */
+#define USB_FIFORP_gm  0x1F  /* FIFO Read Pointer group mask. */
+#define USB_FIFORP_gp  0  /* FIFO Read Pointer group position. */
+#define USB_FIFORP0_bm  (1<<0)  /* FIFO Read Pointer bit 0 mask. */
+#define USB_FIFORP0_bp  0  /* FIFO Read Pointer bit 0 position. */
+#define USB_FIFORP1_bm  (1<<1)  /* FIFO Read Pointer bit 1 mask. */
+#define USB_FIFORP1_bp  1  /* FIFO Read Pointer bit 1 position. */
+#define USB_FIFORP2_bm  (1<<2)  /* FIFO Read Pointer bit 2 mask. */
+#define USB_FIFORP2_bp  2  /* FIFO Read Pointer bit 2 position. */
+#define USB_FIFORP3_bm  (1<<3)  /* FIFO Read Pointer bit 3 mask. */
+#define USB_FIFORP3_bp  3  /* FIFO Read Pointer bit 3 position. */
+#define USB_FIFORP4_bm  (1<<4)  /* FIFO Read Pointer bit 4 mask. */
+#define USB_FIFORP4_bp  4  /* FIFO Read Pointer bit 4 position. */
+
+
+/* USB.INTCTRLA  bit masks and bit positions */
+#define USB_INTLVL_gm  0x03  /* Interrupt Level group mask. */
+#define USB_INTLVL_gp  0  /* Interrupt Level group position. */
+#define USB_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
+#define USB_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
+#define USB_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
+#define USB_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
+#define USB_STALLIE_bm  0x10  /* STALL Interrupt Enable bit mask. */
+#define USB_STALLIE_bp  4  /* STALL Interrupt Enable bit position. */
+#define USB_BUSERRIE_bm  0x20  /* Bus Error Interrupt Enable bit mask. */
+#define USB_BUSERRIE_bp  5  /* Bus Error Interrupt Enable bit position. */
+#define USB_BUSEVIE_bm  0x40  /* Bus Event Interrupt Enable bit mask. */
+#define USB_BUSEVIE_bp  6  /* Bus Event Interrupt Enable bit position. */
+#define USB_SOFIE_bm  0x80  /* Start Of Frame Interrupt Enable bit mask. */
+#define USB_SOFIE_bp  7  /* Start Of Frame Interrupt Enable bit position. */
+
+/* USB.INTCTRLB  bit masks and bit positions */
+#define USB_SETUPIE_bm  0x01  /* SETUP Transaction Complete Interrupt Enable bit mask. */
+#define USB_SETUPIE_bp  0  /* SETUP Transaction Complete Interrupt Enable bit position. */
+#define USB_TRNIE_bm  0x02  /* Transaction Complete Interrupt Enable bit mask. */
+#define USB_TRNIE_bp  1  /* Transaction Complete Interrupt Enable bit position. */
+
+/* USB.INTFLAGSACLR  bit masks and bit positions */
+#define USB_STALLIF_bm  0x01  /* STALL Interrupt Flag bit mask. */
+#define USB_STALLIF_bp  0  /* STALL Interrupt Flag bit position. */
+#define USB_OVFIF_bm  0x02  /* Overflow Interrupt Flag bit mask. */
+#define USB_OVFIF_bp  1  /* Overflow Interrupt Flag bit position. */
+#define USB_UNFIF_bm  0x04  /* Underflow Interrupt Flag bit mask. */
+#define USB_UNFIF_bp  2  /* Underflow Interrupt Flag bit position. */
+#define USB_CRCIF_bm  0x08  /* Isochronous CRC Error Interrupt Flag bit mask. */
+#define USB_CRCIF_bp  3  /* Isochronous CRC Error Interrupt Flag bit position. */
+#define USB_RSTIF_bm  0x10  /* Reset Interrupt Flag bit mask. */
+#define USB_RSTIF_bp  4  /* Reset Interrupt Flag bit position. */
+#define USB_RESUMEIF_bm  0x20  /* Resume Interrupt Flag bit mask. */
+#define USB_RESUMEIF_bp  5  /* Resume Interrupt Flag bit position. */
+#define USB_SUSPENDIF_bm  0x40  /* Suspend Interrupt Flag bit mask. */
+#define USB_SUSPENDIF_bp  6  /* Suspend Interrupt Flag bit position. */
+#define USB_SOFIF_bm  0x80  /* Start Of Frame Interrupt Flag bit mask. */
+#define USB_SOFIF_bp  7  /* Start Of Frame Interrupt Flag bit position. */
+
+/* USB.INTFLAGSASET  bit masks and bit positions */
+/* USB_STALLIF  is already defined. */
+/* USB_OVFIF  is already defined. */
+/* USB_UNFIF  is already defined. */
+/* USB_CRCIF  is already defined. */
+/* USB_RSTIF  is already defined. */
+/* USB_RESUMEIF  is already defined. */
+/* USB_SUSPENDIF  is already defined. */
+/* USB_SOFIF  is already defined. */
+
+/* USB.INTFLAGSBCLR  bit masks and bit positions */
+#define USB_SETUPIF_bm  0x01  /* SETUP Transaction Complete Interrupt Flag bit mask. */
+#define USB_SETUPIF_bp  0  /* SETUP Transaction Complete Interrupt Flag bit position. */
+#define USB_TRNIF_bm  0x02  /* Transaction Complete Interrupt Flag bit mask. */
+#define USB_TRNIF_bp  1  /* Transaction Complete Interrupt Flag bit position. */
+
+/* USB.INTFLAGSBSET  bit masks and bit positions */
+/* USB_SETUPIF  is already defined. */
+/* USB_TRNIF  is already defined. */
+
+
+
+
+
+
+
+
+/* VPORT - Virtual Ports */
+/* VPORT.INTFLAGS  bit masks and bit positions */
+#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
+#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
+#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
+#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
+
+/* WDT - Watch-Dog Timer */
+/* WDT.CTRL  bit masks and bit positions */
+#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
+#define WDT_CEN_bp  0  /* Change Enable bit position. */
+#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
+#define WDT_ENABLE_bp  1  /* Enable bit position. */
+#define WDT_PER_gm  0x3C  /* Period group mask. */
+#define WDT_PER_gp  2  /* Period group position. */
+#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
+#define WDT_PER0_bp  2  /* Period bit 0 position. */
+#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
+#define WDT_PER1_bp  3  /* Period bit 1 position. */
+#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
+#define WDT_PER2_bp  4  /* Period bit 2 position. */
+#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
+#define WDT_PER3_bp  5  /* Period bit 3 position. */
+
+/* WDT.WINCTRL  bit masks and bit positions */
+#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
+#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
+#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
+#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
+#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
+#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
+#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
+#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
+#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
+#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
+#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
+#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
+#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
+#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
+
+/* WDT.STATUS  bit masks and bit positions */
+#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
+#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
+
+/* XOCD - On-Chip Debug System */
+/* OCD.OCDR0  bit masks and bit positions */
+#define OCD_OCDRD_gm  0xFF  /* OCDR Dirty group mask. */
+#define OCD_OCDRD_gp  0  /* OCDR Dirty group position. */
+#define OCD_OCDRD0_bm  (1<<0)  /* OCDR Dirty bit 0 mask. */
+#define OCD_OCDRD0_bp  0  /* OCDR Dirty bit 0 position. */
+#define OCD_OCDRD1_bm  (1<<1)  /* OCDR Dirty bit 1 mask. */
+#define OCD_OCDRD1_bp  1  /* OCDR Dirty bit 1 position. */
+#define OCD_OCDRD2_bm  (1<<2)  /* OCDR Dirty bit 2 mask. */
+#define OCD_OCDRD2_bp  2  /* OCDR Dirty bit 2 position. */
+#define OCD_OCDRD3_bm  (1<<3)  /* OCDR Dirty bit 3 mask. */
+#define OCD_OCDRD3_bp  3  /* OCDR Dirty bit 3 position. */
+#define OCD_OCDRD4_bm  (1<<4)  /* OCDR Dirty bit 4 mask. */
+#define OCD_OCDRD4_bp  4  /* OCDR Dirty bit 4 position. */
+#define OCD_OCDRD5_bm  (1<<5)  /* OCDR Dirty bit 5 mask. */
+#define OCD_OCDRD5_bp  5  /* OCDR Dirty bit 5 position. */
+#define OCD_OCDRD6_bm  (1<<6)  /* OCDR Dirty bit 6 mask. */
+#define OCD_OCDRD6_bp  6  /* OCDR Dirty bit 6 position. */
+#define OCD_OCDRD7_bm  (1<<7)  /* OCDR Dirty bit 7 mask. */
+#define OCD_OCDRD7_bp  7  /* OCDR Dirty bit 7 position. */
+
+/* OCD.OCDR1  bit masks and bit positions */
+/* OCD_OCDRD  is already defined. */
+
+
+
+// Generic Port Pins
+
+#define PIN0_bm 0x01
+#define PIN0_bp 0
+#define PIN1_bm 0x02
+#define PIN1_bp 1
+#define PIN2_bm 0x04
+#define PIN2_bp 2
+#define PIN3_bm 0x08
+#define PIN3_bp 3
+#define PIN4_bm 0x10
+#define PIN4_bp 4
+#define PIN5_bm 0x20
+#define PIN5_bp 5
+#define PIN6_bm 0x40
+#define PIN6_bp 6
+#define PIN7_bm 0x80
+#define PIN7_bp 7
+
+/* ========== Interrupt Vector Definitions ========== */
+/* Vector 0 is the reset vector */
+
+/* OSC interrupt vectors */
+#define OSC_OSCF_vect_num  1
+#define OSC_OSCF_vect      _VECTOR(1)  /* Oscillator Failure Interrupt (NMI) */
+
+/* PORTC interrupt vectors */
+#define PORTC_INT0_vect_num  2
+#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
+#define PORTC_INT1_vect_num  3
+#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
+
+/* PORTR interrupt vectors */
+#define PORTR_INT0_vect_num  4
+#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
+#define PORTR_INT1_vect_num  5
+#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
+
+/* DMA interrupt vectors */
+#define DMA_CH0_vect_num  6
+#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
+#define DMA_CH1_vect_num  7
+#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
+#define DMA_CH2_vect_num  8
+#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
+#define DMA_CH3_vect_num  9
+#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
+
+/* RTC interrupt vectors */
+#define RTC_OVF_vect_num  10
+#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
+#define RTC_COMP_vect_num  11
+#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
+
+/* TWIC interrupt vectors */
+#define TWIC_TWIS_vect_num  12
+#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
+#define TWIC_TWIM_vect_num  13
+#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_OVF_vect_num  14
+#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_LUNF_vect_num  14
+#define TCC2_LUNF_vect      _VECTOR(14)  /* Low Byte Underflow Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_ERR_vect_num  15
+#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_HUNF_vect_num  15
+#define TCC2_HUNF_vect      _VECTOR(15)  /* High Byte Underflow Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_CCA_vect_num  16
+#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_LCMPA_vect_num  16
+#define TCC2_LCMPA_vect      _VECTOR(16)  /* Low Byte Compare A Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_CCB_vect_num  17
+#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_LCMPB_vect_num  17
+#define TCC2_LCMPB_vect      _VECTOR(17)  /* Low Byte Compare B Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_CCC_vect_num  18
+#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_LCMPC_vect_num  18
+#define TCC2_LCMPC_vect      _VECTOR(18)  /* Low Byte Compare C Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_CCD_vect_num  19
+#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
+
+/* TCC2 interrupt vectors */
+#define TCC2_LCMPD_vect_num  19
+#define TCC2_LCMPD_vect      _VECTOR(19)  /* Low Byte Compare D Interrupt */
+
+/* TCC1 interrupt vectors */
+#define TCC1_OVF_vect_num  20
+#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
+#define TCC1_ERR_vect_num  21
+#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
+#define TCC1_CCA_vect_num  22
+#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
+#define TCC1_CCB_vect_num  23
+#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
+
+/* SPIC interrupt vectors */
+#define SPIC_INT_vect_num  24
+#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
+
+/* USARTC0 interrupt vectors */
+#define USARTC0_RXC_vect_num  25
+#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
+#define USARTC0_DRE_vect_num  26
+#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
+#define USARTC0_TXC_vect_num  27
+#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
+
+/* USARTC1 interrupt vectors */
+#define USARTC1_RXC_vect_num  28
+#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
+#define USARTC1_DRE_vect_num  29
+#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
+#define USARTC1_TXC_vect_num  30
+#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
+
+/* AES interrupt vectors */
+#define AES_INT_vect_num  31
+#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
+
+/* NVM interrupt vectors */
+#define NVM_EE_vect_num  32
+#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
+#define NVM_SPM_vect_num  33
+#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
+
+/* PORTB interrupt vectors */
+#define PORTB_INT0_vect_num  34
+#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
+#define PORTB_INT1_vect_num  35
+#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
+
+/* ACB interrupt vectors */
+#define ACB_AC0_vect_num  36
+#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
+#define ACB_AC1_vect_num  37
+#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
+#define ACB_ACW_vect_num  38
+#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
+
+/* ADCB interrupt vectors */
+#define ADCB_CH0_vect_num  39
+#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
+#define ADCB_CH1_vect_num  40
+#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
+#define ADCB_CH2_vect_num  41
+#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
+#define ADCB_CH3_vect_num  42
+#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
+
+/* PORTE interrupt vectors */
+#define PORTE_INT0_vect_num  43
+#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
+#define PORTE_INT1_vect_num  44
+#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
+
+/* TWIE interrupt vectors */
+#define TWIE_TWIS_vect_num  45
+#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
+#define TWIE_TWIM_vect_num  46
+#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_OVF_vect_num  47
+#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_LUNF_vect_num  47
+#define TCE2_LUNF_vect      _VECTOR(47)  /* Low Byte Underflow Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_ERR_vect_num  48
+#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_HUNF_vect_num  48
+#define TCE2_HUNF_vect      _VECTOR(48)  /* High Byte Underflow Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_CCA_vect_num  49
+#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_LCMPA_vect_num  49
+#define TCE2_LCMPA_vect      _VECTOR(49)  /* Low Byte Compare A Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_CCB_vect_num  50
+#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_LCMPB_vect_num  50
+#define TCE2_LCMPB_vect      _VECTOR(50)  /* Low Byte Compare B Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_CCC_vect_num  51
+#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_LCMPC_vect_num  51
+#define TCE2_LCMPC_vect      _VECTOR(51)  /* Low Byte Compare C Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_CCD_vect_num  52
+#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
+
+/* TCE2 interrupt vectors */
+#define TCE2_LCMPD_vect_num  52
+#define TCE2_LCMPD_vect      _VECTOR(52)  /* Low Byte Compare D Interrupt */
+
+/* TCE1 interrupt vectors */
+#define TCE1_OVF_vect_num  53
+#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
+#define TCE1_ERR_vect_num  54
+#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
+#define TCE1_CCA_vect_num  55
+#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
+#define TCE1_CCB_vect_num  56
+#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
+
+/* SPIE interrupt vectors */
+#define SPIE_INT_vect_num  57
+#define SPIE_INT_vect      _VECTOR(57)  /* SPI Interrupt */
+
+/* USARTE0 interrupt vectors */
+#define USARTE0_RXC_vect_num  58
+#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
+#define USARTE0_DRE_vect_num  59
+#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
+#define USARTE0_TXC_vect_num  60
+#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
+
+/* USARTE1 interrupt vectors */
+#define USARTE1_RXC_vect_num  61
+#define USARTE1_RXC_vect      _VECTOR(61)  /* Reception Complete Interrupt */
+#define USARTE1_DRE_vect_num  62
+#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
+#define USARTE1_TXC_vect_num  63
+#define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
+
+/* PORTD interrupt vectors */
+#define PORTD_INT0_vect_num  64
+#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
+#define PORTD_INT1_vect_num  65
+#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
+
+/* PORTA interrupt vectors */
+#define PORTA_INT0_vect_num  66
+#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
+#define PORTA_INT1_vect_num  67
+#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
+
+/* ACA interrupt vectors */
+#define ACA_AC0_vect_num  68
+#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
+#define ACA_AC1_vect_num  69
+#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
+#define ACA_ACW_vect_num  70
+#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
+
+/* ADCA interrupt vectors */
+#define ADCA_CH0_vect_num  71
+#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
+#define ADCA_CH1_vect_num  72
+#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
+#define ADCA_CH2_vect_num  73
+#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
+#define ADCA_CH3_vect_num  74
+#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
+
+/* TCD0 interrupt vectors */
+#define TCD0_OVF_vect_num  77
+#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_LUNF_vect_num  77
+#define TCD2_LUNF_vect      _VECTOR(77)  /* Low Byte Underflow Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_ERR_vect_num  78
+#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_HUNF_vect_num  78
+#define TCD2_HUNF_vect      _VECTOR(78)  /* High Byte Underflow Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_CCA_vect_num  79
+#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_LCMPA_vect_num  79
+#define TCD2_LCMPA_vect      _VECTOR(79)  /* Low Byte Compare A Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_CCB_vect_num  80
+#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_LCMPB_vect_num  80
+#define TCD2_LCMPB_vect      _VECTOR(80)  /* Low Byte Compare B Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_CCC_vect_num  81
+#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_LCMPC_vect_num  81
+#define TCD2_LCMPC_vect      _VECTOR(81)  /* Low Byte Compare C Interrupt */
+
+/* TCD0 interrupt vectors */
+#define TCD0_CCD_vect_num  82
+#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
+
+/* TCD2 interrupt vectors */
+#define TCD2_LCMPD_vect_num  82
+#define TCD2_LCMPD_vect      _VECTOR(82)  /* Low Byte Compare D Interrupt */
+
+/* TCD1 interrupt vectors */
+#define TCD1_OVF_vect_num  83
+#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
+#define TCD1_ERR_vect_num  84
+#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
+#define TCD1_CCA_vect_num  85
+#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
+#define TCD1_CCB_vect_num  86
+#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
+
+/* SPID interrupt vectors */
+#define SPID_INT_vect_num  87
+#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
+
+/* USARTD0 interrupt vectors */
+#define USARTD0_RXC_vect_num  88
+#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
+#define USARTD0_DRE_vect_num  89
+#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
+#define USARTD0_TXC_vect_num  90
+#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
+
+/* USARTD1 interrupt vectors */
+#define USARTD1_RXC_vect_num  91
+#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
+#define USARTD1_DRE_vect_num  92
+#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
+#define USARTD1_TXC_vect_num  93
+#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
+
+/* PORTF interrupt vectors */
+#define PORTF_INT0_vect_num  104
+#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
+#define PORTF_INT1_vect_num  105
+#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
+
+/* TCF0 interrupt vectors */
+#define TCF0_OVF_vect_num  108
+#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_LUNF_vect_num  108
+#define TCF2_LUNF_vect      _VECTOR(108)  /* Low Byte Underflow Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_ERR_vect_num  109
+#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_HUNF_vect_num  109
+#define TCF2_HUNF_vect      _VECTOR(109)  /* High Byte Underflow Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_CCA_vect_num  110
+#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_LCMPA_vect_num  110
+#define TCF2_LCMPA_vect      _VECTOR(110)  /* Low Byte Compare A Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_CCB_vect_num  111
+#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_LCMPB_vect_num  111
+#define TCF2_LCMPB_vect      _VECTOR(111)  /* Low Byte Compare B Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_CCC_vect_num  112
+#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_LCMPC_vect_num  112
+#define TCF2_LCMPC_vect      _VECTOR(112)  /* Low Byte Compare C Interrupt */
+
+/* TCF0 interrupt vectors */
+#define TCF0_CCD_vect_num  113
+#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
+
+/* TCF2 interrupt vectors */
+#define TCF2_LCMPD_vect_num  113
+#define TCF2_LCMPD_vect      _VECTOR(113)  /* Low Byte Compare D Interrupt */
+
+/* USARTF0 interrupt vectors */
+#define USARTF0_RXC_vect_num  119
+#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
+#define USARTF0_DRE_vect_num  120
+#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
+#define USARTF0_TXC_vect_num  121
+#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
+
+/* USB interrupt vectors */
+#define USB_BUSEVENT_vect_num  125
+#define USB_BUSEVENT_vect      _VECTOR(125)  /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
+#define USB_TRNCOMPL_vect_num  126
+#define USB_TRNCOMPL_vect      _VECTOR(126)  /* Transaction complete interrupt */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
+
+
+/* ========== Constants ========== */
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define PROGMEM_START     (0x0000)
+#  define PROGMEM_SIZE      (139264)
+#else
+#  define PROGMEM_START     (0x0000U)
+#  define PROGMEM_SIZE      (139264U)
+#endif
+#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define APP_SECTION_START     (0x0000)
+#  define APP_SECTION_SIZE      (131072)
+#  define APP_SECTION_PAGE_SIZE (512)
+#else
+#  define APP_SECTION_START     (0x0000U)
+#  define APP_SECTION_SIZE      (131072U)
+#  define APP_SECTION_PAGE_SIZE (512U)
+#endif
+#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define APPTABLE_SECTION_START     (0x1E000)
+#  define APPTABLE_SECTION_SIZE      (8192)
+#  define APPTABLE_SECTION_PAGE_SIZE (512)
+#else
+#  define APPTABLE_SECTION_START     (0x1E000U)
+#  define APPTABLE_SECTION_SIZE      (8192U)
+#  define APPTABLE_SECTION_PAGE_SIZE (512U)
+#endif
+#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define BOOT_SECTION_START     (0x20000)
+#  define BOOT_SECTION_SIZE      (8192)
+#  define BOOT_SECTION_PAGE_SIZE (512)
+#else
+#  define BOOT_SECTION_START     (0x20000U)
+#  define BOOT_SECTION_SIZE      (8192U)
+#  define BOOT_SECTION_PAGE_SIZE (512U)
+#endif
+#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define DATAMEM_START     (0x0000)
+#  define DATAMEM_SIZE      (16384)
+#else
+#  define DATAMEM_START     (0x0000U)
+#  define DATAMEM_SIZE      (16384U)
+#endif
+#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define IO_START     (0x0000)
+#  define IO_SIZE      (4096)
+#  define IO_PAGE_SIZE (0)
+#else
+#  define IO_START     (0x0000U)
+#  define IO_SIZE      (4096U)
+#  define IO_PAGE_SIZE (0U)
+#endif
+#define IO_END       (IO_START + IO_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define MAPPED_EEPROM_START     (0x1000)
+#  define MAPPED_EEPROM_SIZE      (2048)
+#  define MAPPED_EEPROM_PAGE_SIZE (0)
+#else
+#  define MAPPED_EEPROM_START     (0x1000U)
+#  define MAPPED_EEPROM_SIZE      (2048U)
+#  define MAPPED_EEPROM_PAGE_SIZE (0U)
+#endif
+#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define INTERNAL_SRAM_START     (0x2000)
+#  define INTERNAL_SRAM_SIZE      (8192)
+#  define INTERNAL_SRAM_PAGE_SIZE (0)
+#else
+#  define INTERNAL_SRAM_START     (0x2000U)
+#  define INTERNAL_SRAM_SIZE      (8192U)
+#  define INTERNAL_SRAM_PAGE_SIZE (0U)
+#endif
+#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define EEPROM_START     (0x0000)
+#  define EEPROM_SIZE      (2048)
+#  define EEPROM_PAGE_SIZE (32)
+#else
+#  define EEPROM_START     (0x0000U)
+#  define EEPROM_SIZE      (2048U)
+#  define EEPROM_PAGE_SIZE (32U)
+#endif
+#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SIGNATURES_START     (0x0000)
+#  define SIGNATURES_SIZE      (3)
+#  define SIGNATURES_PAGE_SIZE (0)
+#else
+#  define SIGNATURES_START     (0x0000U)
+#  define SIGNATURES_SIZE      (3U)
+#  define SIGNATURES_PAGE_SIZE (0U)
+#endif
+#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define FUSES_START     (0x0000)
+#  define FUSES_SIZE      (6)
+#  define FUSES_PAGE_SIZE (0)
+#else
+#  define FUSES_START     (0x0000U)
+#  define FUSES_SIZE      (6U)
+#  define FUSES_PAGE_SIZE (0U)
+#endif
+#define FUSES_END       (FUSES_START + FUSES_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define LOCKBITS_START     (0x0000)
+#  define LOCKBITS_SIZE      (1)
+#  define LOCKBITS_PAGE_SIZE (0)
+#else
+#  define LOCKBITS_START     (0x0000U)
+#  define LOCKBITS_SIZE      (1U)
+#  define LOCKBITS_PAGE_SIZE (0U)
+#endif
+#define LOCKBITS_END       (LOCKBITS_START + LOCKBITS_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define USER_SIGNATURES_START     (0x0000)
+#  define USER_SIGNATURES_SIZE      (512)
+#  define USER_SIGNATURES_PAGE_SIZE (512)
+#else
+#  define USER_SIGNATURES_START     (0x0000U)
+#  define USER_SIGNATURES_SIZE      (512U)
+#  define USER_SIGNATURES_PAGE_SIZE (512U)
+#endif
+#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
+
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define PROD_SIGNATURES_START     (0x0000)
+#  define PROD_SIGNATURES_SIZE      (52)
+#  define PROD_SIGNATURES_PAGE_SIZE (512)
+#else
+#  define PROD_SIGNATURES_START     (0x0000U)
+#  define PROD_SIGNATURES_SIZE      (52U)
+#  define PROD_SIGNATURES_PAGE_SIZE (512U)
+#endif
+#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
+
+#define FLASHSTART   PROGMEM_START
+#define FLASHEND     PROGMEM_END
+#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  define SPM_PAGESIZE 512
+#else
+#  define SPM_PAGESIZE 512U
+#endif
+#define RAMSTART     INTERNAL_SRAM_START
+#define RAMSIZE      INTERNAL_SRAM_SIZE
+#define RAMEND       INTERNAL_SRAM_END
+#define E2END        EEPROM_END
+#define E2PAGESIZE   EEPROM_PAGE_SIZE
+
+
+/* ========== Fuses ========== */
+#define FUSE_MEMORY_SIZE 6
+
+/* Fuse Byte 0 (FUSEBYTE0) */
+#define FUSE_JTAGUID0  (unsigned char)~_BV(0)  /* JTAG User ID Bit 0 */
+#define FUSE_JTAGUID1  (unsigned char)~_BV(1)  /* JTAG User ID Bit 1 */
+#define FUSE_JTAGUID2  (unsigned char)~_BV(2)  /* JTAG User ID Bit 2 */
+#define FUSE_JTAGUID3  (unsigned char)~_BV(3)  /* JTAG User ID Bit 3 */
+#define FUSE_JTAGUID4  (unsigned char)~_BV(4)  /* JTAG User ID Bit 4 */
+#define FUSE_JTAGUID5  (unsigned char)~_BV(5)  /* JTAG User ID Bit 5 */
+#define FUSE_JTAGUID6  (unsigned char)~_BV(6)  /* JTAG User ID Bit 6 */
+#define FUSE_JTAGUID7  (unsigned char)~_BV(7)  /* JTAG User ID Bit 7 */
+#define FUSE0_DEFAULT  (0xff)
+#define FUSE_FUSEBYTE0_DEFAULT  (0xff)
+
+/* Fuse Byte 1 (FUSEBYTE1) */
+#define FUSE_WDPER0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDPER1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDPER2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDPER3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWPER0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWPER1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWPER2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWPER3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE1_DEFAULT  (0x0)
+#define FUSE_FUSEBYTE1_DEFAULT  (0x0)
+
+/* Fuse Byte 2 (FUSEBYTE2) */
+#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_TOSCSEL  (unsigned char)~_BV(5)  /* Timer Oscillator pin location */
+#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
+#define FUSE2_DEFAULT  (0xff)
+#define FUSE_FUSEBYTE2_DEFAULT  (0xff)
+
+/* Fuse Byte 3 Reserved */
+
+/* Fuse Byte 4 (FUSEBYTE4) */
+#define FUSE_JTAGEN  (unsigned char)~_BV(0)  /* JTAG Interface Enable */
+#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
+#define FUSE_STARTUPTIME0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
+#define FUSE_STARTUPTIME1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
+#define FUSE_RSTDISBL  (unsigned char)~_BV(4)  /* External Reset Disable */
+#define FUSE4_DEFAULT  (0xff)
+#define FUSE_FUSEBYTE4_DEFAULT  (0xff)
+
+/* Fuse Byte 5 (FUSEBYTE5) */
+#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brownout Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brownout Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brownout Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
+#define FUSE5_DEFAULT  (0xff)
+#define FUSE_FUSEBYTE5_DEFAULT  (0xff)
+
+/* ========== Lock Bits ========== */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_BITS_EXIST
+#define __BOOT_LOCK_BOOT_BITS_EXIST
+
+/* ========== Signature ========== */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x97
+#define SIGNATURE_2 0x42
+
+/* ========== Power Reduction Condition Definitions ========== */
+
+/* PR.PRGEN */
+#define __AVR_HAVE_PRGEN	(PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm)
+#define __AVR_HAVE_PRGEN_USB
+#define __AVR_HAVE_PRGEN_AES
+#define __AVR_HAVE_PRGEN_RTC
+#define __AVR_HAVE_PRGEN_EVSYS
+#define __AVR_HAVE_PRGEN_DMA
+
+/* PR.PRPA */
+#define __AVR_HAVE_PRPA	(PR_DAC_bm|PR_ADC_bm|PR_AC_bm)
+#define __AVR_HAVE_PRPA_DAC
+#define __AVR_HAVE_PRPA_ADC
+#define __AVR_HAVE_PRPA_AC
+
+/* PR.PRPB */
+#define __AVR_HAVE_PRPB	(PR_DAC_bm|PR_ADC_bm|PR_AC_bm)
+#define __AVR_HAVE_PRPB_DAC
+#define __AVR_HAVE_PRPB_ADC
+#define __AVR_HAVE_PRPB_AC
+
+/* PR.PRPC */
+#define __AVR_HAVE_PRPC	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
+#define __AVR_HAVE_PRPC_TWI
+#define __AVR_HAVE_PRPC_USART1
+#define __AVR_HAVE_PRPC_USART0
+#define __AVR_HAVE_PRPC_SPI
+#define __AVR_HAVE_PRPC_HIRES
+#define __AVR_HAVE_PRPC_TC1
+#define __AVR_HAVE_PRPC_TC0
+
+/* PR.PRPD */
+#define __AVR_HAVE_PRPD	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
+#define __AVR_HAVE_PRPD_TWI
+#define __AVR_HAVE_PRPD_USART1
+#define __AVR_HAVE_PRPD_USART0
+#define __AVR_HAVE_PRPD_SPI
+#define __AVR_HAVE_PRPD_HIRES
+#define __AVR_HAVE_PRPD_TC1
+#define __AVR_HAVE_PRPD_TC0
+
+/* PR.PRPE */
+#define __AVR_HAVE_PRPE	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
+#define __AVR_HAVE_PRPE_TWI
+#define __AVR_HAVE_PRPE_USART1
+#define __AVR_HAVE_PRPE_USART0
+#define __AVR_HAVE_PRPE_SPI
+#define __AVR_HAVE_PRPE_HIRES
+#define __AVR_HAVE_PRPE_TC1
+#define __AVR_HAVE_PRPE_TC0
+
+/* PR.PRPF */
+#define __AVR_HAVE_PRPF	(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
+#define __AVR_HAVE_PRPF_TWI
+#define __AVR_HAVE_PRPF_USART1
+#define __AVR_HAVE_PRPF_USART0
+#define __AVR_HAVE_PRPF_SPI
+#define __AVR_HAVE_PRPF_HIRES
+#define __AVR_HAVE_PRPF_TC1
+#define __AVR_HAVE_PRPF_TC0
+
+
+#endif /* #ifdef _AVR_ATXMEGA128A3U_H_INCLUDED */
+
--- avr-libc-2.0.0+Atmel3.6.2.orig/libc/avr-libc/include/avr/iox128a4u.h
+++ avr-libc-2.0.0+Atmel3.6.2/libc/avr-libc/include/avr/iox128a4u.h
@@ -1,7312 +1,7322 @@
-/*****************************************************************************
- *
- * Copyright (C) 2014 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****************************************************************************/
-
-
-/* $Id$ */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox128a4u.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#ifndef _AVR_ATXMEGA128A4U_H_INCLUDED
-#define _AVR_ATXMEGA128A4U_H_INCLUDED
-
-/* Ungrouped common registers */
-#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-/* Deprecated */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-    __extension__ union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-VPORT - Virtual Ports
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/*
---------------------------------------------------------------------------
-CPU - CPU
---------------------------------------------------------------------------
-*/
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-    register8_t USBCTRL;  /* USB Control Register */
-} CLK_t;
-
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2 MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32 MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32.768 kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1.024 kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1.024 kHz from internal 32.768 kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC32_gc = (0x06<<1),  /* 32.768 kHz from internal 32.768 kHz RC oscillator */
-    CLK_RTCSRC_EXTCLK_gc = (0x07<<1),  /* External Clock from TOSC1 */
-} CLK_RTCSRC_t;
-
-/* USB Prescaler Division Factor */
-typedef enum CLK_USBPSDIV_enum
-{
-    CLK_USBPSDIV_1_gc = (0x00<<3),  /* Divide by 1 */
-    CLK_USBPSDIV_2_gc = (0x01<<3),  /* Divide by 2 */
-    CLK_USBPSDIV_4_gc = (0x02<<3),  /* Divide by 4 */
-    CLK_USBPSDIV_8_gc = (0x03<<3),  /* Divide by 8 */
-    CLK_USBPSDIV_16_gc = (0x04<<3),  /* Divide by 16 */
-    CLK_USBPSDIV_32_gc = (0x05<<3),  /* Divide by 32 */
-} CLK_USBPSDIV_t;
-
-/* USB Clock Source */
-typedef enum CLK_USBSRC_enum
-{
-    CLK_USBSRC_PLL_gc = (0x00<<1),  /* PLL */
-    CLK_USBSRC_RC32M_gc = (0x01<<1),  /* Internal 32 MHz RC Oscillator */
-} CLK_USBSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-#define SLEEP_MODE_IDLE (0x00<<1)
-#define SLEEP_MODE_PWR_DOWN (0x02<<1)
-#define SLEEP_MODE_PWR_SAVE (0x03<<1)
-#define SLEEP_MODE_STANDBY (0x06<<1)
-#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32.768 kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control Register */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32.768 kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16 MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16 MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16 MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2 MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32 MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-/* 2 MHz DFLL Calibration Reference */
-typedef enum OSC_RC2MCREF_enum
-{
-    OSC_RC2MCREF_RC32K_gc = (0x00<<0),  /* Internal 32.768 kHz RC Oscillator */
-    OSC_RC2MCREF_XOSC32K_gc = (0x01<<0),  /* External 32.768 kHz Crystal Oscillator */
-} OSC_RC2MCREF_t;
-
-/* 32 MHz DFLL Calibration Reference */
-typedef enum OSC_RC32MCREF_enum
-{
-    OSC_RC32MCREF_RC32K_gc = (0x00<<1),  /* Internal 32.768 kHz RC Oscillator */
-    OSC_RC32MCREF_XOSC32K_gc = (0x01<<1),  /* External 32.768 kHz Crystal Oscillator */
-    OSC_RC32MCREF_USBSOF_gc = (0x02<<1),  /* USB Start of Frame */
-} OSC_RC32MCREF_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t ANAINIT;  /* Analog Startup Delay */
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x03;
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-PORTCFG - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-    register8_t EBIOUT;  /* EBI Output register */
-    register8_t EVOUTSEL;  /* Event Output Select */
-} PORTCFG_t;
-
-/* Virtual Port Mapping */
-typedef enum PORTCFG_VP02MAP_enum
-{
-    PORTCFG_VP02MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP02MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP02MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP02MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP02MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP02MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP02MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP02MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP02MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP02MAP_t;
-
-/* Virtual Port Mapping */
-typedef enum PORTCFG_VP13MAP_enum
-{
-    PORTCFG_VP13MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP13MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP13MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP13MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP13MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP13MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP13MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP13MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP13MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP13MAP_t;
-
-/* System Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* System Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* System Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* System Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* System Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Peripheral Clock Output Select */
-typedef enum PORTCFG_CLKOUTSEL_enum
-{
-    PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2),  /* 1x Peripheral Clock Output to pin */
-    PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2),  /* 2x Peripheral Clock Output to pin */
-    PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2),  /* 4x Peripheral Clock Output to pin */
-} PORTCFG_CLKOUTSEL_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Clock and Event Output Port */
-typedef enum PORTCFG_CLKEVPIN_enum
-{
-    PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7),  /* Clock and Event Ouput on PIN 7 */
-    PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7),  /* Clock and Event Ouput on PIN 4 */
-} PORTCFG_CLKEVPIN_t;
-
-/* EBI Address Output Port */
-typedef enum PORTCFG_EBIADROUT_enum
-{
-    PORTCFG_EBIADROUT_PF_gc = (0x00<<2),  /* EBI port 3 address output on PORTF pins 0 to 7 */
-    PORTCFG_EBIADROUT_PE_gc = (0x01<<2),  /* EBI port 3 address output on PORTE pins 0 to 7 */
-    PORTCFG_EBIADROUT_PFH_gc = (0x02<<2),  /* EBI port 3 address output on PORTF pins 4 to 7 */
-    PORTCFG_EBIADROUT_PEH_gc = (0x03<<2),  /* EBI port 3 address output on PORTE pins 4 to 7 */
-} PORTCFG_EBIADROUT_t;
-
-/* EBI Chip Select Output Port */
-typedef enum PORTCFG_EBICSOUT_enum
-{
-    PORTCFG_EBICSOUT_PH_gc = (0x00<<0),  /* EBI chip select output to PORTH pin 4 to 7 */
-    PORTCFG_EBICSOUT_PL_gc = (0x01<<0),  /* EBI chip select output to PORTL pin 4 to 7 */
-    PORTCFG_EBICSOUT_PF_gc = (0x02<<0),  /* EBI chip select output to PORTF pin 4 to 7 */
-    PORTCFG_EBICSOUT_PE_gc = (0x03<<0),  /* EBI chip select output to PORTE pin 4 to 7 */
-} PORTCFG_EBICSOUT_t;
-
-/* Event Output Select */
-typedef enum PORTCFG_EVOUTSEL_enum
-{
-    PORTCFG_EVOUTSEL_0_gc = (0x00<<0),  /* Event Channel 0 output to pin */
-    PORTCFG_EVOUTSEL_1_gc = (0x01<<0),  /* Event Channel 1 output to pin */
-    PORTCFG_EVOUTSEL_2_gc = (0x02<<0),  /* Event Channel 2 output to pin */
-    PORTCFG_EVOUTSEL_3_gc = (0x03<<0),  /* Event Channel 3 output to pin */
-    PORTCFG_EVOUTSEL_4_gc = (0x04<<0),  /* Event Channel 4 output to pin */
-    PORTCFG_EVOUTSEL_5_gc = (0x05<<0),  /* Event Channel 5 output to pin */
-    PORTCFG_EVOUTSEL_6_gc = (0x06<<0),  /* Event Channel 6 output to pin */
-    PORTCFG_EVOUTSEL_7_gc = (0x07<<0),  /* Event Channel 7 output to pin */
-} PORTCFG_EVOUTSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-CRC - Cyclic Redundancy Checker
---------------------------------------------------------------------------
-*/
-
-/* Cyclic Redundancy Checker */
-typedef struct CRC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t DATAIN;  /* Data Input */
-    register8_t CHECKSUM0;  /* Checksum byte 0 */
-    register8_t CHECKSUM1;  /* Checksum byte 1 */
-    register8_t CHECKSUM2;  /* Checksum byte 2 */
-    register8_t CHECKSUM3;  /* Checksum byte 3 */
-} CRC_t;
-
-/* Reset */
-typedef enum CRC_RESET_enum
-{
-    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
-    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
-    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
-} CRC_RESET_t;
-
-/* Input Source */
-typedef enum CRC_SOURCE_enum
-{
-    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
-    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
-    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
-    CRC_SOURCE_DMAC0_gc = (0x04<<0),  /* DMAC Channel 0 */
-    CRC_SOURCE_DMAC1_gc = (0x05<<0),  /* DMAC Channel 1 */
-    CRC_SOURCE_DMAC2_gc = (0x06<<0),  /* DMAC Channel 2 */
-    CRC_SOURCE_DMAC3_gc = (0x07<<0),  /* DMAC Channel 3 */
-} CRC_SOURCE_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_USB_gc = (0x0A<<0),  /* USB Setup, SOF, CRC error and UNF/OVF */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0),  /* Erase Flash Page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0),  /* Write Flash Page */
-    NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0),  /* Erase-and-write Flash Page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /*  Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Flash Range CRC */
-    NVM_CMD_CHIP_ERASE_gc = (0x40<<0),  /* Erase Chip */
-    NVM_CMD_READ_NVM_gc = (0x43<<0),  /* Read NVM */
-    NVM_CMD_WRITE_FUSE_gc = (0x4C<<0),  /* Write Fuse byte */
-    NVM_CMD_ERASE_BOOT_gc = (0x68<<0),  /* Erase Boot Section */
-    NVM_CMD_FLASH_CRC_gc = (0x78<<0),  /* Flash CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-} NVM_LB_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t SCAN;  /* Input Channel Scan */
-    register8_t reserved_0x07;
-} ADC_CH_t;
-
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t reserved_0x05;
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary Register */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-    ADC_CH_MUXPOS_PIN8_gc = (0x08<<3),  /* Input pin 8 */
-    ADC_CH_MUXPOS_PIN9_gc = (0x09<<3),  /* Input pin 9 */
-    ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3),  /* Input pin 10 */
-    ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3),  /* Input pin 11 */
-    ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3),  /* Input pin 12 */
-    ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3),  /* Input pin 13 */
-    ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3),  /* Input pin 14 */
-    ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3),  /* Input pin 15 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x00<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x01<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x02<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x03<<0),  /* Input pin 7 */
-    ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0),  /* PAD Ground (Input Mode = 3) */
-    ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0),  /* Internal Groud (Input Mode = 3) */
-    ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0),  /* Internal Groud (Input Mode = 4) */
-    ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0),  /* PAD Ground (Input Mode = 4) */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Current Limitation Mode */
-typedef enum ADC_CURRLIMIT_enum
-{
-    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No limit */
-    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit, max. sampling rate 1.5MSPS */
-    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, max. sampling rate 1MSPS */
-    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit, max. sampling rate 0.5MSPS */
-} ADC_CURRLIMIT_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_INTVCC_gc = (0x01<<4),  /* Internal VCC / 1.6 */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-    ADC_REFSEL_INTVCC2_gc = (0x04<<4),  /* Internal VCC / 2 */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCSWEEP_gc = (0x06<<0),  /* The ADC is flushed and restarted for accurate timing */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t reserved_0x04;
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t CH0GAINCAL;  /* Gain Calibration */
-    register8_t CH0OFFSETCAL;  /* Offset Calibration */
-    register8_t CH1GAINCAL;  /* Gain Calibration */
-    register8_t CH1OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel 0 only) */
-    DAC_CHSEL_SINGLE1_gc = (0x01<<5),  /* Single channel operation (Channel 1 only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (Channel 0 and channel 1) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Analog Comparator 0 Control */
-    register8_t AC1CTRL;  /* Analog Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Analog Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Analog Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Counter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* SDA Hold Time */
-typedef enum TWI_SDAHOLD_enum
-{
-    TWI_SDAHOLD_OFF_gc = (0x00<<1),  /* SDA Hold Time off */
-    TWI_SDAHOLD_50NS_gc = (0x01<<1),  /* SDA Hold Time 50 ns */
-    TWI_SDAHOLD_300NS_gc = (0x02<<1),  /* SDA Hold Time 300 ns */
-    TWI_SDAHOLD_400NS_gc = (0x03<<1),  /* SDA Hold Time 400 ns */
-} TWI_SDAHOLD_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-USB - USB
---------------------------------------------------------------------------
-*/
-
-/* USB Endpoint */
-typedef struct USB_EP_struct
-{
-    register8_t STATUS;  /* Endpoint Status */
-    register8_t CTRL;  /* Endpoint Control */
-    _WORDREGISTER(CNT);  /* USB Endpoint Counter */
-    _WORDREGISTER(DATAPTR);  /* Data Pointer */
-    _WORDREGISTER(AUXDATA);  /* Auxiliary Data */
-} USB_EP_t;
-
-
-/* Universal Serial Bus */
-typedef struct USB_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t FIFOWP;  /* FIFO Write Pointer Register */
-    register8_t FIFORP;  /* FIFO Read Pointer Register */
-    _WORDREGISTER(EPPTR);  /* Endpoint Configuration Table Pointer */
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t INTFLAGSACLR;  /* Clear Interrupt Flag Register A */
-    register8_t INTFLAGSASET;  /* Set Interrupt Flag Register A */
-    register8_t INTFLAGSBCLR;  /* Clear Interrupt Flag Register B */
-    register8_t INTFLAGSBSET;  /* Set Interrupt Flag Register B */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t reserved_0x20;
-    register8_t reserved_0x21;
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t CAL0;  /* Calibration Byte 0 */
-    register8_t CAL1;  /* Calibration Byte 1 */
-} USB_t;
-
-
-/* USB Endpoint Table */
-typedef struct USB_EP_TABLE_struct
-{
-    USB_EP_t EP0OUT;  /* Endpoint 0 */
-    USB_EP_t EP0IN;  /* Endpoint 0 */
-    USB_EP_t EP1OUT;  /* Endpoint 1 */
-    USB_EP_t EP1IN;  /* Endpoint 1 */
-    USB_EP_t EP2OUT;  /* Endpoint 2 */
-    USB_EP_t EP2IN;  /* Endpoint 2 */
-    USB_EP_t EP3OUT;  /* Endpoint 3 */
-    USB_EP_t EP3IN;  /* Endpoint 3 */
-    USB_EP_t EP4OUT;  /* Endpoint 4 */
-    USB_EP_t EP4IN;  /* Endpoint 4 */
-    USB_EP_t EP5OUT;  /* Endpoint 5 */
-    USB_EP_t EP5IN;  /* Endpoint 5 */
-    USB_EP_t EP6OUT;  /* Endpoint 6 */
-    USB_EP_t EP6IN;  /* Endpoint 6 */
-    USB_EP_t EP7OUT;  /* Endpoint 7 */
-    USB_EP_t EP7IN;  /* Endpoint 7 */
-    USB_EP_t EP8OUT;  /* Endpoint 8 */
-    USB_EP_t EP8IN;  /* Endpoint 8 */
-    USB_EP_t EP9OUT;  /* Endpoint 9 */
-    USB_EP_t EP9IN;  /* Endpoint 9 */
-    USB_EP_t EP10OUT;  /* Endpoint 10 */
-    USB_EP_t EP10IN;  /* Endpoint 10 */
-    USB_EP_t EP11OUT;  /* Endpoint 11 */
-    USB_EP_t EP11IN;  /* Endpoint 11 */
-    USB_EP_t EP12OUT;  /* Endpoint 12 */
-    USB_EP_t EP12IN;  /* Endpoint 12 */
-    USB_EP_t EP13OUT;  /* Endpoint 13 */
-    USB_EP_t EP13IN;  /* Endpoint 13 */
-    USB_EP_t EP14OUT;  /* Endpoint 14 */
-    USB_EP_t EP14IN;  /* Endpoint 14 */
-    USB_EP_t EP15OUT;  /* Endpoint 15 */
-    USB_EP_t EP15IN;  /* Endpoint 15 */
-    register8_t reserved_0x100;
-    register8_t reserved_0x101;
-    register8_t reserved_0x102;
-    register8_t reserved_0x103;
-    register8_t reserved_0x104;
-    register8_t reserved_0x105;
-    register8_t reserved_0x106;
-    register8_t reserved_0x107;
-    register8_t reserved_0x108;
-    register8_t reserved_0x109;
-    register8_t reserved_0x10A;
-    register8_t reserved_0x10B;
-    register8_t reserved_0x10C;
-    register8_t reserved_0x10D;
-    register8_t reserved_0x10E;
-    register8_t reserved_0x10F;
-    register8_t FRAMENUML;  /* Frame Number Low Byte */
-    register8_t FRAMENUMH;  /* Frame Number High Byte */
-} USB_EP_TABLE_t;
-
-/* Interrupt level */
-typedef enum USB_INTLVL_enum
-{
-    USB_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    USB_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    USB_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    USB_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} USB_INTLVL_t;
-
-/* USB Endpoint Type */
-typedef enum USB_EP_TYPE_enum
-{
-    USB_EP_TYPE_DISABLE_gc = (0x00<<6),  /* Endpoint Disabled */
-    USB_EP_TYPE_CONTROL_gc = (0x01<<6),  /* Control */
-    USB_EP_TYPE_BULK_gc = (0x02<<6),  /* Bulk/Interrupt */
-    USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6),  /* Isochronous */
-} USB_EP_TYPE_t;
-
-/* USB Endpoint Buffersize */
-typedef enum USB_EP_BUFSIZE_enum
-{
-    USB_EP_BUFSIZE_8_gc = (0x00<<0),  /* 8 bytes buffer size */
-    USB_EP_BUFSIZE_16_gc = (0x01<<0),  /* 16 bytes buffer size */
-    USB_EP_BUFSIZE_32_gc = (0x02<<0),  /* 32 bytes buffer size */
-    USB_EP_BUFSIZE_64_gc = (0x03<<0),  /* 64 bytes buffer size */
-    USB_EP_BUFSIZE_128_gc = (0x04<<0),  /* 128 bytes buffer size */
-    USB_EP_BUFSIZE_256_gc = (0x05<<0),  /* 256 bytes buffer size */
-    USB_EP_BUFSIZE_512_gc = (0x06<<0),  /* 512 bytes buffer size */
-    USB_EP_BUFSIZE_1023_gc = (0x07<<0),  /* 1023 bytes buffer size */
-} USB_EP_BUFSIZE_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - I/O Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t REMAP;  /* I/O Port Pin Remap Register */
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SINGLESLOPE_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DSTOP_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DSBOTH_gc = (0x06<<0),  /* Dual Slope, Update on both TOP and BOTTOM */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on both TOP and BOTTOM */
-    TC_WGMODE_DSBOTTOM_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Byte Mode */
-typedef enum TC_BYTEM_enum
-{
-    TC_BYTEM_NORMAL_gc = (0x00<<0),  /* 16-bit mode */
-    TC_BYTEM_BYTEMODE_gc = (0x01<<0),  /* Timer/Counter operating in byte mode only */
-    TC_BYTEM_SPLITMODE_gc = (0x02<<0),  /* Timer/Counter split into two 8-bit Counters (TC2) */
-} TC_BYTEM_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-TC2 - 16-bit Timer/Counter type 2
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter type 2 */
-typedef struct TC2_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t reserved_0x03;
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t reserved_0x08;
-    register8_t CTRLF;  /* Control Register F */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t LCNT;  /* Low Byte Count */
-    register8_t HCNT;  /* High Byte Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    register8_t LPER;  /* Low Byte Period */
-    register8_t HPER;  /* High Byte Period */
-    register8_t LCMPA;  /* Low Byte Compare A */
-    register8_t HCMPA;  /* High Byte Compare A */
-    register8_t LCMPB;  /* Low Byte Compare B */
-    register8_t HCMPB;  /* High Byte Compare B */
-    register8_t LCMPC;  /* Low Byte Compare C */
-    register8_t HCMPC;  /* High Byte Compare C */
-    register8_t LCMPD;  /* Low Byte Compare D */
-    register8_t HCMPD;  /* High Byte Compare D */
-} TC2_t;
-
-/* Clock Selection */
-typedef enum TC2_CLKSEL_enum
-{
-    TC2_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC2_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC2_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC2_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC2_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC2_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC2_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC2_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC2_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC2_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC2_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC2_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC2_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC2_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC2_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC2_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC2_CLKSEL_t;
-
-/* Byte Mode */
-typedef enum TC2_BYTEM_enum
-{
-    TC2_BYTEM_NORMAL_gc = (0x00<<0),  /* 16-bit mode */
-    TC2_BYTEM_BYTEMODE_gc = (0x01<<0),  /* Timer/Counter operating in byte mode only (TC2) */
-    TC2_BYTEM_SPLITMODE_gc = (0x02<<0),  /* Timer/Counter split into two 8-bit Counters */
-} TC2_BYTEM_t;
-
-/* High Byte Underflow Interrupt Level */
-typedef enum TC2_HUNFINTLVL_enum
-{
-    TC2_HUNFINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC2_HUNFINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC2_HUNFINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC2_HUNFINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC2_HUNFINTLVL_t;
-
-/* Low Byte Underflow Interrupt Level */
-typedef enum TC2_LUNFINTLVL_enum
-{
-    TC2_LUNFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC2_LUNFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC2_LUNFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC2_LUNFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC2_LUNFINTLVL_t;
-
-/* Low Byte Compare D Interrupt Level */
-typedef enum TC2_LCMPDINTLVL_enum
-{
-    TC2_LCMPDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC2_LCMPDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC2_LCMPDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC2_LCMPDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC2_LCMPDINTLVL_t;
-
-/* Low Byte Compare C Interrupt Level */
-typedef enum TC2_LCMPCINTLVL_enum
-{
-    TC2_LCMPCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC2_LCMPCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC2_LCMPCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC2_LCMPCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC2_LCMPCINTLVL_t;
-
-/* Low Byte Compare B Interrupt Level */
-typedef enum TC2_LCMPBINTLVL_enum
-{
-    TC2_LCMPBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC2_LCMPBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC2_LCMPBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC2_LCMPBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC2_LCMPBINTLVL_t;
-
-/* Low Byte Compare A Interrupt Level */
-typedef enum TC2_LCMPAINTLVL_enum
-{
-    TC2_LCMPAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC2_LCMPAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC2_LCMPAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC2_LCMPAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC2_LCMPAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC2_CMD_enum
-{
-    TC2_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC2_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC2_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC2_CMD_t;
-
-/* Timer/Counter Command */
-typedef enum TC2_CMDEN_enum
-{
-    TC2_CMDEN_LOW_gc = (0x01<<0),  /* Low Byte Timer/Counter */
-    TC2_CMDEN_HIGH_gc = (0x02<<0),  /* High Byte Timer/Counter */
-    TC2_CMDEN_BOTH_gc = (0x03<<0),  /* Both Low Byte and High Byte Timer/Counters */
-} TC2_CMDEN_t;
-
-
-/*
---------------------------------------------------------------------------
-AWEX - Timer/Counter Advanced Waveform Extension
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t STATUSSET;  /* Status Set Register */
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-
-/*
---------------------------------------------------------------------------
-HIRES - Timer/Counter High-Resolution Extension
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRLA;  /* Control Register */
-} HIRES_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-FUSE - Fuses and Lockbits
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t reserved_0x00;
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* Timer Oscillator pin location */
-typedef enum TOSCSEL_enum
-{
-    TOSCSEL_ALTERNATE_gc = (0x00<<5),  /* TOSC1 / TOSC2 on separate pins */
-    TOSCSEL_XTAL_gc = (0x01<<5),  /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
-} TOSCSEL_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_SAMPLED_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINUOUS_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* BOD operation */
-typedef enum BODACT_enum
-{
-    BODACT_SAMPLED_gc = (0x01<<4),  /* BOD enabled in sampled mode */
-    BODACT_CONTINUOUS_gc = (0x02<<4),  /* BOD enabled continuously */
-    BODACT_DISABLED_gc = (0x03<<4),  /* BOD Disabled */
-} BODACT_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WDP_enum
-{
-    WDP_8CLK_gc = (0x00<<0),  /* 8 cycles (8ms @ 3.3V) */
-    WDP_16CLK_gc = (0x01<<0),  /* 16 cycles (16ms @ 3.3V) */
-    WDP_32CLK_gc = (0x02<<0),  /* 32 cycles (32ms @ 3.3V) */
-    WDP_64CLK_gc = (0x03<<0),  /* 64 cycles (64ms @ 3.3V) */
-    WDP_128CLK_gc = (0x04<<0),  /* 128 cycles (0.125s @ 3.3V) */
-    WDP_256CLK_gc = (0x05<<0),  /* 256 cycles (0.25s @ 3.3V) */
-    WDP_512CLK_gc = (0x06<<0),  /* 512 cycles (0.5s @ 3.3V) */
-    WDP_1KCLK_gc = (0x07<<0),  /* 1K cycles (1s @ 3.3V) */
-    WDP_2KCLK_gc = (0x08<<0),  /* 2K cycles (2s @ 3.3V) */
-    WDP_4KCLK_gc = (0x09<<0),  /* 4K cycles (4s @ 3.3V) */
-    WDP_8KCLK_gc = (0x0A<<0),  /* 8K cycles (8s @ 3.3V) */
-} WDP_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V8_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V0_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V2_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V4_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V6_gc = (0x02<<0),  /* 2.6 V */
-    BODLVL_2V8_gc = (0x01<<0),  /* 2.8 V */
-    BODLVL_3V0_gc = (0x00<<0),  /* 3.0 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-LOCKBIT - Fuses and Lockbits
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum FUSE_BLBB_enum
-{
-    FUSE_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-    FUSE_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    FUSE_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    FUSE_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-} FUSE_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum FUSE_BLBA_enum
-{
-    FUSE_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-    FUSE_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    FUSE_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    FUSE_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-} FUSE_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum FUSE_BLBAT_enum
-{
-    FUSE_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-    FUSE_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    FUSE_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    FUSE_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-} FUSE_BLBAT_t;
-
-/* Lock bits */
-typedef enum FUSE_LB_enum
-{
-    FUSE_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-    FUSE_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    FUSE_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-} FUSE_LB_t;
-
-
-/*
---------------------------------------------------------------------------
-SIGROW - Signature Row
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2 MHz Calibration Value B */
-    register8_t RCOSC2MA;  /* RCOSC 2 MHz Calibration Value A */
-    register8_t RCOSC32K;  /* RCOSC 32.768 kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32 MHz Calibration Value B */
-    register8_t RCOSC32MA;  /* RCOSC 32 MHz Calibration Value A */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t USBCAL0;  /* USB Calibration Byte 0 */
-    register8_t USBCAL1;  /* USB Calibration Byte 1 */
-    register8_t USBRCOSC;  /* USB RCOSC Calibration Value B */
-    register8_t USBRCOSCA;  /* USB RCOSC Calibration Value A */
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 1 */
-    register8_t DACA0OFFCAL;  /* DACA0 Calibration Byte 0 */
-    register8_t DACA0GAINCAL;  /* DACA0 Calibration Byte 1 */
-    register8_t DACB0OFFCAL;  /* DACB0 Calibration Byte 0 */
-    register8_t DACB0GAINCAL;  /* DACB0 Calibration Byte 1 */
-    register8_t DACA1OFFCAL;  /* DACA1 Calibration Byte 0 */
-    register8_t DACA1GAINCAL;  /* DACA1 Calibration Byte 1 */
-    register8_t DACB1OFFCAL;  /* DACB1 Calibration Byte 0 */
-    register8_t DACB1GAINCAL;  /* DACB1 Calibration Byte 1 */
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-    register8_t reserved_0x3F;
-    register8_t reserved_0x40;
-    register8_t reserved_0x41;
-    register8_t reserved_0x42;
-    register8_t reserved_0x43;
-    register8_t reserved_0x44;
-    register8_t reserved_0x45;
-    register8_t reserved_0x46;
-    register8_t reserved_0x47;
-} NVM_PROD_SIGNATURES_t;
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Multi-level Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* I/O port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Module */
-#define CRC    (*(CRC_t *) 0x00D0)  /* Cyclic Redundancy Checker */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non-volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog-to-Digital Converter */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital-to-Analog Converter */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface */
-#define USB    (*(USB_t *) 0x04C0)  /* Universal Serial Bus */
-#define PORTA    (*(PORT_t *) 0x0600)  /* I/O Ports */
-#define PORTB    (*(PORT_t *) 0x0620)  /* I/O Ports */
-#define PORTC    (*(PORT_t *) 0x0640)  /* I/O Ports */
-#define PORTD    (*(PORT_t *) 0x0660)  /* I/O Ports */
-#define PORTE    (*(PORT_t *) 0x0680)  /* I/O Ports */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* I/O Ports */
-#define TCC0    (*(TC0_t *) 0x0800)  /* 16-bit Timer/Counter 0 */
-#define TCC2    (*(TC2_t *) 0x0800)  /* 16-bit Timer/Counter type 2 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* 16-bit Timer/Counter 1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* 16-bit Timer/Counter 0 */
-#define TCD2    (*(TC2_t *) 0x0900)  /* 16-bit Timer/Counter type 2 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* 16-bit Timer/Counter 1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* 16-bit Timer/Counter 0 */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
-#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
-#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
-#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
-#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
-#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
-#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
-#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
-#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
-#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
-#define GPIO_GPIORA  _SFR_MEM8(0x000A)
-#define GPIO_GPIORB  _SFR_MEM8(0x000B)
-#define GPIO_GPIORC  _SFR_MEM8(0x000C)
-#define GPIO_GPIORD  _SFR_MEM8(0x000D)
-#define GPIO_GPIORE  _SFR_MEM8(0x000E)
-#define GPIO_GPIORF  _SFR_MEM8(0x000F)
-
-/* Deprecated */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* NVM_FUSES - Fuses */
-#define FUSE_FUSEBYTE1  _SFR_MEM8(0x0001)
-#define FUSE_FUSEBYTE2  _SFR_MEM8(0x0002)
-#define FUSE_FUSEBYTE4  _SFR_MEM8(0x0004)
-#define FUSE_FUSEBYTE5  _SFR_MEM8(0x0005)
-
-/* NVM_LOCKBITS - Lock Bits */
-#define LOCKBIT_LOCKBITS  _SFR_MEM8(0x0000)
-
-/* NVM_PROD_SIGNATURES - Production Signatures */
-#define PRODSIGNATURES_RCOSC2M  _SFR_MEM8(0x0000)
-#define PRODSIGNATURES_RCOSC2MA  _SFR_MEM8(0x0001)
-#define PRODSIGNATURES_RCOSC32K  _SFR_MEM8(0x0002)
-#define PRODSIGNATURES_RCOSC32M  _SFR_MEM8(0x0003)
-#define PRODSIGNATURES_RCOSC32MA  _SFR_MEM8(0x0004)
-#define PRODSIGNATURES_LOTNUM0  _SFR_MEM8(0x0008)
-#define PRODSIGNATURES_LOTNUM1  _SFR_MEM8(0x0009)
-#define PRODSIGNATURES_LOTNUM2  _SFR_MEM8(0x000A)
-#define PRODSIGNATURES_LOTNUM3  _SFR_MEM8(0x000B)
-#define PRODSIGNATURES_LOTNUM4  _SFR_MEM8(0x000C)
-#define PRODSIGNATURES_LOTNUM5  _SFR_MEM8(0x000D)
-#define PRODSIGNATURES_WAFNUM  _SFR_MEM8(0x0010)
-#define PRODSIGNATURES_COORDX0  _SFR_MEM8(0x0012)
-#define PRODSIGNATURES_COORDX1  _SFR_MEM8(0x0013)
-#define PRODSIGNATURES_COORDY0  _SFR_MEM8(0x0014)
-#define PRODSIGNATURES_COORDY1  _SFR_MEM8(0x0015)
-#define PRODSIGNATURES_USBCAL0  _SFR_MEM8(0x001A)
-#define PRODSIGNATURES_USBCAL1  _SFR_MEM8(0x001B)
-#define PRODSIGNATURES_USBRCOSC  _SFR_MEM8(0x001C)
-#define PRODSIGNATURES_USBRCOSCA  _SFR_MEM8(0x001D)
-#define PRODSIGNATURES_ADCACAL0  _SFR_MEM8(0x0020)
-#define PRODSIGNATURES_ADCACAL1  _SFR_MEM8(0x0021)
-#define PRODSIGNATURES_ADCBCAL0  _SFR_MEM8(0x0024)
-#define PRODSIGNATURES_ADCBCAL1  _SFR_MEM8(0x0025)
-#define PRODSIGNATURES_TEMPSENSE0  _SFR_MEM8(0x002E)
-#define PRODSIGNATURES_TEMPSENSE1  _SFR_MEM8(0x002F)
-#define PRODSIGNATURES_DACA0OFFCAL  _SFR_MEM8(0x0030)
-#define PRODSIGNATURES_DACA0GAINCAL  _SFR_MEM8(0x0031)
-#define PRODSIGNATURES_DACB0OFFCAL  _SFR_MEM8(0x0032)
-#define PRODSIGNATURES_DACB0GAINCAL  _SFR_MEM8(0x0033)
-#define PRODSIGNATURES_DACA1OFFCAL  _SFR_MEM8(0x0034)
-#define PRODSIGNATURES_DACA1GAINCAL  _SFR_MEM8(0x0035)
-#define PRODSIGNATURES_DACB1OFFCAL  _SFR_MEM8(0x0036)
-#define PRODSIGNATURES_DACB1GAINCAL  _SFR_MEM8(0x0037)
-
-/* VPORT - Virtual Port */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT - Virtual Port */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT - Virtual Port */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT - Virtual Port */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-#define CLK_USBCTRL  _SFR_MEM8(0x0044)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLL - DFLL */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLL - DFLL */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_ANAINIT  _SFR_MEM8(0x0097)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - I/O port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-#define PORTCFG_EBIOUT  _SFR_MEM8(0x00B5)
-#define PORTCFG_EVOUTSEL  _SFR_MEM8(0x00B6)
-
-/* AES - AES Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* CRC - Cyclic Redundancy Checker */
-#define CRC_CTRL  _SFR_MEM8(0x00D0)
-#define CRC_STATUS  _SFR_MEM8(0x00D1)
-#define CRC_DATAIN  _SFR_MEM8(0x00D3)
-#define CRC_CHECKSUM0  _SFR_MEM8(0x00D4)
-#define CRC_CHECKSUM1  _SFR_MEM8(0x00D5)
-#define CRC_CHECKSUM2  _SFR_MEM8(0x00D6)
-#define CRC_CHECKSUM3  _SFR_MEM8(0x00D7)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non-volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADC - Analog-to-Digital Converter */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_TEMP  _SFR_MEM8(0x0207)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH0_SCAN  _SFR_MEM8(0x0226)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH1_SCAN  _SFR_MEM8(0x022E)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH2_SCAN  _SFR_MEM8(0x0236)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-#define ADCA_CH3_SCAN  _SFR_MEM8(0x023E)
-
-/* DAC - Digital-to-Analog Converter */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_CH0GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_CH0OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH1GAINCAL  _SFR_MEM8(0x032A)
-#define DACB_CH1OFFSETCAL  _SFR_MEM8(0x032B)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* AC - Analog Comparator */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWI - Two-Wire Interface */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWI - Two-Wire Interface */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* USB - Universal Serial Bus */
-#define USB_CTRLA  _SFR_MEM8(0x04C0)
-#define USB_CTRLB  _SFR_MEM8(0x04C1)
-#define USB_STATUS  _SFR_MEM8(0x04C2)
-#define USB_ADDR  _SFR_MEM8(0x04C3)
-#define USB_FIFOWP  _SFR_MEM8(0x04C4)
-#define USB_FIFORP  _SFR_MEM8(0x04C5)
-#define USB_EPPTR  _SFR_MEM16(0x04C6)
-#define USB_INTCTRLA  _SFR_MEM8(0x04C8)
-#define USB_INTCTRLB  _SFR_MEM8(0x04C9)
-#define USB_INTFLAGSACLR  _SFR_MEM8(0x04CA)
-#define USB_INTFLAGSASET  _SFR_MEM8(0x04CB)
-#define USB_INTFLAGSBCLR  _SFR_MEM8(0x04CC)
-#define USB_INTFLAGSBSET  _SFR_MEM8(0x04CD)
-#define USB_CAL0  _SFR_MEM8(0x04FA)
-#define USB_CAL1  _SFR_MEM8(0x04FB)
-
-/* PORT - I/O Ports */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_REMAP  _SFR_MEM8(0x060E)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORT - I/O Ports */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_REMAP  _SFR_MEM8(0x062E)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORT - I/O Ports */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_REMAP  _SFR_MEM8(0x064E)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORT - I/O Ports */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_REMAP  _SFR_MEM8(0x066E)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORT - I/O Ports */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_REMAP  _SFR_MEM8(0x068E)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORT - I/O Ports */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_REMAP  _SFR_MEM8(0x07EE)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TC0 - 16-bit Timer/Counter 0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TC2 - 16-bit Timer/Counter type 2 */
-#define TCC2_CTRLA  _SFR_MEM8(0x0800)
-#define TCC2_CTRLB  _SFR_MEM8(0x0801)
-#define TCC2_CTRLC  _SFR_MEM8(0x0802)
-#define TCC2_CTRLE  _SFR_MEM8(0x0804)
-#define TCC2_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC2_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC2_CTRLF  _SFR_MEM8(0x0809)
-#define TCC2_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC2_LCNT  _SFR_MEM8(0x0820)
-#define TCC2_HCNT  _SFR_MEM8(0x0821)
-#define TCC2_LPER  _SFR_MEM8(0x0826)
-#define TCC2_HPER  _SFR_MEM8(0x0827)
-#define TCC2_LCMPA  _SFR_MEM8(0x0828)
-#define TCC2_HCMPA  _SFR_MEM8(0x0829)
-#define TCC2_LCMPB  _SFR_MEM8(0x082A)
-#define TCC2_HCMPB  _SFR_MEM8(0x082B)
-#define TCC2_LCMPC  _SFR_MEM8(0x082C)
-#define TCC2_HCMPC  _SFR_MEM8(0x082D)
-#define TCC2_LCMPD  _SFR_MEM8(0x082E)
-#define TCC2_HCMPD  _SFR_MEM8(0x082F)
-
-/* TC1 - 16-bit Timer/Counter 1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEX - Advanced Waveform Extension */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_STATUSSET  _SFR_MEM8(0x0885)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRES - High-Resolution Extension */
-#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPI - Serial Peripheral Interface */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TC0 - 16-bit Timer/Counter 0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TC2 - 16-bit Timer/Counter type 2 */
-#define TCD2_CTRLA  _SFR_MEM8(0x0900)
-#define TCD2_CTRLB  _SFR_MEM8(0x0901)
-#define TCD2_CTRLC  _SFR_MEM8(0x0902)
-#define TCD2_CTRLE  _SFR_MEM8(0x0904)
-#define TCD2_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD2_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD2_CTRLF  _SFR_MEM8(0x0909)
-#define TCD2_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD2_LCNT  _SFR_MEM8(0x0920)
-#define TCD2_HCNT  _SFR_MEM8(0x0921)
-#define TCD2_LPER  _SFR_MEM8(0x0926)
-#define TCD2_HPER  _SFR_MEM8(0x0927)
-#define TCD2_LCMPA  _SFR_MEM8(0x0928)
-#define TCD2_HCMPA  _SFR_MEM8(0x0929)
-#define TCD2_LCMPB  _SFR_MEM8(0x092A)
-#define TCD2_HCMPB  _SFR_MEM8(0x092B)
-#define TCD2_LCMPC  _SFR_MEM8(0x092C)
-#define TCD2_HCMPC  _SFR_MEM8(0x092D)
-#define TCD2_LCMPD  _SFR_MEM8(0x092E)
-#define TCD2_HCMPD  _SFR_MEM8(0x092F)
-
-/* TC1 - 16-bit Timer/Counter 1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRES - High-Resolution Extension */
-#define HIRESD_CTRLA  _SFR_MEM8(0x0990)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPI - Serial Peripheral Interface */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TC0 - 16-bit Timer/Counter 0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* HIRES - High-Resolution Extension */
-#define HIRESE_CTRLA  _SFR_MEM8(0x0A90)
-
-/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* VPORT - Virtual Ports */
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR0  bit masks and bit positions */
-#define OCD_OCDRD_gm  0xFF  /* OCDR Dirty group mask. */
-#define OCD_OCDRD_gp  0  /* OCDR Dirty group position. */
-#define OCD_OCDRD0_bm  (1<<0)  /* OCDR Dirty bit 0 mask. */
-#define OCD_OCDRD0_bp  0  /* OCDR Dirty bit 0 position. */
-#define OCD_OCDRD1_bm  (1<<1)  /* OCDR Dirty bit 1 mask. */
-#define OCD_OCDRD1_bp  1  /* OCDR Dirty bit 1 position. */
-#define OCD_OCDRD2_bm  (1<<2)  /* OCDR Dirty bit 2 mask. */
-#define OCD_OCDRD2_bp  2  /* OCDR Dirty bit 2 position. */
-#define OCD_OCDRD3_bm  (1<<3)  /* OCDR Dirty bit 3 mask. */
-#define OCD_OCDRD3_bp  3  /* OCDR Dirty bit 3 position. */
-#define OCD_OCDRD4_bm  (1<<4)  /* OCDR Dirty bit 4 mask. */
-#define OCD_OCDRD4_bp  4  /* OCDR Dirty bit 4 position. */
-#define OCD_OCDRD5_bm  (1<<5)  /* OCDR Dirty bit 5 mask. */
-#define OCD_OCDRD5_bp  5  /* OCDR Dirty bit 5 position. */
-#define OCD_OCDRD6_bm  (1<<6)  /* OCDR Dirty bit 6 mask. */
-#define OCD_OCDRD6_bp  6  /* OCDR Dirty bit 6 position. */
-#define OCD_OCDRD7_bm  (1<<7)  /* OCDR Dirty bit 7 mask. */
-#define OCD_OCDRD7_bp  7  /* OCDR Dirty bit 7 position. */
-
-/* OCD.OCDR1  bit masks and bit positions */
-/* OCD_OCDRD  Predefined. */
-/* OCD_OCDRD  Predefined. */
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* Clock Source Enable bit position. */
-
-/* CLK.USBCTRL  bit masks and bit positions */
-#define CLK_USBPSDIV_gm  0x38  /* Prescaler Division Factor group mask. */
-#define CLK_USBPSDIV_gp  3  /* Prescaler Division Factor group position. */
-#define CLK_USBPSDIV0_bm  (1<<3)  /* Prescaler Division Factor bit 0 mask. */
-#define CLK_USBPSDIV0_bp  3  /* Prescaler Division Factor bit 0 position. */
-#define CLK_USBPSDIV1_bm  (1<<4)  /* Prescaler Division Factor bit 1 mask. */
-#define CLK_USBPSDIV1_bp  4  /* Prescaler Division Factor bit 1 position. */
-#define CLK_USBPSDIV2_bm  (1<<5)  /* Prescaler Division Factor bit 2 mask. */
-#define CLK_USBPSDIV2_bp  5  /* Prescaler Division Factor bit 2 position. */
-
-#define CLK_USBSRC_gm  0x06  /* Clock Source group mask. */
-#define CLK_USBSRC_gp  1  /* Clock Source group position. */
-#define CLK_USBSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_USBSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_USBSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_USBSRC1_bp  2  /* Clock Source bit 1 position. */
-
-#define CLK_USBSEN_bm  0x01  /* Clock Source Enable bit mask. */
-#define CLK_USBSEN_bp  0  /* Clock Source Enable bit position. */
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_USB_bm  0x40  /* USB bit mask. */
-#define PR_USB_bp  6  /* USB bit position. */
-
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC  Predefined. */
-/* PR_DAC  Predefined. */
-
-/* PR_ADC  Predefined. */
-/* PR_ADC  Predefined. */
-
-/* PR_AC  Predefined. */
-/* PR_AC  Predefined. */
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI  Predefined. */
-/* PR_TWI  Predefined. */
-
-/* PR_USART1  Predefined. */
-/* PR_USART1  Predefined. */
-
-/* PR_USART0  Predefined. */
-/* PR_USART0  Predefined. */
-
-/* PR_SPI  Predefined. */
-/* PR_SPI  Predefined. */
-
-/* PR_HIRES  Predefined. */
-/* PR_HIRES  Predefined. */
-
-/* PR_TC1  Predefined. */
-/* PR_TC1  Predefined. */
-
-/* PR_TC0  Predefined. */
-/* PR_TC0  Predefined. */
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI  Predefined. */
-/* PR_TWI  Predefined. */
-
-/* PR_USART1  Predefined. */
-/* PR_USART1  Predefined. */
-
-/* PR_USART0  Predefined. */
-/* PR_USART0  Predefined. */
-
-/* PR_SPI  Predefined. */
-/* PR_SPI  Predefined. */
-
-/* PR_HIRES  Predefined. */
-/* PR_HIRES  Predefined. */
-
-/* PR_TC1  Predefined. */
-/* PR_TC1  Predefined. */
-
-/* PR_TC0  Predefined. */
-/* PR_TC0  Predefined. */
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI  Predefined. */
-/* PR_TWI  Predefined. */
-
-/* PR_USART1  Predefined. */
-/* PR_USART1  Predefined. */
-
-/* PR_USART0  Predefined. */
-/* PR_USART0  Predefined. */
-
-/* PR_SPI  Predefined. */
-/* PR_SPI  Predefined. */
-
-/* PR_HIRES  Predefined. */
-/* PR_HIRES  Predefined. */
-
-/* PR_TC1  Predefined. */
-/* PR_TC1  Predefined. */
-
-/* PR_TC0  Predefined. */
-/* PR_TC0  Predefined. */
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32.768 kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32 MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32 MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2 MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2 MHz RC Oscillator Enable bit position. */
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32.768 kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32 MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32 MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2 MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2 MHz RC Oscillator Ready bit position. */
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCPWR_bm  0x10  /* 16 MHz Crystal Oscillator High Power mode bit mask. */
-#define OSC_XOSCPWR_bp  4  /* 16 MHz Crystal Oscillator High Power mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_PLLFDIF_bm  0x08  /* PLL Failure Detection Interrupt Flag bit mask. */
-#define OSC_PLLFDIF_bp  3  /* PLL Failure Detection Interrupt Flag bit position. */
-
-#define OSC_PLLFDEN_bm  0x04  /* PLL Failure Detection Enable bit mask. */
-#define OSC_PLLFDEN_bp  2  /* PLL Failure Detection Enable bit position. */
-
-#define OSC_XOSCFDIF_bm  0x02  /* XOSC Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* XOSC Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* XOSC Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* XOSC Failure Detection Enable bit position. */
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLDIV_bm  0x20  /* Divide by 2 bit mask. */
-#define OSC_PLLDIV_bp  5  /* Divide by 2 bit position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_gm  0x06  /* 32 MHz DFLL Calibration Reference group mask. */
-#define OSC_RC32MCREF_gp  1  /* 32 MHz DFLL Calibration Reference group position. */
-#define OSC_RC32MCREF0_bm  (1<<1)  /* 32 MHz DFLL Calibration Reference bit 0 mask. */
-#define OSC_RC32MCREF0_bp  1  /* 32 MHz DFLL Calibration Reference bit 0 position. */
-#define OSC_RC32MCREF1_bm  (1<<2)  /* 32 MHz DFLL Calibration Reference bit 1 mask. */
-#define OSC_RC32MCREF1_bp  2  /* 32 MHz DFLL Calibration Reference bit 1 position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2 MHz DFLL Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2 MHz DFLL Calibration Reference bit position. */
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration Value A group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration Value A group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration Value A bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration Value A bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration Value A bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration Value A bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration Value A bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration Value A bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration Value A bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration Value A bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration Value A bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration Value A bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration Value A bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration Value A bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration Value A bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration Value A bit 6 position. */
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration Value B group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration Value B group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration Value B bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration Value B bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration Value B bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration Value B bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration Value B bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration Value B bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration Value B bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration Value B bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration Value B bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration Value B bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration Value B bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration Value B bit 5 position. */
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-/* MCU.ANAINIT  bit masks and bit positions */
-#define MCU_STARTUPDLYB_gm  0x0C  /* Analog startup delay Port B group mask. */
-#define MCU_STARTUPDLYB_gp  2  /* Analog startup delay Port B group position. */
-#define MCU_STARTUPDLYB0_bm  (1<<2)  /* Analog startup delay Port B bit 0 mask. */
-#define MCU_STARTUPDLYB0_bp  2  /* Analog startup delay Port B bit 0 position. */
-#define MCU_STARTUPDLYB1_bm  (1<<3)  /* Analog startup delay Port B bit 1 mask. */
-#define MCU_STARTUPDLYB1_bp  3  /* Analog startup delay Port B bit 1 position. */
-
-#define MCU_STARTUPDLYA_gm  0x03  /* Analog startup delay Port A group mask. */
-#define MCU_STARTUPDLYA_gp  0  /* Analog startup delay Port A group position. */
-#define MCU_STARTUPDLYA0_bm  (1<<0)  /* Analog startup delay Port A bit 0 mask. */
-#define MCU_STARTUPDLYA0_bp  0  /* Analog startup delay Port A bit 0 position. */
-#define MCU_STARTUPDLYA1_bm  (1<<1)  /* Analog startup delay Port A bit 1 mask. */
-#define MCU_STARTUPDLYA1_bp  1  /* Analog startup delay Port A bit 1 position. */
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXFLOCK_bm  0x08  /* AWeX on T/C F0 Lock bit mask. */
-#define MCU_AWEXFLOCK_bp  3  /* AWeX on T/C F0 Lock bit position. */
-
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXDLOCK_bm  0x02  /* AWeX on T/C D0 Lock bit mask. */
-#define MCU_AWEXDLOCK_bp  1  /* AWeX on T/C D0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-/* PMIC.INTPRI  bit masks and bit positions */
-#define PMIC_INTPRI_gm  0xFF  /* Interrupt Priority group mask. */
-#define PMIC_INTPRI_gp  0  /* Interrupt Priority group position. */
-#define PMIC_INTPRI0_bm  (1<<0)  /* Interrupt Priority bit 0 mask. */
-#define PMIC_INTPRI0_bp  0  /* Interrupt Priority bit 0 position. */
-#define PMIC_INTPRI1_bm  (1<<1)  /* Interrupt Priority bit 1 mask. */
-#define PMIC_INTPRI1_bp  1  /* Interrupt Priority bit 1 position. */
-#define PMIC_INTPRI2_bm  (1<<2)  /* Interrupt Priority bit 2 mask. */
-#define PMIC_INTPRI2_bp  2  /* Interrupt Priority bit 2 position. */
-#define PMIC_INTPRI3_bm  (1<<3)  /* Interrupt Priority bit 3 mask. */
-#define PMIC_INTPRI3_bp  3  /* Interrupt Priority bit 3 position. */
-#define PMIC_INTPRI4_bm  (1<<4)  /* Interrupt Priority bit 4 mask. */
-#define PMIC_INTPRI4_bp  4  /* Interrupt Priority bit 4 position. */
-#define PMIC_INTPRI5_bm  (1<<5)  /* Interrupt Priority bit 5 mask. */
-#define PMIC_INTPRI5_bp  5  /* Interrupt Priority bit 5 position. */
-#define PMIC_INTPRI6_bm  (1<<6)  /* Interrupt Priority bit 6 mask. */
-#define PMIC_INTPRI6_bp  6  /* Interrupt Priority bit 6 position. */
-#define PMIC_INTPRI7_bm  (1<<7)  /* Interrupt Priority bit 7 mask. */
-#define PMIC_INTPRI7_bp  7  /* Interrupt Priority bit 7 position. */
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-/* PORTCFG - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Peripheral Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Peripheral Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Peripheral Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Peripheral Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Peripheral Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Peripheral Clock Output Port bit 1 position. */
-
-#define PORTCFG_CLKOUTSEL_gm  0x0C  /* Peripheral Clock Output Select group mask. */
-#define PORTCFG_CLKOUTSEL_gp  2  /* Peripheral Clock Output Select group position. */
-#define PORTCFG_CLKOUTSEL0_bm  (1<<2)  /* Peripheral Clock Output Select bit 0 mask. */
-#define PORTCFG_CLKOUTSEL0_bp  2  /* Peripheral Clock Output Select bit 0 position. */
-#define PORTCFG_CLKOUTSEL1_bm  (1<<3)  /* Peripheral Clock Output Select bit 1 mask. */
-#define PORTCFG_CLKOUTSEL1_bp  3  /* Peripheral Clock Output Select bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-#define PORTCFG_RTCOUT_bm  0x40  /* RTC Clock Output bit mask. */
-#define PORTCFG_RTCOUT_bp  6  /* RTC Clock Output bit position. */
-
-#define PORTCFG_CLKEVPIN_bm  0x80  /* Peripheral Clock and Event Output pin Select bit mask. */
-#define PORTCFG_CLKEVPIN_bp  7  /* Peripheral Clock and Event Output pin Select bit position. */
-
-/* PORTCFG.EBIOUT  bit masks and bit positions */
-#define PORTCFG_EBICSOUT_gm  0x03  /* EBI Chip Select Output group mask. */
-#define PORTCFG_EBICSOUT_gp  0  /* EBI Chip Select Output group position. */
-#define PORTCFG_EBICSOUT0_bm  (1<<0)  /* EBI Chip Select Output bit 0 mask. */
-#define PORTCFG_EBICSOUT0_bp  0  /* EBI Chip Select Output bit 0 position. */
-#define PORTCFG_EBICSOUT1_bm  (1<<1)  /* EBI Chip Select Output bit 1 mask. */
-#define PORTCFG_EBICSOUT1_bp  1  /* EBI Chip Select Output bit 1 position. */
-
-#define PORTCFG_EBIADROUT_gm  0x0C  /* EBI Address Output group mask. */
-#define PORTCFG_EBIADROUT_gp  2  /* EBI Address Output group position. */
-#define PORTCFG_EBIADROUT0_bm  (1<<2)  /* EBI Address Output bit 0 mask. */
-#define PORTCFG_EBIADROUT0_bp  2  /* EBI Address Output bit 0 position. */
-#define PORTCFG_EBIADROUT1_bm  (1<<3)  /* EBI Address Output bit 1 mask. */
-#define PORTCFG_EBIADROUT1_bp  3  /* EBI Address Output bit 1 position. */
-
-/* PORTCFG.EVOUTSEL  bit masks and bit positions */
-#define PORTCFG_EVOUTSEL_gm  0x07  /* Event Output Select group mask. */
-#define PORTCFG_EVOUTSEL_gp  0  /* Event Output Select group position. */
-#define PORTCFG_EVOUTSEL0_bm  (1<<0)  /* Event Output Select bit 0 mask. */
-#define PORTCFG_EVOUTSEL0_bp  0  /* Event Output Select bit 0 position. */
-#define PORTCFG_EVOUTSEL1_bm  (1<<1)  /* Event Output Select bit 1 mask. */
-#define PORTCFG_EVOUTSEL1_bp  1  /* Event Output Select bit 1 position. */
-#define PORTCFG_EVOUTSEL2_bm  (1<<2)  /* Event Output Select bit 2 mask. */
-#define PORTCFG_EVOUTSEL2_bp  2  /* Event Output Select bit 2 position. */
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-/* CRC - Cyclic Redundancy Checker */
-/* CRC.CTRL  bit masks and bit positions */
-#define CRC_RESET_gm  0xC0  /* Reset group mask. */
-#define CRC_RESET_gp  6  /* Reset group position. */
-#define CRC_RESET0_bm  (1<<6)  /* Reset bit 0 mask. */
-#define CRC_RESET0_bp  6  /* Reset bit 0 position. */
-#define CRC_RESET1_bm  (1<<7)  /* Reset bit 1 mask. */
-#define CRC_RESET1_bp  7  /* Reset bit 1 position. */
-
-#define CRC_CRC32_bm  0x20  /* CRC Mode bit mask. */
-#define CRC_CRC32_bp  5  /* CRC Mode bit position. */
-
-#define CRC_SOURCE_gm  0x0F  /* Input Source group mask. */
-#define CRC_SOURCE_gp  0  /* Input Source group position. */
-#define CRC_SOURCE0_bm  (1<<0)  /* Input Source bit 0 mask. */
-#define CRC_SOURCE0_bp  0  /* Input Source bit 0 position. */
-#define CRC_SOURCE1_bm  (1<<1)  /* Input Source bit 1 mask. */
-#define CRC_SOURCE1_bp  1  /* Input Source bit 1 position. */
-#define CRC_SOURCE2_bm  (1<<2)  /* Input Source bit 2 mask. */
-#define CRC_SOURCE2_bp  2  /* Input Source bit 2 position. */
-#define CRC_SOURCE3_bm  (1<<3)  /* Input Source bit 3 mask. */
-#define CRC_SOURCE3_bp  3  /* Input Source bit 3 position. */
-
-/* CRC.STATUS  bit masks and bit positions */
-#define CRC_ZERO_bm  0x02  /* Zero detection bit mask. */
-#define CRC_ZERO_bp  1  /* Zero detection bit position. */
-
-#define CRC_BUSY_bm  0x01  /* Busy bit mask. */
-#define CRC_BUSY_bp  0  /* Busy bit position. */
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX  Predefined. */
-/* EVSYS_CHMUX  Predefined. */
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM  Predefined. */
-/* EVSYS_QDIRM  Predefined. */
-
-/* EVSYS_QDIEN  Predefined. */
-/* EVSYS_QDIEN  Predefined. */
-
-/* EVSYS_QDEN  Predefined. */
-/* EVSYS_QDEN  Predefined. */
-
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM  Predefined. */
-/* EVSYS_QDIRM  Predefined. */
-
-/* EVSYS_QDIEN  Predefined. */
-/* EVSYS_QDIEN  Predefined. */
-
-/* EVSYS_QDEN  Predefined. */
-/* EVSYS_QDEN  Predefined. */
-
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT  Predefined. */
-/* EVSYS_DIGFILT  Predefined. */
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0x7F  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAIN_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAIN_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAIN0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAIN0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAIN1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAIN1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAIN2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAIN2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* MUX selection on Positive ADC input group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* MUX selection on Positive ADC input group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* MUX selection on Positive ADC input bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* MUX selection on Positive ADC input bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* MUX selection on Positive ADC input bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* MUX selection on Positive ADC input bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* MUX selection on Positive ADC input bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* MUX selection on Positive ADC input bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* MUX selection on Positive ADC input bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* MUX selection on Positive ADC input bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* MUX selection on Internal ADC input group mask. */
-#define ADC_CH_MUXINT_gp  3  /* MUX selection on Internal ADC input group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* MUX selection on Internal ADC input bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* MUX selection on Internal ADC input bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* MUX selection on Internal ADC input bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* MUX selection on Internal ADC input bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* MUX selection on Internal ADC input bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* MUX selection on Internal ADC input bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* MUX selection on Internal ADC input bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* MUX selection on Internal ADC input bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x07  /* MUX selection on Negative ADC input group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* MUX selection on Negative ADC input group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* MUX selection on Negative ADC input bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* MUX selection on Negative ADC input bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* MUX selection on Negative ADC input bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* MUX selection on Negative ADC input bit 1 position. */
-#define ADC_CH_MUXNEG2_bm  (1<<2)  /* MUX selection on Negative ADC input bit 2 mask. */
-#define ADC_CH_MUXNEG2_bp  2  /* MUX selection on Negative ADC input bit 2 position. */
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-/* ADC_CH.SCAN  bit masks and bit positions */
-#define ADC_CH_OFFSET_gm  0xF0  /* Positive MUX setting offset group mask. */
-#define ADC_CH_OFFSET_gp  4  /* Positive MUX setting offset group position. */
-#define ADC_CH_OFFSET0_bm  (1<<4)  /* Positive MUX setting offset bit 0 mask. */
-#define ADC_CH_OFFSET0_bp  4  /* Positive MUX setting offset bit 0 position. */
-#define ADC_CH_OFFSET1_bm  (1<<5)  /* Positive MUX setting offset bit 1 mask. */
-#define ADC_CH_OFFSET1_bp  5  /* Positive MUX setting offset bit 1 position. */
-#define ADC_CH_OFFSET2_bm  (1<<6)  /* Positive MUX setting offset bit 2 mask. */
-#define ADC_CH_OFFSET2_bp  6  /* Positive MUX setting offset bit 2 position. */
-#define ADC_CH_OFFSET3_bm  (1<<7)  /* Positive MUX setting offset bit 3 mask. */
-#define ADC_CH_OFFSET3_bp  7  /* Positive MUX setting offset bit 3 position. */
-
-#define ADC_CH_SCANNUM_gm  0x0F  /* Number of Channels included in scan group mask. */
-#define ADC_CH_SCANNUM_gp  0  /* Number of Channels included in scan group position. */
-#define ADC_CH_SCANNUM0_bm  (1<<0)  /* Number of Channels included in scan bit 0 mask. */
-#define ADC_CH_SCANNUM0_bp  0  /* Number of Channels included in scan bit 0 position. */
-#define ADC_CH_SCANNUM1_bm  (1<<1)  /* Number of Channels included in scan bit 1 mask. */
-#define ADC_CH_SCANNUM1_bp  1  /* Number of Channels included in scan bit 1 position. */
-#define ADC_CH_SCANNUM2_bm  (1<<2)  /* Number of Channels included in scan bit 2 mask. */
-#define ADC_CH_SCANNUM2_bp  2  /* Number of Channels included in scan bit 2 position. */
-#define ADC_CH_SCANNUM3_bm  (1<<3)  /* Number of Channels included in scan bit 3 mask. */
-#define ADC_CH_SCANNUM3_bp  3  /* Number of Channels included in scan bit 3 position. */
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_IMPMODE_bm  0x80  /* Gain Stage Impedance Mode bit mask. */
-#define ADC_IMPMODE_bp  7  /* Gain Stage Impedance Mode bit position. */
-
-#define ADC_CURRLIMIT_gm  0x60  /* Current Limitation group mask. */
-#define ADC_CURRLIMIT_gp  5  /* Current Limitation group position. */
-#define ADC_CURRLIMIT0_bm  (1<<5)  /* Current Limitation bit 0 mask. */
-#define ADC_CURRLIMIT0_bp  5  /* Current Limitation bit 0 position. */
-#define ADC_CURRLIMIT1_bm  (1<<6)  /* Current Limitation bit 1 mask. */
-#define ADC_CURRLIMIT1_bp  6  /* Current Limitation bit 1 position. */
-
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
-#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSPLIT_bm  0x08  /* Separate Event Channel Input for Channel 1 bit mask. */
-#define DAC_EVSPLIT_bp  3  /* Separate Event Channel Input for Channel 1 bit position. */
-
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-/* DAC.CH0GAINCAL  bit masks and bit positions */
-#define DAC_CH0GAINCAL_gm  0x7F  /* Gain Calibration group mask. */
-#define DAC_CH0GAINCAL_gp  0  /* Gain Calibration group position. */
-#define DAC_CH0GAINCAL0_bm  (1<<0)  /* Gain Calibration bit 0 mask. */
-#define DAC_CH0GAINCAL0_bp  0  /* Gain Calibration bit 0 position. */
-#define DAC_CH0GAINCAL1_bm  (1<<1)  /* Gain Calibration bit 1 mask. */
-#define DAC_CH0GAINCAL1_bp  1  /* Gain Calibration bit 1 position. */
-#define DAC_CH0GAINCAL2_bm  (1<<2)  /* Gain Calibration bit 2 mask. */
-#define DAC_CH0GAINCAL2_bp  2  /* Gain Calibration bit 2 position. */
-#define DAC_CH0GAINCAL3_bm  (1<<3)  /* Gain Calibration bit 3 mask. */
-#define DAC_CH0GAINCAL3_bp  3  /* Gain Calibration bit 3 position. */
-#define DAC_CH0GAINCAL4_bm  (1<<4)  /* Gain Calibration bit 4 mask. */
-#define DAC_CH0GAINCAL4_bp  4  /* Gain Calibration bit 4 position. */
-#define DAC_CH0GAINCAL5_bm  (1<<5)  /* Gain Calibration bit 5 mask. */
-#define DAC_CH0GAINCAL5_bp  5  /* Gain Calibration bit 5 position. */
-#define DAC_CH0GAINCAL6_bm  (1<<6)  /* Gain Calibration bit 6 mask. */
-#define DAC_CH0GAINCAL6_bp  6  /* Gain Calibration bit 6 position. */
-
-/* DAC.CH0OFFSETCAL  bit masks and bit positions */
-#define DAC_CH0OFFSETCAL_gm  0x7F  /* Offset Calibration group mask. */
-#define DAC_CH0OFFSETCAL_gp  0  /* Offset Calibration group position. */
-#define DAC_CH0OFFSETCAL0_bm  (1<<0)  /* Offset Calibration bit 0 mask. */
-#define DAC_CH0OFFSETCAL0_bp  0  /* Offset Calibration bit 0 position. */
-#define DAC_CH0OFFSETCAL1_bm  (1<<1)  /* Offset Calibration bit 1 mask. */
-#define DAC_CH0OFFSETCAL1_bp  1  /* Offset Calibration bit 1 position. */
-#define DAC_CH0OFFSETCAL2_bm  (1<<2)  /* Offset Calibration bit 2 mask. */
-#define DAC_CH0OFFSETCAL2_bp  2  /* Offset Calibration bit 2 position. */
-#define DAC_CH0OFFSETCAL3_bm  (1<<3)  /* Offset Calibration bit 3 mask. */
-#define DAC_CH0OFFSETCAL3_bp  3  /* Offset Calibration bit 3 position. */
-#define DAC_CH0OFFSETCAL4_bm  (1<<4)  /* Offset Calibration bit 4 mask. */
-#define DAC_CH0OFFSETCAL4_bp  4  /* Offset Calibration bit 4 position. */
-#define DAC_CH0OFFSETCAL5_bm  (1<<5)  /* Offset Calibration bit 5 mask. */
-#define DAC_CH0OFFSETCAL5_bp  5  /* Offset Calibration bit 5 position. */
-#define DAC_CH0OFFSETCAL6_bm  (1<<6)  /* Offset Calibration bit 6 mask. */
-#define DAC_CH0OFFSETCAL6_bp  6  /* Offset Calibration bit 6 position. */
-
-/* DAC.CH1GAINCAL  bit masks and bit positions */
-#define DAC_CH1GAINCAL_gm  0x7F  /* Gain Calibration group mask. */
-#define DAC_CH1GAINCAL_gp  0  /* Gain Calibration group position. */
-#define DAC_CH1GAINCAL0_bm  (1<<0)  /* Gain Calibration bit 0 mask. */
-#define DAC_CH1GAINCAL0_bp  0  /* Gain Calibration bit 0 position. */
-#define DAC_CH1GAINCAL1_bm  (1<<1)  /* Gain Calibration bit 1 mask. */
-#define DAC_CH1GAINCAL1_bp  1  /* Gain Calibration bit 1 position. */
-#define DAC_CH1GAINCAL2_bm  (1<<2)  /* Gain Calibration bit 2 mask. */
-#define DAC_CH1GAINCAL2_bp  2  /* Gain Calibration bit 2 position. */
-#define DAC_CH1GAINCAL3_bm  (1<<3)  /* Gain Calibration bit 3 mask. */
-#define DAC_CH1GAINCAL3_bp  3  /* Gain Calibration bit 3 position. */
-#define DAC_CH1GAINCAL4_bm  (1<<4)  /* Gain Calibration bit 4 mask. */
-#define DAC_CH1GAINCAL4_bp  4  /* Gain Calibration bit 4 position. */
-#define DAC_CH1GAINCAL5_bm  (1<<5)  /* Gain Calibration bit 5 mask. */
-#define DAC_CH1GAINCAL5_bp  5  /* Gain Calibration bit 5 position. */
-#define DAC_CH1GAINCAL6_bm  (1<<6)  /* Gain Calibration bit 6 mask. */
-#define DAC_CH1GAINCAL6_bp  6  /* Gain Calibration bit 6 position. */
-
-/* DAC.CH1OFFSETCAL  bit masks and bit positions */
-#define DAC_CH1OFFSETCAL_gm  0x7F  /* Offset Calibration group mask. */
-#define DAC_CH1OFFSETCAL_gp  0  /* Offset Calibration group position. */
-#define DAC_CH1OFFSETCAL0_bm  (1<<0)  /* Offset Calibration bit 0 mask. */
-#define DAC_CH1OFFSETCAL0_bp  0  /* Offset Calibration bit 0 position. */
-#define DAC_CH1OFFSETCAL1_bm  (1<<1)  /* Offset Calibration bit 1 mask. */
-#define DAC_CH1OFFSETCAL1_bp  1  /* Offset Calibration bit 1 position. */
-#define DAC_CH1OFFSETCAL2_bm  (1<<2)  /* Offset Calibration bit 2 mask. */
-#define DAC_CH1OFFSETCAL2_bp  2  /* Offset Calibration bit 2 position. */
-#define DAC_CH1OFFSETCAL3_bm  (1<<3)  /* Offset Calibration bit 3 mask. */
-#define DAC_CH1OFFSETCAL3_bp  3  /* Offset Calibration bit 3 position. */
-#define DAC_CH1OFFSETCAL4_bm  (1<<4)  /* Offset Calibration bit 4 mask. */
-#define DAC_CH1OFFSETCAL4_bp  4  /* Offset Calibration bit 4 position. */
-#define DAC_CH1OFFSETCAL5_bm  (1<<5)  /* Offset Calibration bit 5 mask. */
-#define DAC_CH1OFFSETCAL5_bp  5  /* Offset Calibration bit 5 position. */
-#define DAC_CH1OFFSETCAL6_bm  (1<<6)  /* Offset Calibration bit 6 mask. */
-#define DAC_CH1OFFSETCAL6_bp  6  /* Offset Calibration bit 6 position. */
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE  Predefined. */
-/* AC_INTMODE  Predefined. */
-
-/* AC_INTLVL  Predefined. */
-/* AC_INTLVL  Predefined. */
-
-/* AC_HSMODE  Predefined. */
-/* AC_HSMODE  Predefined. */
-
-/* AC_HYSMODE  Predefined. */
-/* AC_HYSMODE  Predefined. */
-
-/* AC_ENABLE  Predefined. */
-/* AC_ENABLE  Predefined. */
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS  Predefined. */
-/* AC_MUXPOS  Predefined. */
-
-/* AC_MUXNEG  Predefined. */
-/* AC_MUXNEG  Predefined. */
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC1OUT_bm  0x02  /* Analog Comparator 1 Output Enable bit mask. */
-#define AC_AC1OUT_bp  1  /* Analog Comparator 1 Output Enable bit position. */
-
-#define AC_AC0OUT_bm  0x01  /* Analog Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Analog Comparator 0 Output Enable bit position. */
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Analog Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Analog Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Analog Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Analog Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Analog Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Analog Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Analog Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Analog Comparator 0 Interrupt Flag bit position. */
-
-/* RTC - Real-Time Counter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_W