; Toshiba MeP AVC Coprocessor description.  -*- Scheme -*-
; Copyright 2011 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc;
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
; MA 02110-1301, USA.

; This file was customized based upon the output of a2cgen 0.42

;------------------------------------------------------------------------------
; MeP-Integrator will redefine the isa pmacros below to allow the bit widths
; specified below for each ME_MODULE using this coprocessor.
; This coprocessor requires 16 and 32 bit insns.
;------------------------------------------------------------------------------
; begin-isas
(define-pmacro avc-core-isa () (ISA ext_core1))
(define-pmacro avc-16-isa   () (ISA ext_cop1_16))
(define-pmacro avc-32-isa   () (ISA ext_cop1_32))
(define-pmacro all-avc-isas () (ISA ext_core1,ext_cop1_16,ext_cop1_32))
; end-isas

(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming)
   (dni xname xcomment (.splice (.unsplice xattrs) avc-core-isa) xsyntax xformat xsemantics xtiming))
(define-pmacro (dn16i xname xcomment xattrs xsyntax xformat xsemantics xtiming)
   (dni xname xcomment (.splice (.unsplice xattrs) avc-16-isa) xsyntax xformat xsemantics xtiming))
(define-pmacro (dn32i xname xcomment xattrs xsyntax xformat xsemantics xtiming)
   (dni xname xcomment (.splice (.unsplice xattrs) avc-32-isa) xsyntax xformat xsemantics xtiming))

; register definitions
; ---------------------
; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
; GDB will use the hardware table generated from this declaration. The operands use h-cr
; from mep-core.cpu so that SID's semantic trace will be consistent between
; the core and the coprocessor but use parse/print handlers which reference the hardware table
; generated from this declarations
(define-hardware
  (name h-cr-avc)
  (comment "32-bit coprocessor registers for avc coprocessor")
  (attrs VIRTUAL all-avc-isas)
  (type register SI (32))
  (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
  (get (index) (trunc SI (c-call DI "h_cr64_get" index)))
  (indices keyword "$c" (.map -reg-pair (.iota 8)))
)
; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
; GDB will use the hardware table generated from this declaration. The operands use h-ccr
; from mep-core.cpu so that SID's semantic trace will be consistent between
; the core and the coprocessor but use parse/print handlers which reference the hardware table
; generated from this declarations
(define-hardware
  (name h-ccr-avc)
  (comment "Coprocessor control registers for avc coprocessor")
  (attrs VIRTUAL all-avc-isas)
  (type register SI (64))
  (set (index newval) (c-call VOID "h_ccr_set" index newval))
  (get (index) (c-call SI "h_ccr_get" index))
  (indices keyword ""
	(.splice
        ($accl1 5) ($acch1 4) ($accl0 3) ($acch0 2) ($CBCR 1) ($csar 0) 
        ($cbcr 1) 
		(.unsplice (.map -ccr-reg-pair (.iota 6)))
        )
  )
)
(dnop avccopCCR5 "Audio Copro Accumulator" (all-avc-isas) h-ccr 5)
(dnop avccopCCR4 "Audio Copro Accumulator" (all-avc-isas) h-ccr 4)
(dnop avccopCCR3 "Audio Copro Accumulator" (all-avc-isas) h-ccr 3)
(dnop avccopCCR2 "Audio Copro Accumulator" (all-avc-isas) h-ccr 2)
(dnop avccopCCR1 "Audio Copro Branch Condition Register" (all-avc-isas) h-ccr 1)
(dnop avccopCCR0 "Audio Copro Shift-Amount Register" (all-avc-isas) h-ccr 0)

; instruction field and operand definitions
(dnf f-avc-v3sub4u0 "sub opecode field" (avc-32-isa) 0 4)
(dnf f-avc-v1sub4u0 "sub opecode field" (avc-16-isa) 0 4)
(dnf f-avc-v3Rn "register field" (avc-32-isa) 4 4)
(dnop avcv3Rn "the operand definition" (avc-32-isa) h-gpr f-avc-v3Rn)
(dnf f-avc-v3CCRn "register field" (avc-32-isa) 4 4)
(define-full-operand avcv3CCRn "the operand definition" (avc-32-isa (CDATA REGNUM)) h-ccr DFLT f-avc-v3CCRn ( (parse "avc_ccr") (print "avc_ccr")) () ())
(df f-avc-v3Imm16s4x24e32-hi "split immediate field hi" (avc-32-isa) 4 8 INT #f #f)
(df f-avc-v3Imm16s4x24e32-lo "split immediate field lo" (avc-32-isa) 24 8 UINT #f #f)
(define-multi-ifield
 (name f-avc-v3Imm16s4x24e32)
 (comment "split immediate field")
 (attrs avc-32-isa)
 (mode INT)
 (subfields f-avc-v3Imm16s4x24e32-hi f-avc-v3Imm16s4x24e32-lo)
 (insert (sequence ()
    (set (ifield f-avc-v3Imm16s4x24e32-hi) (sra INT (ifield f-avc-v3Imm16s4x24e32) 8))
    (set (ifield f-avc-v3Imm16s4x24e32-lo) (and (ifield f-avc-v3Imm16s4x24e32) #xff))))
 (extract (set (ifield f-avc-v3Imm16s4x24e32)
    (or (sll (ifield f-avc-v3Imm16s4x24e32-hi) 8) (ifield f-avc-v3Imm16s4x24e32-lo))))
 )
(dnop avcv3Imm16s4x24e32 "the operand definition" (avc-32-isa) h-sint f-avc-v3Imm16s4x24e32)
(dnf f-avc-v3CRn "register field" (avc-32-isa) 4 4)
(define-full-operand avcv3CRn "the operand definition" (avc-32-isa) h-cr DFLT f-avc-v3CRn ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-v1CRq "register field" (avc-16-isa) 4 4)
(define-full-operand avcv1CRq "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRq ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-v1sub4u4 "sub opecode field" (avc-16-isa) 4 4)
(dnf f-avc-c3Rn "register field" (avc-core-isa) 4 4)
(dnop avcc3Rn "the operand definition" (avc-core-isa) h-gpr f-avc-c3Rn)
(dnf f-avc-c3CCRn "register field" (avc-core-isa) 4 4)
(define-full-operand avcc3CCRn "the operand definition" (avc-core-isa (CDATA REGNUM)) h-ccr DFLT f-avc-c3CCRn ( (parse "avc_ccr") (print "avc_ccr")) () ())
(df f-avc-c3Imm16s4x24e32-hi "split immediate field hi" (avc-core-isa) 4 8 INT #f #f)
(df f-avc-c3Imm16s4x24e32-lo "split immediate field lo" (avc-core-isa) 24 8 UINT #f #f)
(define-multi-ifield
 (name f-avc-c3Imm16s4x24e32)
 (comment "split immediate field")
 (attrs avc-core-isa)
 (mode INT)
 (subfields f-avc-c3Imm16s4x24e32-hi f-avc-c3Imm16s4x24e32-lo)
 (insert (sequence ()
    (set (ifield f-avc-c3Imm16s4x24e32-hi) (sra INT (ifield f-avc-c3Imm16s4x24e32) 8))
    (set (ifield f-avc-c3Imm16s4x24e32-lo) (and (ifield f-avc-c3Imm16s4x24e32) #xff))))
 (extract (set (ifield f-avc-c3Imm16s4x24e32)
    (or (sll (ifield f-avc-c3Imm16s4x24e32-hi) 8) (ifield f-avc-c3Imm16s4x24e32-lo))))
 )
(dnop avcc3Imm16s4x24e32 "the operand definition" (avc-core-isa) h-sint f-avc-c3Imm16s4x24e32)
(dnf f-avc-c3CRn "register field" (avc-core-isa) 4 4)
(define-full-operand avcc3CRn "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRn ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-c3sub4u4 "sub opecode field" (avc-core-isa) 4 4)
(dnf f-avc-v3Rm "register field" (avc-32-isa) 8 4)
(dnop avcv3Rm "the operand definition" (avc-32-isa) h-gpr f-avc-v3Rm)
(df f-avc-v1Imm5u8 "immediate field" (avc-16-isa) 8 5 UINT #f #f)
(dnop avcv1Imm5u8 "the operand definition" (avc-16-isa) h-uint f-avc-v1Imm5u8)
(df f-avc-v1Imm6s8 "immediate field" (avc-16-isa) 8 6 INT #f #f)
(dnop avcv1Imm6s8 "the operand definition" (avc-16-isa) h-sint f-avc-v1Imm6s8)
(df f-avc-v1Imm8s8 "immediate field" (avc-16-isa) 8 8 INT #f #f)
(dnop avcv1Imm8s8 "the operand definition" (avc-16-isa) h-sint f-avc-v1Imm8s8)
(dnf f-avc-v1CRp "register field" (avc-16-isa) 8 4)
(define-full-operand avcv1CRp "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRp ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-v1sub4u8 "sub opecode field" (avc-16-isa) 8 4)
(dnf f-avc-c3Rm "register field" (avc-core-isa) 8 4)
(dnop avcc3Rm "the operand definition" (avc-core-isa) h-gpr f-avc-c3Rm)
(dnf f-avc-c3sub4u8 "sub opecode field" (avc-core-isa) 8 4)
(dnf f-avc-v3sub4u12 "sub opecode field" (avc-32-isa) 12 4)
(dnf f-avc-v1CRo "register field" (avc-16-isa) 12 4)
(define-full-operand avcv1CRo "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRo ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-v1sub4u12 "sub opecode field" (avc-16-isa) 12 4)
(dnf f-avc-v1sub3u13 "sub opecode field" (avc-16-isa) 13 3)
(dnf f-avc-v1sub2u14 "sub opecode field" (avc-16-isa) 14 2)
(dnf f-avc-v3sub4u16 "sub opecode field" (avc-32-isa) 16 4)
(dnf f-avc-c3sub4u16 "sub opecode field" (avc-core-isa) 16 4)
(dnf f-avc-v3CRq "register field" (avc-32-isa) 20 4)
(define-full-operand avcv3CRq "the operand definition" (avc-32-isa) h-cr DFLT f-avc-v3CRq ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-v3sub4u20 "sub opecode field" (avc-32-isa) 20 4)
(dnf f-avc-c3CRq "register field" (avc-core-isa) 20 4)
(define-full-operand avcc3CRq "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRq ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-c3sub4u20 "sub opecode field" (avc-core-isa) 20 4)
(dnf f-avc-v3sub4u24 "sub opecode field" (avc-32-isa) 24 4)
(df f-avc-c3Imm5u24 "immediate field" (avc-core-isa) 24 5 UINT #f #f)
(dnop avcc3Imm5u24 "the operand definition" (avc-core-isa) h-uint f-avc-c3Imm5u24)
(df f-avc-c3Imm6s24 "immediate field" (avc-core-isa) 24 6 INT #f #f)
(dnop avcc3Imm6s24 "the operand definition" (avc-core-isa) h-sint f-avc-c3Imm6s24)
(dnf f-avc-c3CRp "register field" (avc-core-isa) 24 4)
(define-full-operand avcc3CRp "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRp ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-c3sub4u24 "sub opecode field" (avc-core-isa) 24 4)
(dnf f-avc-v3sub4u28 "sub opecode field" (avc-32-isa) 28 4)
(dnf f-avc-c3CRo "register field" (avc-core-isa) 28 4)
(define-full-operand avcc3CRo "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRo ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-c3sub4u28 "sub opecode field" (avc-core-isa) 28 4)
(dnf f-avc-c3sub3u29 "sub opecode field" (avc-core-isa) 29 3)
(dnf f-avc-c3sub2u30 "sub opecode field" (avc-core-isa) 30 2)

; instruction definitions
(dncpi cnop_avc_c3 "cnop" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnop"))
 "cnop"
(+ MAJ_15 (f-sub4 7) (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(c-call "check_option_cp" pc)
 ())
(dncpi cmov1_avc_c3 "cmov1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov1"))
 "cmov $avcc3CRn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3CRn avcc3Rm (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRn avcc3Rm)
)
 ())
(dncpi cmov2_avc_c3 "cmov2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov2"))
 "cmov $avcc3Rm,$avcc3CRn"
(+ MAJ_15 (f-sub4 7) avcc3Rm avcc3CRn (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcc3Rm avcc3CRn)
)
 ())
(dncpi cmovi_avc_c3 "cmovi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovi"))
 "cmovi $avcc3CRq,$avcc3Imm16s4x24e32"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm16s4x24e32 (f-avc-c3sub4u16 #xe))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (ext SI avcc3Imm16s4x24e32))
)
 ())
(dncpi cmovc1_avc_c3 "cmovc1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc1"))
 "cmovc $avcc3CCRn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3CCRn avcc3Rm (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CCRn avcc3Rm)
)
 ())
(dncpi cmovc2_avc_c3 "cmovc2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc2"))
 "cmovc $avcc3Rm,$avcc3CCRn"
(+ MAJ_15 (f-sub4 7) avcc3Rm avcc3CCRn (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcc3Rm avcc3CCRn)
)
 ())
(dncpi cmov_avc_c3 "cmov" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov"))
 "cmov $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq avcc3CRp)
)
 ())
(dncpi cadd3_avc_c3 "cadd3" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd3"))
 "cadd3 $avcc3CRo,$avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRo avcc3CRq avcc3CRp (f-avc-c3sub4u16 #x3) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRo (add avcc3CRq avcc3CRp))
)
 ())
(dncpi caddi_avc_c3 "caddi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddi"))
 "caddi $avcc3CRq,$avcc3Imm6s24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm6s24 (f-avc-c3sub2u30 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (add avcc3CRq (ext SI avcc3Imm6s24)))
)
 ())
(dncpi csub_avc_c3 "csub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub"))
 "csub $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (sub avcc3CRq avcc3CRp))
)
 ())
(dncpi cneg_avc_c3 "cneg" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cneg"))
 "cneg $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (neg avcc3CRp))
)
 ())
(dncpi cextb_avc_c3 "cextb" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextb"))
 "cextb $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (ext SI (and QI (srl avcc3CRq 0) #xff)))
)
 ())
(dncpi cexth_avc_c3 "cexth" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cexth"))
 "cexth $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x2) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (ext SI (and HI (srl avcc3CRq 0) #xffff)))
)
 ())
(dncpi cextub_avc_c3 "cextub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextub"))
 "cextub $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x8) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (zext SI (and QI (srl avcc3CRq 0) #xff)))
)
 ())
(dncpi cextuh_avc_c3 "cextuh" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextuh"))
 "cextuh $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #xa) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (zext SI (and HI (srl avcc3CRq 0) #xffff)))
)
 ())
(dncpi cscltz_avc_c3 "cscltz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cscltz"))
 "cscltz $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u24 #xa) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avcc3CRq) (ext SI 0)) (set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 1) 31) 31)))
(set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 0) 31) 31)))
)
)
 ())
(dncpi cldz_avc_c3 "cldz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cldz"))
 "cldz $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (and avcc3CRp #x80000000) (set avcc3CRq 0)
(if (and avcc3CRp #x40000000) (set avcc3CRq 1)
(if (and avcc3CRp #x20000000) (set avcc3CRq 2)
(if (and avcc3CRp #x10000000) (set avcc3CRq 3)
(if (and avcc3CRp #x8000000) (set avcc3CRq 4)
(if (and avcc3CRp #x4000000) (set avcc3CRq 5)
(if (and avcc3CRp #x2000000) (set avcc3CRq 6)
(if (and avcc3CRp #x1000000) (set avcc3CRq 7)
(if (and avcc3CRp #x800000) (set avcc3CRq 8)
(if (and avcc3CRp #x400000) (set avcc3CRq 9)
(if (and avcc3CRp #x200000) (set avcc3CRq 10)
(if (and avcc3CRp #x100000) (set avcc3CRq 11)
(if (and avcc3CRp #x80000) (set avcc3CRq 12)
(if (and avcc3CRp #x40000) (set avcc3CRq 13)
(if (and avcc3CRp #x20000) (set avcc3CRq 14)
(if (and avcc3CRp #x10000) (set avcc3CRq 15)
(if (and avcc3CRp #x8000) (set avcc3CRq 16)
(if (and avcc3CRp #x4000) (set avcc3CRq 17)
(if (and avcc3CRp #x2000) (set avcc3CRq 18)
(if (and avcc3CRp #x1000) (set avcc3CRq 19)
(if (and avcc3CRp #x800) (set avcc3CRq 20)
(if (and avcc3CRp #x400) (set avcc3CRq 21)
(if (and avcc3CRp #x200) (set avcc3CRq 22)
(if (and avcc3CRp #x100) (set avcc3CRq 23)
(if (and avcc3CRp #x80) (set avcc3CRq 24)
(if (and avcc3CRp #x40) (set avcc3CRq 25)
(if (and avcc3CRp #x20) (set avcc3CRq 26)
(if (and avcc3CRp #x10) (set avcc3CRq 27)
(if (and avcc3CRp #x8) (set avcc3CRq 28)
(if (and avcc3CRp #x4) (set avcc3CRq 29)
(if (and avcc3CRp #x2) (set avcc3CRq 30)
(if (and avcc3CRp #x1) (set avcc3CRq 31)
(set avcc3CRq 32)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
 ())
(dncpi cabs_avc_c3 "cabs" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cabs"))
 "cabs $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (abs (ext SI (subword SI (sub avcc3CRq avcc3CRp) 1))))
)
 ())
(dncpi cad1s_avc_c3 "cad1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cad1s"))
 "cad1s $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (ext SI (subword SI (add avcc3CRq avcc3CRp) 1)))
(set avcc3CRq (subword SI (sra tmp0 1) 1))
)
 ())
(dncpi csb1s_avc_c3 "csb1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csb1s"))
 "csb1s $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (ext SI (subword SI (sub avcc3CRq avcc3CRp) 1)))
(set avcc3CRq (subword SI (sra tmp0 1) 1))
)
 ())
(dncpi cmin_avc_c3 "cmin" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmin"))
 "cmin $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avcc3CRq) (ext SI avcc3CRp)) (set avcc3CRq avcc3CRq)
(set avcc3CRq avcc3CRp)
)
)
 ())
(dncpi cmax_avc_c3 "cmax" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmax"))
 "cmax $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (gt (ext SI avcc3CRq) (ext SI avcc3CRp)) (set avcc3CRq avcc3CRq)
(set avcc3CRq avcc3CRp)
)
)
 ())
(dncpi cminu_avc_c3 "cminu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cminu"))
 "cminu $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (ltu (zext SI avcc3CRq) (zext SI avcc3CRp)) (set avcc3CRq avcc3CRq)
(set avcc3CRq avcc3CRp)
)
)
 ())
(dncpi cmaxu_avc_c3 "cmaxu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmaxu"))
 "cmaxu $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xb) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (gtu (zext SI avcc3CRq) (zext SI avcc3CRp)) (set avcc3CRq avcc3CRq)
(set avcc3CRq avcc3CRp)
)
)
 ())
(dncpi cclipi_avc_c3 "cclipi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipi"))
 "cclipi $avcc3CRq,$avcc3Imm5u24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x4) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avcc3Imm5u24) (ext SI 0)) (set avcc3CRq 0)
(sequence() (set tmp0 (sll 1 (sub avcc3Imm5u24 1)))
(set tmp1 (sub (subword SI tmp0 1) 1))
(if (gt (ext SI avcc3CRq) (ext SI (subword SI tmp1 1))) (set avcc3CRq (subword SI tmp1 1))
(if (lt (ext SI avcc3CRq) (ext SI (neg (subword SI tmp0 1)))) (set avcc3CRq (neg (subword SI tmp0 1)))
(set avcc3CRq avcc3CRq)
)
)
)
)
)
 ())
(dncpi cclipiu_avc_c3 "cclipiu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipiu"))
 "cclipiu $avcc3CRq,$avcc3Imm5u24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x5) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avcc3Imm5u24) (ext SI 0)) (set avcc3CRq 0)
(sequence() (set tmp0 (sub (sll 1 avcc3Imm5u24) 1))
(if (gt (ext SI avcc3CRq) (ext SI (subword SI tmp0 1))) (set avcc3CRq (subword SI tmp0 1))
(if (lt (ext SI avcc3CRq) (ext SI 0)) (set avcc3CRq 0)
(set avcc3CRq avcc3CRq)
)
)
)
)
)
 ())
(dncpi cor_avc_c3 "cor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cor"))
 "cor $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (or avcc3CRq avcc3CRp))
)
 ())
(dncpi cand_avc_c3 "cand" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cand"))
 "cand $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (and avcc3CRq avcc3CRp))
)
 ())
(dncpi cxor_avc_c3 "cxor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cxor"))
 "cxor $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (xor avcc3CRq avcc3CRp))
)
 ())
(dncpi cnor_avc_c3 "cnor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnor"))
 "cnor $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (inv (or avcc3CRq avcc3CRp)))
)
 ())
(dncpi csra_avc_c3 "csra" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csra"))
 "csra $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (sra avcc3CRq (and QI (srl avcc3CRp 0) #x1f)))
)
 ())
(dncpi csrl_avc_c3 "csrl" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrl"))
 "csrl $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (srl avcc3CRq (and QI (srl avcc3CRp 0) #x1f)))
)
 ())
(dncpi csll_avc_c3 "csll" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csll"))
 "csll $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (sll avcc3CRq (and QI (srl avcc3CRp 0) #x1f)))
)
 ())
(dncpi csrai_avc_c3 "csrai" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrai"))
 "csrai $avcc3CRq,$avcc3Imm5u24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x2) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (sra avcc3CRq avcc3Imm5u24))
)
 ())
(dncpi csrli_avc_c3 "csrli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrli"))
 "csrli $avcc3CRq,$avcc3Imm5u24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x3) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (srl avcc3CRq avcc3Imm5u24))
)
 ())
(dncpi cslli_avc_c3 "cslli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslli"))
 "cslli $avcc3CRq,$avcc3Imm5u24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x6) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (sll avcc3CRq avcc3Imm5u24))
)
 ())
(dncpi cfsft_avc_c3 "cfsft" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsft"))
 "cfsft $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avcc3CRq)) 32) (zext DI avcc3CRp)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
 ())
(dncpi cfsfta0_avc_c3 "cfsfta0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta0"))
 "cfsfta0 $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
 ())
(dncpi cfsfta1_avc_c3 "cfsfta1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta1"))
 "cfsfta1 $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
 ())
(dncpi cmula0_avc_c3 "cmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula0"))
 "cmula0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat0)) (c-call "check_option_cp" pc)
(set concat0 (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))
(set avccopCCR2 (subword SI concat0 0))
(set avccopCCR3 (subword SI concat0 1))
)
 ())
(dncpi cmulua0_avc_c3 "cmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua0"))
 "cmulua0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat1)) (c-call "check_option_cp" pc)
(set concat1 (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))
(set avccopCCR2 (subword SI concat1 0))
(set avccopCCR3 (subword SI concat1 1))
)
 ())
(dncpi cnmula0_avc_c3 "cnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula0"))
 "cnmula0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat2)) (c-call "check_option_cp" pc)
(set concat2 (neg (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR2 (subword SI concat2 0))
(set avccopCCR3 (subword SI concat2 1))
)
 ())
(dncpi cmada0_avc_c3 "cmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada0"))
 "cmada0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat3)) (c-call "check_option_cp" pc)
(set concat3 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR2 (subword SI concat3 0))
(set avccopCCR3 (subword SI concat3 1))
)
 ())
(dncpi cmadua0_avc_c3 "cmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua0"))
 "cmadua0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat4)) (c-call "check_option_cp" pc)
(set concat4 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp))))
(set avccopCCR2 (subword SI concat4 0))
(set avccopCCR3 (subword SI concat4 1))
)
 ())
(dncpi cmsba0_avc_c3 "cmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba0"))
 "cmsba0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat5)) (c-call "check_option_cp" pc)
(set concat5 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR2 (subword SI concat5 0))
(set avccopCCR3 (subword SI concat5 1))
)
 ())
(dncpi cmsbua0_avc_c3 "cmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua0"))
 "cmsbua0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat6)) (c-call "check_option_cp" pc)
(set concat6 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp))))
(set avccopCCR2 (subword SI concat6 0))
(set avccopCCR3 (subword SI concat6 1))
)
 ())
(dncpi cmula1_avc_c3 "cmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula1"))
 "cmula1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat7)) (c-call "check_option_cp" pc)
(set concat7 (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))
(set avccopCCR4 (subword SI concat7 0))
(set avccopCCR5 (subword SI concat7 1))
)
 ())
(dncpi cmulua1_avc_c3 "cmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua1"))
 "cmulua1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat8)) (c-call "check_option_cp" pc)
(set concat8 (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))
(set avccopCCR4 (subword SI concat8 0))
(set avccopCCR5 (subword SI concat8 1))
)
 ())
(dncpi cnmula1_avc_c3 "cnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula1"))
 "cnmula1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat9)) (c-call "check_option_cp" pc)
(set concat9 (neg (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR4 (subword SI concat9 0))
(set avccopCCR5 (subword SI concat9 1))
)
 ())
(dncpi cmada1_avc_c3 "cmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada1"))
 "cmada1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat10)) (c-call "check_option_cp" pc)
(set concat10 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR4 (subword SI concat10 0))
(set avccopCCR5 (subword SI concat10 1))
)
 ())
(dncpi cmadua1_avc_c3 "cmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua1"))
 "cmadua1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat11)) (c-call "check_option_cp" pc)
(set concat11 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp))))
(set avccopCCR4 (subword SI concat11 0))
(set avccopCCR5 (subword SI concat11 1))
)
 ())
(dncpi cmsba1_avc_c3 "cmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba1"))
 "cmsba1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat12)) (c-call "check_option_cp" pc)
(set concat12 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR4 (subword SI concat12 0))
(set avccopCCR5 (subword SI concat12 1))
)
 ())
(dncpi cmsbua1_avc_c3 "cmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua1"))
 "cmsbua1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat13)) (c-call "check_option_cp" pc)
(set concat13 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp))))
(set avccopCCR4 (subword SI concat13 0))
(set avccopCCR5 (subword SI concat13 1))
)
 ())
(dncpi xmula0_avc_c3 "xmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula0"))
 "xmula0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat14)) (c-call "check_option_cp" pc)
(set concat14 (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))
(set avccopCCR2 (subword SI concat14 0))
(set avccopCCR3 (subword SI concat14 1))
)
 ())
(dncpi xmulua0_avc_c3 "xmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua0"))
 "xmulua0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat15)) (c-call "check_option_cp" pc)
(set concat15 (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))
(set avccopCCR2 (subword SI concat15 0))
(set avccopCCR3 (subword SI concat15 1))
)
 ())
(dncpi xnmula0_avc_c3 "xnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula0"))
 "xnmula0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat16)) (c-call "check_option_cp" pc)
(set concat16 (neg (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR2 (subword SI concat16 0))
(set avccopCCR3 (subword SI concat16 1))
)
 ())
(dncpi xmada0_avc_c3 "xmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada0"))
 "xmada0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat17)) (c-call "check_option_cp" pc)
(set concat17 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR2 (subword SI concat17 0))
(set avccopCCR3 (subword SI concat17 1))
)
 ())
(dncpi xmadua0_avc_c3 "xmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua0"))
 "xmadua0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat18)) (c-call "check_option_cp" pc)
(set concat18 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm))))
(set avccopCCR2 (subword SI concat18 0))
(set avccopCCR3 (subword SI concat18 1))
)
 ())
(dncpi xmsba0_avc_c3 "xmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba0"))
 "xmsba0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat19)) (c-call "check_option_cp" pc)
(set concat19 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR2 (subword SI concat19 0))
(set avccopCCR3 (subword SI concat19 1))
)
 ())
(dncpi xmsbua0_avc_c3 "xmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua0"))
 "xmsbua0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat20)) (c-call "check_option_cp" pc)
(set concat20 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm))))
(set avccopCCR2 (subword SI concat20 0))
(set avccopCCR3 (subword SI concat20 1))
)
 ())
(dncpi xmula1_avc_c3 "xmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula1"))
 "xmula1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat21)) (c-call "check_option_cp" pc)
(set concat21 (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))
(set avccopCCR4 (subword SI concat21 0))
(set avccopCCR5 (subword SI concat21 1))
)
 ())
(dncpi xmulua1_avc_c3 "xmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua1"))
 "xmulua1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat22)) (c-call "check_option_cp" pc)
(set concat22 (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))
(set avccopCCR4 (subword SI concat22 0))
(set avccopCCR5 (subword SI concat22 1))
)
 ())
(dncpi xnmula1_avc_c3 "xnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula1"))
 "xnmula1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat23)) (c-call "check_option_cp" pc)
(set concat23 (neg (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR4 (subword SI concat23 0))
(set avccopCCR5 (subword SI concat23 1))
)
 ())
(dncpi xmada1_avc_c3 "xmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada1"))
 "xmada1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat24)) (c-call "check_option_cp" pc)
(set concat24 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR4 (subword SI concat24 0))
(set avccopCCR5 (subword SI concat24 1))
)
 ())
(dncpi xmadua1_avc_c3 "xmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua1"))
 "xmadua1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat25)) (c-call "check_option_cp" pc)
(set concat25 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm))))
(set avccopCCR4 (subword SI concat25 0))
(set avccopCCR5 (subword SI concat25 1))
)
 ())
(dncpi xmsba1_avc_c3 "xmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba1"))
 "xmsba1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat26)) (c-call "check_option_cp" pc)
(set concat26 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR4 (subword SI concat26 0))
(set avccopCCR5 (subword SI concat26 1))
)
 ())
(dncpi xmsbua1_avc_c3 "xmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua1"))
 "xmsbua1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat27)) (c-call "check_option_cp" pc)
(set concat27 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm))))
(set avccopCCR4 (subword SI concat27 0))
(set avccopCCR5 (subword SI concat27 1))
)
 ())
(dn16i cnop_avc_v1 "cnop" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnop"))
 "cnop"
(+ (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u4 #x0) (f-avc-v1sub4u0 #x0))
(c-call "check_option_cp" pc)
 ())
(dnmi cpnop16_avc_v1 "cpnop16"
(avc-16-isa NO-DIS)
"cpnop16"
(emit cnop_avc_v1)
)
(dn16i cmov_avc_v1 "cmov" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmov"))
 "cmov $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x3) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq avcv1CRp)
)
 ())
(dn16i cmovi_avc_v1 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmovi"))
 "cmovi $avcv1CRq,$avcv1Imm8s8"
(+ avcv1CRq avcv1Imm8s8 (f-avc-v1sub4u0 #x2))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (ext SI avcv1Imm8s8))
)
 ())
(dn16i cadd3_avc_v1 "cadd3" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd3"))
 "cadd3 $avcv1CRo,$avcv1CRq,$avcv1CRp"
(+ avcv1CRo avcv1CRq avcv1CRp (f-avc-v1sub4u0 #x3))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRo (add avcv1CRq avcv1CRp))
)
 ())
(dn16i caddi_avc_v1 "caddi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddi"))
 "caddi $avcv1CRq,$avcv1Imm6s8"
(+ avcv1CRq avcv1Imm6s8 (f-avc-v1sub2u14 #x0) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (add avcv1CRq (ext SI avcv1Imm6s8)))
)
 ())
(dn16i csub_avc_v1 "csub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub"))
 "csub $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (sub avcv1CRq avcv1CRp))
)
 ())
(dn16i cneg_avc_v1 "cneg" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cneg"))
 "cneg $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (neg avcv1CRp))
)
 ())
(dn16i cextb_avc_v1 "cextb" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextb"))
 "cextb $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (ext SI (and QI (srl avcv1CRq 0) #xff)))
)
 ())
(dn16i cexth_avc_v1 "cexth" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cexth"))
 "cexth $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x2) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (ext SI (and HI (srl avcv1CRq 0) #xffff)))
)
 ())
(dn16i cextub_avc_v1 "cextub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextub"))
 "cextub $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x8) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (zext SI (and QI (srl avcv1CRq 0) #xff)))
)
 ())
(dn16i cextuh_avc_v1 "cextuh" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextuh"))
 "cextuh $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #xa) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (zext SI (and HI (srl avcv1CRq 0) #xffff)))
)
 ())
(dn16i cscltz_avc_v1 "cscltz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cscltz"))
 "cscltz $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u8 #xa) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avcv1CRq) (ext SI 0)) (set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 1) 31) 31)))
(set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 0) 31) 31)))
)
)
 ())
(dn16i cldz_avc_v1 "cldz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cldz"))
 "cldz $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (and avcv1CRp #x80000000) (set avcv1CRq 0)
(if (and avcv1CRp #x40000000) (set avcv1CRq 1)
(if (and avcv1CRp #x20000000) (set avcv1CRq 2)
(if (and avcv1CRp #x10000000) (set avcv1CRq 3)
(if (and avcv1CRp #x8000000) (set avcv1CRq 4)
(if (and avcv1CRp #x4000000) (set avcv1CRq 5)
(if (and avcv1CRp #x2000000) (set avcv1CRq 6)
(if (and avcv1CRp #x1000000) (set avcv1CRq 7)
(if (and avcv1CRp #x800000) (set avcv1CRq 8)
(if (and avcv1CRp #x400000) (set avcv1CRq 9)
(if (and avcv1CRp #x200000) (set avcv1CRq 10)
(if (and avcv1CRp #x100000) (set avcv1CRq 11)
(if (and avcv1CRp #x80000) (set avcv1CRq 12)
(if (and avcv1CRp #x40000) (set avcv1CRq 13)
(if (and avcv1CRp #x20000) (set avcv1CRq 14)
(if (and avcv1CRp #x10000) (set avcv1CRq 15)
(if (and avcv1CRp #x8000) (set avcv1CRq 16)
(if (and avcv1CRp #x4000) (set avcv1CRq 17)
(if (and avcv1CRp #x2000) (set avcv1CRq 18)
(if (and avcv1CRp #x1000) (set avcv1CRq 19)
(if (and avcv1CRp #x800) (set avcv1CRq 20)
(if (and avcv1CRp #x400) (set avcv1CRq 21)
(if (and avcv1CRp #x200) (set avcv1CRq 22)
(if (and avcv1CRp #x100) (set avcv1CRq 23)
(if (and avcv1CRp #x80) (set avcv1CRq 24)
(if (and avcv1CRp #x40) (set avcv1CRq 25)
(if (and avcv1CRp #x20) (set avcv1CRq 26)
(if (and avcv1CRp #x10) (set avcv1CRq 27)
(if (and avcv1CRp #x8) (set avcv1CRq 28)
(if (and avcv1CRp #x4) (set avcv1CRq 29)
(if (and avcv1CRp #x2) (set avcv1CRq 30)
(if (and avcv1CRp #x1) (set avcv1CRq 31)
(set avcv1CRq 32)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
 ())
(dn16i cabs_avc_v1 "cabs" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cabs"))
 "cabs $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x3) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (abs (ext SI (subword SI (sub avcv1CRq avcv1CRp) 1))))
)
 ())
(dn16i cad1s_avc_v1 "cad1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cad1s"))
 "cad1s $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x5))
(sequence((DI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (ext SI (subword SI (add avcv1CRq avcv1CRp) 1)))
(set avcv1CRq (subword SI (sra tmp0 1) 1))
)
 ())
(dn16i csb1s_avc_v1 "csb1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csb1s"))
 "csb1s $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x5))
(sequence((DI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (ext SI (subword SI (sub avcv1CRq avcv1CRp) 1)))
(set avcv1CRq (subword SI (sra tmp0 1) 1))
)
 ())
(dn16i cmin_avc_v1 "cmin" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmin"))
 "cmin $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x8) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avcv1CRq) (ext SI avcv1CRp)) (set avcv1CRq avcv1CRq)
(set avcv1CRq avcv1CRp)
)
)
 ())
(dn16i cmax_avc_v1 "cmax" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmax"))
 "cmax $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (gt (ext SI avcv1CRq) (ext SI avcv1CRp)) (set avcv1CRq avcv1CRq)
(set avcv1CRq avcv1CRp)
)
)
 ())
(dn16i cminu_avc_v1 "cminu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cminu"))
 "cminu $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (ltu (zext SI avcv1CRq) (zext SI avcv1CRp)) (set avcv1CRq avcv1CRq)
(set avcv1CRq avcv1CRp)
)
)
 ())
(dn16i cmaxu_avc_v1 "cmaxu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmaxu"))
 "cmaxu $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xb) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (gtu (zext SI avcv1CRq) (zext SI avcv1CRp)) (set avcv1CRq avcv1CRq)
(set avcv1CRq avcv1CRp)
)
)
 ())
(dn16i cclipi_avc_v1 "cclipi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipi"))
 "cclipi $avcv1CRq,$avcv1Imm5u8"
(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x4) (f-avc-v1sub4u0 #x5))
(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avcv1Imm5u8) (ext SI 0)) (set avcv1CRq 0)
(sequence() (set tmp0 (sll 1 (sub avcv1Imm5u8 1)))
(set tmp1 (sub (subword SI tmp0 1) 1))
(if (gt (ext SI avcv1CRq) (ext SI (subword SI tmp1 1))) (set avcv1CRq (subword SI tmp1 1))
(if (lt (ext SI avcv1CRq) (ext SI (neg (subword SI tmp0 1)))) (set avcv1CRq (neg (subword SI tmp0 1)))
(set avcv1CRq avcv1CRq)
)
)
)
)
)
 ())
(dn16i cclipiu_avc_v1 "cclipiu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipiu"))
 "cclipiu $avcv1CRq,$avcv1Imm5u8"
(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x5) (f-avc-v1sub4u0 #x5))
(sequence((DI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avcv1Imm5u8) (ext SI 0)) (set avcv1CRq 0)
(sequence() (set tmp0 (sub (sll 1 avcv1Imm5u8) 1))
(if (gt (ext SI avcv1CRq) (ext SI (subword SI tmp0 1))) (set avcv1CRq (subword SI tmp0 1))
(if (lt (ext SI avcv1CRq) (ext SI 0)) (set avcv1CRq 0)
(set avcv1CRq avcv1CRq)
)
)
)
)
)
 ())
(dn16i cor_avc_v1 "cor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cor"))
 "cor $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x4) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (or avcv1CRq avcv1CRp))
)
 ())
(dn16i cand_avc_v1 "cand" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cand"))
 "cand $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x5) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (and avcv1CRq avcv1CRp))
)
 ())
(dn16i cxor_avc_v1 "cxor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cxor"))
 "cxor $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x6) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (xor avcv1CRq avcv1CRp))
)
 ())
(dn16i cnor_avc_v1 "cnor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnor"))
 "cnor $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (inv (or avcv1CRq avcv1CRp)))
)
 ())
(dn16i csra_avc_v1 "csra" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csra"))
 "csra $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xc) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (sra avcv1CRq (and QI (srl avcv1CRp 0) #x1f)))
)
 ())
(dn16i csrl_avc_v1 "csrl" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrl"))
 "csrl $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xd) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (srl avcv1CRq (and QI (srl avcv1CRp 0) #x1f)))
)
 ())
(dn16i csll_avc_v1 "csll" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csll"))
 "csll $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xe) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (sll avcv1CRq (and QI (srl avcv1CRp 0) #x1f)))
)
 ())
(dn16i csrai_avc_v1 "csrai" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrai"))
 "csrai $avcv1CRq,$avcv1Imm5u8"
(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x2) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (sra avcv1CRq avcv1Imm5u8))
)
 ())
(dn16i csrli_avc_v1 "csrli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrli"))
 "csrli $avcv1CRq,$avcv1Imm5u8"
(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x3) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (srl avcv1CRq avcv1Imm5u8))
)
 ())
(dn16i cslli_avc_v1 "cslli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslli"))
 "cslli $avcv1CRq,$avcv1Imm5u8"
(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x6) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (sll avcv1CRq avcv1Imm5u8))
)
 ())
(dn16i cfsft_avc_v1 "cfsft" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsft"))
 "cfsft $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avcv1CRq)) 32) (zext DI avcv1CRp)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
 ())
(dn16i cfsfta0_avc_v1 "cfsfta0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta0"))
 "cfsfta0 $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
 ())
(dn16i cfsfta1_avc_v1 "cfsfta1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta1"))
 "cfsfta1 $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
 ())
(dn16i cmula0_avc_v1 "cmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula0"))
 "cmula0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u0 #x4))
(sequence((DI concat28)) (c-call "check_option_cp" pc)
(set concat28 (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))
(set avccopCCR2 (subword SI concat28 0))
(set avccopCCR3 (subword SI concat28 1))
)
 ())
(dn16i cmulua0_avc_v1 "cmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua0"))
 "cmulua0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x4))
(sequence((DI concat29)) (c-call "check_option_cp" pc)
(set concat29 (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))
(set avccopCCR2 (subword SI concat29 0))
(set avccopCCR3 (subword SI concat29 1))
)
 ())
(dn16i cnmula0_avc_v1 "cnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula0"))
 "cnmula0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x4))
(sequence((DI concat30)) (c-call "check_option_cp" pc)
(set concat30 (neg (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR2 (subword SI concat30 0))
(set avccopCCR3 (subword SI concat30 1))
)
 ())
(dn16i cmada0_avc_v1 "cmada0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada0"))
 "cmada0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x4) (f-avc-v1sub4u0 #x4))
(sequence((DI concat31)) (c-call "check_option_cp" pc)
(set concat31 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR2 (subword SI concat31 0))
(set avccopCCR3 (subword SI concat31 1))
)
 ())
(dn16i cmadua0_avc_v1 "cmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua0"))
 "cmadua0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x5) (f-avc-v1sub4u0 #x4))
(sequence((DI concat32)) (c-call "check_option_cp" pc)
(set concat32 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp))))
(set avccopCCR2 (subword SI concat32 0))
(set avccopCCR3 (subword SI concat32 1))
)
 ())
(dn16i cmsba0_avc_v1 "cmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba0"))
 "cmsba0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x6) (f-avc-v1sub4u0 #x4))
(sequence((DI concat33)) (c-call "check_option_cp" pc)
(set concat33 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR2 (subword SI concat33 0))
(set avccopCCR3 (subword SI concat33 1))
)
 ())
(dn16i cmsbua0_avc_v1 "cmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua0"))
 "cmsbua0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u0 #x4))
(sequence((DI concat34)) (c-call "check_option_cp" pc)
(set concat34 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp))))
(set avccopCCR2 (subword SI concat34 0))
(set avccopCCR3 (subword SI concat34 1))
)
 ())
(dn16i cmula1_avc_v1 "cmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula1"))
 "cmula1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x8) (f-avc-v1sub4u0 #x4))
(sequence((DI concat35)) (c-call "check_option_cp" pc)
(set concat35 (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))
(set avccopCCR4 (subword SI concat35 0))
(set avccopCCR5 (subword SI concat35 1))
)
 ())
(dn16i cmulua1_avc_v1 "cmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua1"))
 "cmulua1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u0 #x4))
(sequence((DI concat36)) (c-call "check_option_cp" pc)
(set concat36 (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))
(set avccopCCR4 (subword SI concat36 0))
(set avccopCCR5 (subword SI concat36 1))
)
 ())
(dn16i cnmula1_avc_v1 "cnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula1"))
 "cnmula1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u0 #x4))
(sequence((DI concat37)) (c-call "check_option_cp" pc)
(set concat37 (neg (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR4 (subword SI concat37 0))
(set avccopCCR5 (subword SI concat37 1))
)
 ())
(dn16i cmada1_avc_v1 "cmada1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada1"))
 "cmada1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xc) (f-avc-v1sub4u0 #x4))
(sequence((DI concat38)) (c-call "check_option_cp" pc)
(set concat38 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR4 (subword SI concat38 0))
(set avccopCCR5 (subword SI concat38 1))
)
 ())
(dn16i cmadua1_avc_v1 "cmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua1"))
 "cmadua1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xd) (f-avc-v1sub4u0 #x4))
(sequence((DI concat39)) (c-call "check_option_cp" pc)
(set concat39 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp))))
(set avccopCCR4 (subword SI concat39 0))
(set avccopCCR5 (subword SI concat39 1))
)
 ())
(dn16i cmsba1_avc_v1 "cmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba1"))
 "cmsba1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xe) (f-avc-v1sub4u0 #x4))
(sequence((DI concat40)) (c-call "check_option_cp" pc)
(set concat40 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR4 (subword SI concat40 0))
(set avccopCCR5 (subword SI concat40 1))
)
 ())
(dn16i cmsbua1_avc_v1 "cmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua1"))
 "cmsbua1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u0 #x4))
(sequence((DI concat41)) (c-call "check_option_cp" pc)
(set concat41 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp))))
(set avccopCCR4 (subword SI concat41 0))
(set avccopCCR5 (subword SI concat41 1))
)
 ())
(dn32i cmov1_avc_v3 "cmov1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov1"))
 "cmov $avcv3CRn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CRn avcv3Rm (f-avc-v3sub4u28 #x0) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcv3CRn avcv3Rm)
)
 ())
(dn32i cmov2_avc_v3 "cmov2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov2"))
 "cmov $avcv3Rm,$avcv3CRn"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rm avcv3CRn (f-avc-v3sub4u28 #x1) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcv3Rm avcv3CRn)
)
 ())
(dn32i cmovi_avc_v3 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovi"))
 "cmovi $avcv3CRq,$avcv3Imm16s4x24e32"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CRq avcv3Imm16s4x24e32 (f-avc-v3sub4u16 #xe))
(sequence() (c-call "check_option_cp" pc)
(set avcv3CRq (ext SI avcv3Imm16s4x24e32))
)
 ())
(dn32i cmovc1_avc_v3 "cmovc1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc1"))
 "cmovc $avcv3CCRn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CCRn avcv3Rm (f-avc-v3sub4u28 #x2) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcv3CCRn avcv3Rm)
)
 ())
(dn32i cmovc2_avc_v3 "cmovc2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc2"))
 "cmovc $avcv3Rm,$avcv3CCRn"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rm avcv3CCRn (f-avc-v3sub4u28 #x3) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcv3Rm avcv3CCRn)
)
 ())
(dn32i xmula0_avc_v3 "xmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula0"))
 "xmula0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x0) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat42)) (c-call "check_option_cp" pc)
(set concat42 (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))
(set avccopCCR2 (subword SI concat42 0))
(set avccopCCR3 (subword SI concat42 1))
)
 ())
(dn32i xmulua0_avc_v3 "xmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua0"))
 "xmulua0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x1) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat43)) (c-call "check_option_cp" pc)
(set concat43 (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))
(set avccopCCR2 (subword SI concat43 0))
(set avccopCCR3 (subword SI concat43 1))
)
 ())
(dn32i xnmula0_avc_v3 "xnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula0"))
 "xnmula0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x2) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat44)) (c-call "check_option_cp" pc)
(set concat44 (neg (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR2 (subword SI concat44 0))
(set avccopCCR3 (subword SI concat44 1))
)
 ())
(dn32i xmada0_avc_v3 "xmada0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada0"))
 "xmada0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x4) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat45)) (c-call "check_option_cp" pc)
(set concat45 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR2 (subword SI concat45 0))
(set avccopCCR3 (subword SI concat45 1))
)
 ())
(dn32i xmadua0_avc_v3 "xmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua0"))
 "xmadua0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x5) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat46)) (c-call "check_option_cp" pc)
(set concat46 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm))))
(set avccopCCR2 (subword SI concat46 0))
(set avccopCCR3 (subword SI concat46 1))
)
 ())
(dn32i xmsba0_avc_v3 "xmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba0"))
 "xmsba0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x6) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat47)) (c-call "check_option_cp" pc)
(set concat47 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR2 (subword SI concat47 0))
(set avccopCCR3 (subword SI concat47 1))
)
 ())
(dn32i xmsbua0_avc_v3 "xmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua0"))
 "xmsbua0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x7) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat48)) (c-call "check_option_cp" pc)
(set concat48 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm))))
(set avccopCCR2 (subword SI concat48 0))
(set avccopCCR3 (subword SI concat48 1))
)
 ())
(dn32i xmula1_avc_v3 "xmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula1"))
 "xmula1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x8) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat49)) (c-call "check_option_cp" pc)
(set concat49 (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))
(set avccopCCR4 (subword SI concat49 0))
(set avccopCCR5 (subword SI concat49 1))
)
 ())
(dn32i xmulua1_avc_v3 "xmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua1"))
 "xmulua1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x9) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat50)) (c-call "check_option_cp" pc)
(set concat50 (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))
(set avccopCCR4 (subword SI concat50 0))
(set avccopCCR5 (subword SI concat50 1))
)
 ())
(dn32i xnmula1_avc_v3 "xnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula1"))
 "xnmula1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xa) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat51)) (c-call "check_option_cp" pc)
(set concat51 (neg (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR4 (subword SI concat51 0))
(set avccopCCR5 (subword SI concat51 1))
)
 ())
(dn32i xmada1_avc_v3 "xmada1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada1"))
 "xmada1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xc) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat52)) (c-call "check_option_cp" pc)
(set concat52 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR4 (subword SI concat52 0))
(set avccopCCR5 (subword SI concat52 1))
)
 ())
(dn32i xmadua1_avc_v3 "xmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua1"))
 "xmadua1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xd) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat53)) (c-call "check_option_cp" pc)
(set concat53 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm))))
(set avccopCCR4 (subword SI concat53 0))
(set avccopCCR5 (subword SI concat53 1))
)
 ())
(dn32i xmsba1_avc_v3 "xmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba1"))
 "xmsba1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xe) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat54)) (c-call "check_option_cp" pc)
(set concat54 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR4 (subword SI concat54 0))
(set avccopCCR5 (subword SI concat54 1))
)
 ())
(dn32i xmsbua1_avc_v3 "xmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua1"))
 "xmsbua1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xf) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat55)) (c-call "check_option_cp" pc)
(set concat55 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm))))
(set avccopCCR4 (subword SI concat55 0))
(set avccopCCR5 (subword SI concat55 1))
)
 ())
