Aspeed SGPIO controller Device Tree Bindings
--------------------------------------------

This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
support the following options:
- Support interrupt option for each input port and various interrupt
  sensitivity option (level-high, level-low, edge-high, edge-low)
- Support reset tolerance option for each output port
- Directly connected to APB bus and its shift clock is from APB bus clock
  divided by a programmable value.
- Co-work with external signal-chained TTL components (74LV165/74LV595)

Required properties:

- compatible : Should be one of
  "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
- #gpio-cells : Should be 2, see gpio.txt
- reg : Address and length of the register set for the device
- gpio-controller : Marks the device node as a GPIO controller
- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
- interrupt-controller : Mark the GPIO controller as an interrupt-controller
- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
  2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
  output. Up to 80 pins, must be a multiple of 8.
- clocks : A phandle to the APB clock for SGPM clock division
- bus-frequency : SGPM CLK frequency

The sgpio and interrupt properties are further described in their respective
bindings documentation:

- Documentation/devicetree/bindings/gpio/gpio.txt
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt

  Example:
	sgpio: sgpio@1e780200 {
		#gpio-cells = <2>;
		compatible = "aspeed,ast2500-sgpio";
		gpio-controller;
		interrupts = <40>;
		reg = <0x1e780200 0x0100>;
		clocks = <&syscon ASPEED_CLK_APB>;
		interrupt-controller;
		ngpios = <8>;
		bus-frequency = <12000000>;
	};
