# TCL File Generated by Component Editor 16.0
# Fri Dec 01 14:41:03 EST 2017
# DO NOT MODIFY


# 
# pll_reset "PLL Reset Controller" v2.0
# Nuand, LLC 2017.12.01.14:41:03
# Monitors a PLL and resets it if lock is lost.
# 

# 
# request TCL package from ACDS 16.0
# 
package require -exact qsys 16.0


# 
# module pll_reset
# 
set_module_property DESCRIPTION "Monitors a PLL and resets it if lock is lost."
set_module_property NAME pll_reset
set_module_property VERSION 2.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP Nuand
set_module_property AUTHOR "Nuand, LLC"
set_module_property DISPLAY_NAME "PLL Reset Controller"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL pll_reset
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file pll_reset.vhd VHDL PATH ../vhdl/pll_reset.vhd TOP_LEVEL_FILE

add_fileset SIM_VHDL SIM_VHDL "" ""
set_fileset_property SIM_VHDL TOP_LEVEL pll_reset
set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file pll_reset.vhd VHDL PATH ../vhdl/pll_reset.vhd
add_fileset_file pll_reset_tb.vhd VHDL PATH ../vhdl/tb/pll_reset_tb.vhd


# 
# parameters
# 
add_parameter SYS_CLOCK_FREQ_HZ NATURAL 10000000 "System clock frequency in Hz"
set_parameter_property SYS_CLOCK_FREQ_HZ DEFAULT_VALUE 10000000
set_parameter_property SYS_CLOCK_FREQ_HZ DISPLAY_NAME SYS_CLOCK_FREQ_HZ
set_parameter_property SYS_CLOCK_FREQ_HZ TYPE NATURAL
set_parameter_property SYS_CLOCK_FREQ_HZ UNITS None
set_parameter_property SYS_CLOCK_FREQ_HZ ALLOWED_RANGES 0:2147483647
set_parameter_property SYS_CLOCK_FREQ_HZ DESCRIPTION "System clock frequency in Hz"
set_parameter_property SYS_CLOCK_FREQ_HZ HDL_PARAMETER true
add_parameter DEVICE_FAMILY STRING "Cyclone V" "Cyclone IV or Cyclone V"
set_parameter_property DEVICE_FAMILY DEFAULT_VALUE "Cyclone V"
set_parameter_property DEVICE_FAMILY DISPLAY_NAME DEVICE_FAMILY
set_parameter_property DEVICE_FAMILY WIDTH ""
set_parameter_property DEVICE_FAMILY TYPE STRING
set_parameter_property DEVICE_FAMILY UNITS None
set_parameter_property DEVICE_FAMILY DESCRIPTION "Cyclone IV or Cyclone V"
set_parameter_property DEVICE_FAMILY HDL_PARAMETER true


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock sys_clock clk Input 1


# 
# connection point pll_locked
# 
add_interface pll_locked conduit end
set_interface_property pll_locked associatedClock clock
set_interface_property pll_locked associatedReset ""
set_interface_property pll_locked ENABLED true
set_interface_property pll_locked EXPORT_OF ""
set_interface_property pll_locked PORT_NAME_MAP ""
set_interface_property pll_locked CMSIS_SVD_VARIABLES ""
set_interface_property pll_locked SVD_ADDRESS_GROUP ""

add_interface_port pll_locked pll_locked pll_locked Input 1


# 
# connection point pll_locked_out
# 
add_interface pll_locked_out conduit end
set_interface_property pll_locked_out associatedClock clock
set_interface_property pll_locked_out associatedReset ""
set_interface_property pll_locked_out ENABLED true
set_interface_property pll_locked_out EXPORT_OF ""
set_interface_property pll_locked_out PORT_NAME_MAP ""
set_interface_property pll_locked_out CMSIS_SVD_VARIABLES ""
set_interface_property pll_locked_out SVD_ADDRESS_GROUP ""

add_interface_port pll_locked_out pll_locked_out pll_locked_out Output 1


# 
# connection point pll_reset
# 
add_interface pll_reset conduit end
set_interface_property pll_reset associatedClock clock
set_interface_property pll_reset associatedReset ""
set_interface_property pll_reset ENABLED true
set_interface_property pll_reset EXPORT_OF ""
set_interface_property pll_reset PORT_NAME_MAP ""
set_interface_property pll_reset CMSIS_SVD_VARIABLES ""
set_interface_property pll_reset SVD_ADDRESS_GROUP ""

add_interface_port pll_reset pll_reset pll_reset Output 1

